Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspace/coverage/default/35.rstmgr_smoke.4234733254 Mar 28 01:11:19 PM PDT 24 Mar 28 01:11:22 PM PDT 24 226787436 ps
T541 /workspace/coverage/default/33.rstmgr_reset.3077082128 Mar 28 01:11:18 PM PDT 24 Mar 28 01:11:24 PM PDT 24 1247499706 ps
T542 /workspace/coverage/default/43.rstmgr_stress_all.4122764389 Mar 28 01:11:33 PM PDT 24 Mar 28 01:12:08 PM PDT 24 8112796786 ps
T543 /workspace/coverage/default/41.rstmgr_stress_all.2955201924 Mar 28 01:11:33 PM PDT 24 Mar 28 01:12:00 PM PDT 24 6750132933 ps
T544 /workspace/coverage/default/7.rstmgr_alert_test.1023773425 Mar 28 01:09:41 PM PDT 24 Mar 28 01:09:42 PM PDT 24 92411937 ps
T63 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3067352328 Mar 28 12:49:23 PM PDT 24 Mar 28 12:49:24 PM PDT 24 203332985 ps
T64 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3480554851 Mar 28 12:49:42 PM PDT 24 Mar 28 12:49:43 PM PDT 24 77413202 ps
T65 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1239124307 Mar 28 12:49:13 PM PDT 24 Mar 28 12:49:14 PM PDT 24 108412614 ps
T118 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.507759399 Mar 28 12:49:41 PM PDT 24 Mar 28 12:49:42 PM PDT 24 74280532 ps
T66 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2934646185 Mar 28 12:49:20 PM PDT 24 Mar 28 12:49:21 PM PDT 24 209608217 ps
T67 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1948321849 Mar 28 12:49:42 PM PDT 24 Mar 28 12:49:45 PM PDT 24 427695416 ps
T68 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4172811578 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:34 PM PDT 24 204159162 ps
T108 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2121793132 Mar 28 12:49:30 PM PDT 24 Mar 28 12:49:32 PM PDT 24 131453813 ps
T109 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4028313815 Mar 28 12:49:31 PM PDT 24 Mar 28 12:49:32 PM PDT 24 64407815 ps
T110 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.751540914 Mar 28 12:49:33 PM PDT 24 Mar 28 12:49:34 PM PDT 24 59239530 ps
T111 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3106406165 Mar 28 12:49:38 PM PDT 24 Mar 28 12:49:39 PM PDT 24 57817982 ps
T112 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.436077262 Mar 28 12:49:41 PM PDT 24 Mar 28 12:49:43 PM PDT 24 253443546 ps
T69 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1792454959 Mar 28 12:49:33 PM PDT 24 Mar 28 12:49:35 PM PDT 24 182943591 ps
T75 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.751569228 Mar 28 12:49:40 PM PDT 24 Mar 28 12:49:42 PM PDT 24 187983765 ps
T70 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2611220607 Mar 28 12:49:35 PM PDT 24 Mar 28 12:49:38 PM PDT 24 232493021 ps
T113 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.199547551 Mar 28 12:49:42 PM PDT 24 Mar 28 12:49:45 PM PDT 24 223818977 ps
T545 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3599896361 Mar 28 12:49:20 PM PDT 24 Mar 28 12:49:21 PM PDT 24 97202101 ps
T546 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1267569283 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:20 PM PDT 24 144904357 ps
T76 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4114798196 Mar 28 12:49:40 PM PDT 24 Mar 28 12:49:41 PM PDT 24 105026412 ps
T114 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2719070559 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:34 PM PDT 24 62194384 ps
T115 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.336792561 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:21 PM PDT 24 140441692 ps
T92 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4112832125 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:34 PM PDT 24 169067183 ps
T93 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3529670669 Mar 28 12:49:36 PM PDT 24 Mar 28 12:49:38 PM PDT 24 463377124 ps
T71 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.87822535 Mar 28 12:49:23 PM PDT 24 Mar 28 12:49:26 PM PDT 24 524194429 ps
T547 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2194326250 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:20 PM PDT 24 271917229 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1358608946 Mar 28 12:49:24 PM PDT 24 Mar 28 12:49:25 PM PDT 24 89950421 ps
T116 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4289636261 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:17 PM PDT 24 208908795 ps
T94 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4147219692 Mar 28 12:49:31 PM PDT 24 Mar 28 12:49:34 PM PDT 24 968376876 ps
T117 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2142717673 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:34 PM PDT 24 471026639 ps
T549 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3029928089 Mar 28 12:49:37 PM PDT 24 Mar 28 12:49:39 PM PDT 24 263739853 ps
T550 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.875490963 Mar 28 12:49:36 PM PDT 24 Mar 28 12:49:37 PM PDT 24 66817185 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.47958740 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:18 PM PDT 24 138286584 ps
T95 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.83780866 Mar 28 12:49:34 PM PDT 24 Mar 28 12:49:38 PM PDT 24 456293200 ps
T552 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.885122563 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:34 PM PDT 24 122027797 ps
T129 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3958044184 Mar 28 12:49:31 PM PDT 24 Mar 28 12:49:33 PM PDT 24 122205366 ps
T553 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.297997870 Mar 28 12:49:42 PM PDT 24 Mar 28 12:49:43 PM PDT 24 78776752 ps
T123 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3328922837 Mar 28 12:49:40 PM PDT 24 Mar 28 12:49:45 PM PDT 24 1708301541 ps
T124 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.161050338 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:22 PM PDT 24 882451366 ps
T119 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3418490077 Mar 28 12:49:45 PM PDT 24 Mar 28 12:49:47 PM PDT 24 148283204 ps
T120 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2940153137 Mar 28 12:49:31 PM PDT 24 Mar 28 12:49:34 PM PDT 24 195530802 ps
T554 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.58880824 Mar 28 12:49:41 PM PDT 24 Mar 28 12:49:43 PM PDT 24 93782463 ps
T555 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.119742588 Mar 28 12:49:34 PM PDT 24 Mar 28 12:49:35 PM PDT 24 212111718 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.241493686 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:21 PM PDT 24 150980459 ps
T557 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2066778234 Mar 28 12:49:20 PM PDT 24 Mar 28 12:49:21 PM PDT 24 61111980 ps
T558 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2863534015 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:20 PM PDT 24 125279256 ps
T559 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3974329180 Mar 28 12:49:33 PM PDT 24 Mar 28 12:49:34 PM PDT 24 75440853 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.592042358 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:20 PM PDT 24 226996229 ps
T561 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2458909383 Mar 28 12:49:41 PM PDT 24 Mar 28 12:49:42 PM PDT 24 152071715 ps
T562 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2177462477 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:18 PM PDT 24 155566129 ps
T125 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1827851852 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:35 PM PDT 24 876868259 ps
T563 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2302924122 Mar 28 12:49:33 PM PDT 24 Mar 28 12:49:35 PM PDT 24 145522335 ps
T564 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2850475153 Mar 28 12:49:31 PM PDT 24 Mar 28 12:49:34 PM PDT 24 331911699 ps
T565 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1562863382 Mar 28 12:49:31 PM PDT 24 Mar 28 12:49:32 PM PDT 24 107706919 ps
T566 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2284395344 Mar 28 12:49:34 PM PDT 24 Mar 28 12:49:35 PM PDT 24 75365103 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2384896328 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:35 PM PDT 24 275036887 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2448062711 Mar 28 12:49:22 PM PDT 24 Mar 28 12:49:23 PM PDT 24 97567943 ps
T569 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.480835122 Mar 28 12:49:37 PM PDT 24 Mar 28 12:49:38 PM PDT 24 128080196 ps
T127 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1850006408 Mar 28 12:49:45 PM PDT 24 Mar 28 12:49:49 PM PDT 24 959961126 ps
T570 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3623320788 Mar 28 12:49:35 PM PDT 24 Mar 28 12:49:39 PM PDT 24 209363165 ps
T571 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1658489083 Mar 28 12:49:40 PM PDT 24 Mar 28 12:49:41 PM PDT 24 133829536 ps
T572 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2728559323 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:28 PM PDT 24 2008089109 ps
T573 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.195086524 Mar 28 12:49:40 PM PDT 24 Mar 28 12:49:42 PM PDT 24 143325390 ps
T574 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3439480295 Mar 28 12:49:36 PM PDT 24 Mar 28 12:49:37 PM PDT 24 126660966 ps
T575 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3223230000 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:20 PM PDT 24 251208247 ps
T576 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.112833321 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:20 PM PDT 24 77783102 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2104159963 Mar 28 12:49:39 PM PDT 24 Mar 28 12:49:41 PM PDT 24 198540815 ps
T578 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1184799772 Mar 28 12:49:38 PM PDT 24 Mar 28 12:49:39 PM PDT 24 125953868 ps
T579 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.958061212 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:17 PM PDT 24 93868348 ps
T580 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3252658615 Mar 28 12:49:35 PM PDT 24 Mar 28 12:49:37 PM PDT 24 61582239 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3416438055 Mar 28 12:49:22 PM PDT 24 Mar 28 12:49:23 PM PDT 24 98321940 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2129998824 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:33 PM PDT 24 58914712 ps
T583 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2278877172 Mar 28 12:49:39 PM PDT 24 Mar 28 12:49:41 PM PDT 24 469570479 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.782159350 Mar 28 12:49:22 PM PDT 24 Mar 28 12:49:26 PM PDT 24 555502035 ps
T585 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3267681112 Mar 28 12:49:41 PM PDT 24 Mar 28 12:49:43 PM PDT 24 145949066 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.665114959 Mar 28 12:49:16 PM PDT 24 Mar 28 12:49:18 PM PDT 24 201457500 ps
T587 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2996044619 Mar 28 12:49:42 PM PDT 24 Mar 28 12:49:43 PM PDT 24 230571334 ps
T134 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3259332546 Mar 28 12:49:40 PM PDT 24 Mar 28 12:49:42 PM PDT 24 471743731 ps
T588 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1831697471 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:33 PM PDT 24 63689838 ps
T589 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1862231539 Mar 28 12:49:45 PM PDT 24 Mar 28 12:49:47 PM PDT 24 103369274 ps
T590 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.365962473 Mar 28 12:49:35 PM PDT 24 Mar 28 12:49:37 PM PDT 24 142904999 ps
T121 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3778552195 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:34 PM PDT 24 501787293 ps
T591 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1824033345 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:20 PM PDT 24 479907378 ps
T592 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3484383368 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:34 PM PDT 24 296953180 ps
T593 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1724333852 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:22 PM PDT 24 264654922 ps
T594 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1109881383 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:33 PM PDT 24 181865660 ps
T126 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1287820380 Mar 28 12:49:37 PM PDT 24 Mar 28 12:49:39 PM PDT 24 430960394 ps
T595 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1773212664 Mar 28 12:49:45 PM PDT 24 Mar 28 12:49:47 PM PDT 24 235022803 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2122997083 Mar 28 12:49:41 PM PDT 24 Mar 28 12:49:43 PM PDT 24 84908849 ps
T597 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1738669446 Mar 28 12:49:41 PM PDT 24 Mar 28 12:49:42 PM PDT 24 89732579 ps
T598 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3372555714 Mar 28 12:49:15 PM PDT 24 Mar 28 12:49:24 PM PDT 24 1553450196 ps
T599 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1000152119 Mar 28 12:49:38 PM PDT 24 Mar 28 12:49:39 PM PDT 24 64066188 ps
T128 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.65525812 Mar 28 12:49:40 PM PDT 24 Mar 28 12:49:42 PM PDT 24 425786087 ps
T122 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2202453863 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:21 PM PDT 24 943991495 ps
T600 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3977439281 Mar 28 12:49:32 PM PDT 24 Mar 28 12:49:34 PM PDT 24 236319039 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3337509806 Mar 28 12:49:18 PM PDT 24 Mar 28 12:49:20 PM PDT 24 346113982 ps
T602 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2535333791 Mar 28 12:49:29 PM PDT 24 Mar 28 12:49:31 PM PDT 24 164083490 ps
T603 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.946924083 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:18 PM PDT 24 189785163 ps
T604 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2971412429 Mar 28 12:49:13 PM PDT 24 Mar 28 12:49:14 PM PDT 24 56699739 ps
T605 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2117364020 Mar 28 12:49:36 PM PDT 24 Mar 28 12:49:38 PM PDT 24 104188323 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1475341286 Mar 28 12:49:17 PM PDT 24 Mar 28 12:49:21 PM PDT 24 881373359 ps
T607 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2710504838 Mar 28 12:49:34 PM PDT 24 Mar 28 12:49:36 PM PDT 24 206732552 ps
T608 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1228684521 Mar 28 12:49:23 PM PDT 24 Mar 28 12:49:25 PM PDT 24 161740466 ps
T135 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3986059800 Mar 28 12:49:31 PM PDT 24 Mar 28 12:49:34 PM PDT 24 941737709 ps
T609 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2156795587 Mar 28 12:49:35 PM PDT 24 Mar 28 12:49:37 PM PDT 24 141856400 ps
T610 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1281455815 Mar 28 12:49:37 PM PDT 24 Mar 28 12:49:39 PM PDT 24 198023963 ps
T611 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.611022438 Mar 28 12:49:33 PM PDT 24 Mar 28 12:49:35 PM PDT 24 131612172 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4205825437 Mar 28 12:49:34 PM PDT 24 Mar 28 12:49:36 PM PDT 24 200243073 ps
T613 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1424184985 Mar 28 12:49:33 PM PDT 24 Mar 28 12:49:36 PM PDT 24 442741690 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.598123587 Mar 28 12:49:30 PM PDT 24 Mar 28 12:49:32 PM PDT 24 147692883 ps
T615 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2390015992 Mar 28 12:49:41 PM PDT 24 Mar 28 12:49:43 PM PDT 24 471069647 ps
T616 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3928374773 Mar 28 12:49:39 PM PDT 24 Mar 28 12:49:41 PM PDT 24 483993060 ps
T617 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3518763085 Mar 28 12:49:33 PM PDT 24 Mar 28 12:49:35 PM PDT 24 426024496 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2504556320 Mar 28 12:49:19 PM PDT 24 Mar 28 12:49:21 PM PDT 24 418493013 ps
T619 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1916697907 Mar 28 12:49:41 PM PDT 24 Mar 28 12:49:42 PM PDT 24 140368132 ps
T620 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1178862366 Mar 28 12:49:40 PM PDT 24 Mar 28 12:49:41 PM PDT 24 92699320 ps

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1396287812
Short name T10
Test name
Test status
Simulation time 106694274 ps
CPU time 0.98 seconds
Started Mar 28 01:09:52 PM PDT 24
Finished Mar 28 01:09:53 PM PDT 24
Peak memory 200828 kb
Host smart-cca7a363-e0cd-4f81-8ddc-c4e479b0d4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396287812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1396287812
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1538875813
Short name T6
Test name
Test status
Simulation time 151953195 ps
CPU time 1.84 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 200848 kb
Host smart-2970faae-6219-4a71-aa2c-bd47030b9943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538875813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1538875813
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1464033391
Short name T33
Test name
Test status
Simulation time 6079672257 ps
CPU time 21.68 seconds
Started Mar 28 01:11:06 PM PDT 24
Finished Mar 28 01:11:28 PM PDT 24
Peak memory 209924 kb
Host smart-f07264da-0f6e-4e76-bada-ebd90191a0a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464033391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1464033391
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1948321849
Short name T67
Test name
Test status
Simulation time 427695416 ps
CPU time 3.08 seconds
Started Mar 28 12:49:42 PM PDT 24
Finished Mar 28 12:49:45 PM PDT 24
Peak memory 208808 kb
Host smart-27e0ab34-9009-4a5b-9385-3ed6917be719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948321849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1948321849
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.988893708
Short name T72
Test name
Test status
Simulation time 8328721946 ps
CPU time 13.02 seconds
Started Mar 28 01:09:18 PM PDT 24
Finished Mar 28 01:09:31 PM PDT 24
Peak memory 217688 kb
Host smart-e953f20c-6875-4d67-b2de-47446ed9fe9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988893708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.988893708
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3578034633
Short name T16
Test name
Test status
Simulation time 1233633620 ps
CPU time 5.81 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:51 PM PDT 24
Peak memory 222532 kb
Host smart-d58ce2dd-fde0-4322-a695-1047336789a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578034633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3578034633
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.161050338
Short name T124
Test name
Test status
Simulation time 882451366 ps
CPU time 3.27 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:22 PM PDT 24
Peak memory 200596 kb
Host smart-5e74804f-a4bc-4eb2-861c-70ef08965534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161050338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
161050338
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1555267863
Short name T58
Test name
Test status
Simulation time 13500437131 ps
CPU time 47.54 seconds
Started Mar 28 01:09:06 PM PDT 24
Finished Mar 28 01:09:54 PM PDT 24
Peak memory 201172 kb
Host smart-095ad849-37a0-4a52-b749-f873acd5c06c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555267863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1555267863
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.751540914
Short name T110
Test name
Test status
Simulation time 59239530 ps
CPU time 0.8 seconds
Started Mar 28 12:49:33 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200396 kb
Host smart-f49c7cd0-5eca-4227-9977-fbf41c9c74bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751540914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.751540914
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1351572129
Short name T9
Test name
Test status
Simulation time 89497551 ps
CPU time 0.82 seconds
Started Mar 28 01:09:54 PM PDT 24
Finished Mar 28 01:09:55 PM PDT 24
Peak memory 200584 kb
Host smart-684d6cae-f509-4cd4-9d0a-600e5986c41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351572129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1351572129
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.280832125
Short name T40
Test name
Test status
Simulation time 1228660762 ps
CPU time 5.82 seconds
Started Mar 28 01:11:17 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 222572 kb
Host smart-9cc4ead2-4c6c-49ab-b4cc-2a19138c8096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280832125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.280832125
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1827851852
Short name T125
Test name
Test status
Simulation time 876868259 ps
CPU time 2.84 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:35 PM PDT 24
Peak memory 200668 kb
Host smart-ed6adb38-6cde-4ba2-9b19-ddf007151a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827851852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1827851852
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.980192203
Short name T32
Test name
Test status
Simulation time 228410683 ps
CPU time 1.29 seconds
Started Mar 28 01:09:14 PM PDT 24
Finished Mar 28 01:09:15 PM PDT 24
Peak memory 200824 kb
Host smart-7703ceb0-1272-4b5f-aafd-e627dac36782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980192203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.980192203
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.653025671
Short name T34
Test name
Test status
Simulation time 1896665164 ps
CPU time 7.38 seconds
Started Mar 28 01:09:39 PM PDT 24
Finished Mar 28 01:09:46 PM PDT 24
Peak memory 218496 kb
Host smart-c0b03d4e-41e0-4b8f-94c4-3c6f4a4665bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653025671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.653025671
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3623320788
Short name T570
Test name
Test status
Simulation time 209363165 ps
CPU time 2.94 seconds
Started Mar 28 12:49:35 PM PDT 24
Finished Mar 28 12:49:39 PM PDT 24
Peak memory 208424 kb
Host smart-bc8b80ad-36a1-4e26-9ab1-4f6177f41184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623320788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3623320788
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_reset.774160591
Short name T99
Test name
Test status
Simulation time 1849175789 ps
CPU time 6.83 seconds
Started Mar 28 01:09:58 PM PDT 24
Finished Mar 28 01:10:05 PM PDT 24
Peak memory 200944 kb
Host smart-4919d844-054d-4ac2-8d1b-74e49bb80c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774160591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.774160591
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1671570145
Short name T29
Test name
Test status
Simulation time 191079656 ps
CPU time 0.85 seconds
Started Mar 28 01:09:51 PM PDT 24
Finished Mar 28 01:09:52 PM PDT 24
Peak memory 200464 kb
Host smart-f7c5caa2-9cf3-4a08-9ca1-f0731e38d48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671570145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1671570145
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4147219692
Short name T94
Test name
Test status
Simulation time 968376876 ps
CPU time 3.05 seconds
Started Mar 28 12:49:31 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200664 kb
Host smart-ba4fc36d-c76c-4d57-a646-31d330a691c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147219692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.4147219692
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.665114959
Short name T586
Test name
Test status
Simulation time 201457500 ps
CPU time 1.61 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 200556 kb
Host smart-8318dfe7-6c4e-4388-bca7-f0bf31abdb7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665114959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.665114959
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1724333852
Short name T593
Test name
Test status
Simulation time 264654922 ps
CPU time 3.12 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:22 PM PDT 24
Peak memory 200432 kb
Host smart-3c87e804-6e0f-4092-949a-862c8b4aae16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724333852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
724333852
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3599896361
Short name T545
Test name
Test status
Simulation time 97202101 ps
CPU time 0.89 seconds
Started Mar 28 12:49:20 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 200384 kb
Host smart-0e16b2eb-859b-43fd-a1b1-43e55d815bbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599896361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
599896361
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2934646185
Short name T66
Test name
Test status
Simulation time 209608217 ps
CPU time 1.45 seconds
Started Mar 28 12:49:20 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 208684 kb
Host smart-0cb2328a-17da-4e32-ae06-123151cad9ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934646185 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2934646185
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2066778234
Short name T557
Test name
Test status
Simulation time 61111980 ps
CPU time 0.85 seconds
Started Mar 28 12:49:20 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 200380 kb
Host smart-dd9623fd-afe1-46ca-a7de-02f0012eede0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066778234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2066778234
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4289636261
Short name T116
Test name
Test status
Simulation time 208908795 ps
CPU time 1.62 seconds
Started Mar 28 12:49:16 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 200620 kb
Host smart-9703bb22-0732-4483-8fd7-d53cba230039
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289636261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.4289636261
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.782159350
Short name T584
Test name
Test status
Simulation time 555502035 ps
CPU time 3.89 seconds
Started Mar 28 12:49:22 PM PDT 24
Finished Mar 28 12:49:26 PM PDT 24
Peak memory 208720 kb
Host smart-4bb68763-2b64-4a2a-a2eb-89faed63f4cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782159350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.782159350
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1824033345
Short name T591
Test name
Test status
Simulation time 479907378 ps
CPU time 1.91 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 200664 kb
Host smart-b019a858-9476-4f8f-b305-5e6a6f67670a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824033345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1824033345
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1228684521
Short name T608
Test name
Test status
Simulation time 161740466 ps
CPU time 2.07 seconds
Started Mar 28 12:49:23 PM PDT 24
Finished Mar 28 12:49:25 PM PDT 24
Peak memory 216980 kb
Host smart-d21867c8-f14a-419a-bf46-b95c4bc49cad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228684521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
228684521
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2728559323
Short name T572
Test name
Test status
Simulation time 2008089109 ps
CPU time 9.27 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:28 PM PDT 24
Peak memory 208660 kb
Host smart-a140570b-2747-4539-a1bf-73cc9a822b8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728559323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
728559323
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.47958740
Short name T551
Test name
Test status
Simulation time 138286584 ps
CPU time 1.05 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 200316 kb
Host smart-f45713da-380e-451e-a368-f9845c62cb00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47958740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.47958740
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2863534015
Short name T558
Test name
Test status
Simulation time 125279256 ps
CPU time 1.31 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 208700 kb
Host smart-9a16590e-923b-45af-a959-bd7a22f71213
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863534015 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2863534015
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.958061212
Short name T579
Test name
Test status
Simulation time 93868348 ps
CPU time 0.89 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:17 PM PDT 24
Peak memory 200396 kb
Host smart-d0adddcc-4e39-4180-95b9-2a053d0c3dee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958061212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.958061212
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.336792561
Short name T115
Test name
Test status
Simulation time 140441692 ps
CPU time 1.13 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 200364 kb
Host smart-37d08466-6e14-4f72-bf9d-d699c6eec9d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336792561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.336792561
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.241493686
Short name T556
Test name
Test status
Simulation time 150980459 ps
CPU time 2 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 208672 kb
Host smart-e659cf71-21db-4930-a91a-8bad4f3682a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241493686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.241493686
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2504556320
Short name T618
Test name
Test status
Simulation time 418493013 ps
CPU time 1.82 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 200636 kb
Host smart-fa18009b-dcc6-4d5e-ab4b-c40c4dad00e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504556320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2504556320
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.885122563
Short name T552
Test name
Test status
Simulation time 122027797 ps
CPU time 0.94 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200452 kb
Host smart-cd778eb0-b368-4a43-905d-5a46e95d2858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885122563 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.885122563
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1831697471
Short name T588
Test name
Test status
Simulation time 63689838 ps
CPU time 0.76 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:33 PM PDT 24
Peak memory 200380 kb
Host smart-9b780efa-7313-4541-a57c-abc23d9b0d31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831697471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1831697471
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3439480295
Short name T574
Test name
Test status
Simulation time 126660966 ps
CPU time 1.07 seconds
Started Mar 28 12:49:36 PM PDT 24
Finished Mar 28 12:49:37 PM PDT 24
Peak memory 200496 kb
Host smart-6a158522-8aa6-4b17-8fed-c8d580c27b17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439480295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3439480295
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3928374773
Short name T616
Test name
Test status
Simulation time 483993060 ps
CPU time 2.19 seconds
Started Mar 28 12:49:39 PM PDT 24
Finished Mar 28 12:49:41 PM PDT 24
Peak memory 200668 kb
Host smart-a421ad97-4e0e-4f53-b980-700a2b1f4ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928374773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3928374773
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2535333791
Short name T602
Test name
Test status
Simulation time 164083490 ps
CPU time 1.55 seconds
Started Mar 28 12:49:29 PM PDT 24
Finished Mar 28 12:49:31 PM PDT 24
Peak memory 208880 kb
Host smart-1f0aa562-40ee-436f-a5d5-403ca4db74ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535333791 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2535333791
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1562863382
Short name T565
Test name
Test status
Simulation time 107706919 ps
CPU time 1.19 seconds
Started Mar 28 12:49:31 PM PDT 24
Finished Mar 28 12:49:32 PM PDT 24
Peak memory 200656 kb
Host smart-485df9c9-08dc-4b7d-b134-a635e9284e5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562863382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1562863382
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2940153137
Short name T120
Test name
Test status
Simulation time 195530802 ps
CPU time 2.95 seconds
Started Mar 28 12:49:31 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 216868 kb
Host smart-e231f440-a4c1-43f6-9c2b-98a891d6ba92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940153137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2940153137
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2278877172
Short name T583
Test name
Test status
Simulation time 469570479 ps
CPU time 1.9 seconds
Started Mar 28 12:49:39 PM PDT 24
Finished Mar 28 12:49:41 PM PDT 24
Peak memory 200652 kb
Host smart-3a696c23-6bce-4f84-ba62-1e14e56a54a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278877172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2278877172
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1184799772
Short name T578
Test name
Test status
Simulation time 125953868 ps
CPU time 0.97 seconds
Started Mar 28 12:49:38 PM PDT 24
Finished Mar 28 12:49:39 PM PDT 24
Peak memory 200500 kb
Host smart-a7c84788-8a54-4c3f-934d-c5b9611c66fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184799772 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1184799772
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3106406165
Short name T111
Test name
Test status
Simulation time 57817982 ps
CPU time 0.76 seconds
Started Mar 28 12:49:38 PM PDT 24
Finished Mar 28 12:49:39 PM PDT 24
Peak memory 200284 kb
Host smart-fbb8fdde-df7e-4142-81c0-8686fe446aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106406165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3106406165
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3029928089
Short name T549
Test name
Test status
Simulation time 263739853 ps
CPU time 1.77 seconds
Started Mar 28 12:49:37 PM PDT 24
Finished Mar 28 12:49:39 PM PDT 24
Peak memory 200536 kb
Host smart-e329fb35-0456-4af9-8503-515a665fd171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029928089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3029928089
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2156795587
Short name T609
Test name
Test status
Simulation time 141856400 ps
CPU time 2.05 seconds
Started Mar 28 12:49:35 PM PDT 24
Finished Mar 28 12:49:37 PM PDT 24
Peak memory 208760 kb
Host smart-a8030a1e-9a20-486d-8517-0fd7f18dad67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156795587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2156795587
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.65525812
Short name T128
Test name
Test status
Simulation time 425786087 ps
CPU time 1.79 seconds
Started Mar 28 12:49:40 PM PDT 24
Finished Mar 28 12:49:42 PM PDT 24
Peak memory 200660 kb
Host smart-dc3ca942-c5b6-40b3-9261-b7da467e71d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65525812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.65525812
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.195086524
Short name T573
Test name
Test status
Simulation time 143325390 ps
CPU time 1.07 seconds
Started Mar 28 12:49:40 PM PDT 24
Finished Mar 28 12:49:42 PM PDT 24
Peak memory 208652 kb
Host smart-1aa8166f-4c55-4c9a-8acc-175a815a1ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195086524 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.195086524
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3252658615
Short name T580
Test name
Test status
Simulation time 61582239 ps
CPU time 0.8 seconds
Started Mar 28 12:49:35 PM PDT 24
Finished Mar 28 12:49:37 PM PDT 24
Peak memory 200320 kb
Host smart-8b837573-6abb-4092-ab9f-6e401cdfe672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252658615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3252658615
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3977439281
Short name T600
Test name
Test status
Simulation time 236319039 ps
CPU time 1.5 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200504 kb
Host smart-492fdd54-6b9c-4ea5-a5c8-4fd59ac47568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977439281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3977439281
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1424184985
Short name T613
Test name
Test status
Simulation time 442741690 ps
CPU time 2.92 seconds
Started Mar 28 12:49:33 PM PDT 24
Finished Mar 28 12:49:36 PM PDT 24
Peak memory 208724 kb
Host smart-186c86bc-2304-48fb-9c09-720426c63401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424184985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1424184985
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1287820380
Short name T126
Test name
Test status
Simulation time 430960394 ps
CPU time 1.93 seconds
Started Mar 28 12:49:37 PM PDT 24
Finished Mar 28 12:49:39 PM PDT 24
Peak memory 200596 kb
Host smart-b0d88b6a-19b9-460d-a8a8-3da8e5e805b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287820380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1287820380
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4112832125
Short name T92
Test name
Test status
Simulation time 169067183 ps
CPU time 1.55 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 208840 kb
Host smart-78ed7df5-24e5-4feb-b7d0-f2273dcbdd32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112832125 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4112832125
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.297997870
Short name T553
Test name
Test status
Simulation time 78776752 ps
CPU time 0.88 seconds
Started Mar 28 12:49:42 PM PDT 24
Finished Mar 28 12:49:43 PM PDT 24
Peak memory 200376 kb
Host smart-d93437db-706d-4e60-935d-9e0df91b846d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297997870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.297997870
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.58880824
Short name T554
Test name
Test status
Simulation time 93782463 ps
CPU time 1.19 seconds
Started Mar 28 12:49:41 PM PDT 24
Finished Mar 28 12:49:43 PM PDT 24
Peak memory 200568 kb
Host smart-c5746e91-8fa6-48ff-a050-cddc5cff8a08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58880824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sam
e_csr_outstanding.58880824
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4114798196
Short name T76
Test name
Test status
Simulation time 105026412 ps
CPU time 0.93 seconds
Started Mar 28 12:49:40 PM PDT 24
Finished Mar 28 12:49:41 PM PDT 24
Peak memory 200424 kb
Host smart-09e58437-d633-40e9-8ad5-0229687a3cf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114798196 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.4114798196
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.507759399
Short name T118
Test name
Test status
Simulation time 74280532 ps
CPU time 0.85 seconds
Started Mar 28 12:49:41 PM PDT 24
Finished Mar 28 12:49:42 PM PDT 24
Peak memory 200384 kb
Host smart-8d982040-72d5-4f15-b031-4d300a0f39ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507759399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.507759399
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2122997083
Short name T596
Test name
Test status
Simulation time 84908849 ps
CPU time 1 seconds
Started Mar 28 12:49:41 PM PDT 24
Finished Mar 28 12:49:43 PM PDT 24
Peak memory 200448 kb
Host smart-1b1250db-a2ae-41b6-af78-775df6bedb76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122997083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2122997083
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2611220607
Short name T70
Test name
Test status
Simulation time 232493021 ps
CPU time 1.82 seconds
Started Mar 28 12:49:35 PM PDT 24
Finished Mar 28 12:49:38 PM PDT 24
Peak memory 210572 kb
Host smart-beadbad1-4a17-457d-bc0a-be70b17d6c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611220607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2611220607
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2390015992
Short name T615
Test name
Test status
Simulation time 471069647 ps
CPU time 1.84 seconds
Started Mar 28 12:49:41 PM PDT 24
Finished Mar 28 12:49:43 PM PDT 24
Peak memory 200680 kb
Host smart-d5f0049c-a3a5-49db-af3e-5266c5f1f5cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390015992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2390015992
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2996044619
Short name T587
Test name
Test status
Simulation time 230571334 ps
CPU time 1.5 seconds
Started Mar 28 12:49:42 PM PDT 24
Finished Mar 28 12:49:43 PM PDT 24
Peak memory 211152 kb
Host smart-d9d91669-e8d0-4c78-b7b3-4dcaa4e30f9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996044619 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2996044619
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1738669446
Short name T597
Test name
Test status
Simulation time 89732579 ps
CPU time 0.92 seconds
Started Mar 28 12:49:41 PM PDT 24
Finished Mar 28 12:49:42 PM PDT 24
Peak memory 200384 kb
Host smart-15df834f-6a56-4ccf-ac29-20c7e7e4dc11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738669446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1738669446
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.199547551
Short name T113
Test name
Test status
Simulation time 223818977 ps
CPU time 1.62 seconds
Started Mar 28 12:49:42 PM PDT 24
Finished Mar 28 12:49:45 PM PDT 24
Peak memory 200632 kb
Host smart-12d79ea3-db30-4304-be23-ba58087a2af3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199547551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.199547551
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1862231539
Short name T589
Test name
Test status
Simulation time 103369274 ps
CPU time 1.43 seconds
Started Mar 28 12:49:45 PM PDT 24
Finished Mar 28 12:49:47 PM PDT 24
Peak memory 211444 kb
Host smart-dd2de54d-9631-4a5e-a749-4c6316060c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862231539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1862231539
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1850006408
Short name T127
Test name
Test status
Simulation time 959961126 ps
CPU time 3.13 seconds
Started Mar 28 12:49:45 PM PDT 24
Finished Mar 28 12:49:49 PM PDT 24
Peak memory 200752 kb
Host smart-fe1f1e8f-9416-411d-aee8-22756ff71cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850006408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1850006408
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2302924122
Short name T563
Test name
Test status
Simulation time 145522335 ps
CPU time 1.19 seconds
Started Mar 28 12:49:33 PM PDT 24
Finished Mar 28 12:49:35 PM PDT 24
Peak memory 210324 kb
Host smart-886cd452-12dd-4a57-a016-76bfc1d8f894
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302924122 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2302924122
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3480554851
Short name T64
Test name
Test status
Simulation time 77413202 ps
CPU time 0.78 seconds
Started Mar 28 12:49:42 PM PDT 24
Finished Mar 28 12:49:43 PM PDT 24
Peak memory 200316 kb
Host smart-1df7b805-d178-41da-9d4c-0361dbf7e092
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480554851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3480554851
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.611022438
Short name T611
Test name
Test status
Simulation time 131612172 ps
CPU time 1.3 seconds
Started Mar 28 12:49:33 PM PDT 24
Finished Mar 28 12:49:35 PM PDT 24
Peak memory 200584 kb
Host smart-8f59f26f-f4a1-49a2-9d91-53dc0c0861a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611022438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.611022438
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3267681112
Short name T585
Test name
Test status
Simulation time 145949066 ps
CPU time 2.1 seconds
Started Mar 28 12:49:41 PM PDT 24
Finished Mar 28 12:49:43 PM PDT 24
Peak memory 208792 kb
Host smart-6cee3c37-1e43-4cdf-92f5-de4e706e234e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267681112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3267681112
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3328922837
Short name T123
Test name
Test status
Simulation time 1708301541 ps
CPU time 4.55 seconds
Started Mar 28 12:49:40 PM PDT 24
Finished Mar 28 12:49:45 PM PDT 24
Peak memory 200680 kb
Host smart-e93c5dca-9d32-42f6-a90f-e9ef839e36d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328922837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3328922837
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3418490077
Short name T119
Test name
Test status
Simulation time 148283204 ps
CPU time 1.36 seconds
Started Mar 28 12:49:45 PM PDT 24
Finished Mar 28 12:49:47 PM PDT 24
Peak memory 208796 kb
Host smart-a7d71758-b0a5-46e1-86b3-677e09b44f8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418490077 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3418490077
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3974329180
Short name T559
Test name
Test status
Simulation time 75440853 ps
CPU time 0.85 seconds
Started Mar 28 12:49:33 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200396 kb
Host smart-8f9b5e05-3bf0-4075-bcc7-df734bf17af8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974329180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3974329180
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.119742588
Short name T555
Test name
Test status
Simulation time 212111718 ps
CPU time 1.49 seconds
Started Mar 28 12:49:34 PM PDT 24
Finished Mar 28 12:49:35 PM PDT 24
Peak memory 208852 kb
Host smart-fb93d8dc-a9fb-49c8-9d21-53bdc99429b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119742588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.119742588
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1792454959
Short name T69
Test name
Test status
Simulation time 182943591 ps
CPU time 1.67 seconds
Started Mar 28 12:49:33 PM PDT 24
Finished Mar 28 12:49:35 PM PDT 24
Peak memory 208736 kb
Host smart-006ef8e2-965f-435a-afe1-dd2be6a8eac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792454959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1792454959
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4205825437
Short name T612
Test name
Test status
Simulation time 200243073 ps
CPU time 1.32 seconds
Started Mar 28 12:49:34 PM PDT 24
Finished Mar 28 12:49:36 PM PDT 24
Peak memory 208716 kb
Host smart-c23c7c71-24bc-4e8c-82bb-91bafc4fabaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205825437 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4205825437
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2284395344
Short name T566
Test name
Test status
Simulation time 75365103 ps
CPU time 0.83 seconds
Started Mar 28 12:49:34 PM PDT 24
Finished Mar 28 12:49:35 PM PDT 24
Peak memory 200396 kb
Host smart-7046d4f2-faa2-4220-8afc-1d0fd7f560bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284395344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2284395344
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2710504838
Short name T607
Test name
Test status
Simulation time 206732552 ps
CPU time 1.42 seconds
Started Mar 28 12:49:34 PM PDT 24
Finished Mar 28 12:49:36 PM PDT 24
Peak memory 200696 kb
Host smart-f61fba53-9118-4458-8ca3-c137e456a373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710504838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2710504838
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.83780866
Short name T95
Test name
Test status
Simulation time 456293200 ps
CPU time 3.53 seconds
Started Mar 28 12:49:34 PM PDT 24
Finished Mar 28 12:49:38 PM PDT 24
Peak memory 208756 kb
Host smart-b9ebb9d7-4fa0-4bf8-b7f5-3106b975ed12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83780866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.83780866
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3518763085
Short name T617
Test name
Test status
Simulation time 426024496 ps
CPU time 1.77 seconds
Started Mar 28 12:49:33 PM PDT 24
Finished Mar 28 12:49:35 PM PDT 24
Peak memory 200608 kb
Host smart-adfc068e-0341-459b-83d0-79f9b566842d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518763085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3518763085
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.592042358
Short name T560
Test name
Test status
Simulation time 226996229 ps
CPU time 1.52 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 200408 kb
Host smart-8b068170-a417-4b63-86a3-c260edaa0066
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592042358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.592042358
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3372555714
Short name T598
Test name
Test status
Simulation time 1553450196 ps
CPU time 9.13 seconds
Started Mar 28 12:49:15 PM PDT 24
Finished Mar 28 12:49:24 PM PDT 24
Peak memory 200472 kb
Host smart-e204d8b7-2280-4950-8e8e-8d5bdf9be77a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372555714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
372555714
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2448062711
Short name T568
Test name
Test status
Simulation time 97567943 ps
CPU time 0.82 seconds
Started Mar 28 12:49:22 PM PDT 24
Finished Mar 28 12:49:23 PM PDT 24
Peak memory 200208 kb
Host smart-0169d9a8-05df-4323-a062-ae9be3fb858f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448062711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
448062711
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3416438055
Short name T581
Test name
Test status
Simulation time 98321940 ps
CPU time 0.93 seconds
Started Mar 28 12:49:22 PM PDT 24
Finished Mar 28 12:49:23 PM PDT 24
Peak memory 208532 kb
Host smart-5a10a507-0525-45fc-a3eb-13d121db666c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416438055 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3416438055
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1358608946
Short name T548
Test name
Test status
Simulation time 89950421 ps
CPU time 0.93 seconds
Started Mar 28 12:49:24 PM PDT 24
Finished Mar 28 12:49:25 PM PDT 24
Peak memory 200436 kb
Host smart-acb87fcc-875a-4674-9d1a-5905b05e90ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358608946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1358608946
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1239124307
Short name T65
Test name
Test status
Simulation time 108412614 ps
CPU time 1.24 seconds
Started Mar 28 12:49:13 PM PDT 24
Finished Mar 28 12:49:14 PM PDT 24
Peak memory 200628 kb
Host smart-83aade32-f443-49ce-b230-79397c2c3608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239124307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1239124307
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3337509806
Short name T601
Test name
Test status
Simulation time 346113982 ps
CPU time 2.73 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 216764 kb
Host smart-b1748440-f311-4309-8bb4-5664967294a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337509806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3337509806
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3067352328
Short name T63
Test name
Test status
Simulation time 203332985 ps
CPU time 1.63 seconds
Started Mar 28 12:49:23 PM PDT 24
Finished Mar 28 12:49:24 PM PDT 24
Peak memory 200548 kb
Host smart-b4be8bf6-2c2b-4ea7-bdde-6f51c2c080b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067352328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
067352328
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2194326250
Short name T547
Test name
Test status
Simulation time 271917229 ps
CPU time 3.31 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 200572 kb
Host smart-5cbea86c-17da-40c1-8cc8-e675e23c3fe0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194326250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
194326250
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2177462477
Short name T562
Test name
Test status
Simulation time 155566129 ps
CPU time 0.98 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 200352 kb
Host smart-550c8142-1130-4809-aa98-79ab94ae864f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177462477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
177462477
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.946924083
Short name T603
Test name
Test status
Simulation time 189785163 ps
CPU time 1.3 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:18 PM PDT 24
Peak memory 208612 kb
Host smart-13d250ba-5d3a-49b1-8945-78dd86502bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946924083 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.946924083
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2971412429
Short name T604
Test name
Test status
Simulation time 56699739 ps
CPU time 0.75 seconds
Started Mar 28 12:49:13 PM PDT 24
Finished Mar 28 12:49:14 PM PDT 24
Peak memory 200324 kb
Host smart-601b6813-7e69-405d-80d9-cf24da7b8059
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971412429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2971412429
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.112833321
Short name T576
Test name
Test status
Simulation time 77783102 ps
CPU time 0.98 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 200360 kb
Host smart-0fa9641b-8e72-4eb0-bc27-9ee3a94de23f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112833321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.112833321
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.87822535
Short name T71
Test name
Test status
Simulation time 524194429 ps
CPU time 3.59 seconds
Started Mar 28 12:49:23 PM PDT 24
Finished Mar 28 12:49:26 PM PDT 24
Peak memory 212380 kb
Host smart-6d3bfa53-ed7d-44b2-8360-1ee2be737db5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87822535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.87822535
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1475341286
Short name T606
Test name
Test status
Simulation time 881373359 ps
CPU time 3.72 seconds
Started Mar 28 12:49:17 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 200528 kb
Host smart-49762b56-c5ab-482b-9a6a-3c5921c76cb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475341286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1475341286
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.598123587
Short name T614
Test name
Test status
Simulation time 147692883 ps
CPU time 1.93 seconds
Started Mar 28 12:49:30 PM PDT 24
Finished Mar 28 12:49:32 PM PDT 24
Peak memory 200468 kb
Host smart-23db5736-647e-478a-ad4d-8d443231ccea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598123587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.598123587
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2384896328
Short name T567
Test name
Test status
Simulation time 275036887 ps
CPU time 3.39 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:35 PM PDT 24
Peak memory 200476 kb
Host smart-f50b6c50-d52e-4440-b563-79c7065be895
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384896328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
384896328
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1267569283
Short name T546
Test name
Test status
Simulation time 144904357 ps
CPU time 0.99 seconds
Started Mar 28 12:49:19 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 200292 kb
Host smart-fc984edd-e898-48b5-af20-188850cbe2c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267569283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
267569283
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.751569228
Short name T75
Test name
Test status
Simulation time 187983765 ps
CPU time 1.61 seconds
Started Mar 28 12:49:40 PM PDT 24
Finished Mar 28 12:49:42 PM PDT 24
Peak memory 208904 kb
Host smart-0a9df319-809d-444a-847f-68b350fdaccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751569228 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.751569228
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2129998824
Short name T582
Test name
Test status
Simulation time 58914712 ps
CPU time 0.8 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:33 PM PDT 24
Peak memory 200324 kb
Host smart-831caf4c-2107-4c07-990f-519863263c7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129998824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2129998824
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1658489083
Short name T571
Test name
Test status
Simulation time 133829536 ps
CPU time 1.22 seconds
Started Mar 28 12:49:40 PM PDT 24
Finished Mar 28 12:49:41 PM PDT 24
Peak memory 200428 kb
Host smart-54ad6892-52d2-4bb4-af5f-58fef5e77a2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658489083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1658489083
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3223230000
Short name T575
Test name
Test status
Simulation time 251208247 ps
CPU time 1.99 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:20 PM PDT 24
Peak memory 200560 kb
Host smart-4006b3ad-525b-456a-9b78-efcdefe6cc33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223230000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3223230000
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2202453863
Short name T122
Test name
Test status
Simulation time 943991495 ps
CPU time 3.45 seconds
Started Mar 28 12:49:18 PM PDT 24
Finished Mar 28 12:49:21 PM PDT 24
Peak memory 200660 kb
Host smart-a5bb818e-b1dd-475d-bd15-52c3a090bb96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202453863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2202453863
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1109881383
Short name T594
Test name
Test status
Simulation time 181865660 ps
CPU time 1.17 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:33 PM PDT 24
Peak memory 208628 kb
Host smart-dfdfb0f0-8fe8-4a51-bee6-cfd6be3c8650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109881383 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1109881383
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1000152119
Short name T599
Test name
Test status
Simulation time 64066188 ps
CPU time 0.81 seconds
Started Mar 28 12:49:38 PM PDT 24
Finished Mar 28 12:49:39 PM PDT 24
Peak memory 200356 kb
Host smart-ade5d905-5030-4d01-b5b3-7486f4ba17ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000152119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1000152119
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2121793132
Short name T108
Test name
Test status
Simulation time 131453813 ps
CPU time 1.14 seconds
Started Mar 28 12:49:30 PM PDT 24
Finished Mar 28 12:49:32 PM PDT 24
Peak memory 200364 kb
Host smart-bbb19940-4438-4846-bbbc-1606fea84cd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121793132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2121793132
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1281455815
Short name T610
Test name
Test status
Simulation time 198023963 ps
CPU time 1.71 seconds
Started Mar 28 12:49:37 PM PDT 24
Finished Mar 28 12:49:39 PM PDT 24
Peak memory 208836 kb
Host smart-280f88cd-a3fa-4fcc-8113-7914b0f49c29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281455815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1281455815
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3778552195
Short name T121
Test name
Test status
Simulation time 501787293 ps
CPU time 2.01 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200660 kb
Host smart-49a461d7-41e0-42d3-868b-3012789e47da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778552195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3778552195
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2104159963
Short name T577
Test name
Test status
Simulation time 198540815 ps
CPU time 1.42 seconds
Started Mar 28 12:49:39 PM PDT 24
Finished Mar 28 12:49:41 PM PDT 24
Peak memory 208712 kb
Host smart-5bc729ab-3da0-4f66-ae6c-e3f49ccc411e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104159963 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2104159963
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2719070559
Short name T114
Test name
Test status
Simulation time 62194384 ps
CPU time 0.78 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200392 kb
Host smart-4d5bb502-c2ed-4954-91ea-4cf9d4b586b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719070559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2719070559
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1773212664
Short name T595
Test name
Test status
Simulation time 235022803 ps
CPU time 1.65 seconds
Started Mar 28 12:49:45 PM PDT 24
Finished Mar 28 12:49:47 PM PDT 24
Peak memory 200692 kb
Host smart-87428bd2-cf36-439e-9777-eadcf17a213e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773212664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1773212664
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3958044184
Short name T129
Test name
Test status
Simulation time 122205366 ps
CPU time 1.82 seconds
Started Mar 28 12:49:31 PM PDT 24
Finished Mar 28 12:49:33 PM PDT 24
Peak memory 208792 kb
Host smart-7fe34df5-28f7-4a76-893b-c211d3f0cd94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958044184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3958044184
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3259332546
Short name T134
Test name
Test status
Simulation time 471743731 ps
CPU time 2.08 seconds
Started Mar 28 12:49:40 PM PDT 24
Finished Mar 28 12:49:42 PM PDT 24
Peak memory 200556 kb
Host smart-70f60914-1d3a-4b5f-8308-79393ee8c243
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259332546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3259332546
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.480835122
Short name T569
Test name
Test status
Simulation time 128080196 ps
CPU time 1.09 seconds
Started Mar 28 12:49:37 PM PDT 24
Finished Mar 28 12:49:38 PM PDT 24
Peak memory 209212 kb
Host smart-b4047323-9c2e-481e-be8f-6ebb5f698074
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480835122 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.480835122
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4028313815
Short name T109
Test name
Test status
Simulation time 64407815 ps
CPU time 0.76 seconds
Started Mar 28 12:49:31 PM PDT 24
Finished Mar 28 12:49:32 PM PDT 24
Peak memory 200312 kb
Host smart-47348274-c050-4aec-b5fb-1f445060d665
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028313815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4028313815
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1916697907
Short name T619
Test name
Test status
Simulation time 140368132 ps
CPU time 1.09 seconds
Started Mar 28 12:49:41 PM PDT 24
Finished Mar 28 12:49:42 PM PDT 24
Peak memory 200384 kb
Host smart-4819d169-ddf5-42bb-aff0-ef7b3828009f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916697907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1916697907
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2850475153
Short name T564
Test name
Test status
Simulation time 331911699 ps
CPU time 2.64 seconds
Started Mar 28 12:49:31 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 208760 kb
Host smart-acb9953a-0fda-41aa-8690-b59e10e5e455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850475153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2850475153
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3529670669
Short name T93
Test name
Test status
Simulation time 463377124 ps
CPU time 2.08 seconds
Started Mar 28 12:49:36 PM PDT 24
Finished Mar 28 12:49:38 PM PDT 24
Peak memory 200644 kb
Host smart-b7d25974-7962-49dd-b0bb-f3c80bcad35b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529670669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3529670669
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2117364020
Short name T605
Test name
Test status
Simulation time 104188323 ps
CPU time 1 seconds
Started Mar 28 12:49:36 PM PDT 24
Finished Mar 28 12:49:38 PM PDT 24
Peak memory 200508 kb
Host smart-4fec85b8-3d1d-451e-9c1c-407f832bdd30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117364020 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2117364020
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1178862366
Short name T620
Test name
Test status
Simulation time 92699320 ps
CPU time 0.84 seconds
Started Mar 28 12:49:40 PM PDT 24
Finished Mar 28 12:49:41 PM PDT 24
Peak memory 200408 kb
Host smart-138ace13-897f-429f-ac4a-5bc991b827cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178862366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1178862366
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.436077262
Short name T112
Test name
Test status
Simulation time 253443546 ps
CPU time 1.65 seconds
Started Mar 28 12:49:41 PM PDT 24
Finished Mar 28 12:49:43 PM PDT 24
Peak memory 200660 kb
Host smart-c8682117-f14e-4444-800b-76d971b44ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436077262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.436077262
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3484383368
Short name T592
Test name
Test status
Simulation time 296953180 ps
CPU time 2.02 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 208808 kb
Host smart-87f7b9a5-72f4-4ddd-bc60-29bd6ccca6ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484383368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3484383368
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3986059800
Short name T135
Test name
Test status
Simulation time 941737709 ps
CPU time 3.03 seconds
Started Mar 28 12:49:31 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200628 kb
Host smart-af945ecc-b21c-4fed-8c24-77b19bb44fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986059800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3986059800
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.365962473
Short name T590
Test name
Test status
Simulation time 142904999 ps
CPU time 1.11 seconds
Started Mar 28 12:49:35 PM PDT 24
Finished Mar 28 12:49:37 PM PDT 24
Peak memory 200508 kb
Host smart-76be443a-a2d7-474f-aff5-58bfdba67b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365962473 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.365962473
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.875490963
Short name T550
Test name
Test status
Simulation time 66817185 ps
CPU time 0.82 seconds
Started Mar 28 12:49:36 PM PDT 24
Finished Mar 28 12:49:37 PM PDT 24
Peak memory 200284 kb
Host smart-e4fa9b90-b61d-44f0-a432-d079a66e0a85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875490963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.875490963
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2458909383
Short name T561
Test name
Test status
Simulation time 152071715 ps
CPU time 1.2 seconds
Started Mar 28 12:49:41 PM PDT 24
Finished Mar 28 12:49:42 PM PDT 24
Peak memory 200472 kb
Host smart-3f196aa0-c23c-4b3a-8af7-a961960e1466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458909383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2458909383
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4172811578
Short name T68
Test name
Test status
Simulation time 204159162 ps
CPU time 1.74 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200608 kb
Host smart-b125d336-ce9c-48ed-afe6-37f73e87c76e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172811578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4172811578
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2142717673
Short name T117
Test name
Test status
Simulation time 471026639 ps
CPU time 1.91 seconds
Started Mar 28 12:49:32 PM PDT 24
Finished Mar 28 12:49:34 PM PDT 24
Peak memory 200624 kb
Host smart-83fcf0a4-8061-47a4-a594-92ebe289cbdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142717673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2142717673
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.535295726
Short name T537
Test name
Test status
Simulation time 83234501 ps
CPU time 0.78 seconds
Started Mar 28 01:08:57 PM PDT 24
Finished Mar 28 01:08:58 PM PDT 24
Peak memory 200728 kb
Host smart-bc11effc-50e3-4854-882e-bc1290a73254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535295726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.535295726
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3064363463
Short name T301
Test name
Test status
Simulation time 1887832449 ps
CPU time 6.92 seconds
Started Mar 28 01:08:54 PM PDT 24
Finished Mar 28 01:09:01 PM PDT 24
Peak memory 217544 kb
Host smart-00d6c94d-8c27-4a89-8403-a6f24eb57b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064363463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3064363463
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.543220446
Short name T495
Test name
Test status
Simulation time 244774279 ps
CPU time 1.11 seconds
Started Mar 28 01:08:55 PM PDT 24
Finished Mar 28 01:08:56 PM PDT 24
Peak memory 218064 kb
Host smart-22aef5ae-9070-4118-8776-496646fef9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543220446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.543220446
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3461643749
Short name T319
Test name
Test status
Simulation time 215444834 ps
CPU time 0.9 seconds
Started Mar 28 01:08:42 PM PDT 24
Finished Mar 28 01:08:43 PM PDT 24
Peak memory 200608 kb
Host smart-8309d70a-823f-4908-96a7-513df4047dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461643749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3461643749
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3495317430
Short name T97
Test name
Test status
Simulation time 1100499844 ps
CPU time 4.74 seconds
Started Mar 28 01:08:43 PM PDT 24
Finished Mar 28 01:08:48 PM PDT 24
Peak memory 200976 kb
Host smart-20117f1a-4a21-437d-a975-b83b33bf07dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495317430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3495317430
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3478613037
Short name T73
Test name
Test status
Simulation time 8276936485 ps
CPU time 16.13 seconds
Started Mar 28 01:08:56 PM PDT 24
Finished Mar 28 01:09:12 PM PDT 24
Peak memory 217724 kb
Host smart-f4e2bb5c-bacf-4099-b979-992f33244158
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478613037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3478613037
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2058973926
Short name T180
Test name
Test status
Simulation time 184791734 ps
CPU time 1.12 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:08:42 PM PDT 24
Peak memory 200800 kb
Host smart-c6bf9669-0386-40f6-826e-dd23357edb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058973926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2058973926
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2789283541
Short name T528
Test name
Test status
Simulation time 118865565 ps
CPU time 1.21 seconds
Started Mar 28 01:08:41 PM PDT 24
Finished Mar 28 01:08:42 PM PDT 24
Peak memory 200884 kb
Host smart-639cbcd6-2975-4d7f-a4de-eb67c26d7510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789283541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2789283541
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1895559130
Short name T104
Test name
Test status
Simulation time 3920985445 ps
CPU time 14.15 seconds
Started Mar 28 01:09:06 PM PDT 24
Finished Mar 28 01:09:21 PM PDT 24
Peak memory 201140 kb
Host smart-89889136-e6ab-4c05-921d-09bb540b877c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895559130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1895559130
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2503113331
Short name T505
Test name
Test status
Simulation time 123665513 ps
CPU time 1.48 seconds
Started Mar 28 01:08:41 PM PDT 24
Finished Mar 28 01:08:43 PM PDT 24
Peak memory 200888 kb
Host smart-2306e161-4cc7-4e92-a678-6d349e0c6390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503113331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2503113331
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.142670073
Short name T475
Test name
Test status
Simulation time 78483378 ps
CPU time 0.82 seconds
Started Mar 28 01:08:42 PM PDT 24
Finished Mar 28 01:08:43 PM PDT 24
Peak memory 200824 kb
Host smart-477f8309-94df-4a8e-af3e-84f0c796cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142670073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.142670073
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4106937061
Short name T215
Test name
Test status
Simulation time 71987297 ps
CPU time 0.76 seconds
Started Mar 28 01:08:59 PM PDT 24
Finished Mar 28 01:09:00 PM PDT 24
Peak memory 200712 kb
Host smart-314f30dd-8783-4e20-98cf-ebd12e9ac63d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106937061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4106937061
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.378743415
Short name T56
Test name
Test status
Simulation time 1226087416 ps
CPU time 5.65 seconds
Started Mar 28 01:08:59 PM PDT 24
Finished Mar 28 01:09:05 PM PDT 24
Peak memory 218392 kb
Host smart-64931cf7-6f1b-407e-b515-74c1f7e8f4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378743415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.378743415
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1220645868
Short name T511
Test name
Test status
Simulation time 251829082 ps
CPU time 1 seconds
Started Mar 28 01:08:56 PM PDT 24
Finished Mar 28 01:08:57 PM PDT 24
Peak memory 218028 kb
Host smart-38da770f-a291-4af3-9b15-73bf041f13a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220645868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1220645868
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3437063114
Short name T266
Test name
Test status
Simulation time 168330027 ps
CPU time 0.91 seconds
Started Mar 28 01:09:00 PM PDT 24
Finished Mar 28 01:09:01 PM PDT 24
Peak memory 200684 kb
Host smart-5bbc743c-2a95-42f3-b516-8a1140c7d05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437063114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3437063114
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3893940029
Short name T397
Test name
Test status
Simulation time 1444549532 ps
CPU time 5.4 seconds
Started Mar 28 01:08:54 PM PDT 24
Finished Mar 28 01:09:00 PM PDT 24
Peak memory 201040 kb
Host smart-49fd05d3-8dd6-45ec-bf88-d90f8a3a8b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893940029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3893940029
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.698609581
Short name T78
Test name
Test status
Simulation time 16862742213 ps
CPU time 23.77 seconds
Started Mar 28 01:08:57 PM PDT 24
Finished Mar 28 01:09:21 PM PDT 24
Peak memory 217768 kb
Host smart-195bf143-b083-4039-8c9b-7656b5ca0c6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698609581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.698609581
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2988222850
Short name T287
Test name
Test status
Simulation time 103697431 ps
CPU time 0.99 seconds
Started Mar 28 01:08:56 PM PDT 24
Finished Mar 28 01:08:57 PM PDT 24
Peak memory 200800 kb
Host smart-9afa9a3e-7dba-4786-965d-860501bdf338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988222850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2988222850
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.633360091
Short name T320
Test name
Test status
Simulation time 123074207 ps
CPU time 1.15 seconds
Started Mar 28 01:08:55 PM PDT 24
Finished Mar 28 01:08:56 PM PDT 24
Peak memory 201060 kb
Host smart-560c14aa-01dc-4591-89eb-7531510f250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633360091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.633360091
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.749593688
Short name T43
Test name
Test status
Simulation time 363622792 ps
CPU time 2.38 seconds
Started Mar 28 01:09:04 PM PDT 24
Finished Mar 28 01:09:07 PM PDT 24
Peak memory 200880 kb
Host smart-e72174f6-0105-4c56-91e3-734eb071a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749593688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.749593688
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2307881374
Short name T240
Test name
Test status
Simulation time 116779468 ps
CPU time 0.94 seconds
Started Mar 28 01:08:56 PM PDT 24
Finished Mar 28 01:08:57 PM PDT 24
Peak memory 200700 kb
Host smart-3c1beb02-0c3c-48b8-bd14-0d55b3126c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307881374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2307881374
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2215336783
Short name T171
Test name
Test status
Simulation time 85614441 ps
CPU time 0.8 seconds
Started Mar 28 01:09:55 PM PDT 24
Finished Mar 28 01:09:56 PM PDT 24
Peak memory 200704 kb
Host smart-19afed09-e186-4056-97b3-3cf230d660bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215336783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2215336783
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2176579328
Short name T395
Test name
Test status
Simulation time 2367971716 ps
CPU time 8.22 seconds
Started Mar 28 01:09:55 PM PDT 24
Finished Mar 28 01:10:03 PM PDT 24
Peak memory 218388 kb
Host smart-52efd4cc-53b9-41cd-8f37-08220382872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176579328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2176579328
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2835209726
Short name T330
Test name
Test status
Simulation time 244488383 ps
CPU time 1.09 seconds
Started Mar 28 01:09:56 PM PDT 24
Finished Mar 28 01:09:58 PM PDT 24
Peak memory 218072 kb
Host smart-68683410-261a-466b-96b3-14e3432b71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835209726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2835209726
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.543291638
Short name T225
Test name
Test status
Simulation time 120733865 ps
CPU time 0.79 seconds
Started Mar 28 01:09:51 PM PDT 24
Finished Mar 28 01:09:52 PM PDT 24
Peak memory 200696 kb
Host smart-7e3379c6-1880-4bcc-ab65-1d1b860a4408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543291638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.543291638
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.611076558
Short name T103
Test name
Test status
Simulation time 1752048134 ps
CPU time 5.89 seconds
Started Mar 28 01:09:49 PM PDT 24
Finished Mar 28 01:09:55 PM PDT 24
Peak memory 201024 kb
Host smart-2177e3b0-1340-47cb-8e44-468891a5fd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611076558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.611076558
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4062375435
Short name T88
Test name
Test status
Simulation time 105743978 ps
CPU time 1 seconds
Started Mar 28 01:09:56 PM PDT 24
Finished Mar 28 01:09:57 PM PDT 24
Peak memory 200844 kb
Host smart-e46a9cd2-a355-4f45-b7ec-dec8bac63a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062375435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4062375435
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2301255400
Short name T264
Test name
Test status
Simulation time 183957849 ps
CPU time 1.35 seconds
Started Mar 28 01:09:58 PM PDT 24
Finished Mar 28 01:10:00 PM PDT 24
Peak memory 200908 kb
Host smart-eaa0124f-3f4d-4e96-b607-bf863f627c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301255400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2301255400
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3146032608
Short name T60
Test name
Test status
Simulation time 4848062109 ps
CPU time 18.61 seconds
Started Mar 28 01:09:58 PM PDT 24
Finished Mar 28 01:10:17 PM PDT 24
Peak memory 201124 kb
Host smart-d115c24f-4078-4e17-b6d3-148ed71a5d95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146032608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3146032608
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.893335341
Short name T179
Test name
Test status
Simulation time 131030980 ps
CPU time 1.59 seconds
Started Mar 28 01:09:50 PM PDT 24
Finished Mar 28 01:09:52 PM PDT 24
Peak memory 200924 kb
Host smart-241aafee-0e6c-40c9-93f3-9eabbebd76ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893335341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.893335341
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1153835715
Short name T273
Test name
Test status
Simulation time 186375579 ps
CPU time 1.21 seconds
Started Mar 28 01:09:52 PM PDT 24
Finished Mar 28 01:09:54 PM PDT 24
Peak memory 200812 kb
Host smart-1ca108d7-70e9-4fe0-8ad7-ac51a876c6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153835715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1153835715
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1200053074
Short name T450
Test name
Test status
Simulation time 2186092687 ps
CPU time 7.93 seconds
Started Mar 28 01:09:52 PM PDT 24
Finished Mar 28 01:10:00 PM PDT 24
Peak memory 222740 kb
Host smart-6020be3f-19a2-423d-a95d-690a9091b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200053074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1200053074
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3172509673
Short name T374
Test name
Test status
Simulation time 244203558 ps
CPU time 1.05 seconds
Started Mar 28 01:09:51 PM PDT 24
Finished Mar 28 01:09:53 PM PDT 24
Peak memory 218120 kb
Host smart-8a84bbeb-69ab-4bdd-9bf4-457c68414292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172509673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3172509673
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3712286498
Short name T211
Test name
Test status
Simulation time 238904380 ps
CPU time 0.98 seconds
Started Mar 28 01:09:52 PM PDT 24
Finished Mar 28 01:09:53 PM PDT 24
Peak memory 200704 kb
Host smart-cd9879f8-0ae7-483c-b890-11e100e5a3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712286498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3712286498
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2761347624
Short name T305
Test name
Test status
Simulation time 95984202 ps
CPU time 0.98 seconds
Started Mar 28 01:09:58 PM PDT 24
Finished Mar 28 01:09:59 PM PDT 24
Peak memory 200828 kb
Host smart-0a4f6044-3f2f-469c-91ea-af26467b242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761347624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2761347624
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3939822820
Short name T140
Test name
Test status
Simulation time 196288358 ps
CPU time 1.29 seconds
Started Mar 28 01:09:52 PM PDT 24
Finished Mar 28 01:09:53 PM PDT 24
Peak memory 200984 kb
Host smart-7b9f26ce-fb57-43ed-bf91-abb745bdd220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939822820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3939822820
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2208637643
Short name T291
Test name
Test status
Simulation time 6958302904 ps
CPU time 29.39 seconds
Started Mar 28 01:09:54 PM PDT 24
Finished Mar 28 01:10:25 PM PDT 24
Peak memory 209200 kb
Host smart-6e3b04fa-8899-41b7-a0d4-362f6c8a9093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208637643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2208637643
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3209659175
Short name T405
Test name
Test status
Simulation time 475775879 ps
CPU time 2.56 seconds
Started Mar 28 01:09:52 PM PDT 24
Finished Mar 28 01:09:55 PM PDT 24
Peak memory 200884 kb
Host smart-36c9f932-0d1a-4e8b-99b1-048ead74d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209659175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3209659175
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3702194287
Short name T327
Test name
Test status
Simulation time 95073268 ps
CPU time 0.81 seconds
Started Mar 28 01:09:50 PM PDT 24
Finished Mar 28 01:09:51 PM PDT 24
Peak memory 200844 kb
Host smart-126e6dd3-c3e6-4b00-ad91-ece86f52a5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702194287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3702194287
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3881187003
Short name T255
Test name
Test status
Simulation time 72691163 ps
CPU time 0.77 seconds
Started Mar 28 01:09:58 PM PDT 24
Finished Mar 28 01:09:59 PM PDT 24
Peak memory 200700 kb
Host smart-10bd6435-90a4-4781-b8ba-3aef687bd8dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881187003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3881187003
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.457283690
Short name T357
Test name
Test status
Simulation time 1898790273 ps
CPU time 7.71 seconds
Started Mar 28 01:09:56 PM PDT 24
Finished Mar 28 01:10:04 PM PDT 24
Peak memory 218564 kb
Host smart-0f6f7b27-a320-4b2b-83d7-476efa847f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457283690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.457283690
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2320869082
Short name T238
Test name
Test status
Simulation time 243953420 ps
CPU time 1.1 seconds
Started Mar 28 01:09:52 PM PDT 24
Finished Mar 28 01:09:53 PM PDT 24
Peak memory 218244 kb
Host smart-5e9f1077-8ea2-4db6-8cf8-c3fa2a950505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320869082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2320869082
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2768102844
Short name T339
Test name
Test status
Simulation time 235037915 ps
CPU time 0.95 seconds
Started Mar 28 01:09:51 PM PDT 24
Finished Mar 28 01:09:52 PM PDT 24
Peak memory 200464 kb
Host smart-645fc4ed-612c-4ce7-90c0-df837aae4232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768102844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2768102844
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.288229378
Short name T174
Test name
Test status
Simulation time 1040493072 ps
CPU time 4.87 seconds
Started Mar 28 01:09:55 PM PDT 24
Finished Mar 28 01:10:00 PM PDT 24
Peak memory 200784 kb
Host smart-b4d78e3b-105c-4bdb-be58-0e058fa300da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288229378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.288229378
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3954855633
Short name T441
Test name
Test status
Simulation time 109660451 ps
CPU time 1.08 seconds
Started Mar 28 01:09:52 PM PDT 24
Finished Mar 28 01:09:53 PM PDT 24
Peak memory 200984 kb
Host smart-de6570b6-8b70-440c-99f7-f96f7b205d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954855633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3954855633
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.4112408393
Short name T510
Test name
Test status
Simulation time 12292346416 ps
CPU time 43.71 seconds
Started Mar 28 01:09:54 PM PDT 24
Finished Mar 28 01:10:39 PM PDT 24
Peak memory 201124 kb
Host smart-396da243-8792-4777-8dd7-9fd59b61454b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112408393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.4112408393
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2315033910
Short name T412
Test name
Test status
Simulation time 126157353 ps
CPU time 1.51 seconds
Started Mar 28 01:09:56 PM PDT 24
Finished Mar 28 01:09:58 PM PDT 24
Peak memory 200896 kb
Host smart-eb39a4cd-d161-42ce-8440-b42b0f743daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315033910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2315033910
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2032134965
Short name T439
Test name
Test status
Simulation time 65688745 ps
CPU time 0.79 seconds
Started Mar 28 01:09:56 PM PDT 24
Finished Mar 28 01:09:57 PM PDT 24
Peak memory 200804 kb
Host smart-1d521b86-2efd-4f12-b909-cece687f1069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032134965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2032134965
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1153568325
Short name T285
Test name
Test status
Simulation time 74190965 ps
CPU time 0.8 seconds
Started Mar 28 01:10:23 PM PDT 24
Finished Mar 28 01:10:25 PM PDT 24
Peak memory 200712 kb
Host smart-3e9f817c-b292-47a5-b527-13f2dd19942e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153568325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1153568325
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.919642214
Short name T37
Test name
Test status
Simulation time 2361500645 ps
CPU time 8.19 seconds
Started Mar 28 01:09:54 PM PDT 24
Finished Mar 28 01:10:03 PM PDT 24
Peak memory 218624 kb
Host smart-a9ca0c11-3bcb-4cc9-998f-f90b14e76735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919642214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.919642214
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1672454357
Short name T222
Test name
Test status
Simulation time 243872653 ps
CPU time 1.07 seconds
Started Mar 28 01:09:47 PM PDT 24
Finished Mar 28 01:09:48 PM PDT 24
Peak memory 218096 kb
Host smart-9e2a826f-4c97-4fa6-b8a6-8631cbfaf340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672454357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1672454357
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.275144776
Short name T507
Test name
Test status
Simulation time 1497000941 ps
CPU time 6.03 seconds
Started Mar 28 01:09:55 PM PDT 24
Finished Mar 28 01:10:01 PM PDT 24
Peak memory 200884 kb
Host smart-0f4d1d43-9a5e-4f2f-9d40-32a6ea425079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275144776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.275144776
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3935833634
Short name T246
Test name
Test status
Simulation time 136082281 ps
CPU time 1.11 seconds
Started Mar 28 01:09:55 PM PDT 24
Finished Mar 28 01:09:57 PM PDT 24
Peak memory 200708 kb
Host smart-42e1d263-a7dc-4d52-8426-81bc818cbda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935833634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3935833634
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3491105103
Short name T208
Test name
Test status
Simulation time 118440290 ps
CPU time 1.13 seconds
Started Mar 28 01:09:51 PM PDT 24
Finished Mar 28 01:09:53 PM PDT 24
Peak memory 200984 kb
Host smart-bc63665a-b683-4df5-915b-867418fa585a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491105103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3491105103
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.737376452
Short name T531
Test name
Test status
Simulation time 4735243356 ps
CPU time 20.79 seconds
Started Mar 28 01:10:19 PM PDT 24
Finished Mar 28 01:10:40 PM PDT 24
Peak memory 210084 kb
Host smart-af4dfeef-18c0-495f-99df-1afa7ac65b19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737376452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.737376452
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.833234153
Short name T368
Test name
Test status
Simulation time 115581951 ps
CPU time 1.49 seconds
Started Mar 28 01:09:56 PM PDT 24
Finished Mar 28 01:09:58 PM PDT 24
Peak memory 200844 kb
Host smart-07c42dd0-11e6-4be3-b9f0-d907c9d4c8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833234153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.833234153
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.324601730
Short name T508
Test name
Test status
Simulation time 214481179 ps
CPU time 1.28 seconds
Started Mar 28 01:09:50 PM PDT 24
Finished Mar 28 01:09:52 PM PDT 24
Peak memory 200840 kb
Host smart-16c9fcd0-e2db-4206-9a64-59eb8360610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324601730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.324601730
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3524762630
Short name T435
Test name
Test status
Simulation time 68487246 ps
CPU time 0.77 seconds
Started Mar 28 01:10:18 PM PDT 24
Finished Mar 28 01:10:19 PM PDT 24
Peak memory 200688 kb
Host smart-aa8b0ba7-dd9b-4a09-8e6c-9cc02169fbee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524762630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3524762630
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1146670423
Short name T47
Test name
Test status
Simulation time 2339184220 ps
CPU time 8.55 seconds
Started Mar 28 01:10:21 PM PDT 24
Finished Mar 28 01:10:29 PM PDT 24
Peak memory 222560 kb
Host smart-ed835982-b1b2-4ade-8516-cce2fed6adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146670423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1146670423
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1035661464
Short name T389
Test name
Test status
Simulation time 244108449 ps
CPU time 1.12 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:18 PM PDT 24
Peak memory 218056 kb
Host smart-75e96c23-b9d8-467c-b319-34b878866703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035661464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1035661464
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2891949411
Short name T223
Test name
Test status
Simulation time 94355370 ps
CPU time 0.77 seconds
Started Mar 28 01:10:19 PM PDT 24
Finished Mar 28 01:10:20 PM PDT 24
Peak memory 200672 kb
Host smart-e4a6d7d6-0cd2-4904-8791-017d9ff35846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891949411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2891949411
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.784733160
Short name T102
Test name
Test status
Simulation time 2086679612 ps
CPU time 7.63 seconds
Started Mar 28 01:10:18 PM PDT 24
Finished Mar 28 01:10:26 PM PDT 24
Peak memory 200992 kb
Host smart-2368ea1d-89d8-4c30-b941-6729cea43825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784733160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.784733160
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2807149932
Short name T295
Test name
Test status
Simulation time 144820762 ps
CPU time 1.08 seconds
Started Mar 28 01:10:22 PM PDT 24
Finished Mar 28 01:10:23 PM PDT 24
Peak memory 200856 kb
Host smart-62b852c5-1076-4f68-b9aa-f0fb249dd10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807149932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2807149932
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.732024506
Short name T278
Test name
Test status
Simulation time 191693222 ps
CPU time 1.29 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:21 PM PDT 24
Peak memory 200928 kb
Host smart-f1d601ad-cce6-45f0-bbb7-f97b4745e4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732024506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.732024506
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.869742412
Short name T387
Test name
Test status
Simulation time 2965339852 ps
CPU time 14.04 seconds
Started Mar 28 01:10:21 PM PDT 24
Finished Mar 28 01:10:36 PM PDT 24
Peak memory 201128 kb
Host smart-c56695d9-a0ab-4d6b-85f0-c29e234a1e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869742412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.869742412
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3659684778
Short name T346
Test name
Test status
Simulation time 402120239 ps
CPU time 2.14 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:22 PM PDT 24
Peak memory 200884 kb
Host smart-6c6f4271-69dc-4ac1-abc9-f87327f29c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659684778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3659684778
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1552977874
Short name T344
Test name
Test status
Simulation time 123041206 ps
CPU time 1.09 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:21 PM PDT 24
Peak memory 200708 kb
Host smart-227d8990-a6a0-4382-804a-babdde730c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552977874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1552977874
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3503587379
Short name T168
Test name
Test status
Simulation time 66235261 ps
CPU time 0.74 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:18 PM PDT 24
Peak memory 200724 kb
Host smart-66fa4971-4878-48db-8742-4da478db1411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503587379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3503587379
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3304148119
Short name T472
Test name
Test status
Simulation time 1222417296 ps
CPU time 5.31 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:26 PM PDT 24
Peak memory 218552 kb
Host smart-aa8ac641-8813-40bb-95b9-6a8a73703d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304148119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3304148119
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1240222949
Short name T250
Test name
Test status
Simulation time 245495741 ps
CPU time 1.13 seconds
Started Mar 28 01:10:19 PM PDT 24
Finished Mar 28 01:10:21 PM PDT 24
Peak memory 218136 kb
Host smart-956b68ff-b868-42c7-acb2-ed45603d5b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240222949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1240222949
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1654329933
Short name T489
Test name
Test status
Simulation time 211314354 ps
CPU time 0.88 seconds
Started Mar 28 01:10:18 PM PDT 24
Finished Mar 28 01:10:19 PM PDT 24
Peak memory 200700 kb
Host smart-05e2184c-cd7d-48be-a3f9-52c9905e784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654329933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1654329933
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3710903435
Short name T256
Test name
Test status
Simulation time 770289882 ps
CPU time 3.98 seconds
Started Mar 28 01:10:21 PM PDT 24
Finished Mar 28 01:10:26 PM PDT 24
Peak memory 200996 kb
Host smart-c0747f8f-212c-4483-a542-989ab6d074b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710903435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3710903435
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3254813863
Short name T409
Test name
Test status
Simulation time 182569628 ps
CPU time 1.14 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:19 PM PDT 24
Peak memory 200880 kb
Host smart-870d6a5a-d744-464f-af88-06eab9b83d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254813863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3254813863
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1724798211
Short name T336
Test name
Test status
Simulation time 123784454 ps
CPU time 1.19 seconds
Started Mar 28 01:10:21 PM PDT 24
Finished Mar 28 01:10:23 PM PDT 24
Peak memory 200960 kb
Host smart-6dfbdea4-9621-40f1-bbc0-6bab27a2a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724798211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1724798211
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.558417828
Short name T527
Test name
Test status
Simulation time 1448965959 ps
CPU time 6.94 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:27 PM PDT 24
Peak memory 209188 kb
Host smart-de64a54c-2d7e-421b-a7a1-723445a57ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558417828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.558417828
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2663702359
Short name T372
Test name
Test status
Simulation time 334940290 ps
CPU time 2.11 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:20 PM PDT 24
Peak memory 200876 kb
Host smart-8a609136-585d-4178-bbb3-409341ed96fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663702359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2663702359
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3614925218
Short name T300
Test name
Test status
Simulation time 177440223 ps
CPU time 1.19 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:22 PM PDT 24
Peak memory 200772 kb
Host smart-293ba055-ba51-4658-983e-dfccc6129b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614925218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3614925218
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.789922975
Short name T271
Test name
Test status
Simulation time 62446828 ps
CPU time 0.7 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:21 PM PDT 24
Peak memory 200696 kb
Host smart-7afaca79-2bbe-4fc7-8438-228dda26e1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789922975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.789922975
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2256809077
Short name T49
Test name
Test status
Simulation time 1910218230 ps
CPU time 7.66 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:24 PM PDT 24
Peak memory 222616 kb
Host smart-552cdc3e-59ef-4bc9-aff3-e39e62e68646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256809077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2256809077
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1364783881
Short name T165
Test name
Test status
Simulation time 244112088 ps
CPU time 1.03 seconds
Started Mar 28 01:10:22 PM PDT 24
Finished Mar 28 01:10:23 PM PDT 24
Peak memory 218244 kb
Host smart-fe4c3f39-4c45-4575-952b-75a192c0d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364783881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1364783881
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2631070813
Short name T277
Test name
Test status
Simulation time 189116499 ps
CPU time 0.89 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:21 PM PDT 24
Peak memory 200696 kb
Host smart-f8755df6-5166-436c-8e5c-4dca988b4b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631070813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2631070813
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.530567917
Short name T529
Test name
Test status
Simulation time 938697692 ps
CPU time 4.9 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:22 PM PDT 24
Peak memory 201020 kb
Host smart-2f7246fc-4789-42c7-a505-7556cbc57cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530567917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.530567917
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2513789508
Short name T79
Test name
Test status
Simulation time 98944028 ps
CPU time 0.96 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:22 PM PDT 24
Peak memory 200820 kb
Host smart-a2f38108-cb29-4f70-95fa-cd4a46e825f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513789508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2513789508
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2982319016
Short name T202
Test name
Test status
Simulation time 259940326 ps
CPU time 1.58 seconds
Started Mar 28 01:10:21 PM PDT 24
Finished Mar 28 01:10:22 PM PDT 24
Peak memory 201036 kb
Host smart-9ab69738-e0ce-4168-8897-e9189a38b835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982319016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2982319016
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1290010968
Short name T100
Test name
Test status
Simulation time 6555452786 ps
CPU time 24.3 seconds
Started Mar 28 01:10:19 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 201124 kb
Host smart-700e4dc6-969e-4364-ade1-da1ec4b6ea63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290010968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1290010968
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1642415001
Short name T82
Test name
Test status
Simulation time 110790882 ps
CPU time 1.33 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:18 PM PDT 24
Peak memory 200892 kb
Host smart-2643fae2-2c01-483d-9e94-759321b434b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642415001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1642415001
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1515138885
Short name T506
Test name
Test status
Simulation time 95122429 ps
CPU time 0.84 seconds
Started Mar 28 01:10:19 PM PDT 24
Finished Mar 28 01:10:20 PM PDT 24
Peak memory 200856 kb
Host smart-8f144e66-b613-4f36-84ab-980d74769891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515138885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1515138885
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3387537668
Short name T323
Test name
Test status
Simulation time 82827037 ps
CPU time 0.8 seconds
Started Mar 28 01:10:22 PM PDT 24
Finished Mar 28 01:10:23 PM PDT 24
Peak memory 200712 kb
Host smart-0d50665a-7f2f-4877-848f-a6b3430ebb28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387537668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3387537668
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2465203665
Short name T38
Test name
Test status
Simulation time 1907164049 ps
CPU time 7.07 seconds
Started Mar 28 01:10:18 PM PDT 24
Finished Mar 28 01:10:25 PM PDT 24
Peak memory 218044 kb
Host smart-f65e601c-d4a8-4992-83d8-c73108239da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465203665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2465203665
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2632766476
Short name T533
Test name
Test status
Simulation time 243499189 ps
CPU time 1.09 seconds
Started Mar 28 01:10:19 PM PDT 24
Finished Mar 28 01:10:20 PM PDT 24
Peak memory 218192 kb
Host smart-9eedbee1-3f97-4ec4-8724-af1bb5bd055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632766476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2632766476
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.948462461
Short name T195
Test name
Test status
Simulation time 106747837 ps
CPU time 0.74 seconds
Started Mar 28 01:10:21 PM PDT 24
Finished Mar 28 01:10:22 PM PDT 24
Peak memory 200716 kb
Host smart-714c293a-c6f0-4f1c-a454-a0f8ae4d3c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948462461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.948462461
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3458862799
Short name T220
Test name
Test status
Simulation time 779380082 ps
CPU time 4.34 seconds
Started Mar 28 01:10:19 PM PDT 24
Finished Mar 28 01:10:23 PM PDT 24
Peak memory 200968 kb
Host smart-60ad8f1a-10ac-482b-9a70-46a84e472fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458862799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3458862799
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2492613040
Short name T484
Test name
Test status
Simulation time 103362632 ps
CPU time 0.91 seconds
Started Mar 28 01:10:21 PM PDT 24
Finished Mar 28 01:10:22 PM PDT 24
Peak memory 200672 kb
Host smart-1452c89c-4432-48f0-b994-1c9ccc42c8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492613040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2492613040
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1085632126
Short name T347
Test name
Test status
Simulation time 251572083 ps
CPU time 1.43 seconds
Started Mar 28 01:10:18 PM PDT 24
Finished Mar 28 01:10:20 PM PDT 24
Peak memory 200972 kb
Host smart-544ae4ba-5489-4472-805c-b6ebe98c77df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085632126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1085632126
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1847876634
Short name T290
Test name
Test status
Simulation time 4581601299 ps
CPU time 20.28 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:37 PM PDT 24
Peak memory 201068 kb
Host smart-221f14b7-4e98-4061-a55e-44d6801f60da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847876634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1847876634
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.761027697
Short name T447
Test name
Test status
Simulation time 300321482 ps
CPU time 1.92 seconds
Started Mar 28 01:10:19 PM PDT 24
Finished Mar 28 01:10:21 PM PDT 24
Peak memory 209096 kb
Host smart-cb71dd9b-b9f5-4f82-9e9c-4a3b651bc544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761027697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.761027697
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.198988684
Short name T181
Test name
Test status
Simulation time 244445929 ps
CPU time 1.34 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:18 PM PDT 24
Peak memory 200804 kb
Host smart-7d3f231f-f2fb-4b0f-b28e-5e9128fd774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198988684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.198988684
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3419379748
Short name T284
Test name
Test status
Simulation time 75286967 ps
CPU time 0.75 seconds
Started Mar 28 01:10:40 PM PDT 24
Finished Mar 28 01:10:41 PM PDT 24
Peak memory 200752 kb
Host smart-87c17d1a-d004-4520-8797-d83750841061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419379748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3419379748
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1218579867
Short name T55
Test name
Test status
Simulation time 1891763648 ps
CPU time 7.95 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:53 PM PDT 24
Peak memory 222572 kb
Host smart-84858764-07bd-4f46-a9ae-6031a54d276c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218579867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1218579867
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1597130844
Short name T141
Test name
Test status
Simulation time 244525779 ps
CPU time 1.16 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:45 PM PDT 24
Peak memory 218084 kb
Host smart-3c7a5c74-bd18-4b66-89f4-e849f16f5902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597130844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1597130844
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3187919828
Short name T465
Test name
Test status
Simulation time 86778733 ps
CPU time 0.74 seconds
Started Mar 28 01:10:17 PM PDT 24
Finished Mar 28 01:10:18 PM PDT 24
Peak memory 200664 kb
Host smart-73eb2b86-779c-4e82-a714-7d12d99e77c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187919828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3187919828
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.982651737
Short name T333
Test name
Test status
Simulation time 2018166568 ps
CPU time 7.44 seconds
Started Mar 28 01:10:22 PM PDT 24
Finished Mar 28 01:10:29 PM PDT 24
Peak memory 201072 kb
Host smart-060426ec-3757-44d5-a40b-e1ef80560135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982651737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.982651737
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2831502460
Short name T210
Test name
Test status
Simulation time 147783857 ps
CPU time 1.06 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 200836 kb
Host smart-3955fc75-b7e8-4b2a-a584-dfdd6c34cc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831502460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2831502460
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1714289783
Short name T427
Test name
Test status
Simulation time 116696271 ps
CPU time 1.1 seconds
Started Mar 28 01:10:20 PM PDT 24
Finished Mar 28 01:10:21 PM PDT 24
Peak memory 200896 kb
Host smart-09a3ebc4-9e56-420c-a25a-32d9fe45f65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714289783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1714289783
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.329742787
Short name T288
Test name
Test status
Simulation time 14869367144 ps
CPU time 52.62 seconds
Started Mar 28 01:10:39 PM PDT 24
Finished Mar 28 01:11:32 PM PDT 24
Peak memory 201108 kb
Host smart-cfda94c7-655e-484d-893c-6ab4beedd726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329742787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.329742787
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2890627851
Short name T335
Test name
Test status
Simulation time 144118026 ps
CPU time 1.68 seconds
Started Mar 28 01:10:40 PM PDT 24
Finished Mar 28 01:10:42 PM PDT 24
Peak memory 200892 kb
Host smart-2d047e63-a1ed-4301-9d14-91e67c58c2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890627851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2890627851
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1116604564
Short name T226
Test name
Test status
Simulation time 106612901 ps
CPU time 0.92 seconds
Started Mar 28 01:10:40 PM PDT 24
Finished Mar 28 01:10:41 PM PDT 24
Peak memory 200836 kb
Host smart-4bbdc5bd-1898-4e10-8338-0c03cb204b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116604564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1116604564
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.648491205
Short name T476
Test name
Test status
Simulation time 73122252 ps
CPU time 0.78 seconds
Started Mar 28 01:10:39 PM PDT 24
Finished Mar 28 01:10:40 PM PDT 24
Peak memory 200728 kb
Host smart-6a707387-9120-4eb1-846f-baf7a53db259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648491205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.648491205
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1694929554
Short name T492
Test name
Test status
Simulation time 1905429441 ps
CPU time 7.32 seconds
Started Mar 28 01:10:39 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 218576 kb
Host smart-8b3c752c-94e9-4c41-8213-92ca7a0b2c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694929554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1694929554
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3476848767
Short name T530
Test name
Test status
Simulation time 243861881 ps
CPU time 1.04 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 218192 kb
Host smart-e0c04058-df56-4f92-8e1c-5c52a32f3fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476848767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3476848767
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1791674326
Short name T515
Test name
Test status
Simulation time 93025953 ps
CPU time 0.8 seconds
Started Mar 28 01:10:40 PM PDT 24
Finished Mar 28 01:10:41 PM PDT 24
Peak memory 200692 kb
Host smart-9c3587cb-9964-4327-a965-75df3b552741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791674326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1791674326
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3657718345
Short name T96
Test name
Test status
Simulation time 1648206994 ps
CPU time 5.97 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:10:48 PM PDT 24
Peak memory 200920 kb
Host smart-153fb404-30c0-4194-8a54-0d8443a4f14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657718345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3657718345
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2696855955
Short name T186
Test name
Test status
Simulation time 101955080 ps
CPU time 0.97 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:42 PM PDT 24
Peak memory 200800 kb
Host smart-7792d930-8d34-456f-ba27-0b5c75c5128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696855955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2696855955
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3060243423
Short name T517
Test name
Test status
Simulation time 197531378 ps
CPU time 1.5 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 200960 kb
Host smart-42e57a8b-02ee-4d4a-9543-a0c22ad0561a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060243423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3060243423
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.600934847
Short name T493
Test name
Test status
Simulation time 12781888711 ps
CPU time 41.43 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:11:26 PM PDT 24
Peak memory 209316 kb
Host smart-b4fca8ee-5737-4566-adb4-99d017e65c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600934847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.600934847
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.936527052
Short name T391
Test name
Test status
Simulation time 554447375 ps
CPU time 2.96 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:10:45 PM PDT 24
Peak memory 200820 kb
Host smart-6839e907-1189-495e-8665-fa102c294670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936527052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.936527052
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1168246262
Short name T132
Test name
Test status
Simulation time 256084403 ps
CPU time 1.42 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 200804 kb
Host smart-8652aead-79f1-4bd5-aab3-fd9750384922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168246262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1168246262
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3889741997
Short name T535
Test name
Test status
Simulation time 68649732 ps
CPU time 0.77 seconds
Started Mar 28 01:08:55 PM PDT 24
Finished Mar 28 01:08:56 PM PDT 24
Peak memory 200632 kb
Host smart-26e1b06e-3f6e-40ca-820c-e8aed1dc6557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889741997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3889741997
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3725937579
Short name T539
Test name
Test status
Simulation time 243947531 ps
CPU time 1.03 seconds
Started Mar 28 01:09:00 PM PDT 24
Finished Mar 28 01:09:01 PM PDT 24
Peak memory 218032 kb
Host smart-5e539584-b69d-4018-914c-97b3c290b67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725937579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3725937579
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.38091305
Short name T403
Test name
Test status
Simulation time 142149096 ps
CPU time 0.79 seconds
Started Mar 28 01:08:55 PM PDT 24
Finished Mar 28 01:08:56 PM PDT 24
Peak memory 200680 kb
Host smart-9c08b927-f7ef-4526-ba94-b16757eaa160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38091305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.38091305
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.373006515
Short name T201
Test name
Test status
Simulation time 816031556 ps
CPU time 4.48 seconds
Started Mar 28 01:08:53 PM PDT 24
Finished Mar 28 01:08:58 PM PDT 24
Peak memory 200992 kb
Host smart-147d5f83-fd98-42a7-b40b-6fd9119dcdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373006515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.373006515
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.379468375
Short name T77
Test name
Test status
Simulation time 8540050308 ps
CPU time 12.56 seconds
Started Mar 28 01:08:55 PM PDT 24
Finished Mar 28 01:09:08 PM PDT 24
Peak memory 217812 kb
Host smart-3f514258-32cf-4728-833b-84940863286d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379468375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.379468375
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.95268120
Short name T308
Test name
Test status
Simulation time 102402260 ps
CPU time 0.96 seconds
Started Mar 28 01:09:04 PM PDT 24
Finished Mar 28 01:09:05 PM PDT 24
Peak memory 200820 kb
Host smart-036f2349-33e4-432e-aaa8-f62622c5bece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95268120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.95268120
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1422720810
Short name T524
Test name
Test status
Simulation time 252945322 ps
CPU time 1.57 seconds
Started Mar 28 01:08:56 PM PDT 24
Finished Mar 28 01:08:58 PM PDT 24
Peak memory 201036 kb
Host smart-efbde961-bc1a-40f9-b6a5-89930192c7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422720810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1422720810
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2008094349
Short name T207
Test name
Test status
Simulation time 3411397578 ps
CPU time 14.9 seconds
Started Mar 28 01:08:54 PM PDT 24
Finished Mar 28 01:09:09 PM PDT 24
Peak memory 209332 kb
Host smart-3eb5ed24-388b-457e-b032-e799ac87715c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008094349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2008094349
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2015898814
Short name T244
Test name
Test status
Simulation time 151999407 ps
CPU time 1.89 seconds
Started Mar 28 01:08:58 PM PDT 24
Finished Mar 28 01:09:00 PM PDT 24
Peak memory 200896 kb
Host smart-66e5dbbb-979b-4921-95fb-c45878a7d796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015898814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2015898814
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3252328501
Short name T144
Test name
Test status
Simulation time 90326613 ps
CPU time 1.05 seconds
Started Mar 28 01:08:55 PM PDT 24
Finished Mar 28 01:08:56 PM PDT 24
Peak memory 200784 kb
Host smart-dc4c0683-578a-414f-b514-91c95681024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252328501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3252328501
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.804466882
Short name T383
Test name
Test status
Simulation time 69412351 ps
CPU time 0.79 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 200612 kb
Host smart-a66b9e26-ff2e-4682-93a0-392478bd8226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804466882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.804466882
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1851782261
Short name T46
Test name
Test status
Simulation time 1893370321 ps
CPU time 6.68 seconds
Started Mar 28 01:10:39 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 230156 kb
Host smart-bb635199-09e3-4bbb-b2a8-77227e1d8655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851782261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1851782261
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2104892983
Short name T433
Test name
Test status
Simulation time 244238382 ps
CPU time 1.1 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 218136 kb
Host smart-4e77167d-dc27-4657-ae91-c6b84b4455e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104892983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2104892983
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3682055006
Short name T23
Test name
Test status
Simulation time 135328694 ps
CPU time 0.82 seconds
Started Mar 28 01:10:40 PM PDT 24
Finished Mar 28 01:10:41 PM PDT 24
Peak memory 200708 kb
Host smart-2ea8f3bf-fce4-40b3-a802-ae695c247114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682055006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3682055006
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3654987174
Short name T160
Test name
Test status
Simulation time 871613102 ps
CPU time 4.42 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:49 PM PDT 24
Peak memory 201004 kb
Host smart-3259daa2-ed3d-4bd2-a2a4-2bf55478edaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654987174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3654987174
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.598013676
Short name T138
Test name
Test status
Simulation time 183320193 ps
CPU time 1.18 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 200848 kb
Host smart-ea075c86-6275-43cf-8b9a-efe1939e120f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598013676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.598013676
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2656223673
Short name T198
Test name
Test status
Simulation time 250789592 ps
CPU time 1.46 seconds
Started Mar 28 01:10:38 PM PDT 24
Finished Mar 28 01:10:39 PM PDT 24
Peak memory 201052 kb
Host smart-8938da4d-5977-469a-b77b-ca584bb9f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656223673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2656223673
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3068209105
Short name T483
Test name
Test status
Simulation time 5032406421 ps
CPU time 21.56 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:11:04 PM PDT 24
Peak memory 201092 kb
Host smart-5ca3f7a9-6d99-4e65-be85-edc20ea5dfd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068209105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3068209105
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.401164198
Short name T151
Test name
Test status
Simulation time 147540277 ps
CPU time 1.76 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:45 PM PDT 24
Peak memory 200844 kb
Host smart-7f44bade-1dd6-4563-bfd0-88e5effe86b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401164198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.401164198
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1133830921
Short name T520
Test name
Test status
Simulation time 129583491 ps
CPU time 0.94 seconds
Started Mar 28 01:10:40 PM PDT 24
Finished Mar 28 01:10:41 PM PDT 24
Peak memory 200660 kb
Host smart-f3404118-62a9-4874-9662-c905678fd54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133830921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1133830921
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3297408809
Short name T486
Test name
Test status
Simulation time 73364037 ps
CPU time 0.83 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 200584 kb
Host smart-15bcffd0-7edb-4cbb-ae50-0756ba98c412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297408809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3297408809
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2322000014
Short name T42
Test name
Test status
Simulation time 2365962238 ps
CPU time 7.95 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:49 PM PDT 24
Peak memory 222804 kb
Host smart-6fc8661f-287e-4e5d-b70a-d75ea8ff70ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322000014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2322000014
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4133037494
Short name T345
Test name
Test status
Simulation time 243832777 ps
CPU time 1.04 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:42 PM PDT 24
Peak memory 218136 kb
Host smart-92f8051b-1391-4668-92dc-21a8bc2c2178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133037494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4133037494
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.596220316
Short name T498
Test name
Test status
Simulation time 182161245 ps
CPU time 0.91 seconds
Started Mar 28 01:10:38 PM PDT 24
Finished Mar 28 01:10:39 PM PDT 24
Peak memory 200648 kb
Host smart-84abbb1d-8907-40f6-84fb-c6ac07bb842b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596220316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.596220316
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3429605582
Short name T479
Test name
Test status
Simulation time 1588670912 ps
CPU time 6.05 seconds
Started Mar 28 01:10:38 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 201040 kb
Host smart-a210471d-3d6b-46a1-997d-5d6b0c1935c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429605582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3429605582
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1202232924
Short name T261
Test name
Test status
Simulation time 141445717 ps
CPU time 1.09 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 200828 kb
Host smart-fc0f6869-d76e-4d81-989a-e98712b81932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202232924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1202232924
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3092270673
Short name T293
Test name
Test status
Simulation time 119621356 ps
CPU time 1.26 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 201020 kb
Host smart-e9db9cc0-7f12-4feb-a9bc-507fb984cf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092270673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3092270673
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.238432802
Short name T457
Test name
Test status
Simulation time 12807555724 ps
CPU time 45.82 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:11:27 PM PDT 24
Peak memory 209344 kb
Host smart-f5565ead-8a66-413f-827c-e6a785f3cea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238432802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.238432802
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.212279490
Short name T312
Test name
Test status
Simulation time 317032069 ps
CPU time 1.95 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 200860 kb
Host smart-685e05c2-6bac-4728-8cc6-7785dc8866bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212279490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.212279490
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3250922753
Short name T190
Test name
Test status
Simulation time 281535056 ps
CPU time 1.42 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 200772 kb
Host smart-d2580b40-31ae-4942-a2a7-1addadf565b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250922753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3250922753
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3571404024
Short name T131
Test name
Test status
Simulation time 67372505 ps
CPU time 0.74 seconds
Started Mar 28 01:10:46 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 200672 kb
Host smart-e407af28-a3e5-4a77-ba1c-3e101d2b751a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571404024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3571404024
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1850489230
Short name T393
Test name
Test status
Simulation time 244359729 ps
CPU time 1.12 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 218068 kb
Host smart-4c862f56-a144-4bca-8893-f9e96ad7f9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850489230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1850489230
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2058409374
Short name T283
Test name
Test status
Simulation time 90914882 ps
CPU time 0.76 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:42 PM PDT 24
Peak memory 200712 kb
Host smart-0b6b5f35-3e47-42e5-a0e4-4a1564140c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058409374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2058409374
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3228908931
Short name T213
Test name
Test status
Simulation time 1680137480 ps
CPU time 6.21 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:49 PM PDT 24
Peak memory 200956 kb
Host smart-cce0edde-b66f-4a09-95b2-ee3a878fa451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228908931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3228908931
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1136983725
Short name T404
Test name
Test status
Simulation time 174322065 ps
CPU time 1.17 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 200804 kb
Host smart-68e7b369-abb3-48c4-a84d-36d956b69481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136983725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1136983725
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.324343246
Short name T470
Test name
Test status
Simulation time 245041457 ps
CPU time 1.45 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:45 PM PDT 24
Peak memory 200912 kb
Host smart-c46c9fd1-ba5c-40c4-9bd9-00f75b4cb62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324343246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.324343246
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1766373571
Short name T324
Test name
Test status
Simulation time 6040578507 ps
CPU time 20.76 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:11:06 PM PDT 24
Peak memory 201124 kb
Host smart-09c82b0c-d007-47e6-a6a5-1cb7c4576258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766373571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1766373571
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1198413524
Short name T147
Test name
Test status
Simulation time 152110563 ps
CPU time 2.02 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:47 PM PDT 24
Peak memory 200872 kb
Host smart-0e515253-9bb9-4ca4-b55c-81335b1f6c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198413524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1198413524
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1585524195
Short name T430
Test name
Test status
Simulation time 115453291 ps
CPU time 0.96 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 200716 kb
Host smart-7b95de59-cd09-428d-849e-33e361f600b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585524195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1585524195
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1887945737
Short name T431
Test name
Test status
Simulation time 60112894 ps
CPU time 0.73 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:45 PM PDT 24
Peak memory 200716 kb
Host smart-b1c304b4-4cc9-40cc-a2cb-b0d057497525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887945737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1887945737
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.662751996
Short name T36
Test name
Test status
Simulation time 2173752999 ps
CPU time 7.66 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:49 PM PDT 24
Peak memory 222740 kb
Host smart-899f87db-8217-426f-8303-bfa69167fc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662751996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.662751996
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3588848636
Short name T452
Test name
Test status
Simulation time 246449327 ps
CPU time 1.01 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 218420 kb
Host smart-94818310-b940-4a05-bcb0-ecfa812cfa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588848636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3588848636
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.709589049
Short name T263
Test name
Test status
Simulation time 207455711 ps
CPU time 0.94 seconds
Started Mar 28 01:10:46 PM PDT 24
Finished Mar 28 01:10:47 PM PDT 24
Peak memory 200652 kb
Host smart-c1cc00f1-f80d-43ff-b4ad-d1919f100a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709589049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.709589049
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1668931366
Short name T242
Test name
Test status
Simulation time 870294859 ps
CPU time 4.32 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 200980 kb
Host smart-a4ef67d9-7b2b-4895-b108-9e8dae9633fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668931366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1668931366
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.847437731
Short name T227
Test name
Test status
Simulation time 98829491 ps
CPU time 0.98 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 200792 kb
Host smart-5fa0d7be-4dbe-4313-ad29-d99a235f0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847437731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.847437731
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2392697344
Short name T212
Test name
Test status
Simulation time 202116909 ps
CPU time 1.47 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:45 PM PDT 24
Peak memory 200940 kb
Host smart-5bc9668e-d650-4dbf-bbcd-9fbd9a8e6830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392697344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2392697344
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.4206471519
Short name T315
Test name
Test status
Simulation time 1339878719 ps
CPU time 5.54 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 200988 kb
Host smart-8ff175f8-a223-48cf-80b2-7f74714984c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206471519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.4206471519
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3182309146
Short name T307
Test name
Test status
Simulation time 171288854 ps
CPU time 1.16 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:42 PM PDT 24
Peak memory 200836 kb
Host smart-219133e5-4d8b-4b89-8b21-e244ab8c4c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182309146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3182309146
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3535408407
Short name T364
Test name
Test status
Simulation time 94999128 ps
CPU time 0.83 seconds
Started Mar 28 01:10:46 PM PDT 24
Finished Mar 28 01:10:47 PM PDT 24
Peak memory 200672 kb
Host smart-b160964a-cce9-4b60-a367-9815e044fd85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535408407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3535408407
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1301054018
Short name T525
Test name
Test status
Simulation time 2348541300 ps
CPU time 8.27 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:52 PM PDT 24
Peak memory 218300 kb
Host smart-980c3603-c64b-44b5-b9b5-8cc72ac0fdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301054018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1301054018
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1347681625
Short name T279
Test name
Test status
Simulation time 244616670 ps
CPU time 1.11 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 218252 kb
Host smart-c028572f-7332-4032-a641-f81722042ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347681625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1347681625
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.4012455388
Short name T13
Test name
Test status
Simulation time 123365330 ps
CPU time 0.76 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 200700 kb
Host smart-34ab6022-1fd4-4241-94b8-be17a3aa59ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012455388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.4012455388
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.843292817
Short name T311
Test name
Test status
Simulation time 1901833093 ps
CPU time 6.67 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:52 PM PDT 24
Peak memory 201004 kb
Host smart-a904a2d3-4494-4dab-8c71-b2cc69341c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843292817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.843292817
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3113301158
Short name T235
Test name
Test status
Simulation time 112072232 ps
CPU time 0.98 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 200836 kb
Host smart-0c9e627e-b755-484f-b71d-e2a59628dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113301158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3113301158
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.793479732
Short name T209
Test name
Test status
Simulation time 259357481 ps
CPU time 1.48 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 201016 kb
Host smart-b9c49021-89e2-4c72-bbd1-d45c4b1aeb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793479732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.793479732
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1308122372
Short name T184
Test name
Test status
Simulation time 1071960755 ps
CPU time 5.19 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:49 PM PDT 24
Peak memory 200984 kb
Host smart-69a2227a-5ddc-4b76-99b3-554e75ef5616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308122372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1308122372
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.386578730
Short name T236
Test name
Test status
Simulation time 129740585 ps
CPU time 1.74 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:47 PM PDT 24
Peak memory 209088 kb
Host smart-716f046d-709f-4cdf-ba93-4dd8a5bee43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386578730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.386578730
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1464638756
Short name T477
Test name
Test status
Simulation time 74623208 ps
CPU time 0.84 seconds
Started Mar 28 01:10:44 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 200708 kb
Host smart-f8e8150e-7e5d-4ad1-8826-2ebf4f6f18a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464638756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1464638756
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.498178363
Short name T369
Test name
Test status
Simulation time 68316507 ps
CPU time 0.79 seconds
Started Mar 28 01:10:59 PM PDT 24
Finished Mar 28 01:11:00 PM PDT 24
Peak memory 200696 kb
Host smart-ef772ff6-0935-4fb5-ae93-5840e12cc1d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498178363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.498178363
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1428207263
Short name T54
Test name
Test status
Simulation time 1220499396 ps
CPU time 5.58 seconds
Started Mar 28 01:10:46 PM PDT 24
Finished Mar 28 01:10:52 PM PDT 24
Peak memory 218512 kb
Host smart-e8e5a04c-dcf7-4ac6-9407-dcdabf26a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428207263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1428207263
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1437323414
Short name T481
Test name
Test status
Simulation time 244279547 ps
CPU time 1.06 seconds
Started Mar 28 01:10:42 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 218100 kb
Host smart-099c008d-8a4a-4f9b-9e9e-5f628f5d5112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437323414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1437323414
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2349657731
Short name T381
Test name
Test status
Simulation time 148319182 ps
CPU time 0.8 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 200632 kb
Host smart-ce9bbcca-7748-4cef-b703-708911c4cd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349657731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2349657731
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.681412986
Short name T267
Test name
Test status
Simulation time 1952833592 ps
CPU time 6.82 seconds
Started Mar 28 01:10:41 PM PDT 24
Finished Mar 28 01:10:48 PM PDT 24
Peak memory 201024 kb
Host smart-30c00644-7900-4280-bdbd-ef68baa53717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681412986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.681412986
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2805915569
Short name T449
Test name
Test status
Simulation time 107785298 ps
CPU time 1.02 seconds
Started Mar 28 01:10:46 PM PDT 24
Finished Mar 28 01:10:48 PM PDT 24
Peak memory 200796 kb
Host smart-739fb618-ed34-44c1-b3b1-7dacf04d32cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805915569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2805915569
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.346132508
Short name T360
Test name
Test status
Simulation time 242107194 ps
CPU time 1.46 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:45 PM PDT 24
Peak memory 200944 kb
Host smart-86c86c53-d9b1-4674-8117-f925c0ceadb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346132508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.346132508
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3432589103
Short name T136
Test name
Test status
Simulation time 1851538204 ps
CPU time 6.76 seconds
Started Mar 28 01:10:43 PM PDT 24
Finished Mar 28 01:10:50 PM PDT 24
Peak memory 201032 kb
Host smart-6263628c-94bc-48be-9b4f-01965b4d455d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432589103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3432589103
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1142669560
Short name T247
Test name
Test status
Simulation time 369993330 ps
CPU time 2.25 seconds
Started Mar 28 01:10:45 PM PDT 24
Finished Mar 28 01:10:47 PM PDT 24
Peak memory 200840 kb
Host smart-85957ec4-2acf-4490-be6a-f006ea3fd1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142669560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1142669560
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2795750795
Short name T57
Test name
Test status
Simulation time 107915920 ps
CPU time 0.96 seconds
Started Mar 28 01:10:46 PM PDT 24
Finished Mar 28 01:10:47 PM PDT 24
Peak memory 200792 kb
Host smart-cfc7b6b6-eff7-422c-9b22-a31a11072d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795750795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2795750795
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2153127938
Short name T316
Test name
Test status
Simulation time 76606694 ps
CPU time 0.78 seconds
Started Mar 28 01:11:02 PM PDT 24
Finished Mar 28 01:11:03 PM PDT 24
Peak memory 200728 kb
Host smart-9d00d60d-87b7-4981-a789-3683a3532a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153127938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2153127938
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3358983823
Short name T370
Test name
Test status
Simulation time 1226368354 ps
CPU time 5.18 seconds
Started Mar 28 01:10:59 PM PDT 24
Finished Mar 28 01:11:05 PM PDT 24
Peak memory 218456 kb
Host smart-0277048d-b33f-4437-88d5-f5d2cfcca740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358983823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3358983823
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2172607144
Short name T310
Test name
Test status
Simulation time 244194402 ps
CPU time 1.01 seconds
Started Mar 28 01:10:59 PM PDT 24
Finished Mar 28 01:11:00 PM PDT 24
Peak memory 218140 kb
Host smart-ac31bc3e-985b-4f25-b93c-42296943e9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172607144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2172607144
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.632631357
Short name T407
Test name
Test status
Simulation time 147746427 ps
CPU time 0.8 seconds
Started Mar 28 01:10:59 PM PDT 24
Finished Mar 28 01:11:00 PM PDT 24
Peak memory 200720 kb
Host smart-2834bf11-0587-4962-8229-7d800c85c510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632631357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.632631357
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.906082441
Short name T438
Test name
Test status
Simulation time 872325977 ps
CPU time 4.02 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:05 PM PDT 24
Peak memory 201024 kb
Host smart-48aad7e2-db0c-452a-8e25-1ef4d2f36d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906082441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.906082441
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.438810943
Short name T155
Test name
Test status
Simulation time 175120030 ps
CPU time 1.26 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:03 PM PDT 24
Peak memory 200828 kb
Host smart-67dc46d4-bc09-4c7d-bb50-470e9a099f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438810943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.438810943
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3091625036
Short name T286
Test name
Test status
Simulation time 113690278 ps
CPU time 1.15 seconds
Started Mar 28 01:10:59 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 200992 kb
Host smart-4d11230e-9493-48ec-9083-635c16970fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091625036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3091625036
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2458745150
Short name T167
Test name
Test status
Simulation time 307112931 ps
CPU time 1.46 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 200692 kb
Host smart-0c1eec52-446f-4e6a-b2f6-0e0ad767f54c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458745150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2458745150
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3230127
Short name T258
Test name
Test status
Simulation time 462404719 ps
CPU time 2.42 seconds
Started Mar 28 01:10:58 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 200900 kb
Host smart-a940b912-e35d-4704-b6fa-bbe704c19410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3230127
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.57878272
Short name T81
Test name
Test status
Simulation time 85785180 ps
CPU time 0.93 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:02 PM PDT 24
Peak memory 200840 kb
Host smart-5c098a68-a09c-4702-a795-2ea640a82c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57878272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.57878272
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2049466475
Short name T31
Test name
Test status
Simulation time 75487345 ps
CPU time 0.77 seconds
Started Mar 28 01:11:03 PM PDT 24
Finished Mar 28 01:11:04 PM PDT 24
Peak memory 200716 kb
Host smart-124e1dbb-1335-4314-8871-6dd726a900af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049466475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2049466475
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1582368637
Short name T62
Test name
Test status
Simulation time 2367254191 ps
CPU time 7.82 seconds
Started Mar 28 01:11:05 PM PDT 24
Finished Mar 28 01:11:13 PM PDT 24
Peak memory 218660 kb
Host smart-3d1ba830-8679-4d10-82bd-be07e20f2105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582368637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1582368637
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.117119963
Short name T402
Test name
Test status
Simulation time 245831236 ps
CPU time 1.04 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:08 PM PDT 24
Peak memory 218104 kb
Host smart-717051ef-9d76-4e78-a761-a54bbd5762d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117119963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.117119963
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1926456128
Short name T497
Test name
Test status
Simulation time 125907593 ps
CPU time 0.79 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 200668 kb
Host smart-5c6d33e5-e118-4d40-961d-0d58c5ea0825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926456128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1926456128
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.231084789
Short name T98
Test name
Test status
Simulation time 1676749906 ps
CPU time 6.82 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:08 PM PDT 24
Peak memory 201012 kb
Host smart-261a3e08-9393-4baf-b5aa-12f922a7f02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231084789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.231084789
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1566178183
Short name T386
Test name
Test status
Simulation time 102957795 ps
CPU time 0.97 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:02 PM PDT 24
Peak memory 200828 kb
Host smart-e5456c1a-313a-4885-86c6-b18356019034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566178183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1566178183
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2825749195
Short name T365
Test name
Test status
Simulation time 204898505 ps
CPU time 1.43 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:03 PM PDT 24
Peak memory 200916 kb
Host smart-12783d83-e414-4c8b-87ea-fc430a254add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825749195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2825749195
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2902669925
Short name T243
Test name
Test status
Simulation time 9706990343 ps
CPU time 30.99 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:32 PM PDT 24
Peak memory 209300 kb
Host smart-02356494-1701-4ad9-ac91-97ece613a599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902669925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2902669925
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.868825653
Short name T485
Test name
Test status
Simulation time 143446338 ps
CPU time 1.84 seconds
Started Mar 28 01:11:04 PM PDT 24
Finished Mar 28 01:11:06 PM PDT 24
Peak memory 200772 kb
Host smart-781d3e84-ce3e-42b8-b5cb-975f179c1c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868825653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.868825653
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3341316686
Short name T149
Test name
Test status
Simulation time 94664111 ps
CPU time 0.86 seconds
Started Mar 28 01:11:02 PM PDT 24
Finished Mar 28 01:11:03 PM PDT 24
Peak memory 200852 kb
Host smart-48832c4d-131f-4284-bddb-5aadcf52daac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341316686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3341316686
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1154520177
Short name T350
Test name
Test status
Simulation time 72146946 ps
CPU time 0.73 seconds
Started Mar 28 01:11:05 PM PDT 24
Finished Mar 28 01:11:06 PM PDT 24
Peak memory 200724 kb
Host smart-b46df187-41ca-418b-8104-d6348b0f283e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154520177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1154520177
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1640687071
Short name T428
Test name
Test status
Simulation time 1889464518 ps
CPU time 6.87 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:13 PM PDT 24
Peak memory 222536 kb
Host smart-79b9c47d-9eab-44ea-a461-ee49162e299c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640687071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1640687071
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.325288797
Short name T1
Test name
Test status
Simulation time 244279307 ps
CPU time 1.09 seconds
Started Mar 28 01:11:03 PM PDT 24
Finished Mar 28 01:11:04 PM PDT 24
Peak memory 217980 kb
Host smart-9448d09c-b96d-4070-aa37-f7504044a4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325288797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.325288797
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2061650567
Short name T488
Test name
Test status
Simulation time 117063517 ps
CPU time 0.8 seconds
Started Mar 28 01:11:03 PM PDT 24
Finished Mar 28 01:11:04 PM PDT 24
Peak memory 200708 kb
Host smart-b1794e3a-bff0-43d7-984f-6cea345610e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061650567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2061650567
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1036636056
Short name T221
Test name
Test status
Simulation time 1000797364 ps
CPU time 4.93 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:12 PM PDT 24
Peak memory 201028 kb
Host smart-30a636eb-5bbc-4fd8-95e1-df6ba484444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036636056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1036636056
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.809934475
Short name T371
Test name
Test status
Simulation time 168035866 ps
CPU time 1.11 seconds
Started Mar 28 01:11:03 PM PDT 24
Finished Mar 28 01:11:05 PM PDT 24
Peak memory 200716 kb
Host smart-285ca1ed-53b0-4fc2-860b-acd4c84b0692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809934475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.809934475
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1730791469
Short name T459
Test name
Test status
Simulation time 111162114 ps
CPU time 1.19 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 201036 kb
Host smart-c55434a9-3986-4540-8da1-7d711c0dbb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730791469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1730791469
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3188256034
Short name T143
Test name
Test status
Simulation time 150240726 ps
CPU time 1.9 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:09 PM PDT 24
Peak memory 200856 kb
Host smart-569339c9-5046-4d2d-95ab-eb8924e47462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188256034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3188256034
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3987785930
Short name T418
Test name
Test status
Simulation time 99413165 ps
CPU time 0.95 seconds
Started Mar 28 01:11:02 PM PDT 24
Finished Mar 28 01:11:03 PM PDT 24
Peak memory 200804 kb
Host smart-f6b213c5-9291-41f1-9d0e-3cdac29a393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987785930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3987785930
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2357384380
Short name T423
Test name
Test status
Simulation time 76162231 ps
CPU time 0.79 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:08 PM PDT 24
Peak memory 200732 kb
Host smart-5e3903b4-02a1-4605-99ad-7dccb31759c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357384380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2357384380
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1852690041
Short name T392
Test name
Test status
Simulation time 2364599711 ps
CPU time 8.83 seconds
Started Mar 28 01:11:05 PM PDT 24
Finished Mar 28 01:11:14 PM PDT 24
Peak memory 218700 kb
Host smart-dce9a95c-41d5-4ca0-84a3-ff846c6fe2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852690041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1852690041
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3369582800
Short name T422
Test name
Test status
Simulation time 244863702 ps
CPU time 1.09 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:08 PM PDT 24
Peak memory 218136 kb
Host smart-5a826685-8617-4c4a-a9ba-ba96cd1fc03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369582800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3369582800
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2929189726
Short name T394
Test name
Test status
Simulation time 110656436 ps
CPU time 0.74 seconds
Started Mar 28 01:11:03 PM PDT 24
Finished Mar 28 01:11:04 PM PDT 24
Peak memory 200584 kb
Host smart-c293050a-f36a-4d17-b67b-add4e4ffd8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929189726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2929189726
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1810067361
Short name T19
Test name
Test status
Simulation time 1817960052 ps
CPU time 6.37 seconds
Started Mar 28 01:11:03 PM PDT 24
Finished Mar 28 01:11:10 PM PDT 24
Peak memory 201008 kb
Host smart-490931ed-e36f-4e6e-9bcb-43600626a91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810067361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1810067361
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.172651151
Short name T456
Test name
Test status
Simulation time 107271926 ps
CPU time 1.01 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:09 PM PDT 24
Peak memory 200860 kb
Host smart-a8a58532-c05d-45d5-8257-da1e498b4c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172651151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.172651151
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1241658298
Short name T415
Test name
Test status
Simulation time 190321854 ps
CPU time 1.35 seconds
Started Mar 28 01:11:04 PM PDT 24
Finished Mar 28 01:11:05 PM PDT 24
Peak memory 201000 kb
Host smart-c1cc7eea-cb4b-4c23-967b-9e7a5a04fb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241658298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1241658298
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3421800782
Short name T105
Test name
Test status
Simulation time 9633811910 ps
CPU time 31.13 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:39 PM PDT 24
Peak memory 209360 kb
Host smart-db78065a-3544-41a0-8436-102c9e1d17f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421800782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3421800782
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2122343059
Short name T8
Test name
Test status
Simulation time 131276514 ps
CPU time 1.68 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:09 PM PDT 24
Peak memory 209144 kb
Host smart-b714f24a-954a-4f91-b0be-408f95ab4698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122343059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2122343059
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1154601690
Short name T237
Test name
Test status
Simulation time 136954669 ps
CPU time 1.1 seconds
Started Mar 28 01:11:04 PM PDT 24
Finished Mar 28 01:11:05 PM PDT 24
Peak memory 200828 kb
Host smart-cbbeb721-f33f-49e8-8a14-bed2b6ce3469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154601690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1154601690
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.612161942
Short name T2
Test name
Test status
Simulation time 70748277 ps
CPU time 0.76 seconds
Started Mar 28 01:09:15 PM PDT 24
Finished Mar 28 01:09:16 PM PDT 24
Peak memory 200680 kb
Host smart-6a21300f-44d3-4f91-8971-0e7505fac708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612161942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.612161942
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.13433201
Short name T382
Test name
Test status
Simulation time 2343416452 ps
CPU time 8.48 seconds
Started Mar 28 01:09:15 PM PDT 24
Finished Mar 28 01:09:24 PM PDT 24
Peak memory 218756 kb
Host smart-8deaf618-9f7c-46ff-8e7e-7e3db2170b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13433201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.13433201
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3854951361
Short name T509
Test name
Test status
Simulation time 243610268 ps
CPU time 1.1 seconds
Started Mar 28 01:09:13 PM PDT 24
Finished Mar 28 01:09:14 PM PDT 24
Peak memory 218020 kb
Host smart-e0570b55-460a-4571-891c-18ddd1044c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854951361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3854951361
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2882445621
Short name T156
Test name
Test status
Simulation time 206444286 ps
CPU time 0.93 seconds
Started Mar 28 01:09:00 PM PDT 24
Finished Mar 28 01:09:01 PM PDT 24
Peak memory 200636 kb
Host smart-552cb4f3-3948-4643-8c89-4a8187e7c53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882445621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2882445621
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2284577159
Short name T436
Test name
Test status
Simulation time 977923320 ps
CPU time 4.77 seconds
Started Mar 28 01:09:15 PM PDT 24
Finished Mar 28 01:09:20 PM PDT 24
Peak memory 201040 kb
Host smart-5004015d-6a57-46ce-9a86-aa05cda059a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284577159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2284577159
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2663645800
Short name T74
Test name
Test status
Simulation time 17066618093 ps
CPU time 25.46 seconds
Started Mar 28 01:09:23 PM PDT 24
Finished Mar 28 01:09:48 PM PDT 24
Peak memory 217780 kb
Host smart-fd7af15e-962f-4953-ad4c-08e93538f3aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663645800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2663645800
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2615245122
Short name T11
Test name
Test status
Simulation time 184281596 ps
CPU time 1.14 seconds
Started Mar 28 01:09:22 PM PDT 24
Finished Mar 28 01:09:23 PM PDT 24
Peak memory 200836 kb
Host smart-3afef470-3689-45e4-881d-20d66ce0912b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615245122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2615245122
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.177373656
Short name T466
Test name
Test status
Simulation time 187162284 ps
CPU time 1.29 seconds
Started Mar 28 01:08:59 PM PDT 24
Finished Mar 28 01:09:01 PM PDT 24
Peak memory 201008 kb
Host smart-7cc436ea-426a-4467-a16c-666b74289fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177373656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.177373656
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3699511314
Short name T329
Test name
Test status
Simulation time 10341066772 ps
CPU time 34.84 seconds
Started Mar 28 01:09:16 PM PDT 24
Finished Mar 28 01:09:51 PM PDT 24
Peak memory 201112 kb
Host smart-42f54241-95a7-4903-b901-ef5f829128d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699511314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3699511314
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2379445242
Short name T200
Test name
Test status
Simulation time 148611022 ps
CPU time 1.77 seconds
Started Mar 28 01:09:17 PM PDT 24
Finished Mar 28 01:09:19 PM PDT 24
Peak memory 200836 kb
Host smart-b6109349-a764-4211-9773-ed5446bb1d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379445242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2379445242
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2024606882
Short name T434
Test name
Test status
Simulation time 96035845 ps
CPU time 0.82 seconds
Started Mar 28 01:09:16 PM PDT 24
Finished Mar 28 01:09:17 PM PDT 24
Peak memory 200860 kb
Host smart-072cdf74-e164-4cc7-9f0a-2a4f1a1beb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024606882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2024606882
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2748584633
Short name T4
Test name
Test status
Simulation time 73779022 ps
CPU time 0.76 seconds
Started Mar 28 01:10:58 PM PDT 24
Finished Mar 28 01:10:59 PM PDT 24
Peak memory 200708 kb
Host smart-aa67be56-231f-4ff1-bd85-543a6b9278fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748584633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2748584633
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4155192462
Short name T41
Test name
Test status
Simulation time 1219115113 ps
CPU time 5.48 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:07 PM PDT 24
Peak memory 218532 kb
Host smart-3f87ba98-4819-4726-8bae-8d220e3956f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155192462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4155192462
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.4261343254
Short name T437
Test name
Test status
Simulation time 243947681 ps
CPU time 1.08 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:03 PM PDT 24
Peak memory 218132 kb
Host smart-3b18749f-9d9c-4304-a8a8-3c9914f09b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261343254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.4261343254
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.288495391
Short name T172
Test name
Test status
Simulation time 218368502 ps
CPU time 0.86 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 200708 kb
Host smart-3a7f8204-12b0-403d-85c3-a0f02eef72a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288495391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.288495391
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.660543232
Short name T352
Test name
Test status
Simulation time 1576584701 ps
CPU time 6.15 seconds
Started Mar 28 01:11:05 PM PDT 24
Finished Mar 28 01:11:12 PM PDT 24
Peak memory 201056 kb
Host smart-b48982c4-060b-40be-8b72-b47533cd2816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660543232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.660543232
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3690942073
Short name T170
Test name
Test status
Simulation time 151618564 ps
CPU time 1.1 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:02 PM PDT 24
Peak memory 200844 kb
Host smart-28ca5491-3de8-49fa-9b5e-9c17e6f59674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690942073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3690942073
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3134758696
Short name T276
Test name
Test status
Simulation time 117612744 ps
CPU time 1.25 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:08 PM PDT 24
Peak memory 200984 kb
Host smart-6a610992-7c1e-4a25-be6d-ebca0b989689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134758696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3134758696
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1468172990
Short name T270
Test name
Test status
Simulation time 6728175351 ps
CPU time 30.01 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:31 PM PDT 24
Peak memory 209356 kb
Host smart-c887e575-b74b-47b3-bc83-2bfe53557813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468172990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1468172990
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2008250105
Short name T133
Test name
Test status
Simulation time 318492565 ps
CPU time 1.92 seconds
Started Mar 28 01:11:05 PM PDT 24
Finished Mar 28 01:11:07 PM PDT 24
Peak memory 200892 kb
Host smart-50a162ef-5496-48db-b8f1-d09684502dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008250105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2008250105
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2758821455
Short name T175
Test name
Test status
Simulation time 71416074 ps
CPU time 0.79 seconds
Started Mar 28 01:11:02 PM PDT 24
Finished Mar 28 01:11:03 PM PDT 24
Peak memory 200776 kb
Host smart-27b31b3c-0cd2-484c-be00-6df4c1a7762e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758821455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2758821455
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.430084415
Short name T154
Test name
Test status
Simulation time 89241354 ps
CPU time 0.84 seconds
Started Mar 28 01:10:59 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 200652 kb
Host smart-aac5a29b-bc05-4669-ac4a-ad1b923b3f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430084415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.430084415
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3153017746
Short name T471
Test name
Test status
Simulation time 1228878548 ps
CPU time 5.65 seconds
Started Mar 28 01:10:58 PM PDT 24
Finished Mar 28 01:11:04 PM PDT 24
Peak memory 222588 kb
Host smart-0d046c4e-1fb7-4f7a-9ebe-7c092d23d92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153017746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3153017746
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1652290154
Short name T322
Test name
Test status
Simulation time 244698758 ps
CPU time 1.03 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:02 PM PDT 24
Peak memory 218096 kb
Host smart-b457013f-771a-40ac-bbe8-2dcd5db034fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652290154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1652290154
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1901669728
Short name T248
Test name
Test status
Simulation time 188194591 ps
CPU time 0.91 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 200752 kb
Host smart-e4034aa6-462e-4216-b730-0d35366e6603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901669728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1901669728
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.660226397
Short name T351
Test name
Test status
Simulation time 714365007 ps
CPU time 3.93 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:05 PM PDT 24
Peak memory 201004 kb
Host smart-96cd83c1-f1b2-4d11-8015-54177f9b85f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660226397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.660226397
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2477210273
Short name T341
Test name
Test status
Simulation time 168323233 ps
CPU time 1.11 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 200788 kb
Host smart-f9ad2e84-d43c-45e2-b994-3110ffb4fc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477210273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2477210273
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.991713584
Short name T197
Test name
Test status
Simulation time 240357426 ps
CPU time 1.4 seconds
Started Mar 28 01:10:57 PM PDT 24
Finished Mar 28 01:10:59 PM PDT 24
Peak memory 201024 kb
Host smart-76665664-e57f-4e20-b581-8db8c521a60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991713584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.991713584
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1655011314
Short name T84
Test name
Test status
Simulation time 1426165461 ps
CPU time 5.69 seconds
Started Mar 28 01:10:58 PM PDT 24
Finished Mar 28 01:11:04 PM PDT 24
Peak memory 201052 kb
Host smart-b01bfef4-054f-4e6c-81c1-246112ce5065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655011314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1655011314
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1633969598
Short name T379
Test name
Test status
Simulation time 330320756 ps
CPU time 2.18 seconds
Started Mar 28 01:10:58 PM PDT 24
Finished Mar 28 01:11:00 PM PDT 24
Peak memory 200808 kb
Host smart-684022e0-ab07-4005-a505-6b41b0743018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633969598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1633969598
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1805721728
Short name T90
Test name
Test status
Simulation time 154736074 ps
CPU time 1.25 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 201032 kb
Host smart-7735b113-77e7-442f-bcca-1d0582264d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805721728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1805721728
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3108796876
Short name T334
Test name
Test status
Simulation time 84533602 ps
CPU time 0.79 seconds
Started Mar 28 01:11:17 PM PDT 24
Finished Mar 28 01:11:18 PM PDT 24
Peak memory 200708 kb
Host smart-8c2ac1a4-ce46-47c0-962c-626e0b245642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108796876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3108796876
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.169919185
Short name T298
Test name
Test status
Simulation time 2361998100 ps
CPU time 7.88 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:15 PM PDT 24
Peak memory 218368 kb
Host smart-6b1662e6-dc40-408a-989a-0fc28ae90268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169919185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.169919185
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4199817165
Short name T367
Test name
Test status
Simulation time 243743403 ps
CPU time 1.16 seconds
Started Mar 28 01:11:07 PM PDT 24
Finished Mar 28 01:11:08 PM PDT 24
Peak memory 218256 kb
Host smart-1e5ae6ed-f499-4e9a-a3a9-5223a987cc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199817165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4199817165
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.812798572
Short name T425
Test name
Test status
Simulation time 73108902 ps
CPU time 0.73 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:02 PM PDT 24
Peak memory 200652 kb
Host smart-8a732efc-f6de-4ff6-8dfb-cdde7b3e30b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812798572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.812798572
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2953779645
Short name T234
Test name
Test status
Simulation time 996454622 ps
CPU time 4.82 seconds
Started Mar 28 01:11:00 PM PDT 24
Finished Mar 28 01:11:05 PM PDT 24
Peak memory 201056 kb
Host smart-0ada0f63-234d-42c0-a67f-bae10d5cf8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953779645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2953779645
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1840293503
Short name T513
Test name
Test status
Simulation time 183359945 ps
CPU time 1.18 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:02 PM PDT 24
Peak memory 200860 kb
Host smart-a70b2fb0-b283-4acf-95cc-7c36fc2149dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840293503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1840293503
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1830881199
Short name T538
Test name
Test status
Simulation time 203698887 ps
CPU time 1.31 seconds
Started Mar 28 01:10:58 PM PDT 24
Finished Mar 28 01:10:59 PM PDT 24
Peak memory 201036 kb
Host smart-0b3df1fd-3edc-40aa-ac69-e3b413b0bed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830881199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1830881199
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.862199357
Short name T419
Test name
Test status
Simulation time 5642120343 ps
CPU time 26.2 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:47 PM PDT 24
Peak memory 201140 kb
Host smart-c4808fb7-78f1-450d-8160-2c59d4a5041a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862199357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.862199357
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2482356247
Short name T523
Test name
Test status
Simulation time 465952652 ps
CPU time 2.54 seconds
Started Mar 28 01:11:01 PM PDT 24
Finished Mar 28 01:11:04 PM PDT 24
Peak memory 200912 kb
Host smart-16b146bb-ff18-4278-a698-c7336af21baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482356247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2482356247
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1623022526
Short name T461
Test name
Test status
Simulation time 138689596 ps
CPU time 0.97 seconds
Started Mar 28 01:10:59 PM PDT 24
Finished Mar 28 01:11:00 PM PDT 24
Peak memory 200848 kb
Host smart-b0497838-91af-4c54-a3bd-b90f07f6af16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623022526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1623022526
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3290170493
Short name T453
Test name
Test status
Simulation time 78904319 ps
CPU time 0.76 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200752 kb
Host smart-1ffd1eff-1939-4374-a7be-135fadbc21fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290170493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3290170493
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.4124949176
Short name T231
Test name
Test status
Simulation time 244455062 ps
CPU time 1.05 seconds
Started Mar 28 01:11:17 PM PDT 24
Finished Mar 28 01:11:18 PM PDT 24
Peak memory 218068 kb
Host smart-fdc09566-b692-4839-b5a4-7dcad663ada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124949176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.4124949176
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2172786740
Short name T166
Test name
Test status
Simulation time 136534171 ps
CPU time 0.78 seconds
Started Mar 28 01:11:18 PM PDT 24
Finished Mar 28 01:11:19 PM PDT 24
Peak memory 200708 kb
Host smart-354ef116-d184-4249-b3bc-b4ad4cc88045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172786740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2172786740
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3077082128
Short name T541
Test name
Test status
Simulation time 1247499706 ps
CPU time 5.08 seconds
Started Mar 28 01:11:18 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 201056 kb
Host smart-57b759e6-6ea4-4138-b998-5c7244c426b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077082128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3077082128
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.163784456
Short name T355
Test name
Test status
Simulation time 160901926 ps
CPU time 1.16 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 200800 kb
Host smart-c8f36f1a-e4e3-41d9-9a38-46b5cfeab4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163784456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.163784456
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.693636214
Short name T314
Test name
Test status
Simulation time 118818178 ps
CPU time 1.18 seconds
Started Mar 28 01:11:16 PM PDT 24
Finished Mar 28 01:11:17 PM PDT 24
Peak memory 201024 kb
Host smart-926fba82-3500-41f6-aaf5-d70cf0ef17ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693636214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.693636214
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1501297534
Short name T218
Test name
Test status
Simulation time 3710013097 ps
CPU time 14.61 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:35 PM PDT 24
Peak memory 209324 kb
Host smart-c4815e94-2c71-41a0-b471-1c3726d54a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501297534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1501297534
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3964283112
Short name T142
Test name
Test status
Simulation time 137665608 ps
CPU time 1.67 seconds
Started Mar 28 01:11:17 PM PDT 24
Finished Mar 28 01:11:19 PM PDT 24
Peak memory 200880 kb
Host smart-1e1588ab-ea26-4526-9f6c-916a3e2cd842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964283112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3964283112
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1948882056
Short name T440
Test name
Test status
Simulation time 242906804 ps
CPU time 1.33 seconds
Started Mar 28 01:11:22 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 200812 kb
Host smart-3f298495-e9c2-43b9-868e-81e44403b914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948882056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1948882056
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1781110874
Short name T252
Test name
Test status
Simulation time 76407616 ps
CPU time 0.82 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200612 kb
Host smart-e63207b0-d09a-4c60-82df-f86d26e7dad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781110874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1781110874
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.322208246
Short name T468
Test name
Test status
Simulation time 1218116192 ps
CPU time 5.45 seconds
Started Mar 28 01:11:18 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 217984 kb
Host smart-a238f536-35f1-4511-b62b-864c85d5dfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322208246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.322208246
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2178019724
Short name T280
Test name
Test status
Simulation time 244614142 ps
CPU time 1.08 seconds
Started Mar 28 01:11:22 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 218220 kb
Host smart-260207f6-4dbf-4046-96a4-073ed96eb8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178019724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2178019724
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.836655219
Short name T159
Test name
Test status
Simulation time 119373117 ps
CPU time 0.85 seconds
Started Mar 28 01:11:22 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 200652 kb
Host smart-fb910c06-4789-4d33-8f11-1c79420b16a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836655219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.836655219
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2871022178
Short name T281
Test name
Test status
Simulation time 1013914564 ps
CPU time 4.87 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:27 PM PDT 24
Peak memory 200992 kb
Host smart-dbf3a3de-dfaa-4009-8b33-b653e35ae922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871022178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2871022178
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1021518378
Short name T230
Test name
Test status
Simulation time 146484287 ps
CPU time 1.05 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200880 kb
Host smart-c5968dea-d1b6-4148-bef0-bcb9b956bd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021518378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1021518378
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2878163724
Short name T299
Test name
Test status
Simulation time 253163763 ps
CPU time 1.7 seconds
Started Mar 28 01:11:22 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 201008 kb
Host smart-c52ee712-18b1-4147-8201-997846742ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878163724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2878163724
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2332243508
Short name T51
Test name
Test status
Simulation time 6357292929 ps
CPU time 21.4 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 201124 kb
Host smart-ca158077-250c-44cf-a368-429c81fb8485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332243508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2332243508
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2740106639
Short name T21
Test name
Test status
Simulation time 256369262 ps
CPU time 1.73 seconds
Started Mar 28 01:11:22 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 200892 kb
Host smart-a0aee659-7fb4-4bd8-8d4d-296de459b2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740106639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2740106639
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1967894930
Short name T206
Test name
Test status
Simulation time 176398856 ps
CPU time 1.05 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 200828 kb
Host smart-ca0e2cfb-fe82-4069-962a-6ffd3e19be2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967894930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1967894930
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2169631829
Short name T443
Test name
Test status
Simulation time 75456103 ps
CPU time 0.79 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200648 kb
Host smart-68dc64a7-11cb-44ec-8d9b-1b1f07de5be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169631829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2169631829
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3946429680
Short name T390
Test name
Test status
Simulation time 2348088557 ps
CPU time 7.76 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:30 PM PDT 24
Peak memory 218420 kb
Host smart-51a58b04-2855-4e9c-92c0-f0d3650628a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946429680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3946429680
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2605180960
Short name T473
Test name
Test status
Simulation time 243996637 ps
CPU time 1.04 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 218168 kb
Host smart-64e3a54e-9206-43a0-88d1-b1834ba1a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605180960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2605180960
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.141182749
Short name T28
Test name
Test status
Simulation time 180369596 ps
CPU time 0.88 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200648 kb
Host smart-3d5129cc-2df2-46b3-a033-bda079620064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141182749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.141182749
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2086062668
Short name T106
Test name
Test status
Simulation time 1702592584 ps
CPU time 6.37 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:27 PM PDT 24
Peak memory 200896 kb
Host smart-e92ef979-839c-41bf-932e-ca7ae0a2ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086062668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2086062668
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4254761303
Short name T478
Test name
Test status
Simulation time 168151670 ps
CPU time 1.13 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200856 kb
Host smart-5dc6ebb7-eaab-48ab-8ddc-4d0b751d6b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254761303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4254761303
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.4234733254
Short name T540
Test name
Test status
Simulation time 226787436 ps
CPU time 1.44 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:22 PM PDT 24
Peak memory 200888 kb
Host smart-d3dadf96-2da9-45f2-90de-e094a92834ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234733254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4234733254
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2811979641
Short name T358
Test name
Test status
Simulation time 841739965 ps
CPU time 4.17 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 200960 kb
Host smart-7672554f-81db-4130-89b6-3b00775f1ee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811979641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2811979641
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1398984953
Short name T504
Test name
Test status
Simulation time 129198019 ps
CPU time 1.65 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:22 PM PDT 24
Peak memory 200944 kb
Host smart-6b71c8e7-3d98-4eb1-b7b0-a2e6ddde4455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398984953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1398984953
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.907905974
Short name T349
Test name
Test status
Simulation time 224707929 ps
CPU time 1.35 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 200700 kb
Host smart-f45e590e-b11b-42c2-8fce-89283428b860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907905974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.907905974
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2843410489
Short name T224
Test name
Test status
Simulation time 68239577 ps
CPU time 0.74 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200696 kb
Host smart-9f131502-9126-4841-bf6c-001ddb0902ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843410489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2843410489
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.536503403
Short name T44
Test name
Test status
Simulation time 2381432872 ps
CPU time 8.28 seconds
Started Mar 28 01:11:22 PM PDT 24
Finished Mar 28 01:11:31 PM PDT 24
Peak memory 230888 kb
Host smart-cdedfd7b-9056-4558-84c3-f2ac0c47421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536503403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.536503403
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3928094977
Short name T269
Test name
Test status
Simulation time 243526976 ps
CPU time 1.05 seconds
Started Mar 28 01:11:17 PM PDT 24
Finished Mar 28 01:11:19 PM PDT 24
Peak memory 218088 kb
Host smart-f943ff31-9604-4840-9a9e-bfc3c16a0c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928094977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3928094977
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3714386340
Short name T259
Test name
Test status
Simulation time 160612073 ps
CPU time 0.9 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 200728 kb
Host smart-7da9b571-c039-41ef-8b9e-7163c2536bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714386340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3714386340
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.387814785
Short name T130
Test name
Test status
Simulation time 1778868699 ps
CPU time 6.37 seconds
Started Mar 28 01:11:22 PM PDT 24
Finished Mar 28 01:11:29 PM PDT 24
Peak memory 200884 kb
Host smart-88b8e5ac-31f2-49f9-b695-84fcfd4b6602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387814785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.387814785
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.730084182
Short name T183
Test name
Test status
Simulation time 175287761 ps
CPU time 1.12 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200828 kb
Host smart-71ffa4bc-3a2a-4a3f-8c27-0b012f9cbdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730084182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.730084182
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2636587827
Short name T376
Test name
Test status
Simulation time 118576858 ps
CPU time 1.13 seconds
Started Mar 28 01:11:18 PM PDT 24
Finished Mar 28 01:11:20 PM PDT 24
Peak memory 200988 kb
Host smart-b1f34a3e-bbb8-45bb-81ed-54f43e766a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636587827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2636587827
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3373729790
Short name T219
Test name
Test status
Simulation time 212997707 ps
CPU time 1.31 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 200856 kb
Host smart-d7e7a0c7-5327-49db-bbd6-9d4102b324a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373729790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3373729790
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2524817259
Short name T217
Test name
Test status
Simulation time 118396995 ps
CPU time 1.44 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:22 PM PDT 24
Peak memory 200896 kb
Host smart-4a66a54d-d664-4e5e-91fb-3b29a1fefbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524817259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2524817259
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1791532461
Short name T145
Test name
Test status
Simulation time 111122882 ps
CPU time 0.98 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200804 kb
Host smart-48bffed8-df32-411f-ab9c-5516aef546ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791532461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1791532461
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2363792361
Short name T188
Test name
Test status
Simulation time 69373209 ps
CPU time 0.78 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200712 kb
Host smart-11a594e5-4333-4ca1-bcc3-8e090bdb0e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363792361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2363792361
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.341774187
Short name T35
Test name
Test status
Simulation time 1886795278 ps
CPU time 7.79 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:30 PM PDT 24
Peak memory 222576 kb
Host smart-0ee7c01b-6b5d-4feb-8bd2-4ece7c10b11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341774187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.341774187
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1608659949
Short name T228
Test name
Test status
Simulation time 246376074 ps
CPU time 1.01 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 217932 kb
Host smart-89fb968e-bcbe-4753-9fd5-83de09ab866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608659949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1608659949
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.201825469
Short name T499
Test name
Test status
Simulation time 188109117 ps
CPU time 0.91 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:21 PM PDT 24
Peak memory 200716 kb
Host smart-b67c92f3-4aff-4752-b8ed-491c87597695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201825469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.201825469
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3474420015
Short name T318
Test name
Test status
Simulation time 1503834406 ps
CPU time 5.95 seconds
Started Mar 28 01:11:22 PM PDT 24
Finished Mar 28 01:11:28 PM PDT 24
Peak memory 201008 kb
Host smart-5f6b602f-5128-44cb-9c39-8d487398be3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474420015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3474420015
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1044666321
Short name T460
Test name
Test status
Simulation time 114115407 ps
CPU time 0.98 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 200824 kb
Host smart-e0179003-5378-403e-8495-f6a1922b8f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044666321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1044666321
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2107236226
Short name T375
Test name
Test status
Simulation time 246696254 ps
CPU time 1.44 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:22 PM PDT 24
Peak memory 201040 kb
Host smart-c2870f4c-3169-4fe7-825e-6a6a525ed5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107236226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2107236226
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.173693969
Short name T464
Test name
Test status
Simulation time 3741318168 ps
CPU time 13.05 seconds
Started Mar 28 01:11:18 PM PDT 24
Finished Mar 28 01:11:32 PM PDT 24
Peak memory 200960 kb
Host smart-6b11ede1-efc0-4370-aa6c-886a3dda2119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173693969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.173693969
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.191779569
Short name T462
Test name
Test status
Simulation time 365360204 ps
CPU time 2.02 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 200896 kb
Host smart-513a5f01-533a-4d52-b098-accdc1c0aad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191779569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.191779569
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3109510373
Short name T338
Test name
Test status
Simulation time 133034584 ps
CPU time 0.96 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 200804 kb
Host smart-13e996eb-9bc1-4071-999c-2e86928e9e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109510373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3109510373
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1358920149
Short name T361
Test name
Test status
Simulation time 55579895 ps
CPU time 0.7 seconds
Started Mar 28 01:11:31 PM PDT 24
Finished Mar 28 01:11:33 PM PDT 24
Peak memory 200720 kb
Host smart-ed558485-fea5-4154-bfbf-449f877471ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358920149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1358920149
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3824695494
Short name T406
Test name
Test status
Simulation time 1224742081 ps
CPU time 5.37 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:26 PM PDT 24
Peak memory 222580 kb
Host smart-2173983b-f4e1-44ac-8aff-fd5ce44aa372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824695494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3824695494
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3668358751
Short name T408
Test name
Test status
Simulation time 245537543 ps
CPU time 1.04 seconds
Started Mar 28 01:11:35 PM PDT 24
Finished Mar 28 01:11:37 PM PDT 24
Peak memory 218192 kb
Host smart-9c987ec7-1327-47f2-b8a5-b0e1477efc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668358751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3668358751
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3291568198
Short name T304
Test name
Test status
Simulation time 111743849 ps
CPU time 0.78 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 200692 kb
Host smart-e1ac73e1-3d44-4d13-b656-ea47e835daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291568198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3291568198
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1175919992
Short name T20
Test name
Test status
Simulation time 1543627978 ps
CPU time 6.12 seconds
Started Mar 28 01:11:19 PM PDT 24
Finished Mar 28 01:11:26 PM PDT 24
Peak memory 201008 kb
Host smart-ab1b3b84-375d-4df6-b975-80224bfd311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175919992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1175919992
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1341079042
Short name T253
Test name
Test status
Simulation time 185404308 ps
CPU time 1.15 seconds
Started Mar 28 01:11:18 PM PDT 24
Finished Mar 28 01:11:19 PM PDT 24
Peak memory 200752 kb
Host smart-2f0fc6f0-d9c3-49dd-8989-b5c3742a6059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341079042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1341079042
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2513178329
Short name T532
Test name
Test status
Simulation time 123038830 ps
CPU time 1.19 seconds
Started Mar 28 01:11:21 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 200984 kb
Host smart-c3b431df-5716-4d24-8e1d-62938a04a526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513178329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2513178329
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1639368424
Short name T204
Test name
Test status
Simulation time 948579155 ps
CPU time 4.7 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 209264 kb
Host smart-7ad05ff8-870c-4cfd-a79e-d83deee1a6eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639368424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1639368424
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4260181796
Short name T158
Test name
Test status
Simulation time 368736923 ps
CPU time 2.26 seconds
Started Mar 28 01:11:20 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 200932 kb
Host smart-890397ad-bf4a-48d2-b782-8ec49a6d6513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260181796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4260181796
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2814752426
Short name T216
Test name
Test status
Simulation time 147329359 ps
CPU time 1.15 seconds
Started Mar 28 01:11:22 PM PDT 24
Finished Mar 28 01:11:24 PM PDT 24
Peak memory 200812 kb
Host smart-337232cd-daed-4f41-9b22-1e09f4fec649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814752426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2814752426
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2365282799
Short name T257
Test name
Test status
Simulation time 64069440 ps
CPU time 0.81 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200680 kb
Host smart-1845f08e-f053-4b68-8c74-d8ab47aef7e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365282799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2365282799
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2759650421
Short name T45
Test name
Test status
Simulation time 1899214086 ps
CPU time 7.52 seconds
Started Mar 28 01:11:39 PM PDT 24
Finished Mar 28 01:11:46 PM PDT 24
Peak memory 217988 kb
Host smart-b48a8107-180d-4d9a-bbbc-12688258c726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759650421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2759650421
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3062093091
Short name T187
Test name
Test status
Simulation time 243941377 ps
CPU time 1.17 seconds
Started Mar 28 01:11:41 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 218268 kb
Host smart-658208af-cb44-47e5-b27f-91f5600927c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062093091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3062093091
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.355131271
Short name T421
Test name
Test status
Simulation time 132981053 ps
CPU time 0.78 seconds
Started Mar 28 01:11:32 PM PDT 24
Finished Mar 28 01:11:34 PM PDT 24
Peak memory 200700 kb
Host smart-1aec1bf7-2089-4487-9489-54ce801bb497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355131271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.355131271
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1018162773
Short name T15
Test name
Test status
Simulation time 813284024 ps
CPU time 4.24 seconds
Started Mar 28 01:11:38 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 200972 kb
Host smart-66ee221d-f979-4da4-b04d-f7aee887f1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018162773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1018162773
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2933498265
Short name T61
Test name
Test status
Simulation time 191607540 ps
CPU time 1.28 seconds
Started Mar 28 01:11:31 PM PDT 24
Finished Mar 28 01:11:33 PM PDT 24
Peak memory 200856 kb
Host smart-1b99449f-1d45-4b63-aa82-65ae7396f645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933498265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2933498265
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1686651992
Short name T356
Test name
Test status
Simulation time 199831932 ps
CPU time 1.39 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 201016 kb
Host smart-0c558873-d7dd-4e79-94fe-99fbe2b7cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686651992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1686651992
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3798810523
Short name T313
Test name
Test status
Simulation time 2228541883 ps
CPU time 10.78 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:11:44 PM PDT 24
Peak memory 200992 kb
Host smart-8c7cd51c-6537-4057-9f45-50dab84be629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798810523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3798810523
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2132104273
Short name T332
Test name
Test status
Simulation time 373787423 ps
CPU time 2.31 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:39 PM PDT 24
Peak memory 200880 kb
Host smart-26a3a4b4-ce61-4e5f-8249-5146c61e00eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132104273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2132104273
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4116090620
Short name T268
Test name
Test status
Simulation time 148691542 ps
CPU time 1.15 seconds
Started Mar 28 01:11:41 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 200844 kb
Host smart-108cd85a-ec6f-4bfe-bdd0-202fdb4833d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116090620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4116090620
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.995785402
Short name T317
Test name
Test status
Simulation time 76820668 ps
CPU time 0.78 seconds
Started Mar 28 01:09:15 PM PDT 24
Finished Mar 28 01:09:16 PM PDT 24
Peak memory 200576 kb
Host smart-3a4af4c5-e9cd-4cd0-a563-d7df29f64853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995785402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.995785402
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3353556307
Short name T59
Test name
Test status
Simulation time 1226407903 ps
CPU time 5.24 seconds
Started Mar 28 01:09:15 PM PDT 24
Finished Mar 28 01:09:20 PM PDT 24
Peak memory 218500 kb
Host smart-d4a33f2d-af87-4efd-acc9-4208a69bbbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353556307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3353556307
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2113107843
Short name T442
Test name
Test status
Simulation time 248706453 ps
CPU time 1.11 seconds
Started Mar 28 01:09:17 PM PDT 24
Finished Mar 28 01:09:18 PM PDT 24
Peak memory 218292 kb
Host smart-5bf86ad9-6bc3-40c9-afd2-0a1613150355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113107843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2113107843
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4081227271
Short name T429
Test name
Test status
Simulation time 150860816 ps
CPU time 0.89 seconds
Started Mar 28 01:09:22 PM PDT 24
Finished Mar 28 01:09:23 PM PDT 24
Peak memory 200700 kb
Host smart-c6b2941e-0086-4529-8aaa-d0564efbacae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081227271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4081227271
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4000394235
Short name T294
Test name
Test status
Simulation time 1687956872 ps
CPU time 6.4 seconds
Started Mar 28 01:09:15 PM PDT 24
Finished Mar 28 01:09:22 PM PDT 24
Peak memory 201056 kb
Host smart-8a16b3bc-4e27-409e-89b8-6c58bfa3cac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000394235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4000394235
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2080465145
Short name T445
Test name
Test status
Simulation time 187614329 ps
CPU time 1.2 seconds
Started Mar 28 01:09:15 PM PDT 24
Finished Mar 28 01:09:16 PM PDT 24
Peak memory 200756 kb
Host smart-acf2dbca-7195-4f56-9027-8e88fce6263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080465145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2080465145
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.405592561
Short name T410
Test name
Test status
Simulation time 117496403 ps
CPU time 1.12 seconds
Started Mar 28 01:09:16 PM PDT 24
Finished Mar 28 01:09:17 PM PDT 24
Peak memory 201004 kb
Host smart-acf64172-bcb9-47f7-86d0-9a3ef0761bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405592561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.405592561
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.940179095
Short name T185
Test name
Test status
Simulation time 4777406729 ps
CPU time 18.15 seconds
Started Mar 28 01:09:13 PM PDT 24
Finished Mar 28 01:09:31 PM PDT 24
Peak memory 201112 kb
Host smart-9db27338-cf1c-4a5c-bf94-1d3da481aac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940179095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.940179095
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2081368495
Short name T91
Test name
Test status
Simulation time 146119851 ps
CPU time 1.81 seconds
Started Mar 28 01:09:14 PM PDT 24
Finished Mar 28 01:09:16 PM PDT 24
Peak memory 200896 kb
Host smart-63dfde78-d856-488b-a49c-2e2a17d1c09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081368495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2081368495
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3015141147
Short name T502
Test name
Test status
Simulation time 73119620 ps
CPU time 0.78 seconds
Started Mar 28 01:11:34 PM PDT 24
Finished Mar 28 01:11:35 PM PDT 24
Peak memory 200700 kb
Host smart-88a480ed-07fd-4110-a45f-17d9190bf0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015141147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3015141147
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2342234303
Short name T292
Test name
Test status
Simulation time 2333547413 ps
CPU time 9.28 seconds
Started Mar 28 01:11:36 PM PDT 24
Finished Mar 28 01:11:46 PM PDT 24
Peak memory 218660 kb
Host smart-5b2243cb-8ecb-4600-b238-eedc8c204e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342234303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2342234303
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1835737181
Short name T309
Test name
Test status
Simulation time 244452856 ps
CPU time 1.06 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:11:34 PM PDT 24
Peak memory 218136 kb
Host smart-88217600-24f2-44ce-8d65-ab0de6cabd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835737181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1835737181
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4261819592
Short name T12
Test name
Test status
Simulation time 218408195 ps
CPU time 0.91 seconds
Started Mar 28 01:11:36 PM PDT 24
Finished Mar 28 01:11:37 PM PDT 24
Peak memory 200716 kb
Host smart-68efacc6-ce3c-48a6-bbcd-b1b852208888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261819592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4261819592
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1136020091
Short name T101
Test name
Test status
Simulation time 902625444 ps
CPU time 4.33 seconds
Started Mar 28 01:11:32 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 201028 kb
Host smart-00d363b6-e946-4a9e-8e38-a62bd581a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136020091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1136020091
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1461968800
Short name T189
Test name
Test status
Simulation time 97323833 ps
CPU time 0.99 seconds
Started Mar 28 01:11:38 PM PDT 24
Finished Mar 28 01:11:39 PM PDT 24
Peak memory 200772 kb
Host smart-fbed2155-3bd0-4eed-8cba-04735c76b3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461968800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1461968800
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1901519964
Short name T388
Test name
Test status
Simulation time 110610612 ps
CPU time 1.15 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:11:34 PM PDT 24
Peak memory 201004 kb
Host smart-ae5f912c-9113-4a15-b6b4-a18401f94697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901519964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1901519964
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1685436954
Short name T87
Test name
Test status
Simulation time 1890746367 ps
CPU time 6.62 seconds
Started Mar 28 01:11:43 PM PDT 24
Finished Mar 28 01:11:50 PM PDT 24
Peak memory 200996 kb
Host smart-5208b58f-ab06-4f42-be03-c04f1e933f23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685436954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1685436954
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3330948393
Short name T432
Test name
Test status
Simulation time 330816359 ps
CPU time 1.96 seconds
Started Mar 28 01:11:34 PM PDT 24
Finished Mar 28 01:11:37 PM PDT 24
Peak memory 200912 kb
Host smart-6ee89fc7-affb-4f0b-8971-c00f8b08072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330948393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3330948393
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3701902095
Short name T501
Test name
Test status
Simulation time 69320504 ps
CPU time 0.75 seconds
Started Mar 28 01:11:32 PM PDT 24
Finished Mar 28 01:11:34 PM PDT 24
Peak memory 200844 kb
Host smart-1f1f97f9-8f83-438f-bac3-253154661b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701902095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3701902095
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1173658316
Short name T232
Test name
Test status
Simulation time 62522393 ps
CPU time 0.79 seconds
Started Mar 28 01:11:41 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 200672 kb
Host smart-4f34b2be-f903-471d-b39a-965795a3302d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173658316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1173658316
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2617562127
Short name T536
Test name
Test status
Simulation time 1887925761 ps
CPU time 7.39 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:47 PM PDT 24
Peak memory 217460 kb
Host smart-cee3596b-6f3e-447b-bab9-10200c8b7064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617562127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2617562127
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4204033882
Short name T455
Test name
Test status
Simulation time 244778676 ps
CPU time 1.04 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:11:34 PM PDT 24
Peak memory 218184 kb
Host smart-a9ab5a16-2c42-4cff-8ce7-102ffff3948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204033882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4204033882
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3968954012
Short name T239
Test name
Test status
Simulation time 179907164 ps
CPU time 0.84 seconds
Started Mar 28 01:11:34 PM PDT 24
Finished Mar 28 01:11:36 PM PDT 24
Peak memory 200728 kb
Host smart-53843318-d898-495b-b0e5-19fd1686edb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968954012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3968954012
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3882028366
Short name T480
Test name
Test status
Simulation time 945789101 ps
CPU time 4.69 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 201056 kb
Host smart-dd6568ca-c3a8-4fac-b915-cff6546796da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882028366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3882028366
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.810480694
Short name T17
Test name
Test status
Simulation time 171532337 ps
CPU time 1.15 seconds
Started Mar 28 01:11:39 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 200796 kb
Host smart-f42a051a-928c-430e-b7ec-7061bbff85cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810480694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.810480694
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1547381055
Short name T359
Test name
Test status
Simulation time 122663413 ps
CPU time 1.22 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:11:35 PM PDT 24
Peak memory 200924 kb
Host smart-91c5f9f9-0339-401c-a854-c8db445e9872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547381055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1547381055
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2955201924
Short name T543
Test name
Test status
Simulation time 6750132933 ps
CPU time 26.72 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:12:00 PM PDT 24
Peak memory 201032 kb
Host smart-3db3cfe5-39bc-42c5-ada1-f9f5142f77e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955201924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2955201924
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.940131223
Short name T245
Test name
Test status
Simulation time 136291387 ps
CPU time 1.86 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 200852 kb
Host smart-fe9f4431-0e4a-4643-950b-7c2106007c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940131223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.940131223
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3603247833
Short name T348
Test name
Test status
Simulation time 155231588 ps
CPU time 1.24 seconds
Started Mar 28 01:11:32 PM PDT 24
Finished Mar 28 01:11:34 PM PDT 24
Peak memory 200980 kb
Host smart-c2018243-edf2-4207-acf7-d48eb538aa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603247833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3603247833
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3440435819
Short name T398
Test name
Test status
Simulation time 78704516 ps
CPU time 0.82 seconds
Started Mar 28 01:11:35 PM PDT 24
Finished Mar 28 01:11:36 PM PDT 24
Peak memory 200540 kb
Host smart-12fd9821-88fb-4724-a105-dede071cfaaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440435819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3440435819
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1958384479
Short name T469
Test name
Test status
Simulation time 2176541302 ps
CPU time 8.21 seconds
Started Mar 28 01:11:39 PM PDT 24
Finished Mar 28 01:11:48 PM PDT 24
Peak memory 222680 kb
Host smart-f10f9f74-59d4-4440-8830-9501244f79dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958384479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1958384479
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2064225979
Short name T251
Test name
Test status
Simulation time 244999490 ps
CPU time 1.05 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 218096 kb
Host smart-aeafaf2b-8e0f-4313-b4c1-e09d8693fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064225979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2064225979
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3954399527
Short name T24
Test name
Test status
Simulation time 141111213 ps
CPU time 0.8 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:11:35 PM PDT 24
Peak memory 200636 kb
Host smart-aa3d3066-1efe-4b13-84c3-cd212a1fe989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954399527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3954399527
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.462934223
Short name T467
Test name
Test status
Simulation time 764291177 ps
CPU time 3.86 seconds
Started Mar 28 01:11:36 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 200884 kb
Host smart-d38efb18-513c-47bc-af52-13e0b7860a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462934223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.462934223
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3907070365
Short name T401
Test name
Test status
Simulation time 148194465 ps
CPU time 1.07 seconds
Started Mar 28 01:11:35 PM PDT 24
Finished Mar 28 01:11:36 PM PDT 24
Peak memory 200672 kb
Host smart-5bab3742-3da2-4caa-a2e1-4449bdcca443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907070365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3907070365
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2074140341
Short name T289
Test name
Test status
Simulation time 121873141 ps
CPU time 1.14 seconds
Started Mar 28 01:11:30 PM PDT 24
Finished Mar 28 01:11:32 PM PDT 24
Peak memory 201024 kb
Host smart-4575b133-31ac-4a7c-84c4-afb65f243e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074140341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2074140341
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3666793173
Short name T182
Test name
Test status
Simulation time 4123778096 ps
CPU time 13.66 seconds
Started Mar 28 01:11:39 PM PDT 24
Finished Mar 28 01:11:52 PM PDT 24
Peak memory 201136 kb
Host smart-a8928063-4a7d-47c0-925f-a4fd55b8b017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666793173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3666793173
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.752913307
Short name T203
Test name
Test status
Simulation time 118529446 ps
CPU time 1.43 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 200848 kb
Host smart-687b6f39-1aa1-4ece-8b02-41cac5bf5b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752913307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.752913307
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4044768844
Short name T340
Test name
Test status
Simulation time 76819309 ps
CPU time 0.8 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 200792 kb
Host smart-6b62ed86-c241-48e6-8996-e783f8b8d9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044768844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4044768844
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.926286162
Short name T83
Test name
Test status
Simulation time 55624294 ps
CPU time 0.69 seconds
Started Mar 28 01:11:35 PM PDT 24
Finished Mar 28 01:11:36 PM PDT 24
Peak memory 200680 kb
Host smart-405e03c0-debb-4452-88eb-5acfd54f8f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926286162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.926286162
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.4274528044
Short name T514
Test name
Test status
Simulation time 1232084188 ps
CPU time 5.78 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:46 PM PDT 24
Peak memory 222624 kb
Host smart-b135524b-c7e5-473f-a5ec-315168dcae73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274528044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4274528044
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.753994589
Short name T342
Test name
Test status
Simulation time 244736622 ps
CPU time 1.03 seconds
Started Mar 28 01:11:34 PM PDT 24
Finished Mar 28 01:11:35 PM PDT 24
Peak memory 218052 kb
Host smart-64f866db-16ff-4b9b-adb8-9e6c508b3e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753994589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.753994589
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3762886210
Short name T22
Test name
Test status
Simulation time 191538896 ps
CPU time 0.94 seconds
Started Mar 28 01:11:36 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200712 kb
Host smart-8f6d8f86-e0fa-4d83-956d-c040a2b2adca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762886210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3762886210
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3178439002
Short name T18
Test name
Test status
Simulation time 1528176523 ps
CPU time 5.8 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:43 PM PDT 24
Peak memory 201012 kb
Host smart-340047d8-6d92-4273-87ae-0ba645e73c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178439002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3178439002
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2799888450
Short name T274
Test name
Test status
Simulation time 102746203 ps
CPU time 1.04 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 200828 kb
Host smart-2a099404-eb55-4d88-adef-17eb2f107ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799888450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2799888450
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1774067427
Short name T463
Test name
Test status
Simulation time 197621147 ps
CPU time 1.38 seconds
Started Mar 28 01:11:35 PM PDT 24
Finished Mar 28 01:11:36 PM PDT 24
Peak memory 201028 kb
Host smart-dd32ba06-01e9-431a-850f-fc9a9ecf9221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774067427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1774067427
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.4122764389
Short name T542
Test name
Test status
Simulation time 8112796786 ps
CPU time 33.83 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:12:08 PM PDT 24
Peak memory 209264 kb
Host smart-64a7a5a6-15bc-4108-80a5-4ed8e40736a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122764389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.4122764389
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.287240935
Short name T7
Test name
Test status
Simulation time 128066103 ps
CPU time 1.56 seconds
Started Mar 28 01:11:41 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 200904 kb
Host smart-88be940d-66dc-44df-8558-d14fb29ffc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287240935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.287240935
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3690958598
Short name T152
Test name
Test status
Simulation time 91653954 ps
CPU time 0.99 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200836 kb
Host smart-f157c107-f9e0-4b53-9bc9-734dd486feca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690958598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3690958598
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.597325710
Short name T516
Test name
Test status
Simulation time 66374497 ps
CPU time 0.77 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200576 kb
Host smart-78e96e68-1406-41f4-90fe-89388ebfa854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597325710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.597325710
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.4026998064
Short name T53
Test name
Test status
Simulation time 1221658200 ps
CPU time 5.33 seconds
Started Mar 28 01:11:36 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 218560 kb
Host smart-b0f10177-3c63-4a29-8561-7c8fa11f8694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026998064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.4026998064
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1002564713
Short name T396
Test name
Test status
Simulation time 244747130 ps
CPU time 1.05 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 218152 kb
Host smart-37d30228-6113-458b-9199-0364b0f92cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002564713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1002564713
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2914404053
Short name T328
Test name
Test status
Simulation time 219535532 ps
CPU time 0.94 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200636 kb
Host smart-cedc7991-34a9-4b84-af7f-6725b0d0e896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914404053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2914404053
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.360852577
Short name T380
Test name
Test status
Simulation time 1785954673 ps
CPU time 6.26 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:43 PM PDT 24
Peak memory 200884 kb
Host smart-5a1879ab-c66f-4b41-94a2-b3f733bb34d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360852577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.360852577
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3311787490
Short name T137
Test name
Test status
Simulation time 183207356 ps
CPU time 1.16 seconds
Started Mar 28 01:11:39 PM PDT 24
Finished Mar 28 01:11:40 PM PDT 24
Peak memory 200796 kb
Host smart-eb044d77-68ac-429c-a97a-8dbdd8dba827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311787490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3311787490
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1890578947
Short name T229
Test name
Test status
Simulation time 249154107 ps
CPU time 1.45 seconds
Started Mar 28 01:11:38 PM PDT 24
Finished Mar 28 01:11:40 PM PDT 24
Peak memory 201036 kb
Host smart-f99c1953-89dc-4d34-aea9-e5e88a95164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890578947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1890578947
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3676620804
Short name T331
Test name
Test status
Simulation time 2929600644 ps
CPU time 10.23 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:51 PM PDT 24
Peak memory 209756 kb
Host smart-53154ef7-5d96-4be1-ac60-7d2441145c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676620804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3676620804
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.264435841
Short name T214
Test name
Test status
Simulation time 422541527 ps
CPU time 2.33 seconds
Started Mar 28 01:11:39 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 209088 kb
Host smart-1505476e-e2a5-417b-b56f-5cfb0b4f35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264435841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.264435841
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3407067644
Short name T191
Test name
Test status
Simulation time 67789532 ps
CPU time 0.8 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200772 kb
Host smart-ce41471c-0ee3-4bb2-8a62-2947fcbe7158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407067644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3407067644
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2483729888
Short name T363
Test name
Test status
Simulation time 80903466 ps
CPU time 0.8 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:45 PM PDT 24
Peak memory 200688 kb
Host smart-5a493ec2-9f6c-4a0d-adce-a5b282f5c6cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483729888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2483729888
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1376336962
Short name T326
Test name
Test status
Simulation time 2363675263 ps
CPU time 8.31 seconds
Started Mar 28 01:11:43 PM PDT 24
Finished Mar 28 01:11:52 PM PDT 24
Peak memory 218360 kb
Host smart-9065e945-1f2c-4caf-8570-056c9915ada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376336962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1376336962
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4228152904
Short name T377
Test name
Test status
Simulation time 246079773 ps
CPU time 1.11 seconds
Started Mar 28 01:11:43 PM PDT 24
Finished Mar 28 01:11:44 PM PDT 24
Peak memory 218144 kb
Host smart-0a5daaf7-4820-4a73-b72b-87073fc0522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228152904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4228152904
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3459298475
Short name T426
Test name
Test status
Simulation time 121944046 ps
CPU time 0.76 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 200664 kb
Host smart-b5fe41ab-dc5d-4ed8-87ac-41e9d1437eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459298475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3459298475
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.4281675979
Short name T400
Test name
Test status
Simulation time 1549879358 ps
CPU time 5.78 seconds
Started Mar 28 01:11:39 PM PDT 24
Finished Mar 28 01:11:44 PM PDT 24
Peak memory 200972 kb
Host smart-d3f35594-5362-468d-ad90-c59050bd328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281675979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.4281675979
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3109407844
Short name T153
Test name
Test status
Simulation time 111749287 ps
CPU time 1.06 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 200832 kb
Host smart-34d282e8-e1b7-4765-a3a2-4afb32500987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109407844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3109407844
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2745395139
Short name T296
Test name
Test status
Simulation time 207648640 ps
CPU time 1.39 seconds
Started Mar 28 01:11:39 PM PDT 24
Finished Mar 28 01:11:40 PM PDT 24
Peak memory 200968 kb
Host smart-eec08615-5b1c-468e-a8f4-01992aa6beb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745395139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2745395139
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.227205549
Short name T353
Test name
Test status
Simulation time 3515270834 ps
CPU time 15.67 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:12:00 PM PDT 24
Peak memory 201116 kb
Host smart-112b2bbe-6b91-4c8a-b1e4-b84dde4abddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227205549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.227205549
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.883612579
Short name T521
Test name
Test status
Simulation time 137374256 ps
CPU time 1.61 seconds
Started Mar 28 01:11:39 PM PDT 24
Finished Mar 28 01:11:40 PM PDT 24
Peak memory 209072 kb
Host smart-bf519a94-c3f9-4d5a-8fe9-7034d28d4e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883612579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.883612579
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1380444774
Short name T491
Test name
Test status
Simulation time 93231204 ps
CPU time 0.83 seconds
Started Mar 28 01:11:41 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 200844 kb
Host smart-70bc69d6-440f-42b5-bc91-abfce2e29d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380444774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1380444774
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.313551823
Short name T249
Test name
Test status
Simulation time 74482447 ps
CPU time 0.89 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:45 PM PDT 24
Peak memory 200680 kb
Host smart-d0dcd83a-fc6e-4b39-a5c4-456d94e35043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313551823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.313551823
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1523460335
Short name T413
Test name
Test status
Simulation time 2349760836 ps
CPU time 7.93 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:52 PM PDT 24
Peak memory 218660 kb
Host smart-a9bf6141-f0a4-41be-aefa-e8c40a3d14cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523460335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1523460335
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3275886128
Short name T414
Test name
Test status
Simulation time 244526166 ps
CPU time 1.1 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:45 PM PDT 24
Peak memory 218092 kb
Host smart-644add2f-4b09-4fe1-84e0-8411419021bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275886128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3275886128
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1892612509
Short name T196
Test name
Test status
Simulation time 203410964 ps
CPU time 0.92 seconds
Started Mar 28 01:11:40 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 200696 kb
Host smart-8d3be59e-0ba8-4779-8754-b0005d1408fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892612509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1892612509
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1700589956
Short name T303
Test name
Test status
Simulation time 1135251003 ps
CPU time 5.21 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:42 PM PDT 24
Peak memory 200980 kb
Host smart-ca404e0f-101a-4d03-8d40-9340db345526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700589956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1700589956
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.761263441
Short name T199
Test name
Test status
Simulation time 179411065 ps
CPU time 1.21 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:45 PM PDT 24
Peak memory 200812 kb
Host smart-f7c432f4-e1ae-428d-9ed4-0dc79f50b255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761263441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.761263441
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3260738606
Short name T260
Test name
Test status
Simulation time 247856167 ps
CPU time 1.5 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200976 kb
Host smart-27facd94-eb37-4715-97ea-9f5fdaceffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260738606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3260738606
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1337828228
Short name T343
Test name
Test status
Simulation time 6139373359 ps
CPU time 28.97 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:12:06 PM PDT 24
Peak memory 209384 kb
Host smart-f7bb1405-3557-4b91-8704-d1ab2f62a2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337828228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1337828228
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3223619659
Short name T424
Test name
Test status
Simulation time 149661743 ps
CPU time 1.86 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:46 PM PDT 24
Peak memory 200748 kb
Host smart-7fc30f73-34bc-4c98-8450-bb2a3610952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223619659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3223619659
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4083140365
Short name T89
Test name
Test status
Simulation time 81745515 ps
CPU time 0.84 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200804 kb
Host smart-7290d5d4-77a5-47ec-8a8c-7231a07034b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083140365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4083140365
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2677330887
Short name T487
Test name
Test status
Simulation time 81319046 ps
CPU time 0.85 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:45 PM PDT 24
Peak memory 200648 kb
Host smart-769930da-ab24-4eee-8b20-28f7a28ee626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677330887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2677330887
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1949908532
Short name T39
Test name
Test status
Simulation time 1884871176 ps
CPU time 6.97 seconds
Started Mar 28 01:11:37 PM PDT 24
Finished Mar 28 01:11:44 PM PDT 24
Peak memory 218584 kb
Host smart-4445fa36-5848-4a1c-9172-a58dead84f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949908532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1949908532
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3253586250
Short name T85
Test name
Test status
Simulation time 245080222 ps
CPU time 1 seconds
Started Mar 28 01:11:42 PM PDT 24
Finished Mar 28 01:11:43 PM PDT 24
Peak memory 218276 kb
Host smart-b1bee79d-1034-4d3d-a8f4-5c082cc1bd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253586250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3253586250
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2604176484
Short name T27
Test name
Test status
Simulation time 192333020 ps
CPU time 0.94 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:11:34 PM PDT 24
Peak memory 200732 kb
Host smart-d1a5de7a-ce09-4007-a610-9a5f3a3c42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604176484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2604176484
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.225271066
Short name T399
Test name
Test status
Simulation time 1095251570 ps
CPU time 5.64 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:49 PM PDT 24
Peak memory 201020 kb
Host smart-02bb6088-404c-4ed1-afc9-a3db7376e40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225271066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.225271066
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2938902553
Short name T448
Test name
Test status
Simulation time 184655571 ps
CPU time 1.19 seconds
Started Mar 28 01:11:36 PM PDT 24
Finished Mar 28 01:11:37 PM PDT 24
Peak memory 200896 kb
Host smart-3edac1bd-1f39-468f-8a01-6517db82444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938902553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2938902553
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2496767377
Short name T177
Test name
Test status
Simulation time 259203350 ps
CPU time 1.44 seconds
Started Mar 28 01:11:33 PM PDT 24
Finished Mar 28 01:11:35 PM PDT 24
Peak memory 201000 kb
Host smart-095353eb-1bca-4303-92a8-3777f40b57a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496767377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2496767377
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.884131074
Short name T272
Test name
Test status
Simulation time 389953231 ps
CPU time 2.22 seconds
Started Mar 28 01:11:32 PM PDT 24
Finished Mar 28 01:11:35 PM PDT 24
Peak memory 201016 kb
Host smart-9e573323-859e-4c74-80e4-df2df7ae2b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884131074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.884131074
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1477418409
Short name T173
Test name
Test status
Simulation time 336952014 ps
CPU time 1.93 seconds
Started Mar 28 01:11:36 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200948 kb
Host smart-bab17fd5-21c5-4121-a069-c9b338af4ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477418409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1477418409
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3549800978
Short name T321
Test name
Test status
Simulation time 129860945 ps
CPU time 1.09 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:45 PM PDT 24
Peak memory 200812 kb
Host smart-a6224569-25a6-4ef6-b15a-de7b5176c1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549800978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3549800978
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2452533803
Short name T169
Test name
Test status
Simulation time 68319793 ps
CPU time 0.78 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:11:52 PM PDT 24
Peak memory 200712 kb
Host smart-5a6816f4-9eac-41f9-9b30-bb51bbdb86b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452533803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2452533803
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.902261699
Short name T52
Test name
Test status
Simulation time 1910375225 ps
CPU time 7.04 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:11:57 PM PDT 24
Peak memory 217984 kb
Host smart-d3209e3b-00ea-4920-bf85-e132d2410f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902261699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.902261699
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.964776394
Short name T148
Test name
Test status
Simulation time 247416970 ps
CPU time 0.98 seconds
Started Mar 28 01:11:47 PM PDT 24
Finished Mar 28 01:11:48 PM PDT 24
Peak memory 218112 kb
Host smart-63080ffb-9b0a-459d-91d2-504bc8a3e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964776394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.964776394
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.960024560
Short name T25
Test name
Test status
Simulation time 216116207 ps
CPU time 0.94 seconds
Started Mar 28 01:11:36 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 200720 kb
Host smart-25376be1-dcc4-4f3f-b16e-2a16d82885bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960024560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.960024560
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3414843423
Short name T512
Test name
Test status
Simulation time 848085335 ps
CPU time 4.16 seconds
Started Mar 28 01:11:35 PM PDT 24
Finished Mar 28 01:11:39 PM PDT 24
Peak memory 201016 kb
Host smart-36a50493-0174-474d-9619-17493839a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414843423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3414843423
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3986230740
Short name T454
Test name
Test status
Simulation time 100620863 ps
CPU time 0.97 seconds
Started Mar 28 01:11:53 PM PDT 24
Finished Mar 28 01:11:55 PM PDT 24
Peak memory 200832 kb
Host smart-87535d58-0731-4858-ac71-83519efbdfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986230740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3986230740
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.439026069
Short name T178
Test name
Test status
Simulation time 202783340 ps
CPU time 1.46 seconds
Started Mar 28 01:11:36 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 201056 kb
Host smart-9b5994c8-6927-4b7d-855b-f3c7b1d95bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439026069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.439026069
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.958728391
Short name T337
Test name
Test status
Simulation time 5214525425 ps
CPU time 22.45 seconds
Started Mar 28 01:11:52 PM PDT 24
Finished Mar 28 01:12:14 PM PDT 24
Peak memory 201092 kb
Host smart-628bf40f-a1f3-4b74-af51-351dca508c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958728391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.958728391
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.438542726
Short name T519
Test name
Test status
Simulation time 141481979 ps
CPU time 1.71 seconds
Started Mar 28 01:11:48 PM PDT 24
Finished Mar 28 01:11:50 PM PDT 24
Peak memory 200852 kb
Host smart-5dde8bc1-c781-4215-a85e-decf8577a722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438542726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.438542726
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1024206300
Short name T262
Test name
Test status
Simulation time 87487584 ps
CPU time 0.89 seconds
Started Mar 28 01:11:44 PM PDT 24
Finished Mar 28 01:11:45 PM PDT 24
Peak memory 200704 kb
Host smart-c9533b46-6d55-4233-86e0-5ecc7c460d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024206300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1024206300
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1941163395
Short name T192
Test name
Test status
Simulation time 72155996 ps
CPU time 0.71 seconds
Started Mar 28 01:11:49 PM PDT 24
Finished Mar 28 01:11:50 PM PDT 24
Peak memory 200728 kb
Host smart-036e592f-68dc-44ee-bfcc-23d3494d7d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941163395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1941163395
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.514423532
Short name T50
Test name
Test status
Simulation time 1233419963 ps
CPU time 5.46 seconds
Started Mar 28 01:11:49 PM PDT 24
Finished Mar 28 01:11:55 PM PDT 24
Peak memory 222552 kb
Host smart-956a485c-e7f8-425b-ae23-56ec3c5420cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514423532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.514423532
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.4169273140
Short name T5
Test name
Test status
Simulation time 244625939 ps
CPU time 1.07 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:11:52 PM PDT 24
Peak memory 218256 kb
Host smart-32698855-2f52-4ed5-afb5-3bf54b521df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169273140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.4169273140
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2006723380
Short name T275
Test name
Test status
Simulation time 114861693 ps
CPU time 0.77 seconds
Started Mar 28 01:11:51 PM PDT 24
Finished Mar 28 01:11:52 PM PDT 24
Peak memory 200692 kb
Host smart-09c74c81-cce7-49c7-9186-e3d265292d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006723380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2006723380
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2146736052
Short name T384
Test name
Test status
Simulation time 1818170458 ps
CPU time 6.96 seconds
Started Mar 28 01:11:48 PM PDT 24
Finished Mar 28 01:11:55 PM PDT 24
Peak memory 201056 kb
Host smart-2c547b7d-77ac-4719-80cb-e99c9b1781e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146736052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2146736052
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3936504077
Short name T526
Test name
Test status
Simulation time 104118815 ps
CPU time 1.01 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:11:51 PM PDT 24
Peak memory 200804 kb
Host smart-1283b83b-72db-4763-b88c-2b0c043cd5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936504077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3936504077
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.4227175549
Short name T354
Test name
Test status
Simulation time 119443744 ps
CPU time 1.14 seconds
Started Mar 28 01:11:49 PM PDT 24
Finished Mar 28 01:11:50 PM PDT 24
Peak memory 201040 kb
Host smart-617af319-1a4d-403d-bafa-bc1dc543e40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227175549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.4227175549
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.994685138
Short name T306
Test name
Test status
Simulation time 13894729995 ps
CPU time 48.21 seconds
Started Mar 28 01:11:55 PM PDT 24
Finished Mar 28 01:12:43 PM PDT 24
Peak memory 201152 kb
Host smart-56535682-83d6-4473-a737-7679787a7d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994685138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.994685138
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.340714515
Short name T3
Test name
Test status
Simulation time 300195442 ps
CPU time 1.96 seconds
Started Mar 28 01:11:50 PM PDT 24
Finished Mar 28 01:11:52 PM PDT 24
Peak memory 200896 kb
Host smart-8575625a-80c5-4316-99e5-3023dd73d4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340714515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.340714515
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.98482895
Short name T150
Test name
Test status
Simulation time 94913024 ps
CPU time 0.9 seconds
Started Mar 28 01:11:49 PM PDT 24
Finished Mar 28 01:11:50 PM PDT 24
Peak memory 200844 kb
Host smart-082617fa-f94c-4a08-9b87-a7c6398c0a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98482895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.98482895
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1488654089
Short name T446
Test name
Test status
Simulation time 63531500 ps
CPU time 0.75 seconds
Started Mar 28 01:09:35 PM PDT 24
Finished Mar 28 01:09:36 PM PDT 24
Peak memory 200708 kb
Host smart-862f6bd4-7506-4b14-9871-dc95d127b863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488654089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1488654089
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2511254015
Short name T458
Test name
Test status
Simulation time 2156216950 ps
CPU time 7.66 seconds
Started Mar 28 01:09:36 PM PDT 24
Finished Mar 28 01:09:43 PM PDT 24
Peak memory 222696 kb
Host smart-71cf96ba-8b35-4c4a-b93c-eef3d551a8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511254015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2511254015
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3527772037
Short name T325
Test name
Test status
Simulation time 243736918 ps
CPU time 1.01 seconds
Started Mar 28 01:09:35 PM PDT 24
Finished Mar 28 01:09:36 PM PDT 24
Peak memory 218188 kb
Host smart-b4f8d217-0835-4f84-9cb7-a4b9d7873494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527772037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3527772037
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.99908820
Short name T80
Test name
Test status
Simulation time 206950141 ps
CPU time 0.88 seconds
Started Mar 28 01:09:16 PM PDT 24
Finished Mar 28 01:09:17 PM PDT 24
Peak memory 200676 kb
Host smart-396bf76f-9ec3-45bb-9148-95117d94dc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99908820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.99908820
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2642929092
Short name T107
Test name
Test status
Simulation time 1449160076 ps
CPU time 5.4 seconds
Started Mar 28 01:09:18 PM PDT 24
Finished Mar 28 01:09:23 PM PDT 24
Peak memory 200976 kb
Host smart-8f768a9f-43fb-4e38-817c-89c1bc4738c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642929092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2642929092
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1492588337
Short name T420
Test name
Test status
Simulation time 142980345 ps
CPU time 1.18 seconds
Started Mar 28 01:09:14 PM PDT 24
Finished Mar 28 01:09:15 PM PDT 24
Peak memory 200832 kb
Host smart-4581d6d0-6c58-4b5e-978f-eebbd65a20b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492588337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1492588337
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3732407097
Short name T494
Test name
Test status
Simulation time 255666870 ps
CPU time 1.5 seconds
Started Mar 28 01:09:16 PM PDT 24
Finished Mar 28 01:09:18 PM PDT 24
Peak memory 200984 kb
Host smart-ce69be44-e983-45e3-94f3-12bdffd37f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732407097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3732407097
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.885214363
Short name T482
Test name
Test status
Simulation time 10989612208 ps
CPU time 38.6 seconds
Started Mar 28 01:09:36 PM PDT 24
Finished Mar 28 01:10:15 PM PDT 24
Peak memory 209352 kb
Host smart-90d823f6-9e95-49a4-834f-dfca0096f574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885214363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.885214363
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1310581330
Short name T176
Test name
Test status
Simulation time 351204599 ps
CPU time 2.34 seconds
Started Mar 28 01:09:15 PM PDT 24
Finished Mar 28 01:09:18 PM PDT 24
Peak memory 200872 kb
Host smart-91b34e31-2826-4517-a327-b7d5ef91b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310581330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1310581330
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2173142951
Short name T194
Test name
Test status
Simulation time 193082085 ps
CPU time 1.24 seconds
Started Mar 28 01:09:17 PM PDT 24
Finished Mar 28 01:09:18 PM PDT 24
Peak memory 200800 kb
Host smart-97b23055-0580-4274-83f7-1bc1fa181442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173142951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2173142951
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2600042790
Short name T139
Test name
Test status
Simulation time 74694245 ps
CPU time 0.8 seconds
Started Mar 28 01:09:41 PM PDT 24
Finished Mar 28 01:09:42 PM PDT 24
Peak memory 200672 kb
Host smart-4331cccd-3444-458c-af68-f9ede36fc04a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600042790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2600042790
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3540619384
Short name T48
Test name
Test status
Simulation time 1228424614 ps
CPU time 5.45 seconds
Started Mar 28 01:09:36 PM PDT 24
Finished Mar 28 01:09:42 PM PDT 24
Peak memory 222608 kb
Host smart-3ebe8431-3a92-49bd-9389-0542fac14989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540619384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3540619384
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3731387998
Short name T500
Test name
Test status
Simulation time 244441807 ps
CPU time 1.07 seconds
Started Mar 28 01:09:35 PM PDT 24
Finished Mar 28 01:09:37 PM PDT 24
Peak memory 218088 kb
Host smart-307ce555-2d15-46e4-94bd-4a37bf85aa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731387998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3731387998
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.120857855
Short name T26
Test name
Test status
Simulation time 181490693 ps
CPU time 0.84 seconds
Started Mar 28 01:09:42 PM PDT 24
Finished Mar 28 01:09:43 PM PDT 24
Peak memory 200572 kb
Host smart-208461fa-f881-4afc-b9b9-cbe75d6ad15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120857855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.120857855
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1677882233
Short name T233
Test name
Test status
Simulation time 678541463 ps
CPU time 3.44 seconds
Started Mar 28 01:09:36 PM PDT 24
Finished Mar 28 01:09:40 PM PDT 24
Peak memory 200988 kb
Host smart-5fb4ba22-768e-44c2-a27a-86a384538230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677882233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1677882233
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2491103114
Short name T241
Test name
Test status
Simulation time 103032868 ps
CPU time 0.93 seconds
Started Mar 28 01:09:35 PM PDT 24
Finished Mar 28 01:09:36 PM PDT 24
Peak memory 200772 kb
Host smart-8d0431a3-11c7-4b4b-a614-6f9eb3528534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491103114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2491103114
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2356118747
Short name T157
Test name
Test status
Simulation time 261029781 ps
CPU time 1.56 seconds
Started Mar 28 01:09:36 PM PDT 24
Finished Mar 28 01:09:38 PM PDT 24
Peak memory 201000 kb
Host smart-e437fbac-2cd4-4c54-a0fc-6da6bb33d75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356118747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2356118747
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.4136785463
Short name T534
Test name
Test status
Simulation time 6817040047 ps
CPU time 23.4 seconds
Started Mar 28 01:09:40 PM PDT 24
Finished Mar 28 01:10:04 PM PDT 24
Peak memory 201116 kb
Host smart-da096cfb-13eb-43dd-84cc-31cfd40eed62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136785463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.4136785463
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2675844235
Short name T282
Test name
Test status
Simulation time 129320137 ps
CPU time 1.53 seconds
Started Mar 28 01:09:35 PM PDT 24
Finished Mar 28 01:09:37 PM PDT 24
Peak memory 209096 kb
Host smart-86e7dd61-0e0e-4049-8d19-d0b0e827ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675844235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2675844235
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3937308766
Short name T86
Test name
Test status
Simulation time 77444611 ps
CPU time 0.83 seconds
Started Mar 28 01:09:36 PM PDT 24
Finished Mar 28 01:09:37 PM PDT 24
Peak memory 200784 kb
Host smart-eabb0b0e-955a-47fc-a58d-e1ac09d96eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937308766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3937308766
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1023773425
Short name T544
Test name
Test status
Simulation time 92411937 ps
CPU time 0.87 seconds
Started Mar 28 01:09:41 PM PDT 24
Finished Mar 28 01:09:42 PM PDT 24
Peak memory 200696 kb
Host smart-d3fb1ae2-f215-4892-8d0b-0ce0bd0080e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023773425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1023773425
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.4273628656
Short name T417
Test name
Test status
Simulation time 1225407118 ps
CPU time 5.85 seconds
Started Mar 28 01:09:43 PM PDT 24
Finished Mar 28 01:09:49 PM PDT 24
Peak memory 218564 kb
Host smart-09321129-7eaa-415f-b679-54759a1e11c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273628656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.4273628656
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1272185938
Short name T163
Test name
Test status
Simulation time 245739684 ps
CPU time 0.99 seconds
Started Mar 28 01:09:40 PM PDT 24
Finished Mar 28 01:09:42 PM PDT 24
Peak memory 218180 kb
Host smart-3da389c2-dd6a-42c3-9c43-790043a6e389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272185938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1272185938
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.983521808
Short name T161
Test name
Test status
Simulation time 218039668 ps
CPU time 0.89 seconds
Started Mar 28 01:09:42 PM PDT 24
Finished Mar 28 01:09:43 PM PDT 24
Peak memory 200712 kb
Host smart-ad99980f-e838-4d06-be36-f9a2ccdd86ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983521808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.983521808
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3264233067
Short name T490
Test name
Test status
Simulation time 1367416992 ps
CPU time 5.14 seconds
Started Mar 28 01:09:41 PM PDT 24
Finished Mar 28 01:09:47 PM PDT 24
Peak memory 201004 kb
Host smart-47353436-d2c2-4d62-86e4-3798c613a6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264233067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3264233067
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.13851419
Short name T146
Test name
Test status
Simulation time 148243741 ps
CPU time 1.1 seconds
Started Mar 28 01:09:43 PM PDT 24
Finished Mar 28 01:09:44 PM PDT 24
Peak memory 200812 kb
Host smart-53a21ca7-792b-4021-8a9d-b5deaec498a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13851419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.13851419
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2603187854
Short name T265
Test name
Test status
Simulation time 256440562 ps
CPU time 1.49 seconds
Started Mar 28 01:09:43 PM PDT 24
Finished Mar 28 01:09:45 PM PDT 24
Peak memory 201048 kb
Host smart-29180871-06e6-4f7e-9af2-1fc8f9b3f929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603187854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2603187854
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2004106496
Short name T373
Test name
Test status
Simulation time 12758849280 ps
CPU time 42.58 seconds
Started Mar 28 01:09:42 PM PDT 24
Finished Mar 28 01:10:25 PM PDT 24
Peak memory 209380 kb
Host smart-f6a3588b-af90-4ad3-a4aa-4320cd2d84f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004106496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2004106496
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.326804275
Short name T302
Test name
Test status
Simulation time 556283027 ps
CPU time 2.69 seconds
Started Mar 28 01:09:41 PM PDT 24
Finished Mar 28 01:09:44 PM PDT 24
Peak memory 200892 kb
Host smart-e3a3e77e-b8d2-4ae0-9c0f-7f4d90d1002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326804275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.326804275
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1249854360
Short name T297
Test name
Test status
Simulation time 190107951 ps
CPU time 1.1 seconds
Started Mar 28 01:09:40 PM PDT 24
Finished Mar 28 01:09:42 PM PDT 24
Peak memory 200648 kb
Host smart-225c7a8a-3b86-423c-8f9c-3f44bda551bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249854360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1249854360
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2777719821
Short name T30
Test name
Test status
Simulation time 66981918 ps
CPU time 0.71 seconds
Started Mar 28 01:09:44 PM PDT 24
Finished Mar 28 01:09:45 PM PDT 24
Peak memory 200676 kb
Host smart-076f158c-0da1-4038-b690-0c9cb449bb24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777719821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2777719821
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2179922761
Short name T522
Test name
Test status
Simulation time 1879921188 ps
CPU time 7.46 seconds
Started Mar 28 01:09:44 PM PDT 24
Finished Mar 28 01:09:51 PM PDT 24
Peak memory 218428 kb
Host smart-a7dc1843-33ba-4b59-8164-a03005527ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179922761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2179922761
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.4013283879
Short name T444
Test name
Test status
Simulation time 244988681 ps
CPU time 1.05 seconds
Started Mar 28 01:09:44 PM PDT 24
Finished Mar 28 01:09:45 PM PDT 24
Peak memory 218140 kb
Host smart-7b74e5a2-88e8-4f05-8a15-7cf10f0756b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013283879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.4013283879
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3284363555
Short name T378
Test name
Test status
Simulation time 180990698 ps
CPU time 0.88 seconds
Started Mar 28 01:09:43 PM PDT 24
Finished Mar 28 01:09:44 PM PDT 24
Peak memory 200644 kb
Host smart-2eff678e-8f98-41a7-b702-9c847b64ca2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284363555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3284363555
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.921225784
Short name T193
Test name
Test status
Simulation time 1185960226 ps
CPU time 5.3 seconds
Started Mar 28 01:09:45 PM PDT 24
Finished Mar 28 01:09:50 PM PDT 24
Peak memory 200984 kb
Host smart-b59fdd09-d494-4da4-8ba2-b1c184764a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921225784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.921225784
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1371005729
Short name T474
Test name
Test status
Simulation time 108864828 ps
CPU time 0.94 seconds
Started Mar 28 01:09:42 PM PDT 24
Finished Mar 28 01:09:44 PM PDT 24
Peak memory 200856 kb
Host smart-75322049-6780-4ac9-8a13-473ee8b60825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371005729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1371005729
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3453535770
Short name T416
Test name
Test status
Simulation time 191108405 ps
CPU time 1.27 seconds
Started Mar 28 01:09:40 PM PDT 24
Finished Mar 28 01:09:42 PM PDT 24
Peak memory 201068 kb
Host smart-e76b5d6e-db27-469c-9427-238614d5b519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453535770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3453535770
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2877108245
Short name T496
Test name
Test status
Simulation time 9846817093 ps
CPU time 34.25 seconds
Started Mar 28 01:09:42 PM PDT 24
Finished Mar 28 01:10:17 PM PDT 24
Peak memory 209332 kb
Host smart-ab9fa42c-e199-4446-83a6-99473a38ab60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877108245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2877108245
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1129714768
Short name T362
Test name
Test status
Simulation time 412494442 ps
CPU time 2.19 seconds
Started Mar 28 01:09:44 PM PDT 24
Finished Mar 28 01:09:46 PM PDT 24
Peak memory 209012 kb
Host smart-a30307e5-cae1-4099-93df-4dcc42437c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129714768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1129714768
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3121248144
Short name T518
Test name
Test status
Simulation time 147745661 ps
CPU time 0.98 seconds
Started Mar 28 01:09:42 PM PDT 24
Finished Mar 28 01:09:43 PM PDT 24
Peak memory 200840 kb
Host smart-7bc8e67a-4674-4042-9858-146932813038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121248144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3121248144
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3339358322
Short name T385
Test name
Test status
Simulation time 85666073 ps
CPU time 0.78 seconds
Started Mar 28 01:09:50 PM PDT 24
Finished Mar 28 01:09:51 PM PDT 24
Peak memory 200748 kb
Host smart-107db135-4285-444f-afc2-af4c70de7d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339358322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3339358322
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1782201702
Short name T411
Test name
Test status
Simulation time 1223258114 ps
CPU time 5.65 seconds
Started Mar 28 01:09:55 PM PDT 24
Finished Mar 28 01:10:01 PM PDT 24
Peak memory 222480 kb
Host smart-00953ab0-4cb5-4b98-b386-5d8ac3e779cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782201702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1782201702
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.962040047
Short name T451
Test name
Test status
Simulation time 244787232 ps
CPU time 1.1 seconds
Started Mar 28 01:09:51 PM PDT 24
Finished Mar 28 01:09:52 PM PDT 24
Peak memory 218248 kb
Host smart-75a6edb0-b83b-4584-8b46-788a877ce2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962040047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.962040047
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1732706301
Short name T164
Test name
Test status
Simulation time 147287424 ps
CPU time 0.82 seconds
Started Mar 28 01:09:43 PM PDT 24
Finished Mar 28 01:09:44 PM PDT 24
Peak memory 200608 kb
Host smart-a537384d-afc3-4c16-a6ba-c6d441db03d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732706301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1732706301
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2003465186
Short name T503
Test name
Test status
Simulation time 904254459 ps
CPU time 4.53 seconds
Started Mar 28 01:09:43 PM PDT 24
Finished Mar 28 01:09:48 PM PDT 24
Peak memory 201036 kb
Host smart-4fdea0c0-5382-4a2c-9ef1-5f884462b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003465186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2003465186
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1347692221
Short name T162
Test name
Test status
Simulation time 180490615 ps
CPU time 1.18 seconds
Started Mar 28 01:09:45 PM PDT 24
Finished Mar 28 01:09:46 PM PDT 24
Peak memory 200788 kb
Host smart-be63f8d7-c18f-47e2-86b8-4efb924f6cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347692221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1347692221
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3404548159
Short name T254
Test name
Test status
Simulation time 112159727 ps
CPU time 1.13 seconds
Started Mar 28 01:09:44 PM PDT 24
Finished Mar 28 01:09:45 PM PDT 24
Peak memory 200940 kb
Host smart-3e5350ad-82d8-43d2-b510-9b3c81e9cebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404548159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3404548159
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3467407284
Short name T366
Test name
Test status
Simulation time 3326755794 ps
CPU time 14.05 seconds
Started Mar 28 01:09:56 PM PDT 24
Finished Mar 28 01:10:10 PM PDT 24
Peak memory 201152 kb
Host smart-97312338-de32-4a8c-90d6-2bc1103355d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467407284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3467407284
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1108249316
Short name T14
Test name
Test status
Simulation time 448460449 ps
CPU time 2.41 seconds
Started Mar 28 01:09:43 PM PDT 24
Finished Mar 28 01:09:46 PM PDT 24
Peak memory 200896 kb
Host smart-70f97b84-7f20-43ac-9dfd-5acd543c6e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108249316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1108249316
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1014260170
Short name T205
Test name
Test status
Simulation time 200200329 ps
CPU time 1.15 seconds
Started Mar 28 01:09:45 PM PDT 24
Finished Mar 28 01:09:47 PM PDT 24
Peak memory 200796 kb
Host smart-ee5a9cb0-662c-4515-8a85-32cfaf82461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014260170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1014260170
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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