Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8091

1

T1

23

T3

26

T5

21

auto[1]

10984

1

T1

21

T2

4

T3

30

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5840	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6499	1			T1	16		T2	2		T3	15
reset_info_cp[2]	2891	1			T1	5		T2	1		T3	7
reset_info_cp[4]	3883	1			T1	12		T2	1		T3	14
reset_info_cp[8]	123	1			T3	1		T7	1		T9	1
reset_info_cp[16]	109	1			T1	1		T5	1		T7	1
reset_info_cp[32]	124	1			T5	2		T7	2		T11	2
reset_info_cp[64]	112	1			T3	1		T7	1		T11	3
reset_info_cp[128]	114	1			T5	1		T7	3		T42	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3106	1			T1	7		T3	6		T5	21
reset_info_cp[1]	auto[1]	2773	1			T1	8		T2	1		T3	8
reset_info_cp[2]	auto[0]	939	1			T1	3		T3	3		T7	17
reset_info_cp[2]	auto[1]	1952	1			T1	2		T2	1		T3	4
reset_info_cp[4]	auto[0]	1397	1			T1	8		T3	3		T7	28
reset_info_cp[4]	auto[1]	2486	1			T1	4		T2	1		T3	11
reset_info_cp[8]	auto[0]	54	1			T7	1		T25	1		T40	1
reset_info_cp[8]	auto[1]	69	1			T3	1		T9	1		T46	1
reset_info_cp[16]	auto[0]	37	1			T7	1		T11	2		T45	1
reset_info_cp[16]	auto[1]	72	1			T1	1		T5	1		T9	1
reset_info_cp[32]	auto[0]	49	1			T7	2		T42	1		T45	1
reset_info_cp[32]	auto[1]	75	1			T5	2		T11	2		T21	1
reset_info_cp[64]	auto[0]	47	1			T3	1		T7	1		T11	2
reset_info_cp[64]	auto[1]	65	1			T11	1		T27	3		T45	1
reset_info_cp[128]	auto[0]	48	1			T42	1		T96	3		T97	1
reset_info_cp[128]	auto[1]	66	1			T5	1		T7	3		T45	2