Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8026

1

T1

18

T3

32

T5

21

auto[1]

11049

1

T1

26

T2

4

T3

24

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5840	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6499	1			T1	16		T2	2		T3	15
reset_info_cp[2]	2891	1			T1	5		T2	1		T3	7
reset_info_cp[4]	3883	1			T1	12		T2	1		T3	14
reset_info_cp[8]	123	1			T3	1		T7	1		T9	1
reset_info_cp[16]	109	1			T1	1		T5	1		T7	1
reset_info_cp[32]	124	1			T5	2		T7	2		T11	2
reset_info_cp[64]	112	1			T3	1		T7	1		T11	3
reset_info_cp[128]	114	1			T5	1		T7	3		T42	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3144	1			T1	7		T3	7		T5	21
reset_info_cp[1]	auto[1]	2735	1			T1	8		T2	1		T3	7
reset_info_cp[2]	auto[0]	863	1			T1	3		T3	3		T7	16
reset_info_cp[2]	auto[1]	2028	1			T1	2		T2	1		T3	4
reset_info_cp[4]	auto[0]	1390	1			T1	4		T3	8		T7	24
reset_info_cp[4]	auto[1]	2493	1			T1	8		T2	1		T3	6
reset_info_cp[8]	auto[0]	60	1			T25	1		T40	1		T79	2
reset_info_cp[8]	auto[1]	63	1			T3	1		T7	1		T9	1
reset_info_cp[16]	auto[0]	35	1			T11	1		T79	1		T80	1
reset_info_cp[16]	auto[1]	74	1			T1	1		T5	1		T7	1
reset_info_cp[32]	auto[0]	43	1			T7	1		T11	1		T42	1
reset_info_cp[32]	auto[1]	81	1			T5	2		T7	1		T11	1
reset_info_cp[64]	auto[0]	47	1			T7	1		T11	1		T45	1
reset_info_cp[64]	auto[1]	65	1			T3	1		T11	2		T27	3
reset_info_cp[128]	auto[0]	45	1			T7	1		T42	1		T80	1
reset_info_cp[128]	auto[1]	69	1			T5	1		T7	2		T45	2