Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/5.rstmgr_stress_all.1668268324 Mar 31 01:26:21 PM PDT 24 Mar 31 01:27:02 PM PDT 24 12058956817 ps
T537 /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1992084332 Mar 31 01:27:03 PM PDT 24 Mar 31 01:27:09 PM PDT 24 1221670739 ps
T538 /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.12321966 Mar 31 01:26:57 PM PDT 24 Mar 31 01:26:58 PM PDT 24 244071787 ps
T539 /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4119908069 Mar 31 01:27:33 PM PDT 24 Mar 31 01:27:39 PM PDT 24 1223253578 ps
T540 /workspace/coverage/default/16.rstmgr_reset.1578287227 Mar 31 01:26:41 PM PDT 24 Mar 31 01:26:46 PM PDT 24 1488798752 ps
T57 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1659568706 Mar 31 12:37:33 PM PDT 24 Mar 31 12:37:41 PM PDT 24 1547053093 ps
T58 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1408186634 Mar 31 12:37:25 PM PDT 24 Mar 31 12:37:28 PM PDT 24 803823310 ps
T59 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.158979221 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:31 PM PDT 24 85787127 ps
T60 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2901599247 Mar 31 12:37:36 PM PDT 24 Mar 31 12:37:38 PM PDT 24 417863217 ps
T61 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.19861399 Mar 31 12:37:23 PM PDT 24 Mar 31 12:37:25 PM PDT 24 198740790 ps
T62 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1299602696 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:33 PM PDT 24 127791350 ps
T541 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1594433618 Mar 31 12:37:22 PM PDT 24 Mar 31 12:37:24 PM PDT 24 144021951 ps
T63 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.290447475 Mar 31 12:37:47 PM PDT 24 Mar 31 12:37:49 PM PDT 24 137653652 ps
T83 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3321059661 Mar 31 12:37:35 PM PDT 24 Mar 31 12:37:37 PM PDT 24 181897259 ps
T542 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2734406586 Mar 31 12:37:58 PM PDT 24 Mar 31 12:37:59 PM PDT 24 77530727 ps
T100 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2442777152 Mar 31 12:37:36 PM PDT 24 Mar 31 12:37:38 PM PDT 24 211537533 ps
T64 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3052270610 Mar 31 12:37:25 PM PDT 24 Mar 31 12:37:28 PM PDT 24 413947647 ps
T101 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.886321853 Mar 31 12:38:02 PM PDT 24 Mar 31 12:38:03 PM PDT 24 65608239 ps
T84 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2696639582 Mar 31 12:37:26 PM PDT 24 Mar 31 12:37:30 PM PDT 24 449820362 ps
T88 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3659997698 Mar 31 12:37:34 PM PDT 24 Mar 31 12:37:40 PM PDT 24 495573251 ps
T85 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4121795851 Mar 31 12:37:27 PM PDT 24 Mar 31 12:37:33 PM PDT 24 682031945 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1276798339 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:34 PM PDT 24 807488459 ps
T544 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.536837891 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:37 PM PDT 24 802581287 ps
T102 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.103627863 Mar 31 12:37:34 PM PDT 24 Mar 31 12:37:35 PM PDT 24 69744882 ps
T86 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2591307996 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:30 PM PDT 24 123829503 ps
T103 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1768812093 Mar 31 12:37:25 PM PDT 24 Mar 31 12:37:26 PM PDT 24 67784910 ps
T87 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2178241703 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:34 PM PDT 24 145900407 ps
T89 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3102606371 Mar 31 12:37:55 PM PDT 24 Mar 31 12:37:58 PM PDT 24 416486490 ps
T545 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1400887428 Mar 31 12:37:28 PM PDT 24 Mar 31 12:37:29 PM PDT 24 79867242 ps
T546 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2184403115 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:33 PM PDT 24 130526677 ps
T104 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3543003735 Mar 31 12:37:28 PM PDT 24 Mar 31 12:37:29 PM PDT 24 163400776 ps
T105 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3427179162 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:32 PM PDT 24 106606939 ps
T106 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2878619879 Mar 31 12:37:23 PM PDT 24 Mar 31 12:37:26 PM PDT 24 227317251 ps
T547 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4226047772 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:31 PM PDT 24 191947096 ps
T121 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3909386250 Mar 31 12:37:26 PM PDT 24 Mar 31 12:37:29 PM PDT 24 817204043 ps
T548 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3831440507 Mar 31 12:37:27 PM PDT 24 Mar 31 12:37:28 PM PDT 24 144456917 ps
T112 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.839156503 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:28 PM PDT 24 955995375 ps
T549 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.591368166 Mar 31 12:37:23 PM PDT 24 Mar 31 12:37:26 PM PDT 24 119607723 ps
T550 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2628447986 Mar 31 12:37:51 PM PDT 24 Mar 31 12:37:53 PM PDT 24 169660538 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1550188044 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:33 PM PDT 24 216816190 ps
T92 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2494832020 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:26 PM PDT 24 87699971 ps
T552 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3846866248 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:33 PM PDT 24 100872442 ps
T553 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3187197845 Mar 31 12:37:27 PM PDT 24 Mar 31 12:37:32 PM PDT 24 729958189 ps
T107 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2324721475 Mar 31 12:37:26 PM PDT 24 Mar 31 12:37:27 PM PDT 24 88070852 ps
T113 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1606378247 Mar 31 12:37:25 PM PDT 24 Mar 31 12:37:28 PM PDT 24 787671622 ps
T108 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4186206217 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:33 PM PDT 24 256443091 ps
T554 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3394144384 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:34 PM PDT 24 422149546 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1017560921 Mar 31 12:37:23 PM PDT 24 Mar 31 12:37:25 PM PDT 24 81191581 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3293540548 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:35 PM PDT 24 83742528 ps
T557 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3207561445 Mar 31 12:37:33 PM PDT 24 Mar 31 12:37:35 PM PDT 24 212487990 ps
T122 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.496400944 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:32 PM PDT 24 883663518 ps
T558 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1971934180 Mar 31 12:37:33 PM PDT 24 Mar 31 12:37:39 PM PDT 24 81360276 ps
T559 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.510394475 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:34 PM PDT 24 417910651 ps
T560 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1387486370 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:33 PM PDT 24 424821081 ps
T561 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2713118395 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:35 PM PDT 24 334532989 ps
T562 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.831355751 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:33 PM PDT 24 75409455 ps
T114 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3470187150 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:35 PM PDT 24 849668333 ps
T563 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.121291763 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:33 PM PDT 24 95450973 ps
T564 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3820191600 Mar 31 12:37:47 PM PDT 24 Mar 31 12:37:49 PM PDT 24 97079871 ps
T565 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.537873901 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:26 PM PDT 24 133406856 ps
T566 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3418105706 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:27 PM PDT 24 201355922 ps
T567 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.960662550 Mar 31 12:37:23 PM PDT 24 Mar 31 12:37:26 PM PDT 24 175073912 ps
T568 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3762877738 Mar 31 12:37:34 PM PDT 24 Mar 31 12:37:36 PM PDT 24 173201587 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1848094138 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:35 PM PDT 24 873337576 ps
T570 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.868600953 Mar 31 12:37:25 PM PDT 24 Mar 31 12:37:26 PM PDT 24 199206839 ps
T571 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.349527455 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:29 PM PDT 24 61451193 ps
T572 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2063931394 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:34 PM PDT 24 198829000 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2185707518 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:30 PM PDT 24 1178418187 ps
T93 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2737209288 Mar 31 12:37:49 PM PDT 24 Mar 31 12:37:51 PM PDT 24 248692376 ps
T574 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2965688222 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:33 PM PDT 24 143943696 ps
T575 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.207091683 Mar 31 12:37:33 PM PDT 24 Mar 31 12:37:35 PM PDT 24 174822258 ps
T576 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.559442782 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:33 PM PDT 24 61857364 ps
T577 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2096279360 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:33 PM PDT 24 914531567 ps
T578 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.903249048 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:30 PM PDT 24 193948759 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.935993345 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:33 PM PDT 24 401279619 ps
T580 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4198540436 Mar 31 12:37:36 PM PDT 24 Mar 31 12:37:37 PM PDT 24 59867191 ps
T581 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.463302921 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:32 PM PDT 24 181606300 ps
T582 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3394578200 Mar 31 12:37:28 PM PDT 24 Mar 31 12:37:31 PM PDT 24 335567380 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.227761484 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:33 PM PDT 24 124321931 ps
T584 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3133801122 Mar 31 12:37:22 PM PDT 24 Mar 31 12:37:23 PM PDT 24 102780350 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2667482865 Mar 31 12:37:19 PM PDT 24 Mar 31 12:37:21 PM PDT 24 127405726 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.121596612 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:27 PM PDT 24 310620906 ps
T587 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1520556322 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:27 PM PDT 24 223748133 ps
T588 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2806039922 Mar 31 12:37:23 PM PDT 24 Mar 31 12:37:25 PM PDT 24 125787398 ps
T589 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4190582486 Mar 31 12:37:25 PM PDT 24 Mar 31 12:37:27 PM PDT 24 120861229 ps
T115 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2697363747 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:31 PM PDT 24 480652254 ps
T590 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.501147962 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:34 PM PDT 24 142332984 ps
T109 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4226342655 Mar 31 12:37:35 PM PDT 24 Mar 31 12:37:37 PM PDT 24 513998290 ps
T591 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3857774806 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:32 PM PDT 24 228401105 ps
T592 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3493899978 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:32 PM PDT 24 192442960 ps
T593 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2899827286 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:26 PM PDT 24 200042223 ps
T110 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1543743846 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:35 PM PDT 24 790544322 ps
T594 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1322867370 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:31 PM PDT 24 99410849 ps
T595 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4073537482 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:30 PM PDT 24 271074331 ps
T596 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2046603732 Mar 31 12:37:26 PM PDT 24 Mar 31 12:37:28 PM PDT 24 502494688 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2589967929 Mar 31 12:37:23 PM PDT 24 Mar 31 12:37:25 PM PDT 24 69780850 ps
T598 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2294488921 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:33 PM PDT 24 123531453 ps
T599 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.554239646 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:27 PM PDT 24 110952745 ps
T600 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1447765180 Mar 31 12:37:26 PM PDT 24 Mar 31 12:37:28 PM PDT 24 475205354 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.750744588 Mar 31 12:37:20 PM PDT 24 Mar 31 12:37:22 PM PDT 24 93658647 ps
T602 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2478138295 Mar 31 12:37:27 PM PDT 24 Mar 31 12:37:28 PM PDT 24 115114938 ps
T603 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.994219566 Mar 31 12:38:08 PM PDT 24 Mar 31 12:38:10 PM PDT 24 81945855 ps
T604 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.835875368 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:30 PM PDT 24 73526999 ps
T605 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.855652211 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:35 PM PDT 24 912712019 ps
T606 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3470990246 Mar 31 12:37:34 PM PDT 24 Mar 31 12:37:35 PM PDT 24 84235411 ps
T607 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4095117662 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:26 PM PDT 24 61331287 ps
T608 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1853867225 Mar 31 12:37:40 PM PDT 24 Mar 31 12:37:42 PM PDT 24 197442713 ps
T609 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3398894339 Mar 31 12:37:23 PM PDT 24 Mar 31 12:37:26 PM PDT 24 501074348 ps
T610 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1463067471 Mar 31 12:37:28 PM PDT 24 Mar 31 12:37:29 PM PDT 24 79451245 ps
T611 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.292564338 Mar 31 12:37:22 PM PDT 24 Mar 31 12:37:23 PM PDT 24 105987348 ps
T612 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.69027216 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:33 PM PDT 24 123162504 ps
T613 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3859339427 Mar 31 12:37:31 PM PDT 24 Mar 31 12:37:34 PM PDT 24 445500499 ps
T614 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1322728963 Mar 31 12:37:32 PM PDT 24 Mar 31 12:37:33 PM PDT 24 129610344 ps
T615 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2642716851 Mar 31 12:37:29 PM PDT 24 Mar 31 12:37:41 PM PDT 24 502251810 ps
T616 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.299072851 Mar 31 12:37:25 PM PDT 24 Mar 31 12:37:26 PM PDT 24 63409948 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2237004036 Mar 31 12:37:42 PM PDT 24 Mar 31 12:37:48 PM PDT 24 478622397 ps
T618 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.252212498 Mar 31 12:37:34 PM PDT 24 Mar 31 12:37:35 PM PDT 24 66870618 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.526160223 Mar 31 12:37:21 PM PDT 24 Mar 31 12:37:24 PM PDT 24 240148088 ps
T620 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1247131198 Mar 31 12:37:22 PM PDT 24 Mar 31 12:37:24 PM PDT 24 195609433 ps
T111 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4045837319 Mar 31 12:37:30 PM PDT 24 Mar 31 12:37:36 PM PDT 24 2224141519 ps

Test location /workspace/coverage/default/41.rstmgr_stress_all.2174654610
Short name T7
Test name
Test status
Simulation time 4937285835 ps
CPU time 22.62 seconds
Started Mar 31 01:27:30 PM PDT 24
Finished Mar 31 01:27:52 PM PDT 24
Peak memory 201156 kb
Host smart-cf77605e-0be3-4517-a28d-fb43a984a3d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174654610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2174654610
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.4034719087
Short name T23
Test name
Test status
Simulation time 140993805 ps
CPU time 1.79 seconds
Started Mar 31 01:27:04 PM PDT 24
Finished Mar 31 01:27:07 PM PDT 24
Peak memory 200864 kb
Host smart-b1b01335-08e8-4d3b-b77b-f5cda5b69e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034719087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.4034719087
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.19861399
Short name T61
Test name
Test status
Simulation time 198740790 ps
CPU time 1.32 seconds
Started Mar 31 12:37:23 PM PDT 24
Finished Mar 31 12:37:25 PM PDT 24
Peak memory 211444 kb
Host smart-59db8f55-bb12-40ab-8485-491eacf12b9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19861399 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.19861399
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2899827974
Short name T65
Test name
Test status
Simulation time 8318060278 ps
CPU time 14.83 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:36 PM PDT 24
Peak memory 221776 kb
Host smart-1cf1a8e4-352e-421c-a648-2384cc6bd322
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899827974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2899827974
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3978149975
Short name T9
Test name
Test status
Simulation time 1227166046 ps
CPU time 5.92 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:35 PM PDT 24
Peak memory 222536 kb
Host smart-c1cb568f-76b6-4074-adbc-6f3e64246b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978149975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3978149975
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.4254028479
Short name T80
Test name
Test status
Simulation time 11630587182 ps
CPU time 38.49 seconds
Started Mar 31 01:27:18 PM PDT 24
Finished Mar 31 01:27:57 PM PDT 24
Peak memory 209328 kb
Host smart-545367ac-d54f-4b8e-8c30-77c575fa43b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254028479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.4254028479
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1408186634
Short name T58
Test name
Test status
Simulation time 803823310 ps
CPU time 2.89 seconds
Started Mar 31 12:37:25 PM PDT 24
Finished Mar 31 12:37:28 PM PDT 24
Peak memory 200552 kb
Host smart-206c315e-0fca-4377-a537-ad9db398c104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408186634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1408186634
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4121795851
Short name T85
Test name
Test status
Simulation time 682031945 ps
CPU time 4.72 seconds
Started Mar 31 12:37:27 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 208792 kb
Host smart-c17c488e-3911-458e-a36a-027ee23e14c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121795851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4121795851
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1013095992
Short name T68
Test name
Test status
Simulation time 81276369 ps
CPU time 0.81 seconds
Started Mar 31 01:26:50 PM PDT 24
Finished Mar 31 01:26:51 PM PDT 24
Peak memory 200644 kb
Host smart-1c9e12ba-b735-4840-844e-cdd1cf5dde22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013095992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1013095992
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1613756510
Short name T43
Test name
Test status
Simulation time 161365333 ps
CPU time 1.16 seconds
Started Mar 31 01:26:53 PM PDT 24
Finished Mar 31 01:26:55 PM PDT 24
Peak memory 200824 kb
Host smart-249cfd4b-904a-47e0-b37d-32b5a9a2ffd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613756510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1613756510
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2538006818
Short name T32
Test name
Test status
Simulation time 1221087722 ps
CPU time 5.6 seconds
Started Mar 31 01:26:54 PM PDT 24
Finished Mar 31 01:27:00 PM PDT 24
Peak memory 217996 kb
Host smart-1721aad8-9e17-472d-a3cc-eddc4709ef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538006818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2538006818
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2513455070
Short name T145
Test name
Test status
Simulation time 108528322 ps
CPU time 0.98 seconds
Started Mar 31 01:26:33 PM PDT 24
Finished Mar 31 01:26:34 PM PDT 24
Peak memory 200836 kb
Host smart-02c3326e-3fe1-4cdd-82a3-e596b90e529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513455070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2513455070
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1543743846
Short name T110
Test name
Test status
Simulation time 790544322 ps
CPU time 3.19 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 200636 kb
Host smart-cb6c619a-db42-4174-bd74-1fe6525ecaa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543743846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1543743846
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.103627863
Short name T102
Test name
Test status
Simulation time 69744882 ps
CPU time 0.79 seconds
Started Mar 31 12:37:34 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 199576 kb
Host smart-c96c81ab-a066-446d-86ee-97508bfb5c55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103627863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.103627863
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2814054193
Short name T10
Test name
Test status
Simulation time 171488087 ps
CPU time 0.88 seconds
Started Mar 31 01:26:36 PM PDT 24
Finished Mar 31 01:26:36 PM PDT 24
Peak memory 200648 kb
Host smart-7bbef24d-2ca8-4037-a9e7-cb3ac8e4dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814054193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2814054193
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1132830846
Short name T130
Test name
Test status
Simulation time 243832946 ps
CPU time 1.08 seconds
Started Mar 31 01:26:15 PM PDT 24
Finished Mar 31 01:26:16 PM PDT 24
Peak memory 218264 kb
Host smart-7d131db1-82e9-49ee-8d04-7f64435e6f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132830846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1132830846
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.868760194
Short name T49
Test name
Test status
Simulation time 1234829828 ps
CPU time 6.03 seconds
Started Mar 31 01:26:46 PM PDT 24
Finished Mar 31 01:26:52 PM PDT 24
Peak memory 218460 kb
Host smart-daf9fa96-9a2a-4e58-80c8-a70698594064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868760194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.868760194
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2697363747
Short name T115
Test name
Test status
Simulation time 480652254 ps
CPU time 2.13 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:31 PM PDT 24
Peak memory 200632 kb
Host smart-d8de8de8-3e2e-461a-98ad-ca5fb969fc9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697363747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2697363747
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2737209288
Short name T93
Test name
Test status
Simulation time 248692376 ps
CPU time 1.71 seconds
Started Mar 31 12:37:49 PM PDT 24
Finished Mar 31 12:37:51 PM PDT 24
Peak memory 208772 kb
Host smart-6789dadc-1a05-48d2-a6a4-c91955baf5cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737209288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
737209288
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2185707518
Short name T573
Test name
Test status
Simulation time 1178418187 ps
CPU time 5.16 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:30 PM PDT 24
Peak memory 216872 kb
Host smart-0bbcc86d-ea13-4d28-9b1e-2f844ea20828
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185707518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
185707518
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2667482865
Short name T585
Test name
Test status
Simulation time 127405726 ps
CPU time 0.94 seconds
Started Mar 31 12:37:19 PM PDT 24
Finished Mar 31 12:37:21 PM PDT 24
Peak memory 200300 kb
Host smart-2d788a59-68b7-44f0-8b66-bc85356468c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667482865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
667482865
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.960662550
Short name T567
Test name
Test status
Simulation time 175073912 ps
CPU time 1.15 seconds
Started Mar 31 12:37:23 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 208688 kb
Host smart-66a1f318-1ab7-408f-b848-ae33b3264357
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960662550 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.960662550
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1017560921
Short name T555
Test name
Test status
Simulation time 81191581 ps
CPU time 0.82 seconds
Started Mar 31 12:37:23 PM PDT 24
Finished Mar 31 12:37:25 PM PDT 24
Peak memory 200396 kb
Host smart-73c710dd-afae-4ad0-93fa-b01d9d489f35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017560921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1017560921
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2806039922
Short name T588
Test name
Test status
Simulation time 125787398 ps
CPU time 1.02 seconds
Started Mar 31 12:37:23 PM PDT 24
Finished Mar 31 12:37:25 PM PDT 24
Peak memory 200436 kb
Host smart-8ebf3012-58b5-4c94-8726-b9774808a03d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806039922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2806039922
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2184403115
Short name T546
Test name
Test status
Simulation time 130526677 ps
CPU time 1.78 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 208864 kb
Host smart-5937ac93-709e-489d-9a1b-c75ffcd711ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184403115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2184403115
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3659997698
Short name T88
Test name
Test status
Simulation time 495573251 ps
CPU time 2.11 seconds
Started Mar 31 12:37:34 PM PDT 24
Finished Mar 31 12:37:40 PM PDT 24
Peak memory 200628 kb
Host smart-f3129615-5ff8-4d29-8172-aa85fa7b99ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659997698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3659997698
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.526160223
Short name T619
Test name
Test status
Simulation time 240148088 ps
CPU time 1.55 seconds
Started Mar 31 12:37:21 PM PDT 24
Finished Mar 31 12:37:24 PM PDT 24
Peak memory 200432 kb
Host smart-942e318b-d554-4d2e-8b7a-c3ea62812242
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526160223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.526160223
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1276798339
Short name T543
Test name
Test status
Simulation time 807488459 ps
CPU time 4.42 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:34 PM PDT 24
Peak memory 200556 kb
Host smart-97fa491d-e879-4c5e-bf07-7b79986bd173
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276798339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
276798339
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2494832020
Short name T92
Test name
Test status
Simulation time 87699971 ps
CPU time 0.85 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 200236 kb
Host smart-8a39a391-1894-4219-a6d1-941b8d9219c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494832020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
494832020
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1550188044
Short name T551
Test name
Test status
Simulation time 216816190 ps
CPU time 1.36 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 208604 kb
Host smart-cae732c1-7962-481e-b6f8-541b5dbd3f8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550188044 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1550188044
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.835875368
Short name T604
Test name
Test status
Simulation time 73526999 ps
CPU time 0.78 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:30 PM PDT 24
Peak memory 200296 kb
Host smart-679945e3-e8c4-42d6-9eb7-c317f3e15d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835875368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.835875368
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3293540548
Short name T556
Test name
Test status
Simulation time 83742528 ps
CPU time 0.93 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 200372 kb
Host smart-c89a43f4-5aab-477a-9d7e-d98ab6e08d02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293540548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3293540548
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2063931394
Short name T572
Test name
Test status
Simulation time 198829000 ps
CPU time 2.73 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:34 PM PDT 24
Peak memory 212360 kb
Host smart-40a1e05b-ebab-4013-914f-a9f075b97b73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063931394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2063931394
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.903249048
Short name T578
Test name
Test status
Simulation time 193948759 ps
CPU time 1.26 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:30 PM PDT 24
Peak memory 208612 kb
Host smart-612ff18a-d759-4f81-aa1b-bef9c5bce751
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903249048 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.903249048
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3857774806
Short name T591
Test name
Test status
Simulation time 228401105 ps
CPU time 1.54 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:32 PM PDT 24
Peak memory 200604 kb
Host smart-22c8ead0-6a52-49c6-8d1b-5f66cf79ad25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857774806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3857774806
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2696639582
Short name T84
Test name
Test status
Simulation time 449820362 ps
CPU time 3.47 seconds
Started Mar 31 12:37:26 PM PDT 24
Finished Mar 31 12:37:30 PM PDT 24
Peak memory 208804 kb
Host smart-5085614d-fec1-4585-b1fc-d4d12d7db7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696639582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2696639582
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.855652211
Short name T605
Test name
Test status
Simulation time 912712019 ps
CPU time 3.04 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 200588 kb
Host smart-ca54e34b-c485-4b5f-8e9a-fe4af0724069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855652211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.855652211
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1322728963
Short name T614
Test name
Test status
Simulation time 129610344 ps
CPU time 1 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200364 kb
Host smart-c0c81891-eeff-4aaf-99d7-6a4d21dfa51a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322728963 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1322728963
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3470990246
Short name T606
Test name
Test status
Simulation time 84235411 ps
CPU time 0.88 seconds
Started Mar 31 12:37:34 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 199508 kb
Host smart-bf92e994-0eed-4fd0-ba33-b86a037ba089
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470990246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3470990246
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2899827286
Short name T593
Test name
Test status
Simulation time 200042223 ps
CPU time 1.67 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 200620 kb
Host smart-2ea9a492-1544-4649-b00f-55e979dc03a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899827286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2899827286
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3394578200
Short name T582
Test name
Test status
Simulation time 335567380 ps
CPU time 2.33 seconds
Started Mar 31 12:37:28 PM PDT 24
Finished Mar 31 12:37:31 PM PDT 24
Peak memory 211516 kb
Host smart-ea7a173f-1872-471a-b67e-e8a48e570b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394578200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3394578200
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3470187150
Short name T114
Test name
Test status
Simulation time 849668333 ps
CPU time 2.86 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 200552 kb
Host smart-a894c7d3-0164-4222-b01a-46e3dd14c866
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470187150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3470187150
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.69027216
Short name T612
Test name
Test status
Simulation time 123162504 ps
CPU time 0.95 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200432 kb
Host smart-e6f195bb-a4cc-46c2-8597-e4cdf147e05b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69027216 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.69027216
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.559442782
Short name T576
Test name
Test status
Simulation time 61857364 ps
CPU time 0.76 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200372 kb
Host smart-608a3eed-5e69-4d20-94b2-cd80c7b7f4fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559442782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.559442782
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.831355751
Short name T562
Test name
Test status
Simulation time 75409455 ps
CPU time 0.94 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200424 kb
Host smart-040c2bd1-e781-4cc5-8d77-6743ded8d1f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831355751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.831355751
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2713118395
Short name T561
Test name
Test status
Simulation time 334532989 ps
CPU time 2.3 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 208820 kb
Host smart-40976048-8105-4f41-a016-c9f6176daed4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713118395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2713118395
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3909386250
Short name T121
Test name
Test status
Simulation time 817204043 ps
CPU time 2.82 seconds
Started Mar 31 12:37:26 PM PDT 24
Finished Mar 31 12:37:29 PM PDT 24
Peak memory 200576 kb
Host smart-22da6d3c-896b-4c59-bbef-60fff31087c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909386250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3909386250
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.537873901
Short name T565
Test name
Test status
Simulation time 133406856 ps
CPU time 1.05 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 200128 kb
Host smart-67b1a139-6aed-4f2a-a7e5-469d8d842071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537873901 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.537873901
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1400887428
Short name T545
Test name
Test status
Simulation time 79867242 ps
CPU time 0.86 seconds
Started Mar 31 12:37:28 PM PDT 24
Finished Mar 31 12:37:29 PM PDT 24
Peak memory 200372 kb
Host smart-7acb08d9-ab65-4c7c-856b-4a2ad705223e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400887428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1400887428
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2965688222
Short name T574
Test name
Test status
Simulation time 143943696 ps
CPU time 1.32 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200692 kb
Host smart-8fa5f674-9a8c-429f-92c4-8531e248eddb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965688222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2965688222
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2178241703
Short name T87
Test name
Test status
Simulation time 145900407 ps
CPU time 1.35 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:34 PM PDT 24
Peak memory 208636 kb
Host smart-63c9e14a-a4cb-481e-b43b-d918549f15f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178241703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2178241703
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2591307996
Short name T86
Test name
Test status
Simulation time 123829503 ps
CPU time 0.95 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:30 PM PDT 24
Peak memory 200424 kb
Host smart-4485c3ed-f902-43c4-9ca2-107f1ed63d9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591307996 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2591307996
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1768812093
Short name T103
Test name
Test status
Simulation time 67784910 ps
CPU time 0.78 seconds
Started Mar 31 12:37:25 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 200228 kb
Host smart-609e24e9-497f-4aed-aa53-3dd3a9939464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768812093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1768812093
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3493899978
Short name T592
Test name
Test status
Simulation time 192442960 ps
CPU time 1.49 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:32 PM PDT 24
Peak memory 200476 kb
Host smart-fdd7fb0c-45c5-4203-a505-b52a168c2900
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493899978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3493899978
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.554239646
Short name T599
Test name
Test status
Simulation time 110952745 ps
CPU time 1.58 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:27 PM PDT 24
Peak memory 210704 kb
Host smart-6af1c2e4-6411-424b-9d0e-06dde0406ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554239646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.554239646
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.839156503
Short name T112
Test name
Test status
Simulation time 955995375 ps
CPU time 3.29 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:28 PM PDT 24
Peak memory 200360 kb
Host smart-e812c4f9-2cd3-4c8a-83d3-1c64069915b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839156503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.839156503
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2628447986
Short name T550
Test name
Test status
Simulation time 169660538 ps
CPU time 1.66 seconds
Started Mar 31 12:37:51 PM PDT 24
Finished Mar 31 12:37:53 PM PDT 24
Peak memory 208904 kb
Host smart-ea95d007-f754-49aa-8b8e-872f6a8576d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628447986 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2628447986
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2734406586
Short name T542
Test name
Test status
Simulation time 77530727 ps
CPU time 0.79 seconds
Started Mar 31 12:37:58 PM PDT 24
Finished Mar 31 12:37:59 PM PDT 24
Peak memory 200396 kb
Host smart-d0dff84b-3b19-49e5-9709-72672186bb8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734406586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2734406586
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3427179162
Short name T105
Test name
Test status
Simulation time 106606939 ps
CPU time 1.23 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:32 PM PDT 24
Peak memory 200604 kb
Host smart-2f49f651-a512-4922-b337-0414d7783c9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427179162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3427179162
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3859339427
Short name T613
Test name
Test status
Simulation time 445500499 ps
CPU time 2.92 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:34 PM PDT 24
Peak memory 208788 kb
Host smart-23a88e68-f459-4665-a18f-0c4f857fe593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859339427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3859339427
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4226342655
Short name T109
Test name
Test status
Simulation time 513998290 ps
CPU time 1.91 seconds
Started Mar 31 12:37:35 PM PDT 24
Finished Mar 31 12:37:37 PM PDT 24
Peak memory 200532 kb
Host smart-617f7d10-e845-4b4a-8ef8-b136e26529b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226342655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4226342655
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3762877738
Short name T568
Test name
Test status
Simulation time 173201587 ps
CPU time 1.27 seconds
Started Mar 31 12:37:34 PM PDT 24
Finished Mar 31 12:37:36 PM PDT 24
Peak memory 200556 kb
Host smart-cc8e4d17-59cd-443e-ab7e-af0fd5064f7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762877738 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3762877738
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.4198540436
Short name T580
Test name
Test status
Simulation time 59867191 ps
CPU time 0.75 seconds
Started Mar 31 12:37:36 PM PDT 24
Finished Mar 31 12:37:37 PM PDT 24
Peak memory 200380 kb
Host smart-b1fb8362-e429-4d46-9c58-241a04719707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198540436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.4198540436
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3820191600
Short name T564
Test name
Test status
Simulation time 97079871 ps
CPU time 1.23 seconds
Started Mar 31 12:37:47 PM PDT 24
Finished Mar 31 12:37:49 PM PDT 24
Peak memory 200628 kb
Host smart-f7eb67fb-988d-4b69-852c-a6b5efe4fb8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820191600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3820191600
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3394144384
Short name T554
Test name
Test status
Simulation time 422149546 ps
CPU time 3.1 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:34 PM PDT 24
Peak memory 208752 kb
Host smart-f7d310bd-87dc-4b20-ac21-5eae9186efa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394144384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3394144384
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2096279360
Short name T577
Test name
Test status
Simulation time 914531567 ps
CPU time 3.06 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200592 kb
Host smart-1973726a-fdc8-4ff2-924e-d0cd27df68a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096279360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2096279360
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.290447475
Short name T63
Test name
Test status
Simulation time 137653652 ps
CPU time 1.06 seconds
Started Mar 31 12:37:47 PM PDT 24
Finished Mar 31 12:37:49 PM PDT 24
Peak memory 200420 kb
Host smart-594e9c51-98a3-404f-b342-7b938a037d5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290447475 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.290447475
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.886321853
Short name T101
Test name
Test status
Simulation time 65608239 ps
CPU time 0.73 seconds
Started Mar 31 12:38:02 PM PDT 24
Finished Mar 31 12:38:03 PM PDT 24
Peak memory 200404 kb
Host smart-faff6b18-0d1a-4b93-bceb-80c90df764b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886321853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.886321853
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.158979221
Short name T59
Test name
Test status
Simulation time 85787127 ps
CPU time 1 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:31 PM PDT 24
Peak memory 200428 kb
Host smart-306dc587-fa51-4520-9755-b8747b2b4b32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158979221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.158979221
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.510394475
Short name T559
Test name
Test status
Simulation time 417910651 ps
CPU time 3.19 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:34 PM PDT 24
Peak memory 208792 kb
Host smart-4d59dd99-ccde-446e-9791-4ed7215ff630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510394475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.510394475
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1853867225
Short name T608
Test name
Test status
Simulation time 197442713 ps
CPU time 1.28 seconds
Started Mar 31 12:37:40 PM PDT 24
Finished Mar 31 12:37:42 PM PDT 24
Peak memory 208636 kb
Host smart-b68a8153-0b9a-4011-9749-ce982bc4458c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853867225 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1853867225
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.252212498
Short name T618
Test name
Test status
Simulation time 66870618 ps
CPU time 0.81 seconds
Started Mar 31 12:37:34 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 200280 kb
Host smart-3c0f5ea8-5697-4748-8f2d-1a9473903b82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252212498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.252212498
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1322867370
Short name T594
Test name
Test status
Simulation time 99410849 ps
CPU time 1.22 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:31 PM PDT 24
Peak memory 200588 kb
Host smart-515bc25f-1343-4a77-b6be-86bfa678a1d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322867370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1322867370
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3102606371
Short name T89
Test name
Test status
Simulation time 416486490 ps
CPU time 3.06 seconds
Started Mar 31 12:37:55 PM PDT 24
Finished Mar 31 12:37:58 PM PDT 24
Peak memory 212356 kb
Host smart-4c44e774-b27f-4c12-9901-3309c46be158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102606371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3102606371
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2901599247
Short name T60
Test name
Test status
Simulation time 417863217 ps
CPU time 1.89 seconds
Started Mar 31 12:37:36 PM PDT 24
Finished Mar 31 12:37:38 PM PDT 24
Peak memory 200596 kb
Host smart-b1f1f27e-8e3c-4dc6-b7d3-4ed0283c25a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901599247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2901599247
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4226047772
Short name T547
Test name
Test status
Simulation time 191947096 ps
CPU time 1.38 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:31 PM PDT 24
Peak memory 208860 kb
Host smart-3b9280dd-609c-4400-8722-929bf1c9456c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226047772 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4226047772
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.994219566
Short name T603
Test name
Test status
Simulation time 81945855 ps
CPU time 0.91 seconds
Started Mar 31 12:38:08 PM PDT 24
Finished Mar 31 12:38:10 PM PDT 24
Peak memory 200496 kb
Host smart-970fc74b-ee1a-4f04-9384-d8c48d2592f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994219566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.994219566
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.121291763
Short name T563
Test name
Test status
Simulation time 95450973 ps
CPU time 1.17 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200692 kb
Host smart-edde6243-1e3c-4bcd-9655-1a2975983354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121291763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.121291763
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3846866248
Short name T552
Test name
Test status
Simulation time 100872442 ps
CPU time 1.44 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 208748 kb
Host smart-e0a15da9-0944-4611-afef-e3934741d85a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846866248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3846866248
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1387486370
Short name T560
Test name
Test status
Simulation time 424821081 ps
CPU time 1.79 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200584 kb
Host smart-0fca6f41-a89d-4fd5-9062-1cb77c3928ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387486370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1387486370
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3133801122
Short name T584
Test name
Test status
Simulation time 102780350 ps
CPU time 1.37 seconds
Started Mar 31 12:37:22 PM PDT 24
Finished Mar 31 12:37:23 PM PDT 24
Peak memory 200420 kb
Host smart-41eb6f5d-4d7c-4de7-b132-88eb9bee85d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133801122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
133801122
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.536837891
Short name T544
Test name
Test status
Simulation time 802581287 ps
CPU time 4.42 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:37 PM PDT 24
Peak memory 200556 kb
Host smart-82b2c1a5-5340-4a05-a008-e474011d0821
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536837891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.536837891
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.292564338
Short name T611
Test name
Test status
Simulation time 105987348 ps
CPU time 0.84 seconds
Started Mar 31 12:37:22 PM PDT 24
Finished Mar 31 12:37:23 PM PDT 24
Peak memory 200308 kb
Host smart-827f3393-c7ad-4f39-852a-d66d3af67a7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292564338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.292564338
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3207561445
Short name T557
Test name
Test status
Simulation time 212487990 ps
CPU time 1.22 seconds
Started Mar 31 12:37:33 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 208704 kb
Host smart-1aa05aed-3864-4083-87c3-113cad7bff61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207561445 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3207561445
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.750744588
Short name T601
Test name
Test status
Simulation time 93658647 ps
CPU time 0.87 seconds
Started Mar 31 12:37:20 PM PDT 24
Finished Mar 31 12:37:22 PM PDT 24
Peak memory 200384 kb
Host smart-9c3b7b01-d1e0-4f7d-a00f-cca5d698d9c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750744588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.750744588
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3543003735
Short name T104
Test name
Test status
Simulation time 163400776 ps
CPU time 1.25 seconds
Started Mar 31 12:37:28 PM PDT 24
Finished Mar 31 12:37:29 PM PDT 24
Peak memory 200456 kb
Host smart-f13d6713-28b5-4a56-9d33-4faa877dbe5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543003735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3543003735
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.227761484
Short name T583
Test name
Test status
Simulation time 124321931 ps
CPU time 1.89 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 217080 kb
Host smart-8302f66a-287f-4625-89fc-17a7d021e293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227761484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.227761484
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1606378247
Short name T113
Test name
Test status
Simulation time 787671622 ps
CPU time 3.18 seconds
Started Mar 31 12:37:25 PM PDT 24
Finished Mar 31 12:37:28 PM PDT 24
Peak memory 200608 kb
Host smart-6c9a346a-86b4-4cb0-bedb-6c897bd5c7bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606378247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1606378247
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2478138295
Short name T602
Test name
Test status
Simulation time 115114938 ps
CPU time 1.34 seconds
Started Mar 31 12:37:27 PM PDT 24
Finished Mar 31 12:37:28 PM PDT 24
Peak memory 200528 kb
Host smart-aea05b0f-551c-4e4e-82cf-810baf38df80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478138295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
478138295
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2237004036
Short name T617
Test name
Test status
Simulation time 478622397 ps
CPU time 5.63 seconds
Started Mar 31 12:37:42 PM PDT 24
Finished Mar 31 12:37:48 PM PDT 24
Peak memory 200512 kb
Host smart-d267d933-c983-442c-a528-bfa0aae3280b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237004036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
237004036
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1594433618
Short name T541
Test name
Test status
Simulation time 144021951 ps
CPU time 0.94 seconds
Started Mar 31 12:37:22 PM PDT 24
Finished Mar 31 12:37:24 PM PDT 24
Peak memory 200292 kb
Host smart-7397c871-e936-4625-8b77-b01601789e45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594433618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
594433618
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1247131198
Short name T620
Test name
Test status
Simulation time 195609433 ps
CPU time 1.3 seconds
Started Mar 31 12:37:22 PM PDT 24
Finished Mar 31 12:37:24 PM PDT 24
Peak memory 208632 kb
Host smart-a7a7ba56-9a20-4801-8fae-33c9c97d4034
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247131198 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1247131198
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2324721475
Short name T107
Test name
Test status
Simulation time 88070852 ps
CPU time 0.87 seconds
Started Mar 31 12:37:26 PM PDT 24
Finished Mar 31 12:37:27 PM PDT 24
Peak memory 200320 kb
Host smart-ef4766dc-8719-4598-90e6-569cae4ee7f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324721475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2324721475
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4186206217
Short name T108
Test name
Test status
Simulation time 256443091 ps
CPU time 1.76 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 208788 kb
Host smart-d526bb77-2d10-4186-b667-a39dbfab56d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186206217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4186206217
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.121596612
Short name T586
Test name
Test status
Simulation time 310620906 ps
CPU time 2.34 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:27 PM PDT 24
Peak memory 208676 kb
Host smart-1494175c-17a5-4fc2-8557-1803e8b508a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121596612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.121596612
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1447765180
Short name T600
Test name
Test status
Simulation time 475205354 ps
CPU time 1.9 seconds
Started Mar 31 12:37:26 PM PDT 24
Finished Mar 31 12:37:28 PM PDT 24
Peak memory 200580 kb
Host smart-87760fff-a1c7-4c33-8454-db195230e38e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447765180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1447765180
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.935993345
Short name T579
Test name
Test status
Simulation time 401279619 ps
CPU time 2.51 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200596 kb
Host smart-e9566718-9b18-40f7-b730-e06769da03bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935993345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.935993345
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1659568706
Short name T57
Test name
Test status
Simulation time 1547053093 ps
CPU time 7.77 seconds
Started Mar 31 12:37:33 PM PDT 24
Finished Mar 31 12:37:41 PM PDT 24
Peak memory 200520 kb
Host smart-75dd51ac-ba11-40b4-8440-f13a7513c264
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659568706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
659568706
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3831440507
Short name T548
Test name
Test status
Simulation time 144456917 ps
CPU time 0.96 seconds
Started Mar 31 12:37:27 PM PDT 24
Finished Mar 31 12:37:28 PM PDT 24
Peak memory 200288 kb
Host smart-0e489973-c076-423a-a37e-a452226318c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831440507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
831440507
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.207091683
Short name T575
Test name
Test status
Simulation time 174822258 ps
CPU time 1.73 seconds
Started Mar 31 12:37:33 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 208816 kb
Host smart-97b495d3-6b4d-4062-81af-a9fda736cdae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207091683 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.207091683
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2589967929
Short name T597
Test name
Test status
Simulation time 69780850 ps
CPU time 0.82 seconds
Started Mar 31 12:37:23 PM PDT 24
Finished Mar 31 12:37:25 PM PDT 24
Peak memory 200360 kb
Host smart-ccc039c4-df87-43c0-94ac-257bc6c2a9d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589967929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2589967929
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2442777152
Short name T100
Test name
Test status
Simulation time 211537533 ps
CPU time 1.47 seconds
Started Mar 31 12:37:36 PM PDT 24
Finished Mar 31 12:37:38 PM PDT 24
Peak memory 200644 kb
Host smart-9616f9c8-8bfd-4288-9880-784614ad0880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442777152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2442777152
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3187197845
Short name T553
Test name
Test status
Simulation time 729958189 ps
CPU time 4.91 seconds
Started Mar 31 12:37:27 PM PDT 24
Finished Mar 31 12:37:32 PM PDT 24
Peak memory 208848 kb
Host smart-18533ac2-a4bc-410b-9c80-d191e519044b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187197845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3187197845
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1848094138
Short name T569
Test name
Test status
Simulation time 873337576 ps
CPU time 3.24 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:35 PM PDT 24
Peak memory 200660 kb
Host smart-99595d7d-f3f7-47b7-9863-30a47a3ce21d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848094138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1848094138
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.591368166
Short name T549
Test name
Test status
Simulation time 119607723 ps
CPU time 1.23 seconds
Started Mar 31 12:37:23 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 208624 kb
Host smart-8e9783d3-9d29-4641-961d-a6a21d3ff775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591368166 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.591368166
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1971934180
Short name T558
Test name
Test status
Simulation time 81360276 ps
CPU time 0.94 seconds
Started Mar 31 12:37:33 PM PDT 24
Finished Mar 31 12:37:39 PM PDT 24
Peak memory 200372 kb
Host smart-cedfd927-c2ff-4bb8-b958-979bbf66904f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971934180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1971934180
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4073537482
Short name T595
Test name
Test status
Simulation time 271074331 ps
CPU time 1.69 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:30 PM PDT 24
Peak memory 200672 kb
Host smart-ecdcd7c3-4a51-4109-8c57-6d0385ac46d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073537482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4073537482
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3418105706
Short name T566
Test name
Test status
Simulation time 201355922 ps
CPU time 2.69 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:27 PM PDT 24
Peak memory 208816 kb
Host smart-3b8fd524-8cbd-4be3-a429-2f85b98efec8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418105706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3418105706
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4045837319
Short name T111
Test name
Test status
Simulation time 2224141519 ps
CPU time 5.43 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:36 PM PDT 24
Peak memory 200696 kb
Host smart-beff9099-0249-4f20-b324-cb2a843f237c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045837319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.4045837319
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.868600953
Short name T570
Test name
Test status
Simulation time 199206839 ps
CPU time 1.21 seconds
Started Mar 31 12:37:25 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 208600 kb
Host smart-045a90c5-4365-4a81-bcb9-f3b08293ef49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868600953 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.868600953
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1463067471
Short name T610
Test name
Test status
Simulation time 79451245 ps
CPU time 0.81 seconds
Started Mar 31 12:37:28 PM PDT 24
Finished Mar 31 12:37:29 PM PDT 24
Peak memory 200364 kb
Host smart-ee36f7bc-66f0-4808-b084-38bb6d1190af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463067471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1463067471
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1520556322
Short name T587
Test name
Test status
Simulation time 223748133 ps
CPU time 1.64 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:27 PM PDT 24
Peak memory 200532 kb
Host smart-d4a933c7-1147-4d2d-ba97-0aa714d49a6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520556322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1520556322
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3398894339
Short name T609
Test name
Test status
Simulation time 501074348 ps
CPU time 2.05 seconds
Started Mar 31 12:37:23 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 200644 kb
Host smart-d3ffbdae-6d69-4e11-a4f8-cbd1a7711324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398894339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3398894339
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.299072851
Short name T616
Test name
Test status
Simulation time 63409948 ps
CPU time 0.72 seconds
Started Mar 31 12:37:25 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 200208 kb
Host smart-d6c5d08e-5cc9-4055-a986-3e2750271647
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299072851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.299072851
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2878619879
Short name T106
Test name
Test status
Simulation time 227317251 ps
CPU time 1.47 seconds
Started Mar 31 12:37:23 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 200672 kb
Host smart-fcb02e21-7db9-4d97-a23f-de79e5bb023c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878619879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2878619879
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3052270610
Short name T64
Test name
Test status
Simulation time 413947647 ps
CPU time 3.05 seconds
Started Mar 31 12:37:25 PM PDT 24
Finished Mar 31 12:37:28 PM PDT 24
Peak memory 208724 kb
Host smart-274dbde8-da06-4656-b99c-cee6ebe8993f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052270610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3052270610
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2046603732
Short name T596
Test name
Test status
Simulation time 502494688 ps
CPU time 2 seconds
Started Mar 31 12:37:26 PM PDT 24
Finished Mar 31 12:37:28 PM PDT 24
Peak memory 200608 kb
Host smart-95e60c4a-4379-465f-b7c4-255d5070b672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046603732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2046603732
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1299602696
Short name T62
Test name
Test status
Simulation time 127791350 ps
CPU time 0.97 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200428 kb
Host smart-2d6615de-2dd0-47df-94cc-1f8620547dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299602696 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1299602696
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4095117662
Short name T607
Test name
Test status
Simulation time 61331287 ps
CPU time 0.81 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:26 PM PDT 24
Peak memory 200288 kb
Host smart-baa6ae2a-0ada-4881-a9de-d955a2140e63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095117662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4095117662
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.463302921
Short name T581
Test name
Test status
Simulation time 181606300 ps
CPU time 1.34 seconds
Started Mar 31 12:37:30 PM PDT 24
Finished Mar 31 12:37:32 PM PDT 24
Peak memory 200644 kb
Host smart-f0b4af31-5782-4b1c-8d97-fa8e907084de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463302921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.463302921
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2294488921
Short name T598
Test name
Test status
Simulation time 123531453 ps
CPU time 1.63 seconds
Started Mar 31 12:37:31 PM PDT 24
Finished Mar 31 12:37:33 PM PDT 24
Peak memory 200736 kb
Host smart-43c5d216-1334-4794-b583-24a4c5f802ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294488921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2294488921
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.496400944
Short name T122
Test name
Test status
Simulation time 883663518 ps
CPU time 3.34 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:32 PM PDT 24
Peak memory 200748 kb
Host smart-eb204728-fa76-4bad-82cd-fa2923e44af4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496400944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
496400944
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3321059661
Short name T83
Test name
Test status
Simulation time 181897259 ps
CPU time 1.63 seconds
Started Mar 31 12:37:35 PM PDT 24
Finished Mar 31 12:37:37 PM PDT 24
Peak memory 208860 kb
Host smart-0cb0b3a2-21e0-468a-93a4-6c4cbf0022e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321059661 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3321059661
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.349527455
Short name T571
Test name
Test status
Simulation time 61451193 ps
CPU time 0.81 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:29 PM PDT 24
Peak memory 200492 kb
Host smart-1eff7c7d-39e2-4ebe-adb8-63977fd95c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349527455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.349527455
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4190582486
Short name T589
Test name
Test status
Simulation time 120861229 ps
CPU time 1.14 seconds
Started Mar 31 12:37:25 PM PDT 24
Finished Mar 31 12:37:27 PM PDT 24
Peak memory 200348 kb
Host smart-859b00ee-ff28-40bf-aea9-1fabe6ebefe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190582486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4190582486
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.501147962
Short name T590
Test name
Test status
Simulation time 142332984 ps
CPU time 1.9 seconds
Started Mar 31 12:37:32 PM PDT 24
Finished Mar 31 12:37:34 PM PDT 24
Peak memory 208816 kb
Host smart-78634a6d-384b-4866-b242-3150e0985aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501147962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.501147962
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2642716851
Short name T615
Test name
Test status
Simulation time 502251810 ps
CPU time 1.91 seconds
Started Mar 31 12:37:29 PM PDT 24
Finished Mar 31 12:37:41 PM PDT 24
Peak memory 200624 kb
Host smart-e6981619-1ded-48c5-a0a6-ee3f21ce39ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642716851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2642716851
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2428566403
Short name T303
Test name
Test status
Simulation time 71244317 ps
CPU time 0.78 seconds
Started Mar 31 01:26:14 PM PDT 24
Finished Mar 31 01:26:15 PM PDT 24
Peak memory 200708 kb
Host smart-05689b76-2f24-4538-8a06-cf8fddd4b8c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428566403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2428566403
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1706082284
Short name T531
Test name
Test status
Simulation time 1907221236 ps
CPU time 7.09 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:18 PM PDT 24
Peak memory 218392 kb
Host smart-6aee6a8a-3490-42c9-89ad-aa44e8f1889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706082284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1706082284
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.367508219
Short name T409
Test name
Test status
Simulation time 98194749 ps
CPU time 0.81 seconds
Started Mar 31 01:26:22 PM PDT 24
Finished Mar 31 01:26:23 PM PDT 24
Peak memory 200636 kb
Host smart-ee82d4ac-9d67-46c1-a03b-9c3ba4d1573a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367508219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.367508219
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2409645998
Short name T357
Test name
Test status
Simulation time 623412052 ps
CPU time 3.49 seconds
Started Mar 31 01:26:22 PM PDT 24
Finished Mar 31 01:26:25 PM PDT 24
Peak memory 200928 kb
Host smart-47e2e66c-aa95-44e5-ad01-ad067b062f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409645998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2409645998
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.157482360
Short name T71
Test name
Test status
Simulation time 16517204753 ps
CPU time 31.6 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:42 PM PDT 24
Peak memory 218848 kb
Host smart-3039db1c-bc8a-4f7f-85e6-dea9667b17f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157482360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.157482360
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2784722870
Short name T127
Test name
Test status
Simulation time 102660655 ps
CPU time 1.03 seconds
Started Mar 31 01:26:15 PM PDT 24
Finished Mar 31 01:26:16 PM PDT 24
Peak memory 200812 kb
Host smart-c255cc23-0827-4db3-b7c6-300e182752a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784722870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2784722870
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1604727897
Short name T230
Test name
Test status
Simulation time 119318496 ps
CPU time 1.24 seconds
Started Mar 31 01:26:15 PM PDT 24
Finished Mar 31 01:26:16 PM PDT 24
Peak memory 201020 kb
Host smart-ab3ca8d3-fa43-41d2-b2fc-5a70a50a7109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604727897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1604727897
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.4272978830
Short name T271
Test name
Test status
Simulation time 869463270 ps
CPU time 4.52 seconds
Started Mar 31 01:26:23 PM PDT 24
Finished Mar 31 01:26:27 PM PDT 24
Peak memory 200960 kb
Host smart-9bcfe9c3-dc7b-494e-b5f9-47dab98d3347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272978830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4272978830
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1746412872
Short name T235
Test name
Test status
Simulation time 266368269 ps
CPU time 1.89 seconds
Started Mar 31 01:26:10 PM PDT 24
Finished Mar 31 01:26:12 PM PDT 24
Peak memory 200856 kb
Host smart-6cdff0cf-474f-4fbe-9967-2d69a7f70e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746412872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1746412872
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3337480493
Short name T258
Test name
Test status
Simulation time 202158000 ps
CPU time 1.27 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:23 PM PDT 24
Peak memory 200764 kb
Host smart-26fa79f6-57f7-4713-95a8-f01c66f495e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337480493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3337480493
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3457930108
Short name T160
Test name
Test status
Simulation time 67912013 ps
CPU time 0.73 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:11 PM PDT 24
Peak memory 200664 kb
Host smart-1669f2e2-f81f-4ebe-a54f-924ab613d8d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457930108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3457930108
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1281075483
Short name T428
Test name
Test status
Simulation time 2156932532 ps
CPU time 7.34 seconds
Started Mar 31 01:26:13 PM PDT 24
Finished Mar 31 01:26:20 PM PDT 24
Peak memory 218072 kb
Host smart-0c6ca5d9-1122-47cb-bfa8-69a388b3c0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281075483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1281075483
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2866069154
Short name T170
Test name
Test status
Simulation time 244482939 ps
CPU time 1.12 seconds
Started Mar 31 01:26:16 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 218112 kb
Host smart-2622636e-a681-42c8-b2d6-977a3afef705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866069154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2866069154
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2871717348
Short name T371
Test name
Test status
Simulation time 111816781 ps
CPU time 0.8 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:11 PM PDT 24
Peak memory 200676 kb
Host smart-0de7dfca-1575-4c49-a036-d911e51c0c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871717348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2871717348
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2733013966
Short name T528
Test name
Test status
Simulation time 987031647 ps
CPU time 5.35 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:27 PM PDT 24
Peak memory 200948 kb
Host smart-b007f561-671c-46b1-887d-777586ac8fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733013966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2733013966
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1837140361
Short name T72
Test name
Test status
Simulation time 8366433964 ps
CPU time 13.68 seconds
Started Mar 31 01:26:14 PM PDT 24
Finished Mar 31 01:26:28 PM PDT 24
Peak memory 217820 kb
Host smart-6c136073-c7a5-4573-97a8-9440a2a02d4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837140361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1837140361
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.667183722
Short name T392
Test name
Test status
Simulation time 145951262 ps
CPU time 1.17 seconds
Started Mar 31 01:26:15 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 200808 kb
Host smart-50378623-755f-4a13-9b9f-0140559cda5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667183722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.667183722
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.4294203472
Short name T234
Test name
Test status
Simulation time 123952991 ps
CPU time 1.15 seconds
Started Mar 31 01:26:12 PM PDT 24
Finished Mar 31 01:26:13 PM PDT 24
Peak memory 200912 kb
Host smart-04a05e14-c131-42b4-b368-b63e77485571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294203472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4294203472
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1411698869
Short name T515
Test name
Test status
Simulation time 11075083904 ps
CPU time 39.88 seconds
Started Mar 31 01:26:08 PM PDT 24
Finished Mar 31 01:26:48 PM PDT 24
Peak memory 201120 kb
Host smart-10ecfe8f-3f11-46c0-8a02-80ec471e8b66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411698869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1411698869
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3252000121
Short name T281
Test name
Test status
Simulation time 121456531 ps
CPU time 1.48 seconds
Started Mar 31 01:26:09 PM PDT 24
Finished Mar 31 01:26:11 PM PDT 24
Peak memory 200816 kb
Host smart-f58b8786-3d3f-41c1-af9a-0a8c43b728b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252000121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3252000121
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2850930392
Short name T325
Test name
Test status
Simulation time 151531834 ps
CPU time 1.26 seconds
Started Mar 31 01:26:12 PM PDT 24
Finished Mar 31 01:26:13 PM PDT 24
Peak memory 201004 kb
Host smart-84e452b1-1e88-4969-9172-ddd0b0ad9922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850930392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2850930392
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3367587473
Short name T445
Test name
Test status
Simulation time 65522127 ps
CPU time 0.81 seconds
Started Mar 31 01:26:37 PM PDT 24
Finished Mar 31 01:26:38 PM PDT 24
Peak memory 200728 kb
Host smart-34356a25-8684-46d2-a7c3-6eeb85322237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367587473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3367587473
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.414608599
Short name T34
Test name
Test status
Simulation time 1903759499 ps
CPU time 7.23 seconds
Started Mar 31 01:26:41 PM PDT 24
Finished Mar 31 01:26:49 PM PDT 24
Peak memory 218360 kb
Host smart-283de891-42b5-440f-89da-a154d53a962f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414608599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.414608599
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.619153246
Short name T372
Test name
Test status
Simulation time 244991639 ps
CPU time 1.03 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:36 PM PDT 24
Peak memory 218104 kb
Host smart-9662513f-2b65-47d5-baf1-ce6d09027ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619153246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.619153246
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2567123324
Short name T427
Test name
Test status
Simulation time 82022229 ps
CPU time 0.83 seconds
Started Mar 31 01:26:35 PM PDT 24
Finished Mar 31 01:26:36 PM PDT 24
Peak memory 200708 kb
Host smart-8360f596-4ecb-475e-ba9c-948f99622f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567123324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2567123324
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.548472955
Short name T398
Test name
Test status
Simulation time 891867012 ps
CPU time 4.42 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:39 PM PDT 24
Peak memory 201132 kb
Host smart-34497fd5-6e68-4f47-b38b-ccace0d3b557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548472955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.548472955
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2481149661
Short name T286
Test name
Test status
Simulation time 142820228 ps
CPU time 1.07 seconds
Started Mar 31 01:26:41 PM PDT 24
Finished Mar 31 01:26:42 PM PDT 24
Peak memory 200812 kb
Host smart-ff90b31d-2ab7-4738-b9bd-e85ff4c52650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481149661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2481149661
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.14147536
Short name T288
Test name
Test status
Simulation time 251488329 ps
CPU time 1.56 seconds
Started Mar 31 01:26:29 PM PDT 24
Finished Mar 31 01:26:31 PM PDT 24
Peak memory 201020 kb
Host smart-b53354ab-0fb9-4e8b-b17f-645bd9acbf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14147536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.14147536
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.740048996
Short name T238
Test name
Test status
Simulation time 2135209698 ps
CPU time 10.09 seconds
Started Mar 31 01:26:32 PM PDT 24
Finished Mar 31 01:26:42 PM PDT 24
Peak memory 201032 kb
Host smart-086c01e9-135f-41bb-837c-ad87042c3b6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740048996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.740048996
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1671406493
Short name T232
Test name
Test status
Simulation time 484495060 ps
CPU time 2.54 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:37 PM PDT 24
Peak memory 200916 kb
Host smart-a3f41e9d-eee5-4ed9-9dac-5d8be5141bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671406493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1671406493
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3705829463
Short name T369
Test name
Test status
Simulation time 125571099 ps
CPU time 1.02 seconds
Started Mar 31 01:26:36 PM PDT 24
Finished Mar 31 01:26:38 PM PDT 24
Peak memory 200808 kb
Host smart-b466c874-35ea-4bb2-bbab-33acbb9da3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705829463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3705829463
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1816916896
Short name T216
Test name
Test status
Simulation time 74742340 ps
CPU time 0.84 seconds
Started Mar 31 01:26:36 PM PDT 24
Finished Mar 31 01:26:37 PM PDT 24
Peak memory 200688 kb
Host smart-23af1fbc-5cbc-4662-9db8-00ff1845da6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816916896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1816916896
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3097898634
Short name T382
Test name
Test status
Simulation time 2346048365 ps
CPU time 8.43 seconds
Started Mar 31 01:26:35 PM PDT 24
Finished Mar 31 01:26:44 PM PDT 24
Peak memory 222696 kb
Host smart-d7e2649e-3afe-4cf1-a8eb-c4724415b892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097898634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3097898634
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3069152405
Short name T44
Test name
Test status
Simulation time 243569342 ps
CPU time 1.1 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:35 PM PDT 24
Peak memory 218236 kb
Host smart-76484b83-9acf-473e-96d6-49eba9df3295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069152405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3069152405
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4052619764
Short name T415
Test name
Test status
Simulation time 754534911 ps
CPU time 4.07 seconds
Started Mar 31 01:26:43 PM PDT 24
Finished Mar 31 01:26:48 PM PDT 24
Peak memory 201036 kb
Host smart-36070d16-27b8-4c13-8fa3-084af2d8b2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052619764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4052619764
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1120321854
Short name T350
Test name
Test status
Simulation time 106031301 ps
CPU time 1 seconds
Started Mar 31 01:26:35 PM PDT 24
Finished Mar 31 01:26:36 PM PDT 24
Peak memory 200736 kb
Host smart-16e7b498-b6c8-44b4-aff9-2eeec16ff8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120321854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1120321854
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3069866381
Short name T535
Test name
Test status
Simulation time 204374062 ps
CPU time 1.41 seconds
Started Mar 31 01:26:43 PM PDT 24
Finished Mar 31 01:26:44 PM PDT 24
Peak memory 200944 kb
Host smart-2c114905-00a1-4308-8ce0-399bba83bb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069866381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3069866381
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2809485898
Short name T399
Test name
Test status
Simulation time 1764795972 ps
CPU time 6.38 seconds
Started Mar 31 01:26:32 PM PDT 24
Finished Mar 31 01:26:39 PM PDT 24
Peak memory 200984 kb
Host smart-715099fd-053c-44e6-a69e-8a56bb0f204d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809485898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2809485898
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2715620859
Short name T433
Test name
Test status
Simulation time 159321852 ps
CPU time 1.87 seconds
Started Mar 31 01:26:32 PM PDT 24
Finished Mar 31 01:26:34 PM PDT 24
Peak memory 200880 kb
Host smart-4df0a8ec-8ebb-41a1-bc54-215d9a5a3b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715620859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2715620859
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2814483
Short name T167
Test name
Test status
Simulation time 249500857 ps
CPU time 1.43 seconds
Started Mar 31 01:26:35 PM PDT 24
Finished Mar 31 01:26:37 PM PDT 24
Peak memory 200836 kb
Host smart-ba7f8599-c68d-4e92-9343-463eb2d7064d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2814483
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2816417851
Short name T252
Test name
Test status
Simulation time 71405419 ps
CPU time 0.77 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:35 PM PDT 24
Peak memory 200716 kb
Host smart-7cdb596f-382d-45c2-a56e-a80247ec4745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816417851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2816417851
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2852327497
Short name T48
Test name
Test status
Simulation time 1220251416 ps
CPU time 5.65 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:40 PM PDT 24
Peak memory 218000 kb
Host smart-243177e2-63b1-45dc-9fd3-f1bd99b226f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852327497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2852327497
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1484634725
Short name T493
Test name
Test status
Simulation time 243823014 ps
CPU time 1.11 seconds
Started Mar 31 01:26:33 PM PDT 24
Finished Mar 31 01:26:34 PM PDT 24
Peak memory 218160 kb
Host smart-ecabb978-fab9-4115-a6c5-71ed6db3d7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484634725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1484634725
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.147257451
Short name T465
Test name
Test status
Simulation time 207832308 ps
CPU time 0.87 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:36 PM PDT 24
Peak memory 200592 kb
Host smart-d162f47a-a98d-4daa-951a-fc0e981bc0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147257451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.147257451
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.332653941
Short name T526
Test name
Test status
Simulation time 816277763 ps
CPU time 4.15 seconds
Started Mar 31 01:26:39 PM PDT 24
Finished Mar 31 01:26:43 PM PDT 24
Peak memory 200828 kb
Host smart-1c0f1fb6-27f0-4ed7-b974-803cfaeedf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332653941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.332653941
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.563080196
Short name T478
Test name
Test status
Simulation time 113248782 ps
CPU time 1.01 seconds
Started Mar 31 01:26:39 PM PDT 24
Finished Mar 31 01:26:40 PM PDT 24
Peak memory 200540 kb
Host smart-683838c0-85de-4669-b969-c7a3f154bbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563080196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.563080196
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1392693620
Short name T188
Test name
Test status
Simulation time 229402036 ps
CPU time 1.47 seconds
Started Mar 31 01:26:39 PM PDT 24
Finished Mar 31 01:26:40 PM PDT 24
Peak memory 200892 kb
Host smart-991b005f-cefb-4c6d-9521-7de961dfa364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392693620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1392693620
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3493975064
Short name T322
Test name
Test status
Simulation time 5230279449 ps
CPU time 24.68 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:27:09 PM PDT 24
Peak memory 210192 kb
Host smart-fb243ba4-e5a1-4efc-b154-3c5b63749120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493975064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3493975064
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2459263035
Short name T153
Test name
Test status
Simulation time 114197024 ps
CPU time 1.45 seconds
Started Mar 31 01:26:42 PM PDT 24
Finished Mar 31 01:26:43 PM PDT 24
Peak memory 200844 kb
Host smart-194bcc16-54b2-471a-a06a-1a083f346337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459263035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2459263035
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1436058860
Short name T296
Test name
Test status
Simulation time 98532675 ps
CPU time 0.78 seconds
Started Mar 31 01:26:40 PM PDT 24
Finished Mar 31 01:26:42 PM PDT 24
Peak memory 200712 kb
Host smart-b2dbc3a1-f5a3-4c89-940c-8c351e10a597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436058860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1436058860
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.999151795
Short name T483
Test name
Test status
Simulation time 1879703425 ps
CPU time 7.53 seconds
Started Mar 31 01:26:41 PM PDT 24
Finished Mar 31 01:26:49 PM PDT 24
Peak memory 217564 kb
Host smart-325909e1-49f8-4b5d-8159-49cca78df691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999151795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.999151795
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1981226524
Short name T318
Test name
Test status
Simulation time 243540440 ps
CPU time 1.17 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:26:45 PM PDT 24
Peak memory 218040 kb
Host smart-9b929a95-b869-4736-8fdc-26386ac0cf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981226524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1981226524
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.4061071297
Short name T237
Test name
Test status
Simulation time 221536348 ps
CPU time 1.09 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:35 PM PDT 24
Peak memory 200680 kb
Host smart-951a5014-00c6-4a27-ac6f-d7f8ef9e65e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061071297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.4061071297
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3280832796
Short name T424
Test name
Test status
Simulation time 1052003141 ps
CPU time 4.82 seconds
Started Mar 31 01:26:41 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 200992 kb
Host smart-5e0e71a7-88c7-48cd-9b98-91138c152286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280832796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3280832796
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2710022520
Short name T275
Test name
Test status
Simulation time 184616057 ps
CPU time 1.22 seconds
Started Mar 31 01:26:40 PM PDT 24
Finished Mar 31 01:26:42 PM PDT 24
Peak memory 200844 kb
Host smart-19cd6eb4-cd4b-418b-839c-1e2694747fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710022520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2710022520
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.613578560
Short name T228
Test name
Test status
Simulation time 115023748 ps
CPU time 1.16 seconds
Started Mar 31 01:26:37 PM PDT 24
Finished Mar 31 01:26:39 PM PDT 24
Peak memory 200972 kb
Host smart-6091770d-b498-4708-ad4d-6ca8a71a8f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613578560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.613578560
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1176160230
Short name T243
Test name
Test status
Simulation time 796081759 ps
CPU time 4.04 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:26:48 PM PDT 24
Peak memory 200884 kb
Host smart-561b4fab-844f-4593-b6d6-f378b1eab23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176160230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1176160230
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.699959342
Short name T302
Test name
Test status
Simulation time 466116624 ps
CPU time 2.49 seconds
Started Mar 31 01:26:36 PM PDT 24
Finished Mar 31 01:26:39 PM PDT 24
Peak memory 200864 kb
Host smart-fa53cfed-cffd-4672-ae09-fd538582514e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699959342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.699959342
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2462698982
Short name T137
Test name
Test status
Simulation time 207242910 ps
CPU time 1.29 seconds
Started Mar 31 01:26:39 PM PDT 24
Finished Mar 31 01:26:40 PM PDT 24
Peak memory 200752 kb
Host smart-ec1b9654-4dc5-427f-b593-fe2bae39ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462698982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2462698982
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3410304441
Short name T214
Test name
Test status
Simulation time 66620927 ps
CPU time 0.75 seconds
Started Mar 31 01:26:41 PM PDT 24
Finished Mar 31 01:26:42 PM PDT 24
Peak memory 200684 kb
Host smart-c94772a6-9e77-4ea1-8303-21d8a92e5d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410304441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3410304441
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1105098961
Short name T53
Test name
Test status
Simulation time 1881750927 ps
CPU time 7.99 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:26:52 PM PDT 24
Peak memory 218328 kb
Host smart-c2615b51-c2da-4e4b-9fcf-711d6df1e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105098961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1105098961
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3364912314
Short name T449
Test name
Test status
Simulation time 243614520 ps
CPU time 1.22 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:47 PM PDT 24
Peak memory 218100 kb
Host smart-361c31dd-56b5-40ee-8bc0-32c8a9f73833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364912314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3364912314
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4005840094
Short name T15
Test name
Test status
Simulation time 175148406 ps
CPU time 0.84 seconds
Started Mar 31 01:26:42 PM PDT 24
Finished Mar 31 01:26:43 PM PDT 24
Peak memory 200700 kb
Host smart-84984f7c-43f7-4832-bfab-523af396afaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005840094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4005840094
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3019193533
Short name T219
Test name
Test status
Simulation time 1713752101 ps
CPU time 6.46 seconds
Started Mar 31 01:26:41 PM PDT 24
Finished Mar 31 01:26:48 PM PDT 24
Peak memory 200984 kb
Host smart-4bf635c5-20af-4f26-a3e7-890e2629c837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019193533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3019193533
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.314896942
Short name T173
Test name
Test status
Simulation time 162326621 ps
CPU time 1.12 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:26:45 PM PDT 24
Peak memory 200792 kb
Host smart-e689a54a-7420-42f8-ac71-782777447453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314896942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.314896942
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1842695551
Short name T211
Test name
Test status
Simulation time 250825796 ps
CPU time 1.52 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 200996 kb
Host smart-e72dcf9e-751b-4d12-a8eb-bf09c92587d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842695551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1842695551
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.650694069
Short name T207
Test name
Test status
Simulation time 8569773386 ps
CPU time 30.65 seconds
Started Mar 31 01:26:40 PM PDT 24
Finished Mar 31 01:27:11 PM PDT 24
Peak memory 201172 kb
Host smart-edc75dfe-416e-4113-a41a-71756286de34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650694069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.650694069
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3111133772
Short name T496
Test name
Test status
Simulation time 139494259 ps
CPU time 1.72 seconds
Started Mar 31 01:26:39 PM PDT 24
Finished Mar 31 01:26:41 PM PDT 24
Peak memory 200820 kb
Host smart-c583b39d-b415-4768-8c40-25ef2ffacf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111133772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3111133772
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1429928133
Short name T139
Test name
Test status
Simulation time 152070588 ps
CPU time 1.12 seconds
Started Mar 31 01:26:40 PM PDT 24
Finished Mar 31 01:26:42 PM PDT 24
Peak memory 200836 kb
Host smart-6552173b-deaa-4256-975d-2429af31276e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429928133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1429928133
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.730603524
Short name T142
Test name
Test status
Simulation time 58204043 ps
CPU time 0.73 seconds
Started Mar 31 01:26:42 PM PDT 24
Finished Mar 31 01:26:43 PM PDT 24
Peak memory 200708 kb
Host smart-daa20c82-3af5-4a64-88e7-c4f32e8854de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730603524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.730603524
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1760305701
Short name T323
Test name
Test status
Simulation time 1230506636 ps
CPU time 5.82 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:51 PM PDT 24
Peak memory 218536 kb
Host smart-ea82def1-0633-49f1-b8ff-2522c2479b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760305701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1760305701
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3777302520
Short name T431
Test name
Test status
Simulation time 244649730 ps
CPU time 1.04 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 218156 kb
Host smart-a009798d-cb3a-483c-8c21-61f96cf5c970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777302520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3777302520
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1487711370
Short name T14
Test name
Test status
Simulation time 143606105 ps
CPU time 0.83 seconds
Started Mar 31 01:26:41 PM PDT 24
Finished Mar 31 01:26:42 PM PDT 24
Peak memory 200712 kb
Host smart-a31c9ba5-dcc8-4568-9532-d5d543c9f72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487711370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1487711370
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2653939045
Short name T256
Test name
Test status
Simulation time 1436968431 ps
CPU time 5.31 seconds
Started Mar 31 01:26:43 PM PDT 24
Finished Mar 31 01:26:49 PM PDT 24
Peak memory 200984 kb
Host smart-a6b06f94-4262-4168-a04e-5040a3c25ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653939045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2653939045
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1326672570
Short name T377
Test name
Test status
Simulation time 177358030 ps
CPU time 1.17 seconds
Started Mar 31 01:26:43 PM PDT 24
Finished Mar 31 01:26:44 PM PDT 24
Peak memory 200824 kb
Host smart-01e49ce7-c167-43cb-b8e8-59ccf716ed89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326672570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1326672570
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2227381538
Short name T254
Test name
Test status
Simulation time 110541227 ps
CPU time 1.16 seconds
Started Mar 31 01:26:43 PM PDT 24
Finished Mar 31 01:26:44 PM PDT 24
Peak memory 201024 kb
Host smart-28cda822-d590-4fc7-848f-262952811ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227381538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2227381538
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3338145015
Short name T220
Test name
Test status
Simulation time 5743870578 ps
CPU time 27.35 seconds
Started Mar 31 01:26:43 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 210908 kb
Host smart-f0e8b388-2b65-4b34-b0a6-f1e09b73d278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338145015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3338145015
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3749234585
Short name T82
Test name
Test status
Simulation time 403904705 ps
CPU time 2.27 seconds
Started Mar 31 01:26:43 PM PDT 24
Finished Mar 31 01:26:45 PM PDT 24
Peak memory 209084 kb
Host smart-60f9db9e-d8c3-41fd-a3bf-e1598098bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749234585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3749234585
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3964285276
Short name T524
Test name
Test status
Simulation time 111404596 ps
CPU time 1.01 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:26:45 PM PDT 24
Peak memory 200824 kb
Host smart-7b46cb2e-83ca-48f2-a3b3-fe93a3f931a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964285276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3964285276
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3458432678
Short name T307
Test name
Test status
Simulation time 72080411 ps
CPU time 0.78 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:26:45 PM PDT 24
Peak memory 200708 kb
Host smart-be62f98e-7cff-4ca9-9759-f2ff29260819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458432678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3458432678
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.355413141
Short name T391
Test name
Test status
Simulation time 2165836715 ps
CPU time 8.01 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:53 PM PDT 24
Peak memory 218652 kb
Host smart-5d2a91f1-86d1-4408-93b8-2f269a4015ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355413141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.355413141
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2057463982
Short name T487
Test name
Test status
Simulation time 245192617 ps
CPU time 1.02 seconds
Started Mar 31 01:26:49 PM PDT 24
Finished Mar 31 01:26:50 PM PDT 24
Peak memory 218124 kb
Host smart-ed2beccb-9195-4be2-b6f2-af9cf0ef4210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057463982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2057463982
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.176289048
Short name T471
Test name
Test status
Simulation time 176246411 ps
CPU time 0.82 seconds
Started Mar 31 01:26:39 PM PDT 24
Finished Mar 31 01:26:41 PM PDT 24
Peak memory 200712 kb
Host smart-57d27a21-bdf8-4f18-a745-1bda46ce36a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176289048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.176289048
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1578287227
Short name T540
Test name
Test status
Simulation time 1488798752 ps
CPU time 5.19 seconds
Started Mar 31 01:26:41 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 200984 kb
Host smart-27faf083-4c2b-44d8-a640-e6081d29ecc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578287227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1578287227
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3424486473
Short name T517
Test name
Test status
Simulation time 152000297 ps
CPU time 1.09 seconds
Started Mar 31 01:26:39 PM PDT 24
Finished Mar 31 01:26:40 PM PDT 24
Peak memory 200884 kb
Host smart-4c83e267-7d8a-4a66-8296-5464b3b5fed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424486473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3424486473
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1212542850
Short name T328
Test name
Test status
Simulation time 125529892 ps
CPU time 1.26 seconds
Started Mar 31 01:26:42 PM PDT 24
Finished Mar 31 01:26:43 PM PDT 24
Peak memory 201020 kb
Host smart-35ec615c-94af-451d-9613-681af3b5b029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212542850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1212542850
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.4162815456
Short name T118
Test name
Test status
Simulation time 11625420424 ps
CPU time 39.58 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:27:25 PM PDT 24
Peak memory 210332 kb
Host smart-d9465aae-336c-4b1c-a77f-77bdb8134c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162815456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.4162815456
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3361983920
Short name T334
Test name
Test status
Simulation time 131230881 ps
CPU time 1.68 seconds
Started Mar 31 01:26:41 PM PDT 24
Finished Mar 31 01:26:43 PM PDT 24
Peak memory 200864 kb
Host smart-0b924ddd-c502-447c-9930-0a457984129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361983920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3361983920
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1101544560
Short name T244
Test name
Test status
Simulation time 139356404 ps
CPU time 1.03 seconds
Started Mar 31 01:26:43 PM PDT 24
Finished Mar 31 01:26:44 PM PDT 24
Peak memory 200820 kb
Host smart-0aa3c592-ed93-49d5-8faa-649eba60dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101544560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1101544560
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2072863804
Short name T46
Test name
Test status
Simulation time 1898002625 ps
CPU time 7.03 seconds
Started Mar 31 01:26:46 PM PDT 24
Finished Mar 31 01:26:53 PM PDT 24
Peak memory 218536 kb
Host smart-350d2637-f957-4ee3-9a67-d77d27dcbbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072863804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2072863804
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1794321868
Short name T277
Test name
Test status
Simulation time 244357055 ps
CPU time 1.15 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 218228 kb
Host smart-e95ecab7-8c4f-47c7-b3bf-c5ba87153b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794321868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1794321868
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4163888391
Short name T12
Test name
Test status
Simulation time 222705379 ps
CPU time 0.95 seconds
Started Mar 31 01:26:48 PM PDT 24
Finished Mar 31 01:26:50 PM PDT 24
Peak memory 200632 kb
Host smart-58fe584d-6fab-4340-ba07-78bc0a2e7a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163888391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4163888391
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2462813931
Short name T267
Test name
Test status
Simulation time 1115757936 ps
CPU time 5 seconds
Started Mar 31 01:26:46 PM PDT 24
Finished Mar 31 01:26:51 PM PDT 24
Peak memory 201000 kb
Host smart-ebe47fc3-e3ac-4fb2-b51a-3dd51216bf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462813931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2462813931
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.326844793
Short name T354
Test name
Test status
Simulation time 173498668 ps
CPU time 1.1 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 200856 kb
Host smart-0009f50a-1c69-4f04-8bfe-96d8fd3a7465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326844793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.326844793
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3937805815
Short name T246
Test name
Test status
Simulation time 190909830 ps
CPU time 1.35 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 201024 kb
Host smart-f3d3c77a-192e-46d7-b06e-b0cf0255f187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937805815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3937805815
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1362911153
Short name T140
Test name
Test status
Simulation time 1096078639 ps
CPU time 4.98 seconds
Started Mar 31 01:26:50 PM PDT 24
Finished Mar 31 01:26:55 PM PDT 24
Peak memory 209184 kb
Host smart-17c6bbc4-1b3e-436b-bd41-41350fd55cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362911153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1362911153
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.753112241
Short name T251
Test name
Test status
Simulation time 140693257 ps
CPU time 1.74 seconds
Started Mar 31 01:26:46 PM PDT 24
Finished Mar 31 01:26:48 PM PDT 24
Peak memory 200788 kb
Host smart-5002650f-4412-4b37-b650-88c805b8c7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753112241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.753112241
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1156763659
Short name T480
Test name
Test status
Simulation time 80732636 ps
CPU time 0.85 seconds
Started Mar 31 01:26:46 PM PDT 24
Finished Mar 31 01:26:47 PM PDT 24
Peak memory 200852 kb
Host smart-203f2846-e9eb-4869-bb38-73b99960afa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156763659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1156763659
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.789154696
Short name T340
Test name
Test status
Simulation time 59233814 ps
CPU time 0.75 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 200700 kb
Host smart-ae9d2aa7-5723-42f1-bbe4-db831c3db643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789154696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.789154696
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1795740702
Short name T136
Test name
Test status
Simulation time 243536779 ps
CPU time 1.02 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 218020 kb
Host smart-17dad767-c9ab-4a8c-9f67-3653e36c5a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795740702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1795740702
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.4089306985
Short name T405
Test name
Test status
Simulation time 79448622 ps
CPU time 0.73 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 200704 kb
Host smart-560ca61a-22c4-4db6-8335-77e6c6f6ac84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089306985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.4089306985
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.4180219667
Short name T491
Test name
Test status
Simulation time 1829997063 ps
CPU time 6.62 seconds
Started Mar 31 01:26:46 PM PDT 24
Finished Mar 31 01:26:53 PM PDT 24
Peak memory 201132 kb
Host smart-50321418-3cb9-4d47-ad5a-ca01bf57312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180219667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.4180219667
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.115581197
Short name T476
Test name
Test status
Simulation time 96999172 ps
CPU time 0.98 seconds
Started Mar 31 01:26:47 PM PDT 24
Finished Mar 31 01:26:48 PM PDT 24
Peak memory 200948 kb
Host smart-bfcfc486-1703-4480-8cd3-deeb4e72b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115581197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.115581197
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3239536121
Short name T532
Test name
Test status
Simulation time 105774833 ps
CPU time 1.15 seconds
Started Mar 31 01:26:46 PM PDT 24
Finished Mar 31 01:26:47 PM PDT 24
Peak memory 200972 kb
Host smart-e803df60-e0e2-43fc-8438-b7a99d111711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239536121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3239536121
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2824518594
Short name T179
Test name
Test status
Simulation time 3326303784 ps
CPU time 12.34 seconds
Started Mar 31 01:26:46 PM PDT 24
Finished Mar 31 01:26:58 PM PDT 24
Peak memory 201120 kb
Host smart-2cd5c904-54fc-4184-aa60-ce76dfca5df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824518594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2824518594
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.866659644
Short name T298
Test name
Test status
Simulation time 134818304 ps
CPU time 1.83 seconds
Started Mar 31 01:26:49 PM PDT 24
Finished Mar 31 01:26:51 PM PDT 24
Peak memory 200904 kb
Host smart-34894249-5fd6-4504-a179-41d3b35caf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866659644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.866659644
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1715044254
Short name T164
Test name
Test status
Simulation time 65539479 ps
CPU time 0.75 seconds
Started Mar 31 01:26:47 PM PDT 24
Finished Mar 31 01:26:48 PM PDT 24
Peak memory 200796 kb
Host smart-21cea821-ab61-4180-9548-3aa931277e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715044254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1715044254
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2838902111
Short name T386
Test name
Test status
Simulation time 79077039 ps
CPU time 0.78 seconds
Started Mar 31 01:26:49 PM PDT 24
Finished Mar 31 01:26:51 PM PDT 24
Peak memory 200724 kb
Host smart-6bf693c7-03d6-48ce-aa0a-70bfdf672854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838902111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2838902111
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1079977151
Short name T5
Test name
Test status
Simulation time 1228341751 ps
CPU time 5.21 seconds
Started Mar 31 01:26:53 PM PDT 24
Finished Mar 31 01:26:58 PM PDT 24
Peak memory 218548 kb
Host smart-d48fc3b1-9735-4163-be45-eff0e3e0b688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079977151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1079977151
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1845950390
Short name T255
Test name
Test status
Simulation time 244621861 ps
CPU time 1.1 seconds
Started Mar 31 01:26:51 PM PDT 24
Finished Mar 31 01:26:53 PM PDT 24
Peak memory 218156 kb
Host smart-6306f05d-3a71-4005-b10a-908086b333c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845950390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1845950390
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.4165313285
Short name T192
Test name
Test status
Simulation time 147828358 ps
CPU time 0.77 seconds
Started Mar 31 01:26:44 PM PDT 24
Finished Mar 31 01:26:45 PM PDT 24
Peak memory 200704 kb
Host smart-430b350b-71eb-4624-ab0c-bd23a7893611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165313285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.4165313285
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1306295883
Short name T172
Test name
Test status
Simulation time 1382664262 ps
CPU time 4.98 seconds
Started Mar 31 01:26:45 PM PDT 24
Finished Mar 31 01:26:50 PM PDT 24
Peak memory 201060 kb
Host smart-3743dce7-78a1-4863-8b2e-0ecd2621a94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306295883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1306295883
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3410611979
Short name T339
Test name
Test status
Simulation time 159234762 ps
CPU time 1.24 seconds
Started Mar 31 01:26:48 PM PDT 24
Finished Mar 31 01:26:50 PM PDT 24
Peak memory 200788 kb
Host smart-2c8c28e1-11d1-49e4-be6c-79f282f16c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410611979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3410611979
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1725039208
Short name T401
Test name
Test status
Simulation time 193820081 ps
CPU time 1.32 seconds
Started Mar 31 01:26:43 PM PDT 24
Finished Mar 31 01:26:45 PM PDT 24
Peak memory 201028 kb
Host smart-f83cb224-364f-41bc-9f24-739bb5c56672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725039208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1725039208
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3344586965
Short name T518
Test name
Test status
Simulation time 2930604563 ps
CPU time 13.06 seconds
Started Mar 31 01:26:49 PM PDT 24
Finished Mar 31 01:27:02 PM PDT 24
Peak memory 209288 kb
Host smart-fa0e6a8e-0b65-4ffe-af93-8d0486fd88cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344586965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3344586965
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.809322662
Short name T346
Test name
Test status
Simulation time 151240731 ps
CPU time 1.84 seconds
Started Mar 31 01:26:47 PM PDT 24
Finished Mar 31 01:26:49 PM PDT 24
Peak memory 200908 kb
Host smart-d333a14f-f175-4074-ba65-c6c32fb2e90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809322662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.809322662
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2614343326
Short name T134
Test name
Test status
Simulation time 166870516 ps
CPU time 1.28 seconds
Started Mar 31 01:26:46 PM PDT 24
Finished Mar 31 01:26:48 PM PDT 24
Peak memory 200984 kb
Host smart-6ce0668a-e79f-49b2-bc62-1d4e9b4cdb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614343326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2614343326
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4109602655
Short name T197
Test name
Test status
Simulation time 81123754 ps
CPU time 0.79 seconds
Started Mar 31 01:26:18 PM PDT 24
Finished Mar 31 01:26:19 PM PDT 24
Peak memory 200688 kb
Host smart-586302e4-f460-46f8-b38e-659dde46d375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109602655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4109602655
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.17895618
Short name T508
Test name
Test status
Simulation time 1229823896 ps
CPU time 5.58 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 218044 kb
Host smart-7d5f3c28-63e0-4e48-8ab0-ddedd5d1d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17895618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.17895618
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2835694219
Short name T149
Test name
Test status
Simulation time 244365677 ps
CPU time 1.13 seconds
Started Mar 31 01:26:18 PM PDT 24
Finished Mar 31 01:26:19 PM PDT 24
Peak memory 218052 kb
Host smart-e882daa0-f145-4fcf-bc68-7f62685449e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835694219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2835694219
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2963702231
Short name T406
Test name
Test status
Simulation time 126500057 ps
CPU time 0.88 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:12 PM PDT 24
Peak memory 200700 kb
Host smart-0d94188d-0e09-4628-a180-ff6bb3cb4b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963702231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2963702231
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1746181369
Short name T292
Test name
Test status
Simulation time 1197285201 ps
CPU time 5.32 seconds
Started Mar 31 01:26:11 PM PDT 24
Finished Mar 31 01:26:16 PM PDT 24
Peak memory 201024 kb
Host smart-a48d6d0e-8f6d-42b7-b5ea-9b2551c5e7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746181369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1746181369
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3399566360
Short name T66
Test name
Test status
Simulation time 17039008510 ps
CPU time 27.24 seconds
Started Mar 31 01:26:17 PM PDT 24
Finished Mar 31 01:26:45 PM PDT 24
Peak memory 217988 kb
Host smart-20fae9ea-977b-4643-ae8e-628606fa9731
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399566360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3399566360
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2222361796
Short name T217
Test name
Test status
Simulation time 185663690 ps
CPU time 1.2 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:23 PM PDT 24
Peak memory 200772 kb
Host smart-cfbcc01b-0521-4b2e-8421-6f542f7af6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222361796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2222361796
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2730274529
Short name T388
Test name
Test status
Simulation time 125904724 ps
CPU time 1.15 seconds
Started Mar 31 01:26:09 PM PDT 24
Finished Mar 31 01:26:11 PM PDT 24
Peak memory 200980 kb
Host smart-66f28188-5e00-41d0-a1c2-7b6ec06b81da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730274529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2730274529
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2563486754
Short name T444
Test name
Test status
Simulation time 16925490600 ps
CPU time 60.46 seconds
Started Mar 31 01:26:17 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 209348 kb
Host smart-3cd6f75b-a9fd-43b3-8649-5a3eb3f5cbf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563486754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2563486754
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1813538629
Short name T125
Test name
Test status
Simulation time 128856064 ps
CPU time 1.6 seconds
Started Mar 31 01:26:09 PM PDT 24
Finished Mar 31 01:26:10 PM PDT 24
Peak memory 209088 kb
Host smart-a0855d8e-28f5-42a7-a785-db43ac207ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813538629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1813538629
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1645489177
Short name T311
Test name
Test status
Simulation time 244324219 ps
CPU time 1.32 seconds
Started Mar 31 01:26:12 PM PDT 24
Finished Mar 31 01:26:13 PM PDT 24
Peak memory 200828 kb
Host smart-c24ec455-9169-445b-8237-5de2f0d315a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645489177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1645489177
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1236833680
Short name T345
Test name
Test status
Simulation time 69996194 ps
CPU time 0.77 seconds
Started Mar 31 01:26:52 PM PDT 24
Finished Mar 31 01:26:53 PM PDT 24
Peak memory 200692 kb
Host smart-5e950754-3750-4a61-8a06-07b9bdc8618f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236833680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1236833680
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.307721129
Short name T527
Test name
Test status
Simulation time 1888387402 ps
CPU time 7.93 seconds
Started Mar 31 01:26:51 PM PDT 24
Finished Mar 31 01:27:00 PM PDT 24
Peak memory 218540 kb
Host smart-3929f4f3-4c41-46c3-8fa6-e7b70dc7f7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307721129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.307721129
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.59855270
Short name T403
Test name
Test status
Simulation time 243988548 ps
CPU time 1.08 seconds
Started Mar 31 01:27:06 PM PDT 24
Finished Mar 31 01:27:08 PM PDT 24
Peak memory 218192 kb
Host smart-57efbb1b-0963-4166-8464-2a5c3e356d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59855270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.59855270
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2122443181
Short name T185
Test name
Test status
Simulation time 135497929 ps
CPU time 0.8 seconds
Started Mar 31 01:26:52 PM PDT 24
Finished Mar 31 01:26:54 PM PDT 24
Peak memory 200676 kb
Host smart-2a591835-8ede-47f8-91bd-d409d61fc9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122443181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2122443181
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.4049799589
Short name T490
Test name
Test status
Simulation time 909619279 ps
CPU time 4.68 seconds
Started Mar 31 01:27:06 PM PDT 24
Finished Mar 31 01:27:11 PM PDT 24
Peak memory 200912 kb
Host smart-35987f39-2659-4474-9953-1c535f586ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049799589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.4049799589
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3108583580
Short name T359
Test name
Test status
Simulation time 98738593 ps
CPU time 0.96 seconds
Started Mar 31 01:26:54 PM PDT 24
Finished Mar 31 01:26:55 PM PDT 24
Peak memory 200852 kb
Host smart-f9b5f226-ff59-4fbb-a378-0d219cbe534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108583580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3108583580
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2224148907
Short name T486
Test name
Test status
Simulation time 197194287 ps
CPU time 1.34 seconds
Started Mar 31 01:26:53 PM PDT 24
Finished Mar 31 01:26:54 PM PDT 24
Peak memory 201040 kb
Host smart-f00b13bb-0996-4801-a605-e0df27135b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224148907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2224148907
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.885442478
Short name T190
Test name
Test status
Simulation time 4516564682 ps
CPU time 17.59 seconds
Started Mar 31 01:26:53 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 201072 kb
Host smart-dc5157ff-ec7c-4ff0-81f8-52518643be8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885442478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.885442478
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3046249064
Short name T488
Test name
Test status
Simulation time 397830142 ps
CPU time 2.18 seconds
Started Mar 31 01:27:00 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 200780 kb
Host smart-da89b23d-2ffa-4a17-8d83-a821746db10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046249064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3046249064
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2647776441
Short name T132
Test name
Test status
Simulation time 87108310 ps
CPU time 0.88 seconds
Started Mar 31 01:26:52 PM PDT 24
Finished Mar 31 01:26:53 PM PDT 24
Peak memory 200768 kb
Host smart-55f38ba9-b2db-4ea2-a733-9d49c412b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647776441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2647776441
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2799597868
Short name T229
Test name
Test status
Simulation time 70150276 ps
CPU time 0.78 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:04 PM PDT 24
Peak memory 200656 kb
Host smart-62c89514-9281-4ca8-955b-01381a9c9489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799597868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2799597868
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3266237035
Short name T33
Test name
Test status
Simulation time 1216034296 ps
CPU time 5.24 seconds
Started Mar 31 01:26:54 PM PDT 24
Finished Mar 31 01:26:59 PM PDT 24
Peak memory 217972 kb
Host smart-13a32fe5-153f-4a9e-9b40-0c1743b43bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266237035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3266237035
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2769183666
Short name T299
Test name
Test status
Simulation time 245578760 ps
CPU time 1.04 seconds
Started Mar 31 01:27:06 PM PDT 24
Finished Mar 31 01:27:07 PM PDT 24
Peak memory 217652 kb
Host smart-517a18cc-fa17-44a5-bcc2-6e1e71e4da0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769183666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2769183666
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1154669054
Short name T463
Test name
Test status
Simulation time 192412426 ps
CPU time 0.95 seconds
Started Mar 31 01:26:55 PM PDT 24
Finished Mar 31 01:26:56 PM PDT 24
Peak memory 200704 kb
Host smart-32cc2396-8f07-4bf9-87a8-70173829614e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154669054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1154669054
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3078207135
Short name T245
Test name
Test status
Simulation time 1382661536 ps
CPU time 6.13 seconds
Started Mar 31 01:27:06 PM PDT 24
Finished Mar 31 01:27:13 PM PDT 24
Peak memory 200496 kb
Host smart-2ecaf3ac-82be-42f6-8e91-b4247cd549fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078207135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3078207135
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.918689905
Short name T348
Test name
Test status
Simulation time 104874823 ps
CPU time 1.03 seconds
Started Mar 31 01:27:06 PM PDT 24
Finished Mar 31 01:27:08 PM PDT 24
Peak memory 200772 kb
Host smart-5d283f31-f514-478c-ae4f-f343c962883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918689905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.918689905
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2176326752
Short name T41
Test name
Test status
Simulation time 125900163 ps
CPU time 1.17 seconds
Started Mar 31 01:26:51 PM PDT 24
Finished Mar 31 01:26:52 PM PDT 24
Peak memory 200980 kb
Host smart-ec75df3c-92cd-4e0c-a13f-9c51ed68e73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176326752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2176326752
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.594344366
Short name T147
Test name
Test status
Simulation time 3468692993 ps
CPU time 14.82 seconds
Started Mar 31 01:27:06 PM PDT 24
Finished Mar 31 01:27:21 PM PDT 24
Peak memory 209212 kb
Host smart-5de6f222-a066-4268-a001-630c331bf4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594344366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.594344366
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3207091088
Short name T495
Test name
Test status
Simulation time 135118704 ps
CPU time 1.74 seconds
Started Mar 31 01:26:51 PM PDT 24
Finished Mar 31 01:26:53 PM PDT 24
Peak memory 200920 kb
Host smart-031700b3-96b1-4c89-9655-e5cb7460db1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207091088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3207091088
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1605076681
Short name T159
Test name
Test status
Simulation time 154990345 ps
CPU time 1.13 seconds
Started Mar 31 01:27:02 PM PDT 24
Finished Mar 31 01:27:04 PM PDT 24
Peak memory 200732 kb
Host smart-07f26903-eeae-4ff3-991f-7c96e6c1708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605076681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1605076681
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.4266171932
Short name T158
Test name
Test status
Simulation time 85524678 ps
CPU time 0.84 seconds
Started Mar 31 01:26:53 PM PDT 24
Finished Mar 31 01:26:55 PM PDT 24
Peak memory 200708 kb
Host smart-9a8d2bd4-dded-4412-86a7-459a0a182e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266171932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.4266171932
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2736353024
Short name T47
Test name
Test status
Simulation time 1233625387 ps
CPU time 5.46 seconds
Started Mar 31 01:26:52 PM PDT 24
Finished Mar 31 01:26:58 PM PDT 24
Peak memory 218500 kb
Host smart-436ad6bc-cea8-46bc-ae4f-cfd73264a110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736353024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2736353024
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1973253092
Short name T414
Test name
Test status
Simulation time 243696498 ps
CPU time 1.09 seconds
Started Mar 31 01:26:53 PM PDT 24
Finished Mar 31 01:26:54 PM PDT 24
Peak memory 218088 kb
Host smart-43b4fc9e-cb7a-4383-ae06-57388ffb1d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973253092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1973253092
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3719198442
Short name T227
Test name
Test status
Simulation time 262773666 ps
CPU time 0.92 seconds
Started Mar 31 01:26:54 PM PDT 24
Finished Mar 31 01:26:55 PM PDT 24
Peak memory 200704 kb
Host smart-2a8d82a4-4be7-4945-9eb1-09e84a390ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719198442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3719198442
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3964027509
Short name T154
Test name
Test status
Simulation time 1951670131 ps
CPU time 7.52 seconds
Started Mar 31 01:26:56 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 201048 kb
Host smart-4af1d56e-1667-4691-b336-a8d0a6d355eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964027509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3964027509
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.4113409929
Short name T155
Test name
Test status
Simulation time 191741623 ps
CPU time 1.3 seconds
Started Mar 31 01:26:50 PM PDT 24
Finished Mar 31 01:26:52 PM PDT 24
Peak memory 201020 kb
Host smart-dd522947-81ef-4d1b-b876-fad0734b1bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113409929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.4113409929
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.4222198913
Short name T98
Test name
Test status
Simulation time 4781309125 ps
CPU time 16.64 seconds
Started Mar 31 01:26:55 PM PDT 24
Finished Mar 31 01:27:12 PM PDT 24
Peak memory 209332 kb
Host smart-734f392d-981b-4b34-86f3-88cf5ca0f178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222198913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.4222198913
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2692203910
Short name T120
Test name
Test status
Simulation time 361199432 ps
CPU time 1.93 seconds
Started Mar 31 01:26:51 PM PDT 24
Finished Mar 31 01:26:53 PM PDT 24
Peak memory 200860 kb
Host smart-a600a50d-0df3-42f2-9a4f-835efb355327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692203910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2692203910
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1266629992
Short name T223
Test name
Test status
Simulation time 119987190 ps
CPU time 1.07 seconds
Started Mar 31 01:26:53 PM PDT 24
Finished Mar 31 01:26:54 PM PDT 24
Peak memory 200740 kb
Host smart-a0d42408-8b77-4d04-b106-63a7f7e2ccd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266629992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1266629992
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.4264791386
Short name T333
Test name
Test status
Simulation time 71151017 ps
CPU time 0.73 seconds
Started Mar 31 01:26:55 PM PDT 24
Finished Mar 31 01:26:56 PM PDT 24
Peak memory 200704 kb
Host smart-824127fc-3e61-4ef0-8a80-2a38a1801683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264791386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.4264791386
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.252192632
Short name T6
Test name
Test status
Simulation time 244160669 ps
CPU time 1.11 seconds
Started Mar 31 01:27:02 PM PDT 24
Finished Mar 31 01:27:04 PM PDT 24
Peak memory 218048 kb
Host smart-a87694e7-38bb-42b3-9523-5f61d17434fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252192632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.252192632
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.682878046
Short name T266
Test name
Test status
Simulation time 147817769 ps
CPU time 0.8 seconds
Started Mar 31 01:26:52 PM PDT 24
Finished Mar 31 01:26:53 PM PDT 24
Peak memory 200688 kb
Host smart-d6e133f5-eb47-4265-b6d9-274030350a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682878046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.682878046
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1207045125
Short name T364
Test name
Test status
Simulation time 1677835021 ps
CPU time 6.94 seconds
Started Mar 31 01:26:53 PM PDT 24
Finished Mar 31 01:27:00 PM PDT 24
Peak memory 201024 kb
Host smart-8edf6872-88a0-448d-99ab-2fecfb7ece9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207045125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1207045125
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2692002842
Short name T191
Test name
Test status
Simulation time 179616213 ps
CPU time 1.28 seconds
Started Mar 31 01:27:08 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 200860 kb
Host smart-e0828477-5974-4f17-b85a-8394023ffcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692002842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2692002842
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.4290860269
Short name T76
Test name
Test status
Simulation time 206322597 ps
CPU time 1.36 seconds
Started Mar 31 01:27:06 PM PDT 24
Finished Mar 31 01:27:08 PM PDT 24
Peak memory 200952 kb
Host smart-80e6ecdf-5de6-41cb-86a3-b0955b85d45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290860269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4290860269
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3605972263
Short name T152
Test name
Test status
Simulation time 8043218300 ps
CPU time 30.66 seconds
Started Mar 31 01:26:57 PM PDT 24
Finished Mar 31 01:27:28 PM PDT 24
Peak memory 201152 kb
Host smart-a7ab8897-1b31-41a1-bdbb-66756ca2385d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605972263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3605972263
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2275418032
Short name T183
Test name
Test status
Simulation time 122041494 ps
CPU time 1.55 seconds
Started Mar 31 01:26:54 PM PDT 24
Finished Mar 31 01:26:56 PM PDT 24
Peak memory 200880 kb
Host smart-1ac0c6a0-d8c3-476f-9052-0a9cbeef8552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275418032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2275418032
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1340257186
Short name T467
Test name
Test status
Simulation time 79149579 ps
CPU time 0.8 seconds
Started Mar 31 01:26:53 PM PDT 24
Finished Mar 31 01:26:54 PM PDT 24
Peak memory 200800 kb
Host smart-dd3d6058-c139-4d17-b24d-909f1db640e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340257186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1340257186
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2613460219
Short name T208
Test name
Test status
Simulation time 83952865 ps
CPU time 0.8 seconds
Started Mar 31 01:26:57 PM PDT 24
Finished Mar 31 01:26:58 PM PDT 24
Peak memory 200676 kb
Host smart-7676ae21-4724-4c01-b28b-3edfcbadb725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613460219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2613460219
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1980847376
Short name T29
Test name
Test status
Simulation time 1220334976 ps
CPU time 5.53 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:27:04 PM PDT 24
Peak memory 217980 kb
Host smart-abf83508-694b-4605-85a4-16d17c73b0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980847376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1980847376
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3144348035
Short name T135
Test name
Test status
Simulation time 245327470 ps
CPU time 1.08 seconds
Started Mar 31 01:26:56 PM PDT 24
Finished Mar 31 01:26:57 PM PDT 24
Peak memory 218104 kb
Host smart-2c7c2ac4-5570-4420-af6c-0f41134ae155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144348035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3144348035
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.543306093
Short name T248
Test name
Test status
Simulation time 201856328 ps
CPU time 0.88 seconds
Started Mar 31 01:26:56 PM PDT 24
Finished Mar 31 01:26:57 PM PDT 24
Peak memory 200612 kb
Host smart-bf19630b-43e2-48ce-8afc-54cdb73ebeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543306093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.543306093
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.462389758
Short name T416
Test name
Test status
Simulation time 1436671163 ps
CPU time 6.22 seconds
Started Mar 31 01:26:59 PM PDT 24
Finished Mar 31 01:27:05 PM PDT 24
Peak memory 200988 kb
Host smart-8871b940-0e7e-489d-bbc7-4e9de22a7428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462389758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.462389758
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3934293345
Short name T475
Test name
Test status
Simulation time 177993707 ps
CPU time 1.17 seconds
Started Mar 31 01:26:57 PM PDT 24
Finished Mar 31 01:26:58 PM PDT 24
Peak memory 200840 kb
Host smart-bef99c29-6045-4e81-8dff-117609be12da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934293345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3934293345
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1278261876
Short name T240
Test name
Test status
Simulation time 253530800 ps
CPU time 1.61 seconds
Started Mar 31 01:27:00 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 200988 kb
Host smart-3eb13e70-56c9-4ee7-afd5-32b1759faa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278261876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1278261876
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1572027672
Short name T45
Test name
Test status
Simulation time 3348606582 ps
CPU time 16.46 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:27:15 PM PDT 24
Peak memory 201032 kb
Host smart-633eee67-7aef-4180-8c11-edf874969d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572027672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1572027672
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2338178133
Short name T337
Test name
Test status
Simulation time 149272995 ps
CPU time 1.8 seconds
Started Mar 31 01:26:57 PM PDT 24
Finished Mar 31 01:26:59 PM PDT 24
Peak memory 200848 kb
Host smart-72bdc557-d202-4944-a951-aa8f7e51507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338178133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2338178133
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2307318865
Short name T484
Test name
Test status
Simulation time 87576389 ps
CPU time 0.84 seconds
Started Mar 31 01:26:55 PM PDT 24
Finished Mar 31 01:26:56 PM PDT 24
Peak memory 200848 kb
Host smart-34483a03-52cb-471e-8410-c90a8d8d948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307318865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2307318865
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.4236386757
Short name T270
Test name
Test status
Simulation time 71164598 ps
CPU time 0.74 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:26:59 PM PDT 24
Peak memory 200672 kb
Host smart-3862c23c-8d1e-4b27-b643-feb70b5916fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236386757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4236386757
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.164849943
Short name T390
Test name
Test status
Simulation time 1230255855 ps
CPU time 5.96 seconds
Started Mar 31 01:26:57 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 217540 kb
Host smart-0280fb61-caa9-4513-9727-ba39a1f52952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164849943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.164849943
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1159499090
Short name T338
Test name
Test status
Simulation time 244871368 ps
CPU time 1.06 seconds
Started Mar 31 01:27:04 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 218020 kb
Host smart-7a16e829-6a8e-45ee-81cc-67a72116783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159499090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1159499090
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3920442907
Short name T507
Test name
Test status
Simulation time 164746359 ps
CPU time 0.9 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:26:59 PM PDT 24
Peak memory 200684 kb
Host smart-124a02c5-62f5-4079-8a4c-9b6009aa4437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920442907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3920442907
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2913387940
Short name T477
Test name
Test status
Simulation time 911953188 ps
CPU time 4.62 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 201000 kb
Host smart-6904c14e-942e-4aed-8f18-bc347cc1f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913387940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2913387940
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2568945965
Short name T523
Test name
Test status
Simulation time 100735182 ps
CPU time 1.02 seconds
Started Mar 31 01:26:59 PM PDT 24
Finished Mar 31 01:27:01 PM PDT 24
Peak memory 200768 kb
Host smart-cdac41b3-9caa-402f-9ab0-a8fadb976507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568945965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2568945965
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4013821839
Short name T119
Test name
Test status
Simulation time 246691485 ps
CPU time 1.54 seconds
Started Mar 31 01:26:56 PM PDT 24
Finished Mar 31 01:26:57 PM PDT 24
Peak memory 200988 kb
Host smart-61eb11b4-8f87-468c-a724-d14b0a2e5cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013821839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4013821839
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.969043293
Short name T421
Test name
Test status
Simulation time 2062629290 ps
CPU time 9.56 seconds
Started Mar 31 01:26:59 PM PDT 24
Finished Mar 31 01:27:09 PM PDT 24
Peak memory 201012 kb
Host smart-9bfbd3bf-b66a-4a5d-afdc-ea224184f63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969043293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.969043293
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3621264473
Short name T283
Test name
Test status
Simulation time 116814461 ps
CPU time 0.95 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:05 PM PDT 24
Peak memory 200584 kb
Host smart-8ca58afd-94ec-4961-8f88-5deb1153c035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621264473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3621264473
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1181153929
Short name T387
Test name
Test status
Simulation time 58322219 ps
CPU time 0.75 seconds
Started Mar 31 01:26:59 PM PDT 24
Finished Mar 31 01:27:00 PM PDT 24
Peak memory 200820 kb
Host smart-7e9e1654-b8ee-4b76-ad91-bc3b582a117d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181153929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1181153929
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2403877291
Short name T287
Test name
Test status
Simulation time 1893841662 ps
CPU time 6.96 seconds
Started Mar 31 01:27:00 PM PDT 24
Finished Mar 31 01:27:08 PM PDT 24
Peak memory 230024 kb
Host smart-eb527a6e-2f6a-43c6-91a8-e3bece43982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403877291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2403877291
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3183904285
Short name T210
Test name
Test status
Simulation time 245905320 ps
CPU time 1.08 seconds
Started Mar 31 01:26:57 PM PDT 24
Finished Mar 31 01:26:58 PM PDT 24
Peak memory 218252 kb
Host smart-6df7f467-0761-4a36-85c7-153b208034fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183904285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3183904285
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.4134185538
Short name T306
Test name
Test status
Simulation time 206524255 ps
CPU time 0.91 seconds
Started Mar 31 01:27:04 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 200636 kb
Host smart-9f827e14-c751-42f1-bae2-0dffb17002d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134185538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.4134185538
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2651453963
Short name T410
Test name
Test status
Simulation time 1400168147 ps
CPU time 5.44 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:27:04 PM PDT 24
Peak memory 201016 kb
Host smart-5224279f-eecc-4e6a-93fd-5aa3016c0223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651453963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2651453963
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1569709626
Short name T263
Test name
Test status
Simulation time 153782400 ps
CPU time 1.17 seconds
Started Mar 31 01:26:59 PM PDT 24
Finished Mar 31 01:27:01 PM PDT 24
Peak memory 200800 kb
Host smart-7184f76c-94b9-4b17-b0eb-1ee9d959729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569709626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1569709626
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2758746520
Short name T291
Test name
Test status
Simulation time 248747212 ps
CPU time 1.49 seconds
Started Mar 31 01:26:56 PM PDT 24
Finished Mar 31 01:26:58 PM PDT 24
Peak memory 201048 kb
Host smart-0eb44753-ac4b-4407-83a6-c15e414c7fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758746520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2758746520
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2365422451
Short name T97
Test name
Test status
Simulation time 2909187947 ps
CPU time 11.49 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 209332 kb
Host smart-c472e0d0-d61a-409c-9583-6ffb86880914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365422451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2365422451
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2355250549
Short name T293
Test name
Test status
Simulation time 109280250 ps
CPU time 1.43 seconds
Started Mar 31 01:26:55 PM PDT 24
Finished Mar 31 01:26:57 PM PDT 24
Peak memory 200928 kb
Host smart-e4abef03-235d-41ce-a103-f67f3524624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355250549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2355250549
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.4023055738
Short name T205
Test name
Test status
Simulation time 63790400 ps
CPU time 0.75 seconds
Started Mar 31 01:26:59 PM PDT 24
Finished Mar 31 01:27:01 PM PDT 24
Peak memory 200824 kb
Host smart-df3fe387-9ca3-42de-ac49-a245d88261df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023055738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.4023055738
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1403169771
Short name T253
Test name
Test status
Simulation time 59403250 ps
CPU time 0.77 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:05 PM PDT 24
Peak memory 200292 kb
Host smart-2965c886-3db3-4a21-bbb9-f3b652d740ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403169771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1403169771
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1507477800
Short name T52
Test name
Test status
Simulation time 2368722008 ps
CPU time 7.9 seconds
Started Mar 31 01:26:56 PM PDT 24
Finished Mar 31 01:27:04 PM PDT 24
Peak memory 217856 kb
Host smart-2b8e8043-94b2-4fc3-b043-4cc0baa467ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507477800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1507477800
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.12321966
Short name T538
Test name
Test status
Simulation time 244071787 ps
CPU time 1.21 seconds
Started Mar 31 01:26:57 PM PDT 24
Finished Mar 31 01:26:58 PM PDT 24
Peak memory 218160 kb
Host smart-99ac657d-f50e-4ad2-a164-1b9003e91f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12321966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.12321966
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1127848289
Short name T198
Test name
Test status
Simulation time 119997939 ps
CPU time 0.78 seconds
Started Mar 31 01:27:00 PM PDT 24
Finished Mar 31 01:27:01 PM PDT 24
Peak memory 200680 kb
Host smart-faf116a8-7139-448b-aa55-97581352c4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127848289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1127848289
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.891296019
Short name T236
Test name
Test status
Simulation time 1887679328 ps
CPU time 6.64 seconds
Started Mar 31 01:26:56 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 201024 kb
Host smart-967f42d3-6c49-41c5-afae-833df42122d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891296019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.891296019
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3523882468
Short name T494
Test name
Test status
Simulation time 159692134 ps
CPU time 1.11 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:26:59 PM PDT 24
Peak memory 200836 kb
Host smart-7c380a1a-e8ac-428b-80f0-0d3fe86f189c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523882468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3523882468
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2051177751
Short name T81
Test name
Test status
Simulation time 198661520 ps
CPU time 1.39 seconds
Started Mar 31 01:27:04 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 200916 kb
Host smart-bc5b8406-ed91-4702-af94-02ebcb70cbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051177751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2051177751
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3149325590
Short name T73
Test name
Test status
Simulation time 612753449 ps
CPU time 2.58 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:27:01 PM PDT 24
Peak memory 201016 kb
Host smart-f0a2618f-4d40-4a1f-a32c-51ce7f954948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149325590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3149325590
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1473698096
Short name T310
Test name
Test status
Simulation time 501942091 ps
CPU time 2.44 seconds
Started Mar 31 01:26:57 PM PDT 24
Finished Mar 31 01:27:00 PM PDT 24
Peak memory 200888 kb
Host smart-036ec804-95f9-4788-bbe0-15610b94f9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473698096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1473698096
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.375074108
Short name T75
Test name
Test status
Simulation time 69484362 ps
CPU time 0.77 seconds
Started Mar 31 01:26:57 PM PDT 24
Finished Mar 31 01:26:58 PM PDT 24
Peak memory 200840 kb
Host smart-6fefc605-5cf0-4f7f-b93d-51327812fe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375074108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.375074108
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.661736374
Short name T206
Test name
Test status
Simulation time 58821696 ps
CPU time 0.76 seconds
Started Mar 31 01:27:05 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 200392 kb
Host smart-b9709b94-7eba-4995-a05d-248673e30706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661736374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.661736374
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.873464958
Short name T404
Test name
Test status
Simulation time 2353804843 ps
CPU time 8.86 seconds
Started Mar 31 01:27:02 PM PDT 24
Finished Mar 31 01:27:12 PM PDT 24
Peak memory 218616 kb
Host smart-e826c015-461a-444e-b796-11dc402c6583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873464958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.873464958
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.59591723
Short name T262
Test name
Test status
Simulation time 243654522 ps
CPU time 1.07 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:05 PM PDT 24
Peak memory 218136 kb
Host smart-1f331cf4-c1a5-45c4-9a2f-fbf6279d6fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59591723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.59591723
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.746612178
Short name T249
Test name
Test status
Simulation time 258617536 ps
CPU time 0.92 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:26:59 PM PDT 24
Peak memory 200688 kb
Host smart-00be2f8c-0032-4ab5-8af1-d9e2388208ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746612178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.746612178
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2080014055
Short name T3
Test name
Test status
Simulation time 835819499 ps
CPU time 4.31 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:27:02 PM PDT 24
Peak memory 201028 kb
Host smart-d53d8177-e273-43c8-ae07-7ef965d35b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080014055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2080014055
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2433290638
Short name T521
Test name
Test status
Simulation time 141245779 ps
CPU time 1.15 seconds
Started Mar 31 01:27:02 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 200800 kb
Host smart-73934bd9-d4e4-4db3-a352-2ff67adb338d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433290638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2433290638
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2696897703
Short name T176
Test name
Test status
Simulation time 123080549 ps
CPU time 1.25 seconds
Started Mar 31 01:26:58 PM PDT 24
Finished Mar 31 01:26:59 PM PDT 24
Peak memory 201024 kb
Host smart-e4b136f5-e7e5-4c98-b845-36af973f4921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696897703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2696897703
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2878287291
Short name T96
Test name
Test status
Simulation time 12208630933 ps
CPU time 41.26 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:45 PM PDT 24
Peak memory 209284 kb
Host smart-294a0a41-fd8c-4d87-9a3b-024c3d3f5f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878287291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2878287291
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.4195493734
Short name T498
Test name
Test status
Simulation time 360905330 ps
CPU time 2.53 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:05 PM PDT 24
Peak memory 200888 kb
Host smart-767e3a86-0e54-4753-bbb2-7cfb368e03d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195493734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.4195493734
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2265070410
Short name T344
Test name
Test status
Simulation time 156862691 ps
CPU time 1.25 seconds
Started Mar 31 01:26:59 PM PDT 24
Finished Mar 31 01:27:01 PM PDT 24
Peak memory 201008 kb
Host smart-e9ed506e-4699-47dc-a7ad-2219e6e94424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265070410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2265070410
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2108479007
Short name T294
Test name
Test status
Simulation time 70660178 ps
CPU time 0.82 seconds
Started Mar 31 01:27:09 PM PDT 24
Finished Mar 31 01:27:11 PM PDT 24
Peak memory 200648 kb
Host smart-5082c9c6-874c-4454-8e60-032fd2190275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108479007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2108479007
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.4015741408
Short name T36
Test name
Test status
Simulation time 1225325984 ps
CPU time 6.17 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 222560 kb
Host smart-38b03efb-7ddd-407d-8d97-ba1a70c587c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015741408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.4015741408
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.35965753
Short name T274
Test name
Test status
Simulation time 244125107 ps
CPU time 1.08 seconds
Started Mar 31 01:27:09 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 218100 kb
Host smart-c8199205-4740-4fb6-a15e-0b588eb9ee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35965753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.35965753
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1035789558
Short name T20
Test name
Test status
Simulation time 218030600 ps
CPU time 0.9 seconds
Started Mar 31 01:27:02 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 200716 kb
Host smart-80e3dd3b-c11b-42ce-8545-413a6edf60e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035789558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1035789558
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1319166694
Short name T25
Test name
Test status
Simulation time 1559258550 ps
CPU time 6.04 seconds
Started Mar 31 01:27:05 PM PDT 24
Finished Mar 31 01:27:12 PM PDT 24
Peak memory 200988 kb
Host smart-6250fa25-a702-4f6b-8138-4a60b0cd9e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319166694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1319166694
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1112166011
Short name T385
Test name
Test status
Simulation time 155746012 ps
CPU time 1.12 seconds
Started Mar 31 01:27:04 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 200736 kb
Host smart-a9e06a6f-589a-467a-820f-7ed2a566bd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112166011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1112166011
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3314839424
Short name T452
Test name
Test status
Simulation time 124868984 ps
CPU time 1.26 seconds
Started Mar 31 01:27:04 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 200960 kb
Host smart-4180211e-17d8-439d-935a-0c4f65aceb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314839424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3314839424
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.911828435
Short name T514
Test name
Test status
Simulation time 4143945255 ps
CPU time 13.77 seconds
Started Mar 31 01:27:04 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 201148 kb
Host smart-63c38364-c8aa-4db8-af54-9ce1e55f8702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911828435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.911828435
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2901689344
Short name T178
Test name
Test status
Simulation time 325408081 ps
CPU time 2.05 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:05 PM PDT 24
Peak memory 200884 kb
Host smart-19795621-29d5-4368-9b36-d7ca911d3271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901689344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2901689344
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.362896886
Short name T280
Test name
Test status
Simulation time 220370735 ps
CPU time 1.26 seconds
Started Mar 31 01:27:06 PM PDT 24
Finished Mar 31 01:27:07 PM PDT 24
Peak memory 200796 kb
Host smart-8569ec2e-7ea3-4579-bdc8-be7713d936d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362896886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.362896886
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3913333778
Short name T313
Test name
Test status
Simulation time 65871862 ps
CPU time 0.77 seconds
Started Mar 31 01:26:19 PM PDT 24
Finished Mar 31 01:26:20 PM PDT 24
Peak memory 200716 kb
Host smart-7e0e6e36-226c-4fc6-93f2-990e57e2383d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913333778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3913333778
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.4289646153
Short name T519
Test name
Test status
Simulation time 1893175718 ps
CPU time 7.39 seconds
Started Mar 31 01:26:17 PM PDT 24
Finished Mar 31 01:26:24 PM PDT 24
Peak memory 218540 kb
Host smart-ab9f9300-505e-4c67-a8f8-f6b9423d3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289646153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.4289646153
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2124230094
Short name T342
Test name
Test status
Simulation time 245791424 ps
CPU time 1.11 seconds
Started Mar 31 01:26:18 PM PDT 24
Finished Mar 31 01:26:19 PM PDT 24
Peak memory 218416 kb
Host smart-333eebe9-dc15-4cda-8d9e-a0fdb236c5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124230094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2124230094
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1652400556
Short name T482
Test name
Test status
Simulation time 138197326 ps
CPU time 0.84 seconds
Started Mar 31 01:26:18 PM PDT 24
Finished Mar 31 01:26:19 PM PDT 24
Peak memory 200816 kb
Host smart-ca37c296-afe1-4c78-9417-b5786de7734f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652400556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1652400556
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3360026200
Short name T94
Test name
Test status
Simulation time 874630857 ps
CPU time 3.87 seconds
Started Mar 31 01:26:16 PM PDT 24
Finished Mar 31 01:26:20 PM PDT 24
Peak memory 201036 kb
Host smart-3088ebc1-3ec7-4f31-8a8a-75d1e17603a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360026200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3360026200
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2483007581
Short name T67
Test name
Test status
Simulation time 8299773499 ps
CPU time 13.28 seconds
Started Mar 31 01:26:22 PM PDT 24
Finished Mar 31 01:26:36 PM PDT 24
Peak memory 218388 kb
Host smart-76a40d13-c321-430c-ac59-7191e57a3afa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483007581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2483007581
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1943472459
Short name T462
Test name
Test status
Simulation time 162659725 ps
CPU time 1.21 seconds
Started Mar 31 01:26:20 PM PDT 24
Finished Mar 31 01:26:21 PM PDT 24
Peak memory 200856 kb
Host smart-f7cf6a18-7525-47de-b3a2-3888c92b6adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943472459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1943472459
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3292795974
Short name T451
Test name
Test status
Simulation time 190745680 ps
CPU time 1.26 seconds
Started Mar 31 01:26:16 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 200912 kb
Host smart-ace7c330-431b-4409-ac0e-bdfa3d61502c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292795974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3292795974
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.634322326
Short name T117
Test name
Test status
Simulation time 9274772442 ps
CPU time 33.39 seconds
Started Mar 31 01:26:23 PM PDT 24
Finished Mar 31 01:26:57 PM PDT 24
Peak memory 209276 kb
Host smart-13e61dc4-4acf-421f-b330-9a8009f4f813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634322326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.634322326
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1545639127
Short name T362
Test name
Test status
Simulation time 114498926 ps
CPU time 1.38 seconds
Started Mar 31 01:26:16 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 200916 kb
Host smart-aab87ac3-a554-4943-a9ca-bc5e4e625112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545639127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1545639127
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1022098434
Short name T413
Test name
Test status
Simulation time 148955983 ps
CPU time 1.02 seconds
Started Mar 31 01:26:18 PM PDT 24
Finished Mar 31 01:26:19 PM PDT 24
Peak memory 200840 kb
Host smart-090de812-aebf-4c3a-b726-721c9a27e5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022098434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1022098434
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3206934617
Short name T69
Test name
Test status
Simulation time 79073982 ps
CPU time 0.8 seconds
Started Mar 31 01:27:05 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 200728 kb
Host smart-4f064c08-0943-44ac-b43d-96a94be1ad06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206934617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3206934617
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1992084332
Short name T537
Test name
Test status
Simulation time 1221670739 ps
CPU time 5.59 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:09 PM PDT 24
Peak memory 222560 kb
Host smart-5296c3a2-2922-4a06-9e52-f880ee9dcd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992084332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1992084332
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3211433352
Short name T301
Test name
Test status
Simulation time 244575710 ps
CPU time 1.06 seconds
Started Mar 31 01:27:04 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 218036 kb
Host smart-0e9a142e-e8c4-423e-9873-9a258d6c755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211433352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3211433352
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2495049098
Short name T314
Test name
Test status
Simulation time 110037176 ps
CPU time 0.8 seconds
Started Mar 31 01:27:06 PM PDT 24
Finished Mar 31 01:27:07 PM PDT 24
Peak memory 200668 kb
Host smart-f6523abb-1f7b-45c7-8550-a2aac8b042a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495049098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2495049098
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.913797523
Short name T193
Test name
Test status
Simulation time 1257793898 ps
CPU time 5.12 seconds
Started Mar 31 01:27:04 PM PDT 24
Finished Mar 31 01:27:09 PM PDT 24
Peak memory 201008 kb
Host smart-ad78fa48-7d8e-4101-b5d7-56116f11914d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913797523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.913797523
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.847816811
Short name T213
Test name
Test status
Simulation time 148200885 ps
CPU time 1.1 seconds
Started Mar 31 01:27:02 PM PDT 24
Finished Mar 31 01:27:04 PM PDT 24
Peak memory 200808 kb
Host smart-f3ab11f3-c4a3-423c-929d-acc74366d195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847816811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.847816811
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2756396455
Short name T138
Test name
Test status
Simulation time 122901883 ps
CPU time 1.3 seconds
Started Mar 31 01:27:09 PM PDT 24
Finished Mar 31 01:27:11 PM PDT 24
Peak memory 200944 kb
Host smart-97dc4f6f-e16a-4367-b03d-8dbee0212e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756396455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2756396455
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3218893162
Short name T203
Test name
Test status
Simulation time 3823023382 ps
CPU time 14.21 seconds
Started Mar 31 01:27:02 PM PDT 24
Finished Mar 31 01:27:17 PM PDT 24
Peak memory 209364 kb
Host smart-bdc8824b-1b24-4d4b-a4dc-a7a73b86900d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218893162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3218893162
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3441545426
Short name T446
Test name
Test status
Simulation time 106317477 ps
CPU time 1.35 seconds
Started Mar 31 01:27:05 PM PDT 24
Finished Mar 31 01:27:07 PM PDT 24
Peak memory 200884 kb
Host smart-89294a8a-a2ff-4b78-a539-074f82ef8333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441545426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3441545426
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.456789895
Short name T329
Test name
Test status
Simulation time 80277742 ps
CPU time 0.91 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:05 PM PDT 24
Peak memory 200844 kb
Host smart-76b0bd80-9d55-4eb2-9f1b-f6b9dbafa1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456789895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.456789895
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2150213849
Short name T373
Test name
Test status
Simulation time 60031647 ps
CPU time 0.75 seconds
Started Mar 31 01:27:11 PM PDT 24
Finished Mar 31 01:27:12 PM PDT 24
Peak memory 200728 kb
Host smart-5db13ad5-30ed-4c00-8de3-7200c005bb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150213849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2150213849
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.608857461
Short name T376
Test name
Test status
Simulation time 2367099435 ps
CPU time 8.21 seconds
Started Mar 31 01:27:10 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 217844 kb
Host smart-c60d2dbe-7ac2-4fe8-8f1b-b041d4cf06c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608857461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.608857461
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3953123052
Short name T374
Test name
Test status
Simulation time 244190401 ps
CPU time 1.13 seconds
Started Mar 31 01:27:10 PM PDT 24
Finished Mar 31 01:27:11 PM PDT 24
Peak memory 218156 kb
Host smart-5a12a016-f3d3-42eb-adf3-aef1c6074a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953123052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3953123052
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1347458176
Short name T13
Test name
Test status
Simulation time 183904399 ps
CPU time 0.84 seconds
Started Mar 31 01:27:01 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 200628 kb
Host smart-9b4b1f81-55d9-4642-9dba-6b6c76953271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347458176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1347458176
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.605323143
Short name T95
Test name
Test status
Simulation time 714242812 ps
CPU time 4.08 seconds
Started Mar 31 01:27:05 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 200756 kb
Host smart-12add529-7fc7-4ae5-936e-d028df0abf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605323143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.605323143
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.457525126
Short name T39
Test name
Test status
Simulation time 154774781 ps
CPU time 1.07 seconds
Started Mar 31 01:27:09 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 200884 kb
Host smart-387a6e1f-a800-4c14-a9d0-b45bfbd41b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457525126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.457525126
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.330548529
Short name T336
Test name
Test status
Simulation time 243286045 ps
CPU time 1.6 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:05 PM PDT 24
Peak memory 201020 kb
Host smart-bfd1e2ff-0ddc-47ab-8ff7-401d400eeabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330548529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.330548529
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3525570281
Short name T412
Test name
Test status
Simulation time 1971217823 ps
CPU time 9.51 seconds
Started Mar 31 01:27:14 PM PDT 24
Finished Mar 31 01:27:24 PM PDT 24
Peak memory 209252 kb
Host smart-8721c0ce-2c12-4186-b1b4-80d34209129e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525570281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3525570281
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3290711603
Short name T131
Test name
Test status
Simulation time 141205152 ps
CPU time 1.93 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:06 PM PDT 24
Peak memory 200860 kb
Host smart-2338316f-a5a2-45aa-8c30-6ebb09908308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290711603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3290711603
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1389049371
Short name T520
Test name
Test status
Simulation time 84908345 ps
CPU time 0.83 seconds
Started Mar 31 01:27:03 PM PDT 24
Finished Mar 31 01:27:04 PM PDT 24
Peak memory 200828 kb
Host smart-f59130f0-482e-4536-aa5b-7715908595a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389049371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1389049371
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2899988093
Short name T473
Test name
Test status
Simulation time 75707254 ps
CPU time 0.8 seconds
Started Mar 31 01:27:09 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 200708 kb
Host smart-0fcb1be6-df56-445d-a708-91f8aca2cc83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899988093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2899988093
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2078748403
Short name T503
Test name
Test status
Simulation time 1894258136 ps
CPU time 6.83 seconds
Started Mar 31 01:27:08 PM PDT 24
Finished Mar 31 01:27:16 PM PDT 24
Peak memory 221580 kb
Host smart-3b4bbd5e-59ff-4b6b-9174-3f1bc4d1f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078748403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2078748403
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.858516717
Short name T151
Test name
Test status
Simulation time 244500490 ps
CPU time 1.09 seconds
Started Mar 31 01:27:11 PM PDT 24
Finished Mar 31 01:27:12 PM PDT 24
Peak memory 218148 kb
Host smart-0bd55f5e-d90c-4d96-a284-c5a04317cc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858516717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.858516717
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2665539731
Short name T367
Test name
Test status
Simulation time 120366344 ps
CPU time 0.86 seconds
Started Mar 31 01:27:11 PM PDT 24
Finished Mar 31 01:27:12 PM PDT 24
Peak memory 200704 kb
Host smart-0652c174-b722-4192-a07e-cfe5ceff7a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665539731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2665539731
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2937519254
Short name T1
Test name
Test status
Simulation time 1234543022 ps
CPU time 5.15 seconds
Started Mar 31 01:27:12 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 201036 kb
Host smart-b37123f8-a2a1-4230-97dd-02af97d4f173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937519254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2937519254
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3664926601
Short name T435
Test name
Test status
Simulation time 149705696 ps
CPU time 1.11 seconds
Started Mar 31 01:27:09 PM PDT 24
Finished Mar 31 01:27:11 PM PDT 24
Peak memory 200948 kb
Host smart-5e2cb3b5-bb58-4188-afcd-80b34c9dc2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664926601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3664926601
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.584364081
Short name T395
Test name
Test status
Simulation time 124368711 ps
CPU time 1.25 seconds
Started Mar 31 01:27:10 PM PDT 24
Finished Mar 31 01:27:11 PM PDT 24
Peak memory 200960 kb
Host smart-f6e73c38-4187-4340-8f50-78f880f02cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584364081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.584364081
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3893034657
Short name T295
Test name
Test status
Simulation time 1481759242 ps
CPU time 6.62 seconds
Started Mar 31 01:27:09 PM PDT 24
Finished Mar 31 01:27:17 PM PDT 24
Peak memory 200968 kb
Host smart-5104150a-0187-4b03-a264-48109d98f219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893034657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3893034657
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.687389495
Short name T162
Test name
Test status
Simulation time 362618888 ps
CPU time 2.32 seconds
Started Mar 31 01:27:11 PM PDT 24
Finished Mar 31 01:27:14 PM PDT 24
Peak memory 200848 kb
Host smart-16d9f1e5-6b64-4ed1-88db-92ce125fd7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687389495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.687389495
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2161255314
Short name T352
Test name
Test status
Simulation time 134318424 ps
CPU time 1.12 seconds
Started Mar 31 01:27:10 PM PDT 24
Finished Mar 31 01:27:11 PM PDT 24
Peak memory 200840 kb
Host smart-1eb4cd8e-b61a-4c6d-b5a4-d1d90f031940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161255314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2161255314
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1788695511
Short name T456
Test name
Test status
Simulation time 59024507 ps
CPU time 0.71 seconds
Started Mar 31 01:27:18 PM PDT 24
Finished Mar 31 01:27:19 PM PDT 24
Peak memory 200712 kb
Host smart-ca6797aa-4040-4ea4-a6ef-02c3f0e33df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788695511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1788695511
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1363973730
Short name T27
Test name
Test status
Simulation time 2189331387 ps
CPU time 7.88 seconds
Started Mar 31 01:27:12 PM PDT 24
Finished Mar 31 01:27:20 PM PDT 24
Peak memory 222692 kb
Host smart-9b8a1029-660c-418b-8e86-18e1dc50b120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363973730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1363973730
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1336079476
Short name T485
Test name
Test status
Simulation time 243665897 ps
CPU time 1.05 seconds
Started Mar 31 01:27:08 PM PDT 24
Finished Mar 31 01:27:10 PM PDT 24
Peak memory 218156 kb
Host smart-db0ce63e-17ba-46e6-9733-1ea49bfcfc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336079476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1336079476
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2331479200
Short name T331
Test name
Test status
Simulation time 103532636 ps
CPU time 0.79 seconds
Started Mar 31 01:27:12 PM PDT 24
Finished Mar 31 01:27:14 PM PDT 24
Peak memory 200680 kb
Host smart-dbbad839-257f-4c30-a232-ff7724dfbcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331479200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2331479200
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3673668555
Short name T279
Test name
Test status
Simulation time 1411039457 ps
CPU time 6 seconds
Started Mar 31 01:27:13 PM PDT 24
Finished Mar 31 01:27:19 PM PDT 24
Peak memory 200952 kb
Host smart-cc29937a-a3d4-4d85-9975-3746e4563c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673668555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3673668555
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.261246811
Short name T24
Test name
Test status
Simulation time 102146890 ps
CPU time 1.05 seconds
Started Mar 31 01:27:11 PM PDT 24
Finished Mar 31 01:27:12 PM PDT 24
Peak memory 200772 kb
Host smart-d2f81ec8-d75f-43e0-9eb8-642fe48d35e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261246811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.261246811
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2151624325
Short name T259
Test name
Test status
Simulation time 235115828 ps
CPU time 1.42 seconds
Started Mar 31 01:27:12 PM PDT 24
Finished Mar 31 01:27:13 PM PDT 24
Peak memory 201000 kb
Host smart-11e13e21-73fe-4dbf-a3d0-73d1c96c7bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151624325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2151624325
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.379457900
Short name T79
Test name
Test status
Simulation time 7324098614 ps
CPU time 32.07 seconds
Started Mar 31 01:27:10 PM PDT 24
Finished Mar 31 01:27:42 PM PDT 24
Peak memory 201120 kb
Host smart-cb4dc709-f953-400b-8951-f703eb364c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379457900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.379457900
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3124714721
Short name T460
Test name
Test status
Simulation time 148451439 ps
CPU time 1.83 seconds
Started Mar 31 01:27:12 PM PDT 24
Finished Mar 31 01:27:15 PM PDT 24
Peak memory 200880 kb
Host smart-f060e4ff-fc06-40cf-950d-29bf6728658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124714721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3124714721
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2960820874
Short name T218
Test name
Test status
Simulation time 80320019 ps
CPU time 0.87 seconds
Started Mar 31 01:27:13 PM PDT 24
Finished Mar 31 01:27:14 PM PDT 24
Peak memory 200840 kb
Host smart-eca5d801-adfd-47cd-ad91-ec2f379de9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960820874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2960820874
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2622765295
Short name T177
Test name
Test status
Simulation time 70113371 ps
CPU time 0.77 seconds
Started Mar 31 01:27:18 PM PDT 24
Finished Mar 31 01:27:19 PM PDT 24
Peak memory 200712 kb
Host smart-a90724d4-978b-47c6-98f6-d14435ef4eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622765295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2622765295
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1338596472
Short name T54
Test name
Test status
Simulation time 1883795339 ps
CPU time 7.34 seconds
Started Mar 31 01:27:18 PM PDT 24
Finished Mar 31 01:27:26 PM PDT 24
Peak memory 222564 kb
Host smart-101b1406-6628-4b9b-bb19-b4c6031cff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338596472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1338596472
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2013669881
Short name T441
Test name
Test status
Simulation time 245276757 ps
CPU time 1.04 seconds
Started Mar 31 01:27:19 PM PDT 24
Finished Mar 31 01:27:21 PM PDT 24
Peak memory 218036 kb
Host smart-8e93a7bc-4ada-45d6-a0d1-3ca4009ef556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013669881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2013669881
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3367102674
Short name T479
Test name
Test status
Simulation time 127578572 ps
CPU time 0.79 seconds
Started Mar 31 01:27:17 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 200676 kb
Host smart-9610cec6-fcb2-4d98-9468-6a4fc13ea2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367102674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3367102674
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3114736309
Short name T360
Test name
Test status
Simulation time 1474800855 ps
CPU time 5.52 seconds
Started Mar 31 01:27:24 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200952 kb
Host smart-61318a00-9077-4375-b255-3ea43c1ee155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114736309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3114736309
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3378050713
Short name T21
Test name
Test status
Simulation time 101745941 ps
CPU time 0.92 seconds
Started Mar 31 01:27:15 PM PDT 24
Finished Mar 31 01:27:16 PM PDT 24
Peak memory 200844 kb
Host smart-e7855376-3aca-4d45-b309-dd5f4ebb7c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378050713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3378050713
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2262006180
Short name T126
Test name
Test status
Simulation time 112040693 ps
CPU time 1.18 seconds
Started Mar 31 01:27:17 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 201040 kb
Host smart-2557a2ab-2ce2-49a4-9a2b-b035668d5c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262006180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2262006180
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2927034476
Short name T407
Test name
Test status
Simulation time 128410527 ps
CPU time 1.78 seconds
Started Mar 31 01:27:21 PM PDT 24
Finished Mar 31 01:27:23 PM PDT 24
Peak memory 200924 kb
Host smart-73db8411-d12f-427e-b7e5-3e966d184129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927034476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2927034476
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3509343892
Short name T502
Test name
Test status
Simulation time 118276163 ps
CPU time 1.01 seconds
Started Mar 31 01:27:19 PM PDT 24
Finished Mar 31 01:27:21 PM PDT 24
Peak memory 200820 kb
Host smart-6be1369e-1746-48ce-aea0-209bf0759100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509343892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3509343892
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2897263471
Short name T261
Test name
Test status
Simulation time 71854756 ps
CPU time 0.75 seconds
Started Mar 31 01:27:19 PM PDT 24
Finished Mar 31 01:27:20 PM PDT 24
Peak memory 200820 kb
Host smart-f883eac0-793c-4cbd-a73c-fa05a91d74d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897263471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2897263471
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3819047482
Short name T28
Test name
Test status
Simulation time 1218948446 ps
CPU time 5.62 seconds
Started Mar 31 01:27:17 PM PDT 24
Finished Mar 31 01:27:23 PM PDT 24
Peak memory 217956 kb
Host smart-e4282ba2-a6af-447b-893f-3e857bd46f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819047482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3819047482
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1797780391
Short name T156
Test name
Test status
Simulation time 243608193 ps
CPU time 1.05 seconds
Started Mar 31 01:27:21 PM PDT 24
Finished Mar 31 01:27:22 PM PDT 24
Peak memory 218208 kb
Host smart-9a2491d5-ece7-42a7-a341-7c8001c38881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797780391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1797780391
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2804656343
Short name T454
Test name
Test status
Simulation time 128570587 ps
CPU time 0.79 seconds
Started Mar 31 01:27:17 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 200608 kb
Host smart-e946890d-cc03-450b-b391-28a0b181b504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804656343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2804656343
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3089953743
Short name T250
Test name
Test status
Simulation time 1601367038 ps
CPU time 6.24 seconds
Started Mar 31 01:27:20 PM PDT 24
Finished Mar 31 01:27:27 PM PDT 24
Peak memory 200944 kb
Host smart-001948e6-7fb1-4eb0-9c93-dfc057ad92d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089953743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3089953743
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1545685531
Short name T260
Test name
Test status
Simulation time 99040773 ps
CPU time 0.93 seconds
Started Mar 31 01:27:21 PM PDT 24
Finished Mar 31 01:27:22 PM PDT 24
Peak memory 200804 kb
Host smart-869aab4a-76bf-4f20-a3f3-9cafc52c1041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545685531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1545685531
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1369927553
Short name T368
Test name
Test status
Simulation time 116696821 ps
CPU time 1.2 seconds
Started Mar 31 01:27:17 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 201020 kb
Host smart-d738493a-6d95-4b8b-92b7-a9db9bb0a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369927553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1369927553
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3759215014
Short name T429
Test name
Test status
Simulation time 9657323789 ps
CPU time 34.22 seconds
Started Mar 31 01:27:23 PM PDT 24
Finished Mar 31 01:27:57 PM PDT 24
Peak memory 201292 kb
Host smart-25afc663-1556-487a-88b7-a226b40b78cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759215014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3759215014
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1905637546
Short name T182
Test name
Test status
Simulation time 149198025 ps
CPU time 1.69 seconds
Started Mar 31 01:27:17 PM PDT 24
Finished Mar 31 01:27:19 PM PDT 24
Peak memory 200908 kb
Host smart-d5e3dce1-f360-4998-970f-5cd65e4a980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905637546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1905637546
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2142013305
Short name T326
Test name
Test status
Simulation time 63572658 ps
CPU time 0.75 seconds
Started Mar 31 01:27:19 PM PDT 24
Finished Mar 31 01:27:20 PM PDT 24
Peak memory 200852 kb
Host smart-b117ee91-d0c6-49f8-8267-7040bf6fc686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142013305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2142013305
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1019177514
Short name T366
Test name
Test status
Simulation time 93693842 ps
CPU time 0.85 seconds
Started Mar 31 01:27:20 PM PDT 24
Finished Mar 31 01:27:21 PM PDT 24
Peak memory 200700 kb
Host smart-e8f84d66-d49b-47f0-9622-af5ca19e4de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019177514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1019177514
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1203933830
Short name T50
Test name
Test status
Simulation time 1223294111 ps
CPU time 5.67 seconds
Started Mar 31 01:27:19 PM PDT 24
Finished Mar 31 01:27:25 PM PDT 24
Peak memory 218540 kb
Host smart-fcba0433-8837-4b90-9476-be8cac818716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203933830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1203933830
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.4133644454
Short name T199
Test name
Test status
Simulation time 243817289 ps
CPU time 1.12 seconds
Started Mar 31 01:27:18 PM PDT 24
Finished Mar 31 01:27:19 PM PDT 24
Peak memory 218136 kb
Host smart-b1d2846f-03bc-4198-83a2-0aa780c5713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133644454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.4133644454
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2290974660
Short name T241
Test name
Test status
Simulation time 96287316 ps
CPU time 0.75 seconds
Started Mar 31 01:27:18 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 200724 kb
Host smart-c7931762-b483-4316-a412-43d7f9a39a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290974660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2290974660
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2498432267
Short name T26
Test name
Test status
Simulation time 1654711822 ps
CPU time 6.52 seconds
Started Mar 31 01:27:18 PM PDT 24
Finished Mar 31 01:27:25 PM PDT 24
Peak memory 200984 kb
Host smart-d242c511-2c38-4da8-b1a3-664c794bfe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498432267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2498432267
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3883836501
Short name T489
Test name
Test status
Simulation time 97913934 ps
CPU time 1.01 seconds
Started Mar 31 01:27:17 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 200884 kb
Host smart-ff0d243e-6e91-445e-baba-f589528fa472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883836501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3883836501
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3553110966
Short name T439
Test name
Test status
Simulation time 202291524 ps
CPU time 1.41 seconds
Started Mar 31 01:27:19 PM PDT 24
Finished Mar 31 01:27:21 PM PDT 24
Peak memory 201008 kb
Host smart-38f4c0da-55d0-4478-9301-9de1be07c7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553110966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3553110966
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2111566789
Short name T247
Test name
Test status
Simulation time 7900255346 ps
CPU time 37.87 seconds
Started Mar 31 01:27:16 PM PDT 24
Finished Mar 31 01:27:54 PM PDT 24
Peak memory 201392 kb
Host smart-4110cfc8-d873-4810-bbc8-652637e4ed56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111566789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2111566789
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1633272328
Short name T273
Test name
Test status
Simulation time 363199494 ps
CPU time 2.35 seconds
Started Mar 31 01:27:16 PM PDT 24
Finished Mar 31 01:27:19 PM PDT 24
Peak memory 200876 kb
Host smart-35d6db83-45df-47bc-9455-bf5e283260e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633272328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1633272328
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2053510670
Short name T186
Test name
Test status
Simulation time 203610775 ps
CPU time 1.26 seconds
Started Mar 31 01:27:19 PM PDT 24
Finished Mar 31 01:27:21 PM PDT 24
Peak memory 200788 kb
Host smart-d032f309-9754-41aa-bcdf-ad7d3375b179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053510670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2053510670
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.245125431
Short name T492
Test name
Test status
Simulation time 70117027 ps
CPU time 0.76 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:30 PM PDT 24
Peak memory 200636 kb
Host smart-c5334386-7552-4da5-bae8-6c36ca1ac2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245125431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.245125431
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.768179756
Short name T35
Test name
Test status
Simulation time 1219163986 ps
CPU time 5.61 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:33 PM PDT 24
Peak memory 218560 kb
Host smart-88d56d4f-bbe4-4f97-8be0-cce30ffdf66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768179756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.768179756
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.948889217
Short name T133
Test name
Test status
Simulation time 244409083 ps
CPU time 1.04 seconds
Started Mar 31 01:27:27 PM PDT 24
Finished Mar 31 01:27:28 PM PDT 24
Peak memory 218104 kb
Host smart-73bdff39-8acd-4142-be47-b5c45a25d6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948889217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.948889217
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.520527677
Short name T383
Test name
Test status
Simulation time 79207543 ps
CPU time 0.74 seconds
Started Mar 31 01:27:17 PM PDT 24
Finished Mar 31 01:27:18 PM PDT 24
Peak memory 200688 kb
Host smart-0fd4d25c-2304-4510-9c99-0f4cb8b5b904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520527677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.520527677
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2673841829
Short name T91
Test name
Test status
Simulation time 1693867835 ps
CPU time 6.07 seconds
Started Mar 31 01:27:19 PM PDT 24
Finished Mar 31 01:27:25 PM PDT 24
Peak memory 200920 kb
Host smart-7418dae6-3678-4049-b262-e81a023bf0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673841829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2673841829
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.293852456
Short name T361
Test name
Test status
Simulation time 172620015 ps
CPU time 1.17 seconds
Started Mar 31 01:27:27 PM PDT 24
Finished Mar 31 01:27:28 PM PDT 24
Peak memory 200816 kb
Host smart-43dc3c42-347f-476f-a90c-31672c41af80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293852456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.293852456
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2167497778
Short name T150
Test name
Test status
Simulation time 195743841 ps
CPU time 1.35 seconds
Started Mar 31 01:27:19 PM PDT 24
Finished Mar 31 01:27:21 PM PDT 24
Peak memory 201024 kb
Host smart-bc21e708-46e2-4433-a3e5-02dec6453a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167497778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2167497778
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3982157
Short name T470
Test name
Test status
Simulation time 309041774 ps
CPU time 2.06 seconds
Started Mar 31 01:27:26 PM PDT 24
Finished Mar 31 01:27:28 PM PDT 24
Peak memory 201016 kb
Host smart-3a429caa-6765-49fb-8207-73088ca9abc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3982157
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.961496566
Short name T438
Test name
Test status
Simulation time 539196180 ps
CPU time 2.64 seconds
Started Mar 31 01:27:33 PM PDT 24
Finished Mar 31 01:27:35 PM PDT 24
Peak memory 200864 kb
Host smart-1464ff69-cb20-46de-8ac9-2cedf95e77d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961496566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.961496566
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2740985401
Short name T458
Test name
Test status
Simulation time 158534291 ps
CPU time 1.09 seconds
Started Mar 31 01:27:24 PM PDT 24
Finished Mar 31 01:27:25 PM PDT 24
Peak memory 200776 kb
Host smart-df3718ea-f4ab-44c5-a70f-b1f3b63fa60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740985401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2740985401
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2459883478
Short name T418
Test name
Test status
Simulation time 75232745 ps
CPU time 0.85 seconds
Started Mar 31 01:27:26 PM PDT 24
Finished Mar 31 01:27:27 PM PDT 24
Peak memory 200668 kb
Host smart-ae38d085-3881-42c3-85bf-a2e3cde4c67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459883478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2459883478
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2441356752
Short name T459
Test name
Test status
Simulation time 2341226079 ps
CPU time 8.72 seconds
Started Mar 31 01:27:27 PM PDT 24
Finished Mar 31 01:27:36 PM PDT 24
Peak memory 218648 kb
Host smart-e1dfc947-9e8d-40ad-bd13-1a1545fed340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441356752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2441356752
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1386266349
Short name T501
Test name
Test status
Simulation time 244989733 ps
CPU time 1.07 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 218124 kb
Host smart-3c29aa95-a0f1-4586-ba07-65a6c7558a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386266349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1386266349
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.832458197
Short name T157
Test name
Test status
Simulation time 232784484 ps
CPU time 1 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200716 kb
Host smart-ad06fbcb-aeff-4678-81e8-49ef67090480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832458197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.832458197
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1324581205
Short name T356
Test name
Test status
Simulation time 1998219720 ps
CPU time 7.64 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:36 PM PDT 24
Peak memory 201024 kb
Host smart-ffe23189-cf79-4afc-91ac-1d71fc7d6c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324581205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1324581205
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3764969700
Short name T129
Test name
Test status
Simulation time 106024742 ps
CPU time 1.13 seconds
Started Mar 31 01:27:26 PM PDT 24
Finished Mar 31 01:27:28 PM PDT 24
Peak memory 200840 kb
Host smart-07ef1ed3-9e5b-4434-ab8e-a86d48509cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764969700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3764969700
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.949841879
Short name T534
Test name
Test status
Simulation time 229039375 ps
CPU time 1.44 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200972 kb
Host smart-10950bea-266c-461b-b62a-3d860da4a92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949841879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.949841879
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.485985598
Short name T324
Test name
Test status
Simulation time 3597389521 ps
CPU time 15.61 seconds
Started Mar 31 01:27:25 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 209332 kb
Host smart-45aa1005-f98e-42d8-9607-4dd7da84ddcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485985598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.485985598
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2123060062
Short name T55
Test name
Test status
Simulation time 503990669 ps
CPU time 2.53 seconds
Started Mar 31 01:27:26 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200876 kb
Host smart-56187ab2-1db5-46f8-876f-9594a8677b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123060062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2123060062
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1547777675
Short name T423
Test name
Test status
Simulation time 84274475 ps
CPU time 0.84 seconds
Started Mar 31 01:27:30 PM PDT 24
Finished Mar 31 01:27:31 PM PDT 24
Peak memory 200824 kb
Host smart-08f59dae-7f6c-432b-b992-c6f61e6af19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547777675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1547777675
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3128253052
Short name T315
Test name
Test status
Simulation time 61040214 ps
CPU time 0.75 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:30 PM PDT 24
Peak memory 200712 kb
Host smart-41f73392-85e6-44bd-b1f4-d3ccd34502f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128253052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3128253052
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3303222037
Short name T321
Test name
Test status
Simulation time 244692148 ps
CPU time 1.17 seconds
Started Mar 31 01:27:30 PM PDT 24
Finished Mar 31 01:27:31 PM PDT 24
Peak memory 217620 kb
Host smart-98a03ed0-cb33-4400-a094-cee31254661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303222037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3303222037
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.140815888
Short name T204
Test name
Test status
Simulation time 71069580 ps
CPU time 0.72 seconds
Started Mar 31 01:27:27 PM PDT 24
Finished Mar 31 01:27:27 PM PDT 24
Peak memory 200640 kb
Host smart-e6b8fce1-132a-4439-ad8c-5c0cfa51e412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140815888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.140815888
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2360486674
Short name T165
Test name
Test status
Simulation time 1718469714 ps
CPU time 6.59 seconds
Started Mar 31 01:27:30 PM PDT 24
Finished Mar 31 01:27:36 PM PDT 24
Peak memory 201000 kb
Host smart-38e213ce-f1af-4545-b0fa-b1b9798a7656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360486674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2360486674
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2768371933
Short name T124
Test name
Test status
Simulation time 110897451 ps
CPU time 1.03 seconds
Started Mar 31 01:27:26 PM PDT 24
Finished Mar 31 01:27:28 PM PDT 24
Peak memory 200836 kb
Host smart-63264946-578b-49c1-b4c9-adca5d8f6a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768371933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2768371933
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2560610216
Short name T448
Test name
Test status
Simulation time 248164960 ps
CPU time 1.46 seconds
Started Mar 31 01:27:32 PM PDT 24
Finished Mar 31 01:27:33 PM PDT 24
Peak memory 200940 kb
Host smart-1bb5051f-6c54-4e49-be9a-f5ce1235401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560610216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2560610216
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3893641946
Short name T343
Test name
Test status
Simulation time 1195292062 ps
CPU time 5.85 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:35 PM PDT 24
Peak memory 201020 kb
Host smart-66b4e29e-86e6-4a81-b223-49534b08a9e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893641946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3893641946
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.878996445
Short name T393
Test name
Test status
Simulation time 152120029 ps
CPU time 1.72 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:30 PM PDT 24
Peak memory 200900 kb
Host smart-c77fd6b7-9b57-49cb-b5b9-de5d897b23d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878996445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.878996445
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1080897349
Short name T347
Test name
Test status
Simulation time 85366712 ps
CPU time 0.86 seconds
Started Mar 31 01:27:30 PM PDT 24
Finished Mar 31 01:27:31 PM PDT 24
Peak memory 200852 kb
Host smart-3d3019e7-e988-4302-aa29-4cbe23cc656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080897349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1080897349
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3418158674
Short name T180
Test name
Test status
Simulation time 61528270 ps
CPU time 0.73 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:22 PM PDT 24
Peak memory 200652 kb
Host smart-f9a60ed7-8ae7-4697-9356-4215d57511f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418158674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3418158674
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3668665810
Short name T351
Test name
Test status
Simulation time 1890207095 ps
CPU time 6.99 seconds
Started Mar 31 01:26:18 PM PDT 24
Finished Mar 31 01:26:25 PM PDT 24
Peak memory 217960 kb
Host smart-925980f3-f87b-4f00-b818-d7d2d238c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668665810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3668665810
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3425774298
Short name T22
Test name
Test status
Simulation time 244375861 ps
CPU time 1.35 seconds
Started Mar 31 01:26:17 PM PDT 24
Finished Mar 31 01:26:19 PM PDT 24
Peak memory 218232 kb
Host smart-6efad2c9-0843-46d3-84ac-91492df4ebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425774298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3425774298
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.887702169
Short name T171
Test name
Test status
Simulation time 213987849 ps
CPU time 0.92 seconds
Started Mar 31 01:26:17 PM PDT 24
Finished Mar 31 01:26:18 PM PDT 24
Peak memory 200688 kb
Host smart-60391e5e-ffd6-4462-b35a-1f481ce82ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887702169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.887702169
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2396497757
Short name T455
Test name
Test status
Simulation time 768068840 ps
CPU time 4.05 seconds
Started Mar 31 01:26:17 PM PDT 24
Finished Mar 31 01:26:21 PM PDT 24
Peak memory 201016 kb
Host smart-a2e6eea7-baf6-4159-9eba-1a01611bfc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396497757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2396497757
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2088050644
Short name T222
Test name
Test status
Simulation time 148485857 ps
CPU time 1.05 seconds
Started Mar 31 01:26:19 PM PDT 24
Finished Mar 31 01:26:21 PM PDT 24
Peak memory 200836 kb
Host smart-e4cdcb48-6a7b-4160-9440-9572a8ea69e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088050644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2088050644
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3914930390
Short name T264
Test name
Test status
Simulation time 228000209 ps
CPU time 1.43 seconds
Started Mar 31 01:26:18 PM PDT 24
Finished Mar 31 01:26:20 PM PDT 24
Peak memory 201028 kb
Host smart-56bbfa3b-ebb7-493a-9749-103ad21bb18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914930390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3914930390
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3847773724
Short name T499
Test name
Test status
Simulation time 2634143052 ps
CPU time 10.87 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:32 PM PDT 24
Peak memory 201088 kb
Host smart-2f7f0619-b601-4e69-9447-ae29e96d53a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847773724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3847773724
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.765398964
Short name T375
Test name
Test status
Simulation time 256818791 ps
CPU time 1.74 seconds
Started Mar 31 01:26:16 PM PDT 24
Finished Mar 31 01:26:17 PM PDT 24
Peak memory 200888 kb
Host smart-e746ffbd-2dec-4577-8fcb-540c1e8f8bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765398964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.765398964
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1454173005
Short name T278
Test name
Test status
Simulation time 246650843 ps
CPU time 1.56 seconds
Started Mar 31 01:26:17 PM PDT 24
Finished Mar 31 01:26:18 PM PDT 24
Peak memory 200984 kb
Host smart-7dbcc5fb-c278-41d3-98cd-9302e94c8fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454173005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1454173005
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2028422957
Short name T530
Test name
Test status
Simulation time 62496680 ps
CPU time 0.75 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200688 kb
Host smart-7492e307-efc7-44d8-b6e3-e1345be76925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028422957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2028422957
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4119908069
Short name T539
Test name
Test status
Simulation time 1223253578 ps
CPU time 5.78 seconds
Started Mar 31 01:27:33 PM PDT 24
Finished Mar 31 01:27:39 PM PDT 24
Peak memory 222552 kb
Host smart-0016eed7-1ad4-4279-b652-7bd79c685f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119908069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4119908069
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3099566730
Short name T37
Test name
Test status
Simulation time 244234102 ps
CPU time 1.05 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 218080 kb
Host smart-4d6a4219-9ba4-4f39-b80c-fc899a10efce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099566730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3099566730
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3907600556
Short name T408
Test name
Test status
Simulation time 105939902 ps
CPU time 0.78 seconds
Started Mar 31 01:27:26 PM PDT 24
Finished Mar 31 01:27:27 PM PDT 24
Peak memory 200680 kb
Host smart-55b0dc1f-cf11-438f-9441-4bb1840d578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907600556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3907600556
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4176052726
Short name T90
Test name
Test status
Simulation time 995668090 ps
CPU time 4.78 seconds
Started Mar 31 01:27:30 PM PDT 24
Finished Mar 31 01:27:35 PM PDT 24
Peak memory 200976 kb
Host smart-f5cf0701-a1ed-43bb-8455-0b1c7c60eb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176052726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4176052726
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3816330892
Short name T317
Test name
Test status
Simulation time 110779289 ps
CPU time 1 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200844 kb
Host smart-ad40ed43-daa4-43f3-931d-3d5f595d3cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816330892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3816330892
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.249555987
Short name T529
Test name
Test status
Simulation time 222247000 ps
CPU time 1.44 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200988 kb
Host smart-0ec8ba3e-89e6-45fb-81d3-a62f6039d55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249555987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.249555987
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3549970663
Short name T450
Test name
Test status
Simulation time 3028761425 ps
CPU time 13.13 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 201136 kb
Host smart-f2c411d8-4a55-462d-ac7c-7d309e83c13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549970663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3549970663
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2049513982
Short name T146
Test name
Test status
Simulation time 372705646 ps
CPU time 2.06 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:31 PM PDT 24
Peak memory 209096 kb
Host smart-e0e72bf1-ce2c-438e-9f7b-64e10c1f4f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049513982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2049513982
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3011327519
Short name T457
Test name
Test status
Simulation time 74105272 ps
CPU time 0.76 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200812 kb
Host smart-99835e80-7c8a-4993-9098-40d1c900c251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011327519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3011327519
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.20596943
Short name T70
Test name
Test status
Simulation time 76481923 ps
CPU time 0.74 seconds
Started Mar 31 01:27:26 PM PDT 24
Finished Mar 31 01:27:27 PM PDT 24
Peak memory 200704 kb
Host smart-c82e9593-9cb9-4690-b403-2b3a1cc50328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20596943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.20596943
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.974590662
Short name T378
Test name
Test status
Simulation time 2364378335 ps
CPU time 8.72 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:37 PM PDT 24
Peak memory 222732 kb
Host smart-99d819c9-b0eb-41bb-ae91-a96e0d5b50b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974590662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.974590662
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2706927600
Short name T443
Test name
Test status
Simulation time 247700224 ps
CPU time 1.03 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 218048 kb
Host smart-086ff521-ee78-468e-ac0f-8b301478575b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706927600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2706927600
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.17250579
Short name T396
Test name
Test status
Simulation time 183198470 ps
CPU time 0.85 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:30 PM PDT 24
Peak memory 200716 kb
Host smart-0c97ddff-dff1-4891-84cd-6331c9c91f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17250579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.17250579
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3885078300
Short name T272
Test name
Test status
Simulation time 868283680 ps
CPU time 4.75 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:33 PM PDT 24
Peak memory 201024 kb
Host smart-aaa32561-e321-45fc-9304-33ab1ce4e38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885078300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3885078300
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3659907580
Short name T123
Test name
Test status
Simulation time 96831434 ps
CPU time 1.02 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200828 kb
Host smart-f62224f2-54e5-4d6d-889c-d1e0ecb7ed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659907580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3659907580
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3510522944
Short name T430
Test name
Test status
Simulation time 124318777 ps
CPU time 1.23 seconds
Started Mar 31 01:27:26 PM PDT 24
Finished Mar 31 01:27:27 PM PDT 24
Peak memory 201024 kb
Host smart-22cd0d46-48b5-45df-9ac0-9e14b7bc1bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510522944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3510522944
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2576225680
Short name T516
Test name
Test status
Simulation time 150247468 ps
CPU time 1.93 seconds
Started Mar 31 01:27:26 PM PDT 24
Finished Mar 31 01:27:28 PM PDT 24
Peak memory 200872 kb
Host smart-1181dee1-cbb8-4060-93ce-fa08275a716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576225680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2576225680
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2472812870
Short name T464
Test name
Test status
Simulation time 131331032 ps
CPU time 1.07 seconds
Started Mar 31 01:27:25 PM PDT 24
Finished Mar 31 01:27:27 PM PDT 24
Peak memory 200740 kb
Host smart-4a5508d4-9b52-4728-8c75-87be8db14493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472812870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2472812870
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3285435739
Short name T468
Test name
Test status
Simulation time 72280718 ps
CPU time 0.8 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:30 PM PDT 24
Peak memory 200688 kb
Host smart-77f1a832-bbe8-453c-b9d1-5c6d8198c59c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285435739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3285435739
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2110932334
Short name T215
Test name
Test status
Simulation time 1896252555 ps
CPU time 7.24 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:36 PM PDT 24
Peak memory 221736 kb
Host smart-f971c02d-4485-4413-9d8f-0e7e7036e016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110932334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2110932334
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.4010488386
Short name T309
Test name
Test status
Simulation time 244790391 ps
CPU time 1.01 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:30 PM PDT 24
Peak memory 218172 kb
Host smart-2489a90e-908c-427d-81f1-6e8eb3a87a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010488386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.4010488386
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3795394000
Short name T226
Test name
Test status
Simulation time 124872649 ps
CPU time 0.79 seconds
Started Mar 31 01:27:27 PM PDT 24
Finished Mar 31 01:27:28 PM PDT 24
Peak memory 200824 kb
Host smart-8e0098e8-2bb9-475a-97f1-337045f07428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795394000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3795394000
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.917550533
Short name T268
Test name
Test status
Simulation time 1151117767 ps
CPU time 5.2 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:33 PM PDT 24
Peak memory 201008 kb
Host smart-84892267-04de-4722-b89a-cae893a6c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917550533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.917550533
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3978432625
Short name T305
Test name
Test status
Simulation time 157117028 ps
CPU time 1.11 seconds
Started Mar 31 01:27:30 PM PDT 24
Finished Mar 31 01:27:31 PM PDT 24
Peak memory 200800 kb
Host smart-769765cd-1c38-4223-a9ed-54ddc14810a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978432625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3978432625
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1972584617
Short name T522
Test name
Test status
Simulation time 113280993 ps
CPU time 1.23 seconds
Started Mar 31 01:27:29 PM PDT 24
Finished Mar 31 01:27:30 PM PDT 24
Peak memory 201024 kb
Host smart-6e8a77ab-8ee5-4ea6-995d-5c7027310cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972584617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1972584617
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.458802422
Short name T212
Test name
Test status
Simulation time 13663173184 ps
CPU time 59.16 seconds
Started Mar 31 01:27:30 PM PDT 24
Finished Mar 31 01:28:29 PM PDT 24
Peak memory 210996 kb
Host smart-ef9ea1b6-7839-42af-9200-bc03e7345fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458802422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.458802422
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1822341092
Short name T201
Test name
Test status
Simulation time 303493600 ps
CPU time 1.95 seconds
Started Mar 31 01:27:30 PM PDT 24
Finished Mar 31 01:27:32 PM PDT 24
Peak memory 209084 kb
Host smart-c30359ba-bf46-40b2-a012-55f90e0c629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822341092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1822341092
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3962388170
Short name T174
Test name
Test status
Simulation time 137858590 ps
CPU time 1.09 seconds
Started Mar 31 01:27:28 PM PDT 24
Finished Mar 31 01:27:29 PM PDT 24
Peak memory 200800 kb
Host smart-f077a3b5-451f-470b-8da4-758d21edd34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962388170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3962388170
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2608804444
Short name T432
Test name
Test status
Simulation time 146120749 ps
CPU time 0.93 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:39 PM PDT 24
Peak memory 200644 kb
Host smart-7758a87b-8c87-4af4-a3e8-1954d210692e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608804444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2608804444
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2447631248
Short name T30
Test name
Test status
Simulation time 1894805098 ps
CPU time 7.17 seconds
Started Mar 31 01:27:33 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 218528 kb
Host smart-c61b2e2f-a3b3-470f-a5c7-3b9b6fa27fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447631248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2447631248
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3775609488
Short name T472
Test name
Test status
Simulation time 243413263 ps
CPU time 1.13 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:37 PM PDT 24
Peak memory 218240 kb
Host smart-3c80c1e8-117a-4c2a-9699-88122c633adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775609488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3775609488
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1217690033
Short name T511
Test name
Test status
Simulation time 232568057 ps
CPU time 1.01 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:38 PM PDT 24
Peak memory 200664 kb
Host smart-43bffb71-9574-4790-b524-f5464989a196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217690033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1217690033
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.758287817
Short name T200
Test name
Test status
Simulation time 801362460 ps
CPU time 4.01 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 200988 kb
Host smart-eb65fff6-daa2-4b15-a572-e3bb64e1f2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758287817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.758287817
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.171028725
Short name T74
Test name
Test status
Simulation time 161782397 ps
CPU time 1.17 seconds
Started Mar 31 01:27:40 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 200844 kb
Host smart-53cc4bdb-77db-42d9-a079-466aa647bada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171028725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.171028725
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2251093464
Short name T284
Test name
Test status
Simulation time 126035235 ps
CPU time 1.26 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:38 PM PDT 24
Peak memory 201024 kb
Host smart-07f27498-1dca-4df0-a17c-1ecb149d428f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251093464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2251093464
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3726207861
Short name T381
Test name
Test status
Simulation time 2647127252 ps
CPU time 13.56 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:52 PM PDT 24
Peak memory 201144 kb
Host smart-f8e74378-06cd-4a2c-9bfa-38f42630cadc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726207861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3726207861
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4265142601
Short name T461
Test name
Test status
Simulation time 478205495 ps
CPU time 2.43 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 200892 kb
Host smart-3df77ffd-1b4e-4f75-9d10-fcdfdc28b02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265142601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4265142601
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2229291751
Short name T163
Test name
Test status
Simulation time 80116142 ps
CPU time 0.78 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:37 PM PDT 24
Peak memory 200856 kb
Host smart-b83d6110-72b7-4f30-85f0-428b02017f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229291751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2229291751
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3269476621
Short name T181
Test name
Test status
Simulation time 72146476 ps
CPU time 0.8 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:37 PM PDT 24
Peak memory 200692 kb
Host smart-91163908-f9be-4a93-824f-81df5b78eaf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269476621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3269476621
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3374554767
Short name T51
Test name
Test status
Simulation time 1224991170 ps
CPU time 5.49 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 217992 kb
Host smart-bafd4627-6087-4142-93a1-3f0eb9241d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374554767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3374554767
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1283442561
Short name T434
Test name
Test status
Simulation time 244958435 ps
CPU time 1 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:37 PM PDT 24
Peak memory 218300 kb
Host smart-ea9d6761-794e-4cf0-94b9-9e852a34b34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283442561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1283442561
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1750699440
Short name T18
Test name
Test status
Simulation time 167982477 ps
CPU time 0.86 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:38 PM PDT 24
Peak memory 200604 kb
Host smart-89fe89a6-c511-4250-9dfc-4ccfdccfa5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750699440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1750699440
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1006117274
Short name T175
Test name
Test status
Simulation time 2224539736 ps
CPU time 7.17 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:46 PM PDT 24
Peak memory 201088 kb
Host smart-6da89825-7798-4877-8a0d-ea32384d6f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006117274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1006117274
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1547175534
Short name T2
Test name
Test status
Simulation time 176203528 ps
CPU time 1.18 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 200768 kb
Host smart-0affb684-2c5f-4707-bc3b-6468ddf8e1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547175534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1547175534
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3820010866
Short name T189
Test name
Test status
Simulation time 249817768 ps
CPU time 1.46 seconds
Started Mar 31 01:27:34 PM PDT 24
Finished Mar 31 01:27:36 PM PDT 24
Peak memory 201032 kb
Host smart-3d25c92c-54fa-445d-8e50-bdbaa1e42b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820010866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3820010866
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3785527102
Short name T497
Test name
Test status
Simulation time 1523215068 ps
CPU time 7.06 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:43 PM PDT 24
Peak memory 200956 kb
Host smart-e5398d96-b7dc-4047-a531-714131a7ee42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785527102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3785527102
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1062375752
Short name T330
Test name
Test status
Simulation time 272993342 ps
CPU time 1.88 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:38 PM PDT 24
Peak memory 200860 kb
Host smart-f3757cae-ea3c-4eb0-beb1-2a135192969b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062375752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1062375752
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2608527626
Short name T221
Test name
Test status
Simulation time 167481647 ps
CPU time 1.39 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:39 PM PDT 24
Peak memory 200948 kb
Host smart-d0100905-3e75-4a6c-90aa-02b96972cecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608527626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2608527626
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3129222337
Short name T447
Test name
Test status
Simulation time 69439345 ps
CPU time 0.79 seconds
Started Mar 31 01:27:35 PM PDT 24
Finished Mar 31 01:27:36 PM PDT 24
Peak memory 200680 kb
Host smart-bc8eff4e-0ad5-453c-b64c-5dd49be4f52d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129222337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3129222337
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2773312087
Short name T389
Test name
Test status
Simulation time 2359051820 ps
CPU time 8.11 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:46 PM PDT 24
Peak memory 222700 kb
Host smart-1845039a-e8c2-4f1f-b45d-221a9f4194bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773312087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2773312087
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2038671054
Short name T420
Test name
Test status
Simulation time 244149766 ps
CPU time 1.08 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 217676 kb
Host smart-44be803b-d7e7-497b-950d-0a48b47aafd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038671054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2038671054
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1309632724
Short name T16
Test name
Test status
Simulation time 186069628 ps
CPU time 0.84 seconds
Started Mar 31 01:27:34 PM PDT 24
Finished Mar 31 01:27:35 PM PDT 24
Peak memory 200680 kb
Host smart-ada89d3b-6ba2-47ad-91e3-2837427329f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309632724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1309632724
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3242489346
Short name T394
Test name
Test status
Simulation time 1949303117 ps
CPU time 7.73 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:45 PM PDT 24
Peak memory 201004 kb
Host smart-cf5bd799-9fa6-48aa-b6fc-7a55332a25ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242489346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3242489346
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2293468590
Short name T370
Test name
Test status
Simulation time 183408305 ps
CPU time 1.18 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:38 PM PDT 24
Peak memory 200740 kb
Host smart-a4f301a1-6fbc-45cd-97b6-c77346167f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293468590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2293468590
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.669273400
Short name T509
Test name
Test status
Simulation time 252856549 ps
CPU time 1.49 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:39 PM PDT 24
Peak memory 200984 kb
Host smart-9af73815-8935-4ab6-960f-9423db973ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669273400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.669273400
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1150254523
Short name T419
Test name
Test status
Simulation time 329024326 ps
CPU time 2.47 seconds
Started Mar 31 01:27:40 PM PDT 24
Finished Mar 31 01:27:42 PM PDT 24
Peak memory 200888 kb
Host smart-b8206e2f-d4d8-4275-be8b-39e4f141409a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150254523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1150254523
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2826672396
Short name T276
Test name
Test status
Simulation time 142148666 ps
CPU time 1.84 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 208676 kb
Host smart-6b82da9a-00f2-4785-8579-e59ccfec1f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826672396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2826672396
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.4024950239
Short name T166
Test name
Test status
Simulation time 184249705 ps
CPU time 1.23 seconds
Started Mar 31 01:27:35 PM PDT 24
Finished Mar 31 01:27:36 PM PDT 24
Peak memory 200832 kb
Host smart-c5fc670e-8956-4d56-b418-6e532ce9c60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024950239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4024950239
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.432227610
Short name T143
Test name
Test status
Simulation time 77239777 ps
CPU time 0.77 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:38 PM PDT 24
Peak memory 200820 kb
Host smart-9f5f3698-a783-4f48-9903-24629454eb18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432227610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.432227610
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2993464331
Short name T533
Test name
Test status
Simulation time 1881497321 ps
CPU time 6.6 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:45 PM PDT 24
Peak memory 218000 kb
Host smart-5651e31e-2cab-4336-bafa-51deb6535208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993464331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2993464331
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2515089366
Short name T285
Test name
Test status
Simulation time 244027616 ps
CPU time 1.1 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 218224 kb
Host smart-c3b3f775-d38c-4908-8643-55fbe2afca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515089366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2515089366
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1283856061
Short name T442
Test name
Test status
Simulation time 189070361 ps
CPU time 0.97 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:39 PM PDT 24
Peak memory 200728 kb
Host smart-7ead60ae-1c44-46a1-92fb-5d4630c7a97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283856061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1283856061
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1517397531
Short name T99
Test name
Test status
Simulation time 2012927109 ps
CPU time 7.6 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:45 PM PDT 24
Peak memory 201016 kb
Host smart-13397065-b812-4a3c-bce8-42e11b3d9ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517397531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1517397531
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1154994576
Short name T422
Test name
Test status
Simulation time 147525895 ps
CPU time 1.1 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:39 PM PDT 24
Peak memory 200840 kb
Host smart-1109b731-d295-45a2-a267-b0544b934bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154994576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1154994576
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.989588057
Short name T513
Test name
Test status
Simulation time 261862906 ps
CPU time 1.43 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 201016 kb
Host smart-e6b38b77-ed16-4ecc-816f-e3b2ecefc52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989588057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.989588057
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.164315213
Short name T506
Test name
Test status
Simulation time 4782403622 ps
CPU time 21.23 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:58 PM PDT 24
Peak memory 201140 kb
Host smart-38acabff-ce20-4958-a14b-40f7f4f06cec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164315213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.164315213
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3899561209
Short name T397
Test name
Test status
Simulation time 138730689 ps
CPU time 1.76 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:39 PM PDT 24
Peak memory 200888 kb
Host smart-92dd0af4-a3ae-49f9-8df8-22297c270ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899561209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3899561209
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.597068753
Short name T40
Test name
Test status
Simulation time 146940904 ps
CPU time 1.17 seconds
Started Mar 31 01:27:40 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 200836 kb
Host smart-87a2aa9b-f60c-47de-b720-64ac29072bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597068753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.597068753
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3134167752
Short name T141
Test name
Test status
Simulation time 62621770 ps
CPU time 0.75 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:38 PM PDT 24
Peak memory 200728 kb
Host smart-37bbce61-87c4-44ca-88c2-96ea2867e73c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134167752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3134167752
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3532296516
Short name T411
Test name
Test status
Simulation time 1232995906 ps
CPU time 5.97 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:44 PM PDT 24
Peak memory 222100 kb
Host smart-07317aba-2c64-496e-afb8-b10dd87ab25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532296516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3532296516
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2899249277
Short name T380
Test name
Test status
Simulation time 244076620 ps
CPU time 1.09 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 218080 kb
Host smart-fd3812b9-b9f4-4f79-a120-b5a12c5b3fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899249277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2899249277
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3780286739
Short name T168
Test name
Test status
Simulation time 214112635 ps
CPU time 0.91 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 200704 kb
Host smart-f10bf61d-3ff8-4335-8e5a-f6b4315eea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780286739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3780286739
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2602668179
Short name T500
Test name
Test status
Simulation time 1719172718 ps
CPU time 6.63 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:46 PM PDT 24
Peak memory 200980 kb
Host smart-ec62e864-c19a-40a4-abae-0c17dad7ff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602668179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2602668179
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.567496563
Short name T525
Test name
Test status
Simulation time 91494951 ps
CPU time 0.95 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 200824 kb
Host smart-e93f88df-aa9c-4eef-a363-a5451406a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567496563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.567496563
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.474922487
Short name T304
Test name
Test status
Simulation time 259237612 ps
CPU time 1.61 seconds
Started Mar 31 01:27:35 PM PDT 24
Finished Mar 31 01:27:37 PM PDT 24
Peak memory 201024 kb
Host smart-6769c182-ca18-49bb-9b7d-7b7fd1cde89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474922487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.474922487
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2408723192
Short name T11
Test name
Test status
Simulation time 12150374360 ps
CPU time 38.96 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:28:16 PM PDT 24
Peak memory 201164 kb
Host smart-783df0b0-368a-49d8-8ef8-05fc2d270c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408723192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2408723192
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.172875944
Short name T290
Test name
Test status
Simulation time 109906200 ps
CPU time 1.41 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 200924 kb
Host smart-3069b9cc-f3b8-43d7-a8eb-5abbc17483b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172875944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.172875944
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4234710123
Short name T144
Test name
Test status
Simulation time 136119470 ps
CPU time 1.05 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:38 PM PDT 24
Peak memory 200840 kb
Host smart-aedaee22-8b4d-460d-a3c0-e21c6ea425fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234710123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4234710123
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1025210279
Short name T184
Test name
Test status
Simulation time 58162820 ps
CPU time 0.74 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 200668 kb
Host smart-a04c6779-2a16-40ff-a217-cb7ebf76aec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025210279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1025210279
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1120045590
Short name T358
Test name
Test status
Simulation time 1233616994 ps
CPU time 5.5 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:43 PM PDT 24
Peak memory 217952 kb
Host smart-b08ddcc5-98a1-4989-884e-6b048ed0b8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120045590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1120045590
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3481207355
Short name T379
Test name
Test status
Simulation time 244492671 ps
CPU time 1.05 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 218136 kb
Host smart-516717b5-84e1-4fe1-aa25-ae3bd89a93cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481207355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3481207355
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1418571416
Short name T257
Test name
Test status
Simulation time 264120413 ps
CPU time 1 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:40 PM PDT 24
Peak memory 200712 kb
Host smart-3be74e5c-21b3-434f-9d2b-ca4d0efb3838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418571416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1418571416
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1899763709
Short name T510
Test name
Test status
Simulation time 1629998831 ps
CPU time 6.36 seconds
Started Mar 31 01:27:37 PM PDT 24
Finished Mar 31 01:27:43 PM PDT 24
Peak memory 200976 kb
Host smart-f86eef5b-c5fe-485a-ae6b-cd8a03df9922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899763709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1899763709
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3892734508
Short name T38
Test name
Test status
Simulation time 106531238 ps
CPU time 0.94 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:37 PM PDT 24
Peak memory 200840 kb
Host smart-2939e03e-72a4-4678-a8f2-443626ce7a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892734508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3892734508
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1218508971
Short name T4
Test name
Test status
Simulation time 201151795 ps
CPU time 1.33 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:38 PM PDT 24
Peak memory 201020 kb
Host smart-6140121e-0df0-4ffe-93e2-42da0e5aba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218508971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1218508971
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1662964208
Short name T233
Test name
Test status
Simulation time 3388183799 ps
CPU time 16.71 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:54 PM PDT 24
Peak memory 201156 kb
Host smart-db7ee1dd-f4df-4355-b518-52ae335a1231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662964208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1662964208
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3131651003
Short name T512
Test name
Test status
Simulation time 126316844 ps
CPU time 1.64 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 200884 kb
Host smart-527dee59-f5e4-4535-a093-3a29656d593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131651003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3131651003
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3764409514
Short name T297
Test name
Test status
Simulation time 83080990 ps
CPU time 0.81 seconds
Started Mar 31 01:27:36 PM PDT 24
Finished Mar 31 01:27:37 PM PDT 24
Peak memory 200816 kb
Host smart-0ca12ba3-b402-4dca-8dbf-759efc4ec747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764409514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3764409514
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2657124875
Short name T481
Test name
Test status
Simulation time 54151101 ps
CPU time 0.7 seconds
Started Mar 31 01:27:40 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 200676 kb
Host smart-103486ae-17a0-4973-88e4-cc42ef88e2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657124875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2657124875
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.924204734
Short name T31
Test name
Test status
Simulation time 1225539270 ps
CPU time 5.62 seconds
Started Mar 31 01:27:42 PM PDT 24
Finished Mar 31 01:27:48 PM PDT 24
Peak memory 222600 kb
Host smart-89d8994c-fbff-4115-a328-ed2a563bb30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924204734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.924204734
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2367910208
Short name T440
Test name
Test status
Simulation time 246319640 ps
CPU time 1.01 seconds
Started Mar 31 01:27:40 PM PDT 24
Finished Mar 31 01:27:41 PM PDT 24
Peak memory 218088 kb
Host smart-0fdb5fd1-9bec-4a85-89df-7df965126725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367910208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2367910208
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1546995069
Short name T209
Test name
Test status
Simulation time 216612450 ps
CPU time 0.87 seconds
Started Mar 31 01:27:44 PM PDT 24
Finished Mar 31 01:27:45 PM PDT 24
Peak memory 200660 kb
Host smart-ed8d9d93-c4ea-488d-9c75-9966460fa6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546995069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1546995069
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1472351033
Short name T116
Test name
Test status
Simulation time 1698754205 ps
CPU time 6.87 seconds
Started Mar 31 01:27:39 PM PDT 24
Finished Mar 31 01:27:46 PM PDT 24
Peak memory 200952 kb
Host smart-11925be3-3ef1-4618-8b92-a3c892a5c43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472351033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1472351033
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1055918475
Short name T466
Test name
Test status
Simulation time 102951350 ps
CPU time 0.99 seconds
Started Mar 31 01:27:41 PM PDT 24
Finished Mar 31 01:27:42 PM PDT 24
Peak memory 200836 kb
Host smart-3f6dd333-bb59-4c75-ba58-71ca9c5b5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055918475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1055918475
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2112867713
Short name T469
Test name
Test status
Simulation time 127581104 ps
CPU time 1.16 seconds
Started Mar 31 01:27:38 PM PDT 24
Finished Mar 31 01:27:39 PM PDT 24
Peak memory 201020 kb
Host smart-108f68e8-6219-4cc2-befe-34de0f399719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112867713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2112867713
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1094119369
Short name T202
Test name
Test status
Simulation time 3845021439 ps
CPU time 13.66 seconds
Started Mar 31 01:27:43 PM PDT 24
Finished Mar 31 01:27:57 PM PDT 24
Peak memory 201124 kb
Host smart-a6de4096-1db9-435c-a9ef-979d1ebf3875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094119369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1094119369
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.28306417
Short name T196
Test name
Test status
Simulation time 112041152 ps
CPU time 1.51 seconds
Started Mar 31 01:27:41 PM PDT 24
Finished Mar 31 01:27:43 PM PDT 24
Peak memory 200872 kb
Host smart-e042d18d-b0d8-4ad4-92bc-c700b9be4f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28306417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.28306417
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.281670835
Short name T282
Test name
Test status
Simulation time 174027480 ps
CPU time 1.16 seconds
Started Mar 31 01:27:50 PM PDT 24
Finished Mar 31 01:27:52 PM PDT 24
Peak memory 200848 kb
Host smart-90ac6426-564f-4300-8419-da722c3b001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281670835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.281670835
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2703530295
Short name T239
Test name
Test status
Simulation time 88480843 ps
CPU time 0.83 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:22 PM PDT 24
Peak memory 200704 kb
Host smart-a01a5724-d603-4f06-9e87-ff7721aea817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703530295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2703530295
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.30657865
Short name T504
Test name
Test status
Simulation time 2150460335 ps
CPU time 7.73 seconds
Started Mar 31 01:26:25 PM PDT 24
Finished Mar 31 01:26:32 PM PDT 24
Peak memory 218128 kb
Host smart-600edefc-7c93-4e89-a01f-ac71da5720f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30657865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.30657865
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3603132913
Short name T355
Test name
Test status
Simulation time 244525182 ps
CPU time 1.29 seconds
Started Mar 31 01:26:24 PM PDT 24
Finished Mar 31 01:26:25 PM PDT 24
Peak memory 218048 kb
Host smart-c93ae40e-7f41-4da2-b8f2-df5dbaeb24f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603132913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3603132913
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2020587650
Short name T19
Test name
Test status
Simulation time 111446845 ps
CPU time 0.76 seconds
Started Mar 31 01:26:17 PM PDT 24
Finished Mar 31 01:26:18 PM PDT 24
Peak memory 200632 kb
Host smart-5d82a5aa-bdf4-40a4-9bcc-4ee0a195f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020587650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2020587650
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2977188783
Short name T265
Test name
Test status
Simulation time 1509165340 ps
CPU time 5.66 seconds
Started Mar 31 01:26:16 PM PDT 24
Finished Mar 31 01:26:21 PM PDT 24
Peak memory 200992 kb
Host smart-125dd158-37cb-42d6-9741-a5ffccfab21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977188783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2977188783
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1602159596
Short name T128
Test name
Test status
Simulation time 116649128 ps
CPU time 1.01 seconds
Started Mar 31 01:26:23 PM PDT 24
Finished Mar 31 01:26:24 PM PDT 24
Peak memory 200812 kb
Host smart-9d4e47e3-bb30-4c0a-a16d-50f6a3b1cee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602159596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1602159596
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.129855638
Short name T335
Test name
Test status
Simulation time 117151675 ps
CPU time 1.25 seconds
Started Mar 31 01:26:19 PM PDT 24
Finished Mar 31 01:26:20 PM PDT 24
Peak memory 201004 kb
Host smart-29ea0455-1884-4895-8ec5-7a62112d2e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129855638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.129855638
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1668268324
Short name T536
Test name
Test status
Simulation time 12058956817 ps
CPU time 40.61 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:27:02 PM PDT 24
Peak memory 210060 kb
Host smart-92ef79b6-a6a7-430a-ac8a-80e2f6193ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668268324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1668268324
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.358026794
Short name T341
Test name
Test status
Simulation time 548211587 ps
CPU time 2.75 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:24 PM PDT 24
Peak memory 200884 kb
Host smart-641eccee-43dd-45ec-a5d9-91640cff6a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358026794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.358026794
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1692929014
Short name T316
Test name
Test status
Simulation time 118862372 ps
CPU time 1.03 seconds
Started Mar 31 01:26:18 PM PDT 24
Finished Mar 31 01:26:19 PM PDT 24
Peak memory 200788 kb
Host smart-57030595-4ca7-47af-8495-59d5e49e273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692929014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1692929014
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1301142696
Short name T224
Test name
Test status
Simulation time 64411011 ps
CPU time 0.73 seconds
Started Mar 31 01:26:25 PM PDT 24
Finished Mar 31 01:26:26 PM PDT 24
Peak memory 200692 kb
Host smart-a114a02a-f9a1-4d62-9a41-10d8287df4ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301142696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1301142696
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.37270263
Short name T320
Test name
Test status
Simulation time 1898624700 ps
CPU time 7.04 seconds
Started Mar 31 01:26:20 PM PDT 24
Finished Mar 31 01:26:27 PM PDT 24
Peak memory 222548 kb
Host smart-3f100358-ea03-44b1-b51e-697ce0b6bc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37270263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.37270263
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3937058269
Short name T148
Test name
Test status
Simulation time 243871660 ps
CPU time 1.13 seconds
Started Mar 31 01:26:24 PM PDT 24
Finished Mar 31 01:26:25 PM PDT 24
Peak memory 218188 kb
Host smart-b79b5214-35fa-4d6c-ac3f-e146dcafbe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937058269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3937058269
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3819409808
Short name T349
Test name
Test status
Simulation time 234031946 ps
CPU time 0.96 seconds
Started Mar 31 01:26:22 PM PDT 24
Finished Mar 31 01:26:23 PM PDT 24
Peak memory 200648 kb
Host smart-28ea1561-4b4f-47e4-bdf5-b9d9a04eb038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819409808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3819409808
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1582709645
Short name T363
Test name
Test status
Simulation time 1248039962 ps
CPU time 5 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:27 PM PDT 24
Peak memory 201132 kb
Host smart-52cbc4c9-2826-46f7-a03a-5307eee2f441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582709645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1582709645
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2496793428
Short name T8
Test name
Test status
Simulation time 159907375 ps
CPU time 1.14 seconds
Started Mar 31 01:26:25 PM PDT 24
Finished Mar 31 01:26:26 PM PDT 24
Peak memory 200836 kb
Host smart-6ab6f90a-1022-4c20-8a4e-8339dfa0fd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496793428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2496793428
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1724360620
Short name T417
Test name
Test status
Simulation time 250528205 ps
CPU time 1.59 seconds
Started Mar 31 01:26:25 PM PDT 24
Finished Mar 31 01:26:27 PM PDT 24
Peak memory 201068 kb
Host smart-cc45fd8c-c9a7-4de7-9ef9-d87e2db09aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724360620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1724360620
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.308810386
Short name T289
Test name
Test status
Simulation time 4045441605 ps
CPU time 17.46 seconds
Started Mar 31 01:26:22 PM PDT 24
Finished Mar 31 01:26:40 PM PDT 24
Peak memory 201144 kb
Host smart-64664e8c-2568-44ea-9087-00563846f6d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308810386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.308810386
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3758474856
Short name T426
Test name
Test status
Simulation time 124831034 ps
CPU time 1.6 seconds
Started Mar 31 01:26:25 PM PDT 24
Finished Mar 31 01:26:26 PM PDT 24
Peak memory 200896 kb
Host smart-e40960e5-10e3-4033-a8fc-5a6c71e3bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758474856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3758474856
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4009357332
Short name T474
Test name
Test status
Simulation time 121736451 ps
CPU time 1.11 seconds
Started Mar 31 01:26:21 PM PDT 24
Finished Mar 31 01:26:22 PM PDT 24
Peak memory 200788 kb
Host smart-c8e8e155-dad1-45c4-986f-805b36dc86e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009357332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4009357332
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2469647086
Short name T365
Test name
Test status
Simulation time 89485192 ps
CPU time 0.81 seconds
Started Mar 31 01:26:23 PM PDT 24
Finished Mar 31 01:26:24 PM PDT 24
Peak memory 200668 kb
Host smart-99c3e90d-f117-4c98-a536-54f2f9a4d310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469647086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2469647086
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2113314640
Short name T425
Test name
Test status
Simulation time 1226753712 ps
CPU time 5.77 seconds
Started Mar 31 01:26:22 PM PDT 24
Finished Mar 31 01:26:28 PM PDT 24
Peak memory 217988 kb
Host smart-08c31ff9-8fbf-44e6-a35b-586a6572326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113314640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2113314640
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3067517205
Short name T242
Test name
Test status
Simulation time 245991273 ps
CPU time 1.07 seconds
Started Mar 31 01:26:23 PM PDT 24
Finished Mar 31 01:26:24 PM PDT 24
Peak memory 218340 kb
Host smart-eb72f10d-1363-46af-bded-8a66096089d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067517205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3067517205
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3609624437
Short name T437
Test name
Test status
Simulation time 137901868 ps
CPU time 0.83 seconds
Started Mar 31 01:26:27 PM PDT 24
Finished Mar 31 01:26:28 PM PDT 24
Peak memory 200688 kb
Host smart-3a5e3789-1d0d-4722-bcc2-526001d60755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609624437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3609624437
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.4188476407
Short name T161
Test name
Test status
Simulation time 1688627436 ps
CPU time 6.06 seconds
Started Mar 31 01:26:22 PM PDT 24
Finished Mar 31 01:26:28 PM PDT 24
Peak memory 200920 kb
Host smart-420fa0e4-8b95-43e8-beed-1b51b2a79f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188476407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.4188476407
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1841295809
Short name T194
Test name
Test status
Simulation time 152443518 ps
CPU time 1.13 seconds
Started Mar 31 01:26:26 PM PDT 24
Finished Mar 31 01:26:27 PM PDT 24
Peak memory 200836 kb
Host smart-ad9a2217-8d9b-4059-afb4-47af9a6ca095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841295809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1841295809
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1467384313
Short name T187
Test name
Test status
Simulation time 116610043 ps
CPU time 1.23 seconds
Started Mar 31 01:26:24 PM PDT 24
Finished Mar 31 01:26:25 PM PDT 24
Peak memory 200936 kb
Host smart-e15e46e8-a135-436c-80b5-4a2cfffbfcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467384313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1467384313
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3332233708
Short name T353
Test name
Test status
Simulation time 5344111917 ps
CPU time 23.16 seconds
Started Mar 31 01:26:23 PM PDT 24
Finished Mar 31 01:26:46 PM PDT 24
Peak memory 201148 kb
Host smart-247e6dfc-515e-47f5-965e-74f2ea5d217b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332233708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3332233708
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3570076856
Short name T169
Test name
Test status
Simulation time 377573634 ps
CPU time 2.32 seconds
Started Mar 31 01:26:20 PM PDT 24
Finished Mar 31 01:26:23 PM PDT 24
Peak memory 200852 kb
Host smart-413786a7-820d-4b7a-a69d-9d2ee7e1cef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570076856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3570076856
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2749905362
Short name T42
Test name
Test status
Simulation time 125613230 ps
CPU time 0.95 seconds
Started Mar 31 01:26:22 PM PDT 24
Finished Mar 31 01:26:23 PM PDT 24
Peak memory 200844 kb
Host smart-15b85731-371c-4f10-a38d-18a27acfa10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749905362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2749905362
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3735748759
Short name T319
Test name
Test status
Simulation time 54813567 ps
CPU time 0.8 seconds
Started Mar 31 01:26:28 PM PDT 24
Finished Mar 31 01:26:28 PM PDT 24
Peak memory 200724 kb
Host smart-ac615240-5b0a-4c04-80b1-2699aec8cd27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735748759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3735748759
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4114570975
Short name T436
Test name
Test status
Simulation time 1896830152 ps
CPU time 7.4 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:41 PM PDT 24
Peak memory 217556 kb
Host smart-3c93887d-705e-466c-8b4e-c9a37c682538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114570975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4114570975
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1213286334
Short name T231
Test name
Test status
Simulation time 244952074 ps
CPU time 1.01 seconds
Started Mar 31 01:26:26 PM PDT 24
Finished Mar 31 01:26:27 PM PDT 24
Peak memory 218140 kb
Host smart-da32a951-b687-4e5d-8914-5f5374f32e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213286334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1213286334
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1449183678
Short name T332
Test name
Test status
Simulation time 120231190 ps
CPU time 0.81 seconds
Started Mar 31 01:26:29 PM PDT 24
Finished Mar 31 01:26:30 PM PDT 24
Peak memory 200704 kb
Host smart-2fdc90e4-e7f4-4844-b4e2-b08caa3b6647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449183678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1449183678
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.162639476
Short name T225
Test name
Test status
Simulation time 1803331694 ps
CPU time 6.64 seconds
Started Mar 31 01:26:28 PM PDT 24
Finished Mar 31 01:26:34 PM PDT 24
Peak memory 200960 kb
Host smart-235f8fed-c126-4866-aa5a-181f3c973054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162639476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.162639476
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3948114744
Short name T384
Test name
Test status
Simulation time 142119558 ps
CPU time 1.1 seconds
Started Mar 31 01:26:28 PM PDT 24
Finished Mar 31 01:26:29 PM PDT 24
Peak memory 200772 kb
Host smart-d458d9b3-fe0d-490c-b98b-6daa263c86d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948114744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3948114744
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.381887518
Short name T195
Test name
Test status
Simulation time 117748820 ps
CPU time 1.23 seconds
Started Mar 31 01:26:22 PM PDT 24
Finished Mar 31 01:26:23 PM PDT 24
Peak memory 200968 kb
Host smart-a9cfdefd-f843-46f1-a796-7502de9526ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381887518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.381887518
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.834017554
Short name T505
Test name
Test status
Simulation time 1099989213 ps
CPU time 5.3 seconds
Started Mar 31 01:26:30 PM PDT 24
Finished Mar 31 01:26:35 PM PDT 24
Peak memory 201040 kb
Host smart-337952ed-3d11-4ced-9c51-ed9078aab8b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834017554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.834017554
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1981068483
Short name T56
Test name
Test status
Simulation time 510163089 ps
CPU time 2.64 seconds
Started Mar 31 01:26:32 PM PDT 24
Finished Mar 31 01:26:35 PM PDT 24
Peak memory 200816 kb
Host smart-4d0a61c7-d2cf-40eb-9514-63e80ceced79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981068483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1981068483
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3702429615
Short name T269
Test name
Test status
Simulation time 131532977 ps
CPU time 1 seconds
Started Mar 31 01:26:31 PM PDT 24
Finished Mar 31 01:26:33 PM PDT 24
Peak memory 200792 kb
Host smart-fe286d65-c460-456f-b7f0-deb7e218e184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702429615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3702429615
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3199013574
Short name T453
Test name
Test status
Simulation time 56953878 ps
CPU time 0.73 seconds
Started Mar 31 01:26:28 PM PDT 24
Finished Mar 31 01:26:29 PM PDT 24
Peak memory 200728 kb
Host smart-42b269c4-30b5-4e25-a105-4f8d3441b7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199013574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3199013574
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.936624277
Short name T327
Test name
Test status
Simulation time 1232157178 ps
CPU time 5.26 seconds
Started Mar 31 01:26:27 PM PDT 24
Finished Mar 31 01:26:33 PM PDT 24
Peak memory 217916 kb
Host smart-c1f47a8f-450d-42f5-b243-9d4224e5501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936624277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.936624277
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.4148660266
Short name T312
Test name
Test status
Simulation time 243950562 ps
CPU time 1.09 seconds
Started Mar 31 01:26:28 PM PDT 24
Finished Mar 31 01:26:29 PM PDT 24
Peak memory 218124 kb
Host smart-60a9b896-dd79-4580-9259-b8f176c94446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148660266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.4148660266
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.238997842
Short name T17
Test name
Test status
Simulation time 214572612 ps
CPU time 0.89 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:35 PM PDT 24
Peak memory 200712 kb
Host smart-ee844bfd-cdc8-41d6-95ed-220984624de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238997842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.238997842
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.629641770
Short name T308
Test name
Test status
Simulation time 2100595515 ps
CPU time 8.06 seconds
Started Mar 31 01:26:31 PM PDT 24
Finished Mar 31 01:26:40 PM PDT 24
Peak memory 201024 kb
Host smart-e96161a7-2ed1-47c6-8f36-ed7c522a09d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629641770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.629641770
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1159596392
Short name T77
Test name
Test status
Simulation time 167113393 ps
CPU time 1.15 seconds
Started Mar 31 01:26:29 PM PDT 24
Finished Mar 31 01:26:31 PM PDT 24
Peak memory 200832 kb
Host smart-13ace548-cee4-4b43-beb1-05a2e5755be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159596392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1159596392
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2259632866
Short name T400
Test name
Test status
Simulation time 118275219 ps
CPU time 1.2 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:26:36 PM PDT 24
Peak memory 201024 kb
Host smart-ee2aa277-3258-44be-926b-9d9330294c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259632866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2259632866
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1478203317
Short name T300
Test name
Test status
Simulation time 8245976716 ps
CPU time 28.64 seconds
Started Mar 31 01:26:34 PM PDT 24
Finished Mar 31 01:27:03 PM PDT 24
Peak memory 201132 kb
Host smart-9c9cb057-cf7b-4076-803a-7c210db3d3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478203317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1478203317
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3054925752
Short name T402
Test name
Test status
Simulation time 376154441 ps
CPU time 2.42 seconds
Started Mar 31 01:26:28 PM PDT 24
Finished Mar 31 01:26:31 PM PDT 24
Peak memory 200864 kb
Host smart-42d72548-fafe-4d64-8d8f-09a6301b55dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054925752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3054925752
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2845000627
Short name T78
Test name
Test status
Simulation time 105646865 ps
CPU time 0.95 seconds
Started Mar 31 01:26:28 PM PDT 24
Finished Mar 31 01:26:29 PM PDT 24
Peak memory 200828 kb
Host smart-e4402dc8-6723-443b-84d5-523b9fe5a731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845000627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2845000627
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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