Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8562

1

T4

109

T10

67

T14

15

auto[1]

11292

1

T4

116

T9

4

T10

68

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5997	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6797	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3104	1			T4	37		T9	1		T10	18
reset_info_cp[4]	4012	1			T4	50		T9	1		T10	36
reset_info_cp[8]	117	1			T4	1		T14	1		T21	1
reset_info_cp[16]	99	1			T4	1		T14	1		T22	1
reset_info_cp[32]	118	1			T22	2		T24	2		T54	1
reset_info_cp[64]	115	1			T4	1		T14	1		T22	3
reset_info_cp[128]	115	1			T10	1		T14	1		T24	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3312	1			T4	32		T10	18		T22	19
reset_info_cp[1]	auto[1]	2865	1			T4	41		T9	1		T10	23
reset_info_cp[2]	auto[0]	995	1			T4	12		T10	10		T24	27
reset_info_cp[2]	auto[1]	2109	1			T4	25		T9	1		T10	8
reset_info_cp[4]	auto[0]	1529	1			T4	23		T10	17		T24	32
reset_info_cp[4]	auto[1]	2483	1			T4	27		T9	1		T10	19
reset_info_cp[8]	auto[0]	46	1			T4	1		T14	1		T21	1
reset_info_cp[8]	auto[1]	71	1			T24	1		T55	1		T56	1
reset_info_cp[16]	auto[0]	42	1			T14	1		T51	1		T54	1
reset_info_cp[16]	auto[1]	57	1			T4	1		T22	1		T36	2
reset_info_cp[32]	auto[0]	45	1			T54	1		T55	1		T96	1
reset_info_cp[32]	auto[1]	73	1			T22	2		T24	2		T55	2
reset_info_cp[64]	auto[0]	46	1			T4	1		T14	1		T24	1
reset_info_cp[64]	auto[1]	69	1			T22	3		T24	1		T36	1
reset_info_cp[128]	auto[0]	44	1			T14	1		T24	1		T56	1
reset_info_cp[128]	auto[1]	71	1			T10	1		T26	1		T36	1