Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T533 /workspace/coverage/default/12.rstmgr_alert_test.2644817040 Apr 02 12:36:56 PM PDT 24 Apr 02 12:36:58 PM PDT 24 79368070 ps
T534 /workspace/coverage/default/5.rstmgr_por_stretcher.2136377574 Apr 02 12:36:45 PM PDT 24 Apr 02 12:36:48 PM PDT 24 106357797 ps
T535 /workspace/coverage/default/43.rstmgr_smoke.4100617650 Apr 02 12:37:44 PM PDT 24 Apr 02 12:37:46 PM PDT 24 181867675 ps
T536 /workspace/coverage/default/28.rstmgr_por_stretcher.7533129 Apr 02 12:37:26 PM PDT 24 Apr 02 12:37:27 PM PDT 24 183191031 ps
T537 /workspace/coverage/default/33.rstmgr_sw_rst.504562207 Apr 02 12:37:29 PM PDT 24 Apr 02 12:37:32 PM PDT 24 437870853 ps
T62 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3063238690 Apr 02 12:24:54 PM PDT 24 Apr 02 12:24:55 PM PDT 24 78907458 ps
T65 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.115726979 Apr 02 12:25:09 PM PDT 24 Apr 02 12:25:12 PM PDT 24 421570806 ps
T63 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3584151368 Apr 02 12:25:15 PM PDT 24 Apr 02 12:25:17 PM PDT 24 192112981 ps
T64 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2160999844 Apr 02 12:25:02 PM PDT 24 Apr 02 12:25:05 PM PDT 24 278398824 ps
T66 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1623107831 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:08 PM PDT 24 134615358 ps
T67 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2549906494 Apr 02 12:25:01 PM PDT 24 Apr 02 12:25:03 PM PDT 24 103157268 ps
T538 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4226416996 Apr 02 12:24:51 PM PDT 24 Apr 02 12:24:52 PM PDT 24 95030267 ps
T68 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2452349959 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:09 PM PDT 24 772202203 ps
T69 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2694815247 Apr 02 12:25:00 PM PDT 24 Apr 02 12:25:03 PM PDT 24 907534061 ps
T539 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.219501233 Apr 02 12:24:59 PM PDT 24 Apr 02 12:25:04 PM PDT 24 803333179 ps
T84 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.583584687 Apr 02 12:25:09 PM PDT 24 Apr 02 12:25:10 PM PDT 24 155817840 ps
T104 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3254106188 Apr 02 12:25:03 PM PDT 24 Apr 02 12:25:04 PM PDT 24 58164263 ps
T85 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.984711772 Apr 02 12:25:05 PM PDT 24 Apr 02 12:25:08 PM PDT 24 189363494 ps
T90 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3186856794 Apr 02 12:24:59 PM PDT 24 Apr 02 12:25:00 PM PDT 24 185201679 ps
T105 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.690031636 Apr 02 12:25:01 PM PDT 24 Apr 02 12:25:03 PM PDT 24 141529556 ps
T106 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3556990132 Apr 02 12:24:59 PM PDT 24 Apr 02 12:25:00 PM PDT 24 124278430 ps
T93 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3292647197 Apr 02 12:25:03 PM PDT 24 Apr 02 12:25:05 PM PDT 24 205247714 ps
T86 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2935605524 Apr 02 12:25:05 PM PDT 24 Apr 02 12:25:08 PM PDT 24 195500080 ps
T88 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2328791642 Apr 02 12:25:10 PM PDT 24 Apr 02 12:25:15 PM PDT 24 623111340 ps
T87 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2364207375 Apr 02 12:24:48 PM PDT 24 Apr 02 12:24:50 PM PDT 24 312441691 ps
T95 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3571974562 Apr 02 12:25:03 PM PDT 24 Apr 02 12:25:05 PM PDT 24 195159571 ps
T540 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3800152881 Apr 02 12:24:56 PM PDT 24 Apr 02 12:24:59 PM PDT 24 157406096 ps
T83 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.462553445 Apr 02 12:25:44 PM PDT 24 Apr 02 12:25:47 PM PDT 24 912462993 ps
T541 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.96554307 Apr 02 12:24:54 PM PDT 24 Apr 02 12:24:56 PM PDT 24 175230753 ps
T107 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.982549910 Apr 02 12:24:49 PM PDT 24 Apr 02 12:24:50 PM PDT 24 55654559 ps
T108 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3116025809 Apr 02 12:25:00 PM PDT 24 Apr 02 12:25:01 PM PDT 24 60314412 ps
T109 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1908362972 Apr 02 12:26:05 PM PDT 24 Apr 02 12:26:06 PM PDT 24 139863437 ps
T542 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1626466480 Apr 02 12:25:15 PM PDT 24 Apr 02 12:25:17 PM PDT 24 278776431 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.93370191 Apr 02 12:24:41 PM PDT 24 Apr 02 12:24:42 PM PDT 24 129244119 ps
T94 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2740615458 Apr 02 12:24:57 PM PDT 24 Apr 02 12:25:00 PM PDT 24 834702438 ps
T110 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1808380957 Apr 02 12:25:00 PM PDT 24 Apr 02 12:25:01 PM PDT 24 76787496 ps
T544 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.970224691 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:07 PM PDT 24 195900157 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2777505638 Apr 02 12:25:04 PM PDT 24 Apr 02 12:25:07 PM PDT 24 448737064 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3458699125 Apr 02 12:25:00 PM PDT 24 Apr 02 12:25:01 PM PDT 24 83248540 ps
T111 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.25758943 Apr 02 12:24:57 PM PDT 24 Apr 02 12:24:59 PM PDT 24 188066682 ps
T112 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2463755816 Apr 02 12:25:01 PM PDT 24 Apr 02 12:25:03 PM PDT 24 151415053 ps
T547 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1969614629 Apr 02 12:24:57 PM PDT 24 Apr 02 12:24:58 PM PDT 24 423074367 ps
T548 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.808303839 Apr 02 12:25:12 PM PDT 24 Apr 02 12:25:19 PM PDT 24 245542454 ps
T89 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.213161820 Apr 02 12:25:05 PM PDT 24 Apr 02 12:25:08 PM PDT 24 942494936 ps
T549 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.839502598 Apr 02 12:25:00 PM PDT 24 Apr 02 12:25:03 PM PDT 24 330736047 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1975551934 Apr 02 12:24:46 PM PDT 24 Apr 02 12:24:48 PM PDT 24 217359719 ps
T551 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.223229415 Apr 02 12:24:46 PM PDT 24 Apr 02 12:24:50 PM PDT 24 60538368 ps
T552 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2463423878 Apr 02 12:25:09 PM PDT 24 Apr 02 12:25:11 PM PDT 24 173154796 ps
T553 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1850420594 Apr 02 12:25:09 PM PDT 24 Apr 02 12:25:13 PM PDT 24 352568978 ps
T554 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.536651732 Apr 02 12:25:03 PM PDT 24 Apr 02 12:25:05 PM PDT 24 130664559 ps
T555 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2983616169 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:08 PM PDT 24 66872526 ps
T556 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3391404422 Apr 02 12:24:51 PM PDT 24 Apr 02 12:24:52 PM PDT 24 96481874 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1509099233 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:09 PM PDT 24 358453312 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2763331858 Apr 02 12:25:13 PM PDT 24 Apr 02 12:25:14 PM PDT 24 140732118 ps
T91 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1395478376 Apr 02 12:25:09 PM PDT 24 Apr 02 12:25:11 PM PDT 24 467501516 ps
T559 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3760099679 Apr 02 12:25:07 PM PDT 24 Apr 02 12:25:10 PM PDT 24 307483972 ps
T560 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1488715580 Apr 02 12:24:35 PM PDT 24 Apr 02 12:24:38 PM PDT 24 520003175 ps
T561 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1568694657 Apr 02 12:25:08 PM PDT 24 Apr 02 12:25:10 PM PDT 24 145578418 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3575794968 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:07 PM PDT 24 75856890 ps
T563 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3769731913 Apr 02 12:24:49 PM PDT 24 Apr 02 12:24:50 PM PDT 24 54067157 ps
T564 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2466397203 Apr 02 12:24:45 PM PDT 24 Apr 02 12:24:51 PM PDT 24 268994338 ps
T565 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2406042970 Apr 02 12:24:56 PM PDT 24 Apr 02 12:25:02 PM PDT 24 485242343 ps
T566 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4214579674 Apr 02 12:25:05 PM PDT 24 Apr 02 12:25:07 PM PDT 24 138873304 ps
T567 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1525419843 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:07 PM PDT 24 75605085 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2616035097 Apr 02 12:25:08 PM PDT 24 Apr 02 12:25:09 PM PDT 24 136524410 ps
T569 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3264563833 Apr 02 12:25:02 PM PDT 24 Apr 02 12:25:03 PM PDT 24 85398692 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1965959700 Apr 02 12:24:58 PM PDT 24 Apr 02 12:24:59 PM PDT 24 137163303 ps
T571 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3183966316 Apr 02 12:25:02 PM PDT 24 Apr 02 12:25:03 PM PDT 24 172832201 ps
T572 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.54169581 Apr 02 12:24:56 PM PDT 24 Apr 02 12:24:57 PM PDT 24 81164334 ps
T92 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4074394503 Apr 02 12:24:52 PM PDT 24 Apr 02 12:24:55 PM PDT 24 935778619 ps
T573 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2765319112 Apr 02 12:26:03 PM PDT 24 Apr 02 12:26:05 PM PDT 24 438626657 ps
T574 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3059131698 Apr 02 12:25:11 PM PDT 24 Apr 02 12:25:12 PM PDT 24 152415342 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3705509614 Apr 02 12:24:52 PM PDT 24 Apr 02 12:24:54 PM PDT 24 253689670 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1383338991 Apr 02 12:24:51 PM PDT 24 Apr 02 12:24:52 PM PDT 24 228238897 ps
T577 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4274876358 Apr 02 12:24:54 PM PDT 24 Apr 02 12:24:57 PM PDT 24 521498901 ps
T578 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.198317163 Apr 02 12:24:59 PM PDT 24 Apr 02 12:25:00 PM PDT 24 430915862 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3194644377 Apr 02 12:24:57 PM PDT 24 Apr 02 12:25:01 PM PDT 24 927080570 ps
T580 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.925505811 Apr 02 12:25:02 PM PDT 24 Apr 02 12:25:03 PM PDT 24 56523315 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3297430434 Apr 02 12:25:01 PM PDT 24 Apr 02 12:25:03 PM PDT 24 433290258 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3656297968 Apr 02 12:24:46 PM PDT 24 Apr 02 12:24:47 PM PDT 24 99739466 ps
T583 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4288223848 Apr 02 12:24:47 PM PDT 24 Apr 02 12:24:50 PM PDT 24 449251584 ps
T584 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3925783288 Apr 02 12:24:56 PM PDT 24 Apr 02 12:24:58 PM PDT 24 187245023 ps
T585 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.289829920 Apr 02 12:25:11 PM PDT 24 Apr 02 12:25:13 PM PDT 24 164749560 ps
T586 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.816615073 Apr 02 12:24:59 PM PDT 24 Apr 02 12:25:00 PM PDT 24 206786582 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.191311051 Apr 02 12:24:47 PM PDT 24 Apr 02 12:24:52 PM PDT 24 1172959278 ps
T588 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4039456939 Apr 02 12:25:07 PM PDT 24 Apr 02 12:25:09 PM PDT 24 80195891 ps
T589 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1138523635 Apr 02 12:25:12 PM PDT 24 Apr 02 12:25:13 PM PDT 24 81730084 ps
T590 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2853977691 Apr 02 12:25:07 PM PDT 24 Apr 02 12:25:08 PM PDT 24 69790770 ps
T591 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3471901775 Apr 02 12:25:03 PM PDT 24 Apr 02 12:25:04 PM PDT 24 129521922 ps
T592 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3320407358 Apr 02 12:25:07 PM PDT 24 Apr 02 12:25:08 PM PDT 24 107615571 ps
T593 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2367922929 Apr 02 12:25:12 PM PDT 24 Apr 02 12:25:14 PM PDT 24 485376296 ps
T594 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.551288638 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:08 PM PDT 24 429615433 ps
T595 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3239440741 Apr 02 12:25:05 PM PDT 24 Apr 02 12:25:06 PM PDT 24 110245060 ps
T596 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2291323048 Apr 02 12:25:43 PM PDT 24 Apr 02 12:25:44 PM PDT 24 58606748 ps
T597 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2422432027 Apr 02 12:25:07 PM PDT 24 Apr 02 12:25:10 PM PDT 24 449447580 ps
T598 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.919326874 Apr 02 12:24:54 PM PDT 24 Apr 02 12:24:55 PM PDT 24 71941539 ps
T599 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.636963772 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:07 PM PDT 24 194496040 ps
T600 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1591853382 Apr 02 12:25:02 PM PDT 24 Apr 02 12:25:03 PM PDT 24 205528152 ps
T601 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1945763408 Apr 02 12:24:59 PM PDT 24 Apr 02 12:25:01 PM PDT 24 423752058 ps
T602 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1933111145 Apr 02 12:24:51 PM PDT 24 Apr 02 12:24:53 PM PDT 24 467578491 ps
T603 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1808012716 Apr 02 12:24:59 PM PDT 24 Apr 02 12:25:00 PM PDT 24 112997073 ps
T604 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3417764941 Apr 02 12:24:57 PM PDT 24 Apr 02 12:24:59 PM PDT 24 194791831 ps
T605 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.620765459 Apr 02 12:25:02 PM PDT 24 Apr 02 12:25:04 PM PDT 24 108938938 ps
T123 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1994060223 Apr 02 12:25:02 PM PDT 24 Apr 02 12:25:04 PM PDT 24 420903004 ps
T606 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.496435705 Apr 02 12:25:07 PM PDT 24 Apr 02 12:25:10 PM PDT 24 193733337 ps
T607 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3604036008 Apr 02 12:24:59 PM PDT 24 Apr 02 12:25:00 PM PDT 24 75818597 ps
T608 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4161621960 Apr 02 12:25:03 PM PDT 24 Apr 02 12:25:04 PM PDT 24 126662238 ps
T124 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1730769118 Apr 02 12:25:04 PM PDT 24 Apr 02 12:25:07 PM PDT 24 932086342 ps
T609 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2788087941 Apr 02 12:25:06 PM PDT 24 Apr 02 12:25:09 PM PDT 24 428329402 ps
T610 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1189079750 Apr 02 12:24:55 PM PDT 24 Apr 02 12:24:57 PM PDT 24 211330236 ps
T611 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3512493622 Apr 02 12:24:52 PM PDT 24 Apr 02 12:24:53 PM PDT 24 64701439 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.487846979 Apr 02 12:25:10 PM PDT 24 Apr 02 12:25:14 PM PDT 24 877539932 ps
T613 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1663638972 Apr 02 12:24:45 PM PDT 24 Apr 02 12:24:49 PM PDT 24 935296277 ps
T614 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.374181927 Apr 02 12:24:57 PM PDT 24 Apr 02 12:24:58 PM PDT 24 190821924 ps
T615 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3985312062 Apr 02 12:25:13 PM PDT 24 Apr 02 12:25:14 PM PDT 24 64581865 ps
T616 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2128071408 Apr 02 12:25:11 PM PDT 24 Apr 02 12:25:12 PM PDT 24 207619487 ps
T617 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.802125085 Apr 02 12:25:01 PM PDT 24 Apr 02 12:25:03 PM PDT 24 460818575 ps
T618 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3518777698 Apr 02 12:25:17 PM PDT 24 Apr 02 12:25:18 PM PDT 24 71445390 ps
T619 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.333523345 Apr 02 12:24:54 PM PDT 24 Apr 02 12:24:54 PM PDT 24 61524746 ps
T620 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.665971313 Apr 02 12:25:13 PM PDT 24 Apr 02 12:25:16 PM PDT 24 377001968 ps

Test location /workspace/coverage/default/7.rstmgr_stress_all.3445415245
Short name T10
Test name
Test status
Simulation time 2136924867 ps
CPU time 9.02 seconds
Started Apr 02 12:36:46 PM PDT 24
Finished Apr 02 12:36:57 PM PDT 24
Peak memory 200968 kb
Host smart-d504ca3d-be3a-4ed8-83bc-670c89cae075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445415245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3445415245
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.285621770
Short name T43
Test name
Test status
Simulation time 373652213 ps
CPU time 2 seconds
Started Apr 02 12:37:23 PM PDT 24
Finished Apr 02 12:37:25 PM PDT 24
Peak memory 200900 kb
Host smart-0d83d421-e083-40c1-a018-d1acff43fa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285621770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.285621770
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2694815247
Short name T69
Test name
Test status
Simulation time 907534061 ps
CPU time 3.03 seconds
Started Apr 02 12:25:00 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 200528 kb
Host smart-00923be5-f179-4b5a-88fe-ca1c4df55d29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694815247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2694815247
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2242240032
Short name T22
Test name
Test status
Simulation time 2355588749 ps
CPU time 8.18 seconds
Started Apr 02 12:36:42 PM PDT 24
Finished Apr 02 12:36:50 PM PDT 24
Peak memory 222720 kb
Host smart-2ea5312f-76b5-431a-9b75-06f407372b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242240032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2242240032
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2825916832
Short name T72
Test name
Test status
Simulation time 16630955556 ps
CPU time 24.81 seconds
Started Apr 02 12:36:35 PM PDT 24
Finished Apr 02 12:37:00 PM PDT 24
Peak memory 217588 kb
Host smart-459e2545-bf94-42bb-a15b-0bdfb6666bfc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825916832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2825916832
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1082979211
Short name T24
Test name
Test status
Simulation time 7923507823 ps
CPU time 27.65 seconds
Started Apr 02 12:37:35 PM PDT 24
Finished Apr 02 12:38:03 PM PDT 24
Peak memory 200992 kb
Host smart-e9c3a769-6230-464b-9b17-f25f2c8e29a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082979211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1082979211
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2328791642
Short name T88
Test name
Test status
Simulation time 623111340 ps
CPU time 4.38 seconds
Started Apr 02 12:25:10 PM PDT 24
Finished Apr 02 12:25:15 PM PDT 24
Peak memory 208652 kb
Host smart-820985db-621e-4aa3-bb60-0a1f4fdcc737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328791642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2328791642
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.4279520989
Short name T138
Test name
Test status
Simulation time 89441927 ps
CPU time 0.89 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200696 kb
Host smart-bd42c15a-11f3-4c47-b9a4-167d7ca118d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279520989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.4279520989
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2365577250
Short name T113
Test name
Test status
Simulation time 6304074090 ps
CPU time 22.91 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:37:21 PM PDT 24
Peak memory 209936 kb
Host smart-b6b8ec2b-d460-472f-885f-6b809f3a85b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365577250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2365577250
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2674797617
Short name T164
Test name
Test status
Simulation time 110690142 ps
CPU time 1.06 seconds
Started Apr 02 12:36:51 PM PDT 24
Finished Apr 02 12:36:55 PM PDT 24
Peak memory 200676 kb
Host smart-dbff882f-f615-4823-b816-2d1412985a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674797617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2674797617
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.373505614
Short name T29
Test name
Test status
Simulation time 1212172179 ps
CPU time 5.77 seconds
Started Apr 02 12:37:05 PM PDT 24
Finished Apr 02 12:37:11 PM PDT 24
Peak memory 218540 kb
Host smart-6768ac4d-9d71-4e42-85dc-fc0023a69e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373505614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.373505614
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.349548603
Short name T7
Test name
Test status
Simulation time 167074865 ps
CPU time 0.94 seconds
Started Apr 02 12:37:01 PM PDT 24
Finished Apr 02 12:37:02 PM PDT 24
Peak memory 200592 kb
Host smart-dbac116e-d8ff-4ed6-b318-0aa0faf2f143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349548603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.349548603
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3144732122
Short name T33
Test name
Test status
Simulation time 2168629300 ps
CPU time 7.54 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:37:00 PM PDT 24
Peak memory 222508 kb
Host smart-acf413d1-a362-40ae-b164-2a9a81ac117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144732122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3144732122
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.462553445
Short name T83
Test name
Test status
Simulation time 912462993 ps
CPU time 2.91 seconds
Started Apr 02 12:25:44 PM PDT 24
Finished Apr 02 12:25:47 PM PDT 24
Peak memory 200468 kb
Host smart-bc9c9172-db32-493f-9ccc-f1603ce32124
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462553445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.462553445
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2364207375
Short name T87
Test name
Test status
Simulation time 312441691 ps
CPU time 2.25 seconds
Started Apr 02 12:24:48 PM PDT 24
Finished Apr 02 12:24:50 PM PDT 24
Peak memory 208568 kb
Host smart-98b8e4c5-bfcd-4d3e-8793-791b3c3c3212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364207375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2364207375
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1992173665
Short name T40
Test name
Test status
Simulation time 246576365 ps
CPU time 1.44 seconds
Started Apr 02 12:37:06 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200992 kb
Host smart-4f5672ea-6709-4482-82f7-cc6cf9b10fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992173665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1992173665
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.213161820
Short name T89
Test name
Test status
Simulation time 942494936 ps
CPU time 3.3 seconds
Started Apr 02 12:25:05 PM PDT 24
Finished Apr 02 12:25:08 PM PDT 24
Peak memory 200496 kb
Host smart-9049898c-a9c4-4426-a023-4c1ee9057aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213161820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.213161820
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.982549910
Short name T107
Test name
Test status
Simulation time 55654559 ps
CPU time 0.73 seconds
Started Apr 02 12:24:49 PM PDT 24
Finished Apr 02 12:24:50 PM PDT 24
Peak memory 200132 kb
Host smart-031caba2-827c-442f-a323-f86bcf018f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982549910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.982549910
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.676284336
Short name T4
Test name
Test status
Simulation time 3916609037 ps
CPU time 17.82 seconds
Started Apr 02 12:36:52 PM PDT 24
Finished Apr 02 12:37:11 PM PDT 24
Peak memory 209240 kb
Host smart-5144963b-ee22-4e53-ba2c-365cebacf5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676284336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.676284336
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3705509614
Short name T575
Test name
Test status
Simulation time 253689670 ps
CPU time 1.62 seconds
Started Apr 02 12:24:52 PM PDT 24
Finished Apr 02 12:24:54 PM PDT 24
Peak memory 200384 kb
Host smart-29b22338-4954-4090-b2c1-3250a0ba88fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705509614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
705509614
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2466397203
Short name T564
Test name
Test status
Simulation time 268994338 ps
CPU time 3.2 seconds
Started Apr 02 12:24:45 PM PDT 24
Finished Apr 02 12:24:51 PM PDT 24
Peak memory 200424 kb
Host smart-a61d3212-b885-4bd6-84e6-ccaef8a59f7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466397203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
466397203
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3656297968
Short name T582
Test name
Test status
Simulation time 99739466 ps
CPU time 0.8 seconds
Started Apr 02 12:24:46 PM PDT 24
Finished Apr 02 12:24:47 PM PDT 24
Peak memory 200120 kb
Host smart-70bb954e-4687-4e41-a736-40026bfb5169
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656297968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
656297968
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1965959700
Short name T570
Test name
Test status
Simulation time 137163303 ps
CPU time 1.07 seconds
Started Apr 02 12:24:58 PM PDT 24
Finished Apr 02 12:24:59 PM PDT 24
Peak memory 209588 kb
Host smart-c8de9c1c-3167-49c0-82d4-de2704e14201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965959700 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1965959700
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1975551934
Short name T550
Test name
Test status
Simulation time 217359719 ps
CPU time 1.42 seconds
Started Apr 02 12:24:46 PM PDT 24
Finished Apr 02 12:24:48 PM PDT 24
Peak memory 200464 kb
Host smart-fbf55c22-27ce-4049-9947-3af70851d148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975551934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1975551934
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1488715580
Short name T560
Test name
Test status
Simulation time 520003175 ps
CPU time 3.11 seconds
Started Apr 02 12:24:35 PM PDT 24
Finished Apr 02 12:24:38 PM PDT 24
Peak memory 208648 kb
Host smart-b68e0dfa-22a8-4299-929c-c0e690674ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488715580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1488715580
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1663638972
Short name T613
Test name
Test status
Simulation time 935296277 ps
CPU time 3.54 seconds
Started Apr 02 12:24:45 PM PDT 24
Finished Apr 02 12:24:49 PM PDT 24
Peak memory 200388 kb
Host smart-e9214c66-e407-4f3e-ad08-8f324a636808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663638972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1663638972
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2777505638
Short name T545
Test name
Test status
Simulation time 448737064 ps
CPU time 2.59 seconds
Started Apr 02 12:25:04 PM PDT 24
Finished Apr 02 12:25:07 PM PDT 24
Peak memory 200436 kb
Host smart-be9165e7-584f-4077-b4a5-504afc6650f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777505638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
777505638
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2160999844
Short name T64
Test name
Test status
Simulation time 278398824 ps
CPU time 3.25 seconds
Started Apr 02 12:25:02 PM PDT 24
Finished Apr 02 12:25:05 PM PDT 24
Peak memory 200472 kb
Host smart-5eca3647-a6f0-463e-bf6b-682d22f1a63a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160999844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
160999844
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.93370191
Short name T543
Test name
Test status
Simulation time 129244119 ps
CPU time 0.89 seconds
Started Apr 02 12:24:41 PM PDT 24
Finished Apr 02 12:24:42 PM PDT 24
Peak memory 200196 kb
Host smart-75398369-969e-4cb9-8c4c-8628e4de73db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93370191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.93370191
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2549906494
Short name T67
Test name
Test status
Simulation time 103157268 ps
CPU time 0.89 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 200300 kb
Host smart-a0dc66c6-e919-4147-8dd9-c21b79341801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549906494 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2549906494
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3458699125
Short name T546
Test name
Test status
Simulation time 83248540 ps
CPU time 0.9 seconds
Started Apr 02 12:25:00 PM PDT 24
Finished Apr 02 12:25:01 PM PDT 24
Peak memory 200220 kb
Host smart-556dbf94-2485-4834-8f21-35d1986f306a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458699125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3458699125
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1383338991
Short name T576
Test name
Test status
Simulation time 228238897 ps
CPU time 1.63 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 200464 kb
Host smart-977eb1b8-e51c-4343-b561-5a115a37a101
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383338991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1383338991
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4074394503
Short name T92
Test name
Test status
Simulation time 935778619 ps
CPU time 3.18 seconds
Started Apr 02 12:24:52 PM PDT 24
Finished Apr 02 12:24:55 PM PDT 24
Peak memory 200468 kb
Host smart-b4003b1e-db73-4a11-8d60-01fd9cb9e2ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074394503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.4074394503
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4161621960
Short name T608
Test name
Test status
Simulation time 126662238 ps
CPU time 1.05 seconds
Started Apr 02 12:25:03 PM PDT 24
Finished Apr 02 12:25:04 PM PDT 24
Peak memory 200244 kb
Host smart-40bb705c-d953-4e03-89b4-ecfac6550833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161621960 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.4161621960
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.925505811
Short name T580
Test name
Test status
Simulation time 56523315 ps
CPU time 0.78 seconds
Started Apr 02 12:25:02 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 200220 kb
Host smart-be9ee0bf-48ab-4b95-8603-687378d69266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925505811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.925505811
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.536651732
Short name T554
Test name
Test status
Simulation time 130664559 ps
CPU time 1.12 seconds
Started Apr 02 12:25:03 PM PDT 24
Finished Apr 02 12:25:05 PM PDT 24
Peak memory 200308 kb
Host smart-c4b4f308-a259-4b53-a197-b132332dba69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536651732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.536651732
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.115726979
Short name T65
Test name
Test status
Simulation time 421570806 ps
CPU time 3 seconds
Started Apr 02 12:25:09 PM PDT 24
Finished Apr 02 12:25:12 PM PDT 24
Peak memory 208652 kb
Host smart-13d42ff0-a886-41cf-8050-4ba59a10ba85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115726979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.115726979
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2452349959
Short name T68
Test name
Test status
Simulation time 772202203 ps
CPU time 2.7 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:09 PM PDT 24
Peak memory 200500 kb
Host smart-38582b6b-7feb-4edd-b102-0256e7ba4ead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452349959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2452349959
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.96554307
Short name T541
Test name
Test status
Simulation time 175230753 ps
CPU time 1.16 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:56 PM PDT 24
Peak memory 209828 kb
Host smart-32bd548f-bf60-4e47-96fa-9ff647425168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96554307 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.96554307
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3604036008
Short name T607
Test name
Test status
Simulation time 75818597 ps
CPU time 0.85 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 200240 kb
Host smart-84a0a77f-5dcc-490e-818e-2b12e275b863
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604036008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3604036008
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3059131698
Short name T574
Test name
Test status
Simulation time 152415342 ps
CPU time 1.18 seconds
Started Apr 02 12:25:11 PM PDT 24
Finished Apr 02 12:25:12 PM PDT 24
Peak memory 200308 kb
Host smart-f5ec490b-d71a-49c7-98e4-45fa17c7a018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059131698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3059131698
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1945763408
Short name T601
Test name
Test status
Simulation time 423752058 ps
CPU time 2.79 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:25:01 PM PDT 24
Peak memory 216712 kb
Host smart-65ecea4c-176d-4942-bc77-6cbb49f47e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945763408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1945763408
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1933111145
Short name T602
Test name
Test status
Simulation time 467578491 ps
CPU time 1.94 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:53 PM PDT 24
Peak memory 200512 kb
Host smart-6e2ed436-ae5f-4594-a27d-d77369e1af16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933111145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1933111145
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3183966316
Short name T571
Test name
Test status
Simulation time 172832201 ps
CPU time 1.2 seconds
Started Apr 02 12:25:02 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 209408 kb
Host smart-a08f4efe-bc0e-4fce-895a-74d4fb8bc9b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183966316 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3183966316
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4039456939
Short name T588
Test name
Test status
Simulation time 80195891 ps
CPU time 0.85 seconds
Started Apr 02 12:25:07 PM PDT 24
Finished Apr 02 12:25:09 PM PDT 24
Peak memory 200240 kb
Host smart-69f41c65-a3d9-457c-bd1a-77f92f7291f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039456939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.4039456939
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3264563833
Short name T569
Test name
Test status
Simulation time 85398692 ps
CPU time 1.04 seconds
Started Apr 02 12:25:02 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 200116 kb
Host smart-4ca6f23a-9fcd-45fc-9f2e-71f9ebcf68ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264563833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3264563833
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3292647197
Short name T93
Test name
Test status
Simulation time 205247714 ps
CPU time 1.47 seconds
Started Apr 02 12:25:03 PM PDT 24
Finished Apr 02 12:25:05 PM PDT 24
Peak memory 200284 kb
Host smart-10a0dd79-0358-4cac-88f6-67f26b923a32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292647197 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3292647197
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2853977691
Short name T590
Test name
Test status
Simulation time 69790770 ps
CPU time 0.77 seconds
Started Apr 02 12:25:07 PM PDT 24
Finished Apr 02 12:25:08 PM PDT 24
Peak memory 200232 kb
Host smart-03313276-3cae-4999-b7c1-699752a37493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853977691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2853977691
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1189079750
Short name T610
Test name
Test status
Simulation time 211330236 ps
CPU time 1.51 seconds
Started Apr 02 12:24:55 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 200548 kb
Host smart-c7d53e34-757c-4a69-b124-d636894c424d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189079750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1189079750
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.984711772
Short name T85
Test name
Test status
Simulation time 189363494 ps
CPU time 2.63 seconds
Started Apr 02 12:25:05 PM PDT 24
Finished Apr 02 12:25:08 PM PDT 24
Peak memory 208576 kb
Host smart-8aa4c5d8-1d4c-4e4d-b17d-3dcb799d94e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984711772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.984711772
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2788087941
Short name T609
Test name
Test status
Simulation time 428329402 ps
CPU time 1.8 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:09 PM PDT 24
Peak memory 200468 kb
Host smart-e2a06de1-1e87-46d6-bbd1-e32049fa9eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788087941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2788087941
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1591853382
Short name T600
Test name
Test status
Simulation time 205528152 ps
CPU time 1.39 seconds
Started Apr 02 12:25:02 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 211264 kb
Host smart-b0fcd091-ca9f-493f-b35e-d71481a8af94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591853382 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1591853382
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3518777698
Short name T618
Test name
Test status
Simulation time 71445390 ps
CPU time 0.76 seconds
Started Apr 02 12:25:17 PM PDT 24
Finished Apr 02 12:25:18 PM PDT 24
Peak memory 200272 kb
Host smart-1fcf7165-8251-4379-a452-5a42cb5527b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518777698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3518777698
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.620765459
Short name T605
Test name
Test status
Simulation time 108938938 ps
CPU time 1.12 seconds
Started Apr 02 12:25:02 PM PDT 24
Finished Apr 02 12:25:04 PM PDT 24
Peak memory 200304 kb
Host smart-8a42e471-f5ad-4f1f-bd3d-37a6ecb53efe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620765459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.620765459
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1626466480
Short name T542
Test name
Test status
Simulation time 278776431 ps
CPU time 2 seconds
Started Apr 02 12:25:15 PM PDT 24
Finished Apr 02 12:25:17 PM PDT 24
Peak memory 208644 kb
Host smart-5aec3e58-570f-4993-916a-025e83bb06e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626466480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1626466480
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.198317163
Short name T578
Test name
Test status
Simulation time 430915862 ps
CPU time 1.83 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 200440 kb
Host smart-30fdb6e3-026e-4c6f-b1c9-6207be1d0a42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198317163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.198317163
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3925783288
Short name T584
Test name
Test status
Simulation time 187245023 ps
CPU time 1.25 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:58 PM PDT 24
Peak memory 208544 kb
Host smart-6d502311-4a96-4e45-a778-762d929acd2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925783288 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3925783288
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3254106188
Short name T104
Test name
Test status
Simulation time 58164263 ps
CPU time 0.82 seconds
Started Apr 02 12:25:03 PM PDT 24
Finished Apr 02 12:25:04 PM PDT 24
Peak memory 200272 kb
Host smart-eeebf31b-0490-445a-a9cf-4742677cffd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254106188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3254106188
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.374181927
Short name T614
Test name
Test status
Simulation time 190821924 ps
CPU time 1.35 seconds
Started Apr 02 12:24:57 PM PDT 24
Finished Apr 02 12:24:58 PM PDT 24
Peak memory 200368 kb
Host smart-9bf1d7a1-9b17-4d9f-ae59-8ec95d010250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374181927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.374181927
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1623107831
Short name T66
Test name
Test status
Simulation time 134615358 ps
CPU time 1.79 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:08 PM PDT 24
Peak memory 208684 kb
Host smart-e87f2b92-7154-4649-acb1-0af78ff91891
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623107831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1623107831
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2128071408
Short name T616
Test name
Test status
Simulation time 207619487 ps
CPU time 1.28 seconds
Started Apr 02 12:25:11 PM PDT 24
Finished Apr 02 12:25:12 PM PDT 24
Peak memory 200188 kb
Host smart-f5c6f145-d0d3-4e73-97df-6d2d1362fed0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128071408 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2128071408
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2291323048
Short name T596
Test name
Test status
Simulation time 58606748 ps
CPU time 0.8 seconds
Started Apr 02 12:25:43 PM PDT 24
Finished Apr 02 12:25:44 PM PDT 24
Peak memory 200264 kb
Host smart-40b29043-a110-423d-9d4d-a4d56ed4ac91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291323048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2291323048
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3471901775
Short name T591
Test name
Test status
Simulation time 129521922 ps
CPU time 1.24 seconds
Started Apr 02 12:25:03 PM PDT 24
Finished Apr 02 12:25:04 PM PDT 24
Peak memory 200476 kb
Host smart-dc354a05-b589-43aa-a4f4-b7b647b4597e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471901775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3471901775
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2422432027
Short name T597
Test name
Test status
Simulation time 449447580 ps
CPU time 2.71 seconds
Started Apr 02 12:25:07 PM PDT 24
Finished Apr 02 12:25:10 PM PDT 24
Peak memory 208616 kb
Host smart-f3cfd93f-63f6-4af2-9e56-35f82e6fce64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422432027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2422432027
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1994060223
Short name T123
Test name
Test status
Simulation time 420903004 ps
CPU time 1.83 seconds
Started Apr 02 12:25:02 PM PDT 24
Finished Apr 02 12:25:04 PM PDT 24
Peak memory 200340 kb
Host smart-593e6ffc-c20e-4347-867a-e991f9f42d51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994060223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1994060223
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3571974562
Short name T95
Test name
Test status
Simulation time 195159571 ps
CPU time 1.89 seconds
Started Apr 02 12:25:03 PM PDT 24
Finished Apr 02 12:25:05 PM PDT 24
Peak memory 208672 kb
Host smart-d6e33638-18e5-4fe4-83e7-a6d3977070a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571974562 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3571974562
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3116025809
Short name T108
Test name
Test status
Simulation time 60314412 ps
CPU time 0.79 seconds
Started Apr 02 12:25:00 PM PDT 24
Finished Apr 02 12:25:01 PM PDT 24
Peak memory 200224 kb
Host smart-88b5a764-6ac3-4469-b808-58443818c10f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116025809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3116025809
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3320407358
Short name T592
Test name
Test status
Simulation time 107615571 ps
CPU time 1.29 seconds
Started Apr 02 12:25:07 PM PDT 24
Finished Apr 02 12:25:08 PM PDT 24
Peak memory 200468 kb
Host smart-2151aa09-84ba-48e9-bf6d-57fd913dc45e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320407358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3320407358
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4274876358
Short name T577
Test name
Test status
Simulation time 521498901 ps
CPU time 3.26 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 208752 kb
Host smart-9e52ec60-88ad-4694-8275-cb502d4c938f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274876358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4274876358
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1730769118
Short name T124
Test name
Test status
Simulation time 932086342 ps
CPU time 3.06 seconds
Started Apr 02 12:25:04 PM PDT 24
Finished Apr 02 12:25:07 PM PDT 24
Peak memory 200548 kb
Host smart-071fe903-4e70-4332-bb92-cf00cb3b2af4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730769118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1730769118
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1568694657
Short name T561
Test name
Test status
Simulation time 145578418 ps
CPU time 1.18 seconds
Started Apr 02 12:25:08 PM PDT 24
Finished Apr 02 12:25:10 PM PDT 24
Peak memory 208484 kb
Host smart-d4d391d5-7f28-4e7c-8326-feec28328e43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568694657 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1568694657
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3063238690
Short name T62
Test name
Test status
Simulation time 78907458 ps
CPU time 0.86 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:55 PM PDT 24
Peak memory 200224 kb
Host smart-b2abb7bf-5ec0-40eb-ba9e-fdf1a9a01724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063238690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3063238690
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3584151368
Short name T63
Test name
Test status
Simulation time 192112981 ps
CPU time 1.36 seconds
Started Apr 02 12:25:15 PM PDT 24
Finished Apr 02 12:25:17 PM PDT 24
Peak memory 200524 kb
Host smart-dc804a3f-1103-42a3-92e3-9ab0c6a5bbba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584151368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3584151368
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.665971313
Short name T620
Test name
Test status
Simulation time 377001968 ps
CPU time 2.9 seconds
Started Apr 02 12:25:13 PM PDT 24
Finished Apr 02 12:25:16 PM PDT 24
Peak memory 212188 kb
Host smart-d543d53e-c40b-4f5c-9b50-8cedf3be0e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665971313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.665971313
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1395478376
Short name T91
Test name
Test status
Simulation time 467501516 ps
CPU time 1.89 seconds
Started Apr 02 12:25:09 PM PDT 24
Finished Apr 02 12:25:11 PM PDT 24
Peak memory 200500 kb
Host smart-679a2157-44dc-44c9-86e6-330eeaa19aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395478376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1395478376
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.289829920
Short name T585
Test name
Test status
Simulation time 164749560 ps
CPU time 1.56 seconds
Started Apr 02 12:25:11 PM PDT 24
Finished Apr 02 12:25:13 PM PDT 24
Peak memory 208772 kb
Host smart-de4c4926-3926-4e11-8120-2585a27e2c40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289829920 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.289829920
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1138523635
Short name T589
Test name
Test status
Simulation time 81730084 ps
CPU time 0.87 seconds
Started Apr 02 12:25:12 PM PDT 24
Finished Apr 02 12:25:13 PM PDT 24
Peak memory 200192 kb
Host smart-d48caa13-e947-481b-89b0-da201438352c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138523635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1138523635
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1525419843
Short name T567
Test name
Test status
Simulation time 75605085 ps
CPU time 1.04 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:07 PM PDT 24
Peak memory 200308 kb
Host smart-6022abca-d29d-4a8f-b906-8d1685a937a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525419843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1525419843
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1850420594
Short name T553
Test name
Test status
Simulation time 352568978 ps
CPU time 2.42 seconds
Started Apr 02 12:25:09 PM PDT 24
Finished Apr 02 12:25:13 PM PDT 24
Peak memory 208672 kb
Host smart-8add46b9-09ed-4b8e-a6bf-c4f69ae6bf3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850420594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1850420594
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.487846979
Short name T612
Test name
Test status
Simulation time 877539932 ps
CPU time 3.23 seconds
Started Apr 02 12:25:10 PM PDT 24
Finished Apr 02 12:25:14 PM PDT 24
Peak memory 200580 kb
Host smart-46c6e02a-b21a-4cd6-bfc8-21c86b0b2f71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487846979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.487846979
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3800152881
Short name T540
Test name
Test status
Simulation time 157406096 ps
CPU time 2.05 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:59 PM PDT 24
Peak memory 200284 kb
Host smart-b831ce25-f3f1-45fd-a9a2-9ab861769e8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800152881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
800152881
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.219501233
Short name T539
Test name
Test status
Simulation time 803333179 ps
CPU time 4.84 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:25:04 PM PDT 24
Peak memory 200448 kb
Host smart-40519c1e-51b6-4e67-8334-725812041ac8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219501233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.219501233
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2763331858
Short name T558
Test name
Test status
Simulation time 140732118 ps
CPU time 0.9 seconds
Started Apr 02 12:25:13 PM PDT 24
Finished Apr 02 12:25:14 PM PDT 24
Peak memory 200176 kb
Host smart-2dcf2c3b-aeb5-4411-8dde-9955b41a5648
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763331858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
763331858
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.970224691
Short name T544
Test name
Test status
Simulation time 195900157 ps
CPU time 1.35 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:07 PM PDT 24
Peak memory 208628 kb
Host smart-44552503-27d9-410d-8e69-305eec372224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970224691 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.970224691
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3512493622
Short name T611
Test name
Test status
Simulation time 64701439 ps
CPU time 0.77 seconds
Started Apr 02 12:24:52 PM PDT 24
Finished Apr 02 12:24:53 PM PDT 24
Peak memory 199956 kb
Host smart-2daa0889-11f7-4fa0-9c36-d9511d84fd6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512493622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3512493622
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.690031636
Short name T105
Test name
Test status
Simulation time 141529556 ps
CPU time 1.08 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 200180 kb
Host smart-7f424a5f-5d07-412d-8719-2663851b4203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690031636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.690031636
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.839502598
Short name T549
Test name
Test status
Simulation time 330736047 ps
CPU time 2.4 seconds
Started Apr 02 12:25:00 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 208636 kb
Host smart-8d05dc1d-ead6-4416-962d-6ab4debc22b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839502598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.839502598
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3297430434
Short name T581
Test name
Test status
Simulation time 433290258 ps
CPU time 1.75 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 200548 kb
Host smart-3572ac64-6730-480d-a8be-2cbaa04c7033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297430434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3297430434
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1509099233
Short name T557
Test name
Test status
Simulation time 358453312 ps
CPU time 2.7 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:09 PM PDT 24
Peak memory 200492 kb
Host smart-dc145043-ee69-4187-81ff-72ef10137fd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509099233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
509099233
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.191311051
Short name T587
Test name
Test status
Simulation time 1172959278 ps
CPU time 5.44 seconds
Started Apr 02 12:24:47 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 200472 kb
Host smart-991ed906-69f3-4e45-bce1-c77eeddb63bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191311051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.191311051
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3391404422
Short name T556
Test name
Test status
Simulation time 96481874 ps
CPU time 0.81 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 200264 kb
Host smart-210feba9-a81c-434c-8026-8192d4127646
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391404422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
391404422
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3239440741
Short name T595
Test name
Test status
Simulation time 110245060 ps
CPU time 1.12 seconds
Started Apr 02 12:25:05 PM PDT 24
Finished Apr 02 12:25:06 PM PDT 24
Peak memory 208504 kb
Host smart-8e570b3d-2381-43b6-a2f2-509ef25282ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239440741 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3239440741
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4226416996
Short name T538
Test name
Test status
Simulation time 95030267 ps
CPU time 0.86 seconds
Started Apr 02 12:24:51 PM PDT 24
Finished Apr 02 12:24:52 PM PDT 24
Peak memory 200244 kb
Host smart-ae4a342f-d0d7-477e-b9b4-190c554baaa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226416996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4226416996
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.919326874
Short name T598
Test name
Test status
Simulation time 71941539 ps
CPU time 0.95 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:55 PM PDT 24
Peak memory 200148 kb
Host smart-e17cd526-3411-4d52-8d79-a90928f6389e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919326874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.919326874
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.808303839
Short name T548
Test name
Test status
Simulation time 245542454 ps
CPU time 1.95 seconds
Started Apr 02 12:25:12 PM PDT 24
Finished Apr 02 12:25:19 PM PDT 24
Peak memory 208712 kb
Host smart-acba9177-a610-4e04-8ff7-bdedfdeddd5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808303839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.808303839
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2367922929
Short name T593
Test name
Test status
Simulation time 485376296 ps
CPU time 1.89 seconds
Started Apr 02 12:25:12 PM PDT 24
Finished Apr 02 12:25:14 PM PDT 24
Peak memory 200448 kb
Host smart-18f73623-c156-4f53-9e97-6d6a1bad4deb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367922929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2367922929
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2765319112
Short name T573
Test name
Test status
Simulation time 438626657 ps
CPU time 2.49 seconds
Started Apr 02 12:26:03 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 200416 kb
Host smart-7b41672f-3e4b-4229-b2b3-d931c3b6fa19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765319112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
765319112
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2406042970
Short name T565
Test name
Test status
Simulation time 485242343 ps
CPU time 5.72 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:25:02 PM PDT 24
Peak memory 216712 kb
Host smart-7500793f-81c7-41d9-98f1-d09a6f0efbc4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406042970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
406042970
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2616035097
Short name T568
Test name
Test status
Simulation time 136524410 ps
CPU time 0.95 seconds
Started Apr 02 12:25:08 PM PDT 24
Finished Apr 02 12:25:09 PM PDT 24
Peak memory 200244 kb
Host smart-38f0b607-81dd-4959-8741-66790f75214a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616035097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
616035097
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.583584687
Short name T84
Test name
Test status
Simulation time 155817840 ps
CPU time 1.39 seconds
Started Apr 02 12:25:09 PM PDT 24
Finished Apr 02 12:25:10 PM PDT 24
Peak memory 208544 kb
Host smart-6256382f-af1b-4229-b668-5d56ebdb8b57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583584687 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.583584687
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.223229415
Short name T551
Test name
Test status
Simulation time 60538368 ps
CPU time 0.75 seconds
Started Apr 02 12:24:46 PM PDT 24
Finished Apr 02 12:24:50 PM PDT 24
Peak memory 200244 kb
Host smart-e069a8a9-9930-49d6-a1e4-9007838a22b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223229415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.223229415
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1908362972
Short name T109
Test name
Test status
Simulation time 139863437 ps
CPU time 1.13 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 200192 kb
Host smart-8031998a-6350-4e8c-b4a8-1821c8f06d2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908362972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1908362972
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4288223848
Short name T583
Test name
Test status
Simulation time 449251584 ps
CPU time 3.23 seconds
Started Apr 02 12:24:47 PM PDT 24
Finished Apr 02 12:24:50 PM PDT 24
Peak memory 211988 kb
Host smart-9a50c90c-2328-4841-89e3-da12018caf29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288223848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.4288223848
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3194644377
Short name T579
Test name
Test status
Simulation time 927080570 ps
CPU time 2.97 seconds
Started Apr 02 12:24:57 PM PDT 24
Finished Apr 02 12:25:01 PM PDT 24
Peak memory 200480 kb
Host smart-52c83a86-d3d9-4a9d-b81e-a42633198685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194644377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3194644377
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.636963772
Short name T599
Test name
Test status
Simulation time 194496040 ps
CPU time 1.23 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:07 PM PDT 24
Peak memory 208508 kb
Host smart-b9c2ad3a-8176-4d79-8595-816cfb382810
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636963772 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.636963772
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3985312062
Short name T615
Test name
Test status
Simulation time 64581865 ps
CPU time 0.77 seconds
Started Apr 02 12:25:13 PM PDT 24
Finished Apr 02 12:25:14 PM PDT 24
Peak memory 200152 kb
Host smart-47d007bb-5023-413b-93a2-d684bfb44093
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985312062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3985312062
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.25758943
Short name T111
Test name
Test status
Simulation time 188066682 ps
CPU time 1.32 seconds
Started Apr 02 12:24:57 PM PDT 24
Finished Apr 02 12:24:59 PM PDT 24
Peak memory 200528 kb
Host smart-b386113d-b703-4ea4-9c27-898d6e4a4ae0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25758943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same
_csr_outstanding.25758943
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2935605524
Short name T86
Test name
Test status
Simulation time 195500080 ps
CPU time 2.8 seconds
Started Apr 02 12:25:05 PM PDT 24
Finished Apr 02 12:25:08 PM PDT 24
Peak memory 208672 kb
Host smart-57d0e586-ffc0-4d4b-a6ff-8e411eb52384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935605524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2935605524
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1969614629
Short name T547
Test name
Test status
Simulation time 423074367 ps
CPU time 1.63 seconds
Started Apr 02 12:24:57 PM PDT 24
Finished Apr 02 12:24:58 PM PDT 24
Peak memory 200460 kb
Host smart-0dc6ff93-c0fc-42f6-83af-8da894fa6766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969614629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1969614629
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.816615073
Short name T586
Test name
Test status
Simulation time 206786582 ps
CPU time 1.37 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 210996 kb
Host smart-7881e709-8e7c-4dfa-8b13-50fdce111720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816615073 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.816615073
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.333523345
Short name T619
Test name
Test status
Simulation time 61524746 ps
CPU time 0.79 seconds
Started Apr 02 12:24:54 PM PDT 24
Finished Apr 02 12:24:54 PM PDT 24
Peak memory 200220 kb
Host smart-565c851e-e540-4a5b-9b91-37fdd7411730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333523345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.333523345
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2463755816
Short name T112
Test name
Test status
Simulation time 151415053 ps
CPU time 1.17 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 200368 kb
Host smart-1a2479f9-0ffe-4e81-8296-9438f6f2de67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463755816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2463755816
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.496435705
Short name T606
Test name
Test status
Simulation time 193733337 ps
CPU time 2.61 seconds
Started Apr 02 12:25:07 PM PDT 24
Finished Apr 02 12:25:10 PM PDT 24
Peak memory 208708 kb
Host smart-39446eef-9c12-426d-b935-136cff65f875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496435705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.496435705
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2740615458
Short name T94
Test name
Test status
Simulation time 834702438 ps
CPU time 2.73 seconds
Started Apr 02 12:24:57 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 200504 kb
Host smart-1033e53c-bf93-4b2d-8e03-d13748bd4ea2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740615458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2740615458
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2463423878
Short name T552
Test name
Test status
Simulation time 173154796 ps
CPU time 1.16 seconds
Started Apr 02 12:25:09 PM PDT 24
Finished Apr 02 12:25:11 PM PDT 24
Peak memory 200408 kb
Host smart-27183bc1-2291-46bd-b91f-3ca18c233658
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463423878 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2463423878
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3769731913
Short name T563
Test name
Test status
Simulation time 54067157 ps
CPU time 0.8 seconds
Started Apr 02 12:24:49 PM PDT 24
Finished Apr 02 12:24:50 PM PDT 24
Peak memory 200204 kb
Host smart-781aa842-8037-4c2b-81fa-be1634d4b60d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769731913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3769731913
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3575794968
Short name T562
Test name
Test status
Simulation time 75856890 ps
CPU time 0.95 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:07 PM PDT 24
Peak memory 200336 kb
Host smart-ad9de0d5-43d5-4f34-af85-906bac72681b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575794968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3575794968
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3186856794
Short name T90
Test name
Test status
Simulation time 185201679 ps
CPU time 1.4 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 208560 kb
Host smart-0ef335f1-7c7f-48fc-9315-3420c186b4bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186856794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3186856794
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1808012716
Short name T603
Test name
Test status
Simulation time 112997073 ps
CPU time 0.9 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 200328 kb
Host smart-3bdfdfd6-5c9f-46e2-9fa5-810ce6c8f831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808012716 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1808012716
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2983616169
Short name T555
Test name
Test status
Simulation time 66872526 ps
CPU time 0.79 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:08 PM PDT 24
Peak memory 200244 kb
Host smart-9aa40861-fbbf-4bc3-82fb-8464d930d9c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983616169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2983616169
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3556990132
Short name T106
Test name
Test status
Simulation time 124278430 ps
CPU time 1.09 seconds
Started Apr 02 12:24:59 PM PDT 24
Finished Apr 02 12:25:00 PM PDT 24
Peak memory 200276 kb
Host smart-5aefc003-ff81-4d18-8e1c-0b925f3fc390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556990132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3556990132
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3760099679
Short name T559
Test name
Test status
Simulation time 307483972 ps
CPU time 1.92 seconds
Started Apr 02 12:25:07 PM PDT 24
Finished Apr 02 12:25:10 PM PDT 24
Peak memory 208608 kb
Host smart-3763a1bf-3d6f-4b34-b980-6926fb36394e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760099679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3760099679
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.802125085
Short name T617
Test name
Test status
Simulation time 460818575 ps
CPU time 1.82 seconds
Started Apr 02 12:25:01 PM PDT 24
Finished Apr 02 12:25:03 PM PDT 24
Peak memory 200536 kb
Host smart-134dcb2e-172c-4d76-9845-5850d6288ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802125085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
802125085
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3417764941
Short name T604
Test name
Test status
Simulation time 194791831 ps
CPU time 1.38 seconds
Started Apr 02 12:24:57 PM PDT 24
Finished Apr 02 12:24:59 PM PDT 24
Peak memory 210856 kb
Host smart-df59bbf5-6ffd-43cf-aff0-88cc6941f689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417764941 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3417764941
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.54169581
Short name T572
Test name
Test status
Simulation time 81164334 ps
CPU time 0.85 seconds
Started Apr 02 12:24:56 PM PDT 24
Finished Apr 02 12:24:57 PM PDT 24
Peak memory 200040 kb
Host smart-33668322-4728-49dd-a063-1d40188bc57b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54169581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.54169581
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1808380957
Short name T110
Test name
Test status
Simulation time 76787496 ps
CPU time 1.02 seconds
Started Apr 02 12:25:00 PM PDT 24
Finished Apr 02 12:25:01 PM PDT 24
Peak memory 200288 kb
Host smart-f92dd958-b3c2-41d6-838f-7cc283151989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808380957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1808380957
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4214579674
Short name T566
Test name
Test status
Simulation time 138873304 ps
CPU time 1.97 seconds
Started Apr 02 12:25:05 PM PDT 24
Finished Apr 02 12:25:07 PM PDT 24
Peak memory 208588 kb
Host smart-7f4104ef-5f01-4fcf-a696-4e942b92a2df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214579674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4214579674
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.551288638
Short name T594
Test name
Test status
Simulation time 429615433 ps
CPU time 1.78 seconds
Started Apr 02 12:25:06 PM PDT 24
Finished Apr 02 12:25:08 PM PDT 24
Peak memory 200528 kb
Host smart-df9f93f9-7c25-4b64-8ba9-3ef3b4ddce42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551288638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
551288638
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4214780319
Short name T405
Test name
Test status
Simulation time 67281236 ps
CPU time 0.74 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:36:40 PM PDT 24
Peak memory 200676 kb
Host smart-6a871caf-9e5a-4ecd-9aa5-b3eaa013287e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214780319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4214780319
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3370882772
Short name T45
Test name
Test status
Simulation time 2186053427 ps
CPU time 7.98 seconds
Started Apr 02 12:36:51 PM PDT 24
Finished Apr 02 12:37:02 PM PDT 24
Peak memory 222408 kb
Host smart-3871eee8-e18b-4ae7-9ea9-ae41b4af864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370882772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3370882772
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2254732379
Short name T130
Test name
Test status
Simulation time 244368615 ps
CPU time 1.13 seconds
Started Apr 02 12:36:40 PM PDT 24
Finished Apr 02 12:36:42 PM PDT 24
Peak memory 218000 kb
Host smart-f7e075aa-6276-4762-8bd2-28f2d79a87e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254732379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2254732379
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.754671273
Short name T499
Test name
Test status
Simulation time 106533053 ps
CPU time 0.79 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 200540 kb
Host smart-22022307-4b82-43b3-a2e6-c5847b4634a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754671273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.754671273
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2588561459
Short name T269
Test name
Test status
Simulation time 1126122231 ps
CPU time 4.9 seconds
Started Apr 02 12:36:38 PM PDT 24
Finished Apr 02 12:36:43 PM PDT 24
Peak memory 200996 kb
Host smart-a78af74c-99f6-4c13-bf84-78c2993339d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588561459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2588561459
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.792670742
Short name T167
Test name
Test status
Simulation time 223949591 ps
CPU time 1.41 seconds
Started Apr 02 12:36:41 PM PDT 24
Finished Apr 02 12:36:43 PM PDT 24
Peak memory 200884 kb
Host smart-a3d4766c-917a-458f-9089-a3ad54a1510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792670742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.792670742
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2562319404
Short name T298
Test name
Test status
Simulation time 1915912318 ps
CPU time 8.04 seconds
Started Apr 02 12:36:48 PM PDT 24
Finished Apr 02 12:36:58 PM PDT 24
Peak memory 200908 kb
Host smart-d56ebe9d-260a-4826-817e-084c2e1a89aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562319404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2562319404
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2690745822
Short name T227
Test name
Test status
Simulation time 379960021 ps
CPU time 2.56 seconds
Started Apr 02 12:36:51 PM PDT 24
Finished Apr 02 12:36:56 PM PDT 24
Peak memory 200656 kb
Host smart-d86eac4d-0ef1-4f0d-a27d-41583ba90957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690745822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2690745822
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3836700661
Short name T300
Test name
Test status
Simulation time 106313674 ps
CPU time 0.89 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 200668 kb
Host smart-f3ac92d2-5e6d-433e-a768-e9472e487a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836700661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3836700661
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2647496634
Short name T495
Test name
Test status
Simulation time 70874485 ps
CPU time 0.78 seconds
Started Apr 02 12:36:38 PM PDT 24
Finished Apr 02 12:36:39 PM PDT 24
Peak memory 200680 kb
Host smart-7f6a43a7-1bee-46f1-87cd-12b3945a3a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647496634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2647496634
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1347503974
Short name T50
Test name
Test status
Simulation time 1903262514 ps
CPU time 7.01 seconds
Started Apr 02 12:36:40 PM PDT 24
Finished Apr 02 12:36:48 PM PDT 24
Peak memory 222000 kb
Host smart-e0a6d1aa-3702-4ea3-b35e-77ff04fb918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347503974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1347503974
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3487836837
Short name T397
Test name
Test status
Simulation time 244523722 ps
CPU time 1.08 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 218108 kb
Host smart-70dc390e-3022-401c-9606-9f0fae38275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487836837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3487836837
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2157594661
Short name T199
Test name
Test status
Simulation time 160650307 ps
CPU time 0.9 seconds
Started Apr 02 12:36:44 PM PDT 24
Finished Apr 02 12:36:46 PM PDT 24
Peak memory 200552 kb
Host smart-5170647a-b5b3-4a1a-abe9-e604cc6b1768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157594661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2157594661
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.429012594
Short name T242
Test name
Test status
Simulation time 1837327328 ps
CPU time 6.87 seconds
Started Apr 02 12:36:40 PM PDT 24
Finished Apr 02 12:36:47 PM PDT 24
Peak memory 200888 kb
Host smart-45510471-cceb-4ff3-9928-db3dd149f8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429012594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.429012594
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.755238809
Short name T71
Test name
Test status
Simulation time 16501624952 ps
CPU time 27.61 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:37:07 PM PDT 24
Peak memory 217616 kb
Host smart-7703fe95-9720-4bcd-8600-dda461fdf26c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755238809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.755238809
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1505704749
Short name T464
Test name
Test status
Simulation time 173160694 ps
CPU time 1.27 seconds
Started Apr 02 12:36:40 PM PDT 24
Finished Apr 02 12:36:42 PM PDT 24
Peak memory 200820 kb
Host smart-410f6965-4352-487b-80a9-30f265894e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505704749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1505704749
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1912136764
Short name T38
Test name
Test status
Simulation time 120447281 ps
CPU time 1.14 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:53 PM PDT 24
Peak memory 200900 kb
Host smart-cc2518b5-4c76-4277-a87a-9f4b3603a91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912136764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1912136764
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.277843467
Short name T55
Test name
Test status
Simulation time 8428937380 ps
CPU time 27.04 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:37:06 PM PDT 24
Peak memory 201076 kb
Host smart-652e0f8f-362a-45a4-8ef3-5a1640b01dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277843467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.277843467
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.715092081
Short name T341
Test name
Test status
Simulation time 391625185 ps
CPU time 2.6 seconds
Started Apr 02 12:36:40 PM PDT 24
Finished Apr 02 12:36:43 PM PDT 24
Peak memory 200792 kb
Host smart-fa49b9f0-f656-4fc8-a105-cc6ea0fe630b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715092081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.715092081
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1106159027
Short name T469
Test name
Test status
Simulation time 148357566 ps
CPU time 1.15 seconds
Started Apr 02 12:36:41 PM PDT 24
Finished Apr 02 12:36:43 PM PDT 24
Peak memory 200688 kb
Host smart-b81d28ae-9405-4d51-b193-3be816974e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106159027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1106159027
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1568266389
Short name T229
Test name
Test status
Simulation time 78648583 ps
CPU time 0.76 seconds
Started Apr 02 12:36:53 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 200692 kb
Host smart-854e87d7-7be9-4335-ae12-c54c627547ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568266389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1568266389
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3609146310
Short name T30
Test name
Test status
Simulation time 1229038107 ps
CPU time 5.55 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 217604 kb
Host smart-976b24ee-9aa9-4cd4-9141-aa2328ea7fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609146310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3609146310
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.779544862
Short name T515
Test name
Test status
Simulation time 243416645 ps
CPU time 1.16 seconds
Started Apr 02 12:36:52 PM PDT 24
Finished Apr 02 12:36:56 PM PDT 24
Peak memory 218188 kb
Host smart-5d3be2dc-0e46-455d-8293-4e850423e5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779544862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.779544862
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4010247259
Short name T525
Test name
Test status
Simulation time 118939279 ps
CPU time 0.78 seconds
Started Apr 02 12:36:52 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 200608 kb
Host smart-e441a64b-d752-47dc-953a-613d41f64126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010247259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4010247259
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2219770992
Short name T455
Test name
Test status
Simulation time 1875925170 ps
CPU time 7.49 seconds
Started Apr 02 12:36:54 PM PDT 24
Finished Apr 02 12:37:05 PM PDT 24
Peak memory 201040 kb
Host smart-aed537bc-914f-41d6-b5ea-e5de0cd72fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219770992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2219770992
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3370063782
Short name T505
Test name
Test status
Simulation time 143564748 ps
CPU time 1.18 seconds
Started Apr 02 12:36:53 PM PDT 24
Finished Apr 02 12:36:56 PM PDT 24
Peak memory 200832 kb
Host smart-36921d7a-1a0a-4a9d-8dda-c30f84074947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370063782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3370063782
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2954747011
Short name T181
Test name
Test status
Simulation time 207456434 ps
CPU time 1.34 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:53 PM PDT 24
Peak memory 201012 kb
Host smart-f057d40f-f2a4-4449-9ee5-3060af4f1270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954747011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2954747011
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3727654442
Short name T342
Test name
Test status
Simulation time 305245224 ps
CPU time 2.11 seconds
Started Apr 02 12:36:51 PM PDT 24
Finished Apr 02 12:36:56 PM PDT 24
Peak memory 209004 kb
Host smart-d2d04fcc-2f5e-43b0-9241-e364f27a6a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727654442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3727654442
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3671831677
Short name T340
Test name
Test status
Simulation time 182691304 ps
CPU time 1.2 seconds
Started Apr 02 12:36:51 PM PDT 24
Finished Apr 02 12:36:55 PM PDT 24
Peak memory 200740 kb
Host smart-55d0eea0-ad43-4732-958c-c93fb4ee37f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671831677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3671831677
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3258542798
Short name T386
Test name
Test status
Simulation time 1893135771 ps
CPU time 7.39 seconds
Started Apr 02 12:36:54 PM PDT 24
Finished Apr 02 12:37:05 PM PDT 24
Peak memory 218540 kb
Host smart-0c8cd511-c810-4b31-8d11-ae490fb633a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258542798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3258542798
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1206584480
Short name T309
Test name
Test status
Simulation time 243912550 ps
CPU time 1.31 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 218040 kb
Host smart-93401dce-3521-4db4-b1ff-2b43bf948e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206584480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1206584480
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2434366561
Short name T278
Test name
Test status
Simulation time 185659242 ps
CPU time 0.94 seconds
Started Apr 02 12:36:54 PM PDT 24
Finished Apr 02 12:36:58 PM PDT 24
Peak memory 200624 kb
Host smart-f1c9ccde-3405-48f2-bdbb-ab7477a93aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434366561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2434366561
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3745485438
Short name T117
Test name
Test status
Simulation time 1494462504 ps
CPU time 6.11 seconds
Started Apr 02 12:36:59 PM PDT 24
Finished Apr 02 12:37:06 PM PDT 24
Peak memory 200872 kb
Host smart-a8964276-b27a-4677-b9d8-64562745d7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745485438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3745485438
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1303524955
Short name T185
Test name
Test status
Simulation time 164820239 ps
CPU time 1.21 seconds
Started Apr 02 12:36:57 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200640 kb
Host smart-d8d42dee-89ac-4c3d-be93-03a7809df114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303524955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1303524955
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2407921507
Short name T450
Test name
Test status
Simulation time 111240086 ps
CPU time 1.13 seconds
Started Apr 02 12:36:58 PM PDT 24
Finished Apr 02 12:37:00 PM PDT 24
Peak memory 200964 kb
Host smart-3c37b541-8a0e-4f03-bf0d-828516dbaa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407921507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2407921507
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1718140041
Short name T240
Test name
Test status
Simulation time 12178921544 ps
CPU time 40.83 seconds
Started Apr 02 12:36:55 PM PDT 24
Finished Apr 02 12:37:38 PM PDT 24
Peak memory 210868 kb
Host smart-539211c6-6564-417a-893b-6296214c015f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718140041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1718140041
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2682346425
Short name T224
Test name
Test status
Simulation time 485115421 ps
CPU time 2.63 seconds
Started Apr 02 12:36:55 PM PDT 24
Finished Apr 02 12:37:00 PM PDT 24
Peak memory 200860 kb
Host smart-5dc319c8-260b-4f8c-b876-0978c04ef4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682346425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2682346425
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1156994527
Short name T502
Test name
Test status
Simulation time 156397997 ps
CPU time 1.07 seconds
Started Apr 02 12:36:59 PM PDT 24
Finished Apr 02 12:37:01 PM PDT 24
Peak memory 200824 kb
Host smart-e6b0d3f7-1fd5-436e-9632-1d2a024e1f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156994527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1156994527
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2644817040
Short name T533
Test name
Test status
Simulation time 79368070 ps
CPU time 0.8 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:36:58 PM PDT 24
Peak memory 200712 kb
Host smart-3cd44651-b902-41dc-b145-707d73e2e1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644817040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2644817040
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2951590613
Short name T385
Test name
Test status
Simulation time 1220998903 ps
CPU time 5.82 seconds
Started Apr 02 12:36:54 PM PDT 24
Finished Apr 02 12:37:01 PM PDT 24
Peak memory 222624 kb
Host smart-36294329-a586-4b75-9ab1-becdf7d5121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951590613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2951590613
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4074850976
Short name T354
Test name
Test status
Simulation time 244540966 ps
CPU time 1.13 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 218000 kb
Host smart-ba725640-c506-40e8-962c-9faa08cd1b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074850976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4074850976
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2878834869
Short name T311
Test name
Test status
Simulation time 84406953 ps
CPU time 0.76 seconds
Started Apr 02 12:36:59 PM PDT 24
Finished Apr 02 12:37:00 PM PDT 24
Peak memory 200684 kb
Host smart-4c246fc9-a520-40d5-8c9a-ba31a769213e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878834869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2878834869
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3684243697
Short name T237
Test name
Test status
Simulation time 1644301657 ps
CPU time 5.97 seconds
Started Apr 02 12:36:59 PM PDT 24
Finished Apr 02 12:37:05 PM PDT 24
Peak memory 201012 kb
Host smart-12de5162-2bdb-4ca2-b0ec-33d318e21bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684243697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3684243697
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.977836839
Short name T267
Test name
Test status
Simulation time 141779721 ps
CPU time 1.12 seconds
Started Apr 02 12:36:57 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200640 kb
Host smart-0c2183e8-395d-41de-afbc-0a04ec65b0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977836839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.977836839
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.365461683
Short name T23
Test name
Test status
Simulation time 238822336 ps
CPU time 1.51 seconds
Started Apr 02 12:36:57 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200968 kb
Host smart-3768be5a-955c-456b-b10e-928afbad3288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365461683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.365461683
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1759815069
Short name T411
Test name
Test status
Simulation time 283822833 ps
CPU time 1.9 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:37:00 PM PDT 24
Peak memory 209076 kb
Host smart-fcd7697f-8508-41d9-9f44-4ba1fce6470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759815069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1759815069
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.4245039181
Short name T197
Test name
Test status
Simulation time 81362710 ps
CPU time 0.84 seconds
Started Apr 02 12:36:58 PM PDT 24
Finished Apr 02 12:37:00 PM PDT 24
Peak memory 200760 kb
Host smart-7539b74d-8230-40cb-aded-b09bd1a277d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245039181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.4245039181
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.286233441
Short name T79
Test name
Test status
Simulation time 70076713 ps
CPU time 0.76 seconds
Started Apr 02 12:36:57 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200660 kb
Host smart-2e9c1aba-27ba-45bb-b3dc-ead94885aa5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286233441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.286233441
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3236090570
Short name T26
Test name
Test status
Simulation time 1880720099 ps
CPU time 7.12 seconds
Started Apr 02 12:36:59 PM PDT 24
Finished Apr 02 12:37:07 PM PDT 24
Peak memory 217864 kb
Host smart-715aba78-e11b-4d10-9b8a-180d2c43d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236090570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3236090570
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.4029421076
Short name T8
Test name
Test status
Simulation time 244656748 ps
CPU time 1.07 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 217996 kb
Host smart-2d138e5e-f1e0-4484-bb20-345f80e19262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029421076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.4029421076
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3149999107
Short name T415
Test name
Test status
Simulation time 106607000 ps
CPU time 0.73 seconds
Started Apr 02 12:36:58 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200656 kb
Host smart-8b7c6db4-c37c-4d97-892c-0cb1f5c3db57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149999107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3149999107
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3399185397
Short name T213
Test name
Test status
Simulation time 1131924359 ps
CPU time 5.95 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:37:04 PM PDT 24
Peak memory 200932 kb
Host smart-c80cc254-e29e-49e7-aa6b-04a9763d8347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399185397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3399185397
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2697707414
Short name T211
Test name
Test status
Simulation time 182323916 ps
CPU time 1.24 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200820 kb
Host smart-7795fc91-22bf-4822-bdb1-5bac6bab0d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697707414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2697707414
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1009074148
Short name T122
Test name
Test status
Simulation time 259579095 ps
CPU time 1.59 seconds
Started Apr 02 12:36:55 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200904 kb
Host smart-aaa77498-2bf2-4614-a5bc-a01c6581b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009074148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1009074148
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.439747718
Short name T191
Test name
Test status
Simulation time 3232855765 ps
CPU time 14.49 seconds
Started Apr 02 12:36:57 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 209332 kb
Host smart-7c4e5dd9-68ed-432d-b691-07ffc1fdd7af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439747718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.439747718
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2693036804
Short name T178
Test name
Test status
Simulation time 495821633 ps
CPU time 2.55 seconds
Started Apr 02 12:36:55 PM PDT 24
Finished Apr 02 12:37:00 PM PDT 24
Peak memory 200852 kb
Host smart-1fa64632-cb02-4454-817c-4560e699572e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693036804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2693036804
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1387260114
Short name T183
Test name
Test status
Simulation time 208986943 ps
CPU time 1.23 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200692 kb
Host smart-a490ded5-1019-46dd-8428-53d68fe0080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387260114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1387260114
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.446773999
Short name T424
Test name
Test status
Simulation time 76325132 ps
CPU time 0.84 seconds
Started Apr 02 12:37:00 PM PDT 24
Finished Apr 02 12:37:02 PM PDT 24
Peak memory 200612 kb
Host smart-d6dd7224-310c-4f5e-b4c2-b77fdfe8861a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446773999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.446773999
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3850056209
Short name T48
Test name
Test status
Simulation time 2347834878 ps
CPU time 8.65 seconds
Started Apr 02 12:36:57 PM PDT 24
Finished Apr 02 12:37:07 PM PDT 24
Peak memory 222648 kb
Host smart-e97c20d2-5825-4a2b-84ad-30de3b466836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850056209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3850056209
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.4231334000
Short name T156
Test name
Test status
Simulation time 243569678 ps
CPU time 1.16 seconds
Started Apr 02 12:37:00 PM PDT 24
Finished Apr 02 12:37:02 PM PDT 24
Peak memory 218136 kb
Host smart-ef543d69-9468-42ee-a21a-a344b82d5387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231334000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.4231334000
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3692018153
Short name T346
Test name
Test status
Simulation time 1589509769 ps
CPU time 6.76 seconds
Started Apr 02 12:36:57 PM PDT 24
Finished Apr 02 12:37:05 PM PDT 24
Peak memory 200924 kb
Host smart-b2808cac-665e-4102-95f2-a9a2d80b3aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692018153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3692018153
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.819703550
Short name T422
Test name
Test status
Simulation time 169152054 ps
CPU time 1.26 seconds
Started Apr 02 12:37:00 PM PDT 24
Finished Apr 02 12:37:02 PM PDT 24
Peak memory 200820 kb
Host smart-4be63fec-e7a9-45ab-99f6-e09da2a5c39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819703550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.819703550
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1677128468
Short name T438
Test name
Test status
Simulation time 256649072 ps
CPU time 1.46 seconds
Started Apr 02 12:36:57 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200964 kb
Host smart-9e538890-e48d-4ffd-b259-adc6a5a1ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677128468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1677128468
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3546279845
Short name T208
Test name
Test status
Simulation time 2033052177 ps
CPU time 6.7 seconds
Started Apr 02 12:37:00 PM PDT 24
Finished Apr 02 12:37:07 PM PDT 24
Peak memory 201028 kb
Host smart-83854e7c-cf9f-42f4-a597-b2328b34730c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546279845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3546279845
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2089980099
Short name T492
Test name
Test status
Simulation time 149357468 ps
CPU time 1.82 seconds
Started Apr 02 12:36:58 PM PDT 24
Finished Apr 02 12:37:00 PM PDT 24
Peak memory 200788 kb
Host smart-e80a034c-df2b-4cf2-b788-6f1714eb7957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089980099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2089980099
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.899202884
Short name T329
Test name
Test status
Simulation time 127273858 ps
CPU time 1.11 seconds
Started Apr 02 12:37:01 PM PDT 24
Finished Apr 02 12:37:02 PM PDT 24
Peak memory 200796 kb
Host smart-a3527c1f-ded3-4703-ba52-1a25e94d16c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899202884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.899202884
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.47678051
Short name T187
Test name
Test status
Simulation time 67736750 ps
CPU time 0.79 seconds
Started Apr 02 12:37:04 PM PDT 24
Finished Apr 02 12:37:05 PM PDT 24
Peak memory 200508 kb
Host smart-9a97644b-08dc-49d8-97f1-8a53449b0c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47678051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.47678051
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2821113609
Short name T350
Test name
Test status
Simulation time 245285826 ps
CPU time 1.06 seconds
Started Apr 02 12:37:05 PM PDT 24
Finished Apr 02 12:37:06 PM PDT 24
Peak memory 218008 kb
Host smart-91a7da4b-cd76-4011-b0f2-7dd05988fcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821113609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2821113609
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.7719167
Short name T532
Test name
Test status
Simulation time 228067084 ps
CPU time 1.03 seconds
Started Apr 02 12:37:07 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200680 kb
Host smart-6f42ba76-9e66-43fb-96a4-a83dd2633f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7719167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.7719167
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1269081468
Short name T326
Test name
Test status
Simulation time 2220497445 ps
CPU time 8.24 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:46 PM PDT 24
Peak memory 201104 kb
Host smart-c141c849-4dac-489e-bee1-44356754241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269081468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1269081468
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2860979673
Short name T488
Test name
Test status
Simulation time 109980552 ps
CPU time 1.04 seconds
Started Apr 02 12:37:04 PM PDT 24
Finished Apr 02 12:37:06 PM PDT 24
Peak memory 200820 kb
Host smart-7f6f28e0-3097-42e8-9aa8-87a5ae5e9e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860979673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2860979673
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.175614756
Short name T120
Test name
Test status
Simulation time 256041695 ps
CPU time 1.72 seconds
Started Apr 02 12:37:05 PM PDT 24
Finished Apr 02 12:37:07 PM PDT 24
Peak memory 200952 kb
Host smart-aea32ecb-a35c-47fc-bbd2-54ac5b95cc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175614756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.175614756
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3157488813
Short name T260
Test name
Test status
Simulation time 1024840533 ps
CPU time 4.26 seconds
Started Apr 02 12:37:03 PM PDT 24
Finished Apr 02 12:37:07 PM PDT 24
Peak memory 200900 kb
Host smart-a75b6bfe-4242-44f6-8e7b-9a45ae5cfe50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157488813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3157488813
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1436676287
Short name T406
Test name
Test status
Simulation time 547375350 ps
CPU time 2.95 seconds
Started Apr 02 12:37:05 PM PDT 24
Finished Apr 02 12:37:08 PM PDT 24
Peak memory 200808 kb
Host smart-6d85f2c2-5b6f-418b-a4f4-a34d8dffad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436676287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1436676287
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4029269002
Short name T494
Test name
Test status
Simulation time 77999254 ps
CPU time 0.77 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200636 kb
Host smart-fe21febe-2d83-4912-a6e6-89d151dd388b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029269002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4029269002
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1753676815
Short name T42
Test name
Test status
Simulation time 1902583941 ps
CPU time 6.93 seconds
Started Apr 02 12:37:05 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 222472 kb
Host smart-53fe4ee0-0d91-484e-b35c-7ce866976c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753676815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1753676815
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.492245517
Short name T1
Test name
Test status
Simulation time 244493621 ps
CPU time 1.08 seconds
Started Apr 02 12:37:05 PM PDT 24
Finished Apr 02 12:37:06 PM PDT 24
Peak memory 218176 kb
Host smart-a6687012-2887-4b37-b049-5b7bbb89f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492245517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.492245517
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1954436373
Short name T467
Test name
Test status
Simulation time 216366176 ps
CPU time 0.91 seconds
Started Apr 02 12:37:02 PM PDT 24
Finished Apr 02 12:37:03 PM PDT 24
Peak memory 200588 kb
Host smart-c15d7ed0-e464-40d0-aef4-849a566e067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954436373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1954436373
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1450505475
Short name T484
Test name
Test status
Simulation time 1868878126 ps
CPU time 6.71 seconds
Started Apr 02 12:37:03 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200880 kb
Host smart-b5a648f7-72c6-4050-b105-d30c6a7438d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450505475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1450505475
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2633576721
Short name T238
Test name
Test status
Simulation time 101202547 ps
CPU time 0.98 seconds
Started Apr 02 12:37:02 PM PDT 24
Finished Apr 02 12:37:03 PM PDT 24
Peak memory 200812 kb
Host smart-0895b865-e359-459f-94a3-ce5f2d3d54c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633576721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2633576721
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1634504697
Short name T446
Test name
Test status
Simulation time 199240213 ps
CPU time 1.47 seconds
Started Apr 02 12:37:05 PM PDT 24
Finished Apr 02 12:37:07 PM PDT 24
Peak memory 200956 kb
Host smart-ab1d01ca-64c2-4d2f-97ad-a23a34234f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634504697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1634504697
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2640172912
Short name T82
Test name
Test status
Simulation time 8986928472 ps
CPU time 31.17 seconds
Started Apr 02 12:37:04 PM PDT 24
Finished Apr 02 12:37:35 PM PDT 24
Peak memory 201068 kb
Host smart-e8b37b90-3e8b-4ac6-9c52-d245228ca6ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640172912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2640172912
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.966257730
Short name T228
Test name
Test status
Simulation time 433664006 ps
CPU time 2.36 seconds
Started Apr 02 12:37:06 PM PDT 24
Finished Apr 02 12:37:11 PM PDT 24
Peak memory 209088 kb
Host smart-57780620-ec60-4fac-be16-1d0913fbcb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966257730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.966257730
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.4121360357
Short name T145
Test name
Test status
Simulation time 239484340 ps
CPU time 1.44 seconds
Started Apr 02 12:37:03 PM PDT 24
Finished Apr 02 12:37:05 PM PDT 24
Peak memory 201000 kb
Host smart-8f12419f-f980-450f-af19-6d6fd08ef520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121360357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.4121360357
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4067272479
Short name T344
Test name
Test status
Simulation time 72953566 ps
CPU time 0.78 seconds
Started Apr 02 12:37:08 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200708 kb
Host smart-59325c3a-2d81-4047-aa83-1d6453a87145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067272479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4067272479
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1118772874
Short name T61
Test name
Test status
Simulation time 1885760215 ps
CPU time 6.87 seconds
Started Apr 02 12:37:08 PM PDT 24
Finished Apr 02 12:37:16 PM PDT 24
Peak memory 218356 kb
Host smart-f46a76c3-30ab-429c-a662-7bf75a614993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118772874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1118772874
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.763591261
Short name T294
Test name
Test status
Simulation time 244698794 ps
CPU time 1.04 seconds
Started Apr 02 12:37:07 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 218220 kb
Host smart-3d60b1c6-58ab-4347-909c-8bdb1eda5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763591261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.763591261
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3816186710
Short name T256
Test name
Test status
Simulation time 204989217 ps
CPU time 0.98 seconds
Started Apr 02 12:37:07 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200720 kb
Host smart-c60873dd-1b5c-4e88-8271-b0bb23447ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816186710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3816186710
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3723297744
Short name T257
Test name
Test status
Simulation time 1006166915 ps
CPU time 5.02 seconds
Started Apr 02 12:37:13 PM PDT 24
Finished Apr 02 12:37:18 PM PDT 24
Peak memory 201008 kb
Host smart-8953d400-d929-427f-bac0-3c76afbf5679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723297744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3723297744
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3892143911
Short name T376
Test name
Test status
Simulation time 188150204 ps
CPU time 1.22 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:16 PM PDT 24
Peak memory 200756 kb
Host smart-4f7c0af4-97e9-4e76-b58a-4ab4c068b951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892143911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3892143911
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2342811805
Short name T384
Test name
Test status
Simulation time 251247593 ps
CPU time 1.48 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 200956 kb
Host smart-c8df0e2f-6b14-4288-bb10-349bdb1d52e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342811805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2342811805
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.215551847
Short name T56
Test name
Test status
Simulation time 3234272956 ps
CPU time 14.85 seconds
Started Apr 02 12:37:08 PM PDT 24
Finished Apr 02 12:37:24 PM PDT 24
Peak memory 210800 kb
Host smart-f1841d07-c2d7-44e9-8d17-dd8713c7e98e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215551847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.215551847
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.331245119
Short name T204
Test name
Test status
Simulation time 465066837 ps
CPU time 2.7 seconds
Started Apr 02 12:37:05 PM PDT 24
Finished Apr 02 12:37:08 PM PDT 24
Peak memory 208952 kb
Host smart-e31cf1b9-d221-4ded-a0e1-09a9659fb9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331245119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.331245119
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.857309167
Short name T14
Test name
Test status
Simulation time 200861092 ps
CPU time 1.38 seconds
Started Apr 02 12:37:08 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200832 kb
Host smart-3da74029-f61c-421f-bb9e-acc64dcc9a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857309167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.857309167
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2368377332
Short name T78
Test name
Test status
Simulation time 73104935 ps
CPU time 0.79 seconds
Started Apr 02 12:37:09 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200928 kb
Host smart-ad4524b9-3d9c-4731-a15f-7023c4c1bf1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368377332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2368377332
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2366323521
Short name T398
Test name
Test status
Simulation time 2186172005 ps
CPU time 7.92 seconds
Started Apr 02 12:37:11 PM PDT 24
Finished Apr 02 12:37:19 PM PDT 24
Peak memory 218516 kb
Host smart-6f5b3bcf-f7bf-45a8-b9c5-c373d15c3c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366323521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2366323521
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2080533187
Short name T155
Test name
Test status
Simulation time 244272859 ps
CPU time 1.18 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:15 PM PDT 24
Peak memory 218048 kb
Host smart-350d5424-4b14-4634-bb29-15f138e9d6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080533187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2080533187
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3977899308
Short name T345
Test name
Test status
Simulation time 236531345 ps
CPU time 0.91 seconds
Started Apr 02 12:37:06 PM PDT 24
Finished Apr 02 12:37:07 PM PDT 24
Peak memory 200676 kb
Host smart-964f385b-928a-43d1-aaff-bbb0ff5b1925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977899308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3977899308
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3222304859
Short name T365
Test name
Test status
Simulation time 1639927970 ps
CPU time 6.37 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:21 PM PDT 24
Peak memory 200932 kb
Host smart-c83918ef-8727-4e7f-acc1-bbf84cf8eb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222304859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3222304859
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2295650728
Short name T444
Test name
Test status
Simulation time 101356991 ps
CPU time 0.99 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:11 PM PDT 24
Peak memory 200780 kb
Host smart-50bc9fd4-3f1e-406e-9dc6-2b3c4ca698bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295650728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2295650728
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.213122484
Short name T315
Test name
Test status
Simulation time 125410010 ps
CPU time 1.29 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:11 PM PDT 24
Peak memory 200960 kb
Host smart-657010be-4b60-470a-b275-6e899648d5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213122484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.213122484
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.251072964
Short name T221
Test name
Test status
Simulation time 966783395 ps
CPU time 5.13 seconds
Started Apr 02 12:37:08 PM PDT 24
Finished Apr 02 12:37:14 PM PDT 24
Peak memory 201008 kb
Host smart-eaf031f6-c686-4329-a781-83c3f55e70f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251072964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.251072964
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1490423292
Short name T248
Test name
Test status
Simulation time 275573233 ps
CPU time 1.88 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:16 PM PDT 24
Peak memory 200804 kb
Host smart-f231862f-788c-4cbb-b791-50e47004041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490423292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1490423292
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1692834608
Short name T483
Test name
Test status
Simulation time 185289546 ps
CPU time 1.17 seconds
Started Apr 02 12:37:08 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200696 kb
Host smart-3e27e02b-8bb4-4ce3-a740-65607faeedc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692834608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1692834608
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1676381478
Short name T343
Test name
Test status
Simulation time 92416103 ps
CPU time 0.82 seconds
Started Apr 02 12:37:11 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 200684 kb
Host smart-1a4a3cef-66de-467a-9f82-1305f115fc4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676381478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1676381478
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3345867198
Short name T510
Test name
Test status
Simulation time 1236035795 ps
CPU time 6.05 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:16 PM PDT 24
Peak memory 218536 kb
Host smart-f8a3f91c-fa1a-4df4-84b4-f70948fbd187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345867198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3345867198
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.637007145
Short name T274
Test name
Test status
Simulation time 244700286 ps
CPU time 1.05 seconds
Started Apr 02 12:37:11 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 218108 kb
Host smart-0aa83c69-e499-4981-8bc3-6967748c140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637007145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.637007145
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3023421186
Short name T246
Test name
Test status
Simulation time 180280831 ps
CPU time 0.9 seconds
Started Apr 02 12:37:09 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200564 kb
Host smart-d073992e-ef3c-4400-8a2e-5480b4d232bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023421186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3023421186
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1335867792
Short name T516
Test name
Test status
Simulation time 784498765 ps
CPU time 4.54 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:14 PM PDT 24
Peak memory 200876 kb
Host smart-2081c8e0-f57f-4140-8083-05f4ca9f8115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335867792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1335867792
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1629469510
Short name T295
Test name
Test status
Simulation time 145868560 ps
CPU time 1.18 seconds
Started Apr 02 12:37:08 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200796 kb
Host smart-824594ad-dd4c-4794-b26b-67cd90b7f507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629469510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1629469510
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3881096653
Short name T262
Test name
Test status
Simulation time 120192489 ps
CPU time 1.22 seconds
Started Apr 02 12:37:15 PM PDT 24
Finished Apr 02 12:37:16 PM PDT 24
Peak memory 200928 kb
Host smart-fad351aa-b38a-4d67-b513-8f1ac50b7c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881096653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3881096653
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2336198595
Short name T223
Test name
Test status
Simulation time 2001296362 ps
CPU time 10.07 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 200908 kb
Host smart-d4859a7f-9dac-4cb7-b998-8f53d23d751b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336198595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2336198595
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3087262580
Short name T527
Test name
Test status
Simulation time 354580950 ps
CPU time 2.16 seconds
Started Apr 02 12:37:06 PM PDT 24
Finished Apr 02 12:37:08 PM PDT 24
Peak memory 200860 kb
Host smart-35291074-fc22-499e-9486-8975526d932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087262580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3087262580
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4178337103
Short name T470
Test name
Test status
Simulation time 134447066 ps
CPU time 1.01 seconds
Started Apr 02 12:37:09 PM PDT 24
Finished Apr 02 12:37:10 PM PDT 24
Peak memory 200732 kb
Host smart-dade5176-5681-44f9-916d-8c7a2dfcdb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178337103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4178337103
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2795946059
Short name T232
Test name
Test status
Simulation time 68945083 ps
CPU time 0.76 seconds
Started Apr 02 12:36:40 PM PDT 24
Finished Apr 02 12:36:41 PM PDT 24
Peak memory 200656 kb
Host smart-f5907441-3ae0-4b27-af64-5132aa642639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795946059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2795946059
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.575553368
Short name T184
Test name
Test status
Simulation time 243827903 ps
CPU time 1.06 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:36:40 PM PDT 24
Peak memory 218120 kb
Host smart-c78e144f-37b9-44f3-9179-a248f3fc95a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575553368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.575553368
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3298793065
Short name T413
Test name
Test status
Simulation time 190943560 ps
CPU time 0.97 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:36:42 PM PDT 24
Peak memory 200680 kb
Host smart-885f0fa1-134f-457c-9a89-31f65c41f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298793065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3298793065
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1510654994
Short name T103
Test name
Test status
Simulation time 1896929359 ps
CPU time 6.6 seconds
Started Apr 02 12:36:40 PM PDT 24
Finished Apr 02 12:36:47 PM PDT 24
Peak memory 200964 kb
Host smart-506d01c9-2fcc-497f-9aa1-b2ced50ac244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510654994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1510654994
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1346549436
Short name T74
Test name
Test status
Simulation time 16523869226 ps
CPU time 30.34 seconds
Started Apr 02 12:36:43 PM PDT 24
Finished Apr 02 12:37:14 PM PDT 24
Peak memory 217892 kb
Host smart-49bc6042-12ed-44ff-a1ed-955c9599c2f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346549436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1346549436
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1615104861
Short name T301
Test name
Test status
Simulation time 100523710 ps
CPU time 0.99 seconds
Started Apr 02 12:36:37 PM PDT 24
Finished Apr 02 12:36:38 PM PDT 24
Peak memory 200712 kb
Host smart-1e5b0a15-0001-4117-a972-33f9451b788d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615104861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1615104861
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.552115563
Short name T170
Test name
Test status
Simulation time 200736417 ps
CPU time 1.38 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:36:41 PM PDT 24
Peak memory 200908 kb
Host smart-1d334b50-2bda-410c-94d5-eb96575ef5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552115563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.552115563
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3999164967
Short name T463
Test name
Test status
Simulation time 3541471998 ps
CPU time 17.28 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:36:57 PM PDT 24
Peak memory 200984 kb
Host smart-95fd69da-84f6-4ab0-a6af-c06c2a33a8b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999164967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3999164967
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1539021193
Short name T327
Test name
Test status
Simulation time 117114021 ps
CPU time 1.41 seconds
Started Apr 02 12:36:38 PM PDT 24
Finished Apr 02 12:36:39 PM PDT 24
Peak memory 200884 kb
Host smart-c95c208b-28b6-4eda-b39e-9df9bcae8a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539021193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1539021193
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2128632095
Short name T322
Test name
Test status
Simulation time 136533372 ps
CPU time 1.12 seconds
Started Apr 02 12:36:42 PM PDT 24
Finished Apr 02 12:36:43 PM PDT 24
Peak memory 200824 kb
Host smart-f04d4c96-b412-453c-a4f9-b2ed3ce7c273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128632095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2128632095
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2410629340
Short name T6
Test name
Test status
Simulation time 75783319 ps
CPU time 0.76 seconds
Started Apr 02 12:37:11 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 200684 kb
Host smart-c7c1b774-c83f-46b1-be25-94aca23164bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410629340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2410629340
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1786291127
Short name T308
Test name
Test status
Simulation time 1900744625 ps
CPU time 6.93 seconds
Started Apr 02 12:37:12 PM PDT 24
Finished Apr 02 12:37:19 PM PDT 24
Peak memory 221944 kb
Host smart-925de4bb-5412-4053-8ea3-cd6e0ba9378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786291127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1786291127
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1997537614
Short name T166
Test name
Test status
Simulation time 243287855 ps
CPU time 1.09 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:11 PM PDT 24
Peak memory 218108 kb
Host smart-be52d814-fcbb-4429-bfd4-dd96cb996a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997537614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1997537614
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1546915770
Short name T318
Test name
Test status
Simulation time 186910293 ps
CPU time 0.87 seconds
Started Apr 02 12:37:13 PM PDT 24
Finished Apr 02 12:37:14 PM PDT 24
Peak memory 200644 kb
Host smart-afa617af-31db-4cc1-8acb-ae397b8816da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546915770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1546915770
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.48565512
Short name T460
Test name
Test status
Simulation time 971364046 ps
CPU time 5.38 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:16 PM PDT 24
Peak memory 200852 kb
Host smart-b3317297-4176-47f1-a229-6d0166a13cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48565512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.48565512
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3947887783
Short name T214
Test name
Test status
Simulation time 177083437 ps
CPU time 1.13 seconds
Started Apr 02 12:37:11 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 200700 kb
Host smart-c2a777c3-1136-421a-8481-f7ec1b491d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947887783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3947887783
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3230634398
Short name T530
Test name
Test status
Simulation time 117537210 ps
CPU time 1.14 seconds
Started Apr 02 12:37:13 PM PDT 24
Finished Apr 02 12:37:14 PM PDT 24
Peak memory 201000 kb
Host smart-3bbd42aa-5a71-41db-a7c5-4fc86d9adcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230634398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3230634398
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1091896088
Short name T218
Test name
Test status
Simulation time 3971860498 ps
CPU time 19.38 seconds
Started Apr 02 12:37:13 PM PDT 24
Finished Apr 02 12:37:33 PM PDT 24
Peak memory 201060 kb
Host smart-2d06de5b-100c-4b7b-ab31-9eb97ee819de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091896088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1091896088
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3687472144
Short name T154
Test name
Test status
Simulation time 134488292 ps
CPU time 1.73 seconds
Started Apr 02 12:37:11 PM PDT 24
Finished Apr 02 12:37:13 PM PDT 24
Peak memory 200776 kb
Host smart-a84f4f56-5f98-4017-955b-50e51a83cda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687472144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3687472144
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2177996265
Short name T131
Test name
Test status
Simulation time 112783884 ps
CPU time 0.96 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:15 PM PDT 24
Peak memory 200820 kb
Host smart-52abca06-a039-49d8-a750-ca2d67c2ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177996265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2177996265
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2334444331
Short name T383
Test name
Test status
Simulation time 64786107 ps
CPU time 0.75 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:15 PM PDT 24
Peak memory 200700 kb
Host smart-bfbc03fc-3931-43a9-bac8-9804eb873717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334444331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2334444331
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3908179074
Short name T35
Test name
Test status
Simulation time 1216632544 ps
CPU time 6.36 seconds
Started Apr 02 12:37:15 PM PDT 24
Finished Apr 02 12:37:22 PM PDT 24
Peak memory 222492 kb
Host smart-81a8cd3e-bd6a-4a19-a0be-42333c313c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908179074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3908179074
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2352386293
Short name T25
Test name
Test status
Simulation time 244663933 ps
CPU time 1.11 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:15 PM PDT 24
Peak memory 218256 kb
Host smart-44054396-3fd5-4d20-9466-956842b9f53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352386293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2352386293
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1014145196
Short name T245
Test name
Test status
Simulation time 192734147 ps
CPU time 0.86 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:11 PM PDT 24
Peak memory 200696 kb
Host smart-8e17ae36-3d37-4e7d-ad1d-c1fc1424026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014145196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1014145196
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.293084887
Short name T285
Test name
Test status
Simulation time 1746910222 ps
CPU time 6.44 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:21 PM PDT 24
Peak memory 201008 kb
Host smart-9cc2ff57-99bc-4672-98ee-e970acb2acc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293084887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.293084887
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4134441981
Short name T399
Test name
Test status
Simulation time 140233150 ps
CPU time 1.14 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:15 PM PDT 24
Peak memory 200812 kb
Host smart-7536748d-dac2-4ce7-a85e-db4ec68251d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134441981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4134441981
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3027603897
Short name T141
Test name
Test status
Simulation time 201522537 ps
CPU time 1.39 seconds
Started Apr 02 12:37:13 PM PDT 24
Finished Apr 02 12:37:15 PM PDT 24
Peak memory 200920 kb
Host smart-88623144-3472-433c-9d05-f660efd097a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027603897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3027603897
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1442736797
Short name T190
Test name
Test status
Simulation time 1296214008 ps
CPU time 5.74 seconds
Started Apr 02 12:37:12 PM PDT 24
Finished Apr 02 12:37:18 PM PDT 24
Peak memory 210168 kb
Host smart-544b4e3e-9898-4922-9cbc-b0a23da88c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442736797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1442736797
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3329370836
Short name T511
Test name
Test status
Simulation time 125529279 ps
CPU time 1.45 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 200784 kb
Host smart-227e9461-4e3a-4d05-8afc-cbb50ee61888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329370836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3329370836
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.793806963
Short name T142
Test name
Test status
Simulation time 94737419 ps
CPU time 0.87 seconds
Started Apr 02 12:37:10 PM PDT 24
Finished Apr 02 12:37:11 PM PDT 24
Peak memory 200768 kb
Host smart-1f732a0c-ef68-4c07-bee4-444bbb8c4ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793806963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.793806963
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.21627105
Short name T52
Test name
Test status
Simulation time 72735361 ps
CPU time 0.74 seconds
Started Apr 02 12:37:19 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 200628 kb
Host smart-b22d06fc-53ae-41e7-9e4a-d1161ea0e4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21627105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.21627105
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3864694225
Short name T360
Test name
Test status
Simulation time 1900625094 ps
CPU time 7.2 seconds
Started Apr 02 12:37:19 PM PDT 24
Finished Apr 02 12:37:27 PM PDT 24
Peak memory 222536 kb
Host smart-8dfc0789-4378-46f6-a9ef-a1c4fe4c60fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864694225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3864694225
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1539003511
Short name T235
Test name
Test status
Simulation time 244397995 ps
CPU time 1.06 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:19 PM PDT 24
Peak memory 218220 kb
Host smart-a8630dfa-78a1-4694-8ee0-57848e525a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539003511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1539003511
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4147855999
Short name T454
Test name
Test status
Simulation time 96031793 ps
CPU time 0.77 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:19 PM PDT 24
Peak memory 200692 kb
Host smart-71a8b5d9-9ebb-40a2-9249-efc73472f222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147855999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4147855999
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1798930150
Short name T352
Test name
Test status
Simulation time 1421794009 ps
CPU time 5.73 seconds
Started Apr 02 12:37:19 PM PDT 24
Finished Apr 02 12:37:25 PM PDT 24
Peak memory 200976 kb
Host smart-77ff7971-3ab2-46fb-b2b1-deabf97d894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798930150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1798930150
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3709603094
Short name T136
Test name
Test status
Simulation time 102731342 ps
CPU time 0.97 seconds
Started Apr 02 12:37:21 PM PDT 24
Finished Apr 02 12:37:22 PM PDT 24
Peak memory 200836 kb
Host smart-10348189-3b41-4a74-a3e4-f605622dbfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709603094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3709603094
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1914153145
Short name T456
Test name
Test status
Simulation time 190481629 ps
CPU time 1.39 seconds
Started Apr 02 12:37:16 PM PDT 24
Finished Apr 02 12:37:18 PM PDT 24
Peak memory 200964 kb
Host smart-93b35f1b-0472-4581-a486-721e03051f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914153145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1914153145
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3536233453
Short name T412
Test name
Test status
Simulation time 3650508404 ps
CPU time 16.7 seconds
Started Apr 02 12:37:20 PM PDT 24
Finished Apr 02 12:37:37 PM PDT 24
Peak memory 201124 kb
Host smart-db279fd9-48b8-42fd-9bb4-d255531c55d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536233453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3536233453
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3106507050
Short name T198
Test name
Test status
Simulation time 324000321 ps
CPU time 2.16 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 200828 kb
Host smart-0979f3ba-de95-4f11-a8bc-0461381763ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106507050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3106507050
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3947453183
Short name T374
Test name
Test status
Simulation time 218242447 ps
CPU time 1.31 seconds
Started Apr 02 12:37:19 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 200792 kb
Host smart-66992c8e-36d7-4e15-b48d-ea6af8e53867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947453183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3947453183
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1177423969
Short name T473
Test name
Test status
Simulation time 75646731 ps
CPU time 0.82 seconds
Started Apr 02 12:37:28 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 200648 kb
Host smart-5243bd0b-cfbd-449b-b4db-7a681a50521c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177423969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1177423969
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3913325085
Short name T28
Test name
Test status
Simulation time 2365760575 ps
CPU time 8.49 seconds
Started Apr 02 12:37:15 PM PDT 24
Finished Apr 02 12:37:24 PM PDT 24
Peak memory 218652 kb
Host smart-7a897eda-4dd4-4a71-b5df-d9be6cbe29db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913325085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3913325085
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4044611501
Short name T330
Test name
Test status
Simulation time 250198681 ps
CPU time 1.05 seconds
Started Apr 02 12:37:16 PM PDT 24
Finished Apr 02 12:37:17 PM PDT 24
Peak memory 218020 kb
Host smart-4e01b66e-1b54-4539-ab33-09074fca5155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044611501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4044611501
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3964793268
Short name T18
Test name
Test status
Simulation time 161483329 ps
CPU time 0.85 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:14 PM PDT 24
Peak memory 200648 kb
Host smart-34032b70-e944-45b3-a6d1-17c882e02000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964793268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3964793268
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1553839092
Short name T159
Test name
Test status
Simulation time 1007667421 ps
CPU time 5.07 seconds
Started Apr 02 12:37:15 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 201028 kb
Host smart-37e8191c-5e76-470b-b0a8-5fa275e860db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553839092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1553839092
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2924427739
Short name T263
Test name
Test status
Simulation time 187697516 ps
CPU time 1.25 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:15 PM PDT 24
Peak memory 200812 kb
Host smart-0f6de9fe-8e39-4719-b9d5-7153b9118748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924427739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2924427739
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2451655170
Short name T121
Test name
Test status
Simulation time 255364614 ps
CPU time 1.49 seconds
Started Apr 02 12:37:16 PM PDT 24
Finished Apr 02 12:37:18 PM PDT 24
Peak memory 200996 kb
Host smart-6bbbbc11-5401-4df0-9df9-83a0e95a0f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451655170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2451655170
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.507605601
Short name T99
Test name
Test status
Simulation time 2472433908 ps
CPU time 11.67 seconds
Started Apr 02 12:37:17 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 209260 kb
Host smart-b69347f4-d6ba-4fbc-bba0-18d042a78a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507605601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.507605601
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3772220977
Short name T133
Test name
Test status
Simulation time 124747075 ps
CPU time 1.6 seconds
Started Apr 02 12:37:14 PM PDT 24
Finished Apr 02 12:37:16 PM PDT 24
Peak memory 200772 kb
Host smart-027031f0-3330-4631-aa1f-abdaf528f0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772220977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3772220977
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2825605236
Short name T486
Test name
Test status
Simulation time 63233379 ps
CPU time 0.74 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:19 PM PDT 24
Peak memory 200768 kb
Host smart-a6be1234-c734-4bf9-9af2-d8eba8056a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825605236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2825605236
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3654320745
Short name T416
Test name
Test status
Simulation time 65531748 ps
CPU time 0.76 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:19 PM PDT 24
Peak memory 200664 kb
Host smart-7f795fad-788f-4a61-ab09-ca8f00d3e84e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654320745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3654320745
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2182693453
Short name T408
Test name
Test status
Simulation time 1888830905 ps
CPU time 7.83 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:26 PM PDT 24
Peak memory 222436 kb
Host smart-a643ca9a-e748-4166-9255-9e4dfa5c052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182693453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2182693453
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3390784162
Short name T264
Test name
Test status
Simulation time 244315065 ps
CPU time 1.09 seconds
Started Apr 02 12:37:20 PM PDT 24
Finished Apr 02 12:37:21 PM PDT 24
Peak memory 218148 kb
Host smart-1325907a-609a-432f-9ed5-f2815f9613f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390784162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3390784162
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3475916418
Short name T453
Test name
Test status
Simulation time 110355981 ps
CPU time 0.79 seconds
Started Apr 02 12:37:20 PM PDT 24
Finished Apr 02 12:37:21 PM PDT 24
Peak memory 200608 kb
Host smart-65f3721d-bdf9-41be-ac05-2f442db7d2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475916418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3475916418
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1186352369
Short name T282
Test name
Test status
Simulation time 1964537042 ps
CPU time 7.28 seconds
Started Apr 02 12:37:27 PM PDT 24
Finished Apr 02 12:37:34 PM PDT 24
Peak memory 201012 kb
Host smart-aed7e776-e881-4d61-9f8b-5d17e754d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186352369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1186352369
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3613724072
Short name T230
Test name
Test status
Simulation time 140250119 ps
CPU time 1.09 seconds
Started Apr 02 12:37:19 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 200700 kb
Host smart-878feda5-164e-4050-ab81-840a7f8aa2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613724072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3613724072
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3921796540
Short name T334
Test name
Test status
Simulation time 227359416 ps
CPU time 1.42 seconds
Started Apr 02 12:37:19 PM PDT 24
Finished Apr 02 12:37:21 PM PDT 24
Peak memory 200996 kb
Host smart-fa53e77e-6ba1-4748-a173-3a23fe44bc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921796540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3921796540
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3315506027
Short name T356
Test name
Test status
Simulation time 5273319223 ps
CPU time 18.11 seconds
Started Apr 02 12:37:21 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 210384 kb
Host smart-640431bd-d779-41f2-96f3-b4f252ddc6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315506027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3315506027
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2632244128
Short name T442
Test name
Test status
Simulation time 128324935 ps
CPU time 1.62 seconds
Started Apr 02 12:37:24 PM PDT 24
Finished Apr 02 12:37:26 PM PDT 24
Peak memory 209052 kb
Host smart-207fc556-a9c4-4101-9bfc-71bf08f907ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632244128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2632244128
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2977394838
Short name T126
Test name
Test status
Simulation time 82022746 ps
CPU time 0.84 seconds
Started Apr 02 12:37:21 PM PDT 24
Finished Apr 02 12:37:22 PM PDT 24
Peak memory 200760 kb
Host smart-e8d54ece-96b1-419d-a885-718670aae15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977394838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2977394838
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2148518015
Short name T5
Test name
Test status
Simulation time 78239806 ps
CPU time 0.86 seconds
Started Apr 02 12:37:20 PM PDT 24
Finished Apr 02 12:37:21 PM PDT 24
Peak memory 200700 kb
Host smart-49c41ce8-23a2-47ff-8171-67d03ca46c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148518015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2148518015
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2144125317
Short name T335
Test name
Test status
Simulation time 1228698439 ps
CPU time 5.34 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:23 PM PDT 24
Peak memory 222496 kb
Host smart-f81c4d2c-01ca-46b1-bf63-00b582915b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144125317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2144125317
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4179205876
Short name T165
Test name
Test status
Simulation time 244696384 ps
CPU time 1.13 seconds
Started Apr 02 12:37:21 PM PDT 24
Finished Apr 02 12:37:22 PM PDT 24
Peak memory 218152 kb
Host smart-b7acf330-7bf4-435f-875d-bf4246009472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179205876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4179205876
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1138900953
Short name T400
Test name
Test status
Simulation time 125358858 ps
CPU time 0.78 seconds
Started Apr 02 12:37:20 PM PDT 24
Finished Apr 02 12:37:21 PM PDT 24
Peak memory 200696 kb
Host smart-d8fb6af6-18ea-4d36-bb42-a1ac57314a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138900953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1138900953
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2642072600
Short name T351
Test name
Test status
Simulation time 832791685 ps
CPU time 4.15 seconds
Started Apr 02 12:37:22 PM PDT 24
Finished Apr 02 12:37:26 PM PDT 24
Peak memory 200944 kb
Host smart-a6c854d8-d814-4387-ade1-6d34f4625635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642072600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2642072600
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3763441018
Short name T80
Test name
Test status
Simulation time 142190593 ps
CPU time 1.13 seconds
Started Apr 02 12:37:21 PM PDT 24
Finished Apr 02 12:37:22 PM PDT 24
Peak memory 200792 kb
Host smart-fb44807a-f6fc-4768-bafd-3f07922992bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763441018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3763441018
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1649301303
Short name T358
Test name
Test status
Simulation time 120582714 ps
CPU time 1.22 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:19 PM PDT 24
Peak memory 200820 kb
Host smart-babf32f7-02ef-47f0-8cc1-f33bf0c3fa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649301303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1649301303
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.966318118
Short name T77
Test name
Test status
Simulation time 4491566408 ps
CPU time 20.3 seconds
Started Apr 02 12:37:20 PM PDT 24
Finished Apr 02 12:37:41 PM PDT 24
Peak memory 209316 kb
Host smart-cafd791c-f2d7-4e95-b6f9-9ec18e1b6ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966318118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.966318118
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.706798446
Short name T81
Test name
Test status
Simulation time 122705241 ps
CPU time 1.57 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 209100 kb
Host smart-1520b966-3910-4cc0-bf03-3c90e4d28da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706798446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.706798446
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3309444102
Short name T317
Test name
Test status
Simulation time 165406293 ps
CPU time 1.26 seconds
Started Apr 02 12:37:19 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 201032 kb
Host smart-21bf0814-217d-4eba-b4d8-2d4de309bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309444102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3309444102
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3214585885
Short name T369
Test name
Test status
Simulation time 74906140 ps
CPU time 0.79 seconds
Started Apr 02 12:37:24 PM PDT 24
Finished Apr 02 12:37:25 PM PDT 24
Peak memory 200608 kb
Host smart-6f4734ab-9320-43bd-8020-3d82c060115d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214585885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3214585885
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3919843629
Short name T359
Test name
Test status
Simulation time 2177382348 ps
CPU time 8.27 seconds
Started Apr 02 12:37:25 PM PDT 24
Finished Apr 02 12:37:34 PM PDT 24
Peak memory 217692 kb
Host smart-7ba17b6a-322d-4eaf-bdef-8b8a3fb61a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919843629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3919843629
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.992424019
Short name T270
Test name
Test status
Simulation time 244611187 ps
CPU time 1.09 seconds
Started Apr 02 12:37:27 PM PDT 24
Finished Apr 02 12:37:28 PM PDT 24
Peak memory 218168 kb
Host smart-be54dc59-3e5c-480b-b2a2-ef4ec5e2577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992424019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.992424019
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3836957281
Short name T17
Test name
Test status
Simulation time 102781527 ps
CPU time 0.75 seconds
Started Apr 02 12:37:20 PM PDT 24
Finished Apr 02 12:37:21 PM PDT 24
Peak memory 200672 kb
Host smart-670b1683-5d65-4725-bf10-30aaab4bf920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836957281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3836957281
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1093077951
Short name T168
Test name
Test status
Simulation time 949503752 ps
CPU time 4.84 seconds
Started Apr 02 12:37:27 PM PDT 24
Finished Apr 02 12:37:32 PM PDT 24
Peak memory 201012 kb
Host smart-268b3850-f2d5-42de-95ad-4ca6a0607c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093077951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1093077951
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1963390480
Short name T519
Test name
Test status
Simulation time 95948604 ps
CPU time 0.97 seconds
Started Apr 02 12:37:19 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 200824 kb
Host smart-4c28e9cf-f0b8-40be-b21e-309a35f85cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963390480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1963390480
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3538112473
Short name T380
Test name
Test status
Simulation time 119282721 ps
CPU time 1.23 seconds
Started Apr 02 12:37:21 PM PDT 24
Finished Apr 02 12:37:22 PM PDT 24
Peak memory 200960 kb
Host smart-ad9d301a-c5c7-44c2-abec-ecc0125c7dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538112473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3538112473
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3055695879
Short name T466
Test name
Test status
Simulation time 231579579 ps
CPU time 1.19 seconds
Started Apr 02 12:37:24 PM PDT 24
Finished Apr 02 12:37:25 PM PDT 24
Peak memory 200824 kb
Host smart-bc26e4c2-7bd5-4c91-b601-31ffc65edf4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055695879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3055695879
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2841441044
Short name T137
Test name
Test status
Simulation time 284871310 ps
CPU time 1.87 seconds
Started Apr 02 12:37:18 PM PDT 24
Finished Apr 02 12:37:20 PM PDT 24
Peak memory 200876 kb
Host smart-5550807e-af70-408d-aa72-80fc9988daff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841441044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2841441044
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2133390934
Short name T528
Test name
Test status
Simulation time 109954576 ps
CPU time 0.91 seconds
Started Apr 02 12:37:21 PM PDT 24
Finished Apr 02 12:37:22 PM PDT 24
Peak memory 200820 kb
Host smart-15bf8f04-d721-498d-b918-146a77e0f174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133390934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2133390934
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3571895277
Short name T476
Test name
Test status
Simulation time 74732837 ps
CPU time 0.81 seconds
Started Apr 02 12:37:25 PM PDT 24
Finished Apr 02 12:37:26 PM PDT 24
Peak memory 200572 kb
Host smart-3d19d57e-0cfa-4db2-ac6a-16f79c7a5198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571895277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3571895277
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2889712
Short name T379
Test name
Test status
Simulation time 1233339043 ps
CPU time 5.81 seconds
Started Apr 02 12:37:23 PM PDT 24
Finished Apr 02 12:37:28 PM PDT 24
Peak memory 218528 kb
Host smart-61e78508-2e69-46ba-aba6-578ef0593da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2889712
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2626755150
Short name T452
Test name
Test status
Simulation time 244035706 ps
CPU time 1.19 seconds
Started Apr 02 12:37:22 PM PDT 24
Finished Apr 02 12:37:23 PM PDT 24
Peak memory 218068 kb
Host smart-1b9f5911-3e31-46ea-8a89-a0cd57971950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626755150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2626755150
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2036155072
Short name T434
Test name
Test status
Simulation time 163248571 ps
CPU time 0.87 seconds
Started Apr 02 12:37:22 PM PDT 24
Finished Apr 02 12:37:23 PM PDT 24
Peak memory 200660 kb
Host smart-0f79386c-798d-48b4-841b-9e1a2a646579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036155072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2036155072
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1620399512
Short name T97
Test name
Test status
Simulation time 960866688 ps
CPU time 4.81 seconds
Started Apr 02 12:37:25 PM PDT 24
Finished Apr 02 12:37:30 PM PDT 24
Peak memory 201056 kb
Host smart-4d45ef1a-a2f9-42dd-8144-e92ccfae9bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620399512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1620399512
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1228979125
Short name T338
Test name
Test status
Simulation time 97233172 ps
CPU time 1.03 seconds
Started Apr 02 12:37:28 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 200836 kb
Host smart-64010dab-5ab9-485a-a957-d400d3d56208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228979125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1228979125
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.348862007
Short name T324
Test name
Test status
Simulation time 221610948 ps
CPU time 1.52 seconds
Started Apr 02 12:37:26 PM PDT 24
Finished Apr 02 12:37:28 PM PDT 24
Peak memory 200844 kb
Host smart-863a7a8a-cf90-41bb-b764-11e1b22028ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348862007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.348862007
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3723030591
Short name T279
Test name
Test status
Simulation time 6101919627 ps
CPU time 23.45 seconds
Started Apr 02 12:37:24 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 201028 kb
Host smart-4968e098-5e5f-4e34-a940-c844c152aa65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723030591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3723030591
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.405135072
Short name T508
Test name
Test status
Simulation time 171779200 ps
CPU time 1.34 seconds
Started Apr 02 12:37:23 PM PDT 24
Finished Apr 02 12:37:24 PM PDT 24
Peak memory 200932 kb
Host smart-44bd09ba-a5b8-4f7e-aebd-9b55fbcd1d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405135072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.405135072
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4048785729
Short name T513
Test name
Test status
Simulation time 72195025 ps
CPU time 0.78 seconds
Started Apr 02 12:37:30 PM PDT 24
Finished Apr 02 12:37:31 PM PDT 24
Peak memory 200692 kb
Host smart-80e4a91a-f231-4ce5-9921-316ebf51b078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048785729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4048785729
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3306934848
Short name T57
Test name
Test status
Simulation time 1220410232 ps
CPU time 6.21 seconds
Started Apr 02 12:37:24 PM PDT 24
Finished Apr 02 12:37:30 PM PDT 24
Peak memory 222468 kb
Host smart-8ede3238-464f-438b-b9e9-dc6b96123118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306934848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3306934848
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.273109835
Short name T37
Test name
Test status
Simulation time 243995945 ps
CPU time 1.06 seconds
Started Apr 02 12:37:27 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 218124 kb
Host smart-9bb20728-dfe6-44ca-9d53-47c18523eb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273109835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.273109835
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.7533129
Short name T536
Test name
Test status
Simulation time 183191031 ps
CPU time 0.89 seconds
Started Apr 02 12:37:26 PM PDT 24
Finished Apr 02 12:37:27 PM PDT 24
Peak memory 200688 kb
Host smart-d87a9241-1bfb-4590-a4db-6067d43f6d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7533129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.7533129
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1910805552
Short name T433
Test name
Test status
Simulation time 869238574 ps
CPU time 4.38 seconds
Started Apr 02 12:37:23 PM PDT 24
Finished Apr 02 12:37:27 PM PDT 24
Peak memory 200984 kb
Host smart-feb089fe-6b21-4821-99ba-e91fbe9f409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910805552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1910805552
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2940902951
Short name T402
Test name
Test status
Simulation time 101446171 ps
CPU time 1 seconds
Started Apr 02 12:37:32 PM PDT 24
Finished Apr 02 12:37:33 PM PDT 24
Peak memory 200764 kb
Host smart-8708073d-8931-4d5f-a607-ccb928074670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940902951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2940902951
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2745287920
Short name T255
Test name
Test status
Simulation time 229292078 ps
CPU time 1.58 seconds
Started Apr 02 12:37:22 PM PDT 24
Finished Apr 02 12:37:24 PM PDT 24
Peak memory 201036 kb
Host smart-16d91b0d-5a1b-44ba-bb74-aaebbd1f5a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745287920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2745287920
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3734668353
Short name T144
Test name
Test status
Simulation time 3111934591 ps
CPU time 11.34 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:50 PM PDT 24
Peak memory 201008 kb
Host smart-65f42dd2-3955-4ccd-9b4c-512b3b542cad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734668353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3734668353
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3338425182
Short name T287
Test name
Test status
Simulation time 321781288 ps
CPU time 1.96 seconds
Started Apr 02 12:37:24 PM PDT 24
Finished Apr 02 12:37:26 PM PDT 24
Peak memory 200788 kb
Host smart-2090b7c9-066c-424f-9fae-45dc6b2e94e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338425182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3338425182
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2770912781
Short name T217
Test name
Test status
Simulation time 163537673 ps
CPU time 1.22 seconds
Started Apr 02 12:37:27 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 200756 kb
Host smart-61264b3f-f88e-479b-81dd-1c5509e6cd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770912781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2770912781
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3404197843
Short name T449
Test name
Test status
Simulation time 66989503 ps
CPU time 0.76 seconds
Started Apr 02 12:37:30 PM PDT 24
Finished Apr 02 12:37:31 PM PDT 24
Peak memory 200668 kb
Host smart-02f03e1b-9bb7-4ad8-b80a-edf5e64a76dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404197843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3404197843
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1303956838
Short name T32
Test name
Test status
Simulation time 1218783224 ps
CPU time 5.37 seconds
Started Apr 02 12:37:26 PM PDT 24
Finished Apr 02 12:37:31 PM PDT 24
Peak memory 221904 kb
Host smart-4dc69788-8e5a-4e48-a8bd-46817b59803c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303956838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1303956838
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1206659908
Short name T313
Test name
Test status
Simulation time 243737967 ps
CPU time 1.13 seconds
Started Apr 02 12:37:31 PM PDT 24
Finished Apr 02 12:37:32 PM PDT 24
Peak memory 218000 kb
Host smart-77ff905b-7306-4f6a-b804-612820bcf392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206659908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1206659908
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1133243256
Short name T177
Test name
Test status
Simulation time 158731775 ps
CPU time 0.85 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200580 kb
Host smart-e316cbdc-90c9-45a7-b2d4-a071367d8ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133243256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1133243256
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1833586458
Short name T403
Test name
Test status
Simulation time 878450113 ps
CPU time 4.61 seconds
Started Apr 02 12:37:28 PM PDT 24
Finished Apr 02 12:37:33 PM PDT 24
Peak memory 200968 kb
Host smart-8b957dfe-d3dd-4edc-9638-b0382824a913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833586458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1833586458
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2715489196
Short name T11
Test name
Test status
Simulation time 99701067 ps
CPU time 0.98 seconds
Started Apr 02 12:37:26 PM PDT 24
Finished Apr 02 12:37:27 PM PDT 24
Peak memory 200816 kb
Host smart-2fb320fb-baf9-43ac-a849-57d7694be6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715489196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2715489196
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.994096372
Short name T216
Test name
Test status
Simulation time 253743912 ps
CPU time 1.45 seconds
Started Apr 02 12:37:31 PM PDT 24
Finished Apr 02 12:37:33 PM PDT 24
Peak memory 200944 kb
Host smart-d79ccf09-1eea-4529-894a-909f33f63afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994096372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.994096372
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3638390608
Short name T288
Test name
Test status
Simulation time 9126525397 ps
CPU time 33.61 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:38:03 PM PDT 24
Peak memory 209316 kb
Host smart-84ed6d83-daaa-4450-b054-56c709c7de82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638390608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3638390608
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.720654226
Short name T388
Test name
Test status
Simulation time 340456909 ps
CPU time 2.36 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:41 PM PDT 24
Peak memory 208964 kb
Host smart-079a90af-f9cf-46a7-833b-aaa3a44fd502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720654226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.720654226
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3798592859
Short name T428
Test name
Test status
Simulation time 76706475 ps
CPU time 0.8 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 200820 kb
Host smart-0f8f7860-aec5-413b-9929-c2fde2d91b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798592859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3798592859
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.712290553
Short name T529
Test name
Test status
Simulation time 70438450 ps
CPU time 0.77 seconds
Started Apr 02 12:36:46 PM PDT 24
Finished Apr 02 12:36:48 PM PDT 24
Peak memory 200644 kb
Host smart-eb615bb5-fafa-4e2d-aec9-460abd3210bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712290553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.712290553
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1761242262
Short name T418
Test name
Test status
Simulation time 1892625433 ps
CPU time 7.11 seconds
Started Apr 02 12:36:38 PM PDT 24
Finished Apr 02 12:36:46 PM PDT 24
Peak memory 217908 kb
Host smart-a7965c3b-f4f4-44ff-bc62-224dc0a74de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761242262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1761242262
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.934161609
Short name T147
Test name
Test status
Simulation time 244314817 ps
CPU time 1.16 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:55 PM PDT 24
Peak memory 218268 kb
Host smart-b9626ad7-de68-40df-a380-d07d439f0141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934161609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.934161609
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2745059735
Short name T254
Test name
Test status
Simulation time 121980690 ps
CPU time 0.79 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:51 PM PDT 24
Peak memory 200588 kb
Host smart-b491749f-1709-4a61-bfd0-38e77a2fa685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745059735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2745059735
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.59895724
Short name T509
Test name
Test status
Simulation time 1714168003 ps
CPU time 6.02 seconds
Started Apr 02 12:36:40 PM PDT 24
Finished Apr 02 12:36:47 PM PDT 24
Peak memory 200884 kb
Host smart-16a3cfb2-038d-4555-90c8-db6284a92429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59895724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.59895724
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1815983203
Short name T70
Test name
Test status
Simulation time 17404662154 ps
CPU time 24.76 seconds
Started Apr 02 12:36:45 PM PDT 24
Finished Apr 02 12:37:12 PM PDT 24
Peak memory 217744 kb
Host smart-247a8cac-d3ab-49c0-8749-6fcabbdcedbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815983203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1815983203
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.937638019
Short name T321
Test name
Test status
Simulation time 110196989 ps
CPU time 0.99 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:52 PM PDT 24
Peak memory 200720 kb
Host smart-62d2581e-ce1a-4282-aa34-080c08c93023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937638019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.937638019
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3438157141
Short name T210
Test name
Test status
Simulation time 234737819 ps
CPU time 1.49 seconds
Started Apr 02 12:36:43 PM PDT 24
Finished Apr 02 12:36:46 PM PDT 24
Peak memory 200952 kb
Host smart-32207e89-3772-47ad-8ce8-fae5ad3382b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438157141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3438157141
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.4227680338
Short name T348
Test name
Test status
Simulation time 179326083 ps
CPU time 1.16 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:36:41 PM PDT 24
Peak memory 200732 kb
Host smart-9118e718-6678-443c-90f3-70b48c920874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227680338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.4227680338
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3129808876
Short name T372
Test name
Test status
Simulation time 349536316 ps
CPU time 1.82 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:36:41 PM PDT 24
Peak memory 200884 kb
Host smart-90ffd740-d8f1-4a37-b441-b7098de79625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129808876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3129808876
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2974164332
Short name T283
Test name
Test status
Simulation time 139148404 ps
CPU time 1.16 seconds
Started Apr 02 12:36:39 PM PDT 24
Finished Apr 02 12:36:40 PM PDT 24
Peak memory 200800 kb
Host smart-6490e040-819f-49d6-8060-d8f2eeef1529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974164332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2974164332
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.36483108
Short name T239
Test name
Test status
Simulation time 74407285 ps
CPU time 0.79 seconds
Started Apr 02 12:37:28 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 200644 kb
Host smart-04d121c7-f1f1-496c-9422-7051c2447b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36483108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.36483108
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1992343791
Short name T59
Test name
Test status
Simulation time 1225491631 ps
CPU time 5.67 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:44 PM PDT 24
Peak memory 218528 kb
Host smart-2ba2d608-2d3d-442b-8f13-fefeb33d5862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992343791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1992343791
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.207286607
Short name T163
Test name
Test status
Simulation time 243523924 ps
CPU time 1.17 seconds
Started Apr 02 12:37:28 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 218004 kb
Host smart-7a36bfd7-a899-4d10-abcb-b7392c2625e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207286607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.207286607
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1257811109
Short name T479
Test name
Test status
Simulation time 125278389 ps
CPU time 0.84 seconds
Started Apr 02 12:37:30 PM PDT 24
Finished Apr 02 12:37:31 PM PDT 24
Peak memory 200680 kb
Host smart-1c06c6f5-8df4-45d3-b05d-e1da2529ce6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257811109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1257811109
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.513289491
Short name T390
Test name
Test status
Simulation time 911915777 ps
CPU time 4.53 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:37:34 PM PDT 24
Peak memory 201032 kb
Host smart-5690f0ff-0800-4ee3-bcfc-dae667199bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513289491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.513289491
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.633254786
Short name T396
Test name
Test status
Simulation time 111289833 ps
CPU time 0.99 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 200820 kb
Host smart-d12fc695-77be-49ee-a894-3d62c9fbd686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633254786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.633254786
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1145122574
Short name T475
Test name
Test status
Simulation time 121321873 ps
CPU time 1.3 seconds
Started Apr 02 12:37:27 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 200996 kb
Host smart-6e4dfe03-3ee6-4659-ab38-a6b192568d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145122574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1145122574
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2749472918
Short name T51
Test name
Test status
Simulation time 2361336885 ps
CPU time 11.42 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:51 PM PDT 24
Peak memory 201012 kb
Host smart-75aefcc3-7238-45f2-9278-f0e0195dbf32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749472918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2749472918
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2503470974
Short name T236
Test name
Test status
Simulation time 383365771 ps
CPU time 2.18 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200864 kb
Host smart-77a59b71-094a-4257-b1cd-d66872cf2a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503470974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2503470974
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3377397535
Short name T127
Test name
Test status
Simulation time 138414624 ps
CPU time 1.14 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200708 kb
Host smart-7317e080-4bb8-48b2-bd75-37fac18374c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377397535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3377397535
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1529708383
Short name T526
Test name
Test status
Simulation time 76161677 ps
CPU time 0.84 seconds
Started Apr 02 12:37:27 PM PDT 24
Finished Apr 02 12:37:28 PM PDT 24
Peak memory 200620 kb
Host smart-78d9d096-bad3-4b95-aef0-3a1b690e8f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529708383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1529708383
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1721905682
Short name T31
Test name
Test status
Simulation time 1224675237 ps
CPU time 5.21 seconds
Started Apr 02 12:37:30 PM PDT 24
Finished Apr 02 12:37:35 PM PDT 24
Peak memory 222160 kb
Host smart-e4c342a3-fbfc-4e82-8271-52d665bfcceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721905682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1721905682
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.783602633
Short name T225
Test name
Test status
Simulation time 248199594 ps
CPU time 1.03 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 218168 kb
Host smart-0cda0cf1-09ba-4051-882d-fe882ea26686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783602633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.783602633
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.231455333
Short name T407
Test name
Test status
Simulation time 189024823 ps
CPU time 0.85 seconds
Started Apr 02 12:37:32 PM PDT 24
Finished Apr 02 12:37:33 PM PDT 24
Peak memory 200492 kb
Host smart-ab69ae34-1a8b-4642-84b8-86f76e4ea9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231455333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.231455333
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3351267563
Short name T116
Test name
Test status
Simulation time 1771747510 ps
CPU time 6.45 seconds
Started Apr 02 12:37:32 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 200968 kb
Host smart-483ba369-c303-47aa-9a7d-9ad2eaeac6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351267563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3351267563
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.614092925
Short name T493
Test name
Test status
Simulation time 165541635 ps
CPU time 1.14 seconds
Started Apr 02 12:37:31 PM PDT 24
Finished Apr 02 12:37:32 PM PDT 24
Peak memory 200764 kb
Host smart-566f709b-88a2-4f0d-91f7-59060d67f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614092925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.614092925
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3409652488
Short name T118
Test name
Test status
Simulation time 264620852 ps
CPU time 1.51 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 200844 kb
Host smart-3f426283-5ea4-47d2-b5ad-8d2501916dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409652488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3409652488
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.944592078
Short name T231
Test name
Test status
Simulation time 6667336742 ps
CPU time 29.29 seconds
Started Apr 02 12:37:28 PM PDT 24
Finished Apr 02 12:37:57 PM PDT 24
Peak memory 201000 kb
Host smart-60aefc94-2071-471a-8f2f-49500434f5d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944592078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.944592078
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.546968117
Short name T472
Test name
Test status
Simulation time 256498253 ps
CPU time 1.72 seconds
Started Apr 02 12:37:30 PM PDT 24
Finished Apr 02 12:37:32 PM PDT 24
Peak memory 200880 kb
Host smart-3a6fec27-2b5c-4532-a244-b58ed3d974dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546968117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.546968117
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.471563840
Short name T203
Test name
Test status
Simulation time 71815061 ps
CPU time 0.74 seconds
Started Apr 02 12:37:28 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 200808 kb
Host smart-d2c74c7f-2ab8-4c94-a742-c86b68d5b577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471563840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.471563840
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2625420035
Short name T461
Test name
Test status
Simulation time 66581909 ps
CPU time 0.8 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:37:30 PM PDT 24
Peak memory 200644 kb
Host smart-912d4b85-2630-4708-be8d-f0aa3b39ea4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625420035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2625420035
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2531696566
Short name T387
Test name
Test status
Simulation time 2367125669 ps
CPU time 8.67 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:37:38 PM PDT 24
Peak memory 222588 kb
Host smart-da9637c6-2d1d-4e32-a694-57dd25802f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531696566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2531696566
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4141855784
Short name T404
Test name
Test status
Simulation time 243862761 ps
CPU time 1.11 seconds
Started Apr 02 12:37:32 PM PDT 24
Finished Apr 02 12:37:34 PM PDT 24
Peak memory 218032 kb
Host smart-70ee70d2-6321-4a02-a99d-38b66ce742e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141855784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4141855784
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1048564920
Short name T290
Test name
Test status
Simulation time 85493365 ps
CPU time 0.8 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:37:30 PM PDT 24
Peak memory 200608 kb
Host smart-e4aa1ad3-85eb-4d08-8ac5-ab3ffb496bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048564920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1048564920
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2308712358
Short name T426
Test name
Test status
Simulation time 1557789822 ps
CPU time 6.36 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:37:36 PM PDT 24
Peak memory 201012 kb
Host smart-814ee247-9360-40ee-87c1-802e556aa19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308712358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2308712358
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3340526300
Short name T275
Test name
Test status
Simulation time 152607981 ps
CPU time 1.13 seconds
Started Apr 02 12:37:28 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 200776 kb
Host smart-86ce1a53-7026-4d8a-979d-28e8e46042ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340526300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3340526300
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1472153651
Short name T339
Test name
Test status
Simulation time 190622615 ps
CPU time 1.34 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200892 kb
Host smart-b624ce52-b08b-48d2-a396-8aa7c8c66c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472153651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1472153651
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.464589851
Short name T115
Test name
Test status
Simulation time 17883663868 ps
CPU time 57 seconds
Started Apr 02 12:37:31 PM PDT 24
Finished Apr 02 12:38:28 PM PDT 24
Peak memory 201072 kb
Host smart-0555d565-74a8-4ace-ad6e-e17037f137d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464589851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.464589851
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1845103842
Short name T39
Test name
Test status
Simulation time 308988135 ps
CPU time 2.02 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:37:31 PM PDT 24
Peak memory 209008 kb
Host smart-a9dda56f-1cf8-47fe-80fd-6ffca505ff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845103842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1845103842
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2746797350
Short name T458
Test name
Test status
Simulation time 74610326 ps
CPU time 0.79 seconds
Started Apr 02 12:37:30 PM PDT 24
Finished Apr 02 12:37:31 PM PDT 24
Peak memory 200792 kb
Host smart-89db2e28-49f9-4cb5-bc43-a49025a151d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746797350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2746797350
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1993965911
Short name T171
Test name
Test status
Simulation time 54331580 ps
CPU time 0.79 seconds
Started Apr 02 12:37:35 PM PDT 24
Finished Apr 02 12:37:36 PM PDT 24
Peak memory 200608 kb
Host smart-182ccf21-24d4-4705-80f9-5328d8b4febb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993965911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1993965911
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.921557577
Short name T427
Test name
Test status
Simulation time 2352220335 ps
CPU time 8.22 seconds
Started Apr 02 12:37:31 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 218604 kb
Host smart-5e56bd3b-097a-4d98-819c-13ed8762d1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921557577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.921557577
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.4228763571
Short name T503
Test name
Test status
Simulation time 244357938 ps
CPU time 1.14 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 218112 kb
Host smart-7fa3731a-4d2e-4505-975c-6008539ea94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228763571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.4228763571
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1713168450
Short name T212
Test name
Test status
Simulation time 90495205 ps
CPU time 0.74 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:37:29 PM PDT 24
Peak memory 200920 kb
Host smart-ece772a4-360e-4b23-8e3f-37c421240fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713168450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1713168450
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.687486774
Short name T189
Test name
Test status
Simulation time 891702174 ps
CPU time 4.66 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:43 PM PDT 24
Peak memory 200996 kb
Host smart-51519336-57d9-4b9c-8ab1-f59e3413165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687486774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.687486774
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2190282070
Short name T273
Test name
Test status
Simulation time 97786652 ps
CPU time 1.03 seconds
Started Apr 02 12:37:34 PM PDT 24
Finished Apr 02 12:37:35 PM PDT 24
Peak memory 200828 kb
Host smart-2569568c-461b-4a60-9954-dccd43ff9e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190282070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2190282070
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2527485302
Short name T520
Test name
Test status
Simulation time 117324474 ps
CPU time 1.23 seconds
Started Apr 02 12:37:31 PM PDT 24
Finished Apr 02 12:37:32 PM PDT 24
Peak memory 200968 kb
Host smart-148389ca-8844-413f-ab98-8a55e8d2d9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527485302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2527485302
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1764170670
Short name T160
Test name
Test status
Simulation time 16297241214 ps
CPU time 57.76 seconds
Started Apr 02 12:37:31 PM PDT 24
Finished Apr 02 12:38:29 PM PDT 24
Peak memory 209136 kb
Host smart-4fac3f72-6dd8-4856-a8f3-cef01ea72a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764170670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1764170670
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.504562207
Short name T537
Test name
Test status
Simulation time 437870853 ps
CPU time 2.55 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:37:32 PM PDT 24
Peak memory 200784 kb
Host smart-38f78d0f-22ef-4a21-8faa-0c69bed3b30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504562207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.504562207
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.257908276
Short name T445
Test name
Test status
Simulation time 163247094 ps
CPU time 1.2 seconds
Started Apr 02 12:37:32 PM PDT 24
Finished Apr 02 12:37:34 PM PDT 24
Peak memory 200968 kb
Host smart-dacfcb3a-1d54-48b1-aa88-486138c6af4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257908276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.257908276
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2910941169
Short name T302
Test name
Test status
Simulation time 63701849 ps
CPU time 0.77 seconds
Started Apr 02 12:37:40 PM PDT 24
Finished Apr 02 12:37:41 PM PDT 24
Peak memory 200532 kb
Host smart-baf47653-6858-4d3d-a3d2-1772aee3fabf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910941169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2910941169
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1609742716
Short name T60
Test name
Test status
Simulation time 1901011673 ps
CPU time 7.03 seconds
Started Apr 02 12:37:30 PM PDT 24
Finished Apr 02 12:37:38 PM PDT 24
Peak memory 217996 kb
Host smart-a2147b29-ac07-482e-ba15-5e439901b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609742716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1609742716
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2979901666
Short name T420
Test name
Test status
Simulation time 246782917 ps
CPU time 1.02 seconds
Started Apr 02 12:37:33 PM PDT 24
Finished Apr 02 12:37:34 PM PDT 24
Peak memory 218352 kb
Host smart-a8dc52e3-81aa-4e33-808a-8cbf0c0ae29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979901666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2979901666
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1989373923
Short name T16
Test name
Test status
Simulation time 195286948 ps
CPU time 0.98 seconds
Started Apr 02 12:37:35 PM PDT 24
Finished Apr 02 12:37:37 PM PDT 24
Peak memory 200700 kb
Host smart-d19f9557-ecbc-457d-a12c-e8e1d14ef2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989373923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1989373923
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2495618781
Short name T134
Test name
Test status
Simulation time 1334073617 ps
CPU time 5.4 seconds
Started Apr 02 12:37:33 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 201004 kb
Host smart-22d06aa2-9342-44e6-a318-d05d76b5dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495618781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2495618781
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1675636073
Short name T226
Test name
Test status
Simulation time 108623541 ps
CPU time 1.01 seconds
Started Apr 02 12:37:32 PM PDT 24
Finished Apr 02 12:37:33 PM PDT 24
Peak memory 200816 kb
Host smart-aa94f551-0b7b-478e-abc0-55335833afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675636073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1675636073
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1967823106
Short name T474
Test name
Test status
Simulation time 199607221 ps
CPU time 1.51 seconds
Started Apr 02 12:37:34 PM PDT 24
Finished Apr 02 12:37:36 PM PDT 24
Peak memory 200920 kb
Host smart-cd7b3fa2-cc1f-4cfc-8b43-c445bf8eb027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967823106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1967823106
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3672475478
Short name T174
Test name
Test status
Simulation time 4840366264 ps
CPU time 20.71 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:59 PM PDT 24
Peak memory 209812 kb
Host smart-e840ae2d-93ee-4226-b8ae-c5a7481538cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672475478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3672475478
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2677538914
Short name T266
Test name
Test status
Simulation time 409411605 ps
CPU time 2.19 seconds
Started Apr 02 12:37:32 PM PDT 24
Finished Apr 02 12:37:35 PM PDT 24
Peak memory 200864 kb
Host smart-8f351378-a33d-4e34-a3bd-a4f2350e74e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677538914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2677538914
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1838783821
Short name T148
Test name
Test status
Simulation time 210330081 ps
CPU time 1.3 seconds
Started Apr 02 12:37:35 PM PDT 24
Finished Apr 02 12:37:37 PM PDT 24
Peak memory 200736 kb
Host smart-12a3f90e-b823-4d5b-a14d-3164181f3557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838783821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1838783821
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.983966910
Short name T368
Test name
Test status
Simulation time 79358288 ps
CPU time 0.85 seconds
Started Apr 02 12:37:36 PM PDT 24
Finished Apr 02 12:37:37 PM PDT 24
Peak memory 200716 kb
Host smart-359634fd-8620-4f2e-8983-f159f213569d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983966910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.983966910
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1922881577
Short name T336
Test name
Test status
Simulation time 1226364940 ps
CPU time 5.19 seconds
Started Apr 02 12:37:30 PM PDT 24
Finished Apr 02 12:37:35 PM PDT 24
Peak memory 222536 kb
Host smart-60ea2569-8767-404e-9900-8afbefe2d50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922881577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1922881577
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4241355549
Short name T487
Test name
Test status
Simulation time 244287708 ps
CPU time 1.13 seconds
Started Apr 02 12:37:29 PM PDT 24
Finished Apr 02 12:37:30 PM PDT 24
Peak memory 217992 kb
Host smart-ed92073c-6095-4aff-9906-36e29f57c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241355549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4241355549
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2612356233
Short name T188
Test name
Test status
Simulation time 174733293 ps
CPU time 0.92 seconds
Started Apr 02 12:37:33 PM PDT 24
Finished Apr 02 12:37:34 PM PDT 24
Peak memory 200676 kb
Host smart-4d83b3f1-c8a6-4984-974a-08f8c3750161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612356233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2612356233
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3522764897
Short name T75
Test name
Test status
Simulation time 2107213182 ps
CPU time 7.86 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 200844 kb
Host smart-20b0fc21-fcad-4385-8a42-76d323613ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522764897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3522764897
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3856254252
Short name T13
Test name
Test status
Simulation time 184273346 ps
CPU time 1.29 seconds
Started Apr 02 12:37:34 PM PDT 24
Finished Apr 02 12:37:35 PM PDT 24
Peak memory 200824 kb
Host smart-34ac3ae3-aa62-484a-a567-deeddb5b23a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856254252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3856254252
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.4190765416
Short name T357
Test name
Test status
Simulation time 230415106 ps
CPU time 1.39 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200840 kb
Host smart-17735b7d-d0f2-4fe6-868d-e535499f200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190765416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4190765416
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2217930735
Short name T276
Test name
Test status
Simulation time 106650801 ps
CPU time 1.43 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200748 kb
Host smart-95aa1152-88f2-4d78-89ee-572c5138ffc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217930735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2217930735
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2782379532
Short name T459
Test name
Test status
Simulation time 88995256 ps
CPU time 0.91 seconds
Started Apr 02 12:37:31 PM PDT 24
Finished Apr 02 12:37:32 PM PDT 24
Peak memory 200756 kb
Host smart-3410c421-d022-459e-b33b-0fc8579248a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782379532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2782379532
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.160410357
Short name T252
Test name
Test status
Simulation time 80915919 ps
CPU time 0.79 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 200688 kb
Host smart-937c88d0-547d-4525-9b61-fe6f9dcb5710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160410357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.160410357
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2354271672
Short name T58
Test name
Test status
Simulation time 1231035912 ps
CPU time 5.53 seconds
Started Apr 02 12:37:36 PM PDT 24
Finished Apr 02 12:37:42 PM PDT 24
Peak memory 218428 kb
Host smart-2df60a7b-718d-4a93-955e-9bdd130f23a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354271672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2354271672
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3231649712
Short name T158
Test name
Test status
Simulation time 243947698 ps
CPU time 1.08 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 218164 kb
Host smart-71d9a4c3-b5b5-4ad6-9f7a-1d07e72fae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231649712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3231649712
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.38290830
Short name T367
Test name
Test status
Simulation time 110033765 ps
CPU time 0.77 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 200684 kb
Host smart-4250817c-645f-4a7c-88b9-05089e5de971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38290830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.38290830
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3886195917
Short name T303
Test name
Test status
Simulation time 1113746174 ps
CPU time 5.66 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:54 PM PDT 24
Peak memory 200920 kb
Host smart-7ac8a198-93ac-44f6-a796-53d727f24760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886195917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3886195917
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3702486733
Short name T419
Test name
Test status
Simulation time 139942322 ps
CPU time 1.15 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200640 kb
Host smart-f69fc00f-ab82-4def-bdf2-a503f23dec52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702486733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3702486733
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4011226858
Short name T272
Test name
Test status
Simulation time 246235783 ps
CPU time 1.62 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:41 PM PDT 24
Peak memory 201016 kb
Host smart-4c7db165-5edd-4f53-8acb-fd3c4f7200e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011226858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4011226858
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3475902613
Short name T378
Test name
Test status
Simulation time 6928206180 ps
CPU time 30.81 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:38:08 PM PDT 24
Peak memory 201096 kb
Host smart-15305e51-d3aa-4f26-8353-aa6c4ada4177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475902613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3475902613
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3087805319
Short name T53
Test name
Test status
Simulation time 334609482 ps
CPU time 2.22 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:42 PM PDT 24
Peak memory 209016 kb
Host smart-bc0d215d-ea03-4176-b9ba-7779ac6a1473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087805319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3087805319
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.571450274
Short name T259
Test name
Test status
Simulation time 193706304 ps
CPU time 1.25 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:51 PM PDT 24
Peak memory 200764 kb
Host smart-1729c6d0-50a0-4432-baef-26e465274cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571450274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.571450274
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2297482370
Short name T421
Test name
Test status
Simulation time 53072863 ps
CPU time 0.71 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200636 kb
Host smart-c6e61647-71e4-4c96-b18b-19df650ef9da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297482370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2297482370
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1102341595
Short name T490
Test name
Test status
Simulation time 2373127395 ps
CPU time 8.31 seconds
Started Apr 02 12:37:36 PM PDT 24
Finished Apr 02 12:37:44 PM PDT 24
Peak memory 217844 kb
Host smart-00cc2347-2355-4f8b-bf82-cbf54bf0d443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102341595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1102341595
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3859498153
Short name T152
Test name
Test status
Simulation time 244284235 ps
CPU time 1.1 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:51 PM PDT 24
Peak memory 218100 kb
Host smart-efcf70b6-3d3c-4bde-8d85-182beacb2970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859498153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3859498153
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1889857645
Short name T19
Test name
Test status
Simulation time 152273874 ps
CPU time 0.84 seconds
Started Apr 02 12:37:35 PM PDT 24
Finished Apr 02 12:37:36 PM PDT 24
Peak memory 200580 kb
Host smart-fa4ecd41-dcab-4eb7-851a-474b14ac45b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889857645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1889857645
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3730384904
Short name T250
Test name
Test status
Simulation time 1413459340 ps
CPU time 5.78 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:56 PM PDT 24
Peak memory 200948 kb
Host smart-35861002-cd3d-4116-928c-208a1a7fdefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730384904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3730384904
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1108273435
Short name T377
Test name
Test status
Simulation time 154613407 ps
CPU time 1.11 seconds
Started Apr 02 12:37:35 PM PDT 24
Finished Apr 02 12:37:37 PM PDT 24
Peak memory 200792 kb
Host smart-c1a49a4c-580d-4d63-bd56-890036d0add4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108273435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1108273435
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3967467508
Short name T209
Test name
Test status
Simulation time 113444206 ps
CPU time 1.23 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 200956 kb
Host smart-87bad4ab-2b47-4720-b9dd-3dc07dff13f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967467508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3967467508
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3686642149
Short name T36
Test name
Test status
Simulation time 7106846360 ps
CPU time 31.19 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:38:11 PM PDT 24
Peak memory 201064 kb
Host smart-290e8f01-9268-4b5c-b29a-9a4c0f452b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686642149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3686642149
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2523746198
Short name T436
Test name
Test status
Simulation time 158204936 ps
CPU time 1.8 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:50 PM PDT 24
Peak memory 209016 kb
Host smart-4110f268-c218-4f45-be32-e8fd67ce91e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523746198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2523746198
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.226269933
Short name T297
Test name
Test status
Simulation time 76040710 ps
CPU time 0.82 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:38 PM PDT 24
Peak memory 200788 kb
Host smart-429e979e-e3b0-4a64-bfd3-7da74b149bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226269933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.226269933
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2092173741
Short name T316
Test name
Test status
Simulation time 63107500 ps
CPU time 0.76 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:38 PM PDT 24
Peak memory 200652 kb
Host smart-58dc295f-3b67-448a-b021-79418f1e72d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092173741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2092173741
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2835290758
Short name T430
Test name
Test status
Simulation time 1226287378 ps
CPU time 6.2 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:56 PM PDT 24
Peak memory 222560 kb
Host smart-2ccdbc75-2576-431a-bf23-8fc2207d4551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835290758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2835290758
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.512523041
Short name T349
Test name
Test status
Simulation time 243953957 ps
CPU time 1.07 seconds
Started Apr 02 12:37:36 PM PDT 24
Finished Apr 02 12:37:37 PM PDT 24
Peak memory 218104 kb
Host smart-d889c00d-5077-479f-b889-143fb30254df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512523041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.512523041
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2700670081
Short name T498
Test name
Test status
Simulation time 156903691 ps
CPU time 0.85 seconds
Started Apr 02 12:37:35 PM PDT 24
Finished Apr 02 12:37:36 PM PDT 24
Peak memory 200668 kb
Host smart-f8d47b34-1106-451c-8ada-98b4a2cede5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700670081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2700670081
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3126262579
Short name T153
Test name
Test status
Simulation time 904240913 ps
CPU time 4.57 seconds
Started Apr 02 12:37:41 PM PDT 24
Finished Apr 02 12:37:45 PM PDT 24
Peak memory 200844 kb
Host smart-4d2a3a3e-c46f-4b37-80ce-beaa3048e846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126262579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3126262579
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1009261831
Short name T485
Test name
Test status
Simulation time 153160767 ps
CPU time 1.14 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:38 PM PDT 24
Peak memory 200828 kb
Host smart-804b17ab-8de2-4c2b-813c-1558877fcdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009261831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1009261831
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2012675144
Short name T331
Test name
Test status
Simulation time 118205849 ps
CPU time 1.17 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 201008 kb
Host smart-7c19022f-c31d-42a3-a2c4-4c97290873de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012675144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2012675144
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2472172440
Short name T268
Test name
Test status
Simulation time 295539894 ps
CPU time 1.51 seconds
Started Apr 02 12:37:40 PM PDT 24
Finished Apr 02 12:37:42 PM PDT 24
Peak memory 200708 kb
Host smart-a163a8f2-5234-466a-8173-9a8e7796f729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472172440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2472172440
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2083846315
Short name T496
Test name
Test status
Simulation time 313371251 ps
CPU time 1.99 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 209096 kb
Host smart-0d4baa88-d979-4d35-a79e-23c3aee14224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083846315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2083846315
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3009608880
Short name T176
Test name
Test status
Simulation time 84076001 ps
CPU time 0.9 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200812 kb
Host smart-7b53ad82-038d-4bf1-9d60-f1fb20fc9558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009608880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3009608880
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1950325232
Short name T261
Test name
Test status
Simulation time 65285295 ps
CPU time 0.73 seconds
Started Apr 02 12:37:40 PM PDT 24
Finished Apr 02 12:37:41 PM PDT 24
Peak memory 200696 kb
Host smart-01ba7918-f7f2-4759-9056-499441cbdea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950325232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1950325232
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.473490965
Short name T27
Test name
Test status
Simulation time 1906927074 ps
CPU time 7.91 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:45 PM PDT 24
Peak memory 217848 kb
Host smart-0b5d1166-99ac-4584-9b95-63a5af10c89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473490965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.473490965
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1181616512
Short name T286
Test name
Test status
Simulation time 244614138 ps
CPU time 1 seconds
Started Apr 02 12:37:33 PM PDT 24
Finished Apr 02 12:37:34 PM PDT 24
Peak memory 218100 kb
Host smart-b27b3ffd-a6b8-4b0e-aba6-47cf6251c82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181616512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1181616512
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.569861244
Short name T337
Test name
Test status
Simulation time 149496441 ps
CPU time 0.79 seconds
Started Apr 02 12:37:36 PM PDT 24
Finished Apr 02 12:37:37 PM PDT 24
Peak memory 200664 kb
Host smart-c9849b5c-94ea-46a5-ba82-1bad44e12f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569861244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.569861244
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.4193979169
Short name T531
Test name
Test status
Simulation time 814697061 ps
CPU time 4.01 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:42 PM PDT 24
Peak memory 201012 kb
Host smart-5a3f2bf2-4847-4b56-bd8d-1c26c8c13ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193979169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.4193979169
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.993273299
Short name T465
Test name
Test status
Simulation time 172320947 ps
CPU time 1.18 seconds
Started Apr 02 12:37:35 PM PDT 24
Finished Apr 02 12:37:37 PM PDT 24
Peak memory 200760 kb
Host smart-cfa56530-3d66-4611-8269-8eecb200d1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993273299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.993273299
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3968433076
Short name T132
Test name
Test status
Simulation time 201447642 ps
CPU time 1.31 seconds
Started Apr 02 12:37:36 PM PDT 24
Finished Apr 02 12:37:38 PM PDT 24
Peak memory 200992 kb
Host smart-b778e7eb-1523-483d-8df9-78649e7dc21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968433076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3968433076
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.499110601
Short name T206
Test name
Test status
Simulation time 150495109 ps
CPU time 1.03 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200644 kb
Host smart-f83ac0bd-7372-4b98-a6eb-92af40f40542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499110601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.499110601
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1887980354
Short name T512
Test name
Test status
Simulation time 147790358 ps
CPU time 1.84 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200900 kb
Host smart-6c9b67db-4088-40a7-b472-796fc380a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887980354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1887980354
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3555844125
Short name T277
Test name
Test status
Simulation time 100371876 ps
CPU time 0.97 seconds
Started Apr 02 12:37:35 PM PDT 24
Finished Apr 02 12:37:37 PM PDT 24
Peak memory 200760 kb
Host smart-da50aba4-ea39-4ad6-b184-2aa933784adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555844125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3555844125
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3527751555
Short name T307
Test name
Test status
Simulation time 76204017 ps
CPU time 0.83 seconds
Started Apr 02 12:36:44 PM PDT 24
Finished Apr 02 12:36:46 PM PDT 24
Peak memory 200604 kb
Host smart-9de965a2-f103-4d42-adfd-474519ac80d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527751555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3527751555
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4275978887
Short name T323
Test name
Test status
Simulation time 243624281 ps
CPU time 1.12 seconds
Started Apr 02 12:36:43 PM PDT 24
Finished Apr 02 12:36:45 PM PDT 24
Peak memory 218068 kb
Host smart-81e7d37b-d6e3-430f-b2b2-c4321650a4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275978887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4275978887
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1684324420
Short name T179
Test name
Test status
Simulation time 81749273 ps
CPU time 0.72 seconds
Started Apr 02 12:36:43 PM PDT 24
Finished Apr 02 12:36:45 PM PDT 24
Peak memory 200544 kb
Host smart-7c25b121-6a57-465c-a53a-c28b58fc94b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684324420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1684324420
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.639856317
Short name T114
Test name
Test status
Simulation time 2034000326 ps
CPU time 7.32 seconds
Started Apr 02 12:36:45 PM PDT 24
Finished Apr 02 12:36:55 PM PDT 24
Peak memory 200868 kb
Host smart-babc93d1-6235-41c0-8e9d-63131ed3e8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639856317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.639856317
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4152314096
Short name T73
Test name
Test status
Simulation time 16522412669 ps
CPU time 28.44 seconds
Started Apr 02 12:36:43 PM PDT 24
Finished Apr 02 12:37:13 PM PDT 24
Peak memory 218908 kb
Host smart-c77c92a3-583a-4db5-84ea-f4b031ab22e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152314096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4152314096
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3917202108
Short name T161
Test name
Test status
Simulation time 154111777 ps
CPU time 1.08 seconds
Started Apr 02 12:36:43 PM PDT 24
Finished Apr 02 12:36:45 PM PDT 24
Peak memory 200724 kb
Host smart-472cb764-6c15-41b7-965c-5920b1d1bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917202108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3917202108
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1762574917
Short name T193
Test name
Test status
Simulation time 245897839 ps
CPU time 1.45 seconds
Started Apr 02 12:36:46 PM PDT 24
Finished Apr 02 12:36:49 PM PDT 24
Peak memory 201020 kb
Host smart-acb91f90-6ba1-4c3d-963a-a32db0633403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762574917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1762574917
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3826629456
Short name T393
Test name
Test status
Simulation time 6537949693 ps
CPU time 29.96 seconds
Started Apr 02 12:36:42 PM PDT 24
Finished Apr 02 12:37:14 PM PDT 24
Peak memory 201204 kb
Host smart-29443ebe-2f87-444a-b5c6-3d0f8d0b2081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826629456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3826629456
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1137158265
Short name T437
Test name
Test status
Simulation time 136275040 ps
CPU time 1.69 seconds
Started Apr 02 12:36:42 PM PDT 24
Finished Apr 02 12:36:44 PM PDT 24
Peak memory 208952 kb
Host smart-c8d4775e-9798-4fc7-afc5-ddd826be6801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137158265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1137158265
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.949947033
Short name T258
Test name
Test status
Simulation time 131781574 ps
CPU time 1.15 seconds
Started Apr 02 12:36:45 PM PDT 24
Finished Apr 02 12:36:49 PM PDT 24
Peak memory 200848 kb
Host smart-4ea35166-7401-44f1-80ca-1c8d772aafff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949947033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.949947033
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3923359232
Short name T425
Test name
Test status
Simulation time 57574985 ps
CPU time 0.74 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 200700 kb
Host smart-445fd29e-d3ef-4ddd-a2df-97686b5653d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923359232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3923359232
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4253708145
Short name T477
Test name
Test status
Simulation time 1228460608 ps
CPU time 5.95 seconds
Started Apr 02 12:37:40 PM PDT 24
Finished Apr 02 12:37:46 PM PDT 24
Peak memory 218544 kb
Host smart-5082db1b-c672-40ba-af94-aa7a5520b183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253708145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4253708145
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3264816505
Short name T299
Test name
Test status
Simulation time 246315507 ps
CPU time 1.02 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 218016 kb
Host smart-39ae9034-4de1-46d8-b6c5-1ab020f385af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264816505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3264816505
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.288959679
Short name T328
Test name
Test status
Simulation time 115701645 ps
CPU time 0.81 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200684 kb
Host smart-c139a522-ac06-4f4d-adff-bdd7bec6c0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288959679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.288959679
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.917844186
Short name T101
Test name
Test status
Simulation time 991999860 ps
CPU time 4.93 seconds
Started Apr 02 12:37:41 PM PDT 24
Finished Apr 02 12:37:46 PM PDT 24
Peak memory 200940 kb
Host smart-0b971f3b-3ecf-4ca2-a366-1e0acf622ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917844186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.917844186
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1487749592
Short name T366
Test name
Test status
Simulation time 144745279 ps
CPU time 1.07 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200832 kb
Host smart-9b84f290-5650-4f15-b2d8-efb3f047dcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487749592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1487749592
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.738592553
Short name T151
Test name
Test status
Simulation time 196287648 ps
CPU time 1.41 seconds
Started Apr 02 12:37:40 PM PDT 24
Finished Apr 02 12:37:42 PM PDT 24
Peak memory 201040 kb
Host smart-7d7a5149-a604-4222-b666-8cfb6716e23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738592553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.738592553
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1508087995
Short name T363
Test name
Test status
Simulation time 10963460854 ps
CPU time 38.24 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:38:28 PM PDT 24
Peak memory 209300 kb
Host smart-8e43d57e-2f8b-4cdb-b6ac-4dd717499ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508087995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1508087995
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.341205674
Short name T394
Test name
Test status
Simulation time 158032715 ps
CPU time 2.03 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200868 kb
Host smart-f34c8ec4-52ee-4fa4-bcdb-a77e8fefe983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341205674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.341205674
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3647264808
Short name T143
Test name
Test status
Simulation time 93320317 ps
CPU time 0.92 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200844 kb
Host smart-fba3cf5e-3f90-4b68-8e07-2f2f553b6960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647264808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3647264808
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2322511435
Short name T150
Test name
Test status
Simulation time 104245192 ps
CPU time 0.86 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:37:48 PM PDT 24
Peak memory 200688 kb
Host smart-5533daea-4bd3-4f41-a691-3ec2ab7c2221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322511435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2322511435
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2369651354
Short name T332
Test name
Test status
Simulation time 1230417638 ps
CPU time 5.55 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:45 PM PDT 24
Peak memory 218544 kb
Host smart-a59b677c-4437-497d-8cb0-b44f4c76e421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369651354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2369651354
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.862844497
Short name T291
Test name
Test status
Simulation time 244989816 ps
CPU time 1.05 seconds
Started Apr 02 12:37:42 PM PDT 24
Finished Apr 02 12:37:43 PM PDT 24
Peak memory 217912 kb
Host smart-6676fdd4-6283-4ae5-90d2-ae2631c404d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862844497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.862844497
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2176302477
Short name T395
Test name
Test status
Simulation time 169398397 ps
CPU time 0.85 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:40 PM PDT 24
Peak memory 200704 kb
Host smart-da698db6-ad12-4206-8bea-dd97ad331c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176302477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2176302477
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2002971068
Short name T172
Test name
Test status
Simulation time 853786519 ps
CPU time 4.29 seconds
Started Apr 02 12:37:44 PM PDT 24
Finished Apr 02 12:37:48 PM PDT 24
Peak memory 201012 kb
Host smart-15b5e762-5e66-499e-8216-64c9f3a3359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002971068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2002971068
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3300249481
Short name T271
Test name
Test status
Simulation time 155118645 ps
CPU time 1.17 seconds
Started Apr 02 12:37:40 PM PDT 24
Finished Apr 02 12:37:42 PM PDT 24
Peak memory 200740 kb
Host smart-8001a169-9a29-4795-b7aa-e42e72e73e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300249481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3300249481
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3355657309
Short name T175
Test name
Test status
Simulation time 256115801 ps
CPU time 1.44 seconds
Started Apr 02 12:37:39 PM PDT 24
Finished Apr 02 12:37:41 PM PDT 24
Peak memory 200996 kb
Host smart-d015f623-d008-4afd-b406-a49bc4849991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355657309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3355657309
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4178273205
Short name T375
Test name
Test status
Simulation time 13891055851 ps
CPU time 51.12 seconds
Started Apr 02 12:37:43 PM PDT 24
Finished Apr 02 12:38:35 PM PDT 24
Peak memory 201016 kb
Host smart-15aa42b3-ad25-47f6-ad40-20f1a699aaba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178273205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4178273205
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2200833631
Short name T140
Test name
Test status
Simulation time 143407816 ps
CPU time 1.91 seconds
Started Apr 02 12:37:37 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 200744 kb
Host smart-287da803-f185-4ab5-883b-43a60c7e821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200833631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2200833631
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2458417030
Short name T523
Test name
Test status
Simulation time 108566720 ps
CPU time 0.94 seconds
Started Apr 02 12:37:38 PM PDT 24
Finished Apr 02 12:37:39 PM PDT 24
Peak memory 200808 kb
Host smart-014b0a8d-1225-4a75-95a8-24d0778bfb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458417030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2458417030
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1476157701
Short name T373
Test name
Test status
Simulation time 84240621 ps
CPU time 0.83 seconds
Started Apr 02 12:37:46 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 200732 kb
Host smart-4405fee4-ccca-4df3-b7b4-0d4f3d40d8a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476157701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1476157701
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.4116364554
Short name T517
Test name
Test status
Simulation time 1225033572 ps
CPU time 5.26 seconds
Started Apr 02 12:37:44 PM PDT 24
Finished Apr 02 12:37:50 PM PDT 24
Peak memory 217432 kb
Host smart-f0d87d3f-4dd6-4d5f-87e6-699fcc7419ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116364554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4116364554
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1488320653
Short name T443
Test name
Test status
Simulation time 244242767 ps
CPU time 1.08 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:50 PM PDT 24
Peak memory 218040 kb
Host smart-d9187f91-d6a3-4271-9bd2-18957c0267bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488320653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1488320653
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2910981831
Short name T410
Test name
Test status
Simulation time 141408375 ps
CPU time 0.81 seconds
Started Apr 02 12:37:42 PM PDT 24
Finished Apr 02 12:37:43 PM PDT 24
Peak memory 200684 kb
Host smart-5bcc9c37-9265-499b-91f4-a18488ef1e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910981831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2910981831
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1790717244
Short name T489
Test name
Test status
Simulation time 1391996111 ps
CPU time 5.23 seconds
Started Apr 02 12:37:53 PM PDT 24
Finished Apr 02 12:37:58 PM PDT 24
Peak memory 200404 kb
Host smart-f7abe014-3ce1-4e11-b27e-59100429acf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790717244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1790717244
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.873871615
Short name T249
Test name
Test status
Simulation time 109328888 ps
CPU time 1.02 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200748 kb
Host smart-e721fcc6-1d6e-4410-897e-3d2a5475a625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873871615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.873871615
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.683018592
Short name T353
Test name
Test status
Simulation time 233453610 ps
CPU time 1.51 seconds
Started Apr 02 12:37:43 PM PDT 24
Finished Apr 02 12:37:45 PM PDT 24
Peak memory 200932 kb
Host smart-facc453d-650e-451b-8e40-20f807840ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683018592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.683018592
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4235635442
Short name T448
Test name
Test status
Simulation time 3290600238 ps
CPU time 14.69 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:38:02 PM PDT 24
Peak memory 209248 kb
Host smart-1fd39d0d-080a-408f-8407-f8714a07485f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235635442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4235635442
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2880807965
Short name T196
Test name
Test status
Simulation time 314248085 ps
CPU time 2.07 seconds
Started Apr 02 12:37:43 PM PDT 24
Finished Apr 02 12:37:46 PM PDT 24
Peak memory 200904 kb
Host smart-7c1844fa-d0ee-4b5d-b930-1da752bbe9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880807965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2880807965
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.243254950
Short name T447
Test name
Test status
Simulation time 104458104 ps
CPU time 0.94 seconds
Started Apr 02 12:37:43 PM PDT 24
Finished Apr 02 12:37:45 PM PDT 24
Peak memory 200776 kb
Host smart-ce207039-5f48-4012-8a87-6001f536be45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243254950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.243254950
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.38609583
Short name T192
Test name
Test status
Simulation time 78033780 ps
CPU time 0.84 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200716 kb
Host smart-033d34fe-bcf1-40e5-a00c-fd288a2e5652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38609583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.38609583
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1454399900
Short name T44
Test name
Test status
Simulation time 1220870969 ps
CPU time 5.28 seconds
Started Apr 02 12:37:41 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 218488 kb
Host smart-c5dcb97f-d5bd-4f02-b8cf-b7711c7a93a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454399900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1454399900
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4286932149
Short name T281
Test name
Test status
Simulation time 243500218 ps
CPU time 1.12 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 218120 kb
Host smart-fb272e85-52f2-4446-8408-003056f8d037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286932149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4286932149
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3676494401
Short name T2
Test name
Test status
Simulation time 218541120 ps
CPU time 0.93 seconds
Started Apr 02 12:37:43 PM PDT 24
Finished Apr 02 12:37:45 PM PDT 24
Peak memory 200616 kb
Host smart-10ecc0c0-21c4-4876-8ae4-4cb433fef649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676494401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3676494401
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.824402025
Short name T381
Test name
Test status
Simulation time 1245918773 ps
CPU time 5.03 seconds
Started Apr 02 12:37:46 PM PDT 24
Finished Apr 02 12:37:51 PM PDT 24
Peak memory 200996 kb
Host smart-f9bf6ac5-0adf-4e81-ac04-de72f0af5e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824402025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.824402025
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.592963876
Short name T389
Test name
Test status
Simulation time 169856729 ps
CPU time 1.23 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200748 kb
Host smart-c0165cf7-4ad7-4b4e-8618-028fd4c5464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592963876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.592963876
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.4100617650
Short name T535
Test name
Test status
Simulation time 181867675 ps
CPU time 1.37 seconds
Started Apr 02 12:37:44 PM PDT 24
Finished Apr 02 12:37:46 PM PDT 24
Peak memory 201004 kb
Host smart-37aa0355-c894-4a7e-96f1-6c2c3510644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100617650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.4100617650
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3934123109
Short name T244
Test name
Test status
Simulation time 8460925725 ps
CPU time 29.29 seconds
Started Apr 02 12:37:46 PM PDT 24
Finished Apr 02 12:38:15 PM PDT 24
Peak memory 201120 kb
Host smart-677fdcaa-b7e9-41bf-b28e-19813dcaeef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934123109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3934123109
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4225135100
Short name T491
Test name
Test status
Simulation time 137414823 ps
CPU time 1.73 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 209112 kb
Host smart-19d4708f-4dd7-4378-8472-11331754c2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225135100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4225135100
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3467383604
Short name T54
Test name
Test status
Simulation time 241774385 ps
CPU time 1.51 seconds
Started Apr 02 12:37:42 PM PDT 24
Finished Apr 02 12:37:43 PM PDT 24
Peak memory 200932 kb
Host smart-c7a6af0a-534d-4a8d-943f-87151872f6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467383604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3467383604
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.458555683
Short name T292
Test name
Test status
Simulation time 55318280 ps
CPU time 0.69 seconds
Started Apr 02 12:37:46 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 200652 kb
Host smart-0e36d749-2576-42cb-aa9e-fb49bab6f0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458555683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.458555683
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1611356708
Short name T49
Test name
Test status
Simulation time 1892001463 ps
CPU time 7.45 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:57 PM PDT 24
Peak memory 218484 kb
Host smart-b52b81d3-ab65-4cc0-9c9c-fc3e6a04c16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611356708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1611356708
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1270109996
Short name T194
Test name
Test status
Simulation time 245072214 ps
CPU time 1.06 seconds
Started Apr 02 12:37:45 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 218072 kb
Host smart-3bde85fb-35c1-43b2-9b83-c2cd32d76aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270109996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1270109996
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3602333168
Short name T478
Test name
Test status
Simulation time 212580092 ps
CPU time 0.96 seconds
Started Apr 02 12:38:00 PM PDT 24
Finished Apr 02 12:38:01 PM PDT 24
Peak memory 200656 kb
Host smart-473b3536-b37f-4cd5-a060-0458efbc4c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602333168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3602333168
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.765996204
Short name T522
Test name
Test status
Simulation time 1044130306 ps
CPU time 5.02 seconds
Started Apr 02 12:37:43 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200912 kb
Host smart-205db70e-8ff1-4c56-9dd6-08d3f2fab7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765996204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.765996204
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1428762710
Short name T423
Test name
Test status
Simulation time 142647189 ps
CPU time 1.1 seconds
Started Apr 02 12:37:46 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 200828 kb
Host smart-6a2041cb-1107-4700-ac2c-c250279ebb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428762710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1428762710
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1860223040
Short name T364
Test name
Test status
Simulation time 256116331 ps
CPU time 1.5 seconds
Started Apr 02 12:37:45 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 200964 kb
Host smart-178eb2e0-6fb0-4c5a-bb94-be5ed54ac823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860223040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1860223040
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2393054531
Short name T457
Test name
Test status
Simulation time 3954444258 ps
CPU time 17.77 seconds
Started Apr 02 12:37:46 PM PDT 24
Finished Apr 02 12:38:04 PM PDT 24
Peak memory 201116 kb
Host smart-8e6dc647-61c9-4ed9-a910-d071d9a9e955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393054531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2393054531
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3375718770
Short name T173
Test name
Test status
Simulation time 326041350 ps
CPU time 2.09 seconds
Started Apr 02 12:37:42 PM PDT 24
Finished Apr 02 12:37:44 PM PDT 24
Peak memory 209056 kb
Host smart-3b0300e2-0a9f-4459-843f-163b9591aec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375718770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3375718770
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.516276827
Short name T169
Test name
Test status
Simulation time 125191450 ps
CPU time 1.05 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:51 PM PDT 24
Peak memory 200816 kb
Host smart-bcd1b8da-9b95-4fd0-9383-033fb0f9f143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516276827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.516276827
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1313576867
Short name T362
Test name
Test status
Simulation time 63988686 ps
CPU time 0.74 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:37:53 PM PDT 24
Peak memory 200652 kb
Host smart-cf37ec58-af39-4009-8f00-237f482321be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313576867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1313576867
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2170096526
Short name T314
Test name
Test status
Simulation time 1902096386 ps
CPU time 7.61 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:55 PM PDT 24
Peak memory 218532 kb
Host smart-d16da813-72c0-4620-b304-b60c60715110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170096526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2170096526
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1958059481
Short name T207
Test name
Test status
Simulation time 244525197 ps
CPU time 1.08 seconds
Started Apr 02 12:37:49 PM PDT 24
Finished Apr 02 12:37:50 PM PDT 24
Peak memory 218256 kb
Host smart-54791062-47ab-4f8b-9a7a-7d953d6bb6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958059481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1958059481
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1399783345
Short name T347
Test name
Test status
Simulation time 173147194 ps
CPU time 0.93 seconds
Started Apr 02 12:37:51 PM PDT 24
Finished Apr 02 12:37:52 PM PDT 24
Peak memory 200696 kb
Host smart-4d5b68a5-88de-4df1-9269-17fa7e005c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399783345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1399783345
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.694701717
Short name T280
Test name
Test status
Simulation time 1501337322 ps
CPU time 5.73 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:37:53 PM PDT 24
Peak memory 200936 kb
Host smart-2ec2cdec-ce5c-4205-87c9-b2dc4156f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694701717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.694701717
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1204869588
Short name T182
Test name
Test status
Simulation time 106731269 ps
CPU time 1.02 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:37:53 PM PDT 24
Peak memory 200776 kb
Host smart-d2e58c63-a9bc-49e8-8e0d-98aee45572c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204869588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1204869588
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4179721615
Short name T9
Test name
Test status
Simulation time 124285320 ps
CPU time 1.19 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:52 PM PDT 24
Peak memory 201012 kb
Host smart-bebb68cc-5ee0-41b6-af34-de5e9d9c169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179721615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4179721615
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.624919666
Short name T100
Test name
Test status
Simulation time 9671866200 ps
CPU time 36.35 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:38:24 PM PDT 24
Peak memory 201116 kb
Host smart-92663633-aa1d-4f2e-94e7-9f14f0ed2ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624919666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.624919666
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.276421279
Short name T251
Test name
Test status
Simulation time 326956874 ps
CPU time 2.14 seconds
Started Apr 02 12:37:49 PM PDT 24
Finished Apr 02 12:37:51 PM PDT 24
Peak memory 209052 kb
Host smart-90358e81-1941-4356-8b72-1d9d8f318e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276421279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.276421279
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1715380173
Short name T241
Test name
Test status
Simulation time 149402404 ps
CPU time 1.09 seconds
Started Apr 02 12:37:46 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 200736 kb
Host smart-0fb4f111-7c68-4f55-a626-776b193782ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715380173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1715380173
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1423279234
Short name T391
Test name
Test status
Simulation time 61284333 ps
CPU time 0.77 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200672 kb
Host smart-0c084ec2-ceb5-4b1d-9248-a1f1c1258b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423279234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1423279234
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4089414495
Short name T47
Test name
Test status
Simulation time 1234330154 ps
CPU time 5.47 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:37:53 PM PDT 24
Peak memory 218472 kb
Host smart-7a18e928-f416-4c35-ad91-676eda069e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089414495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4089414495
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1049289769
Short name T128
Test name
Test status
Simulation time 244031982 ps
CPU time 1.11 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:37:53 PM PDT 24
Peak memory 217576 kb
Host smart-27392997-3060-4219-b2ba-d16d0734869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049289769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1049289769
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2370879003
Short name T186
Test name
Test status
Simulation time 205581569 ps
CPU time 0.94 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200560 kb
Host smart-53901ff0-b69d-47f9-a848-c75eb9d880a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370879003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2370879003
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3427250891
Short name T215
Test name
Test status
Simulation time 763043256 ps
CPU time 3.91 seconds
Started Apr 02 12:37:46 PM PDT 24
Finished Apr 02 12:37:50 PM PDT 24
Peak memory 200968 kb
Host smart-a8fa95c4-ad80-42b3-bae1-a35b5718d658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427250891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3427250891
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.122952257
Short name T125
Test name
Test status
Simulation time 170037602 ps
CPU time 1.27 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200756 kb
Host smart-e253c4ad-2d88-4918-926d-293d43c1d206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122952257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.122952257
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4119315428
Short name T200
Test name
Test status
Simulation time 120123140 ps
CPU time 1.24 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200984 kb
Host smart-4abff48a-f9a2-4315-9e4f-bd4f13802609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119315428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4119315428
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1436557647
Short name T480
Test name
Test status
Simulation time 6801914881 ps
CPU time 24.5 seconds
Started Apr 02 12:37:53 PM PDT 24
Finished Apr 02 12:38:17 PM PDT 24
Peak memory 200632 kb
Host smart-66d6ae74-4776-4d7f-831d-9051bb9a6594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436557647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1436557647
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.723195973
Short name T468
Test name
Test status
Simulation time 359316788 ps
CPU time 2.06 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200912 kb
Host smart-735fa431-e3bb-4c37-b97f-6b553b7e1d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723195973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.723195973
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4049082814
Short name T135
Test name
Test status
Simulation time 100453574 ps
CPU time 1.01 seconds
Started Apr 02 12:37:46 PM PDT 24
Finished Apr 02 12:37:47 PM PDT 24
Peak memory 200832 kb
Host smart-6befc320-9472-4194-b539-41ff34e21ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049082814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4049082814
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1139272563
Short name T234
Test name
Test status
Simulation time 69700398 ps
CPU time 0.78 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:50 PM PDT 24
Peak memory 200688 kb
Host smart-29e36132-ad21-43c7-af3c-972976c4fa80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139272563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1139272563
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4176551307
Short name T481
Test name
Test status
Simulation time 2158137033 ps
CPU time 7.64 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:37:55 PM PDT 24
Peak memory 218576 kb
Host smart-f68cbbb1-f0f7-40e1-97fe-34745ba34861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176551307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4176551307
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1831599642
Short name T451
Test name
Test status
Simulation time 243153802 ps
CPU time 1.1 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:51 PM PDT 24
Peak memory 218104 kb
Host smart-481a9c34-1644-4c34-81a1-e8d2e643c633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831599642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1831599642
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1579167284
Short name T296
Test name
Test status
Simulation time 106331523 ps
CPU time 0.76 seconds
Started Apr 02 12:37:51 PM PDT 24
Finished Apr 02 12:37:52 PM PDT 24
Peak memory 199968 kb
Host smart-238e2a03-1864-4704-93aa-aec2a2ffdd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579167284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1579167284
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2440919986
Short name T222
Test name
Test status
Simulation time 799614962 ps
CPU time 4.24 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:52 PM PDT 24
Peak memory 200980 kb
Host smart-db01a57a-ab6a-4731-99e0-7758a51d0dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440919986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2440919986
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2202164741
Short name T76
Test name
Test status
Simulation time 142943237 ps
CPU time 1.05 seconds
Started Apr 02 12:37:51 PM PDT 24
Finished Apr 02 12:37:52 PM PDT 24
Peak memory 200816 kb
Host smart-96118f34-f418-4a7a-8817-c65e14792fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202164741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2202164741
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1911036825
Short name T441
Test name
Test status
Simulation time 127280681 ps
CPU time 1.18 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:37:53 PM PDT 24
Peak memory 201000 kb
Host smart-4cfb005d-aaa5-49ac-8eff-92a2d77dc00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911036825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1911036825
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.4130693240
Short name T521
Test name
Test status
Simulation time 1482791204 ps
CPU time 7.27 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:55 PM PDT 24
Peak memory 209192 kb
Host smart-e01b97e8-595f-4ee8-89fa-c5139aa52471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130693240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4130693240
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1012057984
Short name T524
Test name
Test status
Simulation time 127280425 ps
CPU time 1.53 seconds
Started Apr 02 12:37:51 PM PDT 24
Finished Apr 02 12:37:53 PM PDT 24
Peak memory 200060 kb
Host smart-bc2789f1-cb01-46bb-b457-886c382b7c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012057984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1012057984
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.608210932
Short name T432
Test name
Test status
Simulation time 178289734 ps
CPU time 1.29 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200804 kb
Host smart-6e10d031-7d0f-48f5-b278-7754bcad9d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608210932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.608210932
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2358309260
Short name T243
Test name
Test status
Simulation time 57861314 ps
CPU time 0.77 seconds
Started Apr 02 12:37:53 PM PDT 24
Finished Apr 02 12:37:54 PM PDT 24
Peak memory 200672 kb
Host smart-10294e0e-77a3-49ab-bb4b-0b7e049523c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358309260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2358309260
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3608180406
Short name T401
Test name
Test status
Simulation time 2356755612 ps
CPU time 8.05 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:38:00 PM PDT 24
Peak memory 218048 kb
Host smart-8a423dbd-614c-4365-95bf-7c446f69d924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608180406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3608180406
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1878670376
Short name T500
Test name
Test status
Simulation time 244981816 ps
CPU time 1.09 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:51 PM PDT 24
Peak memory 218240 kb
Host smart-65de7df6-8541-4f3f-813a-f4e3a7962660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878670376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1878670376
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2041242207
Short name T3
Test name
Test status
Simulation time 84735594 ps
CPU time 0.81 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 200668 kb
Host smart-a83e1f25-1f9b-4e24-bb5e-131ce08844c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041242207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2041242207
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3067570791
Short name T201
Test name
Test status
Simulation time 804818981 ps
CPU time 4.24 seconds
Started Apr 02 12:37:48 PM PDT 24
Finished Apr 02 12:37:52 PM PDT 24
Peak memory 200964 kb
Host smart-9799c7a3-99ba-4b9a-837b-da1b61f3cfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067570791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3067570791
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.78880260
Short name T497
Test name
Test status
Simulation time 111946826 ps
CPU time 1.02 seconds
Started Apr 02 12:37:51 PM PDT 24
Finished Apr 02 12:37:52 PM PDT 24
Peak memory 200768 kb
Host smart-406eaa78-c69a-49a4-86d5-8652978ba325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78880260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.78880260
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.576589785
Short name T504
Test name
Test status
Simulation time 119156464 ps
CPU time 1.2 seconds
Started Apr 02 12:37:47 PM PDT 24
Finished Apr 02 12:37:49 PM PDT 24
Peak memory 201008 kb
Host smart-3c83953d-4278-4472-a0c1-f72acff99643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576589785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.576589785
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.399561764
Short name T102
Test name
Test status
Simulation time 2593059363 ps
CPU time 12.51 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:38:03 PM PDT 24
Peak memory 201152 kb
Host smart-f8727e93-090a-4559-884e-bf8472d41268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399561764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.399561764
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2475556474
Short name T361
Test name
Test status
Simulation time 127873694 ps
CPU time 1.73 seconds
Started Apr 02 12:37:54 PM PDT 24
Finished Apr 02 12:37:56 PM PDT 24
Peak memory 209096 kb
Host smart-ad174183-ae11-47b9-9f71-72ac17438a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475556474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2475556474
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.678948177
Short name T202
Test name
Test status
Simulation time 207786964 ps
CPU time 1.33 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:37:54 PM PDT 24
Peak memory 200784 kb
Host smart-7a6c20e3-bd11-4ba0-b82e-3e415e8973c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678948177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.678948177
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3639243275
Short name T149
Test name
Test status
Simulation time 66279639 ps
CPU time 0.74 seconds
Started Apr 02 12:37:54 PM PDT 24
Finished Apr 02 12:37:55 PM PDT 24
Peak memory 200688 kb
Host smart-cd0f08cd-b85d-463e-945f-876cdb7edf5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639243275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3639243275
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2942624655
Short name T409
Test name
Test status
Simulation time 1911465265 ps
CPU time 6.79 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:37:58 PM PDT 24
Peak memory 217560 kb
Host smart-452ca5ec-9245-4343-90ac-253cbbd984f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942624655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2942624655
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.379484635
Short name T507
Test name
Test status
Simulation time 244736893 ps
CPU time 1.09 seconds
Started Apr 02 12:37:49 PM PDT 24
Finished Apr 02 12:37:50 PM PDT 24
Peak memory 218192 kb
Host smart-6f477574-72f1-48a4-882e-ff63692e62d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379484635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.379484635
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.600254536
Short name T371
Test name
Test status
Simulation time 164566720 ps
CPU time 0.84 seconds
Started Apr 02 12:37:55 PM PDT 24
Finished Apr 02 12:37:56 PM PDT 24
Peak memory 200636 kb
Host smart-a22b3252-1535-4253-b3b5-662a39d6caf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600254536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.600254536
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3572429272
Short name T220
Test name
Test status
Simulation time 1617303088 ps
CPU time 6.15 seconds
Started Apr 02 12:37:51 PM PDT 24
Finished Apr 02 12:37:58 PM PDT 24
Peak memory 200988 kb
Host smart-97d98b24-957b-4a58-8a77-946cc6954aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572429272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3572429272
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2302795601
Short name T139
Test name
Test status
Simulation time 178451722 ps
CPU time 1.25 seconds
Started Apr 02 12:37:55 PM PDT 24
Finished Apr 02 12:37:57 PM PDT 24
Peak memory 200812 kb
Host smart-eb3fbb63-5621-41ec-9944-bd513e7c9aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302795601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2302795601
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.4203055670
Short name T304
Test name
Test status
Simulation time 205482193 ps
CPU time 1.49 seconds
Started Apr 02 12:37:51 PM PDT 24
Finished Apr 02 12:37:52 PM PDT 24
Peak memory 200872 kb
Host smart-98dcfbd1-4af6-436c-afe4-5db6e0af2ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203055670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.4203055670
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1232003517
Short name T310
Test name
Test status
Simulation time 9223600617 ps
CPU time 34.25 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:38:27 PM PDT 24
Peak memory 209280 kb
Host smart-13f4367e-33bb-4d8a-ab19-f7c64c7b800b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232003517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1232003517
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1440733633
Short name T370
Test name
Test status
Simulation time 120903453 ps
CPU time 1.47 seconds
Started Apr 02 12:37:52 PM PDT 24
Finished Apr 02 12:37:53 PM PDT 24
Peak memory 200884 kb
Host smart-651a209b-8a90-42b7-ab88-9587edc4287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440733633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1440733633
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.714788812
Short name T312
Test name
Test status
Simulation time 215246747 ps
CPU time 1.32 seconds
Started Apr 02 12:37:50 PM PDT 24
Finished Apr 02 12:37:52 PM PDT 24
Peak memory 200744 kb
Host smart-7de948ca-949d-4375-9833-9ad3a071a1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714788812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.714788812
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3817075604
Short name T41
Test name
Test status
Simulation time 71113720 ps
CPU time 0.81 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:51 PM PDT 24
Peak memory 200580 kb
Host smart-17a1baef-96b3-4bcc-9d4d-87f7cc4101ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817075604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3817075604
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.577745581
Short name T34
Test name
Test status
Simulation time 2167764636 ps
CPU time 8.49 seconds
Started Apr 02 12:36:43 PM PDT 24
Finished Apr 02 12:36:53 PM PDT 24
Peak memory 221732 kb
Host smart-08074fad-f1e2-40f5-bd52-2d57370af1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577745581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.577745581
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.335856183
Short name T431
Test name
Test status
Simulation time 243698469 ps
CPU time 1.1 seconds
Started Apr 02 12:36:42 PM PDT 24
Finished Apr 02 12:36:45 PM PDT 24
Peak memory 218012 kb
Host smart-471c6dfa-90cc-4888-8fbe-ec3b05bdc659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335856183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.335856183
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2136377574
Short name T534
Test name
Test status
Simulation time 106357797 ps
CPU time 0.84 seconds
Started Apr 02 12:36:45 PM PDT 24
Finished Apr 02 12:36:48 PM PDT 24
Peak memory 200696 kb
Host smart-ebb73b5e-ad57-450c-80c0-440b156ec377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136377574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2136377574
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2432521875
Short name T439
Test name
Test status
Simulation time 1474042450 ps
CPU time 6.17 seconds
Started Apr 02 12:36:47 PM PDT 24
Finished Apr 02 12:36:55 PM PDT 24
Peak memory 200924 kb
Host smart-47155ee8-f6af-403c-98e5-87d2b20f21db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432521875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2432521875
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1219119896
Short name T319
Test name
Test status
Simulation time 155607123 ps
CPU time 1.07 seconds
Started Apr 02 12:36:44 PM PDT 24
Finished Apr 02 12:36:48 PM PDT 24
Peak memory 200760 kb
Host smart-ce503c1f-da6e-46f3-890f-75d321e27ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219119896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1219119896
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1126545160
Short name T129
Test name
Test status
Simulation time 122279835 ps
CPU time 1.3 seconds
Started Apr 02 12:36:45 PM PDT 24
Finished Apr 02 12:36:49 PM PDT 24
Peak memory 200932 kb
Host smart-31c5228d-a99d-44cb-a60c-076d0ce562db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126545160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1126545160
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2389256687
Short name T414
Test name
Test status
Simulation time 2919885140 ps
CPU time 12.99 seconds
Started Apr 02 12:36:43 PM PDT 24
Finished Apr 02 12:36:57 PM PDT 24
Peak memory 209176 kb
Host smart-cef51bc6-d477-4c14-9452-fd215de3da31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389256687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2389256687
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3960631183
Short name T253
Test name
Test status
Simulation time 320788892 ps
CPU time 2.19 seconds
Started Apr 02 12:36:44 PM PDT 24
Finished Apr 02 12:36:48 PM PDT 24
Peak memory 200804 kb
Host smart-fc53ee46-5d57-4ed1-a077-6d75e0a64ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960631183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3960631183
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.98224442
Short name T247
Test name
Test status
Simulation time 291537710 ps
CPU time 1.62 seconds
Started Apr 02 12:36:43 PM PDT 24
Finished Apr 02 12:36:46 PM PDT 24
Peak memory 200812 kb
Host smart-0c8afa94-520c-4ef4-887b-fb5be3bb5ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98224442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.98224442
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3326436396
Short name T180
Test name
Test status
Simulation time 70653411 ps
CPU time 0.84 seconds
Started Apr 02 12:36:46 PM PDT 24
Finished Apr 02 12:36:50 PM PDT 24
Peak memory 200692 kb
Host smart-1cb74ace-c5c3-43d3-83db-2faa7eb3f5e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326436396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3326436396
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.200408887
Short name T46
Test name
Test status
Simulation time 2354928476 ps
CPU time 7.82 seconds
Started Apr 02 12:36:55 PM PDT 24
Finished Apr 02 12:37:06 PM PDT 24
Peak memory 218224 kb
Host smart-a660d8db-4477-4c48-857d-87cb8c32b607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200408887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.200408887
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.555497768
Short name T233
Test name
Test status
Simulation time 244529520 ps
CPU time 1.11 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 217996 kb
Host smart-c0d2907a-7fde-4cd3-9636-4b3261454b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555497768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.555497768
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3611843202
Short name T284
Test name
Test status
Simulation time 134188687 ps
CPU time 0.8 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 200684 kb
Host smart-c2bef5a0-c8b0-47a5-8855-98ecffb05dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611843202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3611843202
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2383984127
Short name T98
Test name
Test status
Simulation time 1827258031 ps
CPU time 6.26 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:58 PM PDT 24
Peak memory 200936 kb
Host smart-f0d1c16e-ea0e-4a4b-a9d7-f9c316d7a1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383984127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2383984127
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3406365846
Short name T482
Test name
Test status
Simulation time 158078923 ps
CPU time 1.09 seconds
Started Apr 02 12:36:47 PM PDT 24
Finished Apr 02 12:36:50 PM PDT 24
Peak memory 200668 kb
Host smart-b774cd50-76ad-4df1-b6ff-309a147876bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406365846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3406365846
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4048346979
Short name T462
Test name
Test status
Simulation time 244870017 ps
CPU time 1.6 seconds
Started Apr 02 12:36:47 PM PDT 24
Finished Apr 02 12:36:50 PM PDT 24
Peak memory 200944 kb
Host smart-61a12caa-e1ec-4474-ae3f-fc8920fbdeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048346979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4048346979
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.150722128
Short name T382
Test name
Test status
Simulation time 15317107741 ps
CPU time 53.92 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:37:46 PM PDT 24
Peak memory 209316 kb
Host smart-44a17988-44cd-46d6-8280-c3eff30491ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150722128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.150722128
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3369743287
Short name T514
Test name
Test status
Simulation time 454613127 ps
CPU time 2.46 seconds
Started Apr 02 12:36:52 PM PDT 24
Finished Apr 02 12:36:56 PM PDT 24
Peak memory 200880 kb
Host smart-6c5e677b-9f21-4405-8c45-1a97d8d25322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369743287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3369743287
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.100294317
Short name T306
Test name
Test status
Simulation time 147498404 ps
CPU time 1.12 seconds
Started Apr 02 12:36:48 PM PDT 24
Finished Apr 02 12:36:51 PM PDT 24
Peak memory 200728 kb
Host smart-1b34a4a4-afc3-4057-a1bc-651d661942f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100294317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.100294317
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3800069582
Short name T293
Test name
Test status
Simulation time 76151930 ps
CPU time 0.77 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:55 PM PDT 24
Peak memory 200672 kb
Host smart-44eb3548-9bdf-4cb9-aa2b-295883d18208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800069582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3800069582
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3612935942
Short name T440
Test name
Test status
Simulation time 2352254083 ps
CPU time 7.71 seconds
Started Apr 02 12:36:47 PM PDT 24
Finished Apr 02 12:36:57 PM PDT 24
Peak memory 217868 kb
Host smart-bb6c4784-66c5-422e-830a-2e40bbd97d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612935942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3612935942
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2224322415
Short name T157
Test name
Test status
Simulation time 244622465 ps
CPU time 1.12 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:52 PM PDT 24
Peak memory 218076 kb
Host smart-116ed015-ce4a-495e-b975-1654d96e7a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224322415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2224322415
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3153553310
Short name T15
Test name
Test status
Simulation time 237321901 ps
CPU time 0.9 seconds
Started Apr 02 12:36:46 PM PDT 24
Finished Apr 02 12:36:50 PM PDT 24
Peak memory 200660 kb
Host smart-d3dab959-3ce9-4b44-ae03-82a977915c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153553310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3153553310
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2089496042
Short name T96
Test name
Test status
Simulation time 2065004468 ps
CPU time 6.97 seconds
Started Apr 02 12:36:48 PM PDT 24
Finished Apr 02 12:36:57 PM PDT 24
Peak memory 200968 kb
Host smart-3a1204c1-eb34-4f7f-b005-401dd1402ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089496042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2089496042
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2061051408
Short name T325
Test name
Test status
Simulation time 150828221 ps
CPU time 1.17 seconds
Started Apr 02 12:36:55 PM PDT 24
Finished Apr 02 12:36:57 PM PDT 24
Peak memory 200616 kb
Host smart-e04c52b0-8e54-4854-816c-abc662754670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061051408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2061051408
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.701685358
Short name T471
Test name
Test status
Simulation time 121204814 ps
CPU time 1.24 seconds
Started Apr 02 12:36:48 PM PDT 24
Finished Apr 02 12:36:52 PM PDT 24
Peak memory 200892 kb
Host smart-63ba8da7-8760-4ba6-aab9-fdd6c7d3a61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701685358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.701685358
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1511576517
Short name T333
Test name
Test status
Simulation time 246332226 ps
CPU time 1.74 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:52 PM PDT 24
Peak memory 200820 kb
Host smart-3529e809-8b57-47c8-a069-4424a1351150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511576517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1511576517
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2796950175
Short name T435
Test name
Test status
Simulation time 69747917 ps
CPU time 0.76 seconds
Started Apr 02 12:36:47 PM PDT 24
Finished Apr 02 12:36:49 PM PDT 24
Peak memory 200768 kb
Host smart-5d86bebe-c9b0-44eb-a13b-fd2107dfcc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796950175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2796950175
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1685676145
Short name T518
Test name
Test status
Simulation time 55487385 ps
CPU time 0.74 seconds
Started Apr 02 12:36:51 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 200660 kb
Host smart-1f14b3a2-639e-40ce-9019-32f404486aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685676145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1685676145
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1557053676
Short name T320
Test name
Test status
Simulation time 1225963373 ps
CPU time 5.55 seconds
Started Apr 02 12:36:46 PM PDT 24
Finished Apr 02 12:36:53 PM PDT 24
Peak memory 222476 kb
Host smart-6c780c53-9cfd-436d-93b7-cab6033003ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557053676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1557053676
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.909802940
Short name T265
Test name
Test status
Simulation time 243819188 ps
CPU time 1.1 seconds
Started Apr 02 12:36:48 PM PDT 24
Finished Apr 02 12:36:51 PM PDT 24
Peak memory 218060 kb
Host smart-72325680-c478-4be2-950d-719cd1811dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909802940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.909802940
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1009433727
Short name T20
Test name
Test status
Simulation time 218151872 ps
CPU time 1 seconds
Started Apr 02 12:36:47 PM PDT 24
Finished Apr 02 12:36:50 PM PDT 24
Peak memory 200600 kb
Host smart-7cdc7519-85c9-496a-ba41-25fe3dbd92bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009433727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1009433727
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1866644146
Short name T205
Test name
Test status
Simulation time 2111412872 ps
CPU time 7.98 seconds
Started Apr 02 12:36:46 PM PDT 24
Finished Apr 02 12:36:56 PM PDT 24
Peak memory 201004 kb
Host smart-b0f4959f-32eb-4ede-871c-70a4967a82fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866644146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1866644146
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.185845782
Short name T305
Test name
Test status
Simulation time 149528018 ps
CPU time 1.07 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:53 PM PDT 24
Peak memory 200812 kb
Host smart-bff26d4f-8758-4849-b695-5ebfcd63621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185845782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.185845782
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1077518962
Short name T146
Test name
Test status
Simulation time 194408671 ps
CPU time 1.29 seconds
Started Apr 02 12:36:49 PM PDT 24
Finished Apr 02 12:36:53 PM PDT 24
Peak memory 200992 kb
Host smart-efe14239-7ccd-42f5-9c90-98ade864c829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077518962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1077518962
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4102393405
Short name T392
Test name
Test status
Simulation time 92286889 ps
CPU time 0.86 seconds
Started Apr 02 12:36:56 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 200692 kb
Host smart-b1a152bd-73fe-46f7-ba98-71a45aebcb87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102393405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4102393405
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.4136268195
Short name T506
Test name
Test status
Simulation time 439286219 ps
CPU time 2.37 seconds
Started Apr 02 12:36:55 PM PDT 24
Finished Apr 02 12:36:58 PM PDT 24
Peak memory 208900 kb
Host smart-7ae38557-c61a-4771-b5f8-2e2c09938f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136268195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.4136268195
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1282469536
Short name T162
Test name
Test status
Simulation time 95275489 ps
CPU time 0.88 seconds
Started Apr 02 12:36:48 PM PDT 24
Finished Apr 02 12:36:51 PM PDT 24
Peak memory 200740 kb
Host smart-214c2f7d-1259-4c91-a7d4-23a0b9ef1c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282469536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1282469536
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.736666368
Short name T219
Test name
Test status
Simulation time 69774142 ps
CPU time 0.79 seconds
Started Apr 02 12:36:51 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 200612 kb
Host smart-9ef58724-b7fc-4280-874d-f12079536e82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736666368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.736666368
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2822797731
Short name T289
Test name
Test status
Simulation time 1212377782 ps
CPU time 5.5 seconds
Started Apr 02 12:36:51 PM PDT 24
Finished Apr 02 12:36:59 PM PDT 24
Peak memory 222476 kb
Host smart-f405398a-f4a7-4ac2-81e7-d5da53b006b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822797731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2822797731
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3185123837
Short name T195
Test name
Test status
Simulation time 243741451 ps
CPU time 1.11 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 218236 kb
Host smart-99b3e7f3-9f4f-4c04-97db-418b493796a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185123837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3185123837
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.4050306088
Short name T12
Test name
Test status
Simulation time 145567913 ps
CPU time 0.83 seconds
Started Apr 02 12:36:52 PM PDT 24
Finished Apr 02 12:36:55 PM PDT 24
Peak memory 200636 kb
Host smart-b320c246-1420-4fef-92cb-f282725ee7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050306088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4050306088
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.419730513
Short name T417
Test name
Test status
Simulation time 1428632469 ps
CPU time 5.47 seconds
Started Apr 02 12:36:54 PM PDT 24
Finished Apr 02 12:37:03 PM PDT 24
Peak memory 201064 kb
Host smart-37c14058-dea9-4fc4-a501-099232e903ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419730513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.419730513
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.212145325
Short name T501
Test name
Test status
Simulation time 174773990 ps
CPU time 1.13 seconds
Started Apr 02 12:36:54 PM PDT 24
Finished Apr 02 12:36:58 PM PDT 24
Peak memory 200820 kb
Host smart-35ed8eb4-5c62-4d74-8b54-603f6bc27a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212145325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.212145325
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3992159422
Short name T355
Test name
Test status
Simulation time 191951341 ps
CPU time 1.46 seconds
Started Apr 02 12:36:51 PM PDT 24
Finished Apr 02 12:36:55 PM PDT 24
Peak memory 200900 kb
Host smart-3f938177-55b8-4ca1-b6d6-7f49af7c3bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992159422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3992159422
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3076997647
Short name T429
Test name
Test status
Simulation time 11219878514 ps
CPU time 39.26 seconds
Started Apr 02 12:36:52 PM PDT 24
Finished Apr 02 12:37:33 PM PDT 24
Peak memory 210252 kb
Host smart-eb256ab8-31f8-4656-8d7b-d0f32f0d9887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076997647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3076997647
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2055765030
Short name T119
Test name
Test status
Simulation time 318871768 ps
CPU time 1.95 seconds
Started Apr 02 12:36:52 PM PDT 24
Finished Apr 02 12:36:56 PM PDT 24
Peak memory 200840 kb
Host smart-f3aaae15-fd85-4023-b90d-cce7731e3c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055765030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2055765030
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.685644410
Short name T21
Test name
Test status
Simulation time 174037757 ps
CPU time 1.22 seconds
Started Apr 02 12:36:50 PM PDT 24
Finished Apr 02 12:36:54 PM PDT 24
Peak memory 200648 kb
Host smart-38c3ff36-7d2f-47f9-a42b-0a4f99815023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685644410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.685644410
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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