Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_info_cp 8 0 8 100.00 100 1 1 0


Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
capture_cross 16 0 16 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8730 1 T1 20 T8 120 T9 18
auto[1] 11598 1 T1 81 T5 4 T8 121



Summary for Variable reset_info_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for reset_info_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 6180 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] 6875 1 T1 27 T2 1 T3 1
reset_info_cp[2] 3194 1 T1 15 T5 1 T8 39
reset_info_cp[4] 4131 1 T1 16 T5 1 T8 58
reset_info_cp[8] 107 1 T1 1 T8 2 T9 1
reset_info_cp[16] 129 1 T8 1 T9 1 T10 1
reset_info_cp[32] 109 1 T10 1 T15 2 T16 1
reset_info_cp[64] 101 1 T1 1 T10 1 T14 1
reset_info_cp[128] 122 1 T1 1 T8 3 T9 2



Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for capture_cross

Bins
reset_info_cpenable_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] auto[0] 3320 1 T1 20 T8 37 T9 18
reset_info_cp[1] auto[1] 2935 1 T1 6 T5 1 T8 32
reset_info_cp[2] auto[0] 1024 1 T8 19 T10 14 T12 6
reset_info_cp[2] auto[1] 2170 1 T1 15 T5 1 T8 20
reset_info_cp[4] auto[0] 1519 1 T8 26 T10 21 T12 7
reset_info_cp[4] auto[1] 2612 1 T1 16 T5 1 T8 32
reset_info_cp[8] auto[0] 41 1 T8 1 T14 1 T133 1
reset_info_cp[8] auto[1] 66 1 T1 1 T8 1 T9 1
reset_info_cp[16] auto[0] 48 1 T10 1 T15 1 T106 1
reset_info_cp[16] auto[1] 81 1 T8 1 T9 1 T32 1
reset_info_cp[32] auto[0] 46 1 T10 1 T15 1 T29 1
reset_info_cp[32] auto[1] 63 1 T15 1 T16 1 T31 1
reset_info_cp[64] auto[0] 42 1 T14 1 T137 1 T108 2
reset_info_cp[64] auto[1] 59 1 T1 1 T10 1 T31 1
reset_info_cp[128] auto[0] 50 1 T10 2 T105 1 T133 1
reset_info_cp[128] auto[1] 72 1 T1 1 T8 3 T9 2

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