Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8663

1

T1

20

T8

126

T9

18

auto[1]

11665

1

T1

81

T5

4

T8

115

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6180	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6875	1			T1	27		T2	1		T3	1
reset_info_cp[2]	3194	1			T1	15		T5	1		T8	39
reset_info_cp[4]	4131	1			T1	16		T5	1		T8	58
reset_info_cp[8]	107	1			T1	1		T8	2		T9	1
reset_info_cp[16]	129	1			T8	1		T9	1		T10	1
reset_info_cp[32]	109	1			T10	1		T15	2		T16	1
reset_info_cp[64]	101	1			T1	1		T10	1		T14	1
reset_info_cp[128]	122	1			T1	1		T8	3		T9	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3313	1			T1	20		T8	31		T9	18
reset_info_cp[1]	auto[1]	2942	1			T1	6		T5	1		T8	38
reset_info_cp[2]	auto[0]	988	1			T8	20		T10	15		T12	7
reset_info_cp[2]	auto[1]	2206	1			T1	15		T5	1		T8	19
reset_info_cp[4]	auto[0]	1541	1			T8	33		T10	17		T12	13
reset_info_cp[4]	auto[1]	2590	1			T1	16		T5	1		T8	25
reset_info_cp[8]	auto[0]	39	1			T14	1		T16	1		T108	1
reset_info_cp[8]	auto[1]	68	1			T1	1		T8	2		T9	1
reset_info_cp[16]	auto[0]	52	1			T8	1		T106	1		T137	1
reset_info_cp[16]	auto[1]	77	1			T9	1		T10	1		T15	1
reset_info_cp[32]	auto[0]	43	1			T10	1		T15	1		T29	1
reset_info_cp[32]	auto[1]	66	1			T15	1		T16	1		T31	1
reset_info_cp[64]	auto[0]	44	1			T105	1		T137	1		T133	1
reset_info_cp[64]	auto[1]	57	1			T1	1		T10	1		T14	1
reset_info_cp[128]	auto[0]	41	1			T8	1		T10	1		T122	1
reset_info_cp[128]	auto[1]	81	1			T1	1		T8	2		T9	2