Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T539 /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1700277765 Apr 04 12:29:47 PM PDT 24 Apr 04 12:29:48 PM PDT 24 138573123 ps
T540 /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3893212538 Apr 04 12:30:17 PM PDT 24 Apr 04 12:30:18 PM PDT 24 133790262 ps
T541 /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.718903815 Apr 04 12:29:47 PM PDT 24 Apr 04 12:29:48 PM PDT 24 151873049 ps
T542 /workspace/coverage/default/29.rstmgr_sw_rst.3197645716 Apr 04 12:29:39 PM PDT 24 Apr 04 12:29:41 PM PDT 24 279698244 ps
T543 /workspace/coverage/default/36.rstmgr_por_stretcher.951284061 Apr 04 12:31:10 PM PDT 24 Apr 04 12:31:12 PM PDT 24 175163598 ps
T59 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2330862471 Apr 04 02:41:53 PM PDT 24 Apr 04 02:41:55 PM PDT 24 201203696 ps
T60 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.980143141 Apr 04 02:41:50 PM PDT 24 Apr 04 02:41:51 PM PDT 24 70492990 ps
T61 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1485977501 Apr 04 02:42:28 PM PDT 24 Apr 04 02:42:30 PM PDT 24 138899725 ps
T62 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.984156994 Apr 04 02:41:44 PM PDT 24 Apr 04 02:41:46 PM PDT 24 200944019 ps
T85 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.674706786 Apr 04 02:41:50 PM PDT 24 Apr 04 02:41:53 PM PDT 24 226410197 ps
T115 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.83213584 Apr 04 02:42:24 PM PDT 24 Apr 04 02:42:25 PM PDT 24 146619584 ps
T63 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1998329540 Apr 04 02:42:06 PM PDT 24 Apr 04 02:42:08 PM PDT 24 109534779 ps
T84 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.806781584 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 232704364 ps
T116 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1953656200 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 68571000 ps
T64 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2555638758 Apr 04 02:42:12 PM PDT 24 Apr 04 02:42:13 PM PDT 24 107022019 ps
T117 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.724679136 Apr 04 02:41:59 PM PDT 24 Apr 04 02:42:00 PM PDT 24 62230654 ps
T136 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3725005089 Apr 04 02:41:54 PM PDT 24 Apr 04 02:42:05 PM PDT 24 79355685 ps
T65 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1168668342 Apr 04 02:42:24 PM PDT 24 Apr 04 02:42:26 PM PDT 24 488822201 ps
T67 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1020284494 Apr 04 02:42:04 PM PDT 24 Apr 04 02:42:06 PM PDT 24 510165203 ps
T118 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2756370467 Apr 04 02:41:45 PM PDT 24 Apr 04 02:41:47 PM PDT 24 143573794 ps
T66 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2243315204 Apr 04 02:42:15 PM PDT 24 Apr 04 02:42:18 PM PDT 24 295583959 ps
T544 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4030472236 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 102364604 ps
T68 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3552709845 Apr 04 02:41:54 PM PDT 24 Apr 04 02:41:57 PM PDT 24 785958400 ps
T119 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.970629512 Apr 04 02:41:52 PM PDT 24 Apr 04 02:41:53 PM PDT 24 68616357 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1510805796 Apr 04 02:42:18 PM PDT 24 Apr 04 02:42:19 PM PDT 24 93497252 ps
T120 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1840242261 Apr 04 02:42:10 PM PDT 24 Apr 04 02:42:11 PM PDT 24 66451081 ps
T86 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3292121232 Apr 04 02:42:25 PM PDT 24 Apr 04 02:42:27 PM PDT 24 780796647 ps
T83 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1655774770 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:55 PM PDT 24 421406911 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4187831513 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 98444916 ps
T95 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1711957753 Apr 04 02:42:20 PM PDT 24 Apr 04 02:42:21 PM PDT 24 170113417 ps
T97 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1240268330 Apr 04 02:42:20 PM PDT 24 Apr 04 02:42:23 PM PDT 24 869282659 ps
T96 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2429478743 Apr 04 02:41:59 PM PDT 24 Apr 04 02:42:00 PM PDT 24 139077441 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.417686843 Apr 04 02:42:00 PM PDT 24 Apr 04 02:42:02 PM PDT 24 148705686 ps
T104 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2358504518 Apr 04 02:41:59 PM PDT 24 Apr 04 02:42:00 PM PDT 24 177861243 ps
T87 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2148845014 Apr 04 02:42:22 PM PDT 24 Apr 04 02:42:26 PM PDT 24 438566786 ps
T121 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2222672032 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 255732527 ps
T548 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2576993044 Apr 04 02:42:13 PM PDT 24 Apr 04 02:42:14 PM PDT 24 96289989 ps
T88 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2524222976 Apr 04 02:41:54 PM PDT 24 Apr 04 02:42:02 PM PDT 24 181452422 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2410968893 Apr 04 02:41:50 PM PDT 24 Apr 04 02:41:52 PM PDT 24 214583557 ps
T550 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.589927416 Apr 04 02:41:54 PM PDT 24 Apr 04 02:41:56 PM PDT 24 139318411 ps
T135 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4133931867 Apr 04 02:42:22 PM PDT 24 Apr 04 02:42:24 PM PDT 24 456996187 ps
T551 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1337409241 Apr 04 02:41:58 PM PDT 24 Apr 04 02:42:00 PM PDT 24 285612070 ps
T552 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1572363761 Apr 04 02:42:08 PM PDT 24 Apr 04 02:42:10 PM PDT 24 322625690 ps
T553 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4119413706 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 138403341 ps
T554 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.673826730 Apr 04 02:42:12 PM PDT 24 Apr 04 02:42:13 PM PDT 24 63867067 ps
T89 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2926146016 Apr 04 02:41:56 PM PDT 24 Apr 04 02:41:59 PM PDT 24 1424884103 ps
T555 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4056130016 Apr 04 02:41:59 PM PDT 24 Apr 04 02:42:00 PM PDT 24 77745096 ps
T556 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1155091251 Apr 04 02:41:50 PM PDT 24 Apr 04 02:41:52 PM PDT 24 71566318 ps
T98 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2683735804 Apr 04 02:42:21 PM PDT 24 Apr 04 02:42:22 PM PDT 24 240704826 ps
T557 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3993974642 Apr 04 02:42:18 PM PDT 24 Apr 04 02:42:19 PM PDT 24 188745956 ps
T558 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1145843438 Apr 04 02:42:13 PM PDT 24 Apr 04 02:42:14 PM PDT 24 88280113 ps
T92 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2268717367 Apr 04 02:42:11 PM PDT 24 Apr 04 02:42:14 PM PDT 24 430492460 ps
T134 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4166063644 Apr 04 02:42:08 PM PDT 24 Apr 04 02:42:11 PM PDT 24 791046200 ps
T559 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.510277153 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 74572692 ps
T560 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4052752662 Apr 04 02:42:01 PM PDT 24 Apr 04 02:42:04 PM PDT 24 139204146 ps
T561 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.748641553 Apr 04 02:42:23 PM PDT 24 Apr 04 02:42:25 PM PDT 24 158080116 ps
T91 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3088028707 Apr 04 02:42:17 PM PDT 24 Apr 04 02:42:19 PM PDT 24 445825876 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2288624244 Apr 04 02:42:08 PM PDT 24 Apr 04 02:42:11 PM PDT 24 273075695 ps
T563 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3208176314 Apr 04 02:41:59 PM PDT 24 Apr 04 02:42:00 PM PDT 24 168406777 ps
T564 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3957457849 Apr 04 02:42:22 PM PDT 24 Apr 04 02:42:24 PM PDT 24 125409753 ps
T565 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.762267411 Apr 04 02:42:06 PM PDT 24 Apr 04 02:42:08 PM PDT 24 122073623 ps
T566 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3024279041 Apr 04 02:42:22 PM PDT 24 Apr 04 02:42:24 PM PDT 24 127703792 ps
T107 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1984871421 Apr 04 02:41:56 PM PDT 24 Apr 04 02:41:57 PM PDT 24 65372180 ps
T567 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2829944402 Apr 04 02:42:18 PM PDT 24 Apr 04 02:42:20 PM PDT 24 225864284 ps
T568 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1288398900 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 188523213 ps
T569 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.596089418 Apr 04 02:41:45 PM PDT 24 Apr 04 02:41:48 PM PDT 24 401372226 ps
T570 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.215870956 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 164772166 ps
T571 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2830188057 Apr 04 02:42:04 PM PDT 24 Apr 04 02:42:05 PM PDT 24 223736593 ps
T572 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1918932026 Apr 04 02:42:01 PM PDT 24 Apr 04 02:42:03 PM PDT 24 128688666 ps
T573 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2978619773 Apr 04 02:42:28 PM PDT 24 Apr 04 02:42:29 PM PDT 24 205947025 ps
T574 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1216346158 Apr 04 02:42:09 PM PDT 24 Apr 04 02:42:11 PM PDT 24 146666152 ps
T575 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2210373522 Apr 04 02:42:09 PM PDT 24 Apr 04 02:42:11 PM PDT 24 226581006 ps
T576 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2041461847 Apr 04 02:41:53 PM PDT 24 Apr 04 02:41:55 PM PDT 24 216029903 ps
T577 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3499145636 Apr 04 02:41:58 PM PDT 24 Apr 04 02:42:01 PM PDT 24 913696518 ps
T578 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1794014928 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:56 PM PDT 24 592663797 ps
T579 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2603634687 Apr 04 02:42:07 PM PDT 24 Apr 04 02:42:09 PM PDT 24 274873268 ps
T580 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3057163191 Apr 04 02:42:24 PM PDT 24 Apr 04 02:42:27 PM PDT 24 165695758 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.57558785 Apr 04 02:42:07 PM PDT 24 Apr 04 02:42:08 PM PDT 24 148409251 ps
T582 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4015472045 Apr 04 02:42:19 PM PDT 24 Apr 04 02:42:20 PM PDT 24 61738836 ps
T583 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3671251166 Apr 04 02:42:22 PM PDT 24 Apr 04 02:42:24 PM PDT 24 223537442 ps
T584 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.12979651 Apr 04 02:41:47 PM PDT 24 Apr 04 02:41:49 PM PDT 24 175499528 ps
T585 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.811446787 Apr 04 02:41:54 PM PDT 24 Apr 04 02:41:55 PM PDT 24 177910314 ps
T586 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1529619027 Apr 04 02:41:54 PM PDT 24 Apr 04 02:41:55 PM PDT 24 119147948 ps
T93 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.278893994 Apr 04 02:41:54 PM PDT 24 Apr 04 02:41:57 PM PDT 24 427038217 ps
T587 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1061602070 Apr 04 02:42:11 PM PDT 24 Apr 04 02:42:16 PM PDT 24 793238880 ps
T90 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.775805241 Apr 04 02:41:46 PM PDT 24 Apr 04 02:41:48 PM PDT 24 416743546 ps
T588 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2301429809 Apr 04 02:42:00 PM PDT 24 Apr 04 02:42:02 PM PDT 24 430369697 ps
T589 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.696498849 Apr 04 02:41:55 PM PDT 24 Apr 04 02:41:56 PM PDT 24 222914669 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2841364649 Apr 04 02:42:16 PM PDT 24 Apr 04 02:42:18 PM PDT 24 359279732 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.986061867 Apr 04 02:42:20 PM PDT 24 Apr 04 02:42:23 PM PDT 24 266327075 ps
T592 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.318637751 Apr 04 02:41:59 PM PDT 24 Apr 04 02:42:01 PM PDT 24 487252391 ps
T593 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1358506736 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 82813477 ps
T594 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1713797959 Apr 04 02:42:10 PM PDT 24 Apr 04 02:42:11 PM PDT 24 70656248 ps
T595 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.22961918 Apr 04 02:41:51 PM PDT 24 Apr 04 02:41:53 PM PDT 24 96488326 ps
T596 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3505949354 Apr 04 02:42:08 PM PDT 24 Apr 04 02:42:09 PM PDT 24 94779444 ps
T597 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3315446910 Apr 04 02:42:18 PM PDT 24 Apr 04 02:42:20 PM PDT 24 492608862 ps
T598 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.82657838 Apr 04 02:41:50 PM PDT 24 Apr 04 02:41:52 PM PDT 24 212482074 ps
T599 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1096017105 Apr 04 02:42:20 PM PDT 24 Apr 04 02:42:21 PM PDT 24 126146866 ps
T600 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3878452036 Apr 04 02:41:59 PM PDT 24 Apr 04 02:42:00 PM PDT 24 429150895 ps
T601 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3457237532 Apr 04 02:41:53 PM PDT 24 Apr 04 02:41:54 PM PDT 24 93110304 ps
T602 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4046284892 Apr 04 02:42:10 PM PDT 24 Apr 04 02:42:13 PM PDT 24 905866241 ps
T603 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.974812994 Apr 04 02:42:10 PM PDT 24 Apr 04 02:42:13 PM PDT 24 189700012 ps
T604 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1071221666 Apr 04 02:42:02 PM PDT 24 Apr 04 02:42:06 PM PDT 24 788918579 ps
T605 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4142933596 Apr 04 02:42:22 PM PDT 24 Apr 04 02:42:23 PM PDT 24 132833212 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3294385418 Apr 04 02:42:16 PM PDT 24 Apr 04 02:42:17 PM PDT 24 87582381 ps
T607 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.487990294 Apr 04 02:42:25 PM PDT 24 Apr 04 02:42:26 PM PDT 24 80614496 ps
T608 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2782064402 Apr 04 02:41:53 PM PDT 24 Apr 04 02:41:55 PM PDT 24 135909206 ps
T609 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.99027237 Apr 04 02:41:54 PM PDT 24 Apr 04 02:41:55 PM PDT 24 88114159 ps
T610 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3005340216 Apr 04 02:41:59 PM PDT 24 Apr 04 02:42:00 PM PDT 24 112522815 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.703570811 Apr 04 02:42:10 PM PDT 24 Apr 04 02:42:19 PM PDT 24 2305341260 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3924776551 Apr 04 02:42:01 PM PDT 24 Apr 04 02:42:03 PM PDT 24 122659561 ps
T613 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4280757412 Apr 04 02:41:46 PM PDT 24 Apr 04 02:41:47 PM PDT 24 65317424 ps
T614 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2887696742 Apr 04 02:42:17 PM PDT 24 Apr 04 02:42:18 PM PDT 24 122624400 ps
T615 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4162735053 Apr 04 02:42:24 PM PDT 24 Apr 04 02:42:26 PM PDT 24 120148468 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.244087856 Apr 04 02:41:50 PM PDT 24 Apr 04 02:41:51 PM PDT 24 55199618 ps
T617 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3951378246 Apr 04 02:41:50 PM PDT 24 Apr 04 02:41:51 PM PDT 24 125365588 ps
T94 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1262580990 Apr 04 02:42:22 PM PDT 24 Apr 04 02:42:24 PM PDT 24 439328959 ps
T618 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.893338984 Apr 04 02:42:17 PM PDT 24 Apr 04 02:42:19 PM PDT 24 166359770 ps
T619 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2947481370 Apr 04 02:41:55 PM PDT 24 Apr 04 02:41:57 PM PDT 24 498620066 ps
T620 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2796222111 Apr 04 02:41:54 PM PDT 24 Apr 04 02:41:55 PM PDT 24 145451235 ps

Test location /workspace/coverage/default/43.rstmgr_stress_all.3558388246
Short name T10
Test name
Test status
Simulation time 3357938462 ps
CPU time 15.28 seconds
Started Apr 04 12:30:23 PM PDT 24
Finished Apr 04 12:30:38 PM PDT 24
Peak memory 209836 kb
Host smart-34165df3-ec76-4e31-a37c-7b9d2a38b79d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558388246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3558388246
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1429733849
Short name T58
Test name
Test status
Simulation time 335705732 ps
CPU time 2.08 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 208716 kb
Host smart-ba4cea1e-5ac2-43a5-be0b-0cd8d097271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429733849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1429733849
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2555638758
Short name T64
Test name
Test status
Simulation time 107022019 ps
CPU time 1.02 seconds
Started Apr 04 02:42:12 PM PDT 24
Finished Apr 04 02:42:13 PM PDT 24
Peak memory 209020 kb
Host smart-4c66957f-3923-4e5f-b5d4-218d9ff59658
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555638758 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2555638758
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.4220079969
Short name T70
Test name
Test status
Simulation time 10729359540 ps
CPU time 16.95 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:29:12 PM PDT 24
Peak memory 217636 kb
Host smart-b91ff594-6336-440f-9dcf-a99aea5e0855
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220079969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4220079969
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.135918800
Short name T1
Test name
Test status
Simulation time 2344884889 ps
CPU time 8.17 seconds
Started Apr 04 12:30:21 PM PDT 24
Finished Apr 04 12:30:30 PM PDT 24
Peak memory 217564 kb
Host smart-6aa4accb-7928-4b0f-ab88-c6b1ea74ffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135918800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.135918800
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3292121232
Short name T86
Test name
Test status
Simulation time 780796647 ps
CPU time 2.64 seconds
Started Apr 04 02:42:25 PM PDT 24
Finished Apr 04 02:42:27 PM PDT 24
Peak memory 200924 kb
Host smart-46ad4fc3-b39f-4934-a523-d283ac6dbc11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292121232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3292121232
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3012189275
Short name T14
Test name
Test status
Simulation time 10255147596 ps
CPU time 40.53 seconds
Started Apr 04 12:29:32 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 200696 kb
Host smart-384fc5b4-47d6-4baa-8bbb-c0aff94cd690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012189275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3012189275
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.4047428977
Short name T6
Test name
Test status
Simulation time 59081513 ps
CPU time 0.78 seconds
Started Apr 04 12:31:02 PM PDT 24
Finished Apr 04 12:31:03 PM PDT 24
Peak memory 200292 kb
Host smart-f4c291f0-e879-4f59-a1af-f9a27692007b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047428977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.4047428977
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2148845014
Short name T87
Test name
Test status
Simulation time 438566786 ps
CPU time 3.14 seconds
Started Apr 04 02:42:22 PM PDT 24
Finished Apr 04 02:42:26 PM PDT 24
Peak memory 209104 kb
Host smart-4659946e-c05a-46da-a6e2-a290a4f22aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148845014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2148845014
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2352931076
Short name T46
Test name
Test status
Simulation time 2333173138 ps
CPU time 7.99 seconds
Started Apr 04 12:29:03 PM PDT 24
Finished Apr 04 12:29:12 PM PDT 24
Peak memory 218296 kb
Host smart-5245ef1a-95fc-4aeb-86ee-2a903c593974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352931076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2352931076
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.316843782
Short name T147
Test name
Test status
Simulation time 157491713 ps
CPU time 1.09 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 200012 kb
Host smart-88c8c639-8fc4-444f-8e56-750f07e405d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316843782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.316843782
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.399639744
Short name T157
Test name
Test status
Simulation time 153450349 ps
CPU time 1.17 seconds
Started Apr 04 12:29:03 PM PDT 24
Finished Apr 04 12:29:04 PM PDT 24
Peak memory 199992 kb
Host smart-7d70ff3b-cf1a-4eca-86a6-110abf33e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399639744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.399639744
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.775805241
Short name T90
Test name
Test status
Simulation time 416743546 ps
CPU time 1.92 seconds
Started Apr 04 02:41:46 PM PDT 24
Finished Apr 04 02:41:48 PM PDT 24
Peak memory 201016 kb
Host smart-ca548f3e-8208-44ee-8af0-b584d4bc5e93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775805241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
775805241
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3316637610
Short name T227
Test name
Test status
Simulation time 1898095187 ps
CPU time 6.93 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:18 PM PDT 24
Peak memory 218228 kb
Host smart-d435e189-5282-4bb5-8beb-aa0fc544e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316637610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3316637610
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.724679136
Short name T117
Test name
Test status
Simulation time 62230654 ps
CPU time 0.82 seconds
Started Apr 04 02:41:59 PM PDT 24
Finished Apr 04 02:42:00 PM PDT 24
Peak memory 200808 kb
Host smart-45a621e7-74de-4dd9-82ac-308f131db89c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724679136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.724679136
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2617025442
Short name T20
Test name
Test status
Simulation time 192118829 ps
CPU time 0.9 seconds
Started Apr 04 12:29:50 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200196 kb
Host smart-ad9f640e-7296-465e-8b6f-8578ca74251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617025442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2617025442
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1794014928
Short name T578
Test name
Test status
Simulation time 592663797 ps
CPU time 3.72 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:56 PM PDT 24
Peak memory 209176 kb
Host smart-9c4a6285-0a1d-4f4f-824c-6a41b01dce6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794014928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1794014928
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2268717367
Short name T92
Test name
Test status
Simulation time 430492460 ps
CPU time 1.81 seconds
Started Apr 04 02:42:11 PM PDT 24
Finished Apr 04 02:42:14 PM PDT 24
Peak memory 201012 kb
Host smart-5cf88fb6-903e-42a1-af26-7b7efac99241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268717367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2268717367
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2330862471
Short name T59
Test name
Test status
Simulation time 201203696 ps
CPU time 1.59 seconds
Started Apr 04 02:41:53 PM PDT 24
Finished Apr 04 02:41:55 PM PDT 24
Peak memory 200960 kb
Host smart-5b64200c-0516-41bb-b8f1-309cbff6b86f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330862471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
330862471
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.703570811
Short name T611
Test name
Test status
Simulation time 2305341260 ps
CPU time 9.49 seconds
Started Apr 04 02:42:10 PM PDT 24
Finished Apr 04 02:42:19 PM PDT 24
Peak memory 201080 kb
Host smart-3885389f-bf95-4c1b-a952-aa6f63c1602a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703570811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.703570811
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.417686843
Short name T547
Test name
Test status
Simulation time 148705686 ps
CPU time 0.94 seconds
Started Apr 04 02:42:00 PM PDT 24
Finished Apr 04 02:42:02 PM PDT 24
Peak memory 200780 kb
Host smart-18a52eb8-f92b-4e0b-8823-8401dfbd1ee5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417686843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.417686843
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3993974642
Short name T557
Test name
Test status
Simulation time 188745956 ps
CPU time 1.35 seconds
Started Apr 04 02:42:18 PM PDT 24
Finished Apr 04 02:42:19 PM PDT 24
Peak memory 211540 kb
Host smart-41473fd5-8873-4104-89c5-f29f59229118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993974642 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3993974642
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.970629512
Short name T119
Test name
Test status
Simulation time 68616357 ps
CPU time 0.79 seconds
Started Apr 04 02:41:52 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200808 kb
Host smart-bf9e8844-f903-4a06-a5ac-a86520804886
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970629512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.970629512
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2830188057
Short name T571
Test name
Test status
Simulation time 223736593 ps
CPU time 1.58 seconds
Started Apr 04 02:42:04 PM PDT 24
Finished Apr 04 02:42:05 PM PDT 24
Peak memory 201032 kb
Host smart-b2262cea-7ae0-4c90-a523-c3fc4430ee62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830188057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2830188057
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2926146016
Short name T89
Test name
Test status
Simulation time 1424884103 ps
CPU time 3.59 seconds
Started Apr 04 02:41:56 PM PDT 24
Finished Apr 04 02:41:59 PM PDT 24
Peak memory 200988 kb
Host smart-68b4d1ec-ea6a-47b4-90a3-8a28e3bf53f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926146016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2926146016
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2410968893
Short name T549
Test name
Test status
Simulation time 214583557 ps
CPU time 1.58 seconds
Started Apr 04 02:41:50 PM PDT 24
Finished Apr 04 02:41:52 PM PDT 24
Peak memory 201048 kb
Host smart-100d0cc4-a1ac-4cbe-b488-1b594b7b814c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410968893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
410968893
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2288624244
Short name T562
Test name
Test status
Simulation time 273075695 ps
CPU time 3.2 seconds
Started Apr 04 02:42:08 PM PDT 24
Finished Apr 04 02:42:11 PM PDT 24
Peak memory 201056 kb
Host smart-be39bd2a-b2d7-4dd8-9864-86825d579c76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288624244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
288624244
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4030472236
Short name T544
Test name
Test status
Simulation time 102364604 ps
CPU time 0.88 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200836 kb
Host smart-d506087b-32e7-4794-9292-9382ad924df7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030472236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
030472236
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.22961918
Short name T595
Test name
Test status
Simulation time 96488326 ps
CPU time 0.9 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200888 kb
Host smart-e1e678ea-fe98-4305-98c9-8eb729abea83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22961918 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.22961918
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.984156994
Short name T62
Test name
Test status
Simulation time 200944019 ps
CPU time 1.53 seconds
Started Apr 04 02:41:44 PM PDT 24
Finished Apr 04 02:41:46 PM PDT 24
Peak memory 201032 kb
Host smart-55150876-504b-4554-8009-575cc16ca3a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984156994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.984156994
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3315446910
Short name T597
Test name
Test status
Simulation time 492608862 ps
CPU time 1.96 seconds
Started Apr 04 02:42:18 PM PDT 24
Finished Apr 04 02:42:20 PM PDT 24
Peak memory 200972 kb
Host smart-705bf511-12f3-4fa8-84db-a535c5f81f0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315446910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3315446910
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.215870956
Short name T570
Test name
Test status
Simulation time 164772166 ps
CPU time 1.58 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 209256 kb
Host smart-c0f5a266-2984-4812-aeef-768817e98cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215870956 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.215870956
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.980143141
Short name T60
Test name
Test status
Simulation time 70492990 ps
CPU time 0.76 seconds
Started Apr 04 02:41:50 PM PDT 24
Finished Apr 04 02:41:51 PM PDT 24
Peak memory 200880 kb
Host smart-acf031b3-3cf5-4aeb-a27a-4efa01942985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980143141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.980143141
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.806781584
Short name T84
Test name
Test status
Simulation time 232704364 ps
CPU time 1.49 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200936 kb
Host smart-1ae8c373-31e1-4c45-a8cf-af1bee0c44fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806781584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.806781584
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2243315204
Short name T66
Test name
Test status
Simulation time 295583959 ps
CPU time 2.29 seconds
Started Apr 04 02:42:15 PM PDT 24
Finished Apr 04 02:42:18 PM PDT 24
Peak memory 209252 kb
Host smart-17626aa6-6b16-461f-9903-d5054a9521a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243315204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2243315204
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4166063644
Short name T134
Test name
Test status
Simulation time 791046200 ps
CPU time 3.21 seconds
Started Apr 04 02:42:08 PM PDT 24
Finished Apr 04 02:42:11 PM PDT 24
Peak memory 201024 kb
Host smart-cde7e1a6-0e41-4af3-a771-fbdc5424c158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166063644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.4166063644
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1096017105
Short name T599
Test name
Test status
Simulation time 126146866 ps
CPU time 1.06 seconds
Started Apr 04 02:42:20 PM PDT 24
Finished Apr 04 02:42:21 PM PDT 24
Peak memory 209004 kb
Host smart-68b2e2d5-6ac7-4509-acf3-0d74e4c26e22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096017105 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1096017105
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1155091251
Short name T556
Test name
Test status
Simulation time 71566318 ps
CPU time 0.81 seconds
Started Apr 04 02:41:50 PM PDT 24
Finished Apr 04 02:41:52 PM PDT 24
Peak memory 200716 kb
Host smart-c4451dea-0b45-40dc-9bce-ac3fa77d2e2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155091251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1155091251
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3957457849
Short name T564
Test name
Test status
Simulation time 125409753 ps
CPU time 1.29 seconds
Started Apr 04 02:42:22 PM PDT 24
Finished Apr 04 02:42:24 PM PDT 24
Peak memory 200992 kb
Host smart-125fec4a-ee1b-465d-8dad-b6e2a4ed5bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957457849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3957457849
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3671251166
Short name T583
Test name
Test status
Simulation time 223537442 ps
CPU time 1.63 seconds
Started Apr 04 02:42:22 PM PDT 24
Finished Apr 04 02:42:24 PM PDT 24
Peak memory 211080 kb
Host smart-7574cec3-2a75-4dfa-8093-5466a1ca0c59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671251166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3671251166
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.811446787
Short name T585
Test name
Test status
Simulation time 177910314 ps
CPU time 1.13 seconds
Started Apr 04 02:41:54 PM PDT 24
Finished Apr 04 02:41:55 PM PDT 24
Peak memory 200840 kb
Host smart-c17e4702-88e7-463d-9cb0-2dc6e7b5abdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811446787 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.811446787
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2576993044
Short name T548
Test name
Test status
Simulation time 96289989 ps
CPU time 0.94 seconds
Started Apr 04 02:42:13 PM PDT 24
Finished Apr 04 02:42:14 PM PDT 24
Peak memory 200740 kb
Host smart-95ab52f5-8dee-48d9-a5e5-962cc9311b39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576993044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2576993044
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4119413706
Short name T553
Test name
Test status
Simulation time 138403341 ps
CPU time 1.05 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200776 kb
Host smart-55da2533-99bc-4ba4-be03-f4975e420d61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119413706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4119413706
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.762267411
Short name T565
Test name
Test status
Simulation time 122073623 ps
CPU time 1.7 seconds
Started Apr 04 02:42:06 PM PDT 24
Finished Apr 04 02:42:08 PM PDT 24
Peak memory 209120 kb
Host smart-453781b8-f27b-47da-bcfe-0aa1ecb1d5a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762267411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.762267411
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3088028707
Short name T91
Test name
Test status
Simulation time 445825876 ps
CPU time 1.82 seconds
Started Apr 04 02:42:17 PM PDT 24
Finished Apr 04 02:42:19 PM PDT 24
Peak memory 200984 kb
Host smart-866ad3aa-9c4f-4be0-b450-e2378fffd49d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088028707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3088028707
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1288398900
Short name T568
Test name
Test status
Simulation time 188523213 ps
CPU time 1.38 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 209132 kb
Host smart-12093221-52c3-4043-9783-691385df1a6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288398900 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1288398900
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1358506736
Short name T593
Test name
Test status
Simulation time 82813477 ps
CPU time 0.84 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200868 kb
Host smart-0c48e823-9b01-4b7a-ad9a-fffff7c45d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358506736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1358506736
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2796222111
Short name T620
Test name
Test status
Simulation time 145451235 ps
CPU time 1.07 seconds
Started Apr 04 02:41:54 PM PDT 24
Finished Apr 04 02:41:55 PM PDT 24
Peak memory 200788 kb
Host smart-c555e0ab-f59a-4b28-b34a-e42ad5b44009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796222111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2796222111
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.589927416
Short name T550
Test name
Test status
Simulation time 139318411 ps
CPU time 1.75 seconds
Started Apr 04 02:41:54 PM PDT 24
Finished Apr 04 02:41:56 PM PDT 24
Peak memory 209192 kb
Host smart-b5da6a43-935b-4d69-ab0c-3dbcfaa39551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589927416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.589927416
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2947481370
Short name T619
Test name
Test status
Simulation time 498620066 ps
CPU time 2.16 seconds
Started Apr 04 02:41:55 PM PDT 24
Finished Apr 04 02:41:57 PM PDT 24
Peak memory 200960 kb
Host smart-e8c5cd2c-8551-48a4-bc11-f957ad648126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947481370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2947481370
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2978619773
Short name T573
Test name
Test status
Simulation time 205947025 ps
CPU time 1.36 seconds
Started Apr 04 02:42:28 PM PDT 24
Finished Apr 04 02:42:29 PM PDT 24
Peak memory 211972 kb
Host smart-719c5760-3ea9-432a-b359-8e24ea5a51d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978619773 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2978619773
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1953656200
Short name T116
Test name
Test status
Simulation time 68571000 ps
CPU time 0.78 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200868 kb
Host smart-36904e8c-7a6d-4520-9766-c119fc2cdb2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953656200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1953656200
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2041461847
Short name T576
Test name
Test status
Simulation time 216029903 ps
CPU time 1.49 seconds
Started Apr 04 02:41:53 PM PDT 24
Finished Apr 04 02:41:55 PM PDT 24
Peak memory 200972 kb
Host smart-1dab7a30-90cd-458f-b397-7210b721764e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041461847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2041461847
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1655774770
Short name T83
Test name
Test status
Simulation time 421406911 ps
CPU time 2.86 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:55 PM PDT 24
Peak memory 209208 kb
Host smart-ff2ac249-b943-464c-9597-524198ba2f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655774770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1655774770
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.318637751
Short name T592
Test name
Test status
Simulation time 487252391 ps
CPU time 2.08 seconds
Started Apr 04 02:41:59 PM PDT 24
Finished Apr 04 02:42:01 PM PDT 24
Peak memory 201052 kb
Host smart-d101f419-297f-4f96-be44-f6d952084d01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318637751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.318637751
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2887696742
Short name T614
Test name
Test status
Simulation time 122624400 ps
CPU time 1.26 seconds
Started Apr 04 02:42:17 PM PDT 24
Finished Apr 04 02:42:18 PM PDT 24
Peak memory 209080 kb
Host smart-3518ede0-c9f3-4568-bb37-042f963d7cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887696742 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2887696742
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1713797959
Short name T594
Test name
Test status
Simulation time 70656248 ps
CPU time 0.82 seconds
Started Apr 04 02:42:10 PM PDT 24
Finished Apr 04 02:42:11 PM PDT 24
Peak memory 200860 kb
Host smart-1feb7f20-89e5-4393-b0c5-6371a24f8aa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713797959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1713797959
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1485977501
Short name T61
Test name
Test status
Simulation time 138899725 ps
CPU time 1.35 seconds
Started Apr 04 02:42:28 PM PDT 24
Finished Apr 04 02:42:30 PM PDT 24
Peak memory 201012 kb
Host smart-6df9430a-57ed-49c8-802a-be98c806f310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485977501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1485977501
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4162735053
Short name T615
Test name
Test status
Simulation time 120148468 ps
CPU time 1.59 seconds
Started Apr 04 02:42:24 PM PDT 24
Finished Apr 04 02:42:26 PM PDT 24
Peak memory 217196 kb
Host smart-70e9c4fa-f6f3-4d94-a1b4-8ab0e629c251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162735053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4162735053
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4133931867
Short name T135
Test name
Test status
Simulation time 456996187 ps
CPU time 2.05 seconds
Started Apr 04 02:42:22 PM PDT 24
Finished Apr 04 02:42:24 PM PDT 24
Peak memory 201004 kb
Host smart-bc2deaf8-7c86-49df-8c18-cddec841e756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133931867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4133931867
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.893338984
Short name T618
Test name
Test status
Simulation time 166359770 ps
CPU time 1.45 seconds
Started Apr 04 02:42:17 PM PDT 24
Finished Apr 04 02:42:19 PM PDT 24
Peak memory 209324 kb
Host smart-8e8c4fa4-799c-482b-a0fb-36f22909a0d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893338984 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.893338984
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.673826730
Short name T554
Test name
Test status
Simulation time 63867067 ps
CPU time 0.77 seconds
Started Apr 04 02:42:12 PM PDT 24
Finished Apr 04 02:42:13 PM PDT 24
Peak memory 200724 kb
Host smart-20cf2b3b-ab26-404a-9df8-1ec0d692d9c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673826730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.673826730
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1216346158
Short name T574
Test name
Test status
Simulation time 146666152 ps
CPU time 1.14 seconds
Started Apr 04 02:42:09 PM PDT 24
Finished Apr 04 02:42:11 PM PDT 24
Peak memory 200892 kb
Host smart-5897720c-bad9-4951-b628-0baa9ca90edd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216346158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1216346158
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.748641553
Short name T561
Test name
Test status
Simulation time 158080116 ps
CPU time 2.36 seconds
Started Apr 04 02:42:23 PM PDT 24
Finished Apr 04 02:42:25 PM PDT 24
Peak memory 200992 kb
Host smart-09d860a7-7d8d-42f8-9069-2120e3e3e2de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748641553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.748641553
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3552709845
Short name T68
Test name
Test status
Simulation time 785958400 ps
CPU time 2.71 seconds
Started Apr 04 02:41:54 PM PDT 24
Finished Apr 04 02:41:57 PM PDT 24
Peak memory 201052 kb
Host smart-0ff0b089-9989-4e97-af6b-6354c0d312ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552709845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3552709845
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3208176314
Short name T563
Test name
Test status
Simulation time 168406777 ps
CPU time 1.19 seconds
Started Apr 04 02:41:59 PM PDT 24
Finished Apr 04 02:42:00 PM PDT 24
Peak memory 200916 kb
Host smart-ac7d348f-d962-45c1-8619-6726b41b3274
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208176314 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3208176314
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1840242261
Short name T120
Test name
Test status
Simulation time 66451081 ps
CPU time 0.77 seconds
Started Apr 04 02:42:10 PM PDT 24
Finished Apr 04 02:42:11 PM PDT 24
Peak memory 200780 kb
Host smart-b42f8c0f-9ff1-49b0-930c-1f6cc40bba9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840242261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1840242261
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.696498849
Short name T589
Test name
Test status
Simulation time 222914669 ps
CPU time 1.46 seconds
Started Apr 04 02:41:55 PM PDT 24
Finished Apr 04 02:41:56 PM PDT 24
Peak memory 201012 kb
Host smart-dab2f19b-c6e9-450d-99a6-40f590147ef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696498849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.696498849
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2683735804
Short name T98
Test name
Test status
Simulation time 240704826 ps
CPU time 1.7 seconds
Started Apr 04 02:42:21 PM PDT 24
Finished Apr 04 02:42:22 PM PDT 24
Peak memory 209176 kb
Host smart-a5001ddd-1aee-4254-a474-0e7dd6ffba4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683735804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2683735804
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4046284892
Short name T602
Test name
Test status
Simulation time 905866241 ps
CPU time 3.38 seconds
Started Apr 04 02:42:10 PM PDT 24
Finished Apr 04 02:42:13 PM PDT 24
Peak memory 201088 kb
Host smart-3e51c451-cedf-46fe-b927-63f2f634866d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046284892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.4046284892
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1998329540
Short name T63
Test name
Test status
Simulation time 109534779 ps
CPU time 1.01 seconds
Started Apr 04 02:42:06 PM PDT 24
Finished Apr 04 02:42:08 PM PDT 24
Peak memory 200848 kb
Host smart-08810462-31a5-4f21-856c-08db49942f2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998329540 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1998329540
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4056130016
Short name T555
Test name
Test status
Simulation time 77745096 ps
CPU time 0.85 seconds
Started Apr 04 02:41:59 PM PDT 24
Finished Apr 04 02:42:00 PM PDT 24
Peak memory 200872 kb
Host smart-14bd3aca-2068-41bd-8a6e-a7c4f245d2ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056130016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4056130016
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3294385418
Short name T606
Test name
Test status
Simulation time 87582381 ps
CPU time 1.02 seconds
Started Apr 04 02:42:16 PM PDT 24
Finished Apr 04 02:42:17 PM PDT 24
Peak memory 200824 kb
Host smart-3be71658-b79e-4bc3-81fc-da709dd4e9e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294385418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3294385418
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2829944402
Short name T567
Test name
Test status
Simulation time 225864284 ps
CPU time 1.87 seconds
Started Apr 04 02:42:18 PM PDT 24
Finished Apr 04 02:42:20 PM PDT 24
Peak memory 217400 kb
Host smart-c27ba750-5316-4fea-a98a-8722bb2d0d99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829944402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2829944402
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2301429809
Short name T588
Test name
Test status
Simulation time 430369697 ps
CPU time 2.01 seconds
Started Apr 04 02:42:00 PM PDT 24
Finished Apr 04 02:42:02 PM PDT 24
Peak memory 201032 kb
Host smart-460e6220-444d-44bb-b86a-baa70e8233fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301429809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2301429809
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3024279041
Short name T566
Test name
Test status
Simulation time 127703792 ps
CPU time 1.37 seconds
Started Apr 04 02:42:22 PM PDT 24
Finished Apr 04 02:42:24 PM PDT 24
Peak memory 213696 kb
Host smart-a5d50101-c350-4143-b971-491da371d3b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024279041 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3024279041
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3725005089
Short name T136
Test name
Test status
Simulation time 79355685 ps
CPU time 0.95 seconds
Started Apr 04 02:41:54 PM PDT 24
Finished Apr 04 02:42:05 PM PDT 24
Peak memory 200852 kb
Host smart-db500c94-f408-4a0e-adbe-2e149127fb4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725005089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3725005089
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3924776551
Short name T612
Test name
Test status
Simulation time 122659561 ps
CPU time 1.23 seconds
Started Apr 04 02:42:01 PM PDT 24
Finished Apr 04 02:42:03 PM PDT 24
Peak memory 200848 kb
Host smart-ac1bcc38-5941-4dde-bdd4-dba0b4cf155c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924776551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3924776551
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1529619027
Short name T586
Test name
Test status
Simulation time 119147948 ps
CPU time 1.47 seconds
Started Apr 04 02:41:54 PM PDT 24
Finished Apr 04 02:41:55 PM PDT 24
Peak memory 217292 kb
Host smart-02b538ff-88ef-42f3-be0d-2dfc60d7213c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529619027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1529619027
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1240268330
Short name T97
Test name
Test status
Simulation time 869282659 ps
CPU time 2.9 seconds
Started Apr 04 02:42:20 PM PDT 24
Finished Apr 04 02:42:23 PM PDT 24
Peak memory 200980 kb
Host smart-285d6b19-a4fa-49ac-a0f1-0a1b51d42000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240268330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1240268330
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2841364649
Short name T590
Test name
Test status
Simulation time 359279732 ps
CPU time 2.4 seconds
Started Apr 04 02:42:16 PM PDT 24
Finished Apr 04 02:42:18 PM PDT 24
Peak memory 201060 kb
Host smart-38c9c444-3394-4ff3-978b-0dcb357a7e7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841364649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
841364649
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1061602070
Short name T587
Test name
Test status
Simulation time 793238880 ps
CPU time 4.48 seconds
Started Apr 04 02:42:11 PM PDT 24
Finished Apr 04 02:42:16 PM PDT 24
Peak memory 201008 kb
Host smart-4f87bc95-282d-473c-8394-2313f176fb69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061602070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
061602070
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3951378246
Short name T617
Test name
Test status
Simulation time 125365588 ps
CPU time 0.87 seconds
Started Apr 04 02:41:50 PM PDT 24
Finished Apr 04 02:41:51 PM PDT 24
Peak memory 200868 kb
Host smart-876b7a6f-de34-4f44-a203-d06e66816775
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951378246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
951378246
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4280757412
Short name T613
Test name
Test status
Simulation time 65317424 ps
CPU time 0.76 seconds
Started Apr 04 02:41:46 PM PDT 24
Finished Apr 04 02:41:47 PM PDT 24
Peak memory 200824 kb
Host smart-fc972e6a-e204-483e-994a-840763166a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280757412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.4280757412
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2756370467
Short name T118
Test name
Test status
Simulation time 143573794 ps
CPU time 1.32 seconds
Started Apr 04 02:41:45 PM PDT 24
Finished Apr 04 02:41:47 PM PDT 24
Peak memory 201028 kb
Host smart-bf19b8d9-2f79-4092-a49d-ba16fda6be11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756370467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2756370467
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.596089418
Short name T569
Test name
Test status
Simulation time 401372226 ps
CPU time 2.79 seconds
Started Apr 04 02:41:45 PM PDT 24
Finished Apr 04 02:41:48 PM PDT 24
Peak memory 209368 kb
Host smart-b933e56b-8412-4938-b521-f8fa4681e282
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596089418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.596089418
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1262580990
Short name T94
Test name
Test status
Simulation time 439328959 ps
CPU time 1.89 seconds
Started Apr 04 02:42:22 PM PDT 24
Finished Apr 04 02:42:24 PM PDT 24
Peak memory 201012 kb
Host smart-a124930a-2800-4448-9688-047912cb1470
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262580990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1262580990
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.82657838
Short name T598
Test name
Test status
Simulation time 212482074 ps
CPU time 1.5 seconds
Started Apr 04 02:41:50 PM PDT 24
Finished Apr 04 02:41:52 PM PDT 24
Peak memory 200876 kb
Host smart-ee4fc22f-9231-430d-848e-dc06a8d79f95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82657838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.82657838
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.986061867
Short name T591
Test name
Test status
Simulation time 266327075 ps
CPU time 3.26 seconds
Started Apr 04 02:42:20 PM PDT 24
Finished Apr 04 02:42:23 PM PDT 24
Peak memory 200572 kb
Host smart-fc5f7e85-579b-43c9-b139-a2a513e89f51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986061867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.986061867
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4187831513
Short name T546
Test name
Test status
Simulation time 98444916 ps
CPU time 0.82 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200772 kb
Host smart-35fa0837-712b-472b-80e3-532395aca316
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187831513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
187831513
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1711957753
Short name T95
Test name
Test status
Simulation time 170113417 ps
CPU time 1.59 seconds
Started Apr 04 02:42:20 PM PDT 24
Finished Apr 04 02:42:21 PM PDT 24
Peak memory 213108 kb
Host smart-839e9492-ae62-40a0-8476-2f7a6f8f3f59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711957753 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1711957753
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.244087856
Short name T616
Test name
Test status
Simulation time 55199618 ps
CPU time 0.74 seconds
Started Apr 04 02:41:50 PM PDT 24
Finished Apr 04 02:41:51 PM PDT 24
Peak memory 200780 kb
Host smart-1f80f0fd-ddfb-444b-a7d1-2de5b4377051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244087856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.244087856
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.510277153
Short name T559
Test name
Test status
Simulation time 74572692 ps
CPU time 0.99 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200780 kb
Host smart-be12b4af-3c7a-42b1-a2dc-8dd556dd4c6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510277153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.510277153
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.974812994
Short name T603
Test name
Test status
Simulation time 189700012 ps
CPU time 2.68 seconds
Started Apr 04 02:42:10 PM PDT 24
Finished Apr 04 02:42:13 PM PDT 24
Peak memory 212552 kb
Host smart-e70c9bc6-acc4-42bc-9185-82a8c3a5b458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974812994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.974812994
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.674706786
Short name T85
Test name
Test status
Simulation time 226410197 ps
CPU time 1.63 seconds
Started Apr 04 02:41:50 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 209236 kb
Host smart-e39df054-090f-4921-8aff-7b5fc5876bcf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674706786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.674706786
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1071221666
Short name T604
Test name
Test status
Simulation time 788918579 ps
CPU time 4.22 seconds
Started Apr 04 02:42:02 PM PDT 24
Finished Apr 04 02:42:06 PM PDT 24
Peak memory 200920 kb
Host smart-276c8390-bb30-459a-8c33-9e17d7bff1cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071221666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
071221666
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1510805796
Short name T545
Test name
Test status
Simulation time 93497252 ps
CPU time 0.81 seconds
Started Apr 04 02:42:18 PM PDT 24
Finished Apr 04 02:42:19 PM PDT 24
Peak memory 200740 kb
Host smart-c01a66a1-1d9d-4ce1-bfb2-eff6c710fd3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510805796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
510805796
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2358504518
Short name T104
Test name
Test status
Simulation time 177861243 ps
CPU time 1.23 seconds
Started Apr 04 02:41:59 PM PDT 24
Finished Apr 04 02:42:00 PM PDT 24
Peak memory 200932 kb
Host smart-8e0b47a5-f315-4e35-be4a-df393cc2903c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358504518 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2358504518
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.487990294
Short name T607
Test name
Test status
Simulation time 80614496 ps
CPU time 0.84 seconds
Started Apr 04 02:42:25 PM PDT 24
Finished Apr 04 02:42:26 PM PDT 24
Peak memory 200736 kb
Host smart-569cd9a5-fead-428e-967e-e917722b74c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487990294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.487990294
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1145843438
Short name T558
Test name
Test status
Simulation time 88280113 ps
CPU time 0.98 seconds
Started Apr 04 02:42:13 PM PDT 24
Finished Apr 04 02:42:14 PM PDT 24
Peak memory 200744 kb
Host smart-3b379d14-eb7c-4cee-bb44-c29e089be9c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145843438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1145843438
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2524222976
Short name T88
Test name
Test status
Simulation time 181452422 ps
CPU time 2.42 seconds
Started Apr 04 02:41:54 PM PDT 24
Finished Apr 04 02:42:02 PM PDT 24
Peak memory 212260 kb
Host smart-cdaa9c4e-45cc-44d3-bafb-76085992a339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524222976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2524222976
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2429478743
Short name T96
Test name
Test status
Simulation time 139077441 ps
CPU time 1.1 seconds
Started Apr 04 02:41:59 PM PDT 24
Finished Apr 04 02:42:00 PM PDT 24
Peak memory 209040 kb
Host smart-5f82d050-bf75-4531-b445-1854656f8041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429478743 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2429478743
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3505949354
Short name T596
Test name
Test status
Simulation time 94779444 ps
CPU time 0.85 seconds
Started Apr 04 02:42:08 PM PDT 24
Finished Apr 04 02:42:09 PM PDT 24
Peak memory 200824 kb
Host smart-bec2b84c-c2e7-470c-9e66-a60cc6ced8b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505949354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3505949354
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4142933596
Short name T605
Test name
Test status
Simulation time 132833212 ps
CPU time 1.3 seconds
Started Apr 04 02:42:22 PM PDT 24
Finished Apr 04 02:42:23 PM PDT 24
Peak memory 200936 kb
Host smart-594bfa07-acd8-482e-be2f-5f466708ddfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142933596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4142933596
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3057163191
Short name T580
Test name
Test status
Simulation time 165695758 ps
CPU time 2.54 seconds
Started Apr 04 02:42:24 PM PDT 24
Finished Apr 04 02:42:27 PM PDT 24
Peak memory 209124 kb
Host smart-a3dc5ae2-85eb-422b-b28b-9fdfc9cb2aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057163191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3057163191
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1168668342
Short name T65
Test name
Test status
Simulation time 488822201 ps
CPU time 2.02 seconds
Started Apr 04 02:42:24 PM PDT 24
Finished Apr 04 02:42:26 PM PDT 24
Peak memory 200936 kb
Host smart-894ffac5-ae9e-4f31-afd1-5cd3922efdc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168668342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1168668342
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2782064402
Short name T608
Test name
Test status
Simulation time 135909206 ps
CPU time 0.99 seconds
Started Apr 04 02:41:53 PM PDT 24
Finished Apr 04 02:41:55 PM PDT 24
Peak memory 200852 kb
Host smart-8fa7092b-671c-4698-a410-c91d427a7c28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782064402 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2782064402
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3457237532
Short name T601
Test name
Test status
Simulation time 93110304 ps
CPU time 0.78 seconds
Started Apr 04 02:41:53 PM PDT 24
Finished Apr 04 02:41:54 PM PDT 24
Peak memory 200796 kb
Host smart-4efe5f19-ac3b-4285-b67d-9db1ae938528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457237532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3457237532
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.83213584
Short name T115
Test name
Test status
Simulation time 146619584 ps
CPU time 1.09 seconds
Started Apr 04 02:42:24 PM PDT 24
Finished Apr 04 02:42:25 PM PDT 24
Peak memory 200752 kb
Host smart-40fe4451-170e-47ef-b630-bc11c755df4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83213584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same
_csr_outstanding.83213584
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1572363761
Short name T552
Test name
Test status
Simulation time 322625690 ps
CPU time 2.43 seconds
Started Apr 04 02:42:08 PM PDT 24
Finished Apr 04 02:42:10 PM PDT 24
Peak memory 212468 kb
Host smart-0824daab-80d7-46e2-a716-70583cea6f36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572363761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1572363761
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.278893994
Short name T93
Test name
Test status
Simulation time 427038217 ps
CPU time 1.86 seconds
Started Apr 04 02:41:54 PM PDT 24
Finished Apr 04 02:41:57 PM PDT 24
Peak memory 201064 kb
Host smart-63d2210f-fd51-4a47-a821-7c49d3bbb85e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278893994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
278893994
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3005340216
Short name T610
Test name
Test status
Simulation time 112522815 ps
CPU time 1.04 seconds
Started Apr 04 02:41:59 PM PDT 24
Finished Apr 04 02:42:00 PM PDT 24
Peak memory 211128 kb
Host smart-ed73a625-3079-45b4-9bfd-44b6656cd445
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005340216 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3005340216
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4015472045
Short name T582
Test name
Test status
Simulation time 61738836 ps
CPU time 0.78 seconds
Started Apr 04 02:42:19 PM PDT 24
Finished Apr 04 02:42:20 PM PDT 24
Peak memory 200764 kb
Host smart-8eb82788-0b2e-4d57-8a43-ff74b50ca5b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015472045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4015472045
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1337409241
Short name T551
Test name
Test status
Simulation time 285612070 ps
CPU time 1.69 seconds
Started Apr 04 02:41:58 PM PDT 24
Finished Apr 04 02:42:00 PM PDT 24
Peak memory 200948 kb
Host smart-30b03738-a9a4-420a-870e-4a03a2c4cf97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337409241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1337409241
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4052752662
Short name T560
Test name
Test status
Simulation time 139204146 ps
CPU time 2.03 seconds
Started Apr 04 02:42:01 PM PDT 24
Finished Apr 04 02:42:04 PM PDT 24
Peak memory 217132 kb
Host smart-3686a175-fc62-440d-af23-1bab5dcb96b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052752662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4052752662
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3499145636
Short name T577
Test name
Test status
Simulation time 913696518 ps
CPU time 3.38 seconds
Started Apr 04 02:41:58 PM PDT 24
Finished Apr 04 02:42:01 PM PDT 24
Peak memory 201084 kb
Host smart-f73ee92e-7729-4f5b-8508-b27b56794b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499145636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3499145636
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.12979651
Short name T584
Test name
Test status
Simulation time 175499528 ps
CPU time 1.19 seconds
Started Apr 04 02:41:47 PM PDT 24
Finished Apr 04 02:41:49 PM PDT 24
Peak memory 210628 kb
Host smart-cc92b91a-604f-4268-a4a1-283aae1c3678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12979651 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.12979651
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1984871421
Short name T107
Test name
Test status
Simulation time 65372180 ps
CPU time 0.74 seconds
Started Apr 04 02:41:56 PM PDT 24
Finished Apr 04 02:41:57 PM PDT 24
Peak memory 200812 kb
Host smart-b9653309-315c-4d4e-95f6-a9f406f5c064
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984871421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1984871421
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2603634687
Short name T579
Test name
Test status
Simulation time 274873268 ps
CPU time 1.52 seconds
Started Apr 04 02:42:07 PM PDT 24
Finished Apr 04 02:42:09 PM PDT 24
Peak memory 201084 kb
Host smart-4c412087-cc33-4263-b983-b09e6655bdad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603634687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2603634687
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1918932026
Short name T572
Test name
Test status
Simulation time 128688666 ps
CPU time 1.75 seconds
Started Apr 04 02:42:01 PM PDT 24
Finished Apr 04 02:42:03 PM PDT 24
Peak memory 211628 kb
Host smart-81ef95d8-1a5c-49d3-8a50-f2bbea803cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918932026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1918932026
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3878452036
Short name T600
Test name
Test status
Simulation time 429150895 ps
CPU time 1.71 seconds
Started Apr 04 02:41:59 PM PDT 24
Finished Apr 04 02:42:00 PM PDT 24
Peak memory 201052 kb
Host smart-50c577ce-5ba2-48f8-8ba9-65a49c26ef32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878452036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3878452036
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.57558785
Short name T581
Test name
Test status
Simulation time 148409251 ps
CPU time 1.24 seconds
Started Apr 04 02:42:07 PM PDT 24
Finished Apr 04 02:42:08 PM PDT 24
Peak memory 209040 kb
Host smart-077b19f5-af42-46ee-acaf-97ebc12fb573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57558785 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.57558785
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.99027237
Short name T609
Test name
Test status
Simulation time 88114159 ps
CPU time 0.91 seconds
Started Apr 04 02:41:54 PM PDT 24
Finished Apr 04 02:41:55 PM PDT 24
Peak memory 200792 kb
Host smart-6515d231-2a7d-4bf7-8974-5af6470d5ce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99027237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.99027237
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2222672032
Short name T121
Test name
Test status
Simulation time 255732527 ps
CPU time 1.49 seconds
Started Apr 04 02:41:51 PM PDT 24
Finished Apr 04 02:41:53 PM PDT 24
Peak memory 200972 kb
Host smart-d8a9a09e-e696-492a-a611-ebfee25c862b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222672032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2222672032
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2210373522
Short name T575
Test name
Test status
Simulation time 226581006 ps
CPU time 1.85 seconds
Started Apr 04 02:42:09 PM PDT 24
Finished Apr 04 02:42:11 PM PDT 24
Peak memory 217264 kb
Host smart-d0891782-144c-4bcc-8db4-dc18ea871744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210373522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2210373522
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1020284494
Short name T67
Test name
Test status
Simulation time 510165203 ps
CPU time 1.98 seconds
Started Apr 04 02:42:04 PM PDT 24
Finished Apr 04 02:42:06 PM PDT 24
Peak memory 201016 kb
Host smart-4d730c62-86da-4e15-ad15-b150b4db1a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020284494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1020284494
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2555662946
Short name T200
Test name
Test status
Simulation time 72900368 ps
CPU time 0.78 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 199964 kb
Host smart-f9d614e1-714a-4165-a30b-ad7baa61138f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555662946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2555662946
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2870084767
Short name T43
Test name
Test status
Simulation time 1233043537 ps
CPU time 6.19 seconds
Started Apr 04 12:29:07 PM PDT 24
Finished Apr 04 12:29:14 PM PDT 24
Peak memory 218292 kb
Host smart-29cecfcb-89bd-4229-964c-78fd4517231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870084767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2870084767
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1240215753
Short name T297
Test name
Test status
Simulation time 244124950 ps
CPU time 1.11 seconds
Started Apr 04 12:29:06 PM PDT 24
Finished Apr 04 12:29:08 PM PDT 24
Peak memory 217780 kb
Host smart-6cbcea84-d7a1-4af2-9f9b-1807ea73894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240215753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1240215753
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1757105856
Short name T510
Test name
Test status
Simulation time 168791396 ps
CPU time 0.85 seconds
Started Apr 04 12:27:49 PM PDT 24
Finished Apr 04 12:27:50 PM PDT 24
Peak memory 199400 kb
Host smart-9c67be59-448b-43c7-bf68-d8ebcb883a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757105856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1757105856
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.4073957814
Short name T452
Test name
Test status
Simulation time 1677165253 ps
CPU time 5.92 seconds
Started Apr 04 12:27:49 PM PDT 24
Finished Apr 04 12:27:55 PM PDT 24
Peak memory 200248 kb
Host smart-312559cb-bc4a-4c48-a66f-c625c1d2ff98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073957814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.4073957814
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1355497450
Short name T220
Test name
Test status
Simulation time 121897575 ps
CPU time 1.28 seconds
Started Apr 04 12:28:48 PM PDT 24
Finished Apr 04 12:28:50 PM PDT 24
Peak memory 199716 kb
Host smart-a84e804b-736b-4137-b5d6-56ec5cce1b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355497450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1355497450
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2010720213
Short name T246
Test name
Test status
Simulation time 147166425 ps
CPU time 1.01 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:28:59 PM PDT 24
Peak memory 200264 kb
Host smart-4383eea3-b680-41d5-b3f7-2c58ea0a5505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010720213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2010720213
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3149681735
Short name T321
Test name
Test status
Simulation time 520329859 ps
CPU time 2.57 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 199660 kb
Host smart-3c5ecbb3-45bd-45e9-9e7b-15f0cb37ec52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149681735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3149681735
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.101060685
Short name T403
Test name
Test status
Simulation time 254660068 ps
CPU time 1.37 seconds
Started Apr 04 12:29:05 PM PDT 24
Finished Apr 04 12:29:07 PM PDT 24
Peak memory 200352 kb
Host smart-f91434a1-7f4e-4e47-adb1-dcbf67ab6d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101060685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.101060685
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2273074770
Short name T422
Test name
Test status
Simulation time 75861940 ps
CPU time 0.84 seconds
Started Apr 04 12:29:07 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 200224 kb
Host smart-556f5d6b-f927-4509-bc29-e73c477c483b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273074770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2273074770
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1785035031
Short name T267
Test name
Test status
Simulation time 1224584837 ps
CPU time 5.43 seconds
Started Apr 04 12:29:03 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 217932 kb
Host smart-fc526ee9-0f67-4b12-a672-50419b071587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785035031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1785035031
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.981542042
Short name T299
Test name
Test status
Simulation time 244870916 ps
CPU time 0.99 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:28:56 PM PDT 24
Peak memory 217620 kb
Host smart-b283521c-57b3-40ab-8ee2-0bf1a2f72d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981542042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.981542042
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.40785495
Short name T223
Test name
Test status
Simulation time 117283567 ps
CPU time 0.76 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 200232 kb
Host smart-1394dd1d-5ec2-4db5-b33c-8343b5be021f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40785495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.40785495
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1416545450
Short name T367
Test name
Test status
Simulation time 1469158524 ps
CPU time 5.71 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:58 PM PDT 24
Peak memory 199360 kb
Host smart-677bf487-129c-4b33-9649-b3205ea07407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416545450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1416545450
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2815520965
Short name T72
Test name
Test status
Simulation time 8280264612 ps
CPU time 14.18 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 217460 kb
Host smart-5b6a47a3-ac76-45e1-8015-d7c8eafddea6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815520965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2815520965
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.4236998790
Short name T392
Test name
Test status
Simulation time 152150017 ps
CPU time 1.02 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 200340 kb
Host smart-34fd299a-cfab-4029-9c4f-aeed97303bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236998790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.4236998790
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.22653983
Short name T233
Test name
Test status
Simulation time 264908720 ps
CPU time 1.63 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 200584 kb
Host smart-34b17dec-dcba-4b08-8b8b-d210ce3159d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22653983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.22653983
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2645085800
Short name T295
Test name
Test status
Simulation time 2948434982 ps
CPU time 12.23 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:29:06 PM PDT 24
Peak memory 199620 kb
Host smart-e58f6a31-dd0b-41b3-ab32-998e01bc2667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645085800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2645085800
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.676366154
Short name T215
Test name
Test status
Simulation time 351410781 ps
CPU time 2.15 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 199952 kb
Host smart-44e65e7b-d2dc-44c9-8ca5-1eb5066bc6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676366154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.676366154
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.600685440
Short name T265
Test name
Test status
Simulation time 77487139 ps
CPU time 0.86 seconds
Started Apr 04 12:29:28 PM PDT 24
Finished Apr 04 12:29:29 PM PDT 24
Peak memory 200260 kb
Host smart-52893047-1ada-4816-987f-0cbd23972a34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600685440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.600685440
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1708302540
Short name T9
Test name
Test status
Simulation time 1224242772 ps
CPU time 5.65 seconds
Started Apr 04 12:29:37 PM PDT 24
Finished Apr 04 12:29:42 PM PDT 24
Peak memory 218288 kb
Host smart-101a4287-a2b2-49ba-8088-9bea7e65c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708302540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1708302540
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2538833290
Short name T525
Test name
Test status
Simulation time 244866758 ps
CPU time 1.13 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 217820 kb
Host smart-fcd7dae2-c828-4fc1-9c58-626e821e0975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538833290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2538833290
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2989480686
Short name T401
Test name
Test status
Simulation time 144196873 ps
CPU time 0.83 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 200336 kb
Host smart-baa56584-c269-404d-8402-fad44648ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989480686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2989480686
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2908126703
Short name T494
Test name
Test status
Simulation time 956367381 ps
CPU time 4.6 seconds
Started Apr 04 12:30:05 PM PDT 24
Finished Apr 04 12:30:10 PM PDT 24
Peak memory 200632 kb
Host smart-e5075c53-bc94-4a44-819f-b66bc5400bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908126703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2908126703
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1682579799
Short name T153
Test name
Test status
Simulation time 185790303 ps
CPU time 1.2 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:10 PM PDT 24
Peak memory 200504 kb
Host smart-e9ef5766-fe83-4af8-8573-e6733faa249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682579799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1682579799
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2613129870
Short name T394
Test name
Test status
Simulation time 115357715 ps
CPU time 1.26 seconds
Started Apr 04 12:29:27 PM PDT 24
Finished Apr 04 12:29:29 PM PDT 24
Peak memory 200580 kb
Host smart-123a1f8f-31c5-49ab-9216-a6365ac8c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613129870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2613129870
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.4039516730
Short name T110
Test name
Test status
Simulation time 6628783530 ps
CPU time 29.69 seconds
Started Apr 04 12:29:34 PM PDT 24
Finished Apr 04 12:30:04 PM PDT 24
Peak memory 208812 kb
Host smart-0f77e157-4e1c-4b5b-a228-864fbf5a3450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039516730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.4039516730
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3573330773
Short name T3
Test name
Test status
Simulation time 501118974 ps
CPU time 3.03 seconds
Started Apr 04 12:29:06 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 200524 kb
Host smart-d142037b-4bf0-410b-b839-31a538ab9893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573330773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3573330773
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1334826251
Short name T338
Test name
Test status
Simulation time 134284615 ps
CPU time 0.96 seconds
Started Apr 04 12:29:53 PM PDT 24
Finished Apr 04 12:29:54 PM PDT 24
Peak memory 200424 kb
Host smart-0c9da799-8944-4218-8e4b-4f5eb0fc75b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334826251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1334826251
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3842732764
Short name T293
Test name
Test status
Simulation time 73658558 ps
CPU time 0.78 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 200232 kb
Host smart-949e4143-f4e7-443a-ad2c-27d65bf0aabe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842732764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3842732764
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.860637644
Short name T47
Test name
Test status
Simulation time 2167045130 ps
CPU time 7.45 seconds
Started Apr 04 12:29:55 PM PDT 24
Finished Apr 04 12:30:04 PM PDT 24
Peak memory 218352 kb
Host smart-6a0b7f3a-7ea9-4017-9fc3-0d5ac37e7cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860637644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.860637644
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.612706640
Short name T82
Test name
Test status
Simulation time 245166313 ps
CPU time 1.2 seconds
Started Apr 04 12:29:20 PM PDT 24
Finished Apr 04 12:29:22 PM PDT 24
Peak memory 217872 kb
Host smart-7fc4d309-efcc-418d-83f1-fdcba51cbd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612706640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.612706640
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3910381893
Short name T201
Test name
Test status
Simulation time 200539547 ps
CPU time 0.95 seconds
Started Apr 04 12:29:19 PM PDT 24
Finished Apr 04 12:29:20 PM PDT 24
Peak memory 200252 kb
Host smart-3892641f-53e4-4dfe-80aa-3475110b6392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910381893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3910381893
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2663370480
Short name T150
Test name
Test status
Simulation time 1788630919 ps
CPU time 6.86 seconds
Started Apr 04 12:29:19 PM PDT 24
Finished Apr 04 12:29:26 PM PDT 24
Peak memory 200552 kb
Host smart-6a7d8e94-9cda-449e-8adc-6083849d08e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663370480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2663370480
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3979105893
Short name T248
Test name
Test status
Simulation time 140070205 ps
CPU time 1.16 seconds
Started Apr 04 12:29:54 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 200400 kb
Host smart-5eceef91-b1f7-46e5-b6f5-f13431374925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979105893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3979105893
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1315092076
Short name T306
Test name
Test status
Simulation time 122077534 ps
CPU time 1.21 seconds
Started Apr 04 12:29:12 PM PDT 24
Finished Apr 04 12:29:13 PM PDT 24
Peak memory 200580 kb
Host smart-d774721e-7bd8-456b-97e1-4bc314fbc488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315092076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1315092076
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2237597711
Short name T112
Test name
Test status
Simulation time 5166313517 ps
CPU time 23.35 seconds
Started Apr 04 12:29:24 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200628 kb
Host smart-d394141d-d2a1-4ca7-ad2e-193b03a5cc4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237597711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2237597711
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.18200738
Short name T443
Test name
Test status
Simulation time 425158915 ps
CPU time 2.38 seconds
Started Apr 04 12:29:56 PM PDT 24
Finished Apr 04 12:29:59 PM PDT 24
Peak memory 200424 kb
Host smart-4f516f7e-dffe-43ad-aeda-d50081251065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18200738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.18200738
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2922006050
Short name T457
Test name
Test status
Simulation time 63493346 ps
CPU time 0.77 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:02 PM PDT 24
Peak memory 200464 kb
Host smart-75574745-a9be-483d-8c9d-370abafab9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922006050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2922006050
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1963400114
Short name T229
Test name
Test status
Simulation time 74998274 ps
CPU time 0.77 seconds
Started Apr 04 12:29:18 PM PDT 24
Finished Apr 04 12:29:18 PM PDT 24
Peak memory 200312 kb
Host smart-4e4c5bac-e94b-4634-a643-59577480fd2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963400114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1963400114
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3780927449
Short name T490
Test name
Test status
Simulation time 2356422786 ps
CPU time 8.59 seconds
Started Apr 04 12:29:54 PM PDT 24
Finished Apr 04 12:30:03 PM PDT 24
Peak memory 222408 kb
Host smart-3a99ef09-1687-43de-9031-c7b0cc4f035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780927449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3780927449
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1393646622
Short name T179
Test name
Test status
Simulation time 244773299 ps
CPU time 1.05 seconds
Started Apr 04 12:29:54 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 217856 kb
Host smart-357263ad-da13-450d-b7b4-53ef7c050bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393646622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1393646622
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.726351586
Short name T399
Test name
Test status
Simulation time 194743686 ps
CPU time 0.97 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 200216 kb
Host smart-c21fdfa2-b03d-4002-afcb-ae06885f8eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726351586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.726351586
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3915552899
Short name T257
Test name
Test status
Simulation time 752529972 ps
CPU time 3.91 seconds
Started Apr 04 12:29:44 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200552 kb
Host smart-062e9e6b-9fca-4630-a916-a8d606a7ca21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915552899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3915552899
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.140326259
Short name T176
Test name
Test status
Simulation time 113857070 ps
CPU time 1.06 seconds
Started Apr 04 12:30:07 PM PDT 24
Finished Apr 04 12:30:09 PM PDT 24
Peak memory 200456 kb
Host smart-b8372c16-0c30-4469-a69f-d79442f11159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140326259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.140326259
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1590023933
Short name T207
Test name
Test status
Simulation time 244779669 ps
CPU time 1.49 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:24 PM PDT 24
Peak memory 200548 kb
Host smart-f6bcf3ee-1eae-457c-902c-3536ce508884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590023933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1590023933
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3749585595
Short name T314
Test name
Test status
Simulation time 3585313082 ps
CPU time 16.41 seconds
Started Apr 04 12:29:18 PM PDT 24
Finished Apr 04 12:29:35 PM PDT 24
Peak memory 200656 kb
Host smart-45914e62-dc6f-49cc-b12f-c168a0aa4002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749585595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3749585595
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3938741985
Short name T238
Test name
Test status
Simulation time 135363700 ps
CPU time 1.59 seconds
Started Apr 04 12:29:19 PM PDT 24
Finished Apr 04 12:29:20 PM PDT 24
Peak memory 208696 kb
Host smart-7b884a82-1d04-4108-a2bd-365da9905a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938741985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3938741985
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2751251972
Short name T493
Test name
Test status
Simulation time 173950740 ps
CPU time 1.11 seconds
Started Apr 04 12:29:21 PM PDT 24
Finished Apr 04 12:29:23 PM PDT 24
Peak memory 200376 kb
Host smart-b3f815aa-524e-4152-86e1-60873c382930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751251972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2751251972
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2322113234
Short name T289
Test name
Test status
Simulation time 56943735 ps
CPU time 0.77 seconds
Started Apr 04 12:29:28 PM PDT 24
Finished Apr 04 12:29:29 PM PDT 24
Peak memory 200252 kb
Host smart-b418a651-f349-4860-9e04-63574e617d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322113234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2322113234
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3407359657
Short name T44
Test name
Test status
Simulation time 1230702855 ps
CPU time 5.28 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:28 PM PDT 24
Peak memory 222272 kb
Host smart-260190b1-d231-45c2-a576-03d4f990b7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407359657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3407359657
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.853105571
Short name T225
Test name
Test status
Simulation time 266363306 ps
CPU time 1.11 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 217868 kb
Host smart-ae6cc2e6-e4fb-4be3-b0ad-bee996da3eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853105571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.853105571
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2540592266
Short name T196
Test name
Test status
Simulation time 1551467491 ps
CPU time 5.5 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:28 PM PDT 24
Peak memory 200552 kb
Host smart-9649df45-b111-4cf0-aa3d-985e97fc7201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540592266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2540592266
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.260528835
Short name T34
Test name
Test status
Simulation time 110241797 ps
CPU time 1.01 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 200356 kb
Host smart-4da38f1c-6ab2-4d2f-84c8-c76fdd793514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260528835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.260528835
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2017782106
Short name T310
Test name
Test status
Simulation time 205914644 ps
CPU time 1.42 seconds
Started Apr 04 12:29:20 PM PDT 24
Finished Apr 04 12:29:22 PM PDT 24
Peak memory 200544 kb
Host smart-8b23f0c3-0e46-4d43-82a0-d1bfddb8bdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017782106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2017782106
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.71658310
Short name T302
Test name
Test status
Simulation time 16861082223 ps
CPU time 63.81 seconds
Started Apr 04 12:29:38 PM PDT 24
Finished Apr 04 12:30:42 PM PDT 24
Peak memory 208852 kb
Host smart-d8967d39-5be0-41b3-ba6a-e3e87af81d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71658310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.71658310
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3214648351
Short name T174
Test name
Test status
Simulation time 518152807 ps
CPU time 3.12 seconds
Started Apr 04 12:29:18 PM PDT 24
Finished Apr 04 12:29:22 PM PDT 24
Peak memory 200464 kb
Host smart-1799b03c-27c4-44f1-9ed9-bf6cb0566c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214648351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3214648351
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.617887460
Short name T456
Test name
Test status
Simulation time 209650541 ps
CPU time 1.3 seconds
Started Apr 04 12:29:21 PM PDT 24
Finished Apr 04 12:29:22 PM PDT 24
Peak memory 200396 kb
Host smart-013f7c58-5021-42e1-a07c-12d8e4990ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617887460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.617887460
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3469843165
Short name T261
Test name
Test status
Simulation time 1224675384 ps
CPU time 5.21 seconds
Started Apr 04 12:29:41 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 218276 kb
Host smart-9b537a2b-1bc8-4db9-a225-3df72c3a46b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469843165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3469843165
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3650269847
Short name T431
Test name
Test status
Simulation time 243871764 ps
CPU time 1.15 seconds
Started Apr 04 12:30:59 PM PDT 24
Finished Apr 04 12:31:01 PM PDT 24
Peak memory 217860 kb
Host smart-e14cd26d-9bc2-4b88-a658-b880a2ef76a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650269847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3650269847
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2242296387
Short name T504
Test name
Test status
Simulation time 129198717 ps
CPU time 0.86 seconds
Started Apr 04 12:29:50 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200196 kb
Host smart-4520b875-131a-4287-a17b-14012f9e7120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242296387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2242296387
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4186595919
Short name T111
Test name
Test status
Simulation time 1851344291 ps
CPU time 6.37 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 200564 kb
Host smart-d2ef2dee-f325-49ea-921c-834f4456e684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186595919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4186595919
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.656715223
Short name T499
Test name
Test status
Simulation time 96245086 ps
CPU time 1.03 seconds
Started Apr 04 12:30:39 PM PDT 24
Finished Apr 04 12:30:41 PM PDT 24
Peak memory 200368 kb
Host smart-8f6667a6-3006-45c1-a4bb-6516d8212faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656715223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.656715223
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.542088720
Short name T232
Test name
Test status
Simulation time 257206158 ps
CPU time 1.41 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:30:17 PM PDT 24
Peak memory 200604 kb
Host smart-9d7ba39c-2f0a-4d74-bbe0-64c24a2d33a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542088720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.542088720
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2600148984
Short name T449
Test name
Test status
Simulation time 2755502787 ps
CPU time 12.49 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:30:02 PM PDT 24
Peak memory 200544 kb
Host smart-4eed46b0-ca9d-4ef0-a80f-7fd37ca7d40f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600148984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2600148984
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2875738973
Short name T30
Test name
Test status
Simulation time 364320768 ps
CPU time 2.23 seconds
Started Apr 04 12:29:50 PM PDT 24
Finished Apr 04 12:29:52 PM PDT 24
Peak memory 200372 kb
Host smart-a9bacf86-31ac-4a89-ac51-e8d55cfdcae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875738973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2875738973
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2100014451
Short name T278
Test name
Test status
Simulation time 205539845 ps
CPU time 1.3 seconds
Started Apr 04 12:30:18 PM PDT 24
Finished Apr 04 12:30:20 PM PDT 24
Peak memory 200368 kb
Host smart-fea2242d-988a-4440-a66d-dd881512152b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100014451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2100014451
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3900994029
Short name T247
Test name
Test status
Simulation time 82239555 ps
CPU time 0.77 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:40 PM PDT 24
Peak memory 200240 kb
Host smart-0160cfe3-7067-435a-97ef-ef94189bb9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900994029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3900994029
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1520636180
Short name T436
Test name
Test status
Simulation time 1241254030 ps
CPU time 5.37 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 221480 kb
Host smart-5f0fb244-d33d-4c9e-a251-65b62f50a21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520636180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1520636180
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3647490263
Short name T165
Test name
Test status
Simulation time 243525415 ps
CPU time 1.11 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 218028 kb
Host smart-141e5e46-b9d5-42c5-94a3-7cc94b34d75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647490263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3647490263
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.837459240
Short name T342
Test name
Test status
Simulation time 115371908 ps
CPU time 0.8 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:30:56 PM PDT 24
Peak memory 200312 kb
Host smart-090736b9-da09-4da6-9c36-5904caaf95eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837459240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.837459240
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1314764126
Short name T204
Test name
Test status
Simulation time 860830842 ps
CPU time 4.19 seconds
Started Apr 04 12:30:18 PM PDT 24
Finished Apr 04 12:30:23 PM PDT 24
Peak memory 200632 kb
Host smart-18b0e18d-4375-4b33-9071-502b33d34752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314764126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1314764126
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3789029589
Short name T496
Test name
Test status
Simulation time 102908968 ps
CPU time 0.98 seconds
Started Apr 04 12:30:58 PM PDT 24
Finished Apr 04 12:30:59 PM PDT 24
Peak memory 200460 kb
Host smart-729428e1-b11b-4c6c-a07f-26c6f2b8c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789029589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3789029589
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.974162245
Short name T514
Test name
Test status
Simulation time 108905599 ps
CPU time 1.17 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:31:24 PM PDT 24
Peak memory 200564 kb
Host smart-b4f438c6-f4a2-4977-ac15-f39806b79fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974162245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.974162245
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1764151965
Short name T8
Test name
Test status
Simulation time 3847983437 ps
CPU time 16.91 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:31:40 PM PDT 24
Peak memory 209528 kb
Host smart-52c01e3c-01e6-4329-a3b2-55d94956dcf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764151965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1764151965
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2687298826
Short name T212
Test name
Test status
Simulation time 512918726 ps
CPU time 2.83 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:30 PM PDT 24
Peak memory 200516 kb
Host smart-fd628cbc-7f60-42ee-8a2e-82b36371561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687298826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2687298826
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3737167013
Short name T414
Test name
Test status
Simulation time 108022761 ps
CPU time 1.02 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:30:57 PM PDT 24
Peak memory 200464 kb
Host smart-77e22794-c1f0-43e5-9f6d-89f4d3b37b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737167013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3737167013
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3309598157
Short name T360
Test name
Test status
Simulation time 94658106 ps
CPU time 0.86 seconds
Started Apr 04 12:31:39 PM PDT 24
Finished Apr 04 12:31:40 PM PDT 24
Peak memory 200392 kb
Host smart-e5f18837-f669-4660-86fa-ddad26594ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309598157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3309598157
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1206848571
Short name T37
Test name
Test status
Simulation time 1892345732 ps
CPU time 7.23 seconds
Started Apr 04 12:30:41 PM PDT 24
Finished Apr 04 12:30:48 PM PDT 24
Peak memory 218252 kb
Host smart-74a5436c-9a14-4be5-bbcf-e0003b4cff85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206848571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1206848571
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2531677318
Short name T406
Test name
Test status
Simulation time 244452739 ps
CPU time 1.05 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 218044 kb
Host smart-163bf47f-6a8c-48a0-874b-c162e1689e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531677318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2531677318
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.168538265
Short name T296
Test name
Test status
Simulation time 90480016 ps
CPU time 0.74 seconds
Started Apr 04 12:30:52 PM PDT 24
Finished Apr 04 12:30:53 PM PDT 24
Peak memory 200340 kb
Host smart-ffe193af-3371-4244-a8c5-c1d3d83d83cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168538265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.168538265
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4250380699
Short name T113
Test name
Test status
Simulation time 777111464 ps
CPU time 3.71 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200552 kb
Host smart-136534b7-b565-4cf5-83fa-5ec10152f0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250380699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4250380699
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2530901236
Short name T377
Test name
Test status
Simulation time 138989503 ps
CPU time 1.21 seconds
Started Apr 04 12:29:30 PM PDT 24
Finished Apr 04 12:29:32 PM PDT 24
Peak memory 200504 kb
Host smart-fab45ddd-d3a1-457a-9109-fc712fafd44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530901236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2530901236
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2192631451
Short name T191
Test name
Test status
Simulation time 205150877 ps
CPU time 1.48 seconds
Started Apr 04 12:29:56 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 200628 kb
Host smart-19e61cb6-dc67-40f4-b6c3-dd5b996c120a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192631451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2192631451
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2632599994
Short name T355
Test name
Test status
Simulation time 2818600049 ps
CPU time 10.02 seconds
Started Apr 04 12:30:58 PM PDT 24
Finished Apr 04 12:31:08 PM PDT 24
Peak memory 200696 kb
Host smart-8887713b-5e65-4db1-8fb0-1e43564f0110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632599994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2632599994
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2033948127
Short name T193
Test name
Test status
Simulation time 401108074 ps
CPU time 2.2 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:42 PM PDT 24
Peak memory 200488 kb
Host smart-865dd715-8d1d-4852-9853-1fa3140e0591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033948127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2033948127
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3513692627
Short name T492
Test name
Test status
Simulation time 129986343 ps
CPU time 0.97 seconds
Started Apr 04 12:31:13 PM PDT 24
Finished Apr 04 12:31:14 PM PDT 24
Peak memory 200484 kb
Host smart-5a92f052-3fe8-4319-86e9-ee1053765a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513692627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3513692627
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1527807828
Short name T432
Test name
Test status
Simulation time 67272868 ps
CPU time 0.74 seconds
Started Apr 04 12:29:42 PM PDT 24
Finished Apr 04 12:29:43 PM PDT 24
Peak memory 200240 kb
Host smart-d7af6623-ebbe-4469-91ef-07c81e2c4a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527807828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1527807828
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3297579415
Short name T277
Test name
Test status
Simulation time 1221799777 ps
CPU time 5.46 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 217712 kb
Host smart-ab82c9c6-89cc-47f8-835b-62d097609dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297579415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3297579415
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1159007381
Short name T471
Test name
Test status
Simulation time 244410829 ps
CPU time 1.07 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 217900 kb
Host smart-fbd4ce06-ac89-4afb-abcb-c9bd759bf23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159007381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1159007381
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1826286028
Short name T430
Test name
Test status
Simulation time 173148348 ps
CPU time 0.87 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 200236 kb
Host smart-d199425c-8f30-4396-aaf1-6dae211f1b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826286028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1826286028
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2713691058
Short name T429
Test name
Test status
Simulation time 887406143 ps
CPU time 4.57 seconds
Started Apr 04 12:30:51 PM PDT 24
Finished Apr 04 12:30:55 PM PDT 24
Peak memory 200540 kb
Host smart-9f8289fa-fddc-4ce3-831c-7cc3cc2e3c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713691058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2713691058
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.718903815
Short name T541
Test name
Test status
Simulation time 151873049 ps
CPU time 1.11 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200184 kb
Host smart-b053aa4d-9774-4a6d-88c6-b67b8a3b5b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718903815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.718903815
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1900888966
Short name T244
Test name
Test status
Simulation time 114666289 ps
CPU time 1.15 seconds
Started Apr 04 12:29:25 PM PDT 24
Finished Apr 04 12:29:26 PM PDT 24
Peak memory 200644 kb
Host smart-9ee90a00-1102-4741-bc57-98731bfc0504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900888966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1900888966
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1747587418
Short name T491
Test name
Test status
Simulation time 12695760572 ps
CPU time 44.7 seconds
Started Apr 04 12:30:21 PM PDT 24
Finished Apr 04 12:31:06 PM PDT 24
Peak memory 200620 kb
Host smart-aa8fe93b-9625-445b-b463-e3bbf852b378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747587418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1747587418
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.164920490
Short name T143
Test name
Test status
Simulation time 140157386 ps
CPU time 1.64 seconds
Started Apr 04 12:29:41 PM PDT 24
Finished Apr 04 12:29:43 PM PDT 24
Peak memory 208620 kb
Host smart-0ddd815d-b104-4bd8-baa5-7f780d679f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164920490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.164920490
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3662279408
Short name T464
Test name
Test status
Simulation time 134455086 ps
CPU time 0.97 seconds
Started Apr 04 12:29:41 PM PDT 24
Finished Apr 04 12:29:42 PM PDT 24
Peak memory 200436 kb
Host smart-27bc01fb-97de-4d65-b3fc-e98864bdc280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662279408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3662279408
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2591144068
Short name T326
Test name
Test status
Simulation time 66863411 ps
CPU time 0.75 seconds
Started Apr 04 12:30:52 PM PDT 24
Finished Apr 04 12:30:53 PM PDT 24
Peak memory 200280 kb
Host smart-278ab4ff-876f-49eb-a6f8-2964b71d7921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591144068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2591144068
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2902153612
Short name T38
Test name
Test status
Simulation time 1895470438 ps
CPU time 6.68 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:54 PM PDT 24
Peak memory 230132 kb
Host smart-769a056e-feac-41ce-965e-6eef6423aa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902153612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2902153612
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3094246357
Short name T474
Test name
Test status
Simulation time 244331167 ps
CPU time 1.07 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:47 PM PDT 24
Peak memory 217848 kb
Host smart-51ff6514-75dc-48c2-80ff-920a66e0711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094246357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3094246357
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1115847256
Short name T81
Test name
Test status
Simulation time 140367769 ps
CPU time 0.85 seconds
Started Apr 04 12:31:06 PM PDT 24
Finished Apr 04 12:31:07 PM PDT 24
Peak memory 200352 kb
Host smart-cc24f9bd-3001-4bcc-bb13-360dc6304ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115847256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1115847256
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1195795625
Short name T167
Test name
Test status
Simulation time 1185991211 ps
CPU time 4.93 seconds
Started Apr 04 12:30:08 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 200644 kb
Host smart-7f5b1eff-0cf7-438f-8cae-ebacd76a42fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195795625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1195795625
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1198296945
Short name T78
Test name
Test status
Simulation time 177827371 ps
CPU time 1.16 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 200416 kb
Host smart-6b37817a-ec31-4617-8868-fc98c3bac32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198296945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1198296945
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2478645553
Short name T231
Test name
Test status
Simulation time 199240431 ps
CPU time 1.31 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:48 PM PDT 24
Peak memory 200676 kb
Host smart-26287018-2106-42be-8ea8-b47dead22a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478645553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2478645553
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2073198868
Short name T343
Test name
Test status
Simulation time 4880314049 ps
CPU time 17.58 seconds
Started Apr 04 12:30:15 PM PDT 24
Finished Apr 04 12:30:33 PM PDT 24
Peak memory 200648 kb
Host smart-6e3f8b64-85cf-4ba9-89e3-956ba9c184e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073198868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2073198868
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.670563303
Short name T103
Test name
Test status
Simulation time 111656226 ps
CPU time 1.41 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 200168 kb
Host smart-c22157a3-c65d-435d-a61a-44ff227236a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670563303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.670563303
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1187384600
Short name T318
Test name
Test status
Simulation time 103367678 ps
CPU time 0.96 seconds
Started Apr 04 12:30:14 PM PDT 24
Finished Apr 04 12:30:15 PM PDT 24
Peak memory 200416 kb
Host smart-9a7ce3f5-2fd6-4c34-9cd2-c74fe6123f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187384600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1187384600
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.209543510
Short name T325
Test name
Test status
Simulation time 75536490 ps
CPU time 0.82 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200316 kb
Host smart-a1ef567b-2c40-41b0-82db-528d9badfed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209543510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.209543510
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3210478166
Short name T470
Test name
Test status
Simulation time 1887846534 ps
CPU time 6.57 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 217208 kb
Host smart-459d7554-be89-4fb9-8452-af2ef50b433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210478166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3210478166
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3244466581
Short name T481
Test name
Test status
Simulation time 243239693 ps
CPU time 1.08 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:30:58 PM PDT 24
Peak memory 218052 kb
Host smart-a3758284-67f6-4fee-b188-ef75bc003fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244466581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3244466581
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.364292803
Short name T21
Test name
Test status
Simulation time 138246696 ps
CPU time 0.82 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200340 kb
Host smart-4ed3b518-81e6-4ab2-b100-1e539dee1f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364292803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.364292803
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2195596363
Short name T114
Test name
Test status
Simulation time 778403506 ps
CPU time 4.31 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:16 PM PDT 24
Peak memory 200588 kb
Host smart-87ab08ef-a841-44ba-9b45-49e328d91057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195596363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2195596363
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.884593753
Short name T516
Test name
Test status
Simulation time 179362643 ps
CPU time 1.14 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 200328 kb
Host smart-5d3f617f-5242-4d7f-931f-ca3d9a0f809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884593753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.884593753
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3415011540
Short name T407
Test name
Test status
Simulation time 109666454 ps
CPU time 1.13 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 200508 kb
Host smart-4cbdb5b9-dd4b-4753-9f20-ac42fe75d624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415011540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3415011540
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.788247141
Short name T184
Test name
Test status
Simulation time 2742683992 ps
CPU time 12.85 seconds
Started Apr 04 12:31:08 PM PDT 24
Finished Apr 04 12:31:21 PM PDT 24
Peak memory 208880 kb
Host smart-2eeed762-3a3c-428c-a6f7-93c51f8efa8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788247141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.788247141
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3988728057
Short name T356
Test name
Test status
Simulation time 440944931 ps
CPU time 2.52 seconds
Started Apr 04 12:31:08 PM PDT 24
Finished Apr 04 12:31:11 PM PDT 24
Peak memory 200496 kb
Host smart-581de71f-8c45-4104-9121-521b1b177ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988728057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3988728057
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1818519028
Short name T523
Test name
Test status
Simulation time 73274241 ps
CPU time 0.86 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:30:56 PM PDT 24
Peak memory 200412 kb
Host smart-a211957b-c542-4fdd-a484-046e0c5f17aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818519028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1818519028
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2073321257
Short name T208
Test name
Test status
Simulation time 80203596 ps
CPU time 0.78 seconds
Started Apr 04 12:28:34 PM PDT 24
Finished Apr 04 12:28:35 PM PDT 24
Peak memory 200232 kb
Host smart-bacbab3e-ea2b-492c-914b-81d475558aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073321257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2073321257
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1417266382
Short name T35
Test name
Test status
Simulation time 2351725434 ps
CPU time 8.14 seconds
Started Apr 04 12:28:28 PM PDT 24
Finished Apr 04 12:28:36 PM PDT 24
Peak memory 218284 kb
Host smart-039a9fe0-0bf8-4751-8b84-9db6f3672a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417266382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1417266382
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1318045159
Short name T128
Test name
Test status
Simulation time 243917407 ps
CPU time 1.12 seconds
Started Apr 04 12:29:55 PM PDT 24
Finished Apr 04 12:29:56 PM PDT 24
Peak memory 217896 kb
Host smart-842d2b7d-3c9c-40d4-b7ae-e5dbe46f4879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318045159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1318045159
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3121430729
Short name T23
Test name
Test status
Simulation time 113372413 ps
CPU time 0.75 seconds
Started Apr 04 12:28:19 PM PDT 24
Finished Apr 04 12:28:20 PM PDT 24
Peak memory 200184 kb
Host smart-7490f698-17f2-462b-81e2-c9a678e292be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121430729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3121430729
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2074033772
Short name T435
Test name
Test status
Simulation time 1952299159 ps
CPU time 6.87 seconds
Started Apr 04 12:28:19 PM PDT 24
Finished Apr 04 12:28:26 PM PDT 24
Peak memory 200532 kb
Host smart-3931e9f6-c404-4369-b6f7-7a7848fbb98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074033772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2074033772
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2669887951
Short name T69
Test name
Test status
Simulation time 17019199721 ps
CPU time 26.92 seconds
Started Apr 04 12:28:37 PM PDT 24
Finished Apr 04 12:29:04 PM PDT 24
Peak memory 218584 kb
Host smart-91ecc93e-c552-4729-ae67-b70ba73b8b8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669887951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2669887951
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.382644973
Short name T178
Test name
Test status
Simulation time 109123326 ps
CPU time 1.09 seconds
Started Apr 04 12:28:19 PM PDT 24
Finished Apr 04 12:28:21 PM PDT 24
Peak memory 200356 kb
Host smart-87511926-4c2f-4b5f-a9fd-f990f5f47cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382644973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.382644973
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4040255152
Short name T281
Test name
Test status
Simulation time 259536353 ps
CPU time 1.44 seconds
Started Apr 04 12:29:23 PM PDT 24
Finished Apr 04 12:29:25 PM PDT 24
Peak memory 199284 kb
Host smart-d2bff365-bc72-4d40-9735-d23c4e4201a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040255152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4040255152
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.4049092235
Short name T518
Test name
Test status
Simulation time 3261474970 ps
CPU time 13.14 seconds
Started Apr 04 12:28:18 PM PDT 24
Finished Apr 04 12:28:31 PM PDT 24
Peak memory 200672 kb
Host smart-060ab4e6-9964-4fec-9bb5-91a218131635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049092235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4049092235
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3800160888
Short name T390
Test name
Test status
Simulation time 346528025 ps
CPU time 2.13 seconds
Started Apr 04 12:28:19 PM PDT 24
Finished Apr 04 12:28:21 PM PDT 24
Peak memory 208700 kb
Host smart-b3f065ac-4ef6-4488-92ed-4d57853ebd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800160888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3800160888
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.45582938
Short name T537
Test name
Test status
Simulation time 153248294 ps
CPU time 1.31 seconds
Started Apr 04 12:28:10 PM PDT 24
Finished Apr 04 12:28:12 PM PDT 24
Peak memory 200360 kb
Host smart-bf0bca03-f885-4696-9bf1-c1ec699cdced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45582938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.45582938
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3145900774
Short name T273
Test name
Test status
Simulation time 68945689 ps
CPU time 0.77 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200240 kb
Host smart-ef928daf-1c7c-4e70-91a6-83d193510af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145900774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3145900774
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.510218635
Short name T473
Test name
Test status
Simulation time 1889960622 ps
CPU time 7.95 seconds
Started Apr 04 12:31:06 PM PDT 24
Finished Apr 04 12:31:14 PM PDT 24
Peak memory 217428 kb
Host smart-8746cae5-0e50-4cbd-b131-49c750ac74e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510218635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.510218635
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3051878689
Short name T287
Test name
Test status
Simulation time 246748158 ps
CPU time 1.04 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 217976 kb
Host smart-a83c0eb2-8fac-4110-af9d-bb78c4e4bdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051878689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3051878689
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.796281433
Short name T237
Test name
Test status
Simulation time 146246738 ps
CPU time 0.89 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:30:56 PM PDT 24
Peak memory 200284 kb
Host smart-37702a0f-a3ac-4c35-95dc-a0a9bfb72cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796281433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.796281433
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.623759793
Short name T511
Test name
Test status
Simulation time 839460477 ps
CPU time 4.18 seconds
Started Apr 04 12:29:41 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 200536 kb
Host smart-508528f1-6ff8-4027-aa00-408a9706a452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623759793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.623759793
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3256366038
Short name T146
Test name
Test status
Simulation time 109203803 ps
CPU time 1.03 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 200432 kb
Host smart-d664728a-5e8f-4ca9-82b0-19520c1b5c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256366038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3256366038
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3332504972
Short name T140
Test name
Test status
Simulation time 115855975 ps
CPU time 1.19 seconds
Started Apr 04 12:29:37 PM PDT 24
Finished Apr 04 12:29:38 PM PDT 24
Peak memory 200556 kb
Host smart-cb738aa7-d42c-46d0-8dc0-0de25c5c089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332504972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3332504972
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1222275932
Short name T255
Test name
Test status
Simulation time 5896195919 ps
CPU time 25.75 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:31:47 PM PDT 24
Peak memory 208952 kb
Host smart-5d2b5d6b-a872-45dd-8190-5ed51db9416c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222275932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1222275932
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.185673179
Short name T145
Test name
Test status
Simulation time 321153192 ps
CPU time 2.06 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:30:59 PM PDT 24
Peak memory 200456 kb
Host smart-76f11986-414e-457f-9c68-ae6684634a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185673179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.185673179
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2381458940
Short name T27
Test name
Test status
Simulation time 114036042 ps
CPU time 1.03 seconds
Started Apr 04 12:31:00 PM PDT 24
Finished Apr 04 12:31:01 PM PDT 24
Peak memory 200464 kb
Host smart-c0eca668-4ec7-4c65-acdd-6e57b0ad6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381458940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2381458940
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1081816280
Short name T478
Test name
Test status
Simulation time 71247766 ps
CPU time 0.75 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:30:54 PM PDT 24
Peak memory 200336 kb
Host smart-b26b2b77-1663-4be9-bf37-96f81b208f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081816280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1081816280
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3609266414
Short name T55
Test name
Test status
Simulation time 1224834370 ps
CPU time 5.98 seconds
Started Apr 04 12:31:52 PM PDT 24
Finished Apr 04 12:31:58 PM PDT 24
Peak memory 222360 kb
Host smart-83dc2023-6345-45bd-93d2-3cb267f89e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609266414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3609266414
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2459866544
Short name T283
Test name
Test status
Simulation time 243415911 ps
CPU time 1.13 seconds
Started Apr 04 12:30:51 PM PDT 24
Finished Apr 04 12:30:53 PM PDT 24
Peak memory 217928 kb
Host smart-3eb3e4fe-9fc5-416a-b1ec-389f7970439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459866544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2459866544
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1460338440
Short name T359
Test name
Test status
Simulation time 249780404 ps
CPU time 0.98 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200320 kb
Host smart-e02a66fb-bf01-405f-84f9-edb8aec5dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460338440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1460338440
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1077597914
Short name T250
Test name
Test status
Simulation time 1397881492 ps
CPU time 5.81 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:53 PM PDT 24
Peak memory 200672 kb
Host smart-3a880e94-c61f-4e5b-bb5c-3332c9e36eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077597914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1077597914
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1700277765
Short name T539
Test name
Test status
Simulation time 138573123 ps
CPU time 1.09 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200492 kb
Host smart-d3f4ba8e-9776-4a62-b924-5197b3fc2a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700277765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1700277765
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.631670729
Short name T513
Test name
Test status
Simulation time 196619534 ps
CPU time 1.35 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200664 kb
Host smart-e7b87da2-4c7a-4e94-a626-33a2aafe2d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631670729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.631670729
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2869389909
Short name T500
Test name
Test status
Simulation time 7305707218 ps
CPU time 29.98 seconds
Started Apr 04 12:30:57 PM PDT 24
Finished Apr 04 12:31:28 PM PDT 24
Peak memory 208924 kb
Host smart-3d57badd-9791-40ab-846b-066bfe68e5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869389909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2869389909
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3649412190
Short name T213
Test name
Test status
Simulation time 110899019 ps
CPU time 1.43 seconds
Started Apr 04 12:31:08 PM PDT 24
Finished Apr 04 12:31:10 PM PDT 24
Peak memory 200536 kb
Host smart-f45a6b69-a4b5-4b11-898a-8f4703ca4307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649412190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3649412190
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2183564512
Short name T447
Test name
Test status
Simulation time 272991255 ps
CPU time 1.43 seconds
Started Apr 04 12:31:43 PM PDT 24
Finished Apr 04 12:31:45 PM PDT 24
Peak memory 200484 kb
Host smart-b4721bd9-5636-4ddc-a80c-2609ff5d6752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183564512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2183564512
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3938039132
Short name T463
Test name
Test status
Simulation time 78898424 ps
CPU time 0.81 seconds
Started Apr 04 12:31:12 PM PDT 24
Finished Apr 04 12:31:13 PM PDT 24
Peak memory 200272 kb
Host smart-3d3a7b7f-e1d3-427a-9323-48138770c0e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938039132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3938039132
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2582175561
Short name T410
Test name
Test status
Simulation time 1879135922 ps
CPU time 6.93 seconds
Started Apr 04 12:29:41 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 217256 kb
Host smart-58549bab-0291-48f6-ab83-fa37caa59a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582175561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2582175561
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2896188652
Short name T331
Test name
Test status
Simulation time 244790889 ps
CPU time 1.14 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:31:11 PM PDT 24
Peak memory 217856 kb
Host smart-e1c6c2b7-b05c-4b1c-ac9b-ec2acee3d174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896188652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2896188652
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3129810091
Short name T387
Test name
Test status
Simulation time 171523266 ps
CPU time 0.83 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 200212 kb
Host smart-bc50e523-574e-41d2-893d-66af8c2c7399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129810091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3129810091
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.4074854377
Short name T123
Test name
Test status
Simulation time 1570796908 ps
CPU time 6.08 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:52 PM PDT 24
Peak memory 200436 kb
Host smart-a25ea0ff-ace1-4cc5-a6fa-b8d3c3e7e7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074854377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.4074854377
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4032810438
Short name T320
Test name
Test status
Simulation time 147164198 ps
CPU time 1.16 seconds
Started Apr 04 12:30:06 PM PDT 24
Finished Apr 04 12:30:08 PM PDT 24
Peak memory 200412 kb
Host smart-6e78fcf1-cfd9-4b97-a9a0-5917d8246fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032810438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4032810438
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.657632210
Short name T175
Test name
Test status
Simulation time 246912240 ps
CPU time 1.59 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 200696 kb
Host smart-cdf561f5-2d3a-4f77-856e-79860f47d352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657632210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.657632210
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.604020664
Short name T285
Test name
Test status
Simulation time 360863134 ps
CPU time 1.98 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:30:59 PM PDT 24
Peak memory 200668 kb
Host smart-96439ec5-a17b-4715-a896-d8e1c44fdf58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604020664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.604020664
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.718578190
Short name T304
Test name
Test status
Simulation time 170372838 ps
CPU time 1.24 seconds
Started Apr 04 12:30:21 PM PDT 24
Finished Apr 04 12:30:22 PM PDT 24
Peak memory 200608 kb
Host smart-b00ae8ef-beed-4325-823a-6e726c458380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718578190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.718578190
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3920986630
Short name T258
Test name
Test status
Simulation time 63249424 ps
CPU time 0.79 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 200252 kb
Host smart-3afaead5-630a-4365-a054-f60e2c8ec2db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920986630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3920986630
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2794169700
Short name T487
Test name
Test status
Simulation time 2355041181 ps
CPU time 9.02 seconds
Started Apr 04 12:31:07 PM PDT 24
Finished Apr 04 12:31:16 PM PDT 24
Peak memory 218288 kb
Host smart-b66d3d01-b5e9-4b13-af26-b17df80157f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794169700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2794169700
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4132843358
Short name T416
Test name
Test status
Simulation time 245250468 ps
CPU time 1.03 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 217972 kb
Host smart-49dadc4b-97a3-4593-8061-eb91d77a0fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132843358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4132843358
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2512485633
Short name T535
Test name
Test status
Simulation time 144984405 ps
CPU time 0.82 seconds
Started Apr 04 12:29:42 PM PDT 24
Finished Apr 04 12:29:43 PM PDT 24
Peak memory 200232 kb
Host smart-1f1bcf85-3511-4db1-9e97-e637536292ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512485633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2512485633
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2920801166
Short name T376
Test name
Test status
Simulation time 891162060 ps
CPU time 4.47 seconds
Started Apr 04 12:31:34 PM PDT 24
Finished Apr 04 12:31:38 PM PDT 24
Peak memory 200652 kb
Host smart-85efbdbc-6559-433e-81c9-69382a43ee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920801166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2920801166
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.133199313
Short name T264
Test name
Test status
Simulation time 141064521 ps
CPU time 1.11 seconds
Started Apr 04 12:31:15 PM PDT 24
Finished Apr 04 12:31:17 PM PDT 24
Peak memory 200464 kb
Host smart-180ed609-3e5c-4f9e-a0fa-f0758a7044a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133199313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.133199313
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1852880393
Short name T458
Test name
Test status
Simulation time 201958411 ps
CPU time 1.39 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200556 kb
Host smart-b4074cea-9ec6-4d58-a64b-cf14ea97ca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852880393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1852880393
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2298138282
Short name T185
Test name
Test status
Simulation time 5345200476 ps
CPU time 21.64 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:30:07 PM PDT 24
Peak memory 208764 kb
Host smart-0d885a6c-927f-451f-b6c3-94036210c2d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298138282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2298138282
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.851256359
Short name T385
Test name
Test status
Simulation time 471242882 ps
CPU time 2.35 seconds
Started Apr 04 12:29:53 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 200464 kb
Host smart-bf38f386-7de7-46a8-afdc-e3c4f6b4fabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851256359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.851256359
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1717584853
Short name T421
Test name
Test status
Simulation time 124569641 ps
CPU time 1.04 seconds
Started Apr 04 12:31:41 PM PDT 24
Finished Apr 04 12:31:42 PM PDT 24
Peak memory 200448 kb
Host smart-35e4d99a-4534-452a-86d2-920d4869c134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717584853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1717584853
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.585975829
Short name T217
Test name
Test status
Simulation time 86566545 ps
CPU time 0.86 seconds
Started Apr 04 12:29:41 PM PDT 24
Finished Apr 04 12:29:42 PM PDT 24
Peak memory 200192 kb
Host smart-c883d0ba-e215-4bc9-8c58-2dd2c02b0c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585975829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.585975829
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3446821231
Short name T74
Test name
Test status
Simulation time 1222368907 ps
CPU time 5.35 seconds
Started Apr 04 12:29:52 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 217624 kb
Host smart-ab309f95-ab12-4966-82a6-40295f5ff73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446821231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3446821231
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3046699585
Short name T2
Test name
Test status
Simulation time 244248713 ps
CPU time 1.03 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:30:55 PM PDT 24
Peak memory 217908 kb
Host smart-48db2313-c834-451e-9560-e7a81eed2944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046699585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3046699585
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.478704958
Short name T315
Test name
Test status
Simulation time 98070258 ps
CPU time 0.74 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 200180 kb
Host smart-0a08a318-14ab-48b5-820a-7fd99210f111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478704958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.478704958
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1800757203
Short name T508
Test name
Test status
Simulation time 1471916366 ps
CPU time 5.83 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 200524 kb
Host smart-625facf0-a281-4522-b98c-c17db319c869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800757203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1800757203
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3432829114
Short name T378
Test name
Test status
Simulation time 158321529 ps
CPU time 1.11 seconds
Started Apr 04 12:29:42 PM PDT 24
Finished Apr 04 12:29:43 PM PDT 24
Peak memory 200368 kb
Host smart-6326d9bf-b9cd-4136-a09d-9e8bc48b17d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432829114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3432829114
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1167544033
Short name T434
Test name
Test status
Simulation time 122783977 ps
CPU time 1.21 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:31:23 PM PDT 24
Peak memory 200632 kb
Host smart-215205a7-30f0-4d0c-9ba8-c296cd7fc393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167544033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1167544033
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2323349784
Short name T358
Test name
Test status
Simulation time 1340868418 ps
CPU time 5.94 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 200384 kb
Host smart-e03f0239-2380-4d9d-94cf-0653111c5714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323349784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2323349784
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3464591379
Short name T328
Test name
Test status
Simulation time 131620650 ps
CPU time 1.59 seconds
Started Apr 04 12:29:41 PM PDT 24
Finished Apr 04 12:29:43 PM PDT 24
Peak memory 200416 kb
Host smart-482017ca-a57e-4f41-a23e-d4041385f6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464591379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3464591379
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.751331576
Short name T412
Test name
Test status
Simulation time 90320585 ps
CPU time 0.87 seconds
Started Apr 04 12:31:44 PM PDT 24
Finished Apr 04 12:31:45 PM PDT 24
Peak memory 200440 kb
Host smart-99b30b41-f81c-42e0-a872-8566f091f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751331576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.751331576
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.241579636
Short name T205
Test name
Test status
Simulation time 65040135 ps
CPU time 0.77 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200240 kb
Host smart-5c04fa4f-e007-4b40-a261-01b52df95ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241579636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.241579636
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2285854162
Short name T262
Test name
Test status
Simulation time 1878133082 ps
CPU time 6.73 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:53 PM PDT 24
Peak memory 218212 kb
Host smart-c62284ef-2f85-4ddb-8b1f-6b11fc551623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285854162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2285854162
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4057969230
Short name T526
Test name
Test status
Simulation time 244944923 ps
CPU time 1.07 seconds
Started Apr 04 12:29:44 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 217856 kb
Host smart-296077a2-b985-42ec-bc23-cfc0bc5325b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057969230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4057969230
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.897163478
Short name T26
Test name
Test status
Simulation time 168111019 ps
CPU time 0.87 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200228 kb
Host smart-10f6da87-09e2-47fa-b3d2-ad483e659c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897163478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.897163478
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2305195765
Short name T498
Test name
Test status
Simulation time 1076249484 ps
CPU time 4.87 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200544 kb
Host smart-8a632237-da8c-4a39-b025-a6edd24de9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305195765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2305195765
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.4191580527
Short name T142
Test name
Test status
Simulation time 176442402 ps
CPU time 1.14 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200352 kb
Host smart-df344e7e-51de-4dff-8848-c8dda863a373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191580527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.4191580527
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3212464364
Short name T102
Test name
Test status
Simulation time 201564543 ps
CPU time 1.32 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200548 kb
Host smart-af67f32d-c8b1-4e25-8202-30aa592a7b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212464364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3212464364
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1298494090
Short name T461
Test name
Test status
Simulation time 9717143356 ps
CPU time 34.09 seconds
Started Apr 04 12:29:38 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 200676 kb
Host smart-63ceb795-c0ef-4157-a196-5fbfa3c7dd6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298494090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1298494090
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.418711335
Short name T475
Test name
Test status
Simulation time 368793349 ps
CPU time 2.35 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 200420 kb
Host smart-2d44e156-e3e7-4880-b24a-cea743d1ad56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418711335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.418711335
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.723579366
Short name T357
Test name
Test status
Simulation time 77487246 ps
CPU time 0.82 seconds
Started Apr 04 12:29:42 PM PDT 24
Finished Apr 04 12:29:43 PM PDT 24
Peak memory 200444 kb
Host smart-ae7cd5a8-6820-4f93-b969-84f61ba932be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723579366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.723579366
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.510229382
Short name T335
Test name
Test status
Simulation time 75363365 ps
CPU time 0.85 seconds
Started Apr 04 12:29:44 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 200248 kb
Host smart-d2d5e2bb-c9b9-4e24-8d2e-043663dc8ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510229382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.510229382
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1184679744
Short name T49
Test name
Test status
Simulation time 1225878421 ps
CPU time 5.5 seconds
Started Apr 04 12:30:02 PM PDT 24
Finished Apr 04 12:30:08 PM PDT 24
Peak memory 222380 kb
Host smart-89fba52a-61fc-4592-b07f-edf46b62df92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184679744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1184679744
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2248122293
Short name T139
Test name
Test status
Simulation time 253530379 ps
CPU time 1.07 seconds
Started Apr 04 12:29:56 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 217768 kb
Host smart-8a530aa4-d26b-45be-83b5-8d04e51bf114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248122293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2248122293
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3855888787
Short name T485
Test name
Test status
Simulation time 140449019 ps
CPU time 0.82 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 200176 kb
Host smart-73acb98f-a2d4-4689-93be-6a5a70564e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855888787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3855888787
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2879627158
Short name T274
Test name
Test status
Simulation time 2101462823 ps
CPU time 8.08 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 200564 kb
Host smart-b27ac2d4-c2eb-490c-827e-6203016a0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879627158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2879627158
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2442826314
Short name T446
Test name
Test status
Simulation time 101037073 ps
CPU time 0.95 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 200368 kb
Host smart-df6a3c65-5e4a-4476-8dfe-541715d3d6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442826314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2442826314
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1291777360
Short name T189
Test name
Test status
Simulation time 121901110 ps
CPU time 1.15 seconds
Started Apr 04 12:29:41 PM PDT 24
Finished Apr 04 12:29:42 PM PDT 24
Peak memory 200620 kb
Host smart-e613895a-f194-41c0-8679-508764e01e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291777360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1291777360
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.271727555
Short name T177
Test name
Test status
Simulation time 2297009318 ps
CPU time 10.44 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:54 PM PDT 24
Peak memory 210020 kb
Host smart-937c36ef-2f90-40d0-b276-5c6f752f04c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271727555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.271727555
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2125535137
Short name T80
Test name
Test status
Simulation time 408984680 ps
CPU time 2.12 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 200408 kb
Host smart-19c10caa-b6bc-42d3-92f8-bddf025d7334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125535137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2125535137
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3441614055
Short name T502
Test name
Test status
Simulation time 149657688 ps
CPU time 1.1 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 200388 kb
Host smart-712178c0-a643-4a2b-bc22-29d8273e2e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441614055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3441614055
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1860824729
Short name T292
Test name
Test status
Simulation time 106999593 ps
CPU time 0.91 seconds
Started Apr 04 12:30:42 PM PDT 24
Finished Apr 04 12:30:43 PM PDT 24
Peak memory 200332 kb
Host smart-a14a7eb3-5abc-4aa9-902d-7abe530aab40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860824729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1860824729
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.761619986
Short name T505
Test name
Test status
Simulation time 244106149 ps
CPU time 1.16 seconds
Started Apr 04 12:29:51 PM PDT 24
Finished Apr 04 12:29:52 PM PDT 24
Peak memory 217760 kb
Host smart-aa14c115-0280-42fa-9aa1-41035da5ab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761619986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.761619986
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2166201237
Short name T19
Test name
Test status
Simulation time 216196931 ps
CPU time 0.97 seconds
Started Apr 04 12:29:44 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 200396 kb
Host smart-b2b179f0-b1f1-4987-8102-0f7255c2a2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166201237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2166201237
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2127806550
Short name T125
Test name
Test status
Simulation time 1509204989 ps
CPU time 6.15 seconds
Started Apr 04 12:30:02 PM PDT 24
Finished Apr 04 12:30:08 PM PDT 24
Peak memory 200616 kb
Host smart-41dbb29f-ea41-4e60-aaee-a4f58b824774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127806550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2127806550
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2112305418
Short name T79
Test name
Test status
Simulation time 110829165 ps
CPU time 1.14 seconds
Started Apr 04 12:30:04 PM PDT 24
Finished Apr 04 12:30:05 PM PDT 24
Peak memory 200456 kb
Host smart-349f8742-ed49-40ea-896a-4af5ca639f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112305418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2112305418
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1694221285
Short name T11
Test name
Test status
Simulation time 118857626 ps
CPU time 1.31 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 200548 kb
Host smart-9a35d198-a96f-41ae-8edd-51fa5000025b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694221285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1694221285
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3429837331
Short name T192
Test name
Test status
Simulation time 2614350730 ps
CPU time 11.08 seconds
Started Apr 04 12:29:53 PM PDT 24
Finished Apr 04 12:30:04 PM PDT 24
Peak memory 200624 kb
Host smart-8c5437d1-9e5d-4eee-a633-3b6575d75e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429837331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3429837331
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.621138565
Short name T440
Test name
Test status
Simulation time 310912998 ps
CPU time 2.05 seconds
Started Apr 04 12:29:55 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 200456 kb
Host smart-d5bfc542-0563-44f8-b369-556a0753b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621138565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.621138565
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1576455107
Short name T130
Test name
Test status
Simulation time 276866908 ps
CPU time 1.54 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200492 kb
Host smart-79eaa80b-6397-4421-8fc9-dfee725df60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576455107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1576455107
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.438125350
Short name T300
Test name
Test status
Simulation time 75231097 ps
CPU time 0.79 seconds
Started Apr 04 12:31:04 PM PDT 24
Finished Apr 04 12:31:05 PM PDT 24
Peak memory 200344 kb
Host smart-d9d7934c-36ce-42e1-9452-d109b88dfcf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438125350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.438125350
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1325014823
Short name T241
Test name
Test status
Simulation time 1900680696 ps
CPU time 8.05 seconds
Started Apr 04 12:29:44 PM PDT 24
Finished Apr 04 12:29:52 PM PDT 24
Peak memory 221808 kb
Host smart-428e3251-a66d-4d97-b0ca-baa4dbe0e5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325014823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1325014823
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.953587105
Short name T171
Test name
Test status
Simulation time 244647875 ps
CPU time 1.09 seconds
Started Apr 04 12:31:43 PM PDT 24
Finished Apr 04 12:31:44 PM PDT 24
Peak memory 218016 kb
Host smart-c498fdf2-6627-49c0-a9c8-14620d47370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953587105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.953587105
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1936996592
Short name T203
Test name
Test status
Simulation time 210068547 ps
CPU time 0.87 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200320 kb
Host smart-ac1e9481-b705-4b46-9784-e4e407405bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936996592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1936996592
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2739014581
Short name T15
Test name
Test status
Simulation time 871699463 ps
CPU time 4.07 seconds
Started Apr 04 12:29:44 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200592 kb
Host smart-2b1e7b61-bf6f-4293-ac0e-cc4169edc2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739014581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2739014581
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3413692826
Short name T371
Test name
Test status
Simulation time 105232399 ps
CPU time 0.97 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200376 kb
Host smart-5cbcac67-8b68-4736-b4e7-a8a4021ec9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413692826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3413692826
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2800473460
Short name T521
Test name
Test status
Simulation time 122316833 ps
CPU time 1.15 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 200396 kb
Host smart-160b8398-efb0-4fe0-86ad-408020fb136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800473460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2800473460
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.4108737049
Short name T438
Test name
Test status
Simulation time 7781005525 ps
CPU time 26.59 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:30:12 PM PDT 24
Peak memory 200400 kb
Host smart-58147a7a-e27b-4c94-8bd8-a36f17933c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108737049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.4108737049
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3067988841
Short name T249
Test name
Test status
Simulation time 149781122 ps
CPU time 1.82 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 200388 kb
Host smart-760fef63-a347-4cff-9c9f-ca968ab34c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067988841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3067988841
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3271854022
Short name T52
Test name
Test status
Simulation time 76287837 ps
CPU time 0.78 seconds
Started Apr 04 12:31:41 PM PDT 24
Finished Apr 04 12:31:41 PM PDT 24
Peak memory 200448 kb
Host smart-d2924d44-f6f3-462a-b010-a5071920d7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271854022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3271854022
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3342614841
Short name T275
Test name
Test status
Simulation time 68776309 ps
CPU time 0.78 seconds
Started Apr 04 12:29:56 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 200224 kb
Host smart-46425886-9908-4918-81a9-fce6ae39136a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342614841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3342614841
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1780059571
Short name T366
Test name
Test status
Simulation time 2349139213 ps
CPU time 8.69 seconds
Started Apr 04 12:30:50 PM PDT 24
Finished Apr 04 12:30:59 PM PDT 24
Peak memory 218320 kb
Host smart-6c65fe28-b3e1-49b3-9346-cb741a25be5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780059571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1780059571
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1002254418
Short name T144
Test name
Test status
Simulation time 251910675 ps
CPU time 1.1 seconds
Started Apr 04 12:29:59 PM PDT 24
Finished Apr 04 12:30:01 PM PDT 24
Peak memory 217796 kb
Host smart-e3bc8b69-176a-4087-b7b5-8bc9d90bfc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002254418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1002254418
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2930161759
Short name T17
Test name
Test status
Simulation time 209660779 ps
CPU time 0.93 seconds
Started Apr 04 12:31:28 PM PDT 24
Finished Apr 04 12:31:29 PM PDT 24
Peak memory 200320 kb
Host smart-d15fa30d-1d30-44ae-9b04-d34b133ca766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930161759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2930161759
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.994673978
Short name T271
Test name
Test status
Simulation time 1791000009 ps
CPU time 7.61 seconds
Started Apr 04 12:29:42 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 200540 kb
Host smart-570b7309-976f-4687-8cce-b6a58332b699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994673978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.994673978
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2920394082
Short name T182
Test name
Test status
Simulation time 106318917 ps
CPU time 0.95 seconds
Started Apr 04 12:30:51 PM PDT 24
Finished Apr 04 12:30:52 PM PDT 24
Peak memory 200436 kb
Host smart-19067a41-03e8-4c9d-bcdc-874d73952cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920394082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2920394082
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1634403728
Short name T195
Test name
Test status
Simulation time 241528612 ps
CPU time 1.45 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 200544 kb
Host smart-9e543a16-1f0d-49b2-be6f-f7f4a1d8fc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634403728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1634403728
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3336088717
Short name T519
Test name
Test status
Simulation time 3136896338 ps
CPU time 14.15 seconds
Started Apr 04 12:30:01 PM PDT 24
Finished Apr 04 12:30:16 PM PDT 24
Peak memory 200672 kb
Host smart-7e8ed6d7-b579-42be-9497-fad33104f357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336088717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3336088717
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3197645716
Short name T542
Test name
Test status
Simulation time 279698244 ps
CPU time 1.87 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 200488 kb
Host smart-ec9aa262-47b1-4ad4-a7b3-a527be400711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197645716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3197645716
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1674311446
Short name T506
Test name
Test status
Simulation time 95069091 ps
CPU time 0.89 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200376 kb
Host smart-0c514fd9-d940-43d8-aeef-67a319e6b071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674311446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1674311446
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1247426937
Short name T56
Test name
Test status
Simulation time 74748964 ps
CPU time 0.79 seconds
Started Apr 04 12:27:48 PM PDT 24
Finished Apr 04 12:27:50 PM PDT 24
Peak memory 199052 kb
Host smart-70eae9df-83f8-4f10-ab13-f3a0bdf0bea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247426937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1247426937
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1466891517
Short name T415
Test name
Test status
Simulation time 243985596 ps
CPU time 1.24 seconds
Started Apr 04 12:29:54 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 217864 kb
Host smart-38c7c510-4e53-4e41-9886-1f6e3dbceb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466891517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1466891517
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2226065526
Short name T254
Test name
Test status
Simulation time 109532855 ps
CPU time 0.77 seconds
Started Apr 04 12:28:36 PM PDT 24
Finished Apr 04 12:28:37 PM PDT 24
Peak memory 200208 kb
Host smart-e6b7f199-ae43-4532-9027-fdc2f37ab03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226065526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2226065526
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2997027690
Short name T301
Test name
Test status
Simulation time 2124252518 ps
CPU time 8.01 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 200544 kb
Host smart-620c6d44-0716-411c-a925-89b705778ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997027690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2997027690
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2659347151
Short name T71
Test name
Test status
Simulation time 17481375809 ps
CPU time 25.81 seconds
Started Apr 04 12:28:15 PM PDT 24
Finished Apr 04 12:28:41 PM PDT 24
Peak memory 216932 kb
Host smart-2c7779ef-336c-4d42-bf0e-858be8501c58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659347151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2659347151
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1007488367
Short name T383
Test name
Test status
Simulation time 137566551 ps
CPU time 1.07 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200464 kb
Host smart-11d5cde3-be29-4340-a928-b42bc695cea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007488367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1007488367
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1234773086
Short name T517
Test name
Test status
Simulation time 203662116 ps
CPU time 1.48 seconds
Started Apr 04 12:28:36 PM PDT 24
Finished Apr 04 12:28:38 PM PDT 24
Peak memory 200572 kb
Host smart-f07016c6-fa48-4c19-ae0a-1d04825954d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234773086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1234773086
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.727298355
Short name T479
Test name
Test status
Simulation time 10854692069 ps
CPU time 40.05 seconds
Started Apr 04 12:29:20 PM PDT 24
Finished Apr 04 12:30:00 PM PDT 24
Peak memory 209652 kb
Host smart-953f52a8-ee20-41c0-9b2d-2a78d873ac76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727298355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.727298355
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2928432981
Short name T409
Test name
Test status
Simulation time 385783296 ps
CPU time 2.46 seconds
Started Apr 04 12:28:49 PM PDT 24
Finished Apr 04 12:28:51 PM PDT 24
Peak memory 200496 kb
Host smart-a65d01ac-c7b7-4810-9405-6c927cb65a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928432981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2928432981
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2807952175
Short name T190
Test name
Test status
Simulation time 92862515 ps
CPU time 0.91 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200368 kb
Host smart-dac083df-53d9-4d82-8771-2ad239d05ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807952175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2807952175
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.23408990
Short name T400
Test name
Test status
Simulation time 73492103 ps
CPU time 0.8 seconds
Started Apr 04 12:29:57 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 200284 kb
Host smart-3c087285-7385-4618-9c4c-a5e8d1bf3832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23408990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.23408990
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1334238837
Short name T40
Test name
Test status
Simulation time 1888303021 ps
CPU time 7.38 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:31:02 PM PDT 24
Peak memory 217336 kb
Host smart-6c1611b7-d625-4409-8bb3-0f9c7e6e9217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334238837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1334238837
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.78999026
Short name T75
Test name
Test status
Simulation time 242909227 ps
CPU time 1.17 seconds
Started Apr 04 12:29:53 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 217972 kb
Host smart-24b11f2a-fdd3-4d07-b85c-d2625e98094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78999026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.78999026
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3649786216
Short name T240
Test name
Test status
Simulation time 112873266 ps
CPU time 0.78 seconds
Started Apr 04 12:31:03 PM PDT 24
Finished Apr 04 12:31:04 PM PDT 24
Peak memory 200312 kb
Host smart-e023af65-284d-4a13-bdb4-dc30c4411eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649786216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3649786216
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2419401664
Short name T489
Test name
Test status
Simulation time 814110942 ps
CPU time 4.39 seconds
Started Apr 04 12:30:13 PM PDT 24
Finished Apr 04 12:30:17 PM PDT 24
Peak memory 200660 kb
Host smart-69daba59-d1d7-4930-b8d8-b8c5d5df9ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419401664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2419401664
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2913563244
Short name T507
Test name
Test status
Simulation time 107868712 ps
CPU time 0.96 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:12 PM PDT 24
Peak memory 200480 kb
Host smart-bfd8e379-633a-4a34-921e-82cfe64562bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913563244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2913563244
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3608261684
Short name T276
Test name
Test status
Simulation time 255690077 ps
CPU time 1.6 seconds
Started Apr 04 12:29:52 PM PDT 24
Finished Apr 04 12:29:54 PM PDT 24
Peak memory 200652 kb
Host smart-db2dc834-a19e-4f8c-bc92-9fe5e2103f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608261684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3608261684
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2655461330
Short name T188
Test name
Test status
Simulation time 7763884288 ps
CPU time 32.61 seconds
Started Apr 04 12:30:00 PM PDT 24
Finished Apr 04 12:30:33 PM PDT 24
Peak memory 209744 kb
Host smart-74099086-a1f0-4fb9-b9e5-5225a97a7078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655461330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2655461330
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.488453265
Short name T408
Test name
Test status
Simulation time 141439326 ps
CPU time 1.74 seconds
Started Apr 04 12:30:00 PM PDT 24
Finished Apr 04 12:30:02 PM PDT 24
Peak memory 200468 kb
Host smart-2a3a6f04-d5c2-4d10-9381-f11d011b5a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488453265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.488453265
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2626135793
Short name T290
Test name
Test status
Simulation time 107281677 ps
CPU time 0.88 seconds
Started Apr 04 12:29:55 PM PDT 24
Finished Apr 04 12:29:56 PM PDT 24
Peak memory 200392 kb
Host smart-8714c4fd-4430-4de4-a8b7-dda89cb91d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626135793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2626135793
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2791160451
Short name T219
Test name
Test status
Simulation time 56079994 ps
CPU time 0.73 seconds
Started Apr 04 12:29:59 PM PDT 24
Finished Apr 04 12:30:00 PM PDT 24
Peak memory 200272 kb
Host smart-b22d1258-e376-4d95-aaf2-98a5c4b862a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791160451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2791160451
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1472180955
Short name T53
Test name
Test status
Simulation time 2158759508 ps
CPU time 7.47 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:53 PM PDT 24
Peak memory 222400 kb
Host smart-6fd9fae6-50a2-4dc2-9fed-9608a129fa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472180955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1472180955
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.126277857
Short name T282
Test name
Test status
Simulation time 244283591 ps
CPU time 1.05 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 217784 kb
Host smart-f321b278-23cd-43aa-b4fc-131289d1895d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126277857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.126277857
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.87666651
Short name T76
Test name
Test status
Simulation time 132025943 ps
CPU time 0.82 seconds
Started Apr 04 12:29:48 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 200296 kb
Host smart-bbdf5e81-ebf6-4a9c-bb0e-83f30d5cd36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87666651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.87666651
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1681601217
Short name T16
Test name
Test status
Simulation time 1389907371 ps
CPU time 5.47 seconds
Started Apr 04 12:29:59 PM PDT 24
Finished Apr 04 12:30:05 PM PDT 24
Peak memory 200636 kb
Host smart-9fa8121d-4a31-4a41-bdf7-a4c4e543073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681601217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1681601217
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2083979157
Short name T425
Test name
Test status
Simulation time 99287694 ps
CPU time 1 seconds
Started Apr 04 12:30:05 PM PDT 24
Finished Apr 04 12:30:07 PM PDT 24
Peak memory 200380 kb
Host smart-a030f5d6-6388-448a-9b45-31ff86798285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083979157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2083979157
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2606048217
Short name T132
Test name
Test status
Simulation time 248283016 ps
CPU time 1.53 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 200740 kb
Host smart-4fe43d94-d903-46d3-b3b9-27488728bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606048217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2606048217
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.889948371
Short name T363
Test name
Test status
Simulation time 6383549197 ps
CPU time 22.36 seconds
Started Apr 04 12:30:10 PM PDT 24
Finished Apr 04 12:30:33 PM PDT 24
Peak memory 200716 kb
Host smart-ad13dc1c-7018-4451-8076-66b21f5f1bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889948371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.889948371
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3244214275
Short name T288
Test name
Test status
Simulation time 327866512 ps
CPU time 2.05 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:30:19 PM PDT 24
Peak memory 200492 kb
Host smart-2fc1a5f0-f815-41dc-a388-cc4bed29dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244214275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3244214275
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1449874552
Short name T344
Test name
Test status
Simulation time 123359284 ps
CPU time 0.95 seconds
Started Apr 04 12:30:02 PM PDT 24
Finished Apr 04 12:30:03 PM PDT 24
Peak memory 200436 kb
Host smart-cf964977-4eb7-436d-8c85-b9a4add79f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449874552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1449874552
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.723362283
Short name T405
Test name
Test status
Simulation time 78235966 ps
CPU time 0.8 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:30:55 PM PDT 24
Peak memory 200524 kb
Host smart-6ab225f9-2f2b-446d-8c4f-f18463ffe009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723362283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.723362283
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.938638037
Short name T294
Test name
Test status
Simulation time 1223422932 ps
CPU time 5.98 seconds
Started Apr 04 12:29:52 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 217224 kb
Host smart-2f7b1171-6912-4065-bb7d-863082703fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938638037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.938638037
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.683132703
Short name T460
Test name
Test status
Simulation time 244613902 ps
CPU time 1.12 seconds
Started Apr 04 12:30:42 PM PDT 24
Finished Apr 04 12:30:44 PM PDT 24
Peak memory 217972 kb
Host smart-f956a303-7a78-4106-9970-59a835a00f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683132703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.683132703
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.218130285
Short name T354
Test name
Test status
Simulation time 84108969 ps
CPU time 0.75 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 200252 kb
Host smart-b33f0719-4c05-4a10-b56d-f2ab83259823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218130285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.218130285
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.586191997
Short name T32
Test name
Test status
Simulation time 1957954093 ps
CPU time 7.48 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:54 PM PDT 24
Peak memory 200700 kb
Host smart-d464e2ec-0dc9-4555-bf2b-3881aa81a3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586191997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.586191997
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3914598567
Short name T163
Test name
Test status
Simulation time 98736206 ps
CPU time 0.95 seconds
Started Apr 04 12:30:00 PM PDT 24
Finished Apr 04 12:30:01 PM PDT 24
Peak memory 200452 kb
Host smart-87ebac3c-a599-4568-b8af-3aeaa122193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914598567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3914598567
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2839309596
Short name T476
Test name
Test status
Simulation time 254288667 ps
CPU time 1.52 seconds
Started Apr 04 12:31:08 PM PDT 24
Finished Apr 04 12:31:10 PM PDT 24
Peak memory 200680 kb
Host smart-41e675b7-711a-4ec2-9461-97e8b4a51c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839309596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2839309596
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1650308167
Short name T319
Test name
Test status
Simulation time 1041911989 ps
CPU time 4.76 seconds
Started Apr 04 12:29:48 PM PDT 24
Finished Apr 04 12:29:53 PM PDT 24
Peak memory 208560 kb
Host smart-01488a43-8e21-4904-ac43-b13b46d4adb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650308167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1650308167
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1898242783
Short name T151
Test name
Test status
Simulation time 121396939 ps
CPU time 1.45 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 200648 kb
Host smart-f9251f30-4cb5-4e58-bb90-0d595940bcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898242783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1898242783
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.883797070
Short name T350
Test name
Test status
Simulation time 117408090 ps
CPU time 0.98 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 200512 kb
Host smart-682d8a39-7d7d-4409-b92c-6cedae23b8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883797070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.883797070
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2900638545
Short name T169
Test name
Test status
Simulation time 76870061 ps
CPU time 0.75 seconds
Started Apr 04 12:29:48 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 200356 kb
Host smart-62b77e58-5242-4ef9-97fc-02e3aa7ec6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900638545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2900638545
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.885537656
Short name T483
Test name
Test status
Simulation time 1220164111 ps
CPU time 5.87 seconds
Started Apr 04 12:30:42 PM PDT 24
Finished Apr 04 12:30:48 PM PDT 24
Peak memory 221384 kb
Host smart-5d302aee-5244-4e53-a3d3-922c81af630b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885537656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.885537656
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1129154442
Short name T245
Test name
Test status
Simulation time 244872578 ps
CPU time 1.07 seconds
Started Apr 04 12:31:28 PM PDT 24
Finished Apr 04 12:31:29 PM PDT 24
Peak memory 217920 kb
Host smart-1018df2d-1603-41c0-8a9a-11adc8ca95be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129154442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1129154442
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2508407488
Short name T25
Test name
Test status
Simulation time 76121558 ps
CPU time 0.7 seconds
Started Apr 04 12:30:07 PM PDT 24
Finished Apr 04 12:30:08 PM PDT 24
Peak memory 200292 kb
Host smart-6fbeb58d-60dc-49b9-a77f-307ca72e76e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508407488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2508407488
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.787185955
Short name T329
Test name
Test status
Simulation time 857988787 ps
CPU time 4.33 seconds
Started Apr 04 12:29:48 PM PDT 24
Finished Apr 04 12:29:53 PM PDT 24
Peak memory 200336 kb
Host smart-8ea7b45a-5231-4ec1-b900-b30abc40d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787185955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.787185955
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1296041508
Short name T317
Test name
Test status
Simulation time 113950495 ps
CPU time 1 seconds
Started Apr 04 12:29:55 PM PDT 24
Finished Apr 04 12:29:57 PM PDT 24
Peak memory 200400 kb
Host smart-2657eecf-d84d-45a3-a5a7-ddab67e67574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296041508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1296041508
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1691319847
Short name T235
Test name
Test status
Simulation time 249151920 ps
CPU time 1.64 seconds
Started Apr 04 12:30:24 PM PDT 24
Finished Apr 04 12:30:26 PM PDT 24
Peak memory 200624 kb
Host smart-78bc8804-41ab-4a3e-a1ac-f311202de1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691319847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1691319847
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2605739780
Short name T124
Test name
Test status
Simulation time 16202366993 ps
CPU time 50.65 seconds
Started Apr 04 12:30:10 PM PDT 24
Finished Apr 04 12:31:01 PM PDT 24
Peak memory 208888 kb
Host smart-521295d5-e009-401b-9bc1-02a3e73892e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605739780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2605739780
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1387741042
Short name T101
Test name
Test status
Simulation time 144158233 ps
CPU time 1.8 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 200440 kb
Host smart-f21dcc9f-b175-48a2-a66d-6de70996f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387741042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1387741042
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3694361805
Short name T448
Test name
Test status
Simulation time 172954965 ps
CPU time 1.1 seconds
Started Apr 04 12:29:57 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 200408 kb
Host smart-52a47ec8-8028-4324-b0c4-483ab4b30110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694361805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3694361805
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1083841172
Short name T307
Test name
Test status
Simulation time 68659316 ps
CPU time 0.74 seconds
Started Apr 04 12:30:41 PM PDT 24
Finished Apr 04 12:30:42 PM PDT 24
Peak memory 200244 kb
Host smart-1450cd1c-d337-493d-a104-2a5a708c8e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083841172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1083841172
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.918597308
Short name T375
Test name
Test status
Simulation time 2350923019 ps
CPU time 8.34 seconds
Started Apr 04 12:30:06 PM PDT 24
Finished Apr 04 12:30:14 PM PDT 24
Peak memory 217532 kb
Host smart-f96386ca-7126-40ea-bd1c-a832eb8f1c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918597308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.918597308
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1273231643
Short name T194
Test name
Test status
Simulation time 243747498 ps
CPU time 1.07 seconds
Started Apr 04 12:29:44 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 217856 kb
Host smart-70cef17c-6058-4662-abb8-34a11f3b624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273231643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1273231643
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2965449753
Short name T503
Test name
Test status
Simulation time 76656095 ps
CPU time 0.76 seconds
Started Apr 04 12:30:10 PM PDT 24
Finished Apr 04 12:30:11 PM PDT 24
Peak memory 200216 kb
Host smart-ad647569-e362-413c-ae53-2d0fbcbda7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965449753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2965449753
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2547139480
Short name T361
Test name
Test status
Simulation time 771536737 ps
CPU time 3.97 seconds
Started Apr 04 12:30:01 PM PDT 24
Finished Apr 04 12:30:06 PM PDT 24
Peak memory 200568 kb
Host smart-6256ef65-2750-4b96-9882-9538646792fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547139480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2547139480
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.995647624
Short name T51
Test name
Test status
Simulation time 177109513 ps
CPU time 1.15 seconds
Started Apr 04 12:30:21 PM PDT 24
Finished Apr 04 12:30:23 PM PDT 24
Peak memory 200456 kb
Host smart-394ef71c-5593-4bde-9897-a5a1eb66ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995647624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.995647624
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.436821720
Short name T5
Test name
Test status
Simulation time 119525062 ps
CPU time 1.21 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 200676 kb
Host smart-229cde64-fb8d-41ca-a823-02479e15e1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436821720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.436821720
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2788871791
Short name T251
Test name
Test status
Simulation time 8743056964 ps
CPU time 36.47 seconds
Started Apr 04 12:30:13 PM PDT 24
Finished Apr 04 12:30:50 PM PDT 24
Peak memory 209940 kb
Host smart-dbe8f5f0-738d-4963-b23f-cf8e8a79e420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788871791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2788871791
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.217276733
Short name T467
Test name
Test status
Simulation time 139075981 ps
CPU time 1.72 seconds
Started Apr 04 12:29:52 PM PDT 24
Finished Apr 04 12:29:54 PM PDT 24
Peak memory 200500 kb
Host smart-045f1309-dd1a-4ab0-a277-ab2c9927296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217276733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.217276733
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2328752873
Short name T484
Test name
Test status
Simulation time 159076871 ps
CPU time 1.17 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200508 kb
Host smart-dcd78dee-6c32-407a-a1b2-4a9755052f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328752873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2328752873
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1526631648
Short name T168
Test name
Test status
Simulation time 76073668 ps
CPU time 0.8 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:30:18 PM PDT 24
Peak memory 200164 kb
Host smart-ec84d4af-c318-4664-a5c0-0b767a6601fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526631648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1526631648
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1122358161
Short name T380
Test name
Test status
Simulation time 1217174163 ps
CPU time 6.07 seconds
Started Apr 04 12:30:09 PM PDT 24
Finished Apr 04 12:30:15 PM PDT 24
Peak memory 222348 kb
Host smart-c2291ea3-e0c3-41d2-aa43-7ba9880d5c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122358161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1122358161
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2004042196
Short name T260
Test name
Test status
Simulation time 243981831 ps
CPU time 1.14 seconds
Started Apr 04 12:30:04 PM PDT 24
Finished Apr 04 12:30:05 PM PDT 24
Peak memory 217928 kb
Host smart-9771f57e-a634-4b9e-9219-ea94d9ec0f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004042196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2004042196
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3137521500
Short name T439
Test name
Test status
Simulation time 163499160 ps
CPU time 0.84 seconds
Started Apr 04 12:30:19 PM PDT 24
Finished Apr 04 12:30:20 PM PDT 24
Peak memory 200256 kb
Host smart-032bb415-dd90-40d8-9e4e-e2c8d45f829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137521500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3137521500
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.380519823
Short name T497
Test name
Test status
Simulation time 1419797902 ps
CPU time 5.45 seconds
Started Apr 04 12:29:52 PM PDT 24
Finished Apr 04 12:29:57 PM PDT 24
Peak memory 200548 kb
Host smart-5bb70b32-2cd9-421e-b001-30627dba6cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380519823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.380519823
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3856350938
Short name T459
Test name
Test status
Simulation time 109361445 ps
CPU time 1.09 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:12 PM PDT 24
Peak memory 200456 kb
Host smart-f7b51b1a-431c-4b87-a19a-7874cdb1247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856350938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3856350938
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1646747904
Short name T228
Test name
Test status
Simulation time 117150669 ps
CPU time 1.24 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:30:27 PM PDT 24
Peak memory 200612 kb
Host smart-22c0edf3-4cef-49e9-bbe1-12b3a80ff1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646747904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1646747904
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2604967954
Short name T29
Test name
Test status
Simulation time 4582440023 ps
CPU time 16.91 seconds
Started Apr 04 12:30:22 PM PDT 24
Finished Apr 04 12:30:39 PM PDT 24
Peak memory 200688 kb
Host smart-7e22ff99-0b7a-4b2d-b39d-ddbd4882401b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604967954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2604967954
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2254168886
Short name T211
Test name
Test status
Simulation time 259856788 ps
CPU time 1.75 seconds
Started Apr 04 12:30:51 PM PDT 24
Finished Apr 04 12:30:53 PM PDT 24
Peak memory 200412 kb
Host smart-0ec86c1a-b71d-46c0-aac9-9a2a3dd02671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254168886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2254168886
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3893212538
Short name T540
Test name
Test status
Simulation time 133790262 ps
CPU time 1.09 seconds
Started Apr 04 12:30:17 PM PDT 24
Finished Apr 04 12:30:18 PM PDT 24
Peak memory 200512 kb
Host smart-e96510f3-4ab5-4035-b067-cdbf67676057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893212538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3893212538
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3940716135
Short name T391
Test name
Test status
Simulation time 81082746 ps
CPU time 0.87 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:30:17 PM PDT 24
Peak memory 200240 kb
Host smart-a16bc6e6-2383-46b7-a8b7-a5a0db75d6f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940716135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3940716135
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2539510078
Short name T347
Test name
Test status
Simulation time 2180015641 ps
CPU time 7.46 seconds
Started Apr 04 12:30:09 PM PDT 24
Finished Apr 04 12:30:17 PM PDT 24
Peak memory 217852 kb
Host smart-df4da8dd-03ac-4d7c-a0b9-546f91864f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539510078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2539510078
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.105792023
Short name T4
Test name
Test status
Simulation time 243617261 ps
CPU time 1.16 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:30:17 PM PDT 24
Peak memory 217836 kb
Host smart-10aece9b-98c1-48f2-8c9e-c7fb26b42d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105792023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.105792023
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.951284061
Short name T543
Test name
Test status
Simulation time 175163598 ps
CPU time 0.86 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:31:12 PM PDT 24
Peak memory 200332 kb
Host smart-9e87fcb0-f41f-4d53-8170-fff60746087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951284061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.951284061
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.284277300
Short name T12
Test name
Test status
Simulation time 1110754804 ps
CPU time 5.65 seconds
Started Apr 04 12:30:15 PM PDT 24
Finished Apr 04 12:30:21 PM PDT 24
Peak memory 200624 kb
Host smart-c0477101-7bd6-4660-bd06-cff982b12b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284277300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.284277300
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.206960855
Short name T141
Test name
Test status
Simulation time 188405082 ps
CPU time 1.17 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:30:26 PM PDT 24
Peak memory 200392 kb
Host smart-bfee6c05-8417-4f05-9896-c01f8c2d3d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206960855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.206960855
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.599355855
Short name T236
Test name
Test status
Simulation time 243981221 ps
CPU time 1.53 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 200696 kb
Host smart-bda2fc12-1aa6-4262-8843-5aa7d0071c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599355855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.599355855
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3009812360
Short name T279
Test name
Test status
Simulation time 15648314389 ps
CPU time 57.56 seconds
Started Apr 04 12:30:23 PM PDT 24
Finished Apr 04 12:31:20 PM PDT 24
Peak memory 208884 kb
Host smart-2b122c27-4c18-479e-8f3e-7ef1f467b6fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009812360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3009812360
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.907752690
Short name T170
Test name
Test status
Simulation time 403866572 ps
CPU time 2.14 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:03 PM PDT 24
Peak memory 200480 kb
Host smart-5974e75b-ff5b-4c9b-ae65-34dc297927c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907752690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.907752690
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.4058502723
Short name T364
Test name
Test status
Simulation time 77329442 ps
CPU time 0.78 seconds
Started Apr 04 12:30:10 PM PDT 24
Finished Apr 04 12:30:11 PM PDT 24
Peak memory 200444 kb
Host smart-444929f1-eab9-4366-82ee-cc0ae785873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058502723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.4058502723
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2284244164
Short name T419
Test name
Test status
Simulation time 65079657 ps
CPU time 0.81 seconds
Started Apr 04 12:29:51 PM PDT 24
Finished Apr 04 12:29:52 PM PDT 24
Peak memory 200332 kb
Host smart-1c80e3c0-f8dd-4c2b-9650-110b817d614a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284244164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2284244164
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.4214042977
Short name T374
Test name
Test status
Simulation time 1222452929 ps
CPU time 5.16 seconds
Started Apr 04 12:29:54 PM PDT 24
Finished Apr 04 12:30:00 PM PDT 24
Peak memory 218268 kb
Host smart-59341108-f047-430f-8fdc-e0547a3d13f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214042977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.4214042977
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2996805216
Short name T512
Test name
Test status
Simulation time 244358518 ps
CPU time 1.15 seconds
Started Apr 04 12:29:56 PM PDT 24
Finished Apr 04 12:29:58 PM PDT 24
Peak memory 217816 kb
Host smart-238ed27b-9941-485b-891d-868b40d7b189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996805216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2996805216
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3467067716
Short name T24
Test name
Test status
Simulation time 142481763 ps
CPU time 0.83 seconds
Started Apr 04 12:31:12 PM PDT 24
Finished Apr 04 12:31:13 PM PDT 24
Peak memory 200356 kb
Host smart-2b9f48c3-7915-4e4e-8f6e-50a97ba54186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467067716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3467067716
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.512272686
Short name T105
Test name
Test status
Simulation time 1986252010 ps
CPU time 7.89 seconds
Started Apr 04 12:31:13 PM PDT 24
Finished Apr 04 12:31:21 PM PDT 24
Peak memory 200656 kb
Host smart-80768f6b-ba36-4011-aa59-f49c0010dfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512272686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.512272686
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2416312035
Short name T222
Test name
Test status
Simulation time 180731427 ps
CPU time 1.24 seconds
Started Apr 04 12:29:56 PM PDT 24
Finished Apr 04 12:29:57 PM PDT 24
Peak memory 200388 kb
Host smart-f82c79b5-b77b-4085-9ab4-62750cf4f8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416312035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2416312035
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2110523094
Short name T531
Test name
Test status
Simulation time 202902556 ps
CPU time 1.46 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:31:12 PM PDT 24
Peak memory 200680 kb
Host smart-f38fe865-63c0-4bb6-a39a-479c95b85518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110523094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2110523094
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3073512809
Short name T291
Test name
Test status
Simulation time 3077713943 ps
CPU time 11.14 seconds
Started Apr 04 12:29:48 PM PDT 24
Finished Apr 04 12:30:00 PM PDT 24
Peak memory 200624 kb
Host smart-c696fffb-7cd3-4912-b72b-6560768193ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073512809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3073512809
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1517277743
Short name T353
Test name
Test status
Simulation time 141867413 ps
CPU time 1.77 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200436 kb
Host smart-9e37964c-dba2-458f-84ec-00531dcc3185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517277743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1517277743
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3507749816
Short name T209
Test name
Test status
Simulation time 74610180 ps
CPU time 0.82 seconds
Started Apr 04 12:30:14 PM PDT 24
Finished Apr 04 12:30:15 PM PDT 24
Peak memory 200480 kb
Host smart-8cbb74b5-d1a5-49a2-9da0-058c77842fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507749816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3507749816
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2176920574
Short name T7
Test name
Test status
Simulation time 68746837 ps
CPU time 0.78 seconds
Started Apr 04 12:30:04 PM PDT 24
Finished Apr 04 12:30:05 PM PDT 24
Peak memory 200232 kb
Host smart-ed55acae-7b8f-47e2-a1ba-e3f96c37231b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176920574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2176920574
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.814119672
Short name T372
Test name
Test status
Simulation time 1229782213 ps
CPU time 5.06 seconds
Started Apr 04 12:30:08 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 222300 kb
Host smart-f853e9fe-fd46-48dd-8058-6807d376b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814119672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.814119672
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4265136099
Short name T428
Test name
Test status
Simulation time 244449321 ps
CPU time 1.07 seconds
Started Apr 04 12:29:48 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 217840 kb
Host smart-3ee89cdf-b6f8-41fd-a672-5edef0decd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265136099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4265136099
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.31166869
Short name T280
Test name
Test status
Simulation time 155457954 ps
CPU time 0.83 seconds
Started Apr 04 12:29:50 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200224 kb
Host smart-2b84f0a1-e4bd-4139-a96f-a26f7aa07e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31166869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.31166869
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1532773655
Short name T396
Test name
Test status
Simulation time 1741787042 ps
CPU time 6.36 seconds
Started Apr 04 12:29:59 PM PDT 24
Finished Apr 04 12:30:06 PM PDT 24
Peak memory 200576 kb
Host smart-7588282f-7b03-48a2-b408-d44efde58964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532773655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1532773655
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3795480579
Short name T462
Test name
Test status
Simulation time 147915552 ps
CPU time 1.16 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 200564 kb
Host smart-ce0511f1-ace5-45d3-96c2-871cc4a0c2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795480579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3795480579
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.903462845
Short name T466
Test name
Test status
Simulation time 197609830 ps
CPU time 1.36 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 200712 kb
Host smart-61a893a2-5037-44ef-8b7c-810ae77fabc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903462845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.903462845
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3095466325
Short name T413
Test name
Test status
Simulation time 1755162491 ps
CPU time 6.3 seconds
Started Apr 04 12:29:50 PM PDT 24
Finished Apr 04 12:29:56 PM PDT 24
Peak memory 200648 kb
Host smart-8039c9b0-62b0-48c4-b543-0bf3047946be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095466325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3095466325
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1839103632
Short name T313
Test name
Test status
Simulation time 476662378 ps
CPU time 2.42 seconds
Started Apr 04 12:29:49 PM PDT 24
Finished Apr 04 12:29:52 PM PDT 24
Peak memory 208636 kb
Host smart-6e81dcb0-797c-4ca4-bb4e-f0a637fc6dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839103632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1839103632
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.17745147
Short name T346
Test name
Test status
Simulation time 128202041 ps
CPU time 1.16 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 200428 kb
Host smart-fd8c1a74-ab35-404b-be18-dcd49f66608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17745147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.17745147
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1974834244
Short name T441
Test name
Test status
Simulation time 84740360 ps
CPU time 0.89 seconds
Started Apr 04 12:30:03 PM PDT 24
Finished Apr 04 12:30:04 PM PDT 24
Peak memory 200344 kb
Host smart-f23b08f7-165a-44e5-9c96-1ab2e140f8f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974834244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1974834244
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4177465182
Short name T469
Test name
Test status
Simulation time 2356975532 ps
CPU time 8.28 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 222424 kb
Host smart-a5102f54-6b07-424e-8872-2963bb319b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177465182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4177465182
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.120114887
Short name T465
Test name
Test status
Simulation time 243908052 ps
CPU time 1.05 seconds
Started Apr 04 12:31:26 PM PDT 24
Finished Apr 04 12:31:28 PM PDT 24
Peak memory 217936 kb
Host smart-7b1fbff8-d772-486f-9c93-0b64fd321df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120114887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.120114887
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.500376957
Short name T395
Test name
Test status
Simulation time 204573320 ps
CPU time 0.88 seconds
Started Apr 04 12:29:50 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200332 kb
Host smart-34ea4005-8a07-4eb8-a630-756936f8bb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500376957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.500376957
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2712492823
Short name T161
Test name
Test status
Simulation time 1372787379 ps
CPU time 6 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:30:59 PM PDT 24
Peak memory 200608 kb
Host smart-8e35b066-ca2f-4019-9909-1c6a3506dba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712492823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2712492823
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1586761533
Short name T362
Test name
Test status
Simulation time 161523467 ps
CPU time 1.14 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:12 PM PDT 24
Peak memory 200480 kb
Host smart-7e34574b-2eab-4f50-b53d-88c4287f5a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586761533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1586761533
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3515396700
Short name T183
Test name
Test status
Simulation time 117373296 ps
CPU time 1.25 seconds
Started Apr 04 12:29:50 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 200628 kb
Host smart-e18072f6-602e-494a-834d-27398bc052bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515396700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3515396700
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1102351717
Short name T284
Test name
Test status
Simulation time 3256475935 ps
CPU time 12.01 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:30:29 PM PDT 24
Peak memory 208748 kb
Host smart-7c9c8d2b-a05b-4845-933d-4bd124e454c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102351717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1102351717
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3967537204
Short name T528
Test name
Test status
Simulation time 135647702 ps
CPU time 1.63 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:30:57 PM PDT 24
Peak memory 208736 kb
Host smart-4fd7d7c2-e6bf-4d8a-a48d-4151eef531df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967537204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3967537204
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2785562821
Short name T324
Test name
Test status
Simulation time 83906686 ps
CPU time 0.85 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:12 PM PDT 24
Peak memory 200376 kb
Host smart-f414d12b-08f8-4881-9bd1-9e62817ca3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785562821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2785562821
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.705999776
Short name T187
Test name
Test status
Simulation time 75573341 ps
CPU time 0.82 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:28:56 PM PDT 24
Peak memory 199108 kb
Host smart-a0692542-ef0b-4f0b-b345-e65e9158971d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705999776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.705999776
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1760844589
Short name T54
Test name
Test status
Simulation time 1222334395 ps
CPU time 5.97 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:58 PM PDT 24
Peak memory 217976 kb
Host smart-5aa3f6a3-16dc-4596-bfd5-5b30672c0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760844589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1760844589
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.168717503
Short name T332
Test name
Test status
Simulation time 243583233 ps
CPU time 1.16 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 216900 kb
Host smart-1858adc7-de19-4b07-8326-ec741ca8c58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168717503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.168717503
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3692336198
Short name T286
Test name
Test status
Simulation time 167699195 ps
CPU time 0.84 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 199908 kb
Host smart-b4a40674-cd10-4d73-95c2-aebd7a17cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692336198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3692336198
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1465385587
Short name T122
Test name
Test status
Simulation time 1540204640 ps
CPU time 5.53 seconds
Started Apr 04 12:27:50 PM PDT 24
Finished Apr 04 12:27:56 PM PDT 24
Peak memory 200520 kb
Host smart-33a657c6-709e-419c-9dcd-9f79c865960c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465385587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1465385587
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3705091644
Short name T73
Test name
Test status
Simulation time 8449592080 ps
CPU time 12.74 seconds
Started Apr 04 12:29:37 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 217548 kb
Host smart-fbffb91a-aed4-4797-acea-9422ec6d16e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705091644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3705091644
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.545295649
Short name T427
Test name
Test status
Simulation time 111817991 ps
CPU time 0.96 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:06 PM PDT 24
Peak memory 200344 kb
Host smart-a26f7de5-6c6f-4c89-89a2-9a2097d9c9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545295649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.545295649
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.4252741677
Short name T234
Test name
Test status
Simulation time 242941620 ps
CPU time 1.56 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 200592 kb
Host smart-39ea9033-792d-46b5-99ec-a90872194edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252741677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.4252741677
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1397838718
Short name T312
Test name
Test status
Simulation time 1868054570 ps
CPU time 6.8 seconds
Started Apr 04 12:29:18 PM PDT 24
Finished Apr 04 12:29:25 PM PDT 24
Peak memory 210144 kb
Host smart-7148dcfa-71d7-4e26-a47b-efe0664550af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397838718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1397838718
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1797018700
Short name T527
Test name
Test status
Simulation time 142948884 ps
CPU time 1.84 seconds
Started Apr 04 12:27:49 PM PDT 24
Finished Apr 04 12:27:51 PM PDT 24
Peak memory 200092 kb
Host smart-955ae928-d349-42ae-841a-b699fea4cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797018700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1797018700
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.768796864
Short name T305
Test name
Test status
Simulation time 82694309 ps
CPU time 0.82 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 200148 kb
Host smart-0ab8ac47-ecf4-4125-997f-5b1867736702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768796864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.768796864
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1222780514
Short name T266
Test name
Test status
Simulation time 83329230 ps
CPU time 0.81 seconds
Started Apr 04 12:30:20 PM PDT 24
Finished Apr 04 12:30:21 PM PDT 24
Peak memory 200308 kb
Host smart-7fb5eec3-4bfd-44f8-8cc8-ff89752ea64c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222780514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1222780514
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.356225645
Short name T224
Test name
Test status
Simulation time 1907457293 ps
CPU time 7.18 seconds
Started Apr 04 12:30:05 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 222276 kb
Host smart-aa9c339c-0ff2-4e0a-ba34-9b382417513a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356225645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.356225645
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1886214393
Short name T272
Test name
Test status
Simulation time 244199931 ps
CPU time 1.09 seconds
Started Apr 04 12:29:57 PM PDT 24
Finished Apr 04 12:29:59 PM PDT 24
Peak memory 217844 kb
Host smart-37bb5254-caac-4b39-8b03-eaf8d93de76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886214393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1886214393
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2277706552
Short name T426
Test name
Test status
Simulation time 130485137 ps
CPU time 0.8 seconds
Started Apr 04 12:30:04 PM PDT 24
Finished Apr 04 12:30:04 PM PDT 24
Peak memory 200332 kb
Host smart-2c858990-f8d0-4642-99fc-f95da214b785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277706552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2277706552
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3838731840
Short name T340
Test name
Test status
Simulation time 793416124 ps
CPU time 3.88 seconds
Started Apr 04 12:30:10 PM PDT 24
Finished Apr 04 12:30:14 PM PDT 24
Peak memory 200616 kb
Host smart-66930fef-4cc3-4dfb-8966-7fe652c0f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838731840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3838731840
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2536246703
Short name T397
Test name
Test status
Simulation time 181858055 ps
CPU time 1.3 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:14 PM PDT 24
Peak memory 200564 kb
Host smart-ab3a9fdb-1aa8-4e6b-be10-23d64daf56df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536246703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2536246703
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.999038241
Short name T336
Test name
Test status
Simulation time 244735850 ps
CPU time 1.62 seconds
Started Apr 04 12:30:02 PM PDT 24
Finished Apr 04 12:30:04 PM PDT 24
Peak memory 200636 kb
Host smart-b63fda2c-55a5-440c-9df4-e73af5128765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999038241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.999038241
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.720460513
Short name T210
Test name
Test status
Simulation time 15092160087 ps
CPU time 47.86 seconds
Started Apr 04 12:30:09 PM PDT 24
Finished Apr 04 12:30:57 PM PDT 24
Peak memory 208920 kb
Host smart-d2082b3c-b3ba-492b-b545-6f905c329e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720460513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.720460513
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2254889230
Short name T164
Test name
Test status
Simulation time 154497050 ps
CPU time 2.01 seconds
Started Apr 04 12:30:05 PM PDT 24
Finished Apr 04 12:30:08 PM PDT 24
Peak memory 200508 kb
Host smart-31e46f0a-73f5-4709-85c2-c7832c2714ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254889230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2254889230
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.600845676
Short name T99
Test name
Test status
Simulation time 85781663 ps
CPU time 0.84 seconds
Started Apr 04 12:29:54 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 200444 kb
Host smart-8c483502-ea52-402d-be0e-0098c284b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600845676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.600845676
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.322847144
Short name T437
Test name
Test status
Simulation time 70165641 ps
CPU time 0.79 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 200344 kb
Host smart-7a826334-6683-4836-83af-2f774de8f6f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322847144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.322847144
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1951012344
Short name T486
Test name
Test status
Simulation time 244321354 ps
CPU time 1.22 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:30:26 PM PDT 24
Peak memory 217936 kb
Host smart-f5e467df-0084-49f4-ad50-303c827c7851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951012344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1951012344
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1750998043
Short name T444
Test name
Test status
Simulation time 206453949 ps
CPU time 0.89 seconds
Started Apr 04 12:30:13 PM PDT 24
Finished Apr 04 12:30:14 PM PDT 24
Peak memory 200288 kb
Host smart-b10c18f2-e5f2-473f-87a7-d915313c280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750998043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1750998043
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2699738894
Short name T216
Test name
Test status
Simulation time 1987540196 ps
CPU time 8.22 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:20 PM PDT 24
Peak memory 200724 kb
Host smart-58cba4fc-c434-4220-a0cc-b454a187de1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699738894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2699738894
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.963382374
Short name T28
Test name
Test status
Simulation time 151576710 ps
CPU time 1.12 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 200468 kb
Host smart-7c4260fe-f680-4ff3-9356-0a269c0c46e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963382374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.963382374
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.935708791
Short name T259
Test name
Test status
Simulation time 242079841 ps
CPU time 1.56 seconds
Started Apr 04 12:30:04 PM PDT 24
Finished Apr 04 12:30:06 PM PDT 24
Peak memory 200624 kb
Host smart-d012b66f-7502-422d-8182-799dee8aa291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935708791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.935708791
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1197706909
Short name T349
Test name
Test status
Simulation time 5244691828 ps
CPU time 19.23 seconds
Started Apr 04 12:30:10 PM PDT 24
Finished Apr 04 12:30:29 PM PDT 24
Peak memory 208876 kb
Host smart-e1f68223-9fc3-442a-90cc-f2c4a896f211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197706909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1197706909
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1227465855
Short name T197
Test name
Test status
Simulation time 392530831 ps
CPU time 2.08 seconds
Started Apr 04 12:30:35 PM PDT 24
Finished Apr 04 12:30:37 PM PDT 24
Peak memory 200424 kb
Host smart-2182c548-65b2-4827-a2ba-7415a68f111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227465855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1227465855
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3404615193
Short name T206
Test name
Test status
Simulation time 166485325 ps
CPU time 1.35 seconds
Started Apr 04 12:30:21 PM PDT 24
Finished Apr 04 12:30:22 PM PDT 24
Peak memory 200584 kb
Host smart-b42c52bd-2f9c-44d4-8890-26865e3ce196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404615193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3404615193
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1199301933
Short name T162
Test name
Test status
Simulation time 89448888 ps
CPU time 0.93 seconds
Started Apr 04 12:30:05 PM PDT 24
Finished Apr 04 12:30:06 PM PDT 24
Peak memory 200340 kb
Host smart-98354b4f-e783-41b5-99fd-48a2a06721ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199301933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1199301933
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1375050565
Short name T45
Test name
Test status
Simulation time 2355958667 ps
CPU time 8.48 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:30:25 PM PDT 24
Peak memory 218336 kb
Host smart-258973af-234c-47dd-a860-f524cdcd6c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375050565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1375050565
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2588887312
Short name T509
Test name
Test status
Simulation time 243982701 ps
CPU time 1.11 seconds
Started Apr 04 12:30:21 PM PDT 24
Finished Apr 04 12:30:22 PM PDT 24
Peak memory 217852 kb
Host smart-d751f5a0-e073-4fa3-9665-156d0252bf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588887312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2588887312
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2911623149
Short name T454
Test name
Test status
Simulation time 228330051 ps
CPU time 0.96 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 200352 kb
Host smart-93487db8-ffa4-4169-b038-b38ea199de30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911623149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2911623149
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.287848619
Short name T433
Test name
Test status
Simulation time 1610201192 ps
CPU time 6.45 seconds
Started Apr 04 12:30:21 PM PDT 24
Finished Apr 04 12:30:27 PM PDT 24
Peak memory 200668 kb
Host smart-fa6732dc-4eae-4d87-8145-6f7adaa6a7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287848619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.287848619
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3059364619
Short name T373
Test name
Test status
Simulation time 176787773 ps
CPU time 1.28 seconds
Started Apr 04 12:30:28 PM PDT 24
Finished Apr 04 12:30:29 PM PDT 24
Peak memory 200468 kb
Host smart-d8be508b-e156-4e03-8b6d-67c3642c3ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059364619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3059364619
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1494556447
Short name T515
Test name
Test status
Simulation time 123940032 ps
CPU time 1.26 seconds
Started Apr 04 12:30:29 PM PDT 24
Finished Apr 04 12:30:30 PM PDT 24
Peak memory 200572 kb
Host smart-35febd56-1bf1-4776-ba65-638e1d62f40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494556447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1494556447
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.46764879
Short name T337
Test name
Test status
Simulation time 3097048947 ps
CPU time 13.44 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:26 PM PDT 24
Peak memory 200692 kb
Host smart-43e477aa-cdac-4da7-861f-11b0633391c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46764879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.46764879
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.484159959
Short name T330
Test name
Test status
Simulation time 344282139 ps
CPU time 1.93 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:14 PM PDT 24
Peak memory 200480 kb
Host smart-4e4b5f02-efab-4ca0-96ff-7b2bab75e3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484159959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.484159959
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1442428881
Short name T131
Test name
Test status
Simulation time 271000636 ps
CPU time 1.43 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:27 PM PDT 24
Peak memory 200452 kb
Host smart-2ed73fa8-58b9-4ec8-8083-f3389597af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442428881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1442428881
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1400391880
Short name T389
Test name
Test status
Simulation time 69993431 ps
CPU time 0.79 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:30:18 PM PDT 24
Peak memory 200312 kb
Host smart-4aa13958-bdb9-4927-9868-7c3a978ad7aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400391880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1400391880
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2616227809
Short name T41
Test name
Test status
Simulation time 1225740694 ps
CPU time 5.61 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:30:31 PM PDT 24
Peak memory 218300 kb
Host smart-8629af16-0487-495e-9f90-8eb01cf080c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616227809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2616227809
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3243200337
Short name T159
Test name
Test status
Simulation time 244079303 ps
CPU time 1.1 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:30:27 PM PDT 24
Peak memory 217944 kb
Host smart-bf68e313-1d5d-40ab-b110-3eae6bcc0aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243200337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3243200337
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3440931473
Short name T468
Test name
Test status
Simulation time 191242181 ps
CPU time 0.95 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:12 PM PDT 24
Peak memory 200276 kb
Host smart-08403f07-382f-4818-9bcb-51803282a2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440931473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3440931473
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2396444411
Short name T341
Test name
Test status
Simulation time 1647046108 ps
CPU time 6.23 seconds
Started Apr 04 12:30:30 PM PDT 24
Finished Apr 04 12:30:36 PM PDT 24
Peak memory 200664 kb
Host smart-96496c74-395e-468e-ae51-2617f92acce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396444411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2396444411
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3426249198
Short name T480
Test name
Test status
Simulation time 182939974 ps
CPU time 1.13 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:38 PM PDT 24
Peak memory 200488 kb
Host smart-c5a44e9c-e8f8-4927-9a94-4dd291b1d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426249198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3426249198
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.187285969
Short name T445
Test name
Test status
Simulation time 187537675 ps
CPU time 1.3 seconds
Started Apr 04 12:30:30 PM PDT 24
Finished Apr 04 12:30:32 PM PDT 24
Peak memory 200624 kb
Host smart-8e4b2038-d87c-4865-bf2d-6f888c7adaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187285969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.187285969
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.475256852
Short name T100
Test name
Test status
Simulation time 159033247 ps
CPU time 1.97 seconds
Started Apr 04 12:30:08 PM PDT 24
Finished Apr 04 12:30:10 PM PDT 24
Peak memory 200540 kb
Host smart-1488054b-9dc8-415d-aa6c-752c3b36ad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475256852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.475256852
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1440538943
Short name T218
Test name
Test status
Simulation time 141233566 ps
CPU time 1.17 seconds
Started Apr 04 12:30:07 PM PDT 24
Finished Apr 04 12:30:09 PM PDT 24
Peak memory 200656 kb
Host smart-06897467-459a-41ff-9e36-e1249bf3c667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440538943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1440538943
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4070463528
Short name T442
Test name
Test status
Simulation time 84201229 ps
CPU time 0.83 seconds
Started Apr 04 12:30:45 PM PDT 24
Finished Apr 04 12:30:46 PM PDT 24
Peak memory 200204 kb
Host smart-1bf681f0-8e31-4c8c-8ccd-1fe0d105803c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070463528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4070463528
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.733133359
Short name T42
Test name
Test status
Simulation time 2358510699 ps
CPU time 8.88 seconds
Started Apr 04 12:30:05 PM PDT 24
Finished Apr 04 12:30:14 PM PDT 24
Peak memory 222424 kb
Host smart-75746d22-13d0-4993-b430-8ef83ec81820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733133359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.733133359
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1681322659
Short name T158
Test name
Test status
Simulation time 244908886 ps
CPU time 1.13 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 217944 kb
Host smart-958b2eb1-d06c-4d94-9c8d-9c415ebf5dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681322659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1681322659
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3706708735
Short name T532
Test name
Test status
Simulation time 187320856 ps
CPU time 0.85 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:27 PM PDT 24
Peak memory 200336 kb
Host smart-bc42b8ab-a3f1-4efb-8d09-400207f77796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706708735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3706708735
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1035375698
Short name T311
Test name
Test status
Simulation time 1844096321 ps
CPU time 7.1 seconds
Started Apr 04 12:30:19 PM PDT 24
Finished Apr 04 12:30:26 PM PDT 24
Peak memory 200636 kb
Host smart-ae93993f-4f74-416d-a75b-e6e4e518e622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035375698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1035375698
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3478949533
Short name T520
Test name
Test status
Simulation time 93403216 ps
CPU time 0.98 seconds
Started Apr 04 12:30:48 PM PDT 24
Finished Apr 04 12:30:49 PM PDT 24
Peak memory 200460 kb
Host smart-1e1fe78b-b01c-4791-9baa-f48ec7c7f350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478949533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3478949533
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2876923227
Short name T221
Test name
Test status
Simulation time 122567169 ps
CPU time 1.19 seconds
Started Apr 04 12:30:23 PM PDT 24
Finished Apr 04 12:30:24 PM PDT 24
Peak memory 200572 kb
Host smart-f0926b64-338e-47a1-bf8c-d995d3be6df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876923227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2876923227
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3530640965
Short name T160
Test name
Test status
Simulation time 1907878495 ps
CPU time 7.12 seconds
Started Apr 04 12:30:33 PM PDT 24
Finished Apr 04 12:30:40 PM PDT 24
Peak memory 200664 kb
Host smart-ddf03ae2-e7eb-4e1f-9359-d6c255644357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530640965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3530640965
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.217337656
Short name T186
Test name
Test status
Simulation time 126956209 ps
CPU time 1.55 seconds
Started Apr 04 12:30:19 PM PDT 24
Finished Apr 04 12:30:21 PM PDT 24
Peak memory 208900 kb
Host smart-1d2cfa1a-68d4-42ed-a9b3-d2c54ba8066d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217337656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.217337656
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2850339440
Short name T308
Test name
Test status
Simulation time 135901857 ps
CPU time 1.07 seconds
Started Apr 04 12:30:45 PM PDT 24
Finished Apr 04 12:30:46 PM PDT 24
Peak memory 200316 kb
Host smart-f3b5fce0-5d42-4a1e-93b2-0fc52bf5b54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850339440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2850339440
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3263550132
Short name T269
Test name
Test status
Simulation time 72524096 ps
CPU time 0.79 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:30:26 PM PDT 24
Peak memory 200404 kb
Host smart-523e35be-daa6-41be-9c79-8edca7104b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263550132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3263550132
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3574500598
Short name T36
Test name
Test status
Simulation time 1232201498 ps
CPU time 5.61 seconds
Started Apr 04 12:30:24 PM PDT 24
Finished Apr 04 12:30:30 PM PDT 24
Peak memory 218280 kb
Host smart-a51f8a61-b59c-4086-8752-2b8c10bd9587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574500598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3574500598
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4213418910
Short name T57
Test name
Test status
Simulation time 245496490 ps
CPU time 1.09 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:38 PM PDT 24
Peak memory 217824 kb
Host smart-4fabb614-878d-4a48-8e55-b89ebf9fd500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213418910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4213418910
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3531529597
Short name T418
Test name
Test status
Simulation time 220166215 ps
CPU time 0.89 seconds
Started Apr 04 12:30:19 PM PDT 24
Finished Apr 04 12:30:20 PM PDT 24
Peak memory 200352 kb
Host smart-453ff9c8-b764-4867-aab9-b45bc8b63ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531529597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3531529597
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1323383304
Short name T253
Test name
Test status
Simulation time 893279102 ps
CPU time 4.4 seconds
Started Apr 04 12:30:20 PM PDT 24
Finished Apr 04 12:30:24 PM PDT 24
Peak memory 200648 kb
Host smart-18ca5980-6585-4c8a-a792-5d3cc408a0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323383304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1323383304
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2783945946
Short name T369
Test name
Test status
Simulation time 95278780 ps
CPU time 1.01 seconds
Started Apr 04 12:30:21 PM PDT 24
Finished Apr 04 12:30:22 PM PDT 24
Peak memory 200456 kb
Host smart-128a8cb5-f4d8-4fbe-8745-a3a32661cd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783945946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2783945946
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.216109473
Short name T333
Test name
Test status
Simulation time 198789189 ps
CPU time 1.34 seconds
Started Apr 04 12:30:14 PM PDT 24
Finished Apr 04 12:30:16 PM PDT 24
Peak memory 200648 kb
Host smart-c0ebed93-e7df-480c-b428-d6e5187086f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216109473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.216109473
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2039363871
Short name T109
Test name
Test status
Simulation time 4169516608 ps
CPU time 18.44 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:30:43 PM PDT 24
Peak memory 200612 kb
Host smart-7020c472-bb2f-4ae5-a41e-0f8903aa47ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039363871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2039363871
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.288088761
Short name T351
Test name
Test status
Simulation time 269289320 ps
CPU time 1.86 seconds
Started Apr 04 12:30:20 PM PDT 24
Finished Apr 04 12:30:22 PM PDT 24
Peak memory 200500 kb
Host smart-736e984a-5154-4655-865b-4dcf846e95cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288088761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.288088761
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.410238859
Short name T345
Test name
Test status
Simulation time 159787570 ps
CPU time 1.05 seconds
Started Apr 04 12:30:23 PM PDT 24
Finished Apr 04 12:30:24 PM PDT 24
Peak memory 200392 kb
Host smart-cba7a766-53a6-404c-b071-20f69e9112cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410238859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.410238859
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.929233092
Short name T50
Test name
Test status
Simulation time 73778601 ps
CPU time 0.83 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:30:27 PM PDT 24
Peak memory 200416 kb
Host smart-939e2235-a58a-4372-a167-6406e420d38a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929233092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.929233092
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2304017877
Short name T298
Test name
Test status
Simulation time 2190506137 ps
CPU time 8.18 seconds
Started Apr 04 12:30:28 PM PDT 24
Finished Apr 04 12:30:36 PM PDT 24
Peak memory 217892 kb
Host smart-4c5dd259-16ad-48e6-ac50-436dca13be74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304017877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2304017877
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1993572377
Short name T172
Test name
Test status
Simulation time 244917706 ps
CPU time 1.12 seconds
Started Apr 04 12:30:35 PM PDT 24
Finished Apr 04 12:30:36 PM PDT 24
Peak memory 217768 kb
Host smart-3f0d860a-5532-47e4-a668-bd12bda2e7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993572377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1993572377
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3091775469
Short name T303
Test name
Test status
Simulation time 213159899 ps
CPU time 0.92 seconds
Started Apr 04 12:30:49 PM PDT 24
Finished Apr 04 12:30:50 PM PDT 24
Peak memory 200248 kb
Host smart-a45d1b00-d0c8-4316-8aba-c8343df767c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091775469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3091775469
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.818388780
Short name T126
Test name
Test status
Simulation time 2061055783 ps
CPU time 7.44 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:30:33 PM PDT 24
Peak memory 200736 kb
Host smart-2428a573-ff6c-4b85-a077-f4be065365e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818388780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.818388780
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.515386432
Short name T252
Test name
Test status
Simulation time 180659367 ps
CPU time 1.25 seconds
Started Apr 04 12:29:58 PM PDT 24
Finished Apr 04 12:30:00 PM PDT 24
Peak memory 200404 kb
Host smart-8b37765a-cd7b-4837-89c8-0db244b272e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515386432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.515386432
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.760065389
Short name T77
Test name
Test status
Simulation time 244372170 ps
CPU time 1.51 seconds
Started Apr 04 12:30:35 PM PDT 24
Finished Apr 04 12:30:36 PM PDT 24
Peak memory 200544 kb
Host smart-7f308209-2707-4f1e-bdb7-77f0a9bb5b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760065389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.760065389
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1818338921
Short name T455
Test name
Test status
Simulation time 1512084341 ps
CPU time 6.82 seconds
Started Apr 04 12:30:30 PM PDT 24
Finished Apr 04 12:30:38 PM PDT 24
Peak memory 208972 kb
Host smart-5d3947b9-5b03-4dce-b806-f9f67f4b6f9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818338921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1818338921
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1479385696
Short name T13
Test name
Test status
Simulation time 482359901 ps
CPU time 2.67 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:30 PM PDT 24
Peak memory 208704 kb
Host smart-61bd740a-97eb-4a9c-a3ec-dae211d1df2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479385696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1479385696
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.700843533
Short name T270
Test name
Test status
Simulation time 102163792 ps
CPU time 0.97 seconds
Started Apr 04 12:30:44 PM PDT 24
Finished Apr 04 12:30:45 PM PDT 24
Peak memory 200368 kb
Host smart-2e7d2f80-fe3d-4ceb-92d2-77b9227cf009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700843533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.700843533
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.193647324
Short name T533
Test name
Test status
Simulation time 84873019 ps
CPU time 0.84 seconds
Started Apr 04 12:30:10 PM PDT 24
Finished Apr 04 12:30:11 PM PDT 24
Peak memory 200176 kb
Host smart-129cf9c3-8b83-4402-a45c-ad999c8ae808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193647324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.193647324
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3960092217
Short name T39
Test name
Test status
Simulation time 1885089490 ps
CPU time 7.25 seconds
Started Apr 04 12:30:08 PM PDT 24
Finished Apr 04 12:30:15 PM PDT 24
Peak memory 218304 kb
Host smart-6735d8ba-8cd6-483b-934c-c2592eb41117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960092217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3960092217
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3345535944
Short name T477
Test name
Test status
Simulation time 244081997 ps
CPU time 1.19 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:39 PM PDT 24
Peak memory 217892 kb
Host smart-8774cc83-c586-4d96-afff-70d988af7bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345535944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3345535944
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2631252570
Short name T239
Test name
Test status
Simulation time 149982134 ps
CPU time 0.85 seconds
Started Apr 04 12:30:43 PM PDT 24
Finished Apr 04 12:30:44 PM PDT 24
Peak memory 200316 kb
Host smart-1ab4a8c3-0e58-4691-bd91-a47001d3b48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631252570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2631252570
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.512336028
Short name T106
Test name
Test status
Simulation time 1890212035 ps
CPU time 7.68 seconds
Started Apr 04 12:30:17 PM PDT 24
Finished Apr 04 12:30:24 PM PDT 24
Peak memory 200628 kb
Host smart-0f27fe30-f597-4f9f-8dc6-4120f2e2510b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512336028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.512336028
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4224117791
Short name T33
Test name
Test status
Simulation time 100817072 ps
CPU time 1.01 seconds
Started Apr 04 12:30:33 PM PDT 24
Finished Apr 04 12:30:34 PM PDT 24
Peak memory 200376 kb
Host smart-9d46362e-8ba1-4361-9d31-5c5fec018143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224117791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4224117791
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2240178627
Short name T411
Test name
Test status
Simulation time 114772172 ps
CPU time 1.22 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:30:54 PM PDT 24
Peak memory 200588 kb
Host smart-b12e1a1e-60f6-435e-9ad7-7e85b10e2157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240178627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2240178627
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.71170939
Short name T263
Test name
Test status
Simulation time 11315332898 ps
CPU time 38.88 seconds
Started Apr 04 12:30:10 PM PDT 24
Finished Apr 04 12:30:49 PM PDT 24
Peak memory 200676 kb
Host smart-510ef72f-5245-4b66-bb7e-ad78152666e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71170939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.71170939
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1276275910
Short name T423
Test name
Test status
Simulation time 128705456 ps
CPU time 1.71 seconds
Started Apr 04 12:30:01 PM PDT 24
Finished Apr 04 12:30:03 PM PDT 24
Peak memory 208728 kb
Host smart-d1b37db9-8b6d-4ff3-9e8f-d41fdf40fab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276275910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1276275910
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1670258682
Short name T472
Test name
Test status
Simulation time 153779787 ps
CPU time 1.17 seconds
Started Apr 04 12:30:48 PM PDT 24
Finished Apr 04 12:30:49 PM PDT 24
Peak memory 200548 kb
Host smart-b31e207f-7946-473e-bada-827b57445520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670258682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1670258682
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4207903808
Short name T530
Test name
Test status
Simulation time 75489525 ps
CPU time 0.73 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:30:54 PM PDT 24
Peak memory 200292 kb
Host smart-751d2037-2f94-4a88-a252-c556cd41ce4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207903808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4207903808
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.747281735
Short name T534
Test name
Test status
Simulation time 1224465850 ps
CPU time 5.79 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:31:02 PM PDT 24
Peak memory 217780 kb
Host smart-6f03dd48-39b7-4b90-b4f1-a7a002e0cde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747281735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.747281735
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1906986644
Short name T402
Test name
Test status
Simulation time 244496653 ps
CPU time 1.1 seconds
Started Apr 04 12:30:09 PM PDT 24
Finished Apr 04 12:30:10 PM PDT 24
Peak memory 217888 kb
Host smart-09520bc2-d35f-407d-a117-dd3527002e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906986644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1906986644
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1704256046
Short name T242
Test name
Test status
Simulation time 197691127 ps
CPU time 1.09 seconds
Started Apr 04 12:30:19 PM PDT 24
Finished Apr 04 12:30:20 PM PDT 24
Peak memory 200244 kb
Host smart-9822c7e3-0c58-4f50-8de3-77b59b31da4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704256046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1704256046
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2756628001
Short name T393
Test name
Test status
Simulation time 1010155472 ps
CPU time 4.57 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:32 PM PDT 24
Peak memory 200636 kb
Host smart-454030c6-4906-489f-a5b3-cbcd4644ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756628001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2756628001
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3603659145
Short name T370
Test name
Test status
Simulation time 115906507 ps
CPU time 1.14 seconds
Started Apr 04 12:30:11 PM PDT 24
Finished Apr 04 12:30:12 PM PDT 24
Peak memory 200376 kb
Host smart-8c7af957-9ad2-4809-ad43-a47b453a1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603659145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3603659145
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2898858130
Short name T154
Test name
Test status
Simulation time 119400656 ps
CPU time 1.16 seconds
Started Apr 04 12:30:31 PM PDT 24
Finished Apr 04 12:30:32 PM PDT 24
Peak memory 200560 kb
Host smart-bb32d22f-f2f5-4bda-9466-431e99d34ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898858130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2898858130
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3061908214
Short name T108
Test name
Test status
Simulation time 4452193630 ps
CPU time 20.17 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:31:16 PM PDT 24
Peak memory 200804 kb
Host smart-1df73187-863d-4f6e-ac0c-1da327ebf893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061908214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3061908214
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3046734944
Short name T386
Test name
Test status
Simulation time 275575313 ps
CPU time 1.98 seconds
Started Apr 04 12:30:32 PM PDT 24
Finished Apr 04 12:30:34 PM PDT 24
Peak memory 200424 kb
Host smart-0976fbd7-2f04-4cfe-b4a9-9ea6f6c8dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046734944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3046734944
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3543150100
Short name T137
Test name
Test status
Simulation time 84280397 ps
CPU time 0.87 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 200448 kb
Host smart-7039cb82-f4df-4bcc-b043-2e2238cb0d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543150100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3543150100
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1628473726
Short name T268
Test name
Test status
Simulation time 86616772 ps
CPU time 0.85 seconds
Started Apr 04 12:30:32 PM PDT 24
Finished Apr 04 12:30:33 PM PDT 24
Peak memory 200352 kb
Host smart-2e7aa141-ec60-48f9-b2ee-058dc5ccf67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628473726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1628473726
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.909744190
Short name T453
Test name
Test status
Simulation time 2351389250 ps
CPU time 7.89 seconds
Started Apr 04 12:30:16 PM PDT 24
Finished Apr 04 12:30:25 PM PDT 24
Peak memory 218040 kb
Host smart-70cef2ba-ffc6-4c3c-b241-50f03298bb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909744190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.909744190
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1203277269
Short name T155
Test name
Test status
Simulation time 243565812 ps
CPU time 1.05 seconds
Started Apr 04 12:30:12 PM PDT 24
Finished Apr 04 12:30:13 PM PDT 24
Peak memory 217840 kb
Host smart-f38f1e7c-e387-421d-a06e-e4b018f2ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203277269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1203277269
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1657295363
Short name T451
Test name
Test status
Simulation time 112988174 ps
CPU time 0.75 seconds
Started Apr 04 12:30:20 PM PDT 24
Finished Apr 04 12:30:21 PM PDT 24
Peak memory 200320 kb
Host smart-20420dc4-d32d-450b-a6a3-ee70e61d5cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657295363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1657295363
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3139469682
Short name T334
Test name
Test status
Simulation time 1954828545 ps
CPU time 8.18 seconds
Started Apr 04 12:30:31 PM PDT 24
Finished Apr 04 12:30:39 PM PDT 24
Peak memory 200660 kb
Host smart-04ec1922-832e-41cb-a9c0-73e33a3532ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139469682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3139469682
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3618822320
Short name T156
Test name
Test status
Simulation time 150741537 ps
CPU time 1.15 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 200376 kb
Host smart-ef18cebb-1d73-46c2-9c95-a20e3d826f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618822320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3618822320
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1362739787
Short name T322
Test name
Test status
Simulation time 195915022 ps
CPU time 1.43 seconds
Started Apr 04 12:30:47 PM PDT 24
Finished Apr 04 12:30:48 PM PDT 24
Peak memory 200568 kb
Host smart-ac1d7232-d8b9-4ad8-87fe-b6117d2cfcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362739787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1362739787
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1111170044
Short name T133
Test name
Test status
Simulation time 3843384965 ps
CPU time 14.22 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:41 PM PDT 24
Peak memory 208880 kb
Host smart-88877f82-a09e-48e4-b533-de67964f9378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111170044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1111170044
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2139040163
Short name T198
Test name
Test status
Simulation time 379749905 ps
CPU time 2.5 seconds
Started Apr 04 12:30:26 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 200408 kb
Host smart-1d7ddd95-ee7a-4930-9760-1f14927d8ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139040163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2139040163
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3412873357
Short name T327
Test name
Test status
Simulation time 94656056 ps
CPU time 0.9 seconds
Started Apr 04 12:30:27 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 200440 kb
Host smart-09180142-28d5-466c-ad3f-625101d43c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412873357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3412873357
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1746505925
Short name T214
Test name
Test status
Simulation time 68081828 ps
CPU time 0.79 seconds
Started Apr 04 12:29:25 PM PDT 24
Finished Apr 04 12:29:27 PM PDT 24
Peak memory 200276 kb
Host smart-29cf022b-7a34-42b9-888b-35e075cc787e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746505925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1746505925
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1675486750
Short name T256
Test name
Test status
Simulation time 1232916775 ps
CPU time 5.57 seconds
Started Apr 04 12:29:15 PM PDT 24
Finished Apr 04 12:29:20 PM PDT 24
Peak memory 218296 kb
Host smart-3fb018a1-1837-471d-904a-9f616c77823e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675486750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1675486750
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4157172275
Short name T404
Test name
Test status
Simulation time 244329994 ps
CPU time 1.12 seconds
Started Apr 04 12:29:02 PM PDT 24
Finished Apr 04 12:29:04 PM PDT 24
Peak memory 216508 kb
Host smart-4687229a-ea96-4a90-a5cc-23b480e4d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157172275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4157172275
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1628520034
Short name T22
Test name
Test status
Simulation time 109316296 ps
CPU time 0.82 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 200184 kb
Host smart-2d392d19-3fd0-4b8b-b0b0-9d9cb619f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628520034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1628520034
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3028801930
Short name T384
Test name
Test status
Simulation time 1913128208 ps
CPU time 6.59 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:29:02 PM PDT 24
Peak memory 199400 kb
Host smart-7ca78411-983f-4060-9eaf-0a4eea7d5de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028801930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3028801930
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2100084895
Short name T538
Test name
Test status
Simulation time 176816268 ps
CPU time 1.07 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 200352 kb
Host smart-98dac1e6-1e4f-4fb2-8b49-480b8c7d8a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100084895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2100084895
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3088107130
Short name T199
Test name
Test status
Simulation time 112581491 ps
CPU time 1.18 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 199532 kb
Host smart-df1d871f-21da-4076-9cf4-6ca4440724fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088107130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3088107130
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2811435260
Short name T488
Test name
Test status
Simulation time 6837829605 ps
CPU time 27.54 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:29:22 PM PDT 24
Peak memory 208516 kb
Host smart-b9b6472b-fe7a-4c7a-b449-42b707906122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811435260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2811435260
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.945284296
Short name T181
Test name
Test status
Simulation time 143458347 ps
CPU time 1.79 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 200424 kb
Host smart-f2938a03-c00b-4be2-8a09-3016ba47f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945284296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.945284296
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.695537193
Short name T129
Test name
Test status
Simulation time 261580071 ps
CPU time 1.37 seconds
Started Apr 04 12:29:39 PM PDT 24
Finished Apr 04 12:29:40 PM PDT 24
Peak memory 200400 kb
Host smart-18d05398-8e45-4e76-b980-6dc7a69815a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695537193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.695537193
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.295068412
Short name T501
Test name
Test status
Simulation time 93784317 ps
CPU time 0.81 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 200316 kb
Host smart-eacdccbb-52a6-42ac-aed8-d7ea4e1ca3c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295068412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.295068412
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2222162180
Short name T323
Test name
Test status
Simulation time 1225715593 ps
CPU time 5.66 seconds
Started Apr 04 12:28:21 PM PDT 24
Finished Apr 04 12:28:27 PM PDT 24
Peak memory 218268 kb
Host smart-00b0d61a-c83c-4eb5-9815-1d3da8a736db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222162180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2222162180
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3566404996
Short name T166
Test name
Test status
Simulation time 245654362 ps
CPU time 1.08 seconds
Started Apr 04 12:28:08 PM PDT 24
Finished Apr 04 12:28:09 PM PDT 24
Peak memory 217812 kb
Host smart-c20285b7-6468-4cf7-b110-81cf04b4283c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566404996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3566404996
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1907119198
Short name T382
Test name
Test status
Simulation time 145816847 ps
CPU time 0.84 seconds
Started Apr 04 12:29:21 PM PDT 24
Finished Apr 04 12:29:22 PM PDT 24
Peak memory 199452 kb
Host smart-07adc078-2c21-4320-92a9-7f6abcf11f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907119198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1907119198
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1163491073
Short name T368
Test name
Test status
Simulation time 1905537506 ps
CPU time 7.29 seconds
Started Apr 04 12:28:45 PM PDT 24
Finished Apr 04 12:28:53 PM PDT 24
Peak memory 200596 kb
Host smart-1439583f-b246-4bf5-9f25-47a0f5652d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163491073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1163491073
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.355366180
Short name T149
Test name
Test status
Simulation time 149443434 ps
CPU time 1.13 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:23 PM PDT 24
Peak memory 200228 kb
Host smart-eb27f51e-707e-4c89-a38f-13763304c0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355366180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.355366180
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.64941736
Short name T230
Test name
Test status
Simulation time 117821170 ps
CPU time 1.16 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:41 PM PDT 24
Peak memory 200536 kb
Host smart-bd3047bd-9d40-4c34-b8cc-1a79035e0818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64941736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.64941736
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3750629065
Short name T352
Test name
Test status
Simulation time 9779406927 ps
CPU time 35.59 seconds
Started Apr 04 12:29:35 PM PDT 24
Finished Apr 04 12:30:11 PM PDT 24
Peak memory 200704 kb
Host smart-9deca42c-94a5-4bf2-9bb8-cc5184a74139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750629065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3750629065
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2914605719
Short name T180
Test name
Test status
Simulation time 114944755 ps
CPU time 1.5 seconds
Started Apr 04 12:28:13 PM PDT 24
Finished Apr 04 12:28:15 PM PDT 24
Peak memory 200428 kb
Host smart-a7b65bc2-f06e-44db-8322-1a030cfbe461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914605719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2914605719
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1993324146
Short name T417
Test name
Test status
Simulation time 105108834 ps
CPU time 1.03 seconds
Started Apr 04 12:28:36 PM PDT 24
Finished Apr 04 12:28:37 PM PDT 24
Peak memory 200340 kb
Host smart-24382dbc-ddea-4ae9-b50e-3b971566f130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993324146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1993324146
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1029351853
Short name T309
Test name
Test status
Simulation time 58582458 ps
CPU time 0.78 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:29:46 PM PDT 24
Peak memory 200240 kb
Host smart-e588d4bc-0768-4c2b-b83b-0d1409ff5f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029351853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1029351853
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1838089900
Short name T31
Test name
Test status
Simulation time 1239074676 ps
CPU time 5.83 seconds
Started Apr 04 12:28:58 PM PDT 24
Finished Apr 04 12:29:04 PM PDT 24
Peak memory 221832 kb
Host smart-e3e36e2e-a7e0-4f77-86d5-11132baab1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838089900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1838089900
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2048669955
Short name T482
Test name
Test status
Simulation time 244161031 ps
CPU time 1.09 seconds
Started Apr 04 12:28:11 PM PDT 24
Finished Apr 04 12:28:13 PM PDT 24
Peak memory 217884 kb
Host smart-a444f620-464d-4847-a9d9-a9d38045db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048669955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2048669955
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.190324295
Short name T398
Test name
Test status
Simulation time 161908553 ps
CPU time 0.8 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:44 PM PDT 24
Peak memory 200204 kb
Host smart-6d5b4fc6-7b6e-4161-b96a-4dad23fdea9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190324295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.190324295
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.547193507
Short name T536
Test name
Test status
Simulation time 742868965 ps
CPU time 4.06 seconds
Started Apr 04 12:28:15 PM PDT 24
Finished Apr 04 12:28:19 PM PDT 24
Peak memory 200040 kb
Host smart-52ddcc14-d7ec-4ff9-99d1-a795c6e7dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547193507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.547193507
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3719802169
Short name T226
Test name
Test status
Simulation time 178158486 ps
CPU time 1.19 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:47 PM PDT 24
Peak memory 200316 kb
Host smart-d5a34642-f779-4ff8-9b61-992b58e796a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719802169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3719802169
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.322233383
Short name T348
Test name
Test status
Simulation time 252857465 ps
CPU time 1.55 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 200544 kb
Host smart-b2deb353-16dd-4289-a749-2ad0ec9655db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322233383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.322233383
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1678771849
Short name T524
Test name
Test status
Simulation time 7476802201 ps
CPU time 26.4 seconds
Started Apr 04 12:28:13 PM PDT 24
Finished Apr 04 12:28:39 PM PDT 24
Peak memory 208828 kb
Host smart-42cc1226-0fcd-442e-a7b7-0fcba0c6b07f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678771849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1678771849
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2506879491
Short name T173
Test name
Test status
Simulation time 145027240 ps
CPU time 1.88 seconds
Started Apr 04 12:28:15 PM PDT 24
Finished Apr 04 12:28:17 PM PDT 24
Peak memory 200512 kb
Host smart-30ba227e-6771-4db1-9db8-2609cd86db79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506879491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2506879491
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2116103500
Short name T424
Test name
Test status
Simulation time 139447892 ps
CPU time 1.2 seconds
Started Apr 04 12:28:13 PM PDT 24
Finished Apr 04 12:28:14 PM PDT 24
Peak memory 200412 kb
Host smart-a41c0e97-e875-4302-8f9f-9e0af9d57bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116103500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2116103500
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3465937284
Short name T127
Test name
Test status
Simulation time 78826616 ps
CPU time 0.9 seconds
Started Apr 04 12:29:16 PM PDT 24
Finished Apr 04 12:29:17 PM PDT 24
Peak memory 200252 kb
Host smart-6bcd2020-4378-4f92-9a57-e190c1c3bfca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465937284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3465937284
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.592591274
Short name T388
Test name
Test status
Simulation time 1220798099 ps
CPU time 5.69 seconds
Started Apr 04 12:30:13 PM PDT 24
Finished Apr 04 12:30:19 PM PDT 24
Peak memory 221896 kb
Host smart-930955d6-44cc-4fc3-9ae2-4265bd9906db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592591274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.592591274
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1901027097
Short name T152
Test name
Test status
Simulation time 244568724 ps
CPU time 1.09 seconds
Started Apr 04 12:29:33 PM PDT 24
Finished Apr 04 12:29:35 PM PDT 24
Peak memory 217904 kb
Host smart-e9e1ddfb-8848-4d35-a036-ee77f5b848bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901027097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1901027097
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2114258007
Short name T379
Test name
Test status
Simulation time 196443509 ps
CPU time 0.89 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 200244 kb
Host smart-0dc56a05-3d9f-4352-9a26-a7bda8d17f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114258007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2114258007
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3218968756
Short name T381
Test name
Test status
Simulation time 789737316 ps
CPU time 4.29 seconds
Started Apr 04 12:29:33 PM PDT 24
Finished Apr 04 12:29:37 PM PDT 24
Peak memory 200836 kb
Host smart-2938828d-c1ad-4568-8dba-852a286da237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218968756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3218968756
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3550808767
Short name T202
Test name
Test status
Simulation time 95746584 ps
CPU time 1.04 seconds
Started Apr 04 12:29:23 PM PDT 24
Finished Apr 04 12:29:25 PM PDT 24
Peak memory 200504 kb
Host smart-f85dfcac-c7e8-4eb0-95ca-6cca969bb506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550808767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3550808767
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3134609932
Short name T450
Test name
Test status
Simulation time 190481823 ps
CPU time 1.37 seconds
Started Apr 04 12:29:53 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 200628 kb
Host smart-9386f349-c03d-44c5-8153-8fe0f4584392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134609932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3134609932
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2253764952
Short name T243
Test name
Test status
Simulation time 3653978459 ps
CPU time 13.96 seconds
Started Apr 04 12:29:42 PM PDT 24
Finished Apr 04 12:29:56 PM PDT 24
Peak memory 200632 kb
Host smart-0dd89fcf-96c3-4700-acb5-73206a6ba957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253764952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2253764952
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.902262132
Short name T522
Test name
Test status
Simulation time 118819943 ps
CPU time 1.48 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:49 PM PDT 24
Peak memory 200412 kb
Host smart-c451373f-4f7f-401e-bedf-faeaf9a550ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902262132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.902262132
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.296936298
Short name T339
Test name
Test status
Simulation time 124368495 ps
CPU time 1.1 seconds
Started Apr 04 12:29:05 PM PDT 24
Finished Apr 04 12:29:06 PM PDT 24
Peak memory 200344 kb
Host smart-97e6f64e-8f82-494f-a380-953e515e4c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296936298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.296936298
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.504573851
Short name T138
Test name
Test status
Simulation time 61576094 ps
CPU time 0.76 seconds
Started Apr 04 12:29:12 PM PDT 24
Finished Apr 04 12:29:13 PM PDT 24
Peak memory 200228 kb
Host smart-83cdbbb0-0561-45ee-9159-dcc34201a0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504573851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.504573851
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1132597898
Short name T48
Test name
Test status
Simulation time 1900638140 ps
CPU time 7.06 seconds
Started Apr 04 12:29:43 PM PDT 24
Finished Apr 04 12:29:50 PM PDT 24
Peak memory 222340 kb
Host smart-ce3c760e-427e-4b95-b3e7-01942dd0069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132597898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1132597898
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3913443188
Short name T529
Test name
Test status
Simulation time 243745129 ps
CPU time 1.17 seconds
Started Apr 04 12:29:08 PM PDT 24
Finished Apr 04 12:29:09 PM PDT 24
Peak memory 217920 kb
Host smart-ce2fd47a-d17d-4424-a931-3c81a4ddbdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913443188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3913443188
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.76386472
Short name T18
Test name
Test status
Simulation time 225981510 ps
CPU time 1 seconds
Started Apr 04 12:29:20 PM PDT 24
Finished Apr 04 12:29:22 PM PDT 24
Peak memory 200344 kb
Host smart-ee806e79-db35-4120-ac1e-9bef5ad6a4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76386472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.76386472
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.497754586
Short name T495
Test name
Test status
Simulation time 2150880555 ps
CPU time 8.12 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:30 PM PDT 24
Peak memory 200604 kb
Host smart-10509efc-03ec-4d55-8497-259f33da6334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497754586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.497754586
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.88177584
Short name T316
Test name
Test status
Simulation time 109735481 ps
CPU time 1 seconds
Started Apr 04 12:29:15 PM PDT 24
Finished Apr 04 12:29:16 PM PDT 24
Peak memory 200388 kb
Host smart-d151e702-7dea-42a9-9b81-5776f9bef4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88177584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.88177584
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4129354178
Short name T365
Test name
Test status
Simulation time 197452566 ps
CPU time 1.35 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 200540 kb
Host smart-0e7a3ef1-46bb-423f-87bb-6be7d4bcc2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129354178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4129354178
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3018299191
Short name T420
Test name
Test status
Simulation time 332611885 ps
CPU time 2.23 seconds
Started Apr 04 12:29:40 PM PDT 24
Finished Apr 04 12:29:43 PM PDT 24
Peak memory 208728 kb
Host smart-a136fe00-4bf3-48ef-8449-40ff8f794675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018299191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3018299191
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1133254941
Short name T148
Test name
Test status
Simulation time 131069023 ps
CPU time 1.1 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:30:57 PM PDT 24
Peak memory 200408 kb
Host smart-f9b0fb9d-500c-4b5d-b267-318d09b022c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133254941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1133254941
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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