Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8032

1

T2

31

T3

19

T4

12

auto[1]

10857

1

T1

4

T2

29

T3

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5810	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6424	1			T1	2		T2	24		T3	1
reset_info_cp[2]	2907	1			T1	1		T2	11		T6	6
reset_info_cp[4]	3815	1			T1	1		T2	9		T6	8
reset_info_cp[8]	114	1			T4	1		T6	1		T10	1
reset_info_cp[16]	107	1			T10	1		T55	1		T96	1
reset_info_cp[32]	118	1			T2	1		T3	3		T7	1
reset_info_cp[64]	94	1			T1	1		T2	1		T3	2
reset_info_cp[128]	120	1			T3	1		T4	2		T6	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3072	1			T2	13		T6	10		T8	11
reset_info_cp[1]	auto[1]	2732	1			T1	1		T2	10		T6	12
reset_info_cp[2]	auto[0]	894	1			T2	1		T6	1		T8	4
reset_info_cp[2]	auto[1]	2013	1			T1	1		T2	10		T6	5
reset_info_cp[4]	auto[0]	1387	1			T2	6		T6	5		T8	5
reset_info_cp[4]	auto[1]	2428	1			T1	1		T2	3		T6	3
reset_info_cp[8]	auto[0]	55	1			T4	1		T6	1		T10	1
reset_info_cp[8]	auto[1]	59	1			T41	1		T50	1		T54	1
reset_info_cp[16]	auto[0]	46	1			T10	1		T96	1		T97	2
reset_info_cp[16]	auto[1]	61	1			T55	1		T50	2		T35	1
reset_info_cp[32]	auto[0]	46	1			T2	1		T3	3		T10	1
reset_info_cp[32]	auto[1]	72	1			T7	1		T58	1		T97	1
reset_info_cp[64]	auto[0]	35	1			T3	2		T4	1		T57	1
reset_info_cp[64]	auto[1]	59	1			T1	1		T2	1		T96	1
reset_info_cp[128]	auto[0]	52	1			T3	1		T4	2		T6	1
reset_info_cp[128]	auto[1]	68	1			T22	1		T55	1		T103	1