Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspace/coverage/default/36.rstmgr_por_stretcher.77774191 Apr 15 12:38:37 PM PDT 24 Apr 15 12:38:40 PM PDT 24 194412619 ps
T541 /workspace/coverage/default/46.rstmgr_stress_all.3682846942 Apr 15 12:38:58 PM PDT 24 Apr 15 12:39:16 PM PDT 24 4232646662 ps
T542 /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3490786220 Apr 15 12:38:49 PM PDT 24 Apr 15 12:38:55 PM PDT 24 1225577148 ps
T543 /workspace/coverage/default/3.rstmgr_por_stretcher.3312478252 Apr 15 12:37:47 PM PDT 24 Apr 15 12:37:49 PM PDT 24 154822376 ps
T544 /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2221095454 Apr 15 12:37:45 PM PDT 24 Apr 15 12:37:52 PM PDT 24 1234797864 ps
T77 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3756684645 Apr 15 12:22:40 PM PDT 24 Apr 15 12:22:43 PM PDT 24 170531819 ps
T73 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2790719725 Apr 15 12:22:42 PM PDT 24 Apr 15 12:22:44 PM PDT 24 77482793 ps
T74 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1111143155 Apr 15 12:22:45 PM PDT 24 Apr 15 12:22:47 PM PDT 24 206041345 ps
T75 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4224757852 Apr 15 12:22:49 PM PDT 24 Apr 15 12:22:50 PM PDT 24 113456853 ps
T76 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1993899292 Apr 15 12:22:45 PM PDT 24 Apr 15 12:22:47 PM PDT 24 108619812 ps
T107 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2137197633 Apr 15 12:22:59 PM PDT 24 Apr 15 12:23:01 PM PDT 24 136907166 ps
T78 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2755541080 Apr 15 12:22:46 PM PDT 24 Apr 15 12:22:48 PM PDT 24 108032093 ps
T545 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.414988579 Apr 15 12:23:27 PM PDT 24 Apr 15 12:23:28 PM PDT 24 73855312 ps
T108 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3148841603 Apr 15 12:22:56 PM PDT 24 Apr 15 12:22:58 PM PDT 24 97081010 ps
T140 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2845053696 Apr 15 12:22:45 PM PDT 24 Apr 15 12:22:47 PM PDT 24 70535816 ps
T109 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3757957335 Apr 15 12:22:35 PM PDT 24 Apr 15 12:22:36 PM PDT 24 62246551 ps
T110 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3005637844 Apr 15 12:22:45 PM PDT 24 Apr 15 12:22:47 PM PDT 24 56578345 ps
T88 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2637384832 Apr 15 12:22:47 PM PDT 24 Apr 15 12:22:49 PM PDT 24 151206983 ps
T111 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.264601388 Apr 15 12:22:45 PM PDT 24 Apr 15 12:22:47 PM PDT 24 102940532 ps
T112 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4187145615 Apr 15 12:23:58 PM PDT 24 Apr 15 12:24:00 PM PDT 24 132943891 ps
T113 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2449607281 Apr 15 12:23:46 PM PDT 24 Apr 15 12:23:53 PM PDT 24 149697295 ps
T99 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2753800981 Apr 15 12:22:42 PM PDT 24 Apr 15 12:22:44 PM PDT 24 174040080 ps
T139 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1018115838 Apr 15 12:22:42 PM PDT 24 Apr 15 12:22:51 PM PDT 24 1553744368 ps
T114 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.600220236 Apr 15 12:23:38 PM PDT 24 Apr 15 12:23:42 PM PDT 24 242540954 ps
T100 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1417777419 Apr 15 12:22:42 PM PDT 24 Apr 15 12:22:44 PM PDT 24 181029988 ps
T79 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4002820 Apr 15 12:22:45 PM PDT 24 Apr 15 12:22:49 PM PDT 24 211736488 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2204991299 Apr 15 12:22:40 PM PDT 24 Apr 15 12:22:42 PM PDT 24 82857548 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2543682117 Apr 15 12:23:52 PM PDT 24 Apr 15 12:23:53 PM PDT 24 136867972 ps
T115 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3183514791 Apr 15 12:22:50 PM PDT 24 Apr 15 12:22:54 PM PDT 24 797784752 ps
T548 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3468328971 Apr 15 12:22:44 PM PDT 24 Apr 15 12:22:46 PM PDT 24 79539006 ps
T549 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3025667056 Apr 15 12:22:47 PM PDT 24 Apr 15 12:22:48 PM PDT 24 81024328 ps
T101 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1382617288 Apr 15 12:22:43 PM PDT 24 Apr 15 12:22:45 PM PDT 24 208574963 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3364607510 Apr 15 12:22:46 PM PDT 24 Apr 15 12:22:48 PM PDT 24 143702002 ps
T81 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3725358765 Apr 15 12:22:48 PM PDT 24 Apr 15 12:22:50 PM PDT 24 225415625 ps
T551 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1965971400 Apr 15 12:22:41 PM PDT 24 Apr 15 12:22:42 PM PDT 24 108865501 ps
T552 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.466570780 Apr 15 12:22:39 PM PDT 24 Apr 15 12:22:46 PM PDT 24 86825571 ps
T102 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.312054970 Apr 15 12:22:35 PM PDT 24 Apr 15 12:22:37 PM PDT 24 306075646 ps
T553 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.443017590 Apr 15 12:22:47 PM PDT 24 Apr 15 12:22:56 PM PDT 24 2003635329 ps
T554 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4278297157 Apr 15 12:22:46 PM PDT 24 Apr 15 12:22:48 PM PDT 24 110320017 ps
T124 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3583092554 Apr 15 12:22:44 PM PDT 24 Apr 15 12:22:48 PM PDT 24 566739859 ps
T555 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3994095135 Apr 15 12:23:40 PM PDT 24 Apr 15 12:23:43 PM PDT 24 209365386 ps
T556 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.808907822 Apr 15 12:23:22 PM PDT 24 Apr 15 12:23:24 PM PDT 24 113949053 ps
T116 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2632678154 Apr 15 12:22:48 PM PDT 24 Apr 15 12:22:51 PM PDT 24 877707256 ps
T557 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2673001692 Apr 15 12:22:38 PM PDT 24 Apr 15 12:22:47 PM PDT 24 2000053334 ps
T558 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4250844818 Apr 15 12:22:25 PM PDT 24 Apr 15 12:22:26 PM PDT 24 112403033 ps
T117 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3663087297 Apr 15 12:22:40 PM PDT 24 Apr 15 12:22:43 PM PDT 24 796795583 ps
T559 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2503550690 Apr 15 12:22:36 PM PDT 24 Apr 15 12:22:37 PM PDT 24 101867628 ps
T125 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2313246375 Apr 15 12:22:43 PM PDT 24 Apr 15 12:22:46 PM PDT 24 323706409 ps
T560 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3198825533 Apr 15 12:22:44 PM PDT 24 Apr 15 12:22:46 PM PDT 24 147362796 ps
T561 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.38574228 Apr 15 12:22:42 PM PDT 24 Apr 15 12:22:44 PM PDT 24 63374631 ps
T562 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1029108084 Apr 15 12:23:05 PM PDT 24 Apr 15 12:23:06 PM PDT 24 78360787 ps
T563 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.69316732 Apr 15 12:22:42 PM PDT 24 Apr 15 12:22:44 PM PDT 24 220279189 ps
T564 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1701383839 Apr 15 12:22:38 PM PDT 24 Apr 15 12:22:40 PM PDT 24 183292193 ps
T565 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.716852983 Apr 15 12:22:44 PM PDT 24 Apr 15 12:22:46 PM PDT 24 118648612 ps
T135 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3054266367 Apr 15 12:22:55 PM PDT 24 Apr 15 12:22:59 PM PDT 24 879580370 ps
T566 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.980254803 Apr 15 12:22:46 PM PDT 24 Apr 15 12:22:51 PM PDT 24 537859552 ps
T567 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2886840493 Apr 15 12:22:40 PM PDT 24 Apr 15 12:22:44 PM PDT 24 1110131316 ps
T568 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.184081459 Apr 15 12:22:40 PM PDT 24 Apr 15 12:22:42 PM PDT 24 171952151 ps
T569 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1813294300 Apr 15 12:22:48 PM PDT 24 Apr 15 12:22:51 PM PDT 24 360861103 ps
T570 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1494819696 Apr 15 12:22:44 PM PDT 24 Apr 15 12:22:46 PM PDT 24 74784186 ps
T571 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3163913145 Apr 15 12:22:50 PM PDT 24 Apr 15 12:22:53 PM PDT 24 195865139 ps
T572 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1490165493 Apr 15 12:22:45 PM PDT 24 Apr 15 12:22:47 PM PDT 24 69107526 ps
T136 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2537057990 Apr 15 12:22:39 PM PDT 24 Apr 15 12:22:42 PM PDT 24 794293620 ps
T137 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2682645682 Apr 15 12:22:38 PM PDT 24 Apr 15 12:22:40 PM PDT 24 447869484 ps
T573 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3755485429 Apr 15 12:23:17 PM PDT 24 Apr 15 12:23:21 PM PDT 24 265817615 ps
T574 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2952910644 Apr 15 12:22:38 PM PDT 24 Apr 15 12:22:40 PM PDT 24 118744254 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3779881911 Apr 15 12:22:44 PM PDT 24 Apr 15 12:22:54 PM PDT 24 1563627942 ps
T576 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1756564864 Apr 15 12:22:56 PM PDT 24 Apr 15 12:22:58 PM PDT 24 175869953 ps
T577 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1510176439 Apr 15 12:22:39 PM PDT 24 Apr 15 12:22:47 PM PDT 24 503419561 ps
T578 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2464065593 Apr 15 12:22:41 PM PDT 24 Apr 15 12:22:42 PM PDT 24 69413860 ps
T579 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4216589916 Apr 15 12:22:57 PM PDT 24 Apr 15 12:23:00 PM PDT 24 417623497 ps
T580 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3746774207 Apr 15 12:22:43 PM PDT 24 Apr 15 12:22:45 PM PDT 24 150856218 ps
T138 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1454847411 Apr 15 12:23:06 PM PDT 24 Apr 15 12:23:09 PM PDT 24 466121698 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1956261466 Apr 15 12:23:21 PM PDT 24 Apr 15 12:23:25 PM PDT 24 201452316 ps
T104 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1150134253 Apr 15 12:22:47 PM PDT 24 Apr 15 12:22:48 PM PDT 24 73739772 ps
T582 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3332345788 Apr 15 12:22:38 PM PDT 24 Apr 15 12:22:41 PM PDT 24 247291242 ps
T583 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1571825739 Apr 15 12:22:41 PM PDT 24 Apr 15 12:22:43 PM PDT 24 188360822 ps
T584 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3010748526 Apr 15 12:22:44 PM PDT 24 Apr 15 12:22:45 PM PDT 24 63563322 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1211113264 Apr 15 12:22:40 PM PDT 24 Apr 15 12:22:41 PM PDT 24 84955470 ps
T120 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3207855669 Apr 15 12:22:39 PM PDT 24 Apr 15 12:22:42 PM PDT 24 892706705 ps
T586 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1601366691 Apr 15 12:22:43 PM PDT 24 Apr 15 12:22:46 PM PDT 24 492864362 ps
T587 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2493571775 Apr 15 12:22:48 PM PDT 24 Apr 15 12:22:50 PM PDT 24 178166213 ps
T588 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2432824154 Apr 15 12:23:34 PM PDT 24 Apr 15 12:23:37 PM PDT 24 69697486 ps
T589 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3098891037 Apr 15 12:22:49 PM PDT 24 Apr 15 12:22:52 PM PDT 24 355024667 ps
T590 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1563960283 Apr 15 12:22:48 PM PDT 24 Apr 15 12:22:51 PM PDT 24 417690911 ps
T591 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.826198713 Apr 15 12:23:45 PM PDT 24 Apr 15 12:23:47 PM PDT 24 93354954 ps
T592 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2531406200 Apr 15 12:22:36 PM PDT 24 Apr 15 12:22:40 PM PDT 24 537032032 ps
T593 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.747695659 Apr 15 12:22:47 PM PDT 24 Apr 15 12:22:49 PM PDT 24 143818396 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3834845439 Apr 15 12:22:44 PM PDT 24 Apr 15 12:22:46 PM PDT 24 156067744 ps
T595 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.179250531 Apr 15 12:22:43 PM PDT 24 Apr 15 12:22:44 PM PDT 24 113952326 ps
T596 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2420846447 Apr 15 12:22:40 PM PDT 24 Apr 15 12:22:41 PM PDT 24 64536667 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1941994706 Apr 15 12:22:55 PM PDT 24 Apr 15 12:22:56 PM PDT 24 150534096 ps
T598 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3240785185 Apr 15 12:23:34 PM PDT 24 Apr 15 12:23:37 PM PDT 24 121782542 ps
T599 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4188435967 Apr 15 12:23:14 PM PDT 24 Apr 15 12:23:17 PM PDT 24 502285409 ps
T600 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3418987539 Apr 15 12:22:45 PM PDT 24 Apr 15 12:22:47 PM PDT 24 85326693 ps
T601 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2698087795 Apr 15 12:22:39 PM PDT 24 Apr 15 12:22:41 PM PDT 24 132333405 ps
T602 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.161156100 Apr 15 12:22:48 PM PDT 24 Apr 15 12:22:52 PM PDT 24 1047419859 ps
T603 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2009198560 Apr 15 12:22:42 PM PDT 24 Apr 15 12:22:44 PM PDT 24 60824230 ps
T121 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3322847689 Apr 15 12:22:41 PM PDT 24 Apr 15 12:22:43 PM PDT 24 426289359 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1279920915 Apr 15 12:22:47 PM PDT 24 Apr 15 12:22:48 PM PDT 24 108780521 ps
T122 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4010972149 Apr 15 12:22:47 PM PDT 24 Apr 15 12:22:51 PM PDT 24 871199022 ps
T605 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3791444689 Apr 15 12:22:59 PM PDT 24 Apr 15 12:23:01 PM PDT 24 199984000 ps
T606 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2766751148 Apr 15 12:22:41 PM PDT 24 Apr 15 12:22:43 PM PDT 24 105363080 ps
T607 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3885291583 Apr 15 12:22:38 PM PDT 24 Apr 15 12:22:42 PM PDT 24 472691642 ps
T118 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1513998570 Apr 15 12:22:29 PM PDT 24 Apr 15 12:22:32 PM PDT 24 781118641 ps
T608 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.220088717 Apr 15 12:23:27 PM PDT 24 Apr 15 12:23:29 PM PDT 24 68081759 ps
T609 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1196697870 Apr 15 12:22:40 PM PDT 24 Apr 15 12:22:42 PM PDT 24 119064903 ps
T610 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3880082518 Apr 15 12:22:50 PM PDT 24 Apr 15 12:22:53 PM PDT 24 161235500 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3099616626 Apr 15 12:22:41 PM PDT 24 Apr 15 12:22:42 PM PDT 24 97326941 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3608066660 Apr 15 12:22:43 PM PDT 24 Apr 15 12:22:47 PM PDT 24 445581142 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3610679183 Apr 15 12:23:33 PM PDT 24 Apr 15 12:23:37 PM PDT 24 196362124 ps
T119 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.176083392 Apr 15 12:22:49 PM PDT 24 Apr 15 12:22:51 PM PDT 24 399983719 ps
T614 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.853493509 Apr 15 12:22:49 PM PDT 24 Apr 15 12:22:50 PM PDT 24 149067269 ps
T615 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3539195539 Apr 15 12:23:21 PM PDT 24 Apr 15 12:23:22 PM PDT 24 68035676 ps
T616 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2234755874 Apr 15 12:22:57 PM PDT 24 Apr 15 12:22:58 PM PDT 24 119862150 ps
T123 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3904857103 Apr 15 12:22:35 PM PDT 24 Apr 15 12:22:37 PM PDT 24 507246226 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3240903187 Apr 15 12:22:41 PM PDT 24 Apr 15 12:22:42 PM PDT 24 59114762 ps
T618 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1427627779 Apr 15 12:22:43 PM PDT 24 Apr 15 12:22:45 PM PDT 24 88824055 ps
T619 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3398187292 Apr 15 12:22:59 PM PDT 24 Apr 15 12:23:07 PM PDT 24 904278578 ps
T620 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.298126146 Apr 15 12:22:49 PM PDT 24 Apr 15 12:22:51 PM PDT 24 195705449 ps

Test location /workspace/coverage/default/7.rstmgr_stress_all.13447133
Short name T2
Test name
Test status
Simulation time 2468137905 ps
CPU time 8.67 seconds
Started Apr 15 12:37:48 PM PDT 24
Finished Apr 15 12:37:58 PM PDT 24
Peak memory 201040 kb
Host smart-6ff559fa-326d-44e5-a5a9-d0772f79ebbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13447133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.13447133
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1779704143
Short name T72
Test name
Test status
Simulation time 327444284 ps
CPU time 1.97 seconds
Started Apr 15 12:37:58 PM PDT 24
Finished Apr 15 12:38:01 PM PDT 24
Peak memory 200740 kb
Host smart-2834f9d4-0869-4ea5-b2a7-38cf3d3ada2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779704143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1779704143
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1111143155
Short name T74
Test name
Test status
Simulation time 206041345 ps
CPU time 1.27 seconds
Started Apr 15 12:22:45 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 200852 kb
Host smart-01e324aa-16f2-4006-8299-e830454d8d68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111143155 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1111143155
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1643807577
Short name T48
Test name
Test status
Simulation time 8300807998 ps
CPU time 15.34 seconds
Started Apr 15 12:37:44 PM PDT 24
Finished Apr 15 12:38:00 PM PDT 24
Peak memory 217824 kb
Host smart-ef696bdb-ce3a-43a1-95fb-39c19ab51b8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643807577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1643807577
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.750597485
Short name T55
Test name
Test status
Simulation time 1222074369 ps
CPU time 5.31 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 217812 kb
Host smart-965ce0d0-814f-463c-a1ce-c07b3fd7d8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750597485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.750597485
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3183514791
Short name T115
Test name
Test status
Simulation time 797784752 ps
CPU time 3.24 seconds
Started Apr 15 12:22:50 PM PDT 24
Finished Apr 15 12:22:54 PM PDT 24
Peak memory 201012 kb
Host smart-a4dc81af-9303-42bb-9605-a928a71d55a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183514791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3183514791
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1765182629
Short name T105
Test name
Test status
Simulation time 6726331494 ps
CPU time 28.06 seconds
Started Apr 15 12:37:40 PM PDT 24
Finished Apr 15 12:38:09 PM PDT 24
Peak memory 201132 kb
Host smart-83e6e84a-cbaa-43f4-b3a5-a0b9bdc06f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765182629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1765182629
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2584104458
Short name T41
Test name
Test status
Simulation time 1229579932 ps
CPU time 5.63 seconds
Started Apr 15 12:37:49 PM PDT 24
Finished Apr 15 12:37:56 PM PDT 24
Peak memory 218156 kb
Host smart-6949b31c-c841-46cf-97e3-b8ab231384d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584104458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2584104458
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1691994376
Short name T61
Test name
Test status
Simulation time 66570526 ps
CPU time 0.77 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 200628 kb
Host smart-a2324b06-d8fd-4569-9d8c-37af00105028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691994376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1691994376
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4002820
Short name T79
Test name
Test status
Simulation time 211736488 ps
CPU time 3.06 seconds
Started Apr 15 12:22:45 PM PDT 24
Finished Apr 15 12:22:49 PM PDT 24
Peak memory 209092 kb
Host smart-0da03c4b-8b29-456f-95ca-cacf49ad96d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4002820
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3925152391
Short name T7
Test name
Test status
Simulation time 148074279 ps
CPU time 1.15 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 200680 kb
Host smart-04210242-644c-4619-bd89-88255d6994c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925152391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3925152391
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1513998570
Short name T118
Test name
Test status
Simulation time 781118641 ps
CPU time 2.77 seconds
Started Apr 15 12:22:29 PM PDT 24
Finished Apr 15 12:22:32 PM PDT 24
Peak memory 201032 kb
Host smart-e2a33947-60b0-437c-b9f9-2d07a2b867f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513998570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1513998570
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1599811855
Short name T5
Test name
Test status
Simulation time 202534380 ps
CPU time 0.89 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 200468 kb
Host smart-822bf634-54ba-4c2f-86a2-ba3adb446244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599811855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1599811855
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3530485178
Short name T25
Test name
Test status
Simulation time 2356762810 ps
CPU time 7.91 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 218716 kb
Host smart-84dcea0f-4163-4fe0-87a4-4ad9c48db948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530485178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3530485178
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.69316732
Short name T563
Test name
Test status
Simulation time 220279189 ps
CPU time 1.66 seconds
Started Apr 15 12:22:42 PM PDT 24
Finished Apr 15 12:22:44 PM PDT 24
Peak memory 209148 kb
Host smart-534b991d-c83f-4a12-ba8a-f04315239be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69316732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.69316732
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.4154661537
Short name T4
Test name
Test status
Simulation time 132495671 ps
CPU time 1.08 seconds
Started Apr 15 12:37:58 PM PDT 24
Finished Apr 15 12:37:59 PM PDT 24
Peak memory 200820 kb
Host smart-248442ae-6dac-4f44-9c36-4426321e27ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154661537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.4154661537
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3207855669
Short name T120
Test name
Test status
Simulation time 892706705 ps
CPU time 2.97 seconds
Started Apr 15 12:22:39 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 200992 kb
Host smart-5da8af74-0334-481d-8433-a2dab6029404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207855669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3207855669
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3757957335
Short name T109
Test name
Test status
Simulation time 62246551 ps
CPU time 0.85 seconds
Started Apr 15 12:22:35 PM PDT 24
Finished Apr 15 12:22:36 PM PDT 24
Peak memory 200744 kb
Host smart-9c9436ad-f160-45a1-83da-b572300d0a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757957335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3757957335
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.417373168
Short name T146
Test name
Test status
Simulation time 244364638 ps
CPU time 1.03 seconds
Started Apr 15 12:38:16 PM PDT 24
Finished Apr 15 12:38:18 PM PDT 24
Peak memory 218144 kb
Host smart-c0e5ab47-cf5a-40dd-a8e9-ed7591365d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417373168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.417373168
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.650993371
Short name T173
Test name
Test status
Simulation time 121492984 ps
CPU time 1.52 seconds
Started Apr 15 12:37:57 PM PDT 24
Finished Apr 15 12:37:59 PM PDT 24
Peak memory 200760 kb
Host smart-b490948f-fc98-4340-87d9-fae217918a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650993371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.650993371
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4250844818
Short name T558
Test name
Test status
Simulation time 112403033 ps
CPU time 1.32 seconds
Started Apr 15 12:22:25 PM PDT 24
Finished Apr 15 12:22:26 PM PDT 24
Peak memory 200908 kb
Host smart-e0c55db3-5f19-41db-af72-bbee2efee1c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250844818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
250844818
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3779881911
Short name T575
Test name
Test status
Simulation time 1563627942 ps
CPU time 8.89 seconds
Started Apr 15 12:22:44 PM PDT 24
Finished Apr 15 12:22:54 PM PDT 24
Peak memory 200744 kb
Host smart-6ef035b1-76b3-48b8-9afa-c9ae5d65dbf9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779881911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
779881911
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3099616626
Short name T611
Test name
Test status
Simulation time 97326941 ps
CPU time 0.8 seconds
Started Apr 15 12:22:41 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 200772 kb
Host smart-a2ff4a98-efba-413c-98c7-9f5f7f8ffc46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099616626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
099616626
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1279920915
Short name T604
Test name
Test status
Simulation time 108780521 ps
CPU time 1.04 seconds
Started Apr 15 12:22:47 PM PDT 24
Finished Apr 15 12:22:48 PM PDT 24
Peak memory 211544 kb
Host smart-0103e57f-81bc-4556-ab5a-23c2180f9c83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279920915 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1279920915
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2766751148
Short name T606
Test name
Test status
Simulation time 105363080 ps
CPU time 1.17 seconds
Started Apr 15 12:22:41 PM PDT 24
Finished Apr 15 12:22:43 PM PDT 24
Peak memory 200960 kb
Host smart-7a8e6cda-ddf5-40f7-933d-20e5e4eed2ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766751148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2766751148
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.312054970
Short name T102
Test name
Test status
Simulation time 306075646 ps
CPU time 2.07 seconds
Started Apr 15 12:22:35 PM PDT 24
Finished Apr 15 12:22:37 PM PDT 24
Peak memory 211924 kb
Host smart-9ca904aa-7ff0-438f-8b73-aa419dd443ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312054970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.312054970
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3332345788
Short name T582
Test name
Test status
Simulation time 247291242 ps
CPU time 1.72 seconds
Started Apr 15 12:22:38 PM PDT 24
Finished Apr 15 12:22:41 PM PDT 24
Peak memory 209084 kb
Host smart-b5fc9bd6-ab73-482a-8710-e967f71c66f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332345788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
332345788
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2673001692
Short name T557
Test name
Test status
Simulation time 2000053334 ps
CPU time 9.1 seconds
Started Apr 15 12:22:38 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 217200 kb
Host smart-79cc90ed-e510-4df8-a89d-0dbc6f1b995d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673001692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
673001692
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1211113264
Short name T585
Test name
Test status
Simulation time 84955470 ps
CPU time 0.78 seconds
Started Apr 15 12:22:40 PM PDT 24
Finished Apr 15 12:22:41 PM PDT 24
Peak memory 200528 kb
Host smart-e4d3a9ca-71c1-45a5-a30c-378d678b4b08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211113264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
211113264
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1571825739
Short name T583
Test name
Test status
Simulation time 188360822 ps
CPU time 1.13 seconds
Started Apr 15 12:22:41 PM PDT 24
Finished Apr 15 12:22:43 PM PDT 24
Peak memory 200816 kb
Host smart-7c4281c8-5cb0-4a08-8473-bc978ab66b94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571825739 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1571825739
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2204991299
Short name T546
Test name
Test status
Simulation time 82857548 ps
CPU time 0.81 seconds
Started Apr 15 12:22:40 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 200756 kb
Host smart-1d260228-e40b-4bda-88e6-d72f46d10036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204991299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2204991299
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3834845439
Short name T594
Test name
Test status
Simulation time 156067744 ps
CPU time 1.19 seconds
Started Apr 15 12:22:44 PM PDT 24
Finished Apr 15 12:22:46 PM PDT 24
Peak memory 200752 kb
Host smart-f99bf535-3d87-49e7-b3ee-63cc38c4a267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834845439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3834845439
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2531406200
Short name T592
Test name
Test status
Simulation time 537032032 ps
CPU time 3.78 seconds
Started Apr 15 12:22:36 PM PDT 24
Finished Apr 15 12:22:40 PM PDT 24
Peak memory 212112 kb
Host smart-f1b73ba5-d150-45a4-812d-3861134a8c96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531406200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2531406200
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3322847689
Short name T121
Test name
Test status
Simulation time 426289359 ps
CPU time 1.86 seconds
Started Apr 15 12:22:41 PM PDT 24
Finished Apr 15 12:22:43 PM PDT 24
Peak memory 200964 kb
Host smart-78e15f78-9376-4aba-b9a5-c21afb8e4256
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322847689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3322847689
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3994095135
Short name T555
Test name
Test status
Simulation time 209365386 ps
CPU time 1.48 seconds
Started Apr 15 12:23:40 PM PDT 24
Finished Apr 15 12:23:43 PM PDT 24
Peak memory 209152 kb
Host smart-1b04d134-9ab8-4ebf-9a15-ce02a1d71ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994095135 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3994095135
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2420846447
Short name T596
Test name
Test status
Simulation time 64536667 ps
CPU time 0.78 seconds
Started Apr 15 12:22:40 PM PDT 24
Finished Apr 15 12:22:41 PM PDT 24
Peak memory 200740 kb
Host smart-44523f47-5f4d-4735-8e2b-03f49e26611e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420846447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2420846447
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2449607281
Short name T113
Test name
Test status
Simulation time 149697295 ps
CPU time 1.15 seconds
Started Apr 15 12:23:46 PM PDT 24
Finished Apr 15 12:23:53 PM PDT 24
Peak memory 200808 kb
Host smart-b5f99806-6110-48df-b37c-d0d63a164e74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449607281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2449607281
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3583092554
Short name T124
Test name
Test status
Simulation time 566739859 ps
CPU time 3.48 seconds
Started Apr 15 12:22:44 PM PDT 24
Finished Apr 15 12:22:48 PM PDT 24
Peak memory 217228 kb
Host smart-118947e3-cf7a-4bbc-815f-3d6294c78663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583092554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3583092554
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2537057990
Short name T136
Test name
Test status
Simulation time 794293620 ps
CPU time 2.81 seconds
Started Apr 15 12:22:39 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 200992 kb
Host smart-29e07361-4b1e-45f1-b866-b33c9738cdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537057990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2537057990
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.747695659
Short name T593
Test name
Test status
Simulation time 143818396 ps
CPU time 1.2 seconds
Started Apr 15 12:22:47 PM PDT 24
Finished Apr 15 12:22:49 PM PDT 24
Peak memory 209028 kb
Host smart-fb5257bf-7777-4406-85b3-85fdb9e711d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747695659 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.747695659
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.220088717
Short name T608
Test name
Test status
Simulation time 68081759 ps
CPU time 0.78 seconds
Started Apr 15 12:23:27 PM PDT 24
Finished Apr 15 12:23:29 PM PDT 24
Peak memory 200700 kb
Host smart-8a712399-4677-4bbd-9cfc-82f721d18f1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220088717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.220088717
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1993899292
Short name T76
Test name
Test status
Simulation time 108619812 ps
CPU time 1.21 seconds
Started Apr 15 12:22:45 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 201000 kb
Host smart-8278b31c-bb49-4663-994a-68645c0e6ffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993899292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1993899292
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3240785185
Short name T598
Test name
Test status
Simulation time 121782542 ps
CPU time 1.65 seconds
Started Apr 15 12:23:34 PM PDT 24
Finished Apr 15 12:23:37 PM PDT 24
Peak memory 209160 kb
Host smart-9a910ea1-9c6e-4b9b-a7e6-02d7c16e92f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240785185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3240785185
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2632678154
Short name T116
Test name
Test status
Simulation time 877707256 ps
CPU time 3.07 seconds
Started Apr 15 12:22:48 PM PDT 24
Finished Apr 15 12:22:51 PM PDT 24
Peak memory 201012 kb
Host smart-b566370b-ba89-42ae-8980-2694b0bf4d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632678154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2632678154
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1701383839
Short name T564
Test name
Test status
Simulation time 183292193 ps
CPU time 1.15 seconds
Started Apr 15 12:22:38 PM PDT 24
Finished Apr 15 12:22:40 PM PDT 24
Peak memory 200868 kb
Host smart-2cdc5742-2225-40f6-b2f4-1fcc8bac1ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701383839 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1701383839
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1494819696
Short name T570
Test name
Test status
Simulation time 74784186 ps
CPU time 0.78 seconds
Started Apr 15 12:22:44 PM PDT 24
Finished Apr 15 12:22:46 PM PDT 24
Peak memory 200752 kb
Host smart-ca6cc1ef-a15b-40ae-a55e-3466b984b5fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494819696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1494819696
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.826198713
Short name T591
Test name
Test status
Simulation time 93354954 ps
CPU time 1.15 seconds
Started Apr 15 12:23:45 PM PDT 24
Finished Apr 15 12:23:47 PM PDT 24
Peak memory 201004 kb
Host smart-fbf78526-cb46-4666-a6b2-53be0d2e3746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826198713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.826198713
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1454847411
Short name T138
Test name
Test status
Simulation time 466121698 ps
CPU time 1.86 seconds
Started Apr 15 12:23:06 PM PDT 24
Finished Apr 15 12:23:09 PM PDT 24
Peak memory 201044 kb
Host smart-27abad21-d3c3-4a0d-8899-382523399c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454847411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1454847411
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1196697870
Short name T609
Test name
Test status
Simulation time 119064903 ps
CPU time 1.21 seconds
Started Apr 15 12:22:40 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 211536 kb
Host smart-affb450f-efc5-4d7c-8512-da8839f1cf0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196697870 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1196697870
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2790719725
Short name T73
Test name
Test status
Simulation time 77482793 ps
CPU time 0.96 seconds
Started Apr 15 12:22:42 PM PDT 24
Finished Apr 15 12:22:44 PM PDT 24
Peak memory 201060 kb
Host smart-aacd687b-7503-467e-8b48-a3ec066aa3d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790719725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2790719725
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.264601388
Short name T111
Test name
Test status
Simulation time 102940532 ps
CPU time 1.25 seconds
Started Apr 15 12:22:45 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 200960 kb
Host smart-5bee0618-4511-4695-afc4-cf58c08b296c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264601388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.264601388
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3791444689
Short name T605
Test name
Test status
Simulation time 199984000 ps
CPU time 1.47 seconds
Started Apr 15 12:22:59 PM PDT 24
Finished Apr 15 12:23:01 PM PDT 24
Peak memory 209020 kb
Host smart-be60f2a9-292b-47d8-b0c1-19ed66ee8c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791444689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3791444689
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4216589916
Short name T579
Test name
Test status
Simulation time 417623497 ps
CPU time 1.78 seconds
Started Apr 15 12:22:57 PM PDT 24
Finished Apr 15 12:23:00 PM PDT 24
Peak memory 201044 kb
Host smart-1bba8cf1-9832-4bbd-a763-dcf1464d00b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216589916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.4216589916
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3198825533
Short name T560
Test name
Test status
Simulation time 147362796 ps
CPU time 1.18 seconds
Started Apr 15 12:22:44 PM PDT 24
Finished Apr 15 12:22:46 PM PDT 24
Peak memory 209024 kb
Host smart-4425ea5a-453b-4248-b6f5-c4c4ccf978ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198825533 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3198825533
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3005637844
Short name T110
Test name
Test status
Simulation time 56578345 ps
CPU time 0.69 seconds
Started Apr 15 12:22:45 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 200772 kb
Host smart-7900b7a4-26ff-4f74-a99c-9eeadb5a3f0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005637844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3005637844
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3468328971
Short name T548
Test name
Test status
Simulation time 79539006 ps
CPU time 0.93 seconds
Started Apr 15 12:22:44 PM PDT 24
Finished Apr 15 12:22:46 PM PDT 24
Peak memory 200796 kb
Host smart-ea91bb47-a7da-4aec-b09e-9ad150b843c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468328971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3468328971
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2755541080
Short name T78
Test name
Test status
Simulation time 108032093 ps
CPU time 1.51 seconds
Started Apr 15 12:22:46 PM PDT 24
Finished Apr 15 12:22:48 PM PDT 24
Peak memory 209140 kb
Host smart-1a8cbbc0-c890-4e1d-b6de-370eafd466f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755541080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2755541080
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.176083392
Short name T119
Test name
Test status
Simulation time 399983719 ps
CPU time 1.71 seconds
Started Apr 15 12:22:49 PM PDT 24
Finished Apr 15 12:22:51 PM PDT 24
Peak memory 200988 kb
Host smart-1241cc8e-6ddc-4641-b6f5-5ad33d3a27c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176083392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.176083392
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2637384832
Short name T88
Test name
Test status
Simulation time 151206983 ps
CPU time 1.38 seconds
Started Apr 15 12:22:47 PM PDT 24
Finished Apr 15 12:22:49 PM PDT 24
Peak memory 209004 kb
Host smart-88b1f000-5d99-41d5-8f7b-099ad051f991
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637384832 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2637384832
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3025667056
Short name T549
Test name
Test status
Simulation time 81024328 ps
CPU time 0.83 seconds
Started Apr 15 12:22:47 PM PDT 24
Finished Apr 15 12:22:48 PM PDT 24
Peak memory 200756 kb
Host smart-9d837021-fa16-428f-8ea5-6745e2852b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025667056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3025667056
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1427627779
Short name T618
Test name
Test status
Simulation time 88824055 ps
CPU time 0.99 seconds
Started Apr 15 12:22:43 PM PDT 24
Finished Apr 15 12:22:45 PM PDT 24
Peak memory 200784 kb
Host smart-752959d6-5b8a-4073-8818-71eec1654218
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427627779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1427627779
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4278297157
Short name T554
Test name
Test status
Simulation time 110320017 ps
CPU time 1.4 seconds
Started Apr 15 12:22:46 PM PDT 24
Finished Apr 15 12:22:48 PM PDT 24
Peak memory 209140 kb
Host smart-e1e8183a-e7aa-4e97-9a75-8b3ca0ec82ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278297157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4278297157
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3054266367
Short name T135
Test name
Test status
Simulation time 879580370 ps
CPU time 3.34 seconds
Started Apr 15 12:22:55 PM PDT 24
Finished Apr 15 12:22:59 PM PDT 24
Peak memory 200940 kb
Host smart-756eb7d1-9e4f-4fe1-b6ed-e13a837dddf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054266367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3054266367
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1417777419
Short name T100
Test name
Test status
Simulation time 181029988 ps
CPU time 1.19 seconds
Started Apr 15 12:22:42 PM PDT 24
Finished Apr 15 12:22:44 PM PDT 24
Peak memory 208972 kb
Host smart-850ec8ad-2ecc-4052-bea0-421b5a4f7445
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417777419 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1417777419
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.38574228
Short name T561
Test name
Test status
Simulation time 63374631 ps
CPU time 0.8 seconds
Started Apr 15 12:22:42 PM PDT 24
Finished Apr 15 12:22:44 PM PDT 24
Peak memory 200576 kb
Host smart-312902da-4dfd-4db0-bedd-457b0e86eb45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38574228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.38574228
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3418987539
Short name T600
Test name
Test status
Simulation time 85326693 ps
CPU time 1 seconds
Started Apr 15 12:22:45 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 200684 kb
Host smart-f3a3d943-7021-467e-8066-9799a22571fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418987539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3418987539
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1813294300
Short name T569
Test name
Test status
Simulation time 360861103 ps
CPU time 2.65 seconds
Started Apr 15 12:22:48 PM PDT 24
Finished Apr 15 12:22:51 PM PDT 24
Peak memory 209132 kb
Host smart-55e28c25-fdac-403c-9a0a-beeb0085f213
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813294300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1813294300
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1510176439
Short name T577
Test name
Test status
Simulation time 503419561 ps
CPU time 1.85 seconds
Started Apr 15 12:22:39 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 200948 kb
Host smart-6b0708eb-3400-491c-ae29-a9688c9f357e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510176439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1510176439
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4224757852
Short name T75
Test name
Test status
Simulation time 113456853 ps
CPU time 0.89 seconds
Started Apr 15 12:22:49 PM PDT 24
Finished Apr 15 12:22:50 PM PDT 24
Peak memory 200868 kb
Host smart-91891ac0-da4c-4848-a58c-ae4d2e9ea0e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224757852 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.4224757852
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1150134253
Short name T104
Test name
Test status
Simulation time 73739772 ps
CPU time 0.88 seconds
Started Apr 15 12:22:47 PM PDT 24
Finished Apr 15 12:22:48 PM PDT 24
Peak memory 200696 kb
Host smart-a30b2485-e5d0-4a37-8562-cd44acb69748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150134253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1150134253
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2137197633
Short name T107
Test name
Test status
Simulation time 136907166 ps
CPU time 1.1 seconds
Started Apr 15 12:22:59 PM PDT 24
Finished Apr 15 12:23:01 PM PDT 24
Peak memory 200812 kb
Host smart-05a7b565-8ea2-41d6-82e8-7fc5c05c7faa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137197633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2137197633
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.980254803
Short name T566
Test name
Test status
Simulation time 537859552 ps
CPU time 4.09 seconds
Started Apr 15 12:22:46 PM PDT 24
Finished Apr 15 12:22:51 PM PDT 24
Peak memory 209220 kb
Host smart-7364b912-213e-443e-adc5-611cb05a4d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980254803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.980254803
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4188435967
Short name T599
Test name
Test status
Simulation time 502285409 ps
CPU time 2.02 seconds
Started Apr 15 12:23:14 PM PDT 24
Finished Apr 15 12:23:17 PM PDT 24
Peak memory 200988 kb
Host smart-7e49290c-e609-4f38-975b-586406f4342e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188435967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.4188435967
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2493571775
Short name T587
Test name
Test status
Simulation time 178166213 ps
CPU time 1.47 seconds
Started Apr 15 12:22:48 PM PDT 24
Finished Apr 15 12:22:50 PM PDT 24
Peak memory 212316 kb
Host smart-c315268f-e175-44e4-bbdc-86703cd6ea26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493571775 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2493571775
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.466570780
Short name T552
Test name
Test status
Simulation time 86825571 ps
CPU time 0.9 seconds
Started Apr 15 12:22:39 PM PDT 24
Finished Apr 15 12:22:46 PM PDT 24
Peak memory 200596 kb
Host smart-8e4ed4b9-3c2a-493d-b25b-48e09a268d9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466570780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.466570780
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3148841603
Short name T108
Test name
Test status
Simulation time 97081010 ps
CPU time 1.29 seconds
Started Apr 15 12:22:56 PM PDT 24
Finished Apr 15 12:22:58 PM PDT 24
Peak memory 201000 kb
Host smart-bd452def-2ef9-453e-a45a-44e4719b9a8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148841603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3148841603
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3725358765
Short name T81
Test name
Test status
Simulation time 225415625 ps
CPU time 1.68 seconds
Started Apr 15 12:22:48 PM PDT 24
Finished Apr 15 12:22:50 PM PDT 24
Peak memory 212560 kb
Host smart-489ebac3-50df-4128-800a-c8a1ce2739eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725358765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3725358765
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1601366691
Short name T586
Test name
Test status
Simulation time 492864362 ps
CPU time 2.02 seconds
Started Apr 15 12:22:43 PM PDT 24
Finished Apr 15 12:22:46 PM PDT 24
Peak memory 200984 kb
Host smart-6d782fd2-e235-4bf9-a579-d790ab64ae1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601366691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1601366691
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3163913145
Short name T571
Test name
Test status
Simulation time 195865139 ps
CPU time 1.83 seconds
Started Apr 15 12:22:50 PM PDT 24
Finished Apr 15 12:22:53 PM PDT 24
Peak memory 209220 kb
Host smart-82461d5f-35f6-4133-8236-ec74d1ed0db9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163913145 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3163913145
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2845053696
Short name T140
Test name
Test status
Simulation time 70535816 ps
CPU time 0.8 seconds
Started Apr 15 12:22:45 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 200624 kb
Host smart-6dedb207-ffa0-41d2-893d-4487f4224933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845053696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2845053696
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.298126146
Short name T620
Test name
Test status
Simulation time 195705449 ps
CPU time 1.47 seconds
Started Apr 15 12:22:49 PM PDT 24
Finished Apr 15 12:22:51 PM PDT 24
Peak memory 200988 kb
Host smart-2fb9d7c5-db20-4c26-8b24-98ab562b7f7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298126146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.298126146
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3398187292
Short name T619
Test name
Test status
Simulation time 904278578 ps
CPU time 3 seconds
Started Apr 15 12:22:59 PM PDT 24
Finished Apr 15 12:23:07 PM PDT 24
Peak memory 201008 kb
Host smart-51f3c40c-e9de-4b18-ad12-8a2d90d011d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398187292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3398187292
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3608066660
Short name T612
Test name
Test status
Simulation time 445581142 ps
CPU time 2.78 seconds
Started Apr 15 12:22:43 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 200944 kb
Host smart-56eb6943-1ca2-4d59-9a2a-832cb4c59238
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608066660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
608066660
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3755485429
Short name T573
Test name
Test status
Simulation time 265817615 ps
CPU time 3.27 seconds
Started Apr 15 12:23:17 PM PDT 24
Finished Apr 15 12:23:21 PM PDT 24
Peak memory 200932 kb
Host smart-396f19a0-ec38-4565-ac67-c573adf4a399
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755485429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
755485429
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2503550690
Short name T559
Test name
Test status
Simulation time 101867628 ps
CPU time 0.87 seconds
Started Apr 15 12:22:36 PM PDT 24
Finished Apr 15 12:22:37 PM PDT 24
Peak memory 200668 kb
Host smart-beb82643-a473-4cf1-ab9c-c418da925e32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503550690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
503550690
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3880082518
Short name T610
Test name
Test status
Simulation time 161235500 ps
CPU time 1.39 seconds
Started Apr 15 12:22:50 PM PDT 24
Finished Apr 15 12:22:53 PM PDT 24
Peak memory 209004 kb
Host smart-0da78ec7-caa4-453a-91eb-6786e6cf795a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880082518 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3880082518
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2464065593
Short name T578
Test name
Test status
Simulation time 69413860 ps
CPU time 0.76 seconds
Started Apr 15 12:22:41 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 200704 kb
Host smart-1b9f46c1-9b9a-4b19-b681-84d68e0b6e99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464065593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2464065593
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3364607510
Short name T550
Test name
Test status
Simulation time 143702002 ps
CPU time 1.15 seconds
Started Apr 15 12:22:46 PM PDT 24
Finished Apr 15 12:22:48 PM PDT 24
Peak memory 200756 kb
Host smart-30d47d8e-5db6-429b-9045-fad78c723762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364607510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3364607510
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3756684645
Short name T77
Test name
Test status
Simulation time 170531819 ps
CPU time 2.59 seconds
Started Apr 15 12:22:40 PM PDT 24
Finished Apr 15 12:22:43 PM PDT 24
Peak memory 212940 kb
Host smart-188486fc-36de-4c92-a80d-8ca3ab0a3e78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756684645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3756684645
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4010972149
Short name T122
Test name
Test status
Simulation time 871199022 ps
CPU time 3.45 seconds
Started Apr 15 12:22:47 PM PDT 24
Finished Apr 15 12:22:51 PM PDT 24
Peak memory 201028 kb
Host smart-b76c9074-5f4f-4124-ac17-aa0fd29d207b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010972149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.4010972149
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1965971400
Short name T551
Test name
Test status
Simulation time 108865501 ps
CPU time 1.37 seconds
Started Apr 15 12:22:41 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 200984 kb
Host smart-2aca2b1b-f797-45ce-a0f5-2a039b07cab0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965971400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
965971400
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1018115838
Short name T139
Test name
Test status
Simulation time 1553744368 ps
CPU time 8.57 seconds
Started Apr 15 12:22:42 PM PDT 24
Finished Apr 15 12:22:51 PM PDT 24
Peak memory 200928 kb
Host smart-e54f816a-85df-4a45-8030-1942971c4707
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018115838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
018115838
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.184081459
Short name T568
Test name
Test status
Simulation time 171952151 ps
CPU time 0.98 seconds
Started Apr 15 12:22:40 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 200676 kb
Host smart-a5e305ee-900d-4852-ac8a-e947419875d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184081459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.184081459
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.179250531
Short name T595
Test name
Test status
Simulation time 113952326 ps
CPU time 0.99 seconds
Started Apr 15 12:22:43 PM PDT 24
Finished Apr 15 12:22:44 PM PDT 24
Peak memory 200836 kb
Host smart-addbadfd-b674-49ec-8fec-9b72f933e1ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179250531 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.179250531
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3240903187
Short name T617
Test name
Test status
Simulation time 59114762 ps
CPU time 0.75 seconds
Started Apr 15 12:22:41 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 200732 kb
Host smart-605dd6ce-2b88-4940-9f0e-c317a82198c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240903187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3240903187
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2698087795
Short name T601
Test name
Test status
Simulation time 132333405 ps
CPU time 1.24 seconds
Started Apr 15 12:22:39 PM PDT 24
Finished Apr 15 12:22:41 PM PDT 24
Peak memory 200968 kb
Host smart-4763a6c2-65e5-4440-86ea-e27157c82ac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698087795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2698087795
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2313246375
Short name T125
Test name
Test status
Simulation time 323706409 ps
CPU time 2.07 seconds
Started Apr 15 12:22:43 PM PDT 24
Finished Apr 15 12:22:46 PM PDT 24
Peak memory 209192 kb
Host smart-bc9f47bc-78bd-4486-8a0d-be85ff36f521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313246375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2313246375
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3904857103
Short name T123
Test name
Test status
Simulation time 507246226 ps
CPU time 2.15 seconds
Started Apr 15 12:22:35 PM PDT 24
Finished Apr 15 12:22:37 PM PDT 24
Peak memory 200920 kb
Host smart-7e30eaf5-65b0-4f27-929d-494f486859a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904857103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3904857103
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.808907822
Short name T556
Test name
Test status
Simulation time 113949053 ps
CPU time 1.37 seconds
Started Apr 15 12:23:22 PM PDT 24
Finished Apr 15 12:23:24 PM PDT 24
Peak memory 200176 kb
Host smart-7d13082e-6439-47e9-9740-f24cb8c19708
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808907822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.808907822
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.443017590
Short name T553
Test name
Test status
Simulation time 2003635329 ps
CPU time 8.96 seconds
Started Apr 15 12:22:47 PM PDT 24
Finished Apr 15 12:22:56 PM PDT 24
Peak memory 200888 kb
Host smart-09e656c2-4920-4f07-a494-5e659e771f3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443017590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.443017590
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1941994706
Short name T597
Test name
Test status
Simulation time 150534096 ps
CPU time 0.94 seconds
Started Apr 15 12:22:55 PM PDT 24
Finished Apr 15 12:22:56 PM PDT 24
Peak memory 200728 kb
Host smart-b0d1650c-94c2-4c74-a25d-0eb4246047e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941994706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
941994706
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1382617288
Short name T101
Test name
Test status
Simulation time 208574963 ps
CPU time 1.37 seconds
Started Apr 15 12:22:43 PM PDT 24
Finished Apr 15 12:22:45 PM PDT 24
Peak memory 200852 kb
Host smart-58408112-3a17-4c2e-9ea3-d8122daca15d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382617288 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1382617288
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2009198560
Short name T603
Test name
Test status
Simulation time 60824230 ps
CPU time 0.78 seconds
Started Apr 15 12:22:42 PM PDT 24
Finished Apr 15 12:22:44 PM PDT 24
Peak memory 200672 kb
Host smart-efd6ec92-a26a-4fe0-b8da-d1a06db77015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009198560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2009198560
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2543682117
Short name T547
Test name
Test status
Simulation time 136867972 ps
CPU time 1.05 seconds
Started Apr 15 12:23:52 PM PDT 24
Finished Apr 15 12:23:53 PM PDT 24
Peak memory 200804 kb
Host smart-51e408a9-41bb-4c54-925d-de19d16e4f5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543682117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2543682117
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3610679183
Short name T613
Test name
Test status
Simulation time 196362124 ps
CPU time 2.63 seconds
Started Apr 15 12:23:33 PM PDT 24
Finished Apr 15 12:23:37 PM PDT 24
Peak memory 209208 kb
Host smart-0f9e6255-7594-4f22-a078-93694178e93b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610679183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3610679183
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2952910644
Short name T574
Test name
Test status
Simulation time 118744254 ps
CPU time 0.95 seconds
Started Apr 15 12:22:38 PM PDT 24
Finished Apr 15 12:22:40 PM PDT 24
Peak memory 200944 kb
Host smart-181ec6f3-81ba-45c6-a7aa-6ea23b1bdc24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952910644 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2952910644
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1490165493
Short name T572
Test name
Test status
Simulation time 69107526 ps
CPU time 0.77 seconds
Started Apr 15 12:22:45 PM PDT 24
Finished Apr 15 12:22:47 PM PDT 24
Peak memory 200748 kb
Host smart-0e2543d7-876f-4a82-bb2e-db98b43a880c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490165493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1490165493
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.853493509
Short name T614
Test name
Test status
Simulation time 149067269 ps
CPU time 1.12 seconds
Started Apr 15 12:22:49 PM PDT 24
Finished Apr 15 12:22:50 PM PDT 24
Peak memory 200744 kb
Host smart-d47a7fcb-0236-4aaa-b883-1ae041583073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853493509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.853493509
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3885291583
Short name T607
Test name
Test status
Simulation time 472691642 ps
CPU time 3.08 seconds
Started Apr 15 12:22:38 PM PDT 24
Finished Apr 15 12:22:42 PM PDT 24
Peak memory 209148 kb
Host smart-195aab96-bc7d-4fe9-b5b7-2426001ee56b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885291583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3885291583
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2886840493
Short name T567
Test name
Test status
Simulation time 1110131316 ps
CPU time 3.59 seconds
Started Apr 15 12:22:40 PM PDT 24
Finished Apr 15 12:22:44 PM PDT 24
Peak memory 200980 kb
Host smart-de50eac3-a49b-435f-98f8-7d3e59b6ef70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886840493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2886840493
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.716852983
Short name T565
Test name
Test status
Simulation time 118648612 ps
CPU time 0.95 seconds
Started Apr 15 12:22:44 PM PDT 24
Finished Apr 15 12:22:46 PM PDT 24
Peak memory 200856 kb
Host smart-777c64de-b86d-4c5e-b320-78d8429c7a8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716852983 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.716852983
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.414988579
Short name T545
Test name
Test status
Simulation time 73855312 ps
CPU time 0.79 seconds
Started Apr 15 12:23:27 PM PDT 24
Finished Apr 15 12:23:28 PM PDT 24
Peak memory 200632 kb
Host smart-2071d8b0-91f7-49ab-b883-db6ebd019ca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414988579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.414988579
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1029108084
Short name T562
Test name
Test status
Simulation time 78360787 ps
CPU time 0.94 seconds
Started Apr 15 12:23:05 PM PDT 24
Finished Apr 15 12:23:06 PM PDT 24
Peak memory 200824 kb
Host smart-7acce691-2fb5-4dce-9691-3dcc6d9800c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029108084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1029108084
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2753800981
Short name T99
Test name
Test status
Simulation time 174040080 ps
CPU time 1.33 seconds
Started Apr 15 12:22:42 PM PDT 24
Finished Apr 15 12:22:44 PM PDT 24
Peak memory 200784 kb
Host smart-a1987a60-4a30-4b2f-98c5-f31731b92115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753800981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2753800981
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2682645682
Short name T137
Test name
Test status
Simulation time 447869484 ps
CPU time 1.69 seconds
Started Apr 15 12:22:38 PM PDT 24
Finished Apr 15 12:22:40 PM PDT 24
Peak memory 201024 kb
Host smart-954cda29-4db9-4fe5-90fe-31200d124fab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682645682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2682645682
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3539195539
Short name T615
Test name
Test status
Simulation time 68035676 ps
CPU time 0.81 seconds
Started Apr 15 12:23:21 PM PDT 24
Finished Apr 15 12:23:22 PM PDT 24
Peak memory 200740 kb
Host smart-e0cd9150-1db2-4e95-ad93-a6b3e363bf8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539195539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3539195539
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4187145615
Short name T112
Test name
Test status
Simulation time 132943891 ps
CPU time 1.37 seconds
Started Apr 15 12:23:58 PM PDT 24
Finished Apr 15 12:24:00 PM PDT 24
Peak memory 201012 kb
Host smart-79b1cf53-a0ee-44c3-a3b8-75cc8a612063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187145615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.4187145615
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3098891037
Short name T589
Test name
Test status
Simulation time 355024667 ps
CPU time 2.23 seconds
Started Apr 15 12:22:49 PM PDT 24
Finished Apr 15 12:22:52 PM PDT 24
Peak memory 209168 kb
Host smart-4a831326-e9a3-47dd-a217-282357568921
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098891037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3098891037
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1756564864
Short name T576
Test name
Test status
Simulation time 175869953 ps
CPU time 1.69 seconds
Started Apr 15 12:22:56 PM PDT 24
Finished Apr 15 12:22:58 PM PDT 24
Peak memory 209180 kb
Host smart-867f8bf9-fc2d-4dda-8ac8-7c0cd6fd68e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756564864 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1756564864
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2432824154
Short name T588
Test name
Test status
Simulation time 69697486 ps
CPU time 0.89 seconds
Started Apr 15 12:23:34 PM PDT 24
Finished Apr 15 12:23:37 PM PDT 24
Peak memory 200752 kb
Host smart-61308bd8-d800-46d6-8ac2-32d961a924ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432824154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2432824154
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.600220236
Short name T114
Test name
Test status
Simulation time 242540954 ps
CPU time 1.49 seconds
Started Apr 15 12:23:38 PM PDT 24
Finished Apr 15 12:23:42 PM PDT 24
Peak memory 200980 kb
Host smart-6c82e8a0-92c4-42d7-abbe-bcd457da80f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600220236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.600220236
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1563960283
Short name T590
Test name
Test status
Simulation time 417690911 ps
CPU time 2.56 seconds
Started Apr 15 12:22:48 PM PDT 24
Finished Apr 15 12:22:51 PM PDT 24
Peak memory 209192 kb
Host smart-e11cd064-7991-41ec-8bc9-affdfa681c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563960283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1563960283
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3663087297
Short name T117
Test name
Test status
Simulation time 796795583 ps
CPU time 2.86 seconds
Started Apr 15 12:22:40 PM PDT 24
Finished Apr 15 12:22:43 PM PDT 24
Peak memory 200996 kb
Host smart-8766d6ee-545c-47d7-adcc-65562e383f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663087297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3663087297
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3746774207
Short name T580
Test name
Test status
Simulation time 150856218 ps
CPU time 1.12 seconds
Started Apr 15 12:22:43 PM PDT 24
Finished Apr 15 12:22:45 PM PDT 24
Peak memory 201036 kb
Host smart-a8b6875e-f4f3-4bea-801c-9f50a8df4906
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746774207 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3746774207
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3010748526
Short name T584
Test name
Test status
Simulation time 63563322 ps
CPU time 0.8 seconds
Started Apr 15 12:22:44 PM PDT 24
Finished Apr 15 12:22:45 PM PDT 24
Peak memory 200736 kb
Host smart-17a7760a-06c7-430f-995b-4042500f1e26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010748526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3010748526
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2234755874
Short name T616
Test name
Test status
Simulation time 119862150 ps
CPU time 1.06 seconds
Started Apr 15 12:22:57 PM PDT 24
Finished Apr 15 12:22:58 PM PDT 24
Peak memory 200760 kb
Host smart-e6426099-dfbc-41eb-b239-2a6eb16eea83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234755874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2234755874
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1956261466
Short name T581
Test name
Test status
Simulation time 201452316 ps
CPU time 2.86 seconds
Started Apr 15 12:23:21 PM PDT 24
Finished Apr 15 12:23:25 PM PDT 24
Peak memory 209204 kb
Host smart-739124be-eb3d-46d8-a2c2-56e47cc19aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956261466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1956261466
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.161156100
Short name T602
Test name
Test status
Simulation time 1047419859 ps
CPU time 3.37 seconds
Started Apr 15 12:22:48 PM PDT 24
Finished Apr 15 12:22:52 PM PDT 24
Peak memory 201064 kb
Host smart-b2b838f2-19c2-41cd-a244-df37f720496c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161156100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
161156100
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2677853586
Short name T341
Test name
Test status
Simulation time 74706297 ps
CPU time 0.78 seconds
Started Apr 15 12:37:41 PM PDT 24
Finished Apr 15 12:37:43 PM PDT 24
Peak memory 200584 kb
Host smart-deacfe8a-3050-41ec-b4e4-da8ec6b58d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677853586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2677853586
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2221095454
Short name T544
Test name
Test status
Simulation time 1234797864 ps
CPU time 5.77 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:52 PM PDT 24
Peak memory 222104 kb
Host smart-1bcd691d-b533-4691-9b15-c74f7d1b709d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221095454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2221095454
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3066828536
Short name T436
Test name
Test status
Simulation time 243954325 ps
CPU time 1.01 seconds
Started Apr 15 12:37:39 PM PDT 24
Finished Apr 15 12:37:41 PM PDT 24
Peak memory 218172 kb
Host smart-7f151d1c-b57f-428c-a662-d9845fa9b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066828536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3066828536
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4282719216
Short name T313
Test name
Test status
Simulation time 158864390 ps
CPU time 0.84 seconds
Started Apr 15 12:37:46 PM PDT 24
Finished Apr 15 12:37:48 PM PDT 24
Peak memory 200584 kb
Host smart-aae7bcc1-3430-47ee-ab55-c2ab2af3c687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282719216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4282719216
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1230420473
Short name T283
Test name
Test status
Simulation time 1353161597 ps
CPU time 5.3 seconds
Started Apr 15 12:37:40 PM PDT 24
Finished Apr 15 12:37:46 PM PDT 24
Peak memory 200936 kb
Host smart-ab2147d1-7e0d-4aec-86b1-b972eea35e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230420473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1230420473
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3096741681
Short name T83
Test name
Test status
Simulation time 8394102838 ps
CPU time 13.28 seconds
Started Apr 15 12:37:41 PM PDT 24
Finished Apr 15 12:37:56 PM PDT 24
Peak memory 221736 kb
Host smart-96bf3579-a8df-40ec-9237-14aa63ed59cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096741681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3096741681
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3765034289
Short name T398
Test name
Test status
Simulation time 112565797 ps
CPU time 1.04 seconds
Started Apr 15 12:37:40 PM PDT 24
Finished Apr 15 12:37:41 PM PDT 24
Peak memory 200736 kb
Host smart-983d9470-ccbd-4e18-b5b3-61287c814b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765034289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3765034289
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2040379676
Short name T434
Test name
Test status
Simulation time 200691849 ps
CPU time 1.36 seconds
Started Apr 15 12:37:48 PM PDT 24
Finished Apr 15 12:37:51 PM PDT 24
Peak memory 201032 kb
Host smart-e0b26123-299f-46fa-a30e-ef5c62494a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040379676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2040379676
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3842692764
Short name T353
Test name
Test status
Simulation time 7429126158 ps
CPU time 24.85 seconds
Started Apr 15 12:37:38 PM PDT 24
Finished Apr 15 12:38:04 PM PDT 24
Peak memory 210828 kb
Host smart-70caceb3-c8df-4904-9636-5f485a1ac1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842692764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3842692764
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1716054422
Short name T318
Test name
Test status
Simulation time 109197554 ps
CPU time 1.33 seconds
Started Apr 15 12:37:41 PM PDT 24
Finished Apr 15 12:37:43 PM PDT 24
Peak memory 200736 kb
Host smart-509956b2-5f8b-4dc7-b349-d7ca17791f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716054422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1716054422
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1284828906
Short name T528
Test name
Test status
Simulation time 264534526 ps
CPU time 1.42 seconds
Started Apr 15 12:37:40 PM PDT 24
Finished Apr 15 12:37:43 PM PDT 24
Peak memory 200816 kb
Host smart-c8740267-b547-4e2b-8792-9681351dbe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284828906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1284828906
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.868654656
Short name T407
Test name
Test status
Simulation time 68499407 ps
CPU time 0.8 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:47 PM PDT 24
Peak memory 200628 kb
Host smart-000aa532-f380-4b35-991f-5b2541b017b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868654656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.868654656
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3886054472
Short name T502
Test name
Test status
Simulation time 1225048963 ps
CPU time 5.67 seconds
Started Apr 15 12:37:43 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 217684 kb
Host smart-8e3b4a8b-383a-4615-9e70-ab2e9d93c1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886054472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3886054472
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1750258019
Short name T452
Test name
Test status
Simulation time 244363622 ps
CPU time 1.07 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:47 PM PDT 24
Peak memory 218208 kb
Host smart-90559d0e-b2d3-4cad-8afc-14470275dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750258019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1750258019
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.343067410
Short name T403
Test name
Test status
Simulation time 131908304 ps
CPU time 0.79 seconds
Started Apr 15 12:37:36 PM PDT 24
Finished Apr 15 12:37:37 PM PDT 24
Peak memory 200644 kb
Host smart-a7f3b1fc-5e37-45ff-89d0-421639ea3944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343067410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.343067410
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2215233115
Short name T150
Test name
Test status
Simulation time 1081410070 ps
CPU time 4.7 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:51 PM PDT 24
Peak memory 200956 kb
Host smart-b09df756-3f40-4975-a794-c55f672a1bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215233115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2215233115
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1380591427
Short name T90
Test name
Test status
Simulation time 17446551727 ps
CPU time 25.52 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:38:11 PM PDT 24
Peak memory 218724 kb
Host smart-32a0625a-d54c-4bc2-abdc-0d7a4e1723ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380591427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1380591427
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.735981099
Short name T268
Test name
Test status
Simulation time 149655034 ps
CPU time 1.08 seconds
Started Apr 15 12:37:44 PM PDT 24
Finished Apr 15 12:37:46 PM PDT 24
Peak memory 200788 kb
Host smart-69cdbc0e-d4a5-43fd-a01e-7168fffec127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735981099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.735981099
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3656096555
Short name T154
Test name
Test status
Simulation time 247567287 ps
CPU time 1.51 seconds
Started Apr 15 12:37:46 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 201028 kb
Host smart-08d70f9b-42aa-4081-9317-37b3fc61c74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656096555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3656096555
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.521397384
Short name T430
Test name
Test status
Simulation time 1606619169 ps
CPU time 6.27 seconds
Started Apr 15 12:37:42 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 200960 kb
Host smart-43cd1f26-d2d5-4c41-a876-6ca0b91469cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521397384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.521397384
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2778382704
Short name T189
Test name
Test status
Simulation time 446120394 ps
CPU time 2.32 seconds
Started Apr 15 12:37:43 PM PDT 24
Finished Apr 15 12:37:46 PM PDT 24
Peak memory 200748 kb
Host smart-089ea7dd-24a3-48c8-969e-9803ae3dfa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778382704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2778382704
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2810233472
Short name T463
Test name
Test status
Simulation time 77903846 ps
CPU time 0.91 seconds
Started Apr 15 12:37:43 PM PDT 24
Finished Apr 15 12:37:45 PM PDT 24
Peak memory 200800 kb
Host smart-72f26185-933b-4370-8613-03cb7c7fb3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810233472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2810233472
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2584199968
Short name T454
Test name
Test status
Simulation time 60858712 ps
CPU time 0.76 seconds
Started Apr 15 12:38:01 PM PDT 24
Finished Apr 15 12:38:03 PM PDT 24
Peak memory 200608 kb
Host smart-d8fa40ba-c03d-4b48-98e8-31e9edf0a21a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584199968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2584199968
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.702662116
Short name T67
Test name
Test status
Simulation time 2350725522 ps
CPU time 8.9 seconds
Started Apr 15 12:37:56 PM PDT 24
Finished Apr 15 12:38:06 PM PDT 24
Peak memory 218416 kb
Host smart-5c13ecdd-8798-4a6a-924a-66fb2246b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702662116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.702662116
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3894057083
Short name T478
Test name
Test status
Simulation time 244750012 ps
CPU time 1.06 seconds
Started Apr 15 12:37:56 PM PDT 24
Finished Apr 15 12:37:57 PM PDT 24
Peak memory 218144 kb
Host smart-8fcb8525-7b7a-4da8-8140-d9979d296965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894057083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3894057083
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2323098210
Short name T399
Test name
Test status
Simulation time 90161722 ps
CPU time 0.78 seconds
Started Apr 15 12:37:59 PM PDT 24
Finished Apr 15 12:38:01 PM PDT 24
Peak memory 200640 kb
Host smart-82cfad71-d305-47b6-b0c4-5cc8b651d04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323098210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2323098210
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.205244220
Short name T91
Test name
Test status
Simulation time 1612577044 ps
CPU time 6.87 seconds
Started Apr 15 12:37:59 PM PDT 24
Finished Apr 15 12:38:07 PM PDT 24
Peak memory 200992 kb
Host smart-86962bb5-0e1f-4b7a-8a89-dd4c75124a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205244220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.205244220
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.412913863
Short name T360
Test name
Test status
Simulation time 152946868 ps
CPU time 1.17 seconds
Started Apr 15 12:38:03 PM PDT 24
Finished Apr 15 12:38:05 PM PDT 24
Peak memory 200788 kb
Host smart-c2d928f8-4dcb-4051-ab1a-f05b2b380315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412913863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.412913863
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.4248812549
Short name T278
Test name
Test status
Simulation time 193454232 ps
CPU time 1.4 seconds
Started Apr 15 12:38:01 PM PDT 24
Finished Apr 15 12:38:03 PM PDT 24
Peak memory 201036 kb
Host smart-c9e41e37-0f37-499e-8fad-a5784475de7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248812549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.4248812549
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1108285582
Short name T417
Test name
Test status
Simulation time 4680978914 ps
CPU time 17.07 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:18 PM PDT 24
Peak memory 201080 kb
Host smart-3a9472da-3330-4358-8c67-3549adb4cf58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108285582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1108285582
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3643828130
Short name T429
Test name
Test status
Simulation time 78740411 ps
CPU time 0.8 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:02 PM PDT 24
Peak memory 200796 kb
Host smart-6b299b9a-1687-4a04-a522-fae2f9e5e058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643828130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3643828130
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.980219740
Short name T233
Test name
Test status
Simulation time 61319438 ps
CPU time 0.75 seconds
Started Apr 15 12:37:57 PM PDT 24
Finished Apr 15 12:37:58 PM PDT 24
Peak memory 200628 kb
Host smart-4ea44926-425c-4d36-8394-c26b8b0fc668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980219740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.980219740
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4106461715
Short name T44
Test name
Test status
Simulation time 1887092627 ps
CPU time 7.5 seconds
Started Apr 15 12:37:58 PM PDT 24
Finished Apr 15 12:38:06 PM PDT 24
Peak memory 218572 kb
Host smart-dc4309cb-3ea9-4ed4-a54b-f5ac68bae247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106461715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4106461715
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2674712756
Short name T372
Test name
Test status
Simulation time 244526576 ps
CPU time 1.07 seconds
Started Apr 15 12:37:55 PM PDT 24
Finished Apr 15 12:37:57 PM PDT 24
Peak memory 218240 kb
Host smart-adf321ed-50ec-4e2d-875d-f644aeea26ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674712756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2674712756
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.421579561
Short name T457
Test name
Test status
Simulation time 141026688 ps
CPU time 0.85 seconds
Started Apr 15 12:37:59 PM PDT 24
Finished Apr 15 12:38:01 PM PDT 24
Peak memory 200572 kb
Host smart-90471fd9-32e2-404b-b9b0-33eaa79ddd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421579561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.421579561
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2340778980
Short name T59
Test name
Test status
Simulation time 968790387 ps
CPU time 4.71 seconds
Started Apr 15 12:37:58 PM PDT 24
Finished Apr 15 12:38:03 PM PDT 24
Peak memory 201040 kb
Host smart-36ceb371-2a8a-4953-b7ca-68d7120a754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340778980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2340778980
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2497864995
Short name T474
Test name
Test status
Simulation time 103236510 ps
CPU time 0.98 seconds
Started Apr 15 12:37:57 PM PDT 24
Finished Apr 15 12:37:59 PM PDT 24
Peak memory 200836 kb
Host smart-706bf541-9450-4054-9d16-aa63bcb81165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497864995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2497864995
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.4164846269
Short name T294
Test name
Test status
Simulation time 113657434 ps
CPU time 1.21 seconds
Started Apr 15 12:37:56 PM PDT 24
Finished Apr 15 12:37:58 PM PDT 24
Peak memory 200988 kb
Host smart-85ea9808-e11b-4ba6-91dc-979b17b9ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164846269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.4164846269
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2773760770
Short name T487
Test name
Test status
Simulation time 3932191305 ps
CPU time 13.88 seconds
Started Apr 15 12:37:58 PM PDT 24
Finished Apr 15 12:38:13 PM PDT 24
Peak memory 209240 kb
Host smart-e348a52c-d143-43e7-8059-6e79c1fa4b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773760770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2773760770
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1780162026
Short name T299
Test name
Test status
Simulation time 370991732 ps
CPU time 2.39 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:03 PM PDT 24
Peak memory 200828 kb
Host smart-f64dc695-12cc-44b3-91b3-c4a6c02877c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780162026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1780162026
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1947010866
Short name T312
Test name
Test status
Simulation time 88532103 ps
CPU time 0.84 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:02 PM PDT 24
Peak memory 200560 kb
Host smart-eab52c73-30d7-4727-8afc-df9477d0c430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947010866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1947010866
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.175770185
Short name T488
Test name
Test status
Simulation time 1227367382 ps
CPU time 5.64 seconds
Started Apr 15 12:38:01 PM PDT 24
Finished Apr 15 12:38:08 PM PDT 24
Peak memory 217592 kb
Host smart-15b9045c-b07e-47aa-8ca5-8d438fcae5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175770185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.175770185
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4268935566
Short name T174
Test name
Test status
Simulation time 244278534 ps
CPU time 1.07 seconds
Started Apr 15 12:38:02 PM PDT 24
Finished Apr 15 12:38:03 PM PDT 24
Peak memory 218312 kb
Host smart-a80fd94b-3b4a-43d7-8a62-932891b3798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268935566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4268935566
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.4102787918
Short name T486
Test name
Test status
Simulation time 91080186 ps
CPU time 0.78 seconds
Started Apr 15 12:37:57 PM PDT 24
Finished Apr 15 12:37:58 PM PDT 24
Peak memory 200644 kb
Host smart-e5a6fc74-fd62-4488-8df4-51a575f96bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102787918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.4102787918
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3516367363
Short name T252
Test name
Test status
Simulation time 1802871115 ps
CPU time 6.86 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:08 PM PDT 24
Peak memory 200980 kb
Host smart-08d383b0-13cd-42fc-8077-d1adcfd5ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516367363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3516367363
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.489740927
Short name T223
Test name
Test status
Simulation time 103031075 ps
CPU time 1.05 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:02 PM PDT 24
Peak memory 200804 kb
Host smart-1c8d0d87-8127-4347-9880-1b7bf7058803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489740927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.489740927
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.4020314563
Short name T387
Test name
Test status
Simulation time 230282322 ps
CPU time 1.71 seconds
Started Apr 15 12:37:56 PM PDT 24
Finished Apr 15 12:37:59 PM PDT 24
Peak memory 201016 kb
Host smart-dcc10faf-d5b3-4ec3-847d-625e9921bce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020314563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.4020314563
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.4260486386
Short name T182
Test name
Test status
Simulation time 8089094801 ps
CPU time 28.09 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 201084 kb
Host smart-eb9f4be1-d068-4222-bda2-77127b7df1ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260486386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.4260486386
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2421350681
Short name T369
Test name
Test status
Simulation time 155998256 ps
CPU time 1.94 seconds
Started Apr 15 12:37:57 PM PDT 24
Finished Apr 15 12:38:00 PM PDT 24
Peak memory 200776 kb
Host smart-494595ca-935e-49cd-86aa-0671308400c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421350681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2421350681
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3921847820
Short name T155
Test name
Test status
Simulation time 237565780 ps
CPU time 1.37 seconds
Started Apr 15 12:38:02 PM PDT 24
Finished Apr 15 12:38:04 PM PDT 24
Peak memory 200860 kb
Host smart-aea41352-78e6-4061-b80b-3bfd23da94aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921847820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3921847820
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2610155034
Short name T512
Test name
Test status
Simulation time 72623994 ps
CPU time 0.78 seconds
Started Apr 15 12:38:05 PM PDT 24
Finished Apr 15 12:38:07 PM PDT 24
Peak memory 200644 kb
Host smart-0d8ecdf3-dd77-4e13-b1e7-a424ce775984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610155034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2610155034
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3748329767
Short name T133
Test name
Test status
Simulation time 1904847138 ps
CPU time 6.95 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:07 PM PDT 24
Peak memory 222728 kb
Host smart-f374c240-1be1-498e-a482-03c2936b45dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748329767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3748329767
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2082091916
Short name T250
Test name
Test status
Simulation time 244734321 ps
CPU time 1.1 seconds
Started Apr 15 12:38:05 PM PDT 24
Finished Apr 15 12:38:06 PM PDT 24
Peak memory 218196 kb
Host smart-a293110d-08a6-42cd-a249-527c373d56c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082091916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2082091916
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3771517070
Short name T501
Test name
Test status
Simulation time 194116560 ps
CPU time 0.86 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:02 PM PDT 24
Peak memory 200572 kb
Host smart-da13fdb3-b9ba-481f-aa19-c99c2c1e60cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771517070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3771517070
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.4196037553
Short name T427
Test name
Test status
Simulation time 926751512 ps
CPU time 4.35 seconds
Started Apr 15 12:38:02 PM PDT 24
Finished Apr 15 12:38:07 PM PDT 24
Peak memory 201028 kb
Host smart-3ff7f877-cf84-4612-a1b7-ea3704ec637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196037553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.4196037553
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1727848563
Short name T379
Test name
Test status
Simulation time 102198214 ps
CPU time 1.07 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:02 PM PDT 24
Peak memory 200756 kb
Host smart-82dde723-fdab-4faa-a90c-4d91aba2b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727848563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1727848563
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3520123424
Short name T132
Test name
Test status
Simulation time 246492526 ps
CPU time 1.44 seconds
Started Apr 15 12:38:57 PM PDT 24
Finished Apr 15 12:38:59 PM PDT 24
Peak memory 201032 kb
Host smart-f3cf582f-720a-4afd-a43f-e65f2779aef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520123424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3520123424
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1997790362
Short name T425
Test name
Test status
Simulation time 4703812234 ps
CPU time 15.43 seconds
Started Apr 15 12:38:05 PM PDT 24
Finished Apr 15 12:38:21 PM PDT 24
Peak memory 200996 kb
Host smart-fd7349f3-95db-4758-bdb8-d4b26509e501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997790362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1997790362
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3545518161
Short name T479
Test name
Test status
Simulation time 154237415 ps
CPU time 1.34 seconds
Started Apr 15 12:38:01 PM PDT 24
Finished Apr 15 12:38:04 PM PDT 24
Peak memory 200920 kb
Host smart-0ab95bec-ce19-4a34-b6cc-fdc213b02680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545518161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3545518161
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1706342745
Short name T192
Test name
Test status
Simulation time 65281242 ps
CPU time 0.78 seconds
Started Apr 15 12:38:13 PM PDT 24
Finished Apr 15 12:38:14 PM PDT 24
Peak memory 200620 kb
Host smart-badfcad0-fd02-4ca1-8789-29461ff120e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706342745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1706342745
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3018644709
Short name T198
Test name
Test status
Simulation time 1895302652 ps
CPU time 7.4 seconds
Started Apr 15 12:38:12 PM PDT 24
Finished Apr 15 12:38:20 PM PDT 24
Peak memory 218552 kb
Host smart-8b8c51e6-1d71-4fda-92e3-520ed821bd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018644709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3018644709
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3018541861
Short name T386
Test name
Test status
Simulation time 244737217 ps
CPU time 1.16 seconds
Started Apr 15 12:38:13 PM PDT 24
Finished Apr 15 12:38:15 PM PDT 24
Peak memory 218124 kb
Host smart-083069f4-d22a-4f6d-b711-ed821256d70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018541861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3018541861
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3592637850
Short name T228
Test name
Test status
Simulation time 169611028 ps
CPU time 0.84 seconds
Started Apr 15 12:38:07 PM PDT 24
Finished Apr 15 12:38:09 PM PDT 24
Peak memory 200612 kb
Host smart-c3a421b3-181f-4c22-af78-d69de5a61a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592637850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3592637850
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3866270295
Short name T307
Test name
Test status
Simulation time 1610886321 ps
CPU time 5.93 seconds
Started Apr 15 12:38:08 PM PDT 24
Finished Apr 15 12:38:15 PM PDT 24
Peak memory 200996 kb
Host smart-42d3de9f-ca6d-4e21-888f-871d65f50c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866270295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3866270295
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1376905280
Short name T489
Test name
Test status
Simulation time 103156405 ps
CPU time 1.04 seconds
Started Apr 15 12:38:05 PM PDT 24
Finished Apr 15 12:38:07 PM PDT 24
Peak memory 200832 kb
Host smart-0815ffa0-5e37-4cc0-a0e2-50a0d9450d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376905280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1376905280
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2818093477
Short name T428
Test name
Test status
Simulation time 198531797 ps
CPU time 1.42 seconds
Started Apr 15 12:38:06 PM PDT 24
Finished Apr 15 12:38:08 PM PDT 24
Peak memory 200920 kb
Host smart-0a318cff-b7ee-40b5-a49f-89847ba61501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818093477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2818093477
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3167237288
Short name T280
Test name
Test status
Simulation time 12382463359 ps
CPU time 45.37 seconds
Started Apr 15 12:38:12 PM PDT 24
Finished Apr 15 12:38:58 PM PDT 24
Peak memory 201028 kb
Host smart-175412c4-ca0b-4602-8a87-bc021ddc2d4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167237288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3167237288
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2139474178
Short name T180
Test name
Test status
Simulation time 134579033 ps
CPU time 1.77 seconds
Started Apr 15 12:38:06 PM PDT 24
Finished Apr 15 12:38:08 PM PDT 24
Peak memory 208920 kb
Host smart-01eb442b-1492-4e8e-936e-f41c0c7803b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139474178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2139474178
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.652828337
Short name T95
Test name
Test status
Simulation time 200358119 ps
CPU time 1.43 seconds
Started Apr 15 12:38:04 PM PDT 24
Finished Apr 15 12:38:06 PM PDT 24
Peak memory 200836 kb
Host smart-c22ff179-cc62-4615-9214-0acceb3b7eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652828337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.652828337
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1389280211
Short name T492
Test name
Test status
Simulation time 66909959 ps
CPU time 0.8 seconds
Started Apr 15 12:38:12 PM PDT 24
Finished Apr 15 12:38:13 PM PDT 24
Peak memory 200636 kb
Host smart-ccc7cfed-5329-4198-9834-9ceb18bfaac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389280211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1389280211
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3578491172
Short name T376
Test name
Test status
Simulation time 2360880763 ps
CPU time 8.07 seconds
Started Apr 15 12:38:12 PM PDT 24
Finished Apr 15 12:38:21 PM PDT 24
Peak memory 230616 kb
Host smart-7e18ac55-7d8c-49e0-a280-c11f62d4755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578491172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3578491172
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3805007822
Short name T260
Test name
Test status
Simulation time 244027890 ps
CPU time 1.16 seconds
Started Apr 15 12:38:11 PM PDT 24
Finished Apr 15 12:38:13 PM PDT 24
Peak memory 218300 kb
Host smart-5233cca9-466e-4152-a7ff-6a606b8692ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805007822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3805007822
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3976041289
Short name T317
Test name
Test status
Simulation time 82396537 ps
CPU time 0.82 seconds
Started Apr 15 12:38:13 PM PDT 24
Finished Apr 15 12:38:14 PM PDT 24
Peak memory 200544 kb
Host smart-ed265a00-aeb7-4674-801c-7ee0afefd702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976041289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3976041289
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.538051250
Short name T243
Test name
Test status
Simulation time 954323187 ps
CPU time 5.1 seconds
Started Apr 15 12:38:12 PM PDT 24
Finished Apr 15 12:38:18 PM PDT 24
Peak memory 201040 kb
Host smart-8b60ac1e-ded7-4b93-b54d-2c53bcecbe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538051250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.538051250
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4169116122
Short name T143
Test name
Test status
Simulation time 107985904 ps
CPU time 1.05 seconds
Started Apr 15 12:38:12 PM PDT 24
Finished Apr 15 12:38:13 PM PDT 24
Peak memory 200720 kb
Host smart-f0d98617-eee4-46e0-884d-269e841afee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169116122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4169116122
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.793978655
Short name T168
Test name
Test status
Simulation time 119159584 ps
CPU time 1.17 seconds
Started Apr 15 12:38:12 PM PDT 24
Finished Apr 15 12:38:14 PM PDT 24
Peak memory 200916 kb
Host smart-823226b7-8fda-4ac2-9146-f9b4a7a84971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793978655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.793978655
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3183545232
Short name T232
Test name
Test status
Simulation time 2616419771 ps
CPU time 11.84 seconds
Started Apr 15 12:38:11 PM PDT 24
Finished Apr 15 12:38:23 PM PDT 24
Peak memory 209296 kb
Host smart-595cd940-65a2-43f7-ae87-ee6724666c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183545232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3183545232
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.461308856
Short name T147
Test name
Test status
Simulation time 316077050 ps
CPU time 2.08 seconds
Started Apr 15 12:38:13 PM PDT 24
Finished Apr 15 12:38:16 PM PDT 24
Peak memory 209044 kb
Host smart-d85d33aa-14a1-4122-9c5a-10ef19589b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461308856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.461308856
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.4213192051
Short name T410
Test name
Test status
Simulation time 67943242 ps
CPU time 0.82 seconds
Started Apr 15 12:38:13 PM PDT 24
Finished Apr 15 12:38:14 PM PDT 24
Peak memory 200812 kb
Host smart-75830a0d-86bf-43e6-9e5d-ca202bdad00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213192051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.4213192051
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3335980367
Short name T432
Test name
Test status
Simulation time 65329649 ps
CPU time 0.76 seconds
Started Apr 15 12:38:15 PM PDT 24
Finished Apr 15 12:38:16 PM PDT 24
Peak memory 200576 kb
Host smart-e693b4b4-4ccd-4d82-a9a9-747dc5d8a9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335980367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3335980367
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.457554658
Short name T63
Test name
Test status
Simulation time 1234340825 ps
CPU time 5.37 seconds
Started Apr 15 12:38:16 PM PDT 24
Finished Apr 15 12:38:21 PM PDT 24
Peak memory 218100 kb
Host smart-31f1f0a7-83f6-42f9-9b56-3236488b7780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457554658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.457554658
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1029326297
Short name T349
Test name
Test status
Simulation time 119165205 ps
CPU time 0.8 seconds
Started Apr 15 12:38:20 PM PDT 24
Finished Apr 15 12:38:22 PM PDT 24
Peak memory 200620 kb
Host smart-fb1b66b2-d118-4628-b324-197a94c594dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029326297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1029326297
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2715270023
Short name T165
Test name
Test status
Simulation time 935750189 ps
CPU time 4.52 seconds
Started Apr 15 12:38:10 PM PDT 24
Finished Apr 15 12:38:15 PM PDT 24
Peak memory 200964 kb
Host smart-8228fab9-6d7b-4b04-8970-e0bc64d1d47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715270023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2715270023
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1970271087
Short name T33
Test name
Test status
Simulation time 179324011 ps
CPU time 1.29 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:23 PM PDT 24
Peak memory 200808 kb
Host smart-a65642a0-5629-45db-8506-58e5275bc147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970271087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1970271087
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.467395740
Short name T264
Test name
Test status
Simulation time 191859752 ps
CPU time 1.32 seconds
Started Apr 15 12:38:15 PM PDT 24
Finished Apr 15 12:38:17 PM PDT 24
Peak memory 200960 kb
Host smart-42087efd-6c1a-49b3-87d6-9ab5b59d3cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467395740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.467395740
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2475507081
Short name T58
Test name
Test status
Simulation time 1789335890 ps
CPU time 6.34 seconds
Started Apr 15 12:38:16 PM PDT 24
Finished Apr 15 12:38:23 PM PDT 24
Peak memory 201056 kb
Host smart-4887b27d-faba-433d-82ef-748a0f24f939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475507081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2475507081
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1604365358
Short name T51
Test name
Test status
Simulation time 277024072 ps
CPU time 1.86 seconds
Started Apr 15 12:38:12 PM PDT 24
Finished Apr 15 12:38:14 PM PDT 24
Peak memory 200740 kb
Host smart-33fc1972-18d3-42c5-87d9-05fdb030f7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604365358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1604365358
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2610954568
Short name T508
Test name
Test status
Simulation time 144077361 ps
CPU time 1.25 seconds
Started Apr 15 12:38:11 PM PDT 24
Finished Apr 15 12:38:12 PM PDT 24
Peak memory 200792 kb
Host smart-7af531b6-cea9-4e64-858f-7535fc9595f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610954568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2610954568
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3870777875
Short name T261
Test name
Test status
Simulation time 74315538 ps
CPU time 0.88 seconds
Started Apr 15 12:38:23 PM PDT 24
Finished Apr 15 12:38:24 PM PDT 24
Peak memory 200596 kb
Host smart-434358d4-fed9-430a-9c0b-68a909314c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870777875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3870777875
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.613555919
Short name T525
Test name
Test status
Simulation time 1227535408 ps
CPU time 5.78 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 217988 kb
Host smart-23bf0561-47a1-417c-bbc9-7072c938b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613555919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.613555919
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1590681434
Short name T80
Test name
Test status
Simulation time 244233885 ps
CPU time 1.2 seconds
Started Apr 15 12:38:24 PM PDT 24
Finished Apr 15 12:38:25 PM PDT 24
Peak memory 218172 kb
Host smart-22b36aec-cd33-489f-97b4-d54e823db671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590681434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1590681434
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3731439545
Short name T213
Test name
Test status
Simulation time 180112616 ps
CPU time 0.97 seconds
Started Apr 15 12:38:17 PM PDT 24
Finished Apr 15 12:38:19 PM PDT 24
Peak memory 200596 kb
Host smart-b4ca9c3c-e0f3-4302-bbcd-5499d8e77b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731439545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3731439545
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.415691643
Short name T103
Test name
Test status
Simulation time 1896634399 ps
CPU time 6.73 seconds
Started Apr 15 12:38:16 PM PDT 24
Finished Apr 15 12:38:23 PM PDT 24
Peak memory 201000 kb
Host smart-253cb0b7-3850-4572-9ab5-888b5fd45e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415691643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.415691643
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1625688402
Short name T172
Test name
Test status
Simulation time 105247690 ps
CPU time 1.06 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:23 PM PDT 24
Peak memory 200780 kb
Host smart-44e32150-f405-4e2c-8685-33e2c2f00232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625688402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1625688402
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1363806617
Short name T315
Test name
Test status
Simulation time 205190065 ps
CPU time 1.39 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:23 PM PDT 24
Peak memory 200960 kb
Host smart-d96f4fcb-d8eb-4a14-845f-061ccc68c96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363806617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1363806617
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.708538889
Short name T272
Test name
Test status
Simulation time 1147785575 ps
CPU time 6.21 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 209148 kb
Host smart-91fd27d0-1794-4b84-adba-9d0940f235e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708538889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.708538889
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2182967830
Short name T466
Test name
Test status
Simulation time 484245734 ps
CPU time 2.59 seconds
Started Apr 15 12:38:14 PM PDT 24
Finished Apr 15 12:38:17 PM PDT 24
Peak memory 200812 kb
Host smart-4fcc2d62-b064-45c0-aad4-4a48af7ed77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182967830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2182967830
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1706576620
Short name T467
Test name
Test status
Simulation time 112530486 ps
CPU time 1.05 seconds
Started Apr 15 12:38:15 PM PDT 24
Finished Apr 15 12:38:17 PM PDT 24
Peak memory 200836 kb
Host smart-37f33217-01c5-4c3b-8d6d-71fd809ca3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706576620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1706576620
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3741618945
Short name T476
Test name
Test status
Simulation time 73940475 ps
CPU time 0.76 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:27 PM PDT 24
Peak memory 200556 kb
Host smart-7e4a5a90-d4e4-40ac-9ac7-c1fb9d20f5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741618945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3741618945
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2154523113
Short name T62
Test name
Test status
Simulation time 1216506442 ps
CPU time 6.34 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 218544 kb
Host smart-b4685b49-644b-4d29-8074-1cf011553d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154523113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2154523113
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3672159157
Short name T495
Test name
Test status
Simulation time 244233215 ps
CPU time 1.03 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 218080 kb
Host smart-927b34e1-8c4d-4192-b698-38c18075fea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672159157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3672159157
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2933962555
Short name T262
Test name
Test status
Simulation time 150249007 ps
CPU time 0.92 seconds
Started Apr 15 12:38:23 PM PDT 24
Finished Apr 15 12:38:24 PM PDT 24
Peak memory 200620 kb
Host smart-72bfd561-5ad3-4761-9981-d05d3f6602c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933962555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2933962555
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.789074366
Short name T513
Test name
Test status
Simulation time 814035206 ps
CPU time 4.49 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:26 PM PDT 24
Peak memory 200956 kb
Host smart-b3e8fc93-0117-4046-a2de-84c47735a927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789074366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.789074366
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.129274500
Short name T248
Test name
Test status
Simulation time 180232768 ps
CPU time 1.19 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 200792 kb
Host smart-8a0c6480-e7eb-41f6-834d-5e4a85edbada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129274500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.129274500
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2117147515
Short name T451
Test name
Test status
Simulation time 242865816 ps
CPU time 1.53 seconds
Started Apr 15 12:38:16 PM PDT 24
Finished Apr 15 12:38:18 PM PDT 24
Peak memory 200956 kb
Host smart-d9d3e91e-5c36-4be2-a45b-ff042bd0e25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117147515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2117147515
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3430616816
Short name T342
Test name
Test status
Simulation time 2841718894 ps
CPU time 12.25 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 209232 kb
Host smart-40cc523b-acc4-4298-825b-c5f1c198a62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430616816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3430616816
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1945914653
Short name T480
Test name
Test status
Simulation time 296566878 ps
CPU time 2.03 seconds
Started Apr 15 12:38:22 PM PDT 24
Finished Apr 15 12:38:25 PM PDT 24
Peak memory 209008 kb
Host smart-2880d4cc-b0dc-48a1-b88b-995d925cbb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945914653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1945914653
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.663929855
Short name T236
Test name
Test status
Simulation time 216326948 ps
CPU time 1.37 seconds
Started Apr 15 12:38:23 PM PDT 24
Finished Apr 15 12:38:25 PM PDT 24
Peak memory 200784 kb
Host smart-a4b9d3a7-13d7-4c38-93b9-ab5a9cb56f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663929855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.663929855
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1170924517
Short name T435
Test name
Test status
Simulation time 66873504 ps
CPU time 0.75 seconds
Started Apr 15 12:38:22 PM PDT 24
Finished Apr 15 12:38:23 PM PDT 24
Peak memory 200544 kb
Host smart-d5212c26-03ef-46af-be0d-339d460bfa58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170924517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1170924517
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2196992556
Short name T374
Test name
Test status
Simulation time 245161259 ps
CPU time 1.02 seconds
Started Apr 15 12:38:23 PM PDT 24
Finished Apr 15 12:38:25 PM PDT 24
Peak memory 218148 kb
Host smart-e88f7164-91ec-4ffe-a867-6f6888bf4058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196992556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2196992556
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2890614601
Short name T18
Test name
Test status
Simulation time 143066430 ps
CPU time 0.82 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 200608 kb
Host smart-70079662-0200-41bd-b9ae-6a12961463fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890614601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2890614601
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2450966247
Short name T527
Test name
Test status
Simulation time 1519661484 ps
CPU time 5.7 seconds
Started Apr 15 12:38:22 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 201020 kb
Host smart-c14cce26-2666-407e-a869-ccc36e229042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450966247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2450966247
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.662598368
Short name T339
Test name
Test status
Simulation time 160208622 ps
CPU time 1.13 seconds
Started Apr 15 12:38:23 PM PDT 24
Finished Apr 15 12:38:25 PM PDT 24
Peak memory 200796 kb
Host smart-e46e1169-1c64-4c1f-b57c-bef40595da4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662598368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.662598368
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1831867042
Short name T279
Test name
Test status
Simulation time 232569068 ps
CPU time 1.48 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200920 kb
Host smart-ac4fd68e-fae4-4b55-a5f7-d17df78118b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831867042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1831867042
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2442250470
Short name T385
Test name
Test status
Simulation time 3945779385 ps
CPU time 13.32 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:43 PM PDT 24
Peak memory 201044 kb
Host smart-36e91a1d-6bc0-4b0d-8228-3dfbf99468a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442250470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2442250470
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.737178195
Short name T439
Test name
Test status
Simulation time 352482937 ps
CPU time 2.05 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200740 kb
Host smart-1c6260bf-5c07-4386-a717-82b6ce00a7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737178195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.737178195
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2023785010
Short name T494
Test name
Test status
Simulation time 283231708 ps
CPU time 1.46 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:24 PM PDT 24
Peak memory 200836 kb
Host smart-8f022071-8d35-49d5-b772-139866a85b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023785010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2023785010
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3076127776
Short name T270
Test name
Test status
Simulation time 92952893 ps
CPU time 0.82 seconds
Started Apr 15 12:37:46 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 200584 kb
Host smart-8dc93e30-de89-4991-b1aa-6f8d9dc30c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076127776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3076127776
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2090888153
Short name T24
Test name
Test status
Simulation time 1902621402 ps
CPU time 7.07 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:54 PM PDT 24
Peak memory 222612 kb
Host smart-38b0a269-4ccc-4245-973a-8b33db99451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090888153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2090888153
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.636300684
Short name T520
Test name
Test status
Simulation time 243871523 ps
CPU time 1.11 seconds
Started Apr 15 12:37:43 PM PDT 24
Finished Apr 15 12:37:45 PM PDT 24
Peak memory 218096 kb
Host smart-7cc4dbf8-b734-4e95-8ef8-a894fa80939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636300684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.636300684
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1371995210
Short name T20
Test name
Test status
Simulation time 99650143 ps
CPU time 0.75 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:47 PM PDT 24
Peak memory 200648 kb
Host smart-bd6147e2-5a1c-4792-82a1-4a51bf6e6472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371995210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1371995210
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2945864549
Short name T196
Test name
Test status
Simulation time 1369168962 ps
CPU time 4.89 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:51 PM PDT 24
Peak memory 201060 kb
Host smart-c4d338d7-cb78-441f-b3ac-03c03d84a935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945864549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2945864549
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2389753365
Short name T89
Test name
Test status
Simulation time 8435060189 ps
CPU time 12.64 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:38:01 PM PDT 24
Peak memory 217580 kb
Host smart-40736ce2-7c19-4322-803b-1c6bef1a3994
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389753365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2389753365
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.599968755
Short name T11
Test name
Test status
Simulation time 148022653 ps
CPU time 1.04 seconds
Started Apr 15 12:37:48 PM PDT 24
Finished Apr 15 12:37:50 PM PDT 24
Peak memory 200776 kb
Host smart-b1adfde7-9d11-4f72-905a-418b0415d879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599968755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.599968755
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2253685271
Short name T321
Test name
Test status
Simulation time 126612700 ps
CPU time 1.17 seconds
Started Apr 15 12:37:49 PM PDT 24
Finished Apr 15 12:37:52 PM PDT 24
Peak memory 200944 kb
Host smart-14f4c850-c3b0-4e24-8c2e-dbfb2d2fcc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253685271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2253685271
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2010855790
Short name T97
Test name
Test status
Simulation time 2779264312 ps
CPU time 14.1 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:38:01 PM PDT 24
Peak memory 201116 kb
Host smart-936e549d-8497-4e8a-81f9-c80cc11f1644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010855790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2010855790
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.426159826
Short name T499
Test name
Test status
Simulation time 122824681 ps
CPU time 1.55 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:48 PM PDT 24
Peak memory 200748 kb
Host smart-c9af7bb2-193a-4e60-b5bd-bbf7fb266e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426159826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.426159826
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2603627029
Short name T319
Test name
Test status
Simulation time 111273323 ps
CPU time 0.97 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:47 PM PDT 24
Peak memory 200748 kb
Host smart-000253a2-2777-4013-bca5-abde05444b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603627029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2603627029
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1672934942
Short name T259
Test name
Test status
Simulation time 79941991 ps
CPU time 0.79 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:23 PM PDT 24
Peak memory 200640 kb
Host smart-5f3a8efd-a94b-4f75-9f6a-1a93d9ec9d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672934942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1672934942
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2251545779
Short name T375
Test name
Test status
Simulation time 2181295750 ps
CPU time 8.09 seconds
Started Apr 15 12:38:19 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 222692 kb
Host smart-76681402-768c-4eaa-b9c4-07cc0d312e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251545779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2251545779
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.4008409094
Short name T282
Test name
Test status
Simulation time 244941816 ps
CPU time 1.06 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:27 PM PDT 24
Peak memory 218148 kb
Host smart-47d1b311-07a7-43c7-b66a-cdf578bbcdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008409094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.4008409094
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2700296770
Short name T284
Test name
Test status
Simulation time 208704012 ps
CPU time 0.87 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:26 PM PDT 24
Peak memory 200556 kb
Host smart-8c57b41d-c69c-4af7-9985-121106e2be96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700296770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2700296770
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3851745171
Short name T310
Test name
Test status
Simulation time 1378753043 ps
CPU time 5.76 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200928 kb
Host smart-ad27643a-f9f7-4b5c-9903-8cd1d61305ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851745171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3851745171
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.495257592
Short name T422
Test name
Test status
Simulation time 107957182 ps
CPU time 1.09 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:22 PM PDT 24
Peak memory 201020 kb
Host smart-0ded3e10-1345-4a31-8f32-282eafc389ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495257592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.495257592
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2977779715
Short name T526
Test name
Test status
Simulation time 114025917 ps
CPU time 1.15 seconds
Started Apr 15 12:38:22 PM PDT 24
Finished Apr 15 12:38:24 PM PDT 24
Peak memory 201012 kb
Host smart-29447ff6-da3f-4eb1-b58d-767464e688e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977779715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2977779715
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.4071897941
Short name T96
Test name
Test status
Simulation time 3630970487 ps
CPU time 17.23 seconds
Started Apr 15 12:38:24 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 201012 kb
Host smart-cb945535-10e3-4b66-8430-ee0d9bd1151d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071897941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4071897941
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3260182219
Short name T443
Test name
Test status
Simulation time 320585008 ps
CPU time 2.25 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200800 kb
Host smart-3c57fea4-1ade-4b9a-9b28-a72d9990d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260182219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3260182219
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.262650445
Short name T529
Test name
Test status
Simulation time 102190074 ps
CPU time 1.01 seconds
Started Apr 15 12:38:20 PM PDT 24
Finished Apr 15 12:38:21 PM PDT 24
Peak memory 200856 kb
Host smart-55f1950c-f8a2-41f5-a39f-0bd7bbd762f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262650445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.262650445
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3159540928
Short name T216
Test name
Test status
Simulation time 71246413 ps
CPU time 0.75 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:27 PM PDT 24
Peak memory 200544 kb
Host smart-dfffb0da-33e3-4d7d-91f1-62aff774563b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159540928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3159540928
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3261882743
Short name T31
Test name
Test status
Simulation time 1896870931 ps
CPU time 7.36 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 218596 kb
Host smart-0c36a048-dfc6-4ec8-a64a-cc8c69ae89a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261882743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3261882743
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.817495255
Short name T237
Test name
Test status
Simulation time 244274021 ps
CPU time 1.04 seconds
Started Apr 15 12:38:20 PM PDT 24
Finished Apr 15 12:38:21 PM PDT 24
Peak memory 218172 kb
Host smart-a73745d3-1d47-4c6b-ad79-43d0dc2a03d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817495255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.817495255
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.4104508714
Short name T265
Test name
Test status
Simulation time 180164141 ps
CPU time 0.84 seconds
Started Apr 15 12:38:20 PM PDT 24
Finished Apr 15 12:38:21 PM PDT 24
Peak memory 200648 kb
Host smart-3712dc64-beae-4545-a5cc-0b452e827efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104508714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.4104508714
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.7344769
Short name T6
Test name
Test status
Simulation time 1822001831 ps
CPU time 6.42 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 200996 kb
Host smart-217c3738-0373-41d7-8e8d-48d28fa9bf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7344769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.7344769
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2199462263
Short name T496
Test name
Test status
Simulation time 93819080 ps
CPU time 0.97 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200756 kb
Host smart-331384cc-d84a-451c-ab31-6bbca4385c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199462263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2199462263
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3609872440
Short name T207
Test name
Test status
Simulation time 195190602 ps
CPU time 1.3 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 200968 kb
Host smart-d76d8662-5011-4f47-960e-ec6a7f1fa3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609872440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3609872440
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3922012892
Short name T295
Test name
Test status
Simulation time 2006045135 ps
CPU time 9.94 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 201116 kb
Host smart-111b4720-d86a-4f5f-bf51-d9d80b65775c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922012892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3922012892
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1480696813
Short name T164
Test name
Test status
Simulation time 134409564 ps
CPU time 1.67 seconds
Started Apr 15 12:38:24 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 200772 kb
Host smart-f2bedbe4-31a5-4810-8334-404a3abb2a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480696813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1480696813
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1539585879
Short name T184
Test name
Test status
Simulation time 137200558 ps
CPU time 1.15 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:26 PM PDT 24
Peak memory 200744 kb
Host smart-2ec855c1-a0fa-4d82-8da4-00fd4222ae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539585879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1539585879
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.4090731518
Short name T518
Test name
Test status
Simulation time 1224662321 ps
CPU time 5.36 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 218600 kb
Host smart-67ec9140-494f-41ed-8436-c5d53ac7347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090731518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4090731518
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.847250102
Short name T397
Test name
Test status
Simulation time 244411214 ps
CPU time 1.11 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 218200 kb
Host smart-343dc476-5b76-4dd8-ac2e-8698df56f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847250102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.847250102
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3992546588
Short name T227
Test name
Test status
Simulation time 154233679 ps
CPU time 0.84 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200624 kb
Host smart-9b8fed82-2f4a-4f81-a8b0-6ac772307964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992546588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3992546588
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1569024337
Short name T134
Test name
Test status
Simulation time 1051340228 ps
CPU time 5.08 seconds
Started Apr 15 12:38:19 PM PDT 24
Finished Apr 15 12:38:24 PM PDT 24
Peak memory 201012 kb
Host smart-99710593-85f8-4c5c-bc6d-b8a754dfb13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569024337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1569024337
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2405685998
Short name T56
Test name
Test status
Simulation time 157827479 ps
CPU time 1.13 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:27 PM PDT 24
Peak memory 200796 kb
Host smart-b3bbb208-198b-42b2-be4c-9c62cf3d797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405685998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2405685998
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.590172617
Short name T1
Test name
Test status
Simulation time 207039430 ps
CPU time 1.37 seconds
Started Apr 15 12:38:20 PM PDT 24
Finished Apr 15 12:38:22 PM PDT 24
Peak memory 200980 kb
Host smart-ee855f5a-7cfc-4f19-98e0-e3bae0844bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590172617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.590172617
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2532505363
Short name T50
Test name
Test status
Simulation time 7946590607 ps
CPU time 28.67 seconds
Started Apr 15 12:38:24 PM PDT 24
Finished Apr 15 12:38:53 PM PDT 24
Peak memory 209204 kb
Host smart-d084282f-662f-4644-9424-c6a194758705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532505363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2532505363
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.249358832
Short name T222
Test name
Test status
Simulation time 503160067 ps
CPU time 2.53 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 200792 kb
Host smart-a873db36-603b-4977-b1f5-7f7ac9c1960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249358832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.249358832
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1057355444
Short name T94
Test name
Test status
Simulation time 138033602 ps
CPU time 1.09 seconds
Started Apr 15 12:38:19 PM PDT 24
Finished Apr 15 12:38:21 PM PDT 24
Peak memory 200836 kb
Host smart-d883d5a8-ddd2-4b7f-a2e0-2a9436034f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057355444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1057355444
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3546404227
Short name T465
Test name
Test status
Simulation time 87735244 ps
CPU time 0.8 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200668 kb
Host smart-4f4d5079-9ba4-460d-83a5-acfa287cb1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546404227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3546404227
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2875413421
Short name T215
Test name
Test status
Simulation time 1225046422 ps
CPU time 6.07 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 218636 kb
Host smart-0378090d-92e1-4688-94ef-29eb06dc63a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875413421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2875413421
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3537574541
Short name T316
Test name
Test status
Simulation time 244453477 ps
CPU time 1.11 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 218220 kb
Host smart-bbdeda25-11d3-4207-a552-a532b6172960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537574541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3537574541
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1653726346
Short name T244
Test name
Test status
Simulation time 119569021 ps
CPU time 0.77 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200640 kb
Host smart-c31a9b35-efe1-4915-8d9b-09c4b9be64b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653726346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1653726346
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3026255427
Short name T8
Test name
Test status
Simulation time 877780878 ps
CPU time 4.54 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 201020 kb
Host smart-f9a9ff21-5ce8-4fd3-8572-e4cfc14a31bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026255427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3026255427
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3969737943
Short name T186
Test name
Test status
Simulation time 99647256 ps
CPU time 1 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200808 kb
Host smart-e210c341-db80-43be-a81f-6bf24e428456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969737943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3969737943
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.4183656706
Short name T354
Test name
Test status
Simulation time 199872539 ps
CPU time 1.38 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 200956 kb
Host smart-a8906288-6926-47e5-ac00-efddb2fcdd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183656706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4183656706
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.77140765
Short name T517
Test name
Test status
Simulation time 4193981288 ps
CPU time 14.03 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 201096 kb
Host smart-4e0d460d-4898-486d-b5ef-ef28a082000e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77140765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.77140765
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.4084502309
Short name T34
Test name
Test status
Simulation time 337816568 ps
CPU time 2.28 seconds
Started Apr 15 12:38:24 PM PDT 24
Finished Apr 15 12:38:27 PM PDT 24
Peak memory 200768 kb
Host smart-c8e38022-8ab3-4d10-b732-0195bb16239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084502309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.4084502309
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2160460584
Short name T185
Test name
Test status
Simulation time 140747429 ps
CPU time 1.06 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200812 kb
Host smart-8eac6615-38c8-444f-94c3-d5eee105f419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160460584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2160460584
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3589908750
Short name T188
Test name
Test status
Simulation time 52580932 ps
CPU time 0.76 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:27 PM PDT 24
Peak memory 200676 kb
Host smart-22fa4853-d223-417e-a8e2-2fbc446af71d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589908750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3589908750
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4053516173
Short name T66
Test name
Test status
Simulation time 2363042869 ps
CPU time 7.59 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 218660 kb
Host smart-e2af1ac9-0e5b-42fa-9263-191cc0efa8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053516173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4053516173
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2635080522
Short name T504
Test name
Test status
Simulation time 246083189 ps
CPU time 1.04 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 218164 kb
Host smart-9781d8c9-6136-4d24-b174-4b5415aac5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635080522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2635080522
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1901168787
Short name T392
Test name
Test status
Simulation time 125494716 ps
CPU time 0.86 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:27 PM PDT 24
Peak memory 200644 kb
Host smart-b35c2c0f-9a28-49b7-aff4-be00139e8c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901168787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1901168787
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.201378579
Short name T462
Test name
Test status
Simulation time 1169496678 ps
CPU time 4.7 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 201056 kb
Host smart-66b5b060-eaad-45de-9d99-d6c9e2911ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201378579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.201378579
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.266059099
Short name T320
Test name
Test status
Simulation time 99572203 ps
CPU time 0.95 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 200836 kb
Host smart-8028e992-5d55-47c5-9d13-7e2e7fd8b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266059099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.266059099
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.323508347
Short name T365
Test name
Test status
Simulation time 119984595 ps
CPU time 1.19 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 200948 kb
Host smart-5810c76d-c2c6-43f6-ba71-10508914f356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323508347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.323508347
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2840266569
Short name T475
Test name
Test status
Simulation time 8675558966 ps
CPU time 31.57 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:39:03 PM PDT 24
Peak memory 209280 kb
Host smart-a22dee43-516b-4738-bc4a-721b9731f9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840266569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2840266569
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.225827826
Short name T348
Test name
Test status
Simulation time 322042306 ps
CPU time 2.16 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 200840 kb
Host smart-c369e24f-40c3-4640-9ad1-b9ef16433776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225827826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.225827826
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3385547862
Short name T383
Test name
Test status
Simulation time 193816776 ps
CPU time 1.27 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 200836 kb
Host smart-8a629973-117c-42d8-a66a-588cc56fd25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385547862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3385547862
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2900981357
Short name T159
Test name
Test status
Simulation time 77150051 ps
CPU time 0.78 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:26 PM PDT 24
Peak memory 200648 kb
Host smart-aadcb1ac-5266-4932-a9e2-63e0f7b87298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900981357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2900981357
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.222687487
Short name T327
Test name
Test status
Simulation time 2193181215 ps
CPU time 7.74 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 218204 kb
Host smart-01e937ef-7074-4227-bf5f-2bd4b736f709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222687487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.222687487
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1747852572
Short name T178
Test name
Test status
Simulation time 245026414 ps
CPU time 1.16 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 218164 kb
Host smart-2c7c7009-58e8-458a-aab3-48cb54bb0ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747852572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1747852572
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1528540337
Short name T416
Test name
Test status
Simulation time 1804669160 ps
CPU time 7.2 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 201020 kb
Host smart-6a18aac4-ae9d-4067-bb96-3f2683ff624f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528540337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1528540337
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1165373431
Short name T362
Test name
Test status
Simulation time 98147285 ps
CPU time 0.98 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 200836 kb
Host smart-c9d7e8ad-1c5e-4963-b506-a3d10fb43c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165373431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1165373431
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.497406457
Short name T70
Test name
Test status
Simulation time 122249416 ps
CPU time 1.27 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200992 kb
Host smart-692e80e0-6807-4b7c-bec9-1d6b435312e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497406457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.497406457
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2665112934
Short name T322
Test name
Test status
Simulation time 7744468584 ps
CPU time 33.85 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:39:00 PM PDT 24
Peak memory 209300 kb
Host smart-3e606367-ae9a-4663-b4f7-5bf20a7a7258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665112934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2665112934
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2999781022
Short name T40
Test name
Test status
Simulation time 113319699 ps
CPU time 1.42 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200820 kb
Host smart-6645db5f-e15e-4ab2-8ca4-7fd32a694024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999781022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2999781022
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2187587597
Short name T276
Test name
Test status
Simulation time 73531467 ps
CPU time 0.78 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200792 kb
Host smart-06bfe628-b76e-42a8-bff1-edd146bfdce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187587597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2187587597
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3406461707
Short name T468
Test name
Test status
Simulation time 71313207 ps
CPU time 0.75 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200632 kb
Host smart-ee6506a3-12a1-4559-b7a4-baa8e4ac6523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406461707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3406461707
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1431854410
Short name T303
Test name
Test status
Simulation time 1880041923 ps
CPU time 7.11 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 222608 kb
Host smart-b6f48da4-157a-4086-b279-5dce693b5087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431854410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1431854410
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2797501476
Short name T220
Test name
Test status
Simulation time 244330019 ps
CPU time 1.1 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 218196 kb
Host smart-f7b87b6d-5338-4404-812f-25e5b70296c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797501476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2797501476
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.534201643
Short name T16
Test name
Test status
Simulation time 161648868 ps
CPU time 0.83 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:27 PM PDT 24
Peak memory 200564 kb
Host smart-6559bfdc-7d3e-4f45-b738-022013c9efe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534201643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.534201643
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2233455331
Short name T38
Test name
Test status
Simulation time 1442199338 ps
CPU time 6.1 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 201020 kb
Host smart-46a43511-8b67-4b32-9c27-560007ef41e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233455331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2233455331
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.135416736
Short name T521
Test name
Test status
Simulation time 154033383 ps
CPU time 1.2 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 200832 kb
Host smart-4996e388-ae9a-4120-a896-abf1ee7faa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135416736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.135416736
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1757225118
Short name T371
Test name
Test status
Simulation time 117828529 ps
CPU time 1.22 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 201052 kb
Host smart-8c0c167d-8b4b-4210-aab8-802780d3204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757225118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1757225118
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3118212686
Short name T367
Test name
Test status
Simulation time 8859392586 ps
CPU time 40.31 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:39:09 PM PDT 24
Peak memory 201044 kb
Host smart-661c3ba2-0d90-4c74-801b-417da39ec94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118212686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3118212686
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2825491548
Short name T221
Test name
Test status
Simulation time 421083668 ps
CPU time 2.44 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 208976 kb
Host smart-e8f8c746-df77-48e6-a084-5d9dd43094f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825491548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2825491548
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1768774319
Short name T175
Test name
Test status
Simulation time 98607022 ps
CPU time 0.87 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 200792 kb
Host smart-87161705-e3f2-4159-a39c-1d1b6394209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768774319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1768774319
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1574974493
Short name T350
Test name
Test status
Simulation time 68780124 ps
CPU time 0.75 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 200676 kb
Host smart-c7a32edc-46cd-4aff-b16f-ac707eb80747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574974493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1574974493
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3604362334
Short name T231
Test name
Test status
Simulation time 1219963233 ps
CPU time 5.46 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 218620 kb
Host smart-613dc127-4453-4389-a564-887479267472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604362334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3604362334
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2243126502
Short name T249
Test name
Test status
Simulation time 244661166 ps
CPU time 1.14 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 218164 kb
Host smart-2c2ba055-d294-44aa-b8f6-05d28c822a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243126502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2243126502
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2183423512
Short name T12
Test name
Test status
Simulation time 230285817 ps
CPU time 0.91 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200656 kb
Host smart-01318af3-3521-4577-b79e-3f6ad4c64329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183423512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2183423512
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.347378852
Short name T238
Test name
Test status
Simulation time 875907955 ps
CPU time 4.7 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200984 kb
Host smart-9231d25b-3f8b-42f4-a31b-50ff27033696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347378852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.347378852
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2138754357
Short name T500
Test name
Test status
Simulation time 95319501 ps
CPU time 0.96 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 200804 kb
Host smart-1760a3da-9cc7-48fd-9550-eb2aa8be5cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138754357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2138754357
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.490445842
Short name T214
Test name
Test status
Simulation time 124913458 ps
CPU time 1.18 seconds
Started Apr 15 12:38:25 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 200960 kb
Host smart-49f77272-6d58-41fe-ac68-3e951c863b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490445842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.490445842
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2057818846
Short name T473
Test name
Test status
Simulation time 8260761580 ps
CPU time 27.55 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:38:56 PM PDT 24
Peak memory 201116 kb
Host smart-db9d1227-c35b-49d8-a0d1-0bbbfb62fd6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057818846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2057818846
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1133429789
Short name T415
Test name
Test status
Simulation time 328333195 ps
CPU time 2.15 seconds
Started Apr 15 12:38:24 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 209020 kb
Host smart-16c8d251-1941-40af-a7f3-b782b1afe5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133429789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1133429789
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1961640452
Short name T274
Test name
Test status
Simulation time 67359704 ps
CPU time 0.78 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 200752 kb
Host smart-301067da-7961-460e-9b16-a4ac69104a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961640452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1961640452
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.140008648
Short name T142
Test name
Test status
Simulation time 75904794 ps
CPU time 0.81 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:28 PM PDT 24
Peak memory 200640 kb
Host smart-46f3ccaf-6f90-471a-914f-01e78817ab70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140008648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.140008648
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3226958711
Short name T30
Test name
Test status
Simulation time 1896930052 ps
CPU time 6.94 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 218604 kb
Host smart-75d58cba-b1f3-4ad2-8090-66ae7319cc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226958711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3226958711
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2603344750
Short name T275
Test name
Test status
Simulation time 243870644 ps
CPU time 1.23 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 218156 kb
Host smart-6363335c-891d-4c52-acd8-ec430cd9b751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603344750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2603344750
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1437457638
Short name T396
Test name
Test status
Simulation time 136905597 ps
CPU time 0.84 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 200644 kb
Host smart-570414cb-f56f-4f83-afe1-ec12f1e0a649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437457638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1437457638
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3317141305
Short name T208
Test name
Test status
Simulation time 1237199592 ps
CPU time 5.77 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 200936 kb
Host smart-d767e214-cf6b-495f-b165-f82ff1f852a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317141305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3317141305
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1869997499
Short name T338
Test name
Test status
Simulation time 182525721 ps
CPU time 1.26 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200836 kb
Host smart-7e396cea-4e26-4698-a4d3-1e14ee9c1d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869997499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1869997499
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3974683234
Short name T533
Test name
Test status
Simulation time 115155477 ps
CPU time 1.18 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 201012 kb
Host smart-fde15c0e-f7a5-4533-a10a-a0468980745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974683234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3974683234
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1339588807
Short name T535
Test name
Test status
Simulation time 7989378590 ps
CPU time 29.54 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:39:01 PM PDT 24
Peak memory 209312 kb
Host smart-b5c6729f-57fc-4297-bd76-6d6bfcc6b188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339588807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1339588807
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1799194571
Short name T498
Test name
Test status
Simulation time 147870291 ps
CPU time 1.86 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200848 kb
Host smart-c269ac24-fded-4ab9-bdc3-67453ef5a7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799194571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1799194571
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.225360254
Short name T363
Test name
Test status
Simulation time 287618195 ps
CPU time 1.49 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 201052 kb
Host smart-40127522-9e14-48e6-9e53-da26bb3cdc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225360254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.225360254
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1368407093
Short name T152
Test name
Test status
Simulation time 82329852 ps
CPU time 0.8 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 199992 kb
Host smart-5ccc39ee-1877-41b5-a80e-e82b0cc6aa8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368407093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1368407093
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.381150774
Short name T401
Test name
Test status
Simulation time 1222797340 ps
CPU time 5.32 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 217820 kb
Host smart-5cf628eb-2158-4647-9f19-0be57400e4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381150774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.381150774
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.108695265
Short name T464
Test name
Test status
Simulation time 243371731 ps
CPU time 1.1 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 218304 kb
Host smart-2794fa97-4304-4219-a743-0367e377a379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108695265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.108695265
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.911800175
Short name T234
Test name
Test status
Simulation time 90489386 ps
CPU time 0.74 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200672 kb
Host smart-a27de8bb-09aa-46c6-8f17-8e1fe9d201d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911800175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.911800175
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2976322158
Short name T47
Test name
Test status
Simulation time 966240428 ps
CPU time 4.54 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 201004 kb
Host smart-e000abcd-866b-468d-9984-1d9240ac174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976322158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2976322158
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2026342268
Short name T358
Test name
Test status
Simulation time 99693589 ps
CPU time 0.97 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 200844 kb
Host smart-99631692-80aa-47e8-bc3f-c7d9e0067a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026342268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2026342268
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2504331842
Short name T201
Test name
Test status
Simulation time 250820807 ps
CPU time 1.51 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 201036 kb
Host smart-846f70de-d9e8-4712-837c-3ddd3d908087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504331842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2504331842
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.596999368
Short name T306
Test name
Test status
Simulation time 4672769857 ps
CPU time 17.74 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 208424 kb
Host smart-4013ed92-ce9c-4e34-ac4c-d20ffd43c334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596999368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.596999368
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3007577967
Short name T211
Test name
Test status
Simulation time 251740525 ps
CPU time 1.81 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200824 kb
Host smart-e1455d82-4b67-48ea-8e67-bd58198b7318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007577967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3007577967
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.849982475
Short name T364
Test name
Test status
Simulation time 97607531 ps
CPU time 0.91 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 200808 kb
Host smart-b7f7c98f-edca-4c38-b4e5-aef99550ce0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849982475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.849982475
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4034455181
Short name T263
Test name
Test status
Simulation time 62160180 ps
CPU time 0.76 seconds
Started Apr 15 12:37:48 PM PDT 24
Finished Apr 15 12:37:50 PM PDT 24
Peak memory 200640 kb
Host smart-461ef120-def5-49a3-907d-f81f3d197211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034455181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4034455181
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1810428024
Short name T511
Test name
Test status
Simulation time 1233830453 ps
CPU time 5.93 seconds
Started Apr 15 12:37:54 PM PDT 24
Finished Apr 15 12:38:00 PM PDT 24
Peak memory 217624 kb
Host smart-dda3a71d-e044-43bb-9c8d-26bd35e14935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810428024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1810428024
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2664766638
Short name T347
Test name
Test status
Simulation time 244996102 ps
CPU time 1.07 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:47 PM PDT 24
Peak memory 218144 kb
Host smart-d7d664f3-8185-4d2b-8738-3dca308f19da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664766638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2664766638
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3312478252
Short name T543
Test name
Test status
Simulation time 154822376 ps
CPU time 0.8 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 200580 kb
Host smart-60f0a6d1-c7fe-4317-967c-b82debe4abce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312478252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3312478252
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2462378757
Short name T54
Test name
Test status
Simulation time 1335369063 ps
CPU time 5.19 seconds
Started Apr 15 12:37:44 PM PDT 24
Finished Apr 15 12:37:50 PM PDT 24
Peak memory 200936 kb
Host smart-d0ecf9ec-9227-4f18-94a3-2525ee2a9734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462378757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2462378757
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.885247618
Short name T39
Test name
Test status
Simulation time 139241208 ps
CPU time 1.1 seconds
Started Apr 15 12:37:43 PM PDT 24
Finished Apr 15 12:37:45 PM PDT 24
Peak memory 201016 kb
Host smart-c7f0be6c-d34f-4f75-bacb-7f6459ddb4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885247618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.885247618
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1352173573
Short name T246
Test name
Test status
Simulation time 194873288 ps
CPU time 1.31 seconds
Started Apr 15 12:37:49 PM PDT 24
Finished Apr 15 12:37:51 PM PDT 24
Peak memory 200976 kb
Host smart-2a63aeae-6fae-43f0-b379-31a6f1e3e31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352173573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1352173573
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1841339244
Short name T419
Test name
Test status
Simulation time 116495027 ps
CPU time 1.57 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:47 PM PDT 24
Peak memory 200824 kb
Host smart-313001fd-fc9c-48a2-adc4-064a95e8e584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841339244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1841339244
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2882152479
Short name T298
Test name
Test status
Simulation time 137450787 ps
CPU time 1.17 seconds
Started Apr 15 12:37:42 PM PDT 24
Finished Apr 15 12:37:44 PM PDT 24
Peak memory 200800 kb
Host smart-d50b44c2-6b8b-42f7-85ec-f6f4d74a7f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882152479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2882152479
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1784561486
Short name T329
Test name
Test status
Simulation time 100659874 ps
CPU time 0.81 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 200652 kb
Host smart-f44f34a0-4b43-4e60-8b60-eb600fb68665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784561486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1784561486
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1615682030
Short name T445
Test name
Test status
Simulation time 2343470920 ps
CPU time 8.26 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 222480 kb
Host smart-4b70d276-085a-4237-b1c9-6c3e967706a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615682030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1615682030
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2401836108
Short name T287
Test name
Test status
Simulation time 244580436 ps
CPU time 1.16 seconds
Started Apr 15 12:38:26 PM PDT 24
Finished Apr 15 12:38:29 PM PDT 24
Peak memory 218204 kb
Host smart-ed9f146e-4cd6-49c7-8114-df66cb14471f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401836108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2401836108
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1990865041
Short name T292
Test name
Test status
Simulation time 216189858 ps
CPU time 1.02 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 200624 kb
Host smart-d52bc06e-5dcc-438d-8a28-6bb6e677f7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990865041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1990865041
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.385716445
Short name T408
Test name
Test status
Simulation time 1440869016 ps
CPU time 5.69 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:42 PM PDT 24
Peak memory 200796 kb
Host smart-5d4cddae-825c-4a0e-9876-c2c98a4a62c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385716445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.385716445
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.858268289
Short name T130
Test name
Test status
Simulation time 241940639 ps
CPU time 1.5 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 201012 kb
Host smart-5d60516f-3426-41c9-a7b8-88f4f019ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858268289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.858268289
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3195855765
Short name T290
Test name
Test status
Simulation time 8912887544 ps
CPU time 34 seconds
Started Apr 15 12:38:27 PM PDT 24
Finished Apr 15 12:39:02 PM PDT 24
Peak memory 200904 kb
Host smart-d4cfe666-74a4-4553-ae16-1bd4e5ecbfc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195855765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3195855765
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.979780450
Short name T309
Test name
Test status
Simulation time 132537305 ps
CPU time 1.59 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 208984 kb
Host smart-3030e685-8798-47d1-b050-c3899899592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979780450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.979780450
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2997033724
Short name T226
Test name
Test status
Simulation time 229691516 ps
CPU time 1.3 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 200860 kb
Host smart-8fbb5614-fff7-4971-a7cc-7f4d55c9f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997033724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2997033724
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.500142921
Short name T229
Test name
Test status
Simulation time 70207250 ps
CPU time 0.78 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 200580 kb
Host smart-d88260e3-ef6c-407c-b2a7-560db9c8ca88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500142921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.500142921
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.250700031
Short name T29
Test name
Test status
Simulation time 2341306347 ps
CPU time 8.29 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 218612 kb
Host smart-60c81eb2-de53-41e3-b4d9-51b44ed79ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250700031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.250700031
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.4061612825
Short name T187
Test name
Test status
Simulation time 244618964 ps
CPU time 1.03 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 217808 kb
Host smart-f8a5a7fe-a468-4c2e-bc47-c8b70d457244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061612825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.4061612825
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1856315106
Short name T384
Test name
Test status
Simulation time 102400347 ps
CPU time 0.77 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 200672 kb
Host smart-ea55917f-4f24-460c-8806-3e2d9ec89232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856315106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1856315106
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.10380217
Short name T336
Test name
Test status
Simulation time 1602469862 ps
CPU time 6.18 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 200988 kb
Host smart-f60f8f10-e74c-4b87-8602-75c71be873e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10380217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.10380217
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3977680024
Short name T141
Test name
Test status
Simulation time 144327079 ps
CPU time 1.11 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 200840 kb
Host smart-47096a2d-4062-43aa-9ea4-a2ce7a69abf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977680024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3977680024
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.587893214
Short name T197
Test name
Test status
Simulation time 196829462 ps
CPU time 1.37 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 201072 kb
Host smart-990977fe-9d83-4114-a603-bebc96ad28f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587893214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.587893214
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2751152742
Short name T106
Test name
Test status
Simulation time 13097174235 ps
CPU time 45.6 seconds
Started Apr 15 12:38:45 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 209260 kb
Host smart-5a835f4c-a501-4899-8710-eaeaba6dba6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751152742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2751152742
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3003163066
Short name T210
Test name
Test status
Simulation time 147578010 ps
CPU time 1.9 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200816 kb
Host smart-16a153bc-013f-44ab-b625-dca4161e6032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003163066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3003163066
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.153798754
Short name T204
Test name
Test status
Simulation time 139997807 ps
CPU time 1.03 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:30 PM PDT 24
Peak memory 200704 kb
Host smart-768c707a-e7f9-40ce-9abb-7bbf09866b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153798754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.153798754
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1734705121
Short name T277
Test name
Test status
Simulation time 79029922 ps
CPU time 0.87 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200632 kb
Host smart-ddb3721a-c100-4864-92a3-077e3c202271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734705121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1734705121
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.175096996
Short name T514
Test name
Test status
Simulation time 2353973056 ps
CPU time 8.02 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 218716 kb
Host smart-4cf7476d-b12c-4ed9-9100-fec2874606a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175096996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.175096996
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3125964662
Short name T163
Test name
Test status
Simulation time 244109900 ps
CPU time 1.07 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:31 PM PDT 24
Peak memory 218148 kb
Host smart-20f70b4e-e407-48dc-b4cb-d942d2ee8c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125964662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3125964662
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2063697116
Short name T405
Test name
Test status
Simulation time 111659690 ps
CPU time 0.83 seconds
Started Apr 15 12:38:34 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 200592 kb
Host smart-d971684d-beb8-42a0-9b4a-c48cdb748b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063697116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2063697116
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.698439825
Short name T242
Test name
Test status
Simulation time 1024366352 ps
CPU time 5 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 200988 kb
Host smart-79902b3f-eb0e-4087-a904-ba260778ad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698439825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.698439825
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.342657604
Short name T212
Test name
Test status
Simulation time 110112069 ps
CPU time 0.97 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200844 kb
Host smart-46136643-ee33-4a57-ae2d-1395aedcb9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342657604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.342657604
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1508395162
Short name T532
Test name
Test status
Simulation time 198147996 ps
CPU time 1.44 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200988 kb
Host smart-2a58ac35-eb04-47fb-ae9d-98b2124fcf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508395162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1508395162
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2492547624
Short name T483
Test name
Test status
Simulation time 4818531922 ps
CPU time 21.1 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:54 PM PDT 24
Peak memory 200812 kb
Host smart-b775d2ca-1fad-4c65-aac2-acf02f8ff7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492547624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2492547624
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3296468542
Short name T225
Test name
Test status
Simulation time 151940581 ps
CPU time 1.91 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200824 kb
Host smart-241f4bca-0d90-4842-8a34-0f8b69c7a610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296468542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3296468542
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.4063164256
Short name T36
Test name
Test status
Simulation time 144331938 ps
CPU time 1.07 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 200836 kb
Host smart-9bb55730-f41e-478e-8d2b-855dc550c261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063164256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.4063164256
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.4252024964
Short name T406
Test name
Test status
Simulation time 68331098 ps
CPU time 0.74 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 200568 kb
Host smart-6971aac1-eb6d-4d8d-ac68-6f5f88986973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252024964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.4252024964
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.733611744
Short name T539
Test name
Test status
Simulation time 243493831 ps
CPU time 1.13 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 218284 kb
Host smart-4f3055bd-9f4a-4369-b61f-e9df1fee104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733611744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.733611744
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1332683491
Short name T17
Test name
Test status
Simulation time 233273610 ps
CPU time 0.93 seconds
Started Apr 15 12:38:38 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 200620 kb
Host smart-9ecb7deb-6973-4451-b5f4-0b38191b8ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332683491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1332683491
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.953175041
Short name T343
Test name
Test status
Simulation time 1523876465 ps
CPU time 5.71 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 200996 kb
Host smart-746cf31a-b383-4b71-ac0c-4ca66e18b31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953175041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.953175041
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3447752824
Short name T507
Test name
Test status
Simulation time 162695347 ps
CPU time 1.21 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 200856 kb
Host smart-7b841819-2577-40d7-bcdf-f703b8c017b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447752824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3447752824
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.194548044
Short name T203
Test name
Test status
Simulation time 202069677 ps
CPU time 1.35 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200948 kb
Host smart-65e7db82-530a-46bd-9c27-ff9743a0d613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194548044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.194548044
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1790687781
Short name T128
Test name
Test status
Simulation time 3298855402 ps
CPU time 11.15 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 210276 kb
Host smart-e38b8642-5660-46ae-b8d6-c7acee1db765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790687781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1790687781
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1517406603
Short name T224
Test name
Test status
Simulation time 410489652 ps
CPU time 2.39 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 200848 kb
Host smart-ee256215-67a1-42a1-9a84-a725d572c590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517406603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1517406603
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3589128433
Short name T433
Test name
Test status
Simulation time 140745752 ps
CPU time 1.06 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200828 kb
Host smart-5adc45be-5053-4eeb-b41f-625a6c2bd39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589128433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3589128433
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2397759974
Short name T448
Test name
Test status
Simulation time 54954127 ps
CPU time 0.72 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:44 PM PDT 24
Peak memory 200572 kb
Host smart-94033d12-5fab-473d-b6cd-eb574194ef20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397759974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2397759974
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.840249916
Short name T426
Test name
Test status
Simulation time 2379340008 ps
CPU time 7.7 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 222596 kb
Host smart-4f348126-e63b-46ef-bdc2-3251c7ed20a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840249916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.840249916
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2091107593
Short name T209
Test name
Test status
Simulation time 244611976 ps
CPU time 1.05 seconds
Started Apr 15 12:38:49 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 218108 kb
Host smart-174c30d7-bcdd-481b-9e1e-bb3e405e17a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091107593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2091107593
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3399786910
Short name T304
Test name
Test status
Simulation time 168245151 ps
CPU time 0.84 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 200648 kb
Host smart-e385d9e3-ded1-4e34-a395-d3ac832ca55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399786910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3399786910
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.83412193
Short name T394
Test name
Test status
Simulation time 1209296647 ps
CPU time 5.16 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 201020 kb
Host smart-9a5713d5-9c12-4d94-80bd-3259ff333c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83412193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.83412193
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3918228722
Short name T458
Test name
Test status
Simulation time 148366228 ps
CPU time 1.17 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 200832 kb
Host smart-76b33142-2899-420a-a5a7-958355143dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918228722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3918228722
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3096991546
Short name T69
Test name
Test status
Simulation time 191204544 ps
CPU time 1.33 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 201012 kb
Host smart-1f0e7d98-b223-4cf6-b9c9-ead2418a13a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096991546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3096991546
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3675513270
Short name T230
Test name
Test status
Simulation time 9393238356 ps
CPU time 34.39 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:39:07 PM PDT 24
Peak memory 208920 kb
Host smart-1c3589aa-c018-42b9-848d-89ab763d65ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675513270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3675513270
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.279136237
Short name T217
Test name
Test status
Simulation time 142815546 ps
CPU time 1.77 seconds
Started Apr 15 12:38:38 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 200788 kb
Host smart-23afb440-9c13-40c1-b09e-9c0b39e2b559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279136237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.279136237
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.4274958629
Short name T194
Test name
Test status
Simulation time 139415809 ps
CPU time 1.09 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 200308 kb
Host smart-de6bad92-286d-4c51-9515-698303f9c153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274958629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4274958629
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1250393326
Short name T453
Test name
Test status
Simulation time 91359611 ps
CPU time 0.85 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 200624 kb
Host smart-8d97b9fa-f2a5-4bb7-a0ae-5cf2fdf4b565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250393326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1250393326
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2188164171
Short name T68
Test name
Test status
Simulation time 1231335660 ps
CPU time 5.29 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 218680 kb
Host smart-a08c01d1-3377-40e1-8578-d07591749cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188164171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2188164171
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3490460797
Short name T193
Test name
Test status
Simulation time 243440280 ps
CPU time 1.08 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 218040 kb
Host smart-974a4540-a407-48ff-b3b1-5878b0c5c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490460797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3490460797
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.787547697
Short name T361
Test name
Test status
Simulation time 210702065 ps
CPU time 0.85 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 200604 kb
Host smart-40cb7438-b00f-46aa-9a58-a9226ba54bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787547697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.787547697
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1123895503
Short name T409
Test name
Test status
Simulation time 860952902 ps
CPU time 4.36 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:43 PM PDT 24
Peak memory 200920 kb
Host smart-a5fdbf0a-4d92-4b72-8817-5533e7f554c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123895503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1123895503
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.672065138
Short name T411
Test name
Test status
Simulation time 151867617 ps
CPU time 1.16 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 200828 kb
Host smart-d88cbebf-2481-4250-88ff-5a29aca90937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672065138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.672065138
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2268488083
Short name T308
Test name
Test status
Simulation time 192443052 ps
CPU time 1.37 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 201040 kb
Host smart-05d368f3-806b-441e-8db9-8386e595d670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268488083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2268488083
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.495355384
Short name T519
Test name
Test status
Simulation time 17836514101 ps
CPU time 56.18 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 209316 kb
Host smart-1b053b1a-5f6f-490a-9106-f40cc1998f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495355384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.495355384
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1432678268
Short name T49
Test name
Test status
Simulation time 414027690 ps
CPU time 2.19 seconds
Started Apr 15 12:38:28 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 209008 kb
Host smart-1f3d5f73-f380-4aaa-8ac9-e1680c04100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432678268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1432678268
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1204426252
Short name T219
Test name
Test status
Simulation time 78607678 ps
CPU time 0.83 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 200796 kb
Host smart-f1ab6be1-84fc-447d-ad6e-e3df6d1cb527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204426252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1204426252
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2582561649
Short name T300
Test name
Test status
Simulation time 77193006 ps
CPU time 0.8 seconds
Started Apr 15 12:38:38 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 200600 kb
Host smart-04b44e13-0506-411c-8c25-6d9a1a013e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582561649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2582561649
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.909920465
Short name T23
Test name
Test status
Simulation time 1223370565 ps
CPU time 5.93 seconds
Started Apr 15 12:38:36 PM PDT 24
Finished Apr 15 12:38:43 PM PDT 24
Peak memory 218144 kb
Host smart-01f050d3-894c-40ea-b1d4-de8884438e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909920465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.909920465
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1314051607
Short name T82
Test name
Test status
Simulation time 244489594 ps
CPU time 1.1 seconds
Started Apr 15 12:38:42 PM PDT 24
Finished Apr 15 12:38:43 PM PDT 24
Peak memory 218088 kb
Host smart-3a05d21b-ee63-4612-86dc-18953ad13631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314051607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1314051607
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.77774191
Short name T540
Test name
Test status
Simulation time 194412619 ps
CPU time 0.93 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 200580 kb
Host smart-16d1ac77-8550-4bfe-b83e-0e7b925ed7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77774191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.77774191
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1483572991
Short name T200
Test name
Test status
Simulation time 793069923 ps
CPU time 4.27 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 201016 kb
Host smart-8fe1b496-7b57-4885-8387-a7385fbc06f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483572991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1483572991
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.312515514
Short name T162
Test name
Test status
Simulation time 178909480 ps
CPU time 1.14 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:33 PM PDT 24
Peak memory 200864 kb
Host smart-c30dd464-bf60-4265-aefd-ca82190a68a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312515514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.312515514
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1505997004
Short name T156
Test name
Test status
Simulation time 108563483 ps
CPU time 1.11 seconds
Started Apr 15 12:38:43 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 200980 kb
Host smart-a3738168-f2b6-4faa-a8cf-871648ade2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505997004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1505997004
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.341209524
Short name T199
Test name
Test status
Simulation time 3387602146 ps
CPU time 15.79 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:53 PM PDT 24
Peak memory 209100 kb
Host smart-a4197199-e7f7-4640-a051-d0c7c1e97e43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341209524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.341209524
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1465317381
Short name T311
Test name
Test status
Simulation time 143414479 ps
CPU time 1.84 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 200824 kb
Host smart-3717ce94-d2da-4eeb-87b0-a77e73771150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465317381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1465317381
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1670217973
Short name T258
Test name
Test status
Simulation time 94080645 ps
CPU time 0.88 seconds
Started Apr 15 12:38:34 PM PDT 24
Finished Apr 15 12:38:36 PM PDT 24
Peak memory 200748 kb
Host smart-6e8e2a08-556d-41f3-8394-784df0759377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670217973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1670217973
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2399727680
Short name T171
Test name
Test status
Simulation time 77122064 ps
CPU time 0.75 seconds
Started Apr 15 12:38:49 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 200296 kb
Host smart-00587ef2-19e3-4df3-aee8-b29d72fdc077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399727680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2399727680
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.269344804
Short name T65
Test name
Test status
Simulation time 1228370721 ps
CPU time 5.42 seconds
Started Apr 15 12:38:34 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 218596 kb
Host smart-d9c42644-25a1-4ed5-b8d9-7097eb3cfda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269344804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.269344804
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.964344276
Short name T240
Test name
Test status
Simulation time 243481973 ps
CPU time 1.07 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 218176 kb
Host smart-4152b207-aa51-4ad5-8ef3-50eb7034d225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964344276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.964344276
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1936146768
Short name T286
Test name
Test status
Simulation time 151485982 ps
CPU time 0.82 seconds
Started Apr 15 12:38:34 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 200584 kb
Host smart-502dffa5-2aef-471b-96a2-b3f38615d0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936146768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1936146768
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3947142881
Short name T218
Test name
Test status
Simulation time 1114160281 ps
CPU time 4.8 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:43 PM PDT 24
Peak memory 200964 kb
Host smart-d0e2e911-f75f-47b8-a329-ea9e3809701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947142881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3947142881
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2938174747
Short name T301
Test name
Test status
Simulation time 153822026 ps
CPU time 1.12 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 200796 kb
Host smart-c24b0e5f-cda3-47ac-92df-394b0c241184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938174747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2938174747
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.929639128
Short name T98
Test name
Test status
Simulation time 128081930 ps
CPU time 1.23 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 201004 kb
Host smart-4b86f8ee-b4fa-4812-abe0-128bf591378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929639128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.929639128
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.738420031
Short name T459
Test name
Test status
Simulation time 3151172080 ps
CPU time 11.4 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:48 PM PDT 24
Peak memory 209276 kb
Host smart-ffbbbf2d-1127-4e0a-9dfc-2053b906f406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738420031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.738420031
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2374715168
Short name T524
Test name
Test status
Simulation time 154737083 ps
CPU time 1.84 seconds
Started Apr 15 12:38:34 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 200780 kb
Host smart-05847545-aa25-4b36-ad61-a3894f4743c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374715168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2374715168
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1769379595
Short name T3
Test name
Test status
Simulation time 171831111 ps
CPU time 1.29 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:34 PM PDT 24
Peak memory 200968 kb
Host smart-8707ffbb-699b-4ca1-bb9e-1d9d32b76e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769379595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1769379595
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.384288194
Short name T160
Test name
Test status
Simulation time 78701924 ps
CPU time 0.83 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 200644 kb
Host smart-00b23712-6004-4a96-b62b-7a68b504c815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384288194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.384288194
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3322930926
Short name T26
Test name
Test status
Simulation time 1232498522 ps
CPU time 5.55 seconds
Started Apr 15 12:38:30 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 218644 kb
Host smart-519d6d57-f6d2-42a4-89c4-34c42aac9e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322930926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3322930926
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2007379922
Short name T145
Test name
Test status
Simulation time 245119996 ps
CPU time 1.12 seconds
Started Apr 15 12:38:34 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 218076 kb
Host smart-e65394ad-8203-423f-ae41-ddb2b3a59521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007379922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2007379922
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.883949102
Short name T440
Test name
Test status
Simulation time 107203757 ps
CPU time 0.82 seconds
Started Apr 15 12:38:44 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 200632 kb
Host smart-7ea2bc5b-6e8e-4e89-976b-5dd039087935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883949102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.883949102
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.257448608
Short name T393
Test name
Test status
Simulation time 881129353 ps
CPU time 4.55 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 201016 kb
Host smart-f0fc888c-c7a0-44ba-a1ec-631bcdfbba59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257448608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.257448608
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.579836691
Short name T305
Test name
Test status
Simulation time 95026281 ps
CPU time 0.97 seconds
Started Apr 15 12:38:43 PM PDT 24
Finished Apr 15 12:38:50 PM PDT 24
Peak memory 200824 kb
Host smart-6479ebbc-e087-4d84-abc9-c5c77a8be97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579836691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.579836691
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1106341158
Short name T335
Test name
Test status
Simulation time 106406946 ps
CPU time 1.11 seconds
Started Apr 15 12:38:49 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 200672 kb
Host smart-86d431b9-810c-4f36-8e48-43297a00b172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106341158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1106341158
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.325890633
Short name T357
Test name
Test status
Simulation time 4815452079 ps
CPU time 15.5 seconds
Started Apr 15 12:38:31 PM PDT 24
Finished Apr 15 12:38:49 PM PDT 24
Peak memory 201036 kb
Host smart-c4a194d7-dd87-4dbb-93d3-5be954df53e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325890633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.325890633
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.979255966
Short name T281
Test name
Test status
Simulation time 122040699 ps
CPU time 1.51 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 208948 kb
Host smart-4ca8c1fa-314f-4dba-8271-d589ec1e7258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979255966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.979255966
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3805721422
Short name T179
Test name
Test status
Simulation time 138647271 ps
CPU time 1.17 seconds
Started Apr 15 12:38:29 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 200704 kb
Host smart-5d1a505a-9b6b-4a10-b1ac-5f638c6ca463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805721422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3805721422
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1236767642
Short name T421
Test name
Test status
Simulation time 84025208 ps
CPU time 0.87 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 200580 kb
Host smart-2ae80be5-8f7f-4d14-b53d-47e01f97bdc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236767642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1236767642
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4262473933
Short name T64
Test name
Test status
Simulation time 1217329285 ps
CPU time 5.68 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:44 PM PDT 24
Peak memory 217580 kb
Host smart-5c4e2200-0ec2-4301-8d33-0ea1e1fe77ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262473933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4262473933
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3396882901
Short name T254
Test name
Test status
Simulation time 244417707 ps
CPU time 1.1 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 218156 kb
Host smart-407ef496-5fd0-4952-afe3-1db193bef93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396882901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3396882901
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2679172440
Short name T14
Test name
Test status
Simulation time 166905363 ps
CPU time 0.84 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 200668 kb
Host smart-bd084644-7f18-4d0a-9ad5-3cc757b5343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679172440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2679172440
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2450332725
Short name T129
Test name
Test status
Simulation time 1694035881 ps
CPU time 6.03 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:44 PM PDT 24
Peak memory 201004 kb
Host smart-826b37d9-1b4e-46a6-b0a5-52f8049aeaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450332725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2450332725
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2959361283
Short name T431
Test name
Test status
Simulation time 160285904 ps
CPU time 1.12 seconds
Started Apr 15 12:38:42 PM PDT 24
Finished Apr 15 12:38:44 PM PDT 24
Peak memory 200844 kb
Host smart-150c01c0-7aaa-4c35-8247-8b613681e693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959361283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2959361283
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3085903002
Short name T490
Test name
Test status
Simulation time 197528469 ps
CPU time 1.4 seconds
Started Apr 15 12:38:32 PM PDT 24
Finished Apr 15 12:38:35 PM PDT 24
Peak memory 201072 kb
Host smart-6e190f12-57e5-4dc6-adf9-06fff28ad739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085903002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3085903002
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2510785034
Short name T334
Test name
Test status
Simulation time 214907379 ps
CPU time 1.31 seconds
Started Apr 15 12:38:42 PM PDT 24
Finished Apr 15 12:38:44 PM PDT 24
Peak memory 201000 kb
Host smart-68dc82ea-3b43-4ba4-b6fe-067a31645817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510785034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2510785034
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3340156840
Short name T515
Test name
Test status
Simulation time 494073688 ps
CPU time 2.47 seconds
Started Apr 15 12:38:44 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 200780 kb
Host smart-9a97e700-fc3c-4cc1-9200-376be1512d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340156840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3340156840
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.261155392
Short name T153
Test name
Test status
Simulation time 109120799 ps
CPU time 1.09 seconds
Started Apr 15 12:38:36 PM PDT 24
Finished Apr 15 12:38:38 PM PDT 24
Peak memory 200860 kb
Host smart-94d50811-484d-4cf0-a108-4082363563ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261155392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.261155392
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2164323995
Short name T87
Test name
Test status
Simulation time 54121551 ps
CPU time 0.78 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:47 PM PDT 24
Peak memory 200576 kb
Host smart-ce14b967-5f36-4665-8a5f-c3d9ff8729d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164323995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2164323995
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3048550150
Short name T239
Test name
Test status
Simulation time 1221463066 ps
CPU time 5.26 seconds
Started Apr 15 12:37:50 PM PDT 24
Finished Apr 15 12:37:56 PM PDT 24
Peak memory 217580 kb
Host smart-2e4e0022-0080-492a-9edb-dc05dfbeb1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048550150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3048550150
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3581583514
Short name T267
Test name
Test status
Simulation time 243947078 ps
CPU time 1.11 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:37:50 PM PDT 24
Peak memory 218196 kb
Host smart-43beede7-ba51-4d96-bc6b-00e108cd92ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581583514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3581583514
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.783698409
Short name T15
Test name
Test status
Simulation time 106318265 ps
CPU time 0.77 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 200668 kb
Host smart-dd855db9-b9cc-4eeb-abf8-021c88aec2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783698409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.783698409
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2203163215
Short name T471
Test name
Test status
Simulation time 1486992540 ps
CPU time 5.95 seconds
Started Apr 15 12:37:46 PM PDT 24
Finished Apr 15 12:37:53 PM PDT 24
Peak memory 200960 kb
Host smart-6bd4051d-c567-4e86-b28b-f434d84f7338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203163215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2203163215
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.741573866
Short name T84
Test name
Test status
Simulation time 8397186461 ps
CPU time 12.9 seconds
Started Apr 15 12:37:48 PM PDT 24
Finished Apr 15 12:38:02 PM PDT 24
Peak memory 221640 kb
Host smart-239044ba-36b9-49e6-9a1f-b449596c73a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741573866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.741573866
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1677156283
Short name T288
Test name
Test status
Simulation time 146536028 ps
CPU time 1.09 seconds
Started Apr 15 12:37:42 PM PDT 24
Finished Apr 15 12:37:44 PM PDT 24
Peak memory 200716 kb
Host smart-0bd98e75-0394-4e39-b2ba-2294fa90ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677156283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1677156283
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.632210121
Short name T245
Test name
Test status
Simulation time 113068715 ps
CPU time 1.21 seconds
Started Apr 15 12:37:48 PM PDT 24
Finished Apr 15 12:37:51 PM PDT 24
Peak memory 200992 kb
Host smart-a73b3fd7-f8fd-4019-b32d-bd572e31ba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632210121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.632210121
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2328184052
Short name T326
Test name
Test status
Simulation time 2389054400 ps
CPU time 10.85 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:57 PM PDT 24
Peak memory 209288 kb
Host smart-73dc42c5-511e-49ae-942a-26cf7a1e7971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328184052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2328184052
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.660444269
Short name T368
Test name
Test status
Simulation time 482116936 ps
CPU time 2.85 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 200832 kb
Host smart-5f7d9137-ea53-4468-b04f-cf3363973925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660444269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.660444269
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3120557448
Short name T485
Test name
Test status
Simulation time 167080323 ps
CPU time 1.11 seconds
Started Apr 15 12:37:42 PM PDT 24
Finished Apr 15 12:37:44 PM PDT 24
Peak memory 200792 kb
Host smart-245af1ca-36ee-482a-bb3b-ec8176e46ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120557448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3120557448
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2368622267
Short name T291
Test name
Test status
Simulation time 77076296 ps
CPU time 0.8 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 200648 kb
Host smart-28680cf8-7190-47c8-81e3-6cac3562c16e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368622267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2368622267
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.118384122
Short name T461
Test name
Test status
Simulation time 1896667802 ps
CPU time 6.83 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 222604 kb
Host smart-2edb77af-b563-45b8-a9ce-1e44644d4bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118384122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.118384122
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3604289460
Short name T509
Test name
Test status
Simulation time 244318559 ps
CPU time 1.08 seconds
Started Apr 15 12:38:35 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 218296 kb
Host smart-edc4f370-607b-48ee-9181-b91266ecda46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604289460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3604289460
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3149873179
Short name T183
Test name
Test status
Simulation time 173583105 ps
CPU time 0.86 seconds
Started Apr 15 12:38:42 PM PDT 24
Finished Apr 15 12:38:44 PM PDT 24
Peak memory 200600 kb
Host smart-aaf992d4-2346-497e-9334-4d68ff74ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149873179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3149873179
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1248582784
Short name T381
Test name
Test status
Simulation time 1153080064 ps
CPU time 5.47 seconds
Started Apr 15 12:38:38 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 201052 kb
Host smart-0e0dbe97-39ef-4569-bc72-3695e4348f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248582784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1248582784
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.20246977
Short name T266
Test name
Test status
Simulation time 105119956 ps
CPU time 1.03 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 201020 kb
Host smart-8543c9eb-c73a-48e1-9dbd-d07fe3ff7bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20246977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.20246977
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1446560259
Short name T537
Test name
Test status
Simulation time 196744571 ps
CPU time 1.38 seconds
Started Apr 15 12:38:39 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 201016 kb
Host smart-f9a8650f-5f0a-4fa3-ae35-f2c3a5c6960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446560259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1446560259
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1249829200
Short name T522
Test name
Test status
Simulation time 2034669483 ps
CPU time 7.54 seconds
Started Apr 15 12:38:36 PM PDT 24
Finished Apr 15 12:38:44 PM PDT 24
Peak memory 200948 kb
Host smart-ed766a7b-f313-4218-b642-cf00b7849dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249829200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1249829200
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1356419704
Short name T400
Test name
Test status
Simulation time 337709423 ps
CPU time 1.98 seconds
Started Apr 15 12:38:36 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 200736 kb
Host smart-4b709045-0130-40fd-8655-59622c4eb049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356419704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1356419704
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4227317785
Short name T505
Test name
Test status
Simulation time 245865699 ps
CPU time 1.49 seconds
Started Apr 15 12:38:39 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 200988 kb
Host smart-d276cc79-790c-4a09-84ee-f3c427b4b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227317785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4227317785
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.391533700
Short name T85
Test name
Test status
Simulation time 55241736 ps
CPU time 0.72 seconds
Started Apr 15 12:38:38 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 200528 kb
Host smart-71f0c277-aeb2-4611-b3cb-32170ec194c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391533700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.391533700
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.4079465158
Short name T35
Test name
Test status
Simulation time 1224168565 ps
CPU time 5.84 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:44 PM PDT 24
Peak memory 218640 kb
Host smart-7a5d9ed7-2029-44c4-90de-a878cb0d9e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079465158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.4079465158
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3512830800
Short name T516
Test name
Test status
Simulation time 244862704 ps
CPU time 1.09 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 218148 kb
Host smart-db56cdb7-8014-43d0-ac95-b482bd036bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512830800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3512830800
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.138385687
Short name T523
Test name
Test status
Simulation time 196735930 ps
CPU time 1 seconds
Started Apr 15 12:38:40 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 200640 kb
Host smart-fee369cf-f105-40fa-9ab8-225bc773c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138385687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.138385687
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.542718165
Short name T356
Test name
Test status
Simulation time 1030913340 ps
CPU time 4.66 seconds
Started Apr 15 12:38:39 PM PDT 24
Finished Apr 15 12:38:44 PM PDT 24
Peak memory 200768 kb
Host smart-0902cabd-e392-417e-b4f3-12fb9f41b02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542718165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.542718165
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2922446485
Short name T22
Test name
Test status
Simulation time 100707566 ps
CPU time 1 seconds
Started Apr 15 12:38:45 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 200816 kb
Host smart-87661c02-f083-42e3-a46c-e0fa9af704dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922446485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2922446485
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.341136695
Short name T340
Test name
Test status
Simulation time 232574982 ps
CPU time 1.41 seconds
Started Apr 15 12:38:40 PM PDT 24
Finished Apr 15 12:38:42 PM PDT 24
Peak memory 200992 kb
Host smart-71ea2b32-2e4d-42bc-8edd-59a3b8db7b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341136695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.341136695
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2167415391
Short name T359
Test name
Test status
Simulation time 2074131041 ps
CPU time 7.75 seconds
Started Apr 15 12:38:41 PM PDT 24
Finished Apr 15 12:38:55 PM PDT 24
Peak memory 209536 kb
Host smart-a0ee3996-1afc-46d7-9afd-e23ebaaf6838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167415391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2167415391
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.615005361
Short name T71
Test name
Test status
Simulation time 516456193 ps
CPU time 3 seconds
Started Apr 15 12:38:45 PM PDT 24
Finished Apr 15 12:38:48 PM PDT 24
Peak memory 200784 kb
Host smart-5d15762e-67ac-420e-a4e6-c49386ec7acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615005361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.615005361
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.4173277571
Short name T131
Test name
Test status
Simulation time 91318395 ps
CPU time 0.85 seconds
Started Apr 15 12:38:44 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 200840 kb
Host smart-ded8f30e-354a-439c-ab95-19a6364fdbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173277571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.4173277571
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.858601546
Short name T389
Test name
Test status
Simulation time 79291188 ps
CPU time 0.75 seconds
Started Apr 15 12:38:42 PM PDT 24
Finished Apr 15 12:38:43 PM PDT 24
Peak memory 200620 kb
Host smart-8e2ab9a0-799e-457c-9d4b-d44e485156d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858601546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.858601546
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1000117594
Short name T382
Test name
Test status
Simulation time 1233454681 ps
CPU time 6.1 seconds
Started Apr 15 12:38:45 PM PDT 24
Finished Apr 15 12:38:52 PM PDT 24
Peak memory 230412 kb
Host smart-4e565471-2b42-447f-93e7-b41fd754079e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000117594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1000117594
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2560870564
Short name T493
Test name
Test status
Simulation time 246494804 ps
CPU time 1.02 seconds
Started Apr 15 12:38:34 PM PDT 24
Finished Apr 15 12:38:37 PM PDT 24
Peak memory 218156 kb
Host smart-cc628dca-946e-49f3-bcc9-b1d7bb491e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560870564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2560870564
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1553462283
Short name T241
Test name
Test status
Simulation time 95987987 ps
CPU time 0.77 seconds
Started Apr 15 12:38:39 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 200340 kb
Host smart-aacda6ab-6327-4882-b24d-861510f947c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553462283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1553462283
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3566566687
Short name T413
Test name
Test status
Simulation time 899254499 ps
CPU time 4.45 seconds
Started Apr 15 12:38:44 PM PDT 24
Finished Apr 15 12:38:50 PM PDT 24
Peak memory 201028 kb
Host smart-7d6209d9-a3f7-4eab-b3fe-2a07a15c8cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566566687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3566566687
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.271615028
Short name T538
Test name
Test status
Simulation time 97982250 ps
CPU time 0.97 seconds
Started Apr 15 12:38:40 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 200840 kb
Host smart-9d438ad5-3cf0-433b-89d5-830d3b6e5cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271615028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.271615028
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.285804328
Short name T148
Test name
Test status
Simulation time 202328902 ps
CPU time 1.41 seconds
Started Apr 15 12:38:38 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 201016 kb
Host smart-167f6d4c-51f1-4ca8-940f-dbfae8fd7b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285804328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.285804328
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2763425638
Short name T390
Test name
Test status
Simulation time 3621765250 ps
CPU time 12.81 seconds
Started Apr 15 12:38:33 PM PDT 24
Finished Apr 15 12:38:48 PM PDT 24
Peak memory 201032 kb
Host smart-a0ccc127-9a7e-4a63-b5c0-3ddc62c86657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763425638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2763425638
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1471532271
Short name T531
Test name
Test status
Simulation time 121320319 ps
CPU time 1.51 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 200772 kb
Host smart-a52cea28-4990-40ca-8c90-26ac37cf68e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471532271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1471532271
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1338358324
Short name T169
Test name
Test status
Simulation time 98743201 ps
CPU time 0.93 seconds
Started Apr 15 12:38:38 PM PDT 24
Finished Apr 15 12:38:40 PM PDT 24
Peak memory 200796 kb
Host smart-f3353395-0225-404f-a1d9-e74f5767ba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338358324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1338358324
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.371796349
Short name T373
Test name
Test status
Simulation time 74355480 ps
CPU time 0.78 seconds
Started Apr 15 12:38:48 PM PDT 24
Finished Apr 15 12:38:49 PM PDT 24
Peak memory 200612 kb
Host smart-a4e047d4-96fe-4231-b217-f578aa350e2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371796349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.371796349
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2797221596
Short name T370
Test name
Test status
Simulation time 1891621088 ps
CPU time 7.26 seconds
Started Apr 15 12:38:48 PM PDT 24
Finished Apr 15 12:38:55 PM PDT 24
Peak memory 218564 kb
Host smart-b3fea147-c9f9-41f9-afe5-65f622f1324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797221596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2797221596
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3859583767
Short name T423
Test name
Test status
Simulation time 244067011 ps
CPU time 1.05 seconds
Started Apr 15 12:38:43 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 218196 kb
Host smart-fa2667bf-b9cd-4b56-90a4-0fc55cb9fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859583767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3859583767
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2603291344
Short name T202
Test name
Test status
Simulation time 211448548 ps
CPU time 0.92 seconds
Started Apr 15 12:38:44 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 200648 kb
Host smart-67dac2df-4e5e-4cc4-97b3-e32f2ee599fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603291344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2603291344
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1848001036
Short name T21
Test name
Test status
Simulation time 892665111 ps
CPU time 4.84 seconds
Started Apr 15 12:38:43 PM PDT 24
Finished Apr 15 12:38:48 PM PDT 24
Peak memory 201048 kb
Host smart-e996991a-bb9c-43ec-bb5f-5a7a63b93579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848001036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1848001036
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.4254488051
Short name T332
Test name
Test status
Simulation time 187526259 ps
CPU time 1.26 seconds
Started Apr 15 12:38:46 PM PDT 24
Finished Apr 15 12:38:48 PM PDT 24
Peak memory 200840 kb
Host smart-7f09d642-f418-4005-9b6e-07ff41482a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254488051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.4254488051
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2069583791
Short name T206
Test name
Test status
Simulation time 111287546 ps
CPU time 1.11 seconds
Started Apr 15 12:38:37 PM PDT 24
Finished Apr 15 12:38:39 PM PDT 24
Peak memory 200992 kb
Host smart-edd84e58-01cd-48e5-8701-b31fb327d02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069583791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2069583791
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1005413807
Short name T126
Test name
Test status
Simulation time 17903417098 ps
CPU time 59.69 seconds
Started Apr 15 12:38:42 PM PDT 24
Finished Apr 15 12:39:42 PM PDT 24
Peak memory 209232 kb
Host smart-94ffc218-d551-41d5-a458-32a401b34dff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005413807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1005413807
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1624573805
Short name T285
Test name
Test status
Simulation time 293534399 ps
CPU time 2 seconds
Started Apr 15 12:38:43 PM PDT 24
Finished Apr 15 12:38:46 PM PDT 24
Peak memory 209060 kb
Host smart-050cc673-fd72-40bb-af94-26b878f008ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624573805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1624573805
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3038209630
Short name T536
Test name
Test status
Simulation time 71039880 ps
CPU time 0.78 seconds
Started Apr 15 12:38:45 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 200844 kb
Host smart-b923c64b-9591-4cc3-bf11-6b4cd1a389e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038209630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3038209630
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.358662770
Short name T86
Test name
Test status
Simulation time 93280273 ps
CPU time 0.87 seconds
Started Apr 15 12:38:55 PM PDT 24
Finished Apr 15 12:38:57 PM PDT 24
Peak memory 200604 kb
Host smart-7b928417-a4e5-4402-ba38-10baea9d8155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358662770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.358662770
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1690796411
Short name T534
Test name
Test status
Simulation time 1219663584 ps
CPU time 5.61 seconds
Started Apr 15 12:38:46 PM PDT 24
Finished Apr 15 12:38:52 PM PDT 24
Peak memory 230892 kb
Host smart-72c1a6b3-a3c3-4362-9c77-6faa17440b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690796411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1690796411
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2611267900
Short name T296
Test name
Test status
Simulation time 243821817 ps
CPU time 1.14 seconds
Started Apr 15 12:38:40 PM PDT 24
Finished Apr 15 12:38:41 PM PDT 24
Peak memory 218284 kb
Host smart-2f7f4382-fe3d-4a85-8b24-a37f04253c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611267900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2611267900
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.4230475674
Short name T449
Test name
Test status
Simulation time 154739738 ps
CPU time 0.86 seconds
Started Apr 15 12:38:41 PM PDT 24
Finished Apr 15 12:38:42 PM PDT 24
Peak memory 200644 kb
Host smart-390978b8-11b9-44a5-a46c-71386375a2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230475674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4230475674
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.4152806749
Short name T388
Test name
Test status
Simulation time 1173793752 ps
CPU time 5.48 seconds
Started Apr 15 12:38:45 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 201032 kb
Host smart-433d29be-611f-49d8-8c53-51cd9198e82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152806749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4152806749
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1840752418
Short name T247
Test name
Test status
Simulation time 188731732 ps
CPU time 1.25 seconds
Started Apr 15 12:38:40 PM PDT 24
Finished Apr 15 12:38:42 PM PDT 24
Peak memory 200856 kb
Host smart-f07c8659-ad92-4fe4-b40b-3e57afe59d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840752418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1840752418
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2039449929
Short name T391
Test name
Test status
Simulation time 253817393 ps
CPU time 1.46 seconds
Started Apr 15 12:38:49 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 200992 kb
Host smart-b294043a-b01b-4509-8d89-c0d839cd1216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039449929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2039449929
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3409853334
Short name T151
Test name
Test status
Simulation time 4856610051 ps
CPU time 21.55 seconds
Started Apr 15 12:39:00 PM PDT 24
Finished Apr 15 12:39:22 PM PDT 24
Peak memory 209252 kb
Host smart-afb0abf3-5a04-47de-a0ce-dad400d4c404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409853334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3409853334
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3464051397
Short name T235
Test name
Test status
Simulation time 492123856 ps
CPU time 2.49 seconds
Started Apr 15 12:38:53 PM PDT 24
Finished Apr 15 12:38:56 PM PDT 24
Peak memory 200812 kb
Host smart-09be1a64-2497-4481-b452-0bb80dc76901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464051397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3464051397
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3913858038
Short name T484
Test name
Test status
Simulation time 54948847 ps
CPU time 0.78 seconds
Started Apr 15 12:38:48 PM PDT 24
Finished Apr 15 12:38:50 PM PDT 24
Peak memory 200836 kb
Host smart-16824b5c-8457-4ee3-a134-d972af86e688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913858038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3913858038
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.892404791
Short name T437
Test name
Test status
Simulation time 74939170 ps
CPU time 0.8 seconds
Started Apr 15 12:39:00 PM PDT 24
Finished Apr 15 12:39:01 PM PDT 24
Peak memory 200608 kb
Host smart-fc2a55d5-77e7-4df0-bc5f-b372f6fc0d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892404791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.892404791
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1365475137
Short name T27
Test name
Test status
Simulation time 1223412841 ps
CPU time 5.66 seconds
Started Apr 15 12:38:44 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 218636 kb
Host smart-8d8c0b0b-d5ff-4723-b426-7e7d5c64d968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365475137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1365475137
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4236917792
Short name T477
Test name
Test status
Simulation time 244324988 ps
CPU time 1.19 seconds
Started Apr 15 12:38:47 PM PDT 24
Finished Apr 15 12:38:49 PM PDT 24
Peak memory 218304 kb
Host smart-feb31eb1-19c2-4247-af28-b2e62fbb9db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236917792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4236917792
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.4027827112
Short name T314
Test name
Test status
Simulation time 205065517 ps
CPU time 0.91 seconds
Started Apr 15 12:38:46 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 200648 kb
Host smart-f57c29f1-2a54-4acc-a465-c10e4cfe0818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027827112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.4027827112
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1150094069
Short name T167
Test name
Test status
Simulation time 1433340321 ps
CPU time 5.69 seconds
Started Apr 15 12:38:41 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 201016 kb
Host smart-decba8cf-c31d-4f03-aa1e-04a35f1368e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150094069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1150094069
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.546025454
Short name T205
Test name
Test status
Simulation time 142958294 ps
CPU time 1.09 seconds
Started Apr 15 12:38:54 PM PDT 24
Finished Apr 15 12:38:56 PM PDT 24
Peak memory 200844 kb
Host smart-40a312d5-5bea-4b58-a829-5ee3c5de6c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546025454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.546025454
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3142695586
Short name T447
Test name
Test status
Simulation time 122938627 ps
CPU time 1.24 seconds
Started Apr 15 12:38:45 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 201028 kb
Host smart-1247c7f8-5e55-4c5b-b2ea-a62e7d48d823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142695586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3142695586
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1088341548
Short name T460
Test name
Test status
Simulation time 186699822 ps
CPU time 1.18 seconds
Started Apr 15 12:38:45 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 200840 kb
Host smart-e1b5f53d-1d53-408a-af25-6be98c9f6cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088341548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1088341548
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2128119208
Short name T195
Test name
Test status
Simulation time 141942094 ps
CPU time 1.65 seconds
Started Apr 15 12:38:48 PM PDT 24
Finished Apr 15 12:38:50 PM PDT 24
Peak memory 200812 kb
Host smart-bcb01731-72f4-4fa1-bd94-67dfd526e286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128119208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2128119208
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1189710041
Short name T10
Test name
Test status
Simulation time 245691117 ps
CPU time 1.41 seconds
Started Apr 15 12:39:01 PM PDT 24
Finished Apr 15 12:39:03 PM PDT 24
Peak memory 200812 kb
Host smart-2cb6d658-27ab-438c-b27c-02d939e5a7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189710041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1189710041
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.4259874757
Short name T256
Test name
Test status
Simulation time 79862860 ps
CPU time 0.8 seconds
Started Apr 15 12:38:52 PM PDT 24
Finished Apr 15 12:38:53 PM PDT 24
Peak memory 200588 kb
Host smart-7d0647d2-c3fa-4b02-b687-6066c0ea2030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259874757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.4259874757
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3490786220
Short name T542
Test name
Test status
Simulation time 1225577148 ps
CPU time 5.53 seconds
Started Apr 15 12:38:49 PM PDT 24
Finished Apr 15 12:38:55 PM PDT 24
Peak memory 217576 kb
Host smart-f1b7840e-aab2-434d-9307-7f894923c1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490786220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3490786220
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1136659228
Short name T438
Test name
Test status
Simulation time 244289461 ps
CPU time 1.07 seconds
Started Apr 15 12:38:47 PM PDT 24
Finished Apr 15 12:38:49 PM PDT 24
Peak memory 218296 kb
Host smart-a171f237-47fd-4c7f-aa72-ce28987d4dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136659228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1136659228
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4290329627
Short name T253
Test name
Test status
Simulation time 120453626 ps
CPU time 0.8 seconds
Started Apr 15 12:38:46 PM PDT 24
Finished Apr 15 12:38:47 PM PDT 24
Peak memory 200672 kb
Host smart-31424db7-925a-4483-9bec-b364a4303354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290329627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4290329627
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2186793078
Short name T37
Test name
Test status
Simulation time 1975038045 ps
CPU time 7.77 seconds
Started Apr 15 12:38:48 PM PDT 24
Finished Apr 15 12:38:56 PM PDT 24
Peak memory 200996 kb
Host smart-da1412bf-47d9-400a-b898-45931a087b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186793078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2186793078
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1741842020
Short name T157
Test name
Test status
Simulation time 166027512 ps
CPU time 1.35 seconds
Started Apr 15 12:38:48 PM PDT 24
Finished Apr 15 12:38:50 PM PDT 24
Peak memory 200836 kb
Host smart-30ce89e9-be73-46d6-8726-51deba464745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741842020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1741842020
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1482152954
Short name T324
Test name
Test status
Simulation time 198650640 ps
CPU time 1.31 seconds
Started Apr 15 12:38:43 PM PDT 24
Finished Apr 15 12:38:45 PM PDT 24
Peak memory 201000 kb
Host smart-c49584fe-c094-43a2-88a2-df4d96274c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482152954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1482152954
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3682846942
Short name T541
Test name
Test status
Simulation time 4232646662 ps
CPU time 17.77 seconds
Started Apr 15 12:38:58 PM PDT 24
Finished Apr 15 12:39:16 PM PDT 24
Peak memory 209276 kb
Host smart-bc7f21eb-60ba-4e23-adf4-4eccce828319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682846942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3682846942
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3744955896
Short name T395
Test name
Test status
Simulation time 509025149 ps
CPU time 2.7 seconds
Started Apr 15 12:38:47 PM PDT 24
Finished Apr 15 12:38:50 PM PDT 24
Peak memory 200832 kb
Host smart-e835861a-90eb-4338-a815-2f0c7da7e81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744955896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3744955896
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2375486354
Short name T271
Test name
Test status
Simulation time 113616505 ps
CPU time 1.05 seconds
Started Apr 15 12:39:04 PM PDT 24
Finished Apr 15 12:39:06 PM PDT 24
Peak memory 200792 kb
Host smart-bd543ce1-acdf-4fe0-8f30-9298f90edf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375486354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2375486354
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.926615666
Short name T420
Test name
Test status
Simulation time 83206350 ps
CPU time 0.83 seconds
Started Apr 15 12:38:58 PM PDT 24
Finished Apr 15 12:38:59 PM PDT 24
Peak memory 200676 kb
Host smart-deead42f-a493-453c-8263-312ed89784bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926615666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.926615666
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1675109267
Short name T45
Test name
Test status
Simulation time 2344838860 ps
CPU time 7.73 seconds
Started Apr 15 12:38:46 PM PDT 24
Finished Apr 15 12:38:59 PM PDT 24
Peak memory 218636 kb
Host smart-2471867b-518d-4284-b908-c47ae824467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675109267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1675109267
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2105407325
Short name T455
Test name
Test status
Simulation time 243987303 ps
CPU time 1.07 seconds
Started Apr 15 12:39:00 PM PDT 24
Finished Apr 15 12:39:01 PM PDT 24
Peak memory 218296 kb
Host smart-23ca8831-1b15-4854-a7a5-7892f564028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105407325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2105407325
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2247802190
Short name T442
Test name
Test status
Simulation time 204952089 ps
CPU time 0.91 seconds
Started Apr 15 12:39:04 PM PDT 24
Finished Apr 15 12:39:05 PM PDT 24
Peak memory 200656 kb
Host smart-2ca3d7a2-d67e-44b2-aa8a-3ad5d126d7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247802190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2247802190
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3993440764
Short name T418
Test name
Test status
Simulation time 832920126 ps
CPU time 4.28 seconds
Started Apr 15 12:38:58 PM PDT 24
Finished Apr 15 12:39:03 PM PDT 24
Peak memory 201036 kb
Host smart-9b904d5e-6170-4a49-beec-8cf1c63a815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993440764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3993440764
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2105007331
Short name T444
Test name
Test status
Simulation time 177075906 ps
CPU time 1.19 seconds
Started Apr 15 12:38:49 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 200832 kb
Host smart-4f35a9f7-fe4c-4e93-a8e1-746177777737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105007331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2105007331
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4235159802
Short name T506
Test name
Test status
Simulation time 112027645 ps
CPU time 1.24 seconds
Started Apr 15 12:39:01 PM PDT 24
Finished Apr 15 12:39:03 PM PDT 24
Peak memory 201004 kb
Host smart-8b0e1e6c-b471-42ba-a3e7-6234493a44b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235159802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4235159802
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.4114415807
Short name T127
Test name
Test status
Simulation time 13957857531 ps
CPU time 47.59 seconds
Started Apr 15 12:38:46 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 209288 kb
Host smart-e971331f-39b5-4ad2-9537-a20864b29836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114415807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4114415807
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.974809003
Short name T176
Test name
Test status
Simulation time 463909889 ps
CPU time 2.73 seconds
Started Apr 15 12:38:44 PM PDT 24
Finished Apr 15 12:38:48 PM PDT 24
Peak memory 200828 kb
Host smart-2e168663-5183-4731-9e79-1927d1d5c5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974809003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.974809003
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2175053157
Short name T469
Test name
Test status
Simulation time 89778805 ps
CPU time 0.85 seconds
Started Apr 15 12:38:53 PM PDT 24
Finished Apr 15 12:38:54 PM PDT 24
Peak memory 200700 kb
Host smart-a2830f59-83ef-4729-8d80-bdcd542dc19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175053157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2175053157
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.455616449
Short name T331
Test name
Test status
Simulation time 70648681 ps
CPU time 0.75 seconds
Started Apr 15 12:38:55 PM PDT 24
Finished Apr 15 12:38:56 PM PDT 24
Peak memory 200652 kb
Host smart-d1071435-c3bc-43d5-9bab-61cc6135867d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455616449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.455616449
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2986038535
Short name T424
Test name
Test status
Simulation time 1878956855 ps
CPU time 7.57 seconds
Started Apr 15 12:39:08 PM PDT 24
Finished Apr 15 12:39:17 PM PDT 24
Peak memory 222684 kb
Host smart-9b7bbda8-accc-4c5a-94a8-d1e849c41f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986038535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2986038535
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1137718047
Short name T346
Test name
Test status
Simulation time 244034503 ps
CPU time 1.16 seconds
Started Apr 15 12:38:49 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 218140 kb
Host smart-c25cc35f-b6ef-4d5c-9c6f-2b99ec6b72f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137718047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1137718047
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.988453533
Short name T19
Test name
Test status
Simulation time 206821683 ps
CPU time 1.01 seconds
Started Apr 15 12:39:04 PM PDT 24
Finished Apr 15 12:39:05 PM PDT 24
Peak memory 200580 kb
Host smart-52079459-607c-4ecc-956f-2ceff7b7d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988453533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.988453533
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3554182671
Short name T293
Test name
Test status
Simulation time 1810662166 ps
CPU time 7.44 seconds
Started Apr 15 12:39:04 PM PDT 24
Finished Apr 15 12:39:12 PM PDT 24
Peak memory 201008 kb
Host smart-e9102783-adf3-4b57-8465-c0d124eeb55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554182671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3554182671
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2543998732
Short name T378
Test name
Test status
Simulation time 105619211 ps
CPU time 1.01 seconds
Started Apr 15 12:39:01 PM PDT 24
Finished Apr 15 12:39:03 PM PDT 24
Peak memory 200820 kb
Host smart-e64cf647-1687-4269-8441-ee9abff0a024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543998732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2543998732
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2604967484
Short name T414
Test name
Test status
Simulation time 246205123 ps
CPU time 1.39 seconds
Started Apr 15 12:39:01 PM PDT 24
Finished Apr 15 12:39:03 PM PDT 24
Peak memory 201036 kb
Host smart-ef830c59-a073-4f7f-8620-991be233b014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604967484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2604967484
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2050140756
Short name T251
Test name
Test status
Simulation time 995337716 ps
CPU time 4.43 seconds
Started Apr 15 12:39:01 PM PDT 24
Finished Apr 15 12:39:06 PM PDT 24
Peak memory 201028 kb
Host smart-074e4fe3-e2ce-4390-9d49-f3d540e14f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050140756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2050140756
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1066721791
Short name T470
Test name
Test status
Simulation time 384279009 ps
CPU time 2.3 seconds
Started Apr 15 12:39:14 PM PDT 24
Finished Apr 15 12:39:17 PM PDT 24
Peak memory 200844 kb
Host smart-31ec0ba5-5362-4cb2-89c3-d4cfb95bede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066721791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1066721791
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3261492282
Short name T46
Test name
Test status
Simulation time 245067185 ps
CPU time 1.49 seconds
Started Apr 15 12:39:01 PM PDT 24
Finished Apr 15 12:39:03 PM PDT 24
Peak memory 200828 kb
Host smart-244e81b2-6dc3-4f0b-ad79-b0a5fe7d152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261492282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3261492282
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1948066276
Short name T60
Test name
Test status
Simulation time 71404595 ps
CPU time 0.78 seconds
Started Apr 15 12:38:49 PM PDT 24
Finished Apr 15 12:38:51 PM PDT 24
Peak memory 200632 kb
Host smart-540ecb9b-acbf-437a-9b45-7e1c18a3b5f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948066276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1948066276
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1133337753
Short name T43
Test name
Test status
Simulation time 1230615007 ps
CPU time 5.92 seconds
Started Apr 15 12:39:15 PM PDT 24
Finished Apr 15 12:39:22 PM PDT 24
Peak memory 218612 kb
Host smart-e2e7bcb2-448d-42a3-94c6-c39bf188e061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133337753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1133337753
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1726063676
Short name T191
Test name
Test status
Simulation time 244913230 ps
CPU time 1.07 seconds
Started Apr 15 12:39:02 PM PDT 24
Finished Apr 15 12:39:03 PM PDT 24
Peak memory 218160 kb
Host smart-fc105ccc-23b5-48d5-8efa-44d697918808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726063676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1726063676
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1805107893
Short name T402
Test name
Test status
Simulation time 174575496 ps
CPU time 0.82 seconds
Started Apr 15 12:39:06 PM PDT 24
Finished Apr 15 12:39:08 PM PDT 24
Peak memory 200656 kb
Host smart-b09b6f11-f891-4861-9c0c-6cd5145a403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805107893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1805107893
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3231457806
Short name T441
Test name
Test status
Simulation time 1685842096 ps
CPU time 6.52 seconds
Started Apr 15 12:38:49 PM PDT 24
Finished Apr 15 12:38:57 PM PDT 24
Peak memory 200988 kb
Host smart-0f8f5109-325f-4815-93b1-2485ad363181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231457806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3231457806
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2257522443
Short name T255
Test name
Test status
Simulation time 100952537 ps
CPU time 0.98 seconds
Started Apr 15 12:39:00 PM PDT 24
Finished Apr 15 12:39:01 PM PDT 24
Peak memory 200768 kb
Host smart-b1a4c1d6-2661-445c-be0d-a00ee648df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257522443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2257522443
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1712334358
Short name T190
Test name
Test status
Simulation time 119274387 ps
CPU time 1.28 seconds
Started Apr 15 12:39:04 PM PDT 24
Finished Apr 15 12:39:06 PM PDT 24
Peak memory 200964 kb
Host smart-06cf5fcc-cc49-4ef9-b492-b9fba929a2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712334358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1712334358
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1097734025
Short name T351
Test name
Test status
Simulation time 1621456072 ps
CPU time 5.79 seconds
Started Apr 15 12:38:54 PM PDT 24
Finished Apr 15 12:39:00 PM PDT 24
Peak memory 200948 kb
Host smart-c95c23e3-68fb-4dfe-bb33-24e08e873baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097734025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1097734025
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1828703180
Short name T530
Test name
Test status
Simulation time 285286579 ps
CPU time 1.89 seconds
Started Apr 15 12:39:09 PM PDT 24
Finished Apr 15 12:39:12 PM PDT 24
Peak memory 200776 kb
Host smart-aec74dbe-e22d-48ac-b1e3-240f1ac43dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828703180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1828703180
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3580755412
Short name T323
Test name
Test status
Simulation time 146039537 ps
CPU time 1.09 seconds
Started Apr 15 12:39:03 PM PDT 24
Finished Apr 15 12:39:04 PM PDT 24
Peak memory 200824 kb
Host smart-ce55fa00-bced-4bc3-8932-d5f21b39c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580755412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3580755412
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.638341225
Short name T325
Test name
Test status
Simulation time 93613167 ps
CPU time 0.85 seconds
Started Apr 15 12:37:48 PM PDT 24
Finished Apr 15 12:37:50 PM PDT 24
Peak memory 200628 kb
Host smart-4f60c0be-a1c6-48eb-826c-20298a764d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638341225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.638341225
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1931333321
Short name T42
Test name
Test status
Simulation time 1900454632 ps
CPU time 7.24 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:37:56 PM PDT 24
Peak memory 222628 kb
Host smart-ffa167c0-d0ae-401c-a990-d8597183c6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931333321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1931333321
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3913804790
Short name T92
Test name
Test status
Simulation time 243825268 ps
CPU time 1.02 seconds
Started Apr 15 12:37:37 PM PDT 24
Finished Apr 15 12:37:39 PM PDT 24
Peak memory 218216 kb
Host smart-58b1afa6-d827-4751-b231-d32342fac783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913804790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3913804790
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3372351546
Short name T344
Test name
Test status
Simulation time 104828344 ps
CPU time 0.79 seconds
Started Apr 15 12:37:48 PM PDT 24
Finished Apr 15 12:37:51 PM PDT 24
Peak memory 200636 kb
Host smart-f9cb2201-ce0a-41ee-b3ed-05db1c0a84bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372351546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3372351546
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2149695708
Short name T53
Test name
Test status
Simulation time 1461588536 ps
CPU time 5.89 seconds
Started Apr 15 12:37:50 PM PDT 24
Finished Apr 15 12:37:57 PM PDT 24
Peak memory 201016 kb
Host smart-7ff5522a-d278-47a8-b33b-87c65acdab46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149695708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2149695708
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2569841525
Short name T297
Test name
Test status
Simulation time 149902079 ps
CPU time 1.06 seconds
Started Apr 15 12:37:41 PM PDT 24
Finished Apr 15 12:37:43 PM PDT 24
Peak memory 200844 kb
Host smart-5254b33d-b4b8-4142-9739-d70411acb9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569841525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2569841525
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1086439218
Short name T161
Test name
Test status
Simulation time 115236218 ps
CPU time 1.16 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 200952 kb
Host smart-a57c78da-1453-47ce-b5f4-4552aafcc02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086439218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1086439218
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1358167737
Short name T57
Test name
Test status
Simulation time 2334470668 ps
CPU time 10.8 seconds
Started Apr 15 12:37:43 PM PDT 24
Finished Apr 15 12:37:54 PM PDT 24
Peak memory 209248 kb
Host smart-b6572046-6567-44a0-83c8-9c6182d21e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358167737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1358167737
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.4253295617
Short name T269
Test name
Test status
Simulation time 541864429 ps
CPU time 2.92 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:37:52 PM PDT 24
Peak memory 200736 kb
Host smart-8ac1ebdd-a5b8-426b-bb02-3e813fa4df2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253295617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.4253295617
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.231031816
Short name T330
Test name
Test status
Simulation time 85447454 ps
CPU time 0.81 seconds
Started Apr 15 12:37:41 PM PDT 24
Finished Apr 15 12:37:43 PM PDT 24
Peak memory 200748 kb
Host smart-cb46af7c-7adc-4b64-be42-7f2eabb38755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231031816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.231031816
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.773550315
Short name T166
Test name
Test status
Simulation time 72146608 ps
CPU time 0.76 seconds
Started Apr 15 12:37:44 PM PDT 24
Finished Apr 15 12:37:46 PM PDT 24
Peak memory 200584 kb
Host smart-44365e24-947d-43cf-94a3-a24de3e25d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773550315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.773550315
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3391590409
Short name T28
Test name
Test status
Simulation time 1891212512 ps
CPU time 7.9 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:55 PM PDT 24
Peak memory 218556 kb
Host smart-94c8f4a1-5454-4335-ab95-a49bc455107a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391590409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3391590409
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2515212370
Short name T93
Test name
Test status
Simulation time 244944839 ps
CPU time 1.1 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:47 PM PDT 24
Peak memory 218136 kb
Host smart-dd73c550-0dce-446b-98c0-5d9d514b4081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515212370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2515212370
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.117120075
Short name T355
Test name
Test status
Simulation time 200530439 ps
CPU time 0.88 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 200616 kb
Host smart-fd1d0441-5fe5-43dd-991c-aaf1943213ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117120075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.117120075
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3065272626
Short name T273
Test name
Test status
Simulation time 823045282 ps
CPU time 4.12 seconds
Started Apr 15 12:37:52 PM PDT 24
Finished Apr 15 12:37:56 PM PDT 24
Peak memory 200956 kb
Host smart-52a70d89-6633-4212-9e22-009c1bb0cab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065272626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3065272626
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3119178998
Short name T181
Test name
Test status
Simulation time 105858706 ps
CPU time 1.07 seconds
Started Apr 15 12:38:21 PM PDT 24
Finished Apr 15 12:38:23 PM PDT 24
Peak memory 200756 kb
Host smart-e1f3bd54-fcc9-4f3d-9f02-a725cfb1ed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119178998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3119178998
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1196603707
Short name T170
Test name
Test status
Simulation time 205747450 ps
CPU time 1.44 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:48 PM PDT 24
Peak memory 201084 kb
Host smart-459a25bc-6678-4859-8b6d-69dac9e1ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196603707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1196603707
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2207382542
Short name T456
Test name
Test status
Simulation time 5748776547 ps
CPU time 23.1 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:38:09 PM PDT 24
Peak memory 201020 kb
Host smart-d1d41967-a497-4ffb-a3fc-272260724fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207382542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2207382542
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.826502212
Short name T333
Test name
Test status
Simulation time 144067554 ps
CPU time 1.74 seconds
Started Apr 15 12:37:43 PM PDT 24
Finished Apr 15 12:37:46 PM PDT 24
Peak memory 209028 kb
Host smart-db8fadc0-5e4b-4a6a-adce-c320f74f4a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826502212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.826502212
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4178726712
Short name T380
Test name
Test status
Simulation time 85605277 ps
CPU time 0.83 seconds
Started Apr 15 12:37:44 PM PDT 24
Finished Apr 15 12:37:46 PM PDT 24
Peak memory 200788 kb
Host smart-eeb5de81-a54e-4bae-b43a-59cb4c319eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178726712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4178726712
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2209963150
Short name T497
Test name
Test status
Simulation time 80521529 ps
CPU time 0.86 seconds
Started Apr 15 12:37:48 PM PDT 24
Finished Apr 15 12:37:51 PM PDT 24
Peak memory 200604 kb
Host smart-faeb8849-9ecf-4220-bb17-89d99d709b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209963150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2209963150
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3340437227
Short name T481
Test name
Test status
Simulation time 244191370 ps
CPU time 1.18 seconds
Started Apr 15 12:37:46 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 218184 kb
Host smart-0c98861e-2fe4-4ea2-b413-bbbc580a2864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340437227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3340437227
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1420001715
Short name T412
Test name
Test status
Simulation time 129332038 ps
CPU time 0.83 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 200620 kb
Host smart-e1a34068-7e48-4a0b-8c77-a5d90110e0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420001715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1420001715
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.805967616
Short name T289
Test name
Test status
Simulation time 1479541138 ps
CPU time 5.63 seconds
Started Apr 15 12:37:43 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 201056 kb
Host smart-6ba1f3c0-1e3b-41d6-9d92-fed81655e530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805967616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.805967616
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.772486276
Short name T510
Test name
Test status
Simulation time 187488457 ps
CPU time 1.25 seconds
Started Apr 15 12:37:47 PM PDT 24
Finished Apr 15 12:37:50 PM PDT 24
Peak memory 200788 kb
Host smart-9d255506-6040-4bfb-85fd-8061ed3acae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772486276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.772486276
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2591155605
Short name T352
Test name
Test status
Simulation time 258038921 ps
CPU time 1.53 seconds
Started Apr 15 12:37:45 PM PDT 24
Finished Apr 15 12:37:47 PM PDT 24
Peak memory 201000 kb
Host smart-1d1c6e8d-1c69-4eb3-8b98-e9b79931ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591155605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2591155605
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.630774581
Short name T158
Test name
Test status
Simulation time 366207616 ps
CPU time 2.23 seconds
Started Apr 15 12:37:42 PM PDT 24
Finished Apr 15 12:37:45 PM PDT 24
Peak memory 200736 kb
Host smart-24a3ff9b-8ad2-4d90-8b12-1095aabf84b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630774581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.630774581
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1537959991
Short name T345
Test name
Test status
Simulation time 149165624 ps
CPU time 1.02 seconds
Started Apr 15 12:37:46 PM PDT 24
Finished Apr 15 12:37:48 PM PDT 24
Peak memory 200820 kb
Host smart-e03ce2cc-35c8-4d77-90ac-c334cc15204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537959991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1537959991
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.77996028
Short name T9
Test name
Test status
Simulation time 70694630 ps
CPU time 0.74 seconds
Started Apr 15 12:37:54 PM PDT 24
Finished Apr 15 12:37:55 PM PDT 24
Peak memory 200672 kb
Host smart-6442f2a2-17b7-4b55-8947-f896d5da02db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77996028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.77996028
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3053117510
Short name T32
Test name
Test status
Simulation time 2161001558 ps
CPU time 8.99 seconds
Started Apr 15 12:37:52 PM PDT 24
Finished Apr 15 12:38:01 PM PDT 24
Peak memory 218588 kb
Host smart-6c034919-fa07-44f4-8f84-f360e578b93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053117510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3053117510
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.780222715
Short name T302
Test name
Test status
Simulation time 244624139 ps
CPU time 1.05 seconds
Started Apr 15 12:37:52 PM PDT 24
Finished Apr 15 12:37:54 PM PDT 24
Peak memory 218144 kb
Host smart-998ec0f4-6b5b-45f6-82ed-292d0b5c18c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780222715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.780222715
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.414840101
Short name T13
Test name
Test status
Simulation time 209192396 ps
CPU time 1 seconds
Started Apr 15 12:37:46 PM PDT 24
Finished Apr 15 12:37:49 PM PDT 24
Peak memory 200568 kb
Host smart-86a97d43-e42f-407e-94ea-2a2f35f3ba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414840101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.414840101
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4128398438
Short name T257
Test name
Test status
Simulation time 1668677771 ps
CPU time 6.64 seconds
Started Apr 15 12:37:51 PM PDT 24
Finished Apr 15 12:37:58 PM PDT 24
Peak memory 201032 kb
Host smart-4a89ac43-a4d9-48e6-bdb4-03407f4d6ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128398438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4128398438
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.865885012
Short name T491
Test name
Test status
Simulation time 104775190 ps
CPU time 1.01 seconds
Started Apr 15 12:37:50 PM PDT 24
Finished Apr 15 12:37:52 PM PDT 24
Peak memory 200740 kb
Host smart-68438cde-5aea-41c9-a81b-0b27fce533ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865885012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.865885012
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3194916967
Short name T482
Test name
Test status
Simulation time 236409750 ps
CPU time 1.45 seconds
Started Apr 15 12:37:42 PM PDT 24
Finished Apr 15 12:37:44 PM PDT 24
Peak memory 200940 kb
Host smart-eb4f4d7a-2673-43fb-a1d9-5fef509fada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194916967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3194916967
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1120735508
Short name T404
Test name
Test status
Simulation time 1100420262 ps
CPU time 4.41 seconds
Started Apr 15 12:37:54 PM PDT 24
Finished Apr 15 12:37:59 PM PDT 24
Peak memory 201048 kb
Host smart-33b65fbf-3aa6-404e-8a46-61da7faae663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120735508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1120735508
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2515973342
Short name T377
Test name
Test status
Simulation time 364869816 ps
CPU time 1.96 seconds
Started Apr 15 12:37:51 PM PDT 24
Finished Apr 15 12:37:54 PM PDT 24
Peak memory 200736 kb
Host smart-35368f46-b8c1-4506-9143-73ea72f029a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515973342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2515973342
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1378241192
Short name T446
Test name
Test status
Simulation time 70736310 ps
CPU time 0.82 seconds
Started Apr 15 12:37:53 PM PDT 24
Finished Apr 15 12:37:54 PM PDT 24
Peak memory 200756 kb
Host smart-0d6075ba-ba0f-45b5-9f30-3615cdbbc887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378241192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1378241192
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.690456314
Short name T149
Test name
Test status
Simulation time 75523305 ps
CPU time 0.79 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:01 PM PDT 24
Peak memory 200652 kb
Host smart-928b4e2b-3288-4f0a-a210-925aa243afe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690456314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.690456314
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4028678117
Short name T503
Test name
Test status
Simulation time 1228202646 ps
CPU time 5.46 seconds
Started Apr 15 12:38:00 PM PDT 24
Finished Apr 15 12:38:07 PM PDT 24
Peak memory 218572 kb
Host smart-af5ab89b-91bf-44f2-8534-f270bf72fb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028678117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4028678117
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1280775625
Short name T328
Test name
Test status
Simulation time 244164517 ps
CPU time 1.04 seconds
Started Apr 15 12:37:58 PM PDT 24
Finished Apr 15 12:38:00 PM PDT 24
Peak memory 218188 kb
Host smart-6e99ae8e-ce33-49be-ba04-440804b82e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280775625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1280775625
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3430019253
Short name T450
Test name
Test status
Simulation time 188734914 ps
CPU time 0.81 seconds
Started Apr 15 12:37:49 PM PDT 24
Finished Apr 15 12:37:51 PM PDT 24
Peak memory 200556 kb
Host smart-253c8edb-46db-4e62-94fa-cb6c4caa795d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430019253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3430019253
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.794967944
Short name T337
Test name
Test status
Simulation time 1023370967 ps
CPU time 5.03 seconds
Started Apr 15 12:37:49 PM PDT 24
Finished Apr 15 12:37:55 PM PDT 24
Peak memory 200916 kb
Host smart-3d8a017b-3b91-491a-accb-27f145b7de96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794967944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.794967944
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.648873371
Short name T144
Test name
Test status
Simulation time 146538163 ps
CPU time 1.12 seconds
Started Apr 15 12:37:52 PM PDT 24
Finished Apr 15 12:37:54 PM PDT 24
Peak memory 200820 kb
Host smart-4d1dcc95-85b2-44e8-a8df-9ac290f70796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648873371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.648873371
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.609574357
Short name T366
Test name
Test status
Simulation time 202746569 ps
CPU time 1.38 seconds
Started Apr 15 12:37:53 PM PDT 24
Finished Apr 15 12:37:55 PM PDT 24
Peak memory 200976 kb
Host smart-3ec723db-d1a6-4f8e-b66b-5d6fc269eb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609574357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.609574357
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1421586143
Short name T177
Test name
Test status
Simulation time 1159534635 ps
CPU time 4.95 seconds
Started Apr 15 12:38:02 PM PDT 24
Finished Apr 15 12:38:07 PM PDT 24
Peak memory 201012 kb
Host smart-a5781c59-783b-4649-a176-214a25d88ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421586143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1421586143
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2904972289
Short name T52
Test name
Test status
Simulation time 110862206 ps
CPU time 1.36 seconds
Started Apr 15 12:37:51 PM PDT 24
Finished Apr 15 12:37:53 PM PDT 24
Peak memory 200820 kb
Host smart-91e2fe44-ddd8-405b-8284-dc3935b691b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904972289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2904972289
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.516529609
Short name T472
Test name
Test status
Simulation time 143827481 ps
CPU time 1.08 seconds
Started Apr 15 12:37:51 PM PDT 24
Finished Apr 15 12:37:53 PM PDT 24
Peak memory 200860 kb
Host smart-9f1f6151-ebff-4a35-8f4b-228d698febdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516529609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.516529609
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%