Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8762

1

T2

40

T3

37

T7

27

auto[1]

11544

1

T2

26

T3

24

T6

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6299	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6762	1			T1	1		T2	22		T3	22
reset_info_cp[2]	3112	1			T2	11		T3	7		T6	1
reset_info_cp[4]	4197	1			T2	12		T3	15		T6	1
reset_info_cp[8]	103	1			T7	1		T13	2		T42	3
reset_info_cp[16]	103	1			T2	1		T3	2		T7	1
reset_info_cp[32]	113	1			T9	1		T11	1		T13	2
reset_info_cp[64]	105	1			T11	1		T23	1		T52	2
reset_info_cp[128]	132	1			T7	1		T11	1		T23	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3303	1			T2	11		T3	13		T7	5
reset_info_cp[1]	auto[1]	2839	1			T2	10		T3	8		T6	1
reset_info_cp[2]	auto[0]	1004	1			T2	7		T3	5		T7	5
reset_info_cp[2]	auto[1]	2108	1			T2	4		T3	2		T6	1
reset_info_cp[4]	auto[0]	1528	1			T2	3		T3	4		T7	6
reset_info_cp[4]	auto[1]	2669	1			T2	9		T3	11		T6	1
reset_info_cp[8]	auto[0]	35	1			T7	1		T13	2		T42	1
reset_info_cp[8]	auto[1]	68	1			T42	2		T37	1		T47	1
reset_info_cp[16]	auto[0]	48	1			T2	1		T3	2		T7	1
reset_info_cp[16]	auto[1]	55	1			T9	1		T11	1		T34	1
reset_info_cp[32]	auto[0]	47	1			T13	2		T126	2		T98	1
reset_info_cp[32]	auto[1]	66	1			T9	1		T11	1		T42	2
reset_info_cp[64]	auto[0]	41	1			T23	1		T78	2		T94	1
reset_info_cp[64]	auto[1]	64	1			T11	1		T52	2		T78	2
reset_info_cp[128]	auto[0]	50	1			T23	1		T42	3		T78	1
reset_info_cp[128]	auto[1]	82	1			T7	1		T11	1		T78	1