Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/38.rstmgr_sw_rst.3459707200 Apr 16 12:39:43 PM PDT 24 Apr 16 12:39:46 PM PDT 24 131705885 ps
T536 /workspace/coverage/default/6.rstmgr_sw_rst.1520304938 Apr 16 12:39:01 PM PDT 24 Apr 16 12:39:08 PM PDT 24 475531602 ps
T537 /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1375501325 Apr 16 12:39:05 PM PDT 24 Apr 16 12:39:09 PM PDT 24 244079481 ps
T538 /workspace/coverage/default/28.rstmgr_por_stretcher.272942184 Apr 16 12:39:23 PM PDT 24 Apr 16 12:39:25 PM PDT 24 134822618 ps
T539 /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3918158752 Apr 16 12:39:39 PM PDT 24 Apr 16 12:39:42 PM PDT 24 245616120 ps
T55 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4031129629 Apr 16 12:38:54 PM PDT 24 Apr 16 12:38:58 PM PDT 24 525696049 ps
T56 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1692867897 Apr 16 12:38:57 PM PDT 24 Apr 16 12:39:02 PM PDT 24 454858402 ps
T58 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2153805691 Apr 16 12:38:39 PM PDT 24 Apr 16 12:38:42 PM PDT 24 258867210 ps
T57 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3080415813 Apr 16 12:38:34 PM PDT 24 Apr 16 12:38:36 PM PDT 24 143829924 ps
T105 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1084910065 Apr 16 12:38:47 PM PDT 24 Apr 16 12:38:48 PM PDT 24 64452331 ps
T61 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3481813086 Apr 16 12:38:54 PM PDT 24 Apr 16 12:39:00 PM PDT 24 926909890 ps
T59 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4234509680 Apr 16 12:38:37 PM PDT 24 Apr 16 12:38:39 PM PDT 24 130958455 ps
T85 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1997374109 Apr 16 12:38:55 PM PDT 24 Apr 16 12:39:01 PM PDT 24 957542411 ps
T540 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.340844524 Apr 16 12:38:39 PM PDT 24 Apr 16 12:38:48 PM PDT 24 1561339460 ps
T541 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.658453275 Apr 16 12:38:43 PM PDT 24 Apr 16 12:38:45 PM PDT 24 208112997 ps
T106 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.648506087 Apr 16 12:38:30 PM PDT 24 Apr 16 12:38:32 PM PDT 24 143815585 ps
T90 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3399437132 Apr 16 12:38:57 PM PDT 24 Apr 16 12:39:02 PM PDT 24 472831529 ps
T107 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.624695170 Apr 16 12:38:51 PM PDT 24 Apr 16 12:38:53 PM PDT 24 121332878 ps
T108 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.784237317 Apr 16 12:38:54 PM PDT 24 Apr 16 12:38:57 PM PDT 24 149329517 ps
T60 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2712822793 Apr 16 12:38:44 PM PDT 24 Apr 16 12:38:48 PM PDT 24 306027921 ps
T86 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2640902588 Apr 16 12:38:31 PM PDT 24 Apr 16 12:38:34 PM PDT 24 98901028 ps
T91 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3241923251 Apr 16 12:38:53 PM PDT 24 Apr 16 12:38:57 PM PDT 24 482667461 ps
T122 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1970912208 Apr 16 12:38:50 PM PDT 24 Apr 16 12:38:53 PM PDT 24 533870494 ps
T92 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3080581137 Apr 16 12:38:42 PM PDT 24 Apr 16 12:38:45 PM PDT 24 506946386 ps
T542 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.192458389 Apr 16 12:39:00 PM PDT 24 Apr 16 12:39:06 PM PDT 24 79025765 ps
T109 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1510360367 Apr 16 12:38:57 PM PDT 24 Apr 16 12:39:01 PM PDT 24 78481889 ps
T110 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1067452403 Apr 16 12:38:53 PM PDT 24 Apr 16 12:38:56 PM PDT 24 67117572 ps
T111 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3074535884 Apr 16 12:38:58 PM PDT 24 Apr 16 12:39:03 PM PDT 24 58986064 ps
T543 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1913629485 Apr 16 12:38:38 PM PDT 24 Apr 16 12:38:40 PM PDT 24 93147277 ps
T87 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1020062011 Apr 16 12:38:53 PM PDT 24 Apr 16 12:38:57 PM PDT 24 168692828 ps
T88 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.540146136 Apr 16 12:38:44 PM PDT 24 Apr 16 12:38:48 PM PDT 24 303751227 ps
T89 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3164209352 Apr 16 12:38:55 PM PDT 24 Apr 16 12:39:00 PM PDT 24 489608311 ps
T112 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.903158074 Apr 16 12:38:50 PM PDT 24 Apr 16 12:38:52 PM PDT 24 257273662 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3866199732 Apr 16 12:38:25 PM PDT 24 Apr 16 12:38:27 PM PDT 24 98914026 ps
T545 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3069383325 Apr 16 12:38:43 PM PDT 24 Apr 16 12:38:50 PM PDT 24 481074427 ps
T546 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1089928134 Apr 16 12:38:44 PM PDT 24 Apr 16 12:38:45 PM PDT 24 75901036 ps
T114 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1969515974 Apr 16 12:38:35 PM PDT 24 Apr 16 12:38:38 PM PDT 24 338901198 ps
T547 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.793666964 Apr 16 12:38:58 PM PDT 24 Apr 16 12:39:03 PM PDT 24 175567057 ps
T113 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3682450151 Apr 16 12:38:52 PM PDT 24 Apr 16 12:38:56 PM PDT 24 235653445 ps
T548 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.227838545 Apr 16 12:38:50 PM PDT 24 Apr 16 12:38:52 PM PDT 24 81457214 ps
T549 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.204560572 Apr 16 12:38:53 PM PDT 24 Apr 16 12:38:57 PM PDT 24 131825575 ps
T115 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1821167937 Apr 16 12:38:46 PM PDT 24 Apr 16 12:38:48 PM PDT 24 248537775 ps
T116 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3148259967 Apr 16 12:39:02 PM PDT 24 Apr 16 12:39:10 PM PDT 24 544072543 ps
T550 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.395873071 Apr 16 12:38:54 PM PDT 24 Apr 16 12:38:57 PM PDT 24 88036889 ps
T551 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2565154756 Apr 16 12:38:52 PM PDT 24 Apr 16 12:38:55 PM PDT 24 85857819 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.996735845 Apr 16 12:38:43 PM PDT 24 Apr 16 12:38:45 PM PDT 24 191706141 ps
T553 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2285990381 Apr 16 12:38:36 PM PDT 24 Apr 16 12:38:38 PM PDT 24 237244842 ps
T554 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3256202127 Apr 16 12:38:58 PM PDT 24 Apr 16 12:39:04 PM PDT 24 461234264 ps
T555 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2673902888 Apr 16 12:38:58 PM PDT 24 Apr 16 12:39:05 PM PDT 24 921084748 ps
T556 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4256193056 Apr 16 12:38:39 PM PDT 24 Apr 16 12:38:41 PM PDT 24 156407510 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.854884991 Apr 16 12:38:37 PM PDT 24 Apr 16 12:38:39 PM PDT 24 53777968 ps
T558 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2884480292 Apr 16 12:38:54 PM PDT 24 Apr 16 12:38:58 PM PDT 24 209243372 ps
T117 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.66747541 Apr 16 12:38:36 PM PDT 24 Apr 16 12:38:40 PM PDT 24 948588730 ps
T118 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4090743590 Apr 16 12:38:54 PM PDT 24 Apr 16 12:38:57 PM PDT 24 513071775 ps
T559 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.360722953 Apr 16 12:38:21 PM PDT 24 Apr 16 12:38:24 PM PDT 24 470279797 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.37034060 Apr 16 12:38:31 PM PDT 24 Apr 16 12:38:34 PM PDT 24 85565031 ps
T561 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3891458564 Apr 16 12:38:49 PM PDT 24 Apr 16 12:38:50 PM PDT 24 102815735 ps
T562 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2235702441 Apr 16 12:38:41 PM PDT 24 Apr 16 12:38:43 PM PDT 24 59739206 ps
T563 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.934742248 Apr 16 12:38:42 PM PDT 24 Apr 16 12:38:44 PM PDT 24 142699188 ps
T119 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.768837194 Apr 16 12:38:44 PM PDT 24 Apr 16 12:38:47 PM PDT 24 500612679 ps
T564 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.67784345 Apr 16 12:38:52 PM PDT 24 Apr 16 12:38:56 PM PDT 24 438859536 ps
T565 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2079644297 Apr 16 12:38:35 PM PDT 24 Apr 16 12:38:37 PM PDT 24 68578862 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.142294999 Apr 16 12:38:33 PM PDT 24 Apr 16 12:38:35 PM PDT 24 109024980 ps
T567 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3861391113 Apr 16 12:38:22 PM PDT 24 Apr 16 12:38:24 PM PDT 24 129331036 ps
T568 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2242381601 Apr 16 12:38:35 PM PDT 24 Apr 16 12:38:39 PM PDT 24 272446911 ps
T569 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.416664026 Apr 16 12:38:59 PM PDT 24 Apr 16 12:39:04 PM PDT 24 120774579 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1235527824 Apr 16 12:38:37 PM PDT 24 Apr 16 12:38:41 PM PDT 24 433904887 ps
T571 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3340737514 Apr 16 12:38:33 PM PDT 24 Apr 16 12:38:35 PM PDT 24 195200639 ps
T572 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2234010832 Apr 16 12:38:30 PM PDT 24 Apr 16 12:38:32 PM PDT 24 140565746 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3212653725 Apr 16 12:38:32 PM PDT 24 Apr 16 12:38:36 PM PDT 24 164500153 ps
T574 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2866257324 Apr 16 12:38:30 PM PDT 24 Apr 16 12:38:32 PM PDT 24 172625358 ps
T575 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3848556657 Apr 16 12:38:53 PM PDT 24 Apr 16 12:38:56 PM PDT 24 129208329 ps
T576 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3902751134 Apr 16 12:38:39 PM PDT 24 Apr 16 12:38:41 PM PDT 24 138988058 ps
T577 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1308350955 Apr 16 12:38:52 PM PDT 24 Apr 16 12:38:55 PM PDT 24 187790499 ps
T97 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.519984273 Apr 16 12:38:58 PM PDT 24 Apr 16 12:39:03 PM PDT 24 68783269 ps
T578 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.306467088 Apr 16 12:38:41 PM PDT 24 Apr 16 12:38:44 PM PDT 24 192249768 ps
T579 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1639263102 Apr 16 12:38:41 PM PDT 24 Apr 16 12:38:45 PM PDT 24 417243742 ps
T580 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2709218341 Apr 16 12:38:52 PM PDT 24 Apr 16 12:39:04 PM PDT 24 530778345 ps
T581 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2059467843 Apr 16 12:38:52 PM PDT 24 Apr 16 12:38:54 PM PDT 24 188485335 ps
T582 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.166695460 Apr 16 12:38:51 PM PDT 24 Apr 16 12:38:53 PM PDT 24 79790248 ps
T583 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3324971095 Apr 16 12:38:57 PM PDT 24 Apr 16 12:39:02 PM PDT 24 90276251 ps
T584 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3473868142 Apr 16 12:38:59 PM PDT 24 Apr 16 12:39:04 PM PDT 24 136859147 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1630518058 Apr 16 12:38:51 PM PDT 24 Apr 16 12:38:54 PM PDT 24 870449464 ps
T586 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2865324839 Apr 16 12:38:37 PM PDT 24 Apr 16 12:38:40 PM PDT 24 196865266 ps
T587 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3009204837 Apr 16 12:39:06 PM PDT 24 Apr 16 12:39:11 PM PDT 24 232609498 ps
T588 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3786263991 Apr 16 12:38:54 PM PDT 24 Apr 16 12:38:57 PM PDT 24 235240507 ps
T589 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.318253566 Apr 16 12:38:52 PM PDT 24 Apr 16 12:38:55 PM PDT 24 86746935 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1519602948 Apr 16 12:38:46 PM PDT 24 Apr 16 12:38:48 PM PDT 24 138580659 ps
T591 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1621746318 Apr 16 12:38:38 PM PDT 24 Apr 16 12:38:41 PM PDT 24 126082709 ps
T592 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3488366458 Apr 16 12:38:46 PM PDT 24 Apr 16 12:38:48 PM PDT 24 132822134 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1142639017 Apr 16 12:38:40 PM PDT 24 Apr 16 12:38:42 PM PDT 24 62029247 ps
T594 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1607600106 Apr 16 12:38:53 PM PDT 24 Apr 16 12:38:57 PM PDT 24 195401808 ps
T595 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.667083222 Apr 16 12:38:56 PM PDT 24 Apr 16 12:39:02 PM PDT 24 196943965 ps
T596 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3760468610 Apr 16 12:38:55 PM PDT 24 Apr 16 12:38:58 PM PDT 24 156898077 ps
T597 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2882172318 Apr 16 12:38:39 PM PDT 24 Apr 16 12:38:40 PM PDT 24 93697737 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4015259052 Apr 16 12:38:41 PM PDT 24 Apr 16 12:38:44 PM PDT 24 124790608 ps
T120 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3693751276 Apr 16 12:38:48 PM PDT 24 Apr 16 12:38:52 PM PDT 24 949030270 ps
T599 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2489173158 Apr 16 12:38:57 PM PDT 24 Apr 16 12:39:02 PM PDT 24 155582114 ps
T600 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.921373315 Apr 16 12:38:46 PM PDT 24 Apr 16 12:38:48 PM PDT 24 127284121 ps
T601 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.410176931 Apr 16 12:38:46 PM PDT 24 Apr 16 12:38:50 PM PDT 24 944919479 ps
T602 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.134234937 Apr 16 12:38:53 PM PDT 24 Apr 16 12:38:57 PM PDT 24 345695934 ps
T603 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3405463475 Apr 16 12:38:58 PM PDT 24 Apr 16 12:39:04 PM PDT 24 190538549 ps
T604 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2115539388 Apr 16 12:38:39 PM PDT 24 Apr 16 12:38:42 PM PDT 24 210567527 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.743995176 Apr 16 12:38:31 PM PDT 24 Apr 16 12:38:40 PM PDT 24 1556961527 ps
T606 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3757820860 Apr 16 12:38:18 PM PDT 24 Apr 16 12:38:21 PM PDT 24 344024944 ps
T121 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.138134007 Apr 16 12:38:37 PM PDT 24 Apr 16 12:38:39 PM PDT 24 457484842 ps
T607 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4150087068 Apr 16 12:38:35 PM PDT 24 Apr 16 12:38:37 PM PDT 24 56576562 ps
T608 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1805512147 Apr 16 12:38:54 PM PDT 24 Apr 16 12:38:57 PM PDT 24 117689996 ps
T609 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.662622 Apr 16 12:38:57 PM PDT 24 Apr 16 12:39:01 PM PDT 24 140706555 ps
T610 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2744374085 Apr 16 12:38:41 PM PDT 24 Apr 16 12:38:43 PM PDT 24 129624689 ps
T611 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2362102866 Apr 16 12:38:43 PM PDT 24 Apr 16 12:38:45 PM PDT 24 192276286 ps
T612 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3144293033 Apr 16 12:38:40 PM PDT 24 Apr 16 12:38:51 PM PDT 24 2290631358 ps
T613 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2923271619 Apr 16 12:38:21 PM PDT 24 Apr 16 12:38:23 PM PDT 24 407774819 ps
T614 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3950689139 Apr 16 12:38:40 PM PDT 24 Apr 16 12:38:43 PM PDT 24 129448568 ps
T615 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.142930150 Apr 16 12:39:11 PM PDT 24 Apr 16 12:39:14 PM PDT 24 185784838 ps
T616 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1782097370 Apr 16 12:38:40 PM PDT 24 Apr 16 12:38:42 PM PDT 24 65152997 ps
T617 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4225063428 Apr 16 12:38:51 PM PDT 24 Apr 16 12:38:55 PM PDT 24 518410091 ps
T618 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4094373585 Apr 16 12:38:49 PM PDT 24 Apr 16 12:38:50 PM PDT 24 89695013 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3876583547 Apr 16 12:38:39 PM PDT 24 Apr 16 12:38:43 PM PDT 24 310209770 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1088613552 Apr 16 12:38:26 PM PDT 24 Apr 16 12:38:29 PM PDT 24 364281069 ps

Test location /workspace/coverage/default/39.rstmgr_reset.3961790327
Short name T3
Test name
Test status
Simulation time 979376474 ps
CPU time 5.01 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 200952 kb
Host smart-2474de67-ff57-4196-aa3e-7e53871851ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961790327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3961790327
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.189221849
Short name T12
Test name
Test status
Simulation time 145315159 ps
CPU time 1.75 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 200704 kb
Host smart-0ccbb0dc-7fe1-4f2e-bb01-4c89fdd302eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189221849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.189221849
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3481813086
Short name T61
Test name
Test status
Simulation time 926909890 ps
CPU time 3.01 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:39:00 PM PDT 24
Peak memory 201100 kb
Host smart-cb85d283-7fe3-47c9-996f-ff6238154d27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481813086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3481813086
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1469719845
Short name T11
Test name
Test status
Simulation time 2187581569 ps
CPU time 7.9 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:34 PM PDT 24
Peak memory 218572 kb
Host smart-10167358-9939-4f98-89fc-58e30aaa3003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469719845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1469719845
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3205442835
Short name T69
Test name
Test status
Simulation time 16543449306 ps
CPU time 29.34 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:35 PM PDT 24
Peak memory 218728 kb
Host smart-27c9ea2f-5d27-4688-b785-46af95969619
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205442835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3205442835
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1274438622
Short name T42
Test name
Test status
Simulation time 9503143348 ps
CPU time 30.14 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:29 PM PDT 24
Peak memory 201032 kb
Host smart-4da5537e-085d-4a3f-8f53-d44ee2486e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274438622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1274438622
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2640902588
Short name T86
Test name
Test status
Simulation time 98901028 ps
CPU time 1.42 seconds
Started Apr 16 12:38:31 PM PDT 24
Finished Apr 16 12:38:34 PM PDT 24
Peak memory 209164 kb
Host smart-6a7c29ba-72ab-4952-8586-bd13bcb09ebc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640902588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2640902588
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4046655539
Short name T65
Test name
Test status
Simulation time 64446039 ps
CPU time 0.78 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 200864 kb
Host smart-b1521ecd-9eab-41bd-8ef0-758b19f7ad83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046655539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4046655539
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1684210579
Short name T146
Test name
Test status
Simulation time 96826374 ps
CPU time 0.97 seconds
Started Apr 16 12:39:05 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 200820 kb
Host smart-577f1a69-a990-4b99-930c-9f08e4b1fca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684210579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1684210579
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1546827258
Short name T142
Test name
Test status
Simulation time 277368887 ps
CPU time 1.41 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 200784 kb
Host smart-cb82b8a1-4ab9-4346-8cbe-4562516c012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546827258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1546827258
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3241923251
Short name T91
Test name
Test status
Simulation time 482667461 ps
CPU time 1.87 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 201080 kb
Host smart-d2a6c4b7-f470-4300-a30d-491a9753e7c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241923251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3241923251
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1020062011
Short name T87
Test name
Test status
Simulation time 168692828 ps
CPU time 1.56 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 214500 kb
Host smart-501b483b-3c08-4b04-ba54-79f9c891e6e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020062011 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1020062011
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2239186020
Short name T39
Test name
Test status
Simulation time 2357171844 ps
CPU time 8.61 seconds
Started Apr 16 12:39:18 PM PDT 24
Finished Apr 16 12:39:29 PM PDT 24
Peak memory 218468 kb
Host smart-bc1d9894-4f69-44f8-befa-b466441707bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239186020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2239186020
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1602823938
Short name T38
Test name
Test status
Simulation time 1226156232 ps
CPU time 5.93 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 222776 kb
Host smart-52094140-d757-454c-9303-29d7376534e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602823938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1602823938
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4090743590
Short name T118
Test name
Test status
Simulation time 513071775 ps
CPU time 1.92 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 201088 kb
Host smart-abff1732-b63b-418d-a182-6aba03788d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090743590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.4090743590
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.66747541
Short name T117
Test name
Test status
Simulation time 948588730 ps
CPU time 3.14 seconds
Started Apr 16 12:38:36 PM PDT 24
Finished Apr 16 12:38:40 PM PDT 24
Peak memory 201032 kb
Host smart-40ab197e-160b-4b96-a9e7-471d8b1b7684
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66747541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.66747541
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1084910065
Short name T105
Test name
Test status
Simulation time 64452331 ps
CPU time 0.78 seconds
Started Apr 16 12:38:47 PM PDT 24
Finished Apr 16 12:38:48 PM PDT 24
Peak memory 200824 kb
Host smart-4bcfafa6-8681-4274-bbd3-7d5b4e208ae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084910065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1084910065
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1717274563
Short name T22
Test name
Test status
Simulation time 182997526 ps
CPU time 0.95 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 200444 kb
Host smart-eb44c7c5-9496-45f8-b29c-05bc435af148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717274563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1717274563
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2002253196
Short name T50
Test name
Test status
Simulation time 118911653 ps
CPU time 1.41 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200832 kb
Host smart-01567ec6-d2f0-4ad2-8236-eb3023a29ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002253196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2002253196
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3757820860
Short name T606
Test name
Test status
Simulation time 344024944 ps
CPU time 2.55 seconds
Started Apr 16 12:38:18 PM PDT 24
Finished Apr 16 12:38:21 PM PDT 24
Peak memory 217296 kb
Host smart-a0e2480c-18ad-4093-964f-20265df6d3d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757820860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
757820860
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3144293033
Short name T612
Test name
Test status
Simulation time 2290631358 ps
CPU time 9.61 seconds
Started Apr 16 12:38:40 PM PDT 24
Finished Apr 16 12:38:51 PM PDT 24
Peak memory 217300 kb
Host smart-a46e024f-d3d2-42ef-8c29-360a90bcafea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144293033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
144293033
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3866199732
Short name T544
Test name
Test status
Simulation time 98914026 ps
CPU time 0.82 seconds
Started Apr 16 12:38:25 PM PDT 24
Finished Apr 16 12:38:27 PM PDT 24
Peak memory 200676 kb
Host smart-5a4f8808-f600-4834-935f-13200985f112
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866199732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
866199732
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4015259052
Short name T598
Test name
Test status
Simulation time 124790608 ps
CPU time 1.27 seconds
Started Apr 16 12:38:41 PM PDT 24
Finished Apr 16 12:38:44 PM PDT 24
Peak memory 208960 kb
Host smart-3c6a7ec7-9576-49b3-9254-74f36a502160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015259052 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.4015259052
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3861391113
Short name T567
Test name
Test status
Simulation time 129331036 ps
CPU time 1.06 seconds
Started Apr 16 12:38:22 PM PDT 24
Finished Apr 16 12:38:24 PM PDT 24
Peak memory 200864 kb
Host smart-dcdd8a44-a04f-485e-9f4b-d5c93621d6c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861391113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3861391113
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2923271619
Short name T613
Test name
Test status
Simulation time 407774819 ps
CPU time 1.74 seconds
Started Apr 16 12:38:21 PM PDT 24
Finished Apr 16 12:38:23 PM PDT 24
Peak memory 201072 kb
Host smart-c205abd1-f70a-4fa7-8932-a7babd8aa578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923271619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2923271619
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1088613552
Short name T620
Test name
Test status
Simulation time 364281069 ps
CPU time 2.36 seconds
Started Apr 16 12:38:26 PM PDT 24
Finished Apr 16 12:38:29 PM PDT 24
Peak memory 217384 kb
Host smart-89e51326-f131-43a9-8c85-24d48798df73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088613552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
088613552
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.743995176
Short name T605
Test name
Test status
Simulation time 1556961527 ps
CPU time 8.21 seconds
Started Apr 16 12:38:31 PM PDT 24
Finished Apr 16 12:38:40 PM PDT 24
Peak memory 200892 kb
Host smart-dea7b522-58bc-4a90-bc3c-7bc93801157f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743995176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.743995176
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2234010832
Short name T572
Test name
Test status
Simulation time 140565746 ps
CPU time 1.01 seconds
Started Apr 16 12:38:30 PM PDT 24
Finished Apr 16 12:38:32 PM PDT 24
Peak memory 200740 kb
Host smart-7f3efb99-2e48-4bef-863c-1411110228d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234010832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
234010832
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2866257324
Short name T574
Test name
Test status
Simulation time 172625358 ps
CPU time 1.63 seconds
Started Apr 16 12:38:30 PM PDT 24
Finished Apr 16 12:38:32 PM PDT 24
Peak memory 209312 kb
Host smart-ced7ce79-e154-4e5d-8a3f-7e75a87a1aac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866257324 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2866257324
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1142639017
Short name T593
Test name
Test status
Simulation time 62029247 ps
CPU time 0.81 seconds
Started Apr 16 12:38:40 PM PDT 24
Finished Apr 16 12:38:42 PM PDT 24
Peak memory 200828 kb
Host smart-994b3665-ae14-48d0-b351-a1976ec23633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142639017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1142639017
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3080415813
Short name T57
Test name
Test status
Simulation time 143829924 ps
CPU time 1.15 seconds
Started Apr 16 12:38:34 PM PDT 24
Finished Apr 16 12:38:36 PM PDT 24
Peak memory 200832 kb
Host smart-bf53980a-3526-4de7-b14c-ee7f21b0689e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080415813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3080415813
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3212653725
Short name T573
Test name
Test status
Simulation time 164500153 ps
CPU time 2.25 seconds
Started Apr 16 12:38:32 PM PDT 24
Finished Apr 16 12:38:36 PM PDT 24
Peak memory 217232 kb
Host smart-e245b0f5-7334-4954-9c0d-0042f4f9ba02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212653725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3212653725
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.360722953
Short name T559
Test name
Test status
Simulation time 470279797 ps
CPU time 1.79 seconds
Started Apr 16 12:38:21 PM PDT 24
Finished Apr 16 12:38:24 PM PDT 24
Peak memory 201084 kb
Host smart-60050f1b-c651-4f5c-8d17-60dca6c65ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360722953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
360722953
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3488366458
Short name T592
Test name
Test status
Simulation time 132822134 ps
CPU time 1.33 seconds
Started Apr 16 12:38:46 PM PDT 24
Finished Apr 16 12:38:48 PM PDT 24
Peak memory 209304 kb
Host smart-ac8c54e9-f599-4943-910a-024fd95072ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488366458 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3488366458
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1089928134
Short name T546
Test name
Test status
Simulation time 75901036 ps
CPU time 0.76 seconds
Started Apr 16 12:38:44 PM PDT 24
Finished Apr 16 12:38:45 PM PDT 24
Peak memory 200764 kb
Host smart-22b7b4c1-106d-40d3-8ac2-f46a01f79abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089928134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1089928134
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3786263991
Short name T588
Test name
Test status
Simulation time 235240507 ps
CPU time 1.58 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 200992 kb
Host smart-552f0e0e-c022-4a32-abeb-6e1ce82a025f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786263991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3786263991
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3405463475
Short name T603
Test name
Test status
Simulation time 190538549 ps
CPU time 2.56 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 209148 kb
Host smart-366bfd03-dc27-459b-b418-b86a55d5a427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405463475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3405463475
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4031129629
Short name T55
Test name
Test status
Simulation time 525696049 ps
CPU time 1.89 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:58 PM PDT 24
Peak memory 201124 kb
Host smart-7ce484dd-9dca-4b76-a94b-f299918d123c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031129629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.4031129629
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.192458389
Short name T542
Test name
Test status
Simulation time 79025765 ps
CPU time 0.86 seconds
Started Apr 16 12:39:00 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 200904 kb
Host smart-0bff1bba-505e-49a5-85e8-79979099d43f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192458389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.192458389
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.903158074
Short name T112
Test name
Test status
Simulation time 257273662 ps
CPU time 1.54 seconds
Started Apr 16 12:38:50 PM PDT 24
Finished Apr 16 12:38:52 PM PDT 24
Peak memory 201068 kb
Host smart-f5a6c975-378e-4301-86fe-fc7f37c7141b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903158074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.903158074
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2115539388
Short name T604
Test name
Test status
Simulation time 210567527 ps
CPU time 1.81 seconds
Started Apr 16 12:38:39 PM PDT 24
Finished Apr 16 12:38:42 PM PDT 24
Peak memory 201116 kb
Host smart-25879227-84dd-4bf0-938d-742043ef7ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115539388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2115539388
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3693751276
Short name T120
Test name
Test status
Simulation time 949030270 ps
CPU time 3.26 seconds
Started Apr 16 12:38:48 PM PDT 24
Finished Apr 16 12:38:52 PM PDT 24
Peak memory 201016 kb
Host smart-48e9c139-0814-4e4f-add1-bc9a40e21ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693751276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3693751276
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.204560572
Short name T549
Test name
Test status
Simulation time 131825575 ps
CPU time 1.57 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 209232 kb
Host smart-b2a7868a-f001-4bd4-a92d-627694302124
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204560572 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.204560572
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4094373585
Short name T618
Test name
Test status
Simulation time 89695013 ps
CPU time 0.97 seconds
Started Apr 16 12:38:49 PM PDT 24
Finished Apr 16 12:38:50 PM PDT 24
Peak memory 200876 kb
Host smart-e50eece6-2b4d-4e98-addb-a498ba6f70fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094373585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.4094373585
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.318253566
Short name T589
Test name
Test status
Simulation time 86746935 ps
CPU time 0.96 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:55 PM PDT 24
Peak memory 200928 kb
Host smart-2af367f9-afde-4f9a-9383-4a63dcc4b699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318253566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.318253566
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2709218341
Short name T580
Test name
Test status
Simulation time 530778345 ps
CPU time 3.47 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 217176 kb
Host smart-b39aff4c-5484-487f-ba1c-3c1837cd72d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709218341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2709218341
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1692867897
Short name T56
Test name
Test status
Simulation time 454858402 ps
CPU time 1.96 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 201068 kb
Host smart-519dd85f-ce38-4a65-9144-49d94950d2ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692867897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1692867897
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.662622
Short name T609
Test name
Test status
Simulation time 140706555 ps
CPU time 1.09 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 209144 kb
Host smart-2118b0aa-8e73-40d0-9b56-7dfc0d540e47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662622 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.662622
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2882172318
Short name T597
Test name
Test status
Simulation time 93697737 ps
CPU time 0.85 seconds
Started Apr 16 12:38:39 PM PDT 24
Finished Apr 16 12:38:40 PM PDT 24
Peak memory 200664 kb
Host smart-816204c3-2525-4ea9-8652-ce2d0f77aa16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882172318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2882172318
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.624695170
Short name T107
Test name
Test status
Simulation time 121332878 ps
CPU time 1.05 seconds
Started Apr 16 12:38:51 PM PDT 24
Finished Apr 16 12:38:53 PM PDT 24
Peak memory 200896 kb
Host smart-4c1ddf19-7672-4793-8382-14169d052e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624695170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.624695170
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1639263102
Short name T579
Test name
Test status
Simulation time 417243742 ps
CPU time 2.84 seconds
Started Apr 16 12:38:41 PM PDT 24
Finished Apr 16 12:38:45 PM PDT 24
Peak memory 209268 kb
Host smart-93bee65c-2c82-43b6-a46e-1c4053411026
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639263102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1639263102
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.142930150
Short name T615
Test name
Test status
Simulation time 185784838 ps
CPU time 1.19 seconds
Started Apr 16 12:39:11 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 209212 kb
Host smart-dba9d8f8-b80d-4ccd-a9e0-8188eaaacebc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142930150 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.142930150
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1913629485
Short name T543
Test name
Test status
Simulation time 93147277 ps
CPU time 0.93 seconds
Started Apr 16 12:38:38 PM PDT 24
Finished Apr 16 12:38:40 PM PDT 24
Peak memory 200744 kb
Host smart-b28bece6-c223-4d94-85ed-1648ee17b8f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913629485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1913629485
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3760468610
Short name T596
Test name
Test status
Simulation time 156898077 ps
CPU time 1.13 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:38:58 PM PDT 24
Peak memory 200768 kb
Host smart-aedcd5fc-b072-4111-beee-969a0a80d885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760468610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3760468610
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.134234937
Short name T602
Test name
Test status
Simulation time 345695934 ps
CPU time 2.33 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 209240 kb
Host smart-43677cdf-72f0-4b72-bdb4-9d8ced522733
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134234937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.134234937
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1997374109
Short name T85
Test name
Test status
Simulation time 957542411 ps
CPU time 3.18 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 201176 kb
Host smart-b0b1edc6-d12d-4821-86b0-c6cab6b206a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997374109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1997374109
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1805512147
Short name T608
Test name
Test status
Simulation time 117689996 ps
CPU time 0.94 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 200896 kb
Host smart-83dfed04-d616-4f48-9518-95734530f02c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805512147 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1805512147
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.395873071
Short name T550
Test name
Test status
Simulation time 88036889 ps
CPU time 0.85 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 200840 kb
Host smart-b5f597d0-facf-4b0e-97a0-b41edcfc42c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395873071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.395873071
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3950689139
Short name T614
Test name
Test status
Simulation time 129448568 ps
CPU time 1.24 seconds
Started Apr 16 12:38:40 PM PDT 24
Finished Apr 16 12:38:43 PM PDT 24
Peak memory 201044 kb
Host smart-63af3cbd-304e-4c62-93a9-55a30ab9f783
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950689139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3950689139
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4225063428
Short name T617
Test name
Test status
Simulation time 518410091 ps
CPU time 3.25 seconds
Started Apr 16 12:38:51 PM PDT 24
Finished Apr 16 12:38:55 PM PDT 24
Peak memory 209312 kb
Host smart-63ceb1d2-30de-4753-a539-a851c9dec712
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225063428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4225063428
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1630518058
Short name T585
Test name
Test status
Simulation time 870449464 ps
CPU time 2.92 seconds
Started Apr 16 12:38:51 PM PDT 24
Finished Apr 16 12:38:54 PM PDT 24
Peak memory 200980 kb
Host smart-f3db56e7-9a6e-4a49-b68b-3f494b0f270e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630518058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1630518058
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1308350955
Short name T577
Test name
Test status
Simulation time 187790499 ps
CPU time 1.18 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:55 PM PDT 24
Peak memory 209000 kb
Host smart-a1ec6c3c-01ee-4abf-be80-b132f44ba2a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308350955 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1308350955
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2565154756
Short name T551
Test name
Test status
Simulation time 85857819 ps
CPU time 0.83 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:55 PM PDT 24
Peak memory 200868 kb
Host smart-aa5201cc-2a14-4869-964d-1c3bb31b882c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565154756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2565154756
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1510360367
Short name T109
Test name
Test status
Simulation time 78481889 ps
CPU time 0.93 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 200784 kb
Host smart-2930f103-3d42-4414-b641-ca9da630978c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510360367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1510360367
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.67784345
Short name T564
Test name
Test status
Simulation time 438859536 ps
CPU time 2.89 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:56 PM PDT 24
Peak memory 209400 kb
Host smart-4ce328f0-7625-427d-a550-ebe57ec2022a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67784345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.67784345
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3164209352
Short name T89
Test name
Test status
Simulation time 489608311 ps
CPU time 1.93 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:39:00 PM PDT 24
Peak memory 201012 kb
Host smart-866298f8-7b8d-41ff-96f0-63e137a03fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164209352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3164209352
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.416664026
Short name T569
Test name
Test status
Simulation time 120774579 ps
CPU time 0.95 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200964 kb
Host smart-e73e7b1b-054e-424b-899b-a6117127c5f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416664026 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.416664026
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3324971095
Short name T583
Test name
Test status
Simulation time 90276251 ps
CPU time 0.87 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 200756 kb
Host smart-2242a435-3a04-4455-b24f-8333a7f50606
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324971095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3324971095
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.784237317
Short name T108
Test name
Test status
Simulation time 149329517 ps
CPU time 1.09 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 200648 kb
Host smart-bd0d60a1-9149-4894-aa29-081497f3ba78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784237317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.784237317
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2712822793
Short name T60
Test name
Test status
Simulation time 306027921 ps
CPU time 2.13 seconds
Started Apr 16 12:38:44 PM PDT 24
Finished Apr 16 12:38:48 PM PDT 24
Peak memory 209260 kb
Host smart-a520af13-0798-4911-b4c1-8a8f5ba4308d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712822793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2712822793
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.793666964
Short name T547
Test name
Test status
Simulation time 175567057 ps
CPU time 1.15 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 209008 kb
Host smart-1b0dad3e-47a8-424e-b5a8-1c87ff1a52e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793666964 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.793666964
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3074535884
Short name T111
Test name
Test status
Simulation time 58986064 ps
CPU time 0.83 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200844 kb
Host smart-a22ee110-8587-421d-95d0-9e0741c673bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074535884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3074535884
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1607600106
Short name T594
Test name
Test status
Simulation time 195401808 ps
CPU time 1.39 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 200948 kb
Host smart-0927c2b6-b6e4-4e1e-8734-aebd7acb21d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607600106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1607600106
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.667083222
Short name T595
Test name
Test status
Simulation time 196943965 ps
CPU time 2.7 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 212520 kb
Host smart-f7dbf765-3bf0-4804-bd9e-aabe896e3360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667083222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.667083222
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3256202127
Short name T554
Test name
Test status
Simulation time 461234264 ps
CPU time 1.85 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 201056 kb
Host smart-7eee9a64-d6f3-447d-ab18-5590450f5bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256202127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3256202127
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2884480292
Short name T558
Test name
Test status
Simulation time 209243372 ps
CPU time 1.32 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:58 PM PDT 24
Peak memory 208920 kb
Host smart-0965d4b5-6a14-4882-a17d-d5af6ba6b911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884480292 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2884480292
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.519984273
Short name T97
Test name
Test status
Simulation time 68783269 ps
CPU time 0.84 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200716 kb
Host smart-1413126a-30e6-47ad-8be9-2bf169207633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519984273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.519984273
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3473868142
Short name T584
Test name
Test status
Simulation time 136859147 ps
CPU time 1.38 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 201060 kb
Host smart-6d9624c9-e86b-4026-8cf8-8ad381c3e7f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473868142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3473868142
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3148259967
Short name T116
Test name
Test status
Simulation time 544072543 ps
CPU time 3.31 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 209196 kb
Host smart-5fd6e08b-9032-4fbb-a4e6-7b18c51f98dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148259967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3148259967
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2673902888
Short name T555
Test name
Test status
Simulation time 921084748 ps
CPU time 3.15 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:05 PM PDT 24
Peak memory 201132 kb
Host smart-d8241168-ddfb-4005-b51f-037451c3ace3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673902888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2673902888
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1235527824
Short name T570
Test name
Test status
Simulation time 433904887 ps
CPU time 2.66 seconds
Started Apr 16 12:38:37 PM PDT 24
Finished Apr 16 12:38:41 PM PDT 24
Peak memory 200972 kb
Host smart-62f27713-e51a-419e-b2db-0e981332a922
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235527824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
235527824
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3069383325
Short name T545
Test name
Test status
Simulation time 481074427 ps
CPU time 5.75 seconds
Started Apr 16 12:38:43 PM PDT 24
Finished Apr 16 12:38:50 PM PDT 24
Peak memory 200940 kb
Host smart-262e5d30-561b-469b-b099-2fedf8a0d936
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069383325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
069383325
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.142294999
Short name T566
Test name
Test status
Simulation time 109024980 ps
CPU time 0.82 seconds
Started Apr 16 12:38:33 PM PDT 24
Finished Apr 16 12:38:35 PM PDT 24
Peak memory 200784 kb
Host smart-d2f4475a-3895-49e4-a9af-dd89201c1013
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142294999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.142294999
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1519602948
Short name T590
Test name
Test status
Simulation time 138580659 ps
CPU time 1.38 seconds
Started Apr 16 12:38:46 PM PDT 24
Finished Apr 16 12:38:48 PM PDT 24
Peak memory 209268 kb
Host smart-afef0a6a-a0aa-44e0-bf30-0970906a4f37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519602948 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1519602948
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.37034060
Short name T560
Test name
Test status
Simulation time 85565031 ps
CPU time 0.85 seconds
Started Apr 16 12:38:31 PM PDT 24
Finished Apr 16 12:38:34 PM PDT 24
Peak memory 200860 kb
Host smart-708ad8dd-f448-4ce8-a360-68ee44e38d41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37034060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.37034060
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.648506087
Short name T106
Test name
Test status
Simulation time 143815585 ps
CPU time 1.13 seconds
Started Apr 16 12:38:30 PM PDT 24
Finished Apr 16 12:38:32 PM PDT 24
Peak memory 200928 kb
Host smart-236d441f-dd1e-47f6-bd7d-d857801d2ac3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648506087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.648506087
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.540146136
Short name T88
Test name
Test status
Simulation time 303751227 ps
CPU time 2.42 seconds
Started Apr 16 12:38:44 PM PDT 24
Finished Apr 16 12:38:48 PM PDT 24
Peak memory 209304 kb
Host smart-20e9bcde-be48-44c0-a8d5-8e4b4c416e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540146136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.540146136
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4256193056
Short name T556
Test name
Test status
Simulation time 156407510 ps
CPU time 1.87 seconds
Started Apr 16 12:38:39 PM PDT 24
Finished Apr 16 12:38:41 PM PDT 24
Peak memory 200964 kb
Host smart-083a238d-301e-43ba-a083-ab2baf607957
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256193056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
256193056
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2242381601
Short name T568
Test name
Test status
Simulation time 272446911 ps
CPU time 3.2 seconds
Started Apr 16 12:38:35 PM PDT 24
Finished Apr 16 12:38:39 PM PDT 24
Peak memory 200960 kb
Host smart-771cb09b-6cc1-485d-91ac-22c6251514ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242381601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
242381601
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3902751134
Short name T576
Test name
Test status
Simulation time 138988058 ps
CPU time 0.94 seconds
Started Apr 16 12:38:39 PM PDT 24
Finished Apr 16 12:38:41 PM PDT 24
Peak memory 200876 kb
Host smart-c7b0fee4-7e9d-4313-870a-38bfd87e3b61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902751134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
902751134
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.996735845
Short name T552
Test name
Test status
Simulation time 191706141 ps
CPU time 1.26 seconds
Started Apr 16 12:38:43 PM PDT 24
Finished Apr 16 12:38:45 PM PDT 24
Peak memory 209044 kb
Host smart-0dc39077-49a8-4ad1-92af-7b6170ccd0ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996735845 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.996735845
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.854884991
Short name T557
Test name
Test status
Simulation time 53777968 ps
CPU time 0.71 seconds
Started Apr 16 12:38:37 PM PDT 24
Finished Apr 16 12:38:39 PM PDT 24
Peak memory 200724 kb
Host smart-33b468d3-945b-4dbe-aefc-92dc9a625021
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854884991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.854884991
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2285990381
Short name T553
Test name
Test status
Simulation time 237244842 ps
CPU time 1.5 seconds
Started Apr 16 12:38:36 PM PDT 24
Finished Apr 16 12:38:38 PM PDT 24
Peak memory 201084 kb
Host smart-3d9045aa-6f15-4340-bf15-d078d4a47956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285990381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2285990381
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1969515974
Short name T114
Test name
Test status
Simulation time 338901198 ps
CPU time 2.32 seconds
Started Apr 16 12:38:35 PM PDT 24
Finished Apr 16 12:38:38 PM PDT 24
Peak memory 200988 kb
Host smart-e9520aaf-f132-44c1-8efc-e765baf21d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969515974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1969515974
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3080581137
Short name T92
Test name
Test status
Simulation time 506946386 ps
CPU time 2.04 seconds
Started Apr 16 12:38:42 PM PDT 24
Finished Apr 16 12:38:45 PM PDT 24
Peak memory 201100 kb
Host smart-c94f9cbc-733d-46a3-a2cc-6482f2bff9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080581137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3080581137
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.658453275
Short name T541
Test name
Test status
Simulation time 208112997 ps
CPU time 1.58 seconds
Started Apr 16 12:38:43 PM PDT 24
Finished Apr 16 12:38:45 PM PDT 24
Peak memory 200940 kb
Host smart-b035594e-3d0c-4353-9fef-4c6d0462996f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658453275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.658453275
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.340844524
Short name T540
Test name
Test status
Simulation time 1561339460 ps
CPU time 8.24 seconds
Started Apr 16 12:38:39 PM PDT 24
Finished Apr 16 12:38:48 PM PDT 24
Peak memory 201064 kb
Host smart-17d12ae1-f8c4-4834-8b4f-3b1498832b87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340844524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.340844524
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.921373315
Short name T600
Test name
Test status
Simulation time 127284121 ps
CPU time 0.97 seconds
Started Apr 16 12:38:46 PM PDT 24
Finished Apr 16 12:38:48 PM PDT 24
Peak memory 200784 kb
Host smart-9e918b02-3de7-48a1-98c1-84a9f56f3a07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921373315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.921373315
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2059467843
Short name T581
Test name
Test status
Simulation time 188485335 ps
CPU time 1.14 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:54 PM PDT 24
Peak memory 209188 kb
Host smart-f7d71808-8286-454a-9322-1d5897462d99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059467843 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2059467843
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2079644297
Short name T565
Test name
Test status
Simulation time 68578862 ps
CPU time 0.76 seconds
Started Apr 16 12:38:35 PM PDT 24
Finished Apr 16 12:38:37 PM PDT 24
Peak memory 200724 kb
Host smart-6b4776e8-76a3-4276-9498-7340d11afb6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079644297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2079644297
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3340737514
Short name T571
Test name
Test status
Simulation time 195200639 ps
CPU time 1.33 seconds
Started Apr 16 12:38:33 PM PDT 24
Finished Apr 16 12:38:35 PM PDT 24
Peak memory 200916 kb
Host smart-e01452bf-ffce-471a-8147-c377d95b0515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340737514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3340737514
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3876583547
Short name T619
Test name
Test status
Simulation time 310209770 ps
CPU time 2.14 seconds
Started Apr 16 12:38:39 PM PDT 24
Finished Apr 16 12:38:43 PM PDT 24
Peak memory 212292 kb
Host smart-a2c826af-6479-4f9d-be65-1cace99498db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876583547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3876583547
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.138134007
Short name T121
Test name
Test status
Simulation time 457484842 ps
CPU time 1.8 seconds
Started Apr 16 12:38:37 PM PDT 24
Finished Apr 16 12:38:39 PM PDT 24
Peak memory 201176 kb
Host smart-55bf36fe-055a-4335-8749-d8c99a30ad5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138134007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
138134007
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.934742248
Short name T563
Test name
Test status
Simulation time 142699188 ps
CPU time 1.15 seconds
Started Apr 16 12:38:42 PM PDT 24
Finished Apr 16 12:38:44 PM PDT 24
Peak memory 209060 kb
Host smart-76db6281-ae29-4b7b-b18e-3cf12e25cdf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934742248 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.934742248
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4150087068
Short name T607
Test name
Test status
Simulation time 56576562 ps
CPU time 0.76 seconds
Started Apr 16 12:38:35 PM PDT 24
Finished Apr 16 12:38:37 PM PDT 24
Peak memory 200832 kb
Host smart-5abdfc91-788c-4b67-b055-5c27bf05455c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150087068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.4150087068
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2744374085
Short name T610
Test name
Test status
Simulation time 129624689 ps
CPU time 1.1 seconds
Started Apr 16 12:38:41 PM PDT 24
Finished Apr 16 12:38:43 PM PDT 24
Peak memory 200880 kb
Host smart-89fe68a6-5b1c-491d-bbcb-e85389aa9ba9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744374085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2744374085
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1621746318
Short name T591
Test name
Test status
Simulation time 126082709 ps
CPU time 1.69 seconds
Started Apr 16 12:38:38 PM PDT 24
Finished Apr 16 12:38:41 PM PDT 24
Peak memory 211316 kb
Host smart-80e09d31-138e-4ed8-ba90-9b6f10553366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621746318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1621746318
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.768837194
Short name T119
Test name
Test status
Simulation time 500612679 ps
CPU time 1.93 seconds
Started Apr 16 12:38:44 PM PDT 24
Finished Apr 16 12:38:47 PM PDT 24
Peak memory 200916 kb
Host smart-8c9f1db3-b796-4bc5-9b18-dfd006d23456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768837194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
768837194
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.306467088
Short name T578
Test name
Test status
Simulation time 192249768 ps
CPU time 1.38 seconds
Started Apr 16 12:38:41 PM PDT 24
Finished Apr 16 12:38:44 PM PDT 24
Peak memory 209184 kb
Host smart-80664063-f7a8-44f9-b722-6a2dc187de3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306467088 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.306467088
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2235702441
Short name T562
Test name
Test status
Simulation time 59739206 ps
CPU time 0.82 seconds
Started Apr 16 12:38:41 PM PDT 24
Finished Apr 16 12:38:43 PM PDT 24
Peak memory 200768 kb
Host smart-01493502-47a8-4f94-b36e-24d079c8177b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235702441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2235702441
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3891458564
Short name T561
Test name
Test status
Simulation time 102815735 ps
CPU time 1.24 seconds
Started Apr 16 12:38:49 PM PDT 24
Finished Apr 16 12:38:50 PM PDT 24
Peak memory 201092 kb
Host smart-6cd44212-1cae-4ae0-80c0-e1ea27bcbd20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891458564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3891458564
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2153805691
Short name T58
Test name
Test status
Simulation time 258867210 ps
CPU time 1.99 seconds
Started Apr 16 12:38:39 PM PDT 24
Finished Apr 16 12:38:42 PM PDT 24
Peak memory 209336 kb
Host smart-c5983978-13f9-435d-a1b5-3a6c0ae2a462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153805691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2153805691
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1970912208
Short name T122
Test name
Test status
Simulation time 533870494 ps
CPU time 1.94 seconds
Started Apr 16 12:38:50 PM PDT 24
Finished Apr 16 12:38:53 PM PDT 24
Peak memory 200968 kb
Host smart-15879d28-5c76-44ba-a4f5-e6bba3d74db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970912208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1970912208
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2489173158
Short name T599
Test name
Test status
Simulation time 155582114 ps
CPU time 1.42 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 209268 kb
Host smart-5592871c-4f64-4259-98f1-69eb290499c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489173158 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2489173158
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1782097370
Short name T616
Test name
Test status
Simulation time 65152997 ps
CPU time 0.76 seconds
Started Apr 16 12:38:40 PM PDT 24
Finished Apr 16 12:38:42 PM PDT 24
Peak memory 200692 kb
Host smart-d7f1b07a-c484-462d-9615-f83dc6c81cb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782097370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1782097370
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3682450151
Short name T113
Test name
Test status
Simulation time 235653445 ps
CPU time 1.48 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:56 PM PDT 24
Peak memory 200964 kb
Host smart-abcad3db-d5b9-417a-a4b8-897d17d77b8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682450151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3682450151
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2865324839
Short name T586
Test name
Test status
Simulation time 196865266 ps
CPU time 1.64 seconds
Started Apr 16 12:38:37 PM PDT 24
Finished Apr 16 12:38:40 PM PDT 24
Peak memory 211928 kb
Host smart-44d32c42-6784-45ef-ae0f-e1dca4c80820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865324839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2865324839
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.410176931
Short name T601
Test name
Test status
Simulation time 944919479 ps
CPU time 3.11 seconds
Started Apr 16 12:38:46 PM PDT 24
Finished Apr 16 12:38:50 PM PDT 24
Peak memory 200968 kb
Host smart-a90ee58c-7112-45c4-b029-542f22221d97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410176931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
410176931
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3848556657
Short name T575
Test name
Test status
Simulation time 129208329 ps
CPU time 1.06 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:56 PM PDT 24
Peak memory 201204 kb
Host smart-c3df2b68-4459-4cd4-88e7-ab42605bae0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848556657 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3848556657
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.227838545
Short name T548
Test name
Test status
Simulation time 81457214 ps
CPU time 0.88 seconds
Started Apr 16 12:38:50 PM PDT 24
Finished Apr 16 12:38:52 PM PDT 24
Peak memory 200852 kb
Host smart-c0cc6d86-d6ce-49ec-9602-eadfaca35bb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227838545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.227838545
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3009204837
Short name T587
Test name
Test status
Simulation time 232609498 ps
CPU time 1.61 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 201120 kb
Host smart-4a84ee12-1dcb-4469-b23c-44b817ee473b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009204837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3009204837
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1821167937
Short name T115
Test name
Test status
Simulation time 248537775 ps
CPU time 1.73 seconds
Started Apr 16 12:38:46 PM PDT 24
Finished Apr 16 12:38:48 PM PDT 24
Peak memory 209156 kb
Host smart-b24cbd13-c1e2-4058-8c02-cee0013de25a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821167937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1821167937
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2362102866
Short name T611
Test name
Test status
Simulation time 192276286 ps
CPU time 1.32 seconds
Started Apr 16 12:38:43 PM PDT 24
Finished Apr 16 12:38:45 PM PDT 24
Peak memory 209120 kb
Host smart-9ebeb438-32ee-4b59-932f-3d229fa88c43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362102866 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2362102866
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1067452403
Short name T110
Test name
Test status
Simulation time 67117572 ps
CPU time 0.82 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:56 PM PDT 24
Peak memory 200736 kb
Host smart-08ee1702-d04c-438b-b06b-dc615b420028
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067452403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1067452403
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.166695460
Short name T582
Test name
Test status
Simulation time 79790248 ps
CPU time 1.03 seconds
Started Apr 16 12:38:51 PM PDT 24
Finished Apr 16 12:38:53 PM PDT 24
Peak memory 200808 kb
Host smart-8fb6452d-82a4-460c-812b-71f0a6122108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166695460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.166695460
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4234509680
Short name T59
Test name
Test status
Simulation time 130958455 ps
CPU time 1.86 seconds
Started Apr 16 12:38:37 PM PDT 24
Finished Apr 16 12:38:39 PM PDT 24
Peak memory 211816 kb
Host smart-8006963d-0abd-4f93-8e49-495c1840d8b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234509680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4234509680
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3399437132
Short name T90
Test name
Test status
Simulation time 472831529 ps
CPU time 2.05 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 200948 kb
Host smart-0d2eaed6-14a2-4586-afd2-a19ba58f1cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399437132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3399437132
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3656144537
Short name T408
Test name
Test status
Simulation time 65403063 ps
CPU time 0.74 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200612 kb
Host smart-e70b2789-a185-417b-b7b5-857a34626f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656144537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3656144537
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3534804873
Short name T414
Test name
Test status
Simulation time 1227620914 ps
CPU time 5.36 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 218560 kb
Host smart-72f9f650-0336-46f5-84e2-d316f3cd9a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534804873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3534804873
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1097703174
Short name T131
Test name
Test status
Simulation time 244869837 ps
CPU time 1.12 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 218096 kb
Host smart-3501973f-c32e-4afd-8398-830b6a1d0e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097703174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1097703174
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1390650713
Short name T387
Test name
Test status
Simulation time 200914517 ps
CPU time 0.94 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200576 kb
Host smart-d2b2b23f-cc19-450c-aadf-146f6c2bddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390650713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1390650713
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.858350705
Short name T217
Test name
Test status
Simulation time 724738117 ps
CPU time 3.98 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200964 kb
Host smart-6dd39d4b-ff56-4024-bd65-acd97575ae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858350705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.858350705
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2819012871
Short name T63
Test name
Test status
Simulation time 8299013438 ps
CPU time 13.83 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 218288 kb
Host smart-372d949f-e251-4b53-be5b-aaa455a4c69d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819012871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2819012871
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2197682846
Short name T481
Test name
Test status
Simulation time 101816228 ps
CPU time 0.97 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:56 PM PDT 24
Peak memory 200792 kb
Host smart-cca1afcf-e6cb-418e-9a7d-d723d4ea9a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197682846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2197682846
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3122371657
Short name T531
Test name
Test status
Simulation time 196780576 ps
CPU time 1.36 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 200992 kb
Host smart-6c698ab1-41bb-4b49-8fa9-9aa71f128939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122371657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3122371657
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.560166813
Short name T364
Test name
Test status
Simulation time 1950213218 ps
CPU time 8.42 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 200892 kb
Host smart-fb640162-7082-433e-92ab-b55fee862937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560166813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.560166813
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2521270174
Short name T272
Test name
Test status
Simulation time 373941695 ps
CPU time 1.97 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:55 PM PDT 24
Peak memory 200752 kb
Host smart-3eaa7171-8b49-4dbd-b7bc-87b81465e1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521270174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2521270174
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2235755294
Short name T315
Test name
Test status
Simulation time 109493742 ps
CPU time 0.97 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 200688 kb
Host smart-6801bd9f-7c08-465d-80aa-bbab92dd2950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235755294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2235755294
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2350167278
Short name T250
Test name
Test status
Simulation time 65866285 ps
CPU time 0.76 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200568 kb
Host smart-082cb556-449f-463c-ad88-a2b5e883c4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350167278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2350167278
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3761772509
Short name T40
Test name
Test status
Simulation time 1221951296 ps
CPU time 5.95 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:39:00 PM PDT 24
Peak memory 218856 kb
Host smart-555cea96-b83b-457c-9ed5-f91af9b5288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761772509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3761772509
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2101066310
Short name T128
Test name
Test status
Simulation time 243916284 ps
CPU time 1.01 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:56 PM PDT 24
Peak memory 218128 kb
Host smart-8526fc1d-3e7d-44ab-bb5f-79b9a3f1fd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101066310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2101066310
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.169333254
Short name T270
Test name
Test status
Simulation time 1700759787 ps
CPU time 6.08 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200872 kb
Host smart-86638a1a-b8a2-4757-aa20-f5cb983e8318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169333254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.169333254
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1310676612
Short name T478
Test name
Test status
Simulation time 101161446 ps
CPU time 0.99 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:38:58 PM PDT 24
Peak memory 200712 kb
Host smart-8343fd15-441a-4e68-a608-27978c12641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310676612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1310676612
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1936439895
Short name T516
Test name
Test status
Simulation time 202581184 ps
CPU time 1.36 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 201024 kb
Host smart-48084b3a-ce97-4ec6-a4c3-912b7d4ec268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936439895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1936439895
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.516070649
Short name T417
Test name
Test status
Simulation time 10021770812 ps
CPU time 37.15 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:39 PM PDT 24
Peak memory 201040 kb
Host smart-365b7d20-8c8e-4f2a-a317-b4efcce5e635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516070649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.516070649
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.4259674699
Short name T454
Test name
Test status
Simulation time 107701456 ps
CPU time 0.95 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:00 PM PDT 24
Peak memory 200812 kb
Host smart-21224492-1bb8-4a69-abfb-20e0d1c58fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259674699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.4259674699
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3055187465
Short name T411
Test name
Test status
Simulation time 95690215 ps
CPU time 0.85 seconds
Started Apr 16 12:39:32 PM PDT 24
Finished Apr 16 12:39:34 PM PDT 24
Peak memory 200540 kb
Host smart-1a95a0f0-97e2-4d3b-a68d-e155bb9c3e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055187465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3055187465
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.287928241
Short name T53
Test name
Test status
Simulation time 1218462299 ps
CPU time 5.5 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 222648 kb
Host smart-909ea5e9-7f54-4db4-9a18-20c99b8084b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287928241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.287928241
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2085625472
Short name T71
Test name
Test status
Simulation time 244237912 ps
CPU time 1.09 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 218148 kb
Host smart-bf3a461f-db78-42d3-a4ea-171c15ea28e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085625472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2085625472
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.63385721
Short name T21
Test name
Test status
Simulation time 182371380 ps
CPU time 0.87 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:56 PM PDT 24
Peak memory 200536 kb
Host smart-0f73523e-8224-4d6c-882c-a85f2c18ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63385721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.63385721
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.66513924
Short name T210
Test name
Test status
Simulation time 2064258539 ps
CPU time 6.8 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:39:05 PM PDT 24
Peak memory 200884 kb
Host smart-677006e8-b024-4e5b-bbd4-24da9b7cde41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66513924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.66513924
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3973761114
Short name T496
Test name
Test status
Simulation time 174121245 ps
CPU time 1.25 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 200768 kb
Host smart-452610c3-47a3-4204-95b8-cbe83c07d391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973761114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3973761114
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.4139738470
Short name T319
Test name
Test status
Simulation time 119624494 ps
CPU time 1.14 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 200836 kb
Host smart-53273d39-6a3f-43c6-8454-5fb5e896cf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139738470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.4139738470
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2550810180
Short name T416
Test name
Test status
Simulation time 4164434812 ps
CPU time 18.75 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:22 PM PDT 24
Peak memory 209712 kb
Host smart-47069fa4-ac67-441f-9703-09232ea898be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550810180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2550810180
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2643475198
Short name T310
Test name
Test status
Simulation time 132280576 ps
CPU time 1.6 seconds
Started Apr 16 12:39:05 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200668 kb
Host smart-334e1fd5-cc55-41c2-8c8a-1dc7482334a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643475198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2643475198
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4172694240
Short name T143
Test name
Test status
Simulation time 113412530 ps
CPU time 1.08 seconds
Started Apr 16 12:39:05 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200800 kb
Host smart-a0b2f827-a80f-4ea1-843a-76a6ec97a8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172694240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4172694240
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.4270784679
Short name T358
Test name
Test status
Simulation time 90571153 ps
CPU time 0.81 seconds
Started Apr 16 12:39:17 PM PDT 24
Finished Apr 16 12:39:20 PM PDT 24
Peak memory 200572 kb
Host smart-86a36981-8de1-4713-bab8-ede206c626df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270784679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.4270784679
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.644934447
Short name T508
Test name
Test status
Simulation time 1884051075 ps
CPU time 7.09 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 218524 kb
Host smart-f9848a16-7c06-464a-98cb-524c810e30af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644934447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.644934447
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.840930462
Short name T230
Test name
Test status
Simulation time 244412224 ps
CPU time 1.03 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 218100 kb
Host smart-a4a55258-3c92-4c79-999c-8259800ee8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840930462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.840930462
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.4062186629
Short name T532
Test name
Test status
Simulation time 137694946 ps
CPU time 0.81 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:19 PM PDT 24
Peak memory 200628 kb
Host smart-64342f99-ec9c-49e1-8476-d5a3f9a5687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062186629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.4062186629
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4003560791
Short name T330
Test name
Test status
Simulation time 1519494304 ps
CPU time 5.58 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 200968 kb
Host smart-e4856bbd-81c9-4b05-bf9a-effe8ea1373b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003560791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4003560791
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1390811130
Short name T385
Test name
Test status
Simulation time 137857576 ps
CPU time 1.06 seconds
Started Apr 16 12:39:31 PM PDT 24
Finished Apr 16 12:39:33 PM PDT 24
Peak memory 200732 kb
Host smart-a188c9d0-635c-4bf8-8b11-dfb14e5644c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390811130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1390811130
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1919736870
Short name T434
Test name
Test status
Simulation time 196368098 ps
CPU time 1.35 seconds
Started Apr 16 12:39:13 PM PDT 24
Finished Apr 16 12:39:16 PM PDT 24
Peak memory 201020 kb
Host smart-abfc616f-4c56-4e38-aeb8-25a850adad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919736870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1919736870
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1648460020
Short name T304
Test name
Test status
Simulation time 11700747803 ps
CPU time 43.06 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 201056 kb
Host smart-3473c751-9941-4509-bab4-d6937a96ac4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648460020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1648460020
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.486754320
Short name T345
Test name
Test status
Simulation time 522943803 ps
CPU time 2.73 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200744 kb
Host smart-f99adf27-f952-4288-a45c-576835d6932f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486754320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.486754320
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3169728187
Short name T126
Test name
Test status
Simulation time 97771943 ps
CPU time 0.91 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 200788 kb
Host smart-ade22401-88eb-492d-b443-3ef53384eed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169728187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3169728187
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4160579470
Short name T521
Test name
Test status
Simulation time 71741575 ps
CPU time 0.77 seconds
Started Apr 16 12:39:17 PM PDT 24
Finished Apr 16 12:39:19 PM PDT 24
Peak memory 200576 kb
Host smart-7061587c-aa24-42c9-9ca0-f17f2f9db98d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160579470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4160579470
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3621314094
Short name T440
Test name
Test status
Simulation time 1892551614 ps
CPU time 7.46 seconds
Started Apr 16 12:39:10 PM PDT 24
Finished Apr 16 12:39:19 PM PDT 24
Peak memory 230808 kb
Host smart-b25d5d30-cd5e-4417-b0c9-04e2332251de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621314094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3621314094
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4261699291
Short name T225
Test name
Test status
Simulation time 243660318 ps
CPU time 1.09 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 218008 kb
Host smart-d6055532-86f4-44b7-90e8-58102a428342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261699291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4261699291
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.446898408
Short name T192
Test name
Test status
Simulation time 221901042 ps
CPU time 0.96 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 200528 kb
Host smart-ab6a449b-50bd-4b60-b85f-80bd7358925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446898408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.446898408
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2140206088
Short name T487
Test name
Test status
Simulation time 1614577762 ps
CPU time 6.09 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200892 kb
Host smart-e2ddbc6c-fee8-4950-8551-67fea595455e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140206088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2140206088
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3583757926
Short name T169
Test name
Test status
Simulation time 92412833 ps
CPU time 0.97 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 200768 kb
Host smart-783f222e-dba0-4749-9cf1-17685193e441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583757926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3583757926
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3951591381
Short name T512
Test name
Test status
Simulation time 258155018 ps
CPU time 1.5 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 200976 kb
Host smart-6b7f4477-f541-4b15-a609-800a06e8f9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951591381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3951591381
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1844209259
Short name T249
Test name
Test status
Simulation time 161067456 ps
CPU time 1.32 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200916 kb
Host smart-e172f3a8-39d6-44d5-819d-2d2c3c2db773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844209259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1844209259
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1596201533
Short name T514
Test name
Test status
Simulation time 71817687 ps
CPU time 0.79 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 200528 kb
Host smart-00f63001-398a-4d0d-bf3d-6b33c406bec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596201533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1596201533
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3059396469
Short name T462
Test name
Test status
Simulation time 244275674 ps
CPU time 1.08 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 218096 kb
Host smart-a7992fe9-6e9c-42f6-9de9-aa6d30a9af66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059396469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3059396469
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2004311628
Short name T395
Test name
Test status
Simulation time 199318943 ps
CPU time 0.92 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200500 kb
Host smart-8cfc1cb3-a06c-48cb-8c40-514d94074332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004311628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2004311628
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1403053081
Short name T351
Test name
Test status
Simulation time 899043305 ps
CPU time 4.22 seconds
Started Apr 16 12:39:00 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 200888 kb
Host smart-0d7e4ba8-fba5-4e04-b0de-d2749179ed61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403053081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1403053081
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2385039783
Short name T337
Test name
Test status
Simulation time 103123522 ps
CPU time 1.03 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:39:05 PM PDT 24
Peak memory 200700 kb
Host smart-f3e7bfb3-3ef3-426e-a891-25d5e09b0fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385039783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2385039783
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2430020873
Short name T356
Test name
Test status
Simulation time 114157947 ps
CPU time 1.2 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 200972 kb
Host smart-a3d86fc1-ac6e-44ae-a962-862377454312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430020873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2430020873
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.5977971
Short name T224
Test name
Test status
Simulation time 6163659482 ps
CPU time 20.92 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:20 PM PDT 24
Peak memory 200960 kb
Host smart-60c859f4-dfeb-4c9e-8491-b19ba1fb5c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5977971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.5977971
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.289201096
Short name T179
Test name
Test status
Simulation time 323791623 ps
CPU time 2.15 seconds
Started Apr 16 12:39:15 PM PDT 24
Finished Apr 16 12:39:18 PM PDT 24
Peak memory 200676 kb
Host smart-b6d88031-b9ed-499b-82d6-4fed62c542ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289201096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.289201096
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.233858332
Short name T203
Test name
Test status
Simulation time 127984844 ps
CPU time 0.99 seconds
Started Apr 16 12:39:15 PM PDT 24
Finished Apr 16 12:39:17 PM PDT 24
Peak memory 200788 kb
Host smart-9da1e2ff-6d4d-4f3f-ab13-6eb8dd52e416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233858332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.233858332
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1233106403
Short name T510
Test name
Test status
Simulation time 72982989 ps
CPU time 0.76 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 200544 kb
Host smart-66a4bfe6-f7e6-4e0d-abf0-16c935cb3cf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233106403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1233106403
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2074392572
Short name T489
Test name
Test status
Simulation time 1224533048 ps
CPU time 5.57 seconds
Started Apr 16 12:39:10 PM PDT 24
Finished Apr 16 12:39:17 PM PDT 24
Peak memory 218532 kb
Host smart-e93187f0-4836-4de5-8e5f-b136f49e3da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074392572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2074392572
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.315166807
Short name T349
Test name
Test status
Simulation time 244156667 ps
CPU time 1.13 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 217936 kb
Host smart-c186c4b4-edfc-488a-81c3-192f8fe4c1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315166807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.315166807
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4043812064
Short name T15
Test name
Test status
Simulation time 121690874 ps
CPU time 0.81 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:38:59 PM PDT 24
Peak memory 200528 kb
Host smart-47384fd3-e1e4-4725-b843-98a555024dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043812064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4043812064
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3845084942
Short name T234
Test name
Test status
Simulation time 1466996727 ps
CPU time 5.37 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 200980 kb
Host smart-b3d038ff-1f3f-4252-9551-9f3b8eb7be03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845084942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3845084942
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.791636964
Short name T171
Test name
Test status
Simulation time 103859031 ps
CPU time 0.98 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200780 kb
Host smart-a4636907-9214-4900-843f-b43fb22fc418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791636964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.791636964
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4169586098
Short name T185
Test name
Test status
Simulation time 194119319 ps
CPU time 1.48 seconds
Started Apr 16 12:39:31 PM PDT 24
Finished Apr 16 12:39:33 PM PDT 24
Peak memory 200944 kb
Host smart-ff8e348d-3486-424d-85ab-8d345576c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169586098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4169586098
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.447162155
Short name T215
Test name
Test status
Simulation time 5878198005 ps
CPU time 21.48 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:22 PM PDT 24
Peak memory 200992 kb
Host smart-f23cac0f-640e-4eab-92f8-9af4ef522039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447162155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.447162155
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.113234075
Short name T175
Test name
Test status
Simulation time 409076349 ps
CPU time 2.2 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:16 PM PDT 24
Peak memory 200804 kb
Host smart-a0d15051-d216-4b18-9c5e-6d88023361c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113234075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.113234075
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.56178089
Short name T301
Test name
Test status
Simulation time 145817105 ps
CPU time 1.06 seconds
Started Apr 16 12:39:21 PM PDT 24
Finished Apr 16 12:39:23 PM PDT 24
Peak memory 200820 kb
Host smart-aadda9aa-2b39-42c5-8668-5e5c906adb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56178089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.56178089
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1993457803
Short name T499
Test name
Test status
Simulation time 66982343 ps
CPU time 0.8 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200552 kb
Host smart-c58769b7-fc1e-4e79-892a-5c42194b35d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993457803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1993457803
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3514181037
Short name T470
Test name
Test status
Simulation time 1885296838 ps
CPU time 6.88 seconds
Started Apr 16 12:39:04 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 218496 kb
Host smart-f2372046-4afe-47b1-92f6-437169d4e93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514181037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3514181037
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.714852134
Short name T67
Test name
Test status
Simulation time 244658830 ps
CPU time 1.17 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 218156 kb
Host smart-dbcd858d-94d6-4659-8b88-060300ec2393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714852134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.714852134
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.4268589888
Short name T520
Test name
Test status
Simulation time 93944843 ps
CPU time 0.75 seconds
Started Apr 16 12:39:22 PM PDT 24
Finished Apr 16 12:39:24 PM PDT 24
Peak memory 200600 kb
Host smart-d3871873-3f6f-4ce9-b9d4-46fc46e5ea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268589888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.4268589888
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3088306989
Short name T9
Test name
Test status
Simulation time 968200492 ps
CPU time 4.87 seconds
Started Apr 16 12:39:31 PM PDT 24
Finished Apr 16 12:39:37 PM PDT 24
Peak memory 200804 kb
Host smart-6a4b6e7a-830d-4da0-9dad-fe2884a6d2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088306989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3088306989
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4069123075
Short name T218
Test name
Test status
Simulation time 251738191 ps
CPU time 1.52 seconds
Started Apr 16 12:39:20 PM PDT 24
Finished Apr 16 12:39:23 PM PDT 24
Peak memory 200992 kb
Host smart-3ca57221-d5b8-4cdb-ba40-a6ffee0be3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069123075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4069123075
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.4195491179
Short name T376
Test name
Test status
Simulation time 2462047183 ps
CPU time 10.91 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:20 PM PDT 24
Peak memory 201048 kb
Host smart-97070c98-b72f-4410-896c-e9b2d444cdaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195491179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.4195491179
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1865704105
Short name T305
Test name
Test status
Simulation time 549242877 ps
CPU time 2.79 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200768 kb
Host smart-756da964-3fd7-4e2a-b24e-ba96a9d075b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865704105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1865704105
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.109665152
Short name T529
Test name
Test status
Simulation time 104486552 ps
CPU time 0.91 seconds
Started Apr 16 12:39:07 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200672 kb
Host smart-58013c7d-eaae-4528-ac74-97c76310b404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109665152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.109665152
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4022770983
Short name T189
Test name
Test status
Simulation time 109248743 ps
CPU time 0.86 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 200584 kb
Host smart-1865d2a4-9e26-4bf7-9405-b1206ed7e1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022770983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4022770983
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3338919669
Short name T32
Test name
Test status
Simulation time 2167263994 ps
CPU time 7.74 seconds
Started Apr 16 12:39:04 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 217592 kb
Host smart-d3b725fe-d0f5-40f0-b570-db4532e30334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338919669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3338919669
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.565873489
Short name T435
Test name
Test status
Simulation time 244449812 ps
CPU time 1.02 seconds
Started Apr 16 12:39:10 PM PDT 24
Finished Apr 16 12:39:13 PM PDT 24
Peak memory 218080 kb
Host smart-5c81198f-7d6c-4e26-9624-125d30304214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565873489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.565873489
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.799894528
Short name T244
Test name
Test status
Simulation time 86991274 ps
CPU time 0.72 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200528 kb
Host smart-2d87c55d-d068-49c5-880f-c606db27681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799894528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.799894528
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3357045401
Short name T70
Test name
Test status
Simulation time 1433374413 ps
CPU time 5.19 seconds
Started Apr 16 12:39:09 PM PDT 24
Finished Apr 16 12:39:16 PM PDT 24
Peak memory 200896 kb
Host smart-17b74ab2-721a-4ced-93ab-9fe434ff2d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357045401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3357045401
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1692601307
Short name T524
Test name
Test status
Simulation time 165233006 ps
CPU time 1.25 seconds
Started Apr 16 12:39:14 PM PDT 24
Finished Apr 16 12:39:17 PM PDT 24
Peak memory 200732 kb
Host smart-dd63c2a7-2641-4f4f-b973-ce3f7dee37e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692601307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1692601307
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2825570900
Short name T443
Test name
Test status
Simulation time 128524864 ps
CPU time 1.2 seconds
Started Apr 16 12:39:17 PM PDT 24
Finished Apr 16 12:39:20 PM PDT 24
Peak memory 200992 kb
Host smart-7e78359c-20c5-405e-b724-9dfe9f085a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825570900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2825570900
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.756920372
Short name T101
Test name
Test status
Simulation time 6815957539 ps
CPU time 31.31 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:40 PM PDT 24
Peak memory 201000 kb
Host smart-029ad4cf-6daa-4abf-9f3f-1663f8f8ea96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756920372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.756920372
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2587948306
Short name T170
Test name
Test status
Simulation time 384774873 ps
CPU time 2.44 seconds
Started Apr 16 12:39:14 PM PDT 24
Finished Apr 16 12:39:18 PM PDT 24
Peak memory 200780 kb
Host smart-022531fb-81d8-4a75-b46c-cf747b01143a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587948306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2587948306
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1914208808
Short name T517
Test name
Test status
Simulation time 289276894 ps
CPU time 1.49 seconds
Started Apr 16 12:39:22 PM PDT 24
Finished Apr 16 12:39:24 PM PDT 24
Peak memory 200928 kb
Host smart-51d14046-b008-485d-8dd6-1040329eac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914208808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1914208808
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.810678556
Short name T424
Test name
Test status
Simulation time 82908403 ps
CPU time 0.86 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 200612 kb
Host smart-991c7e1a-8d1c-4226-a058-85ee1d5804e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810678556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.810678556
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.117028291
Short name T52
Test name
Test status
Simulation time 1213914341 ps
CPU time 5.74 seconds
Started Apr 16 12:39:27 PM PDT 24
Finished Apr 16 12:39:39 PM PDT 24
Peak memory 222584 kb
Host smart-777e7f1d-dadd-4949-8b75-69736d9c4f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117028291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.117028291
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.840751505
Short name T1
Test name
Test status
Simulation time 244332052 ps
CPU time 1.06 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:00 PM PDT 24
Peak memory 218016 kb
Host smart-e6e775aa-4756-46b7-8009-189f2a69fa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840751505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.840751505
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.632598702
Short name T465
Test name
Test status
Simulation time 124871215 ps
CPU time 0.84 seconds
Started Apr 16 12:39:17 PM PDT 24
Finished Apr 16 12:39:19 PM PDT 24
Peak memory 200484 kb
Host smart-541af56a-d02f-41d0-b23d-88278e250729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632598702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.632598702
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.511625831
Short name T94
Test name
Test status
Simulation time 1651303136 ps
CPU time 6.27 seconds
Started Apr 16 12:39:05 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 200884 kb
Host smart-dd3404de-d37a-481e-b98d-6fe9f3dd5967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511625831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.511625831
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3227479460
Short name T248
Test name
Test status
Simulation time 170331997 ps
CPU time 1.12 seconds
Started Apr 16 12:39:08 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 200808 kb
Host smart-6729c99f-0b0c-498d-8b54-731e861b2b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227479460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3227479460
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2175929312
Short name T228
Test name
Test status
Simulation time 203024937 ps
CPU time 1.39 seconds
Started Apr 16 12:39:00 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 200980 kb
Host smart-ed515ea8-5361-4c6e-84ca-097bdf2a56ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175929312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2175929312
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1449735266
Short name T507
Test name
Test status
Simulation time 10146451744 ps
CPU time 36.37 seconds
Started Apr 16 12:39:10 PM PDT 24
Finished Apr 16 12:39:48 PM PDT 24
Peak memory 201048 kb
Host smart-562165d5-37e6-48b9-8b45-6453d26467bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449735266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1449735266
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4268252876
Short name T167
Test name
Test status
Simulation time 443983189 ps
CPU time 2.64 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 200740 kb
Host smart-cee205fa-c752-4f54-80b0-879e6c6bc141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268252876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4268252876
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1078347898
Short name T533
Test name
Test status
Simulation time 127204602 ps
CPU time 1.06 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200820 kb
Host smart-74d9ca23-c872-43e2-8da8-def8f35ebb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078347898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1078347898
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.770845540
Short name T267
Test name
Test status
Simulation time 62366778 ps
CPU time 0.74 seconds
Started Apr 16 12:39:30 PM PDT 24
Finished Apr 16 12:39:32 PM PDT 24
Peak memory 200612 kb
Host smart-d71a49fb-fa79-47c1-91b9-9df07a6bb357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770845540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.770845540
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2093782223
Short name T522
Test name
Test status
Simulation time 1228131203 ps
CPU time 5.6 seconds
Started Apr 16 12:39:00 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 217940 kb
Host smart-ba964c3f-0de0-4b8b-830e-290ee6732e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093782223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2093782223
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3241130051
Short name T398
Test name
Test status
Simulation time 244491807 ps
CPU time 1.13 seconds
Started Apr 16 12:39:15 PM PDT 24
Finished Apr 16 12:39:17 PM PDT 24
Peak memory 218112 kb
Host smart-263bd8b6-9508-49eb-a3a7-2de2c50de30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241130051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3241130051
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3958766423
Short name T421
Test name
Test status
Simulation time 87200374 ps
CPU time 0.78 seconds
Started Apr 16 12:39:05 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 200496 kb
Host smart-44d5f7ae-bdc6-4d34-b8d0-6941e709ec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958766423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3958766423
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.351833259
Short name T232
Test name
Test status
Simulation time 835169848 ps
CPU time 4.41 seconds
Started Apr 16 12:39:14 PM PDT 24
Finished Apr 16 12:39:20 PM PDT 24
Peak memory 200940 kb
Host smart-9f67c235-54f4-47a7-b7c1-2f96727280f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351833259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.351833259
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1517854377
Short name T178
Test name
Test status
Simulation time 151873541 ps
CPU time 1.12 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200832 kb
Host smart-34dc55ca-9f18-4089-bbcc-f277f9a2ac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517854377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1517854377
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.4280599208
Short name T243
Test name
Test status
Simulation time 117288727 ps
CPU time 1.14 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 200924 kb
Host smart-33b61108-e65f-4fc7-8de9-3443193c20ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280599208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.4280599208
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1056111951
Short name T513
Test name
Test status
Simulation time 5400148694 ps
CPU time 24.18 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:28 PM PDT 24
Peak memory 200984 kb
Host smart-2be7395d-b20f-427e-94c4-89ff14280044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056111951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1056111951
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3732973400
Short name T83
Test name
Test status
Simulation time 442958584 ps
CPU time 2.54 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 209044 kb
Host smart-6965a4a3-c29c-430e-8ad9-ea5b47eb108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732973400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3732973400
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1752843044
Short name T80
Test name
Test status
Simulation time 177983745 ps
CPU time 1.3 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 200996 kb
Host smart-aa02ae64-7350-46d9-938b-0c14f2a603c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752843044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1752843044
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1298344399
Short name T490
Test name
Test status
Simulation time 80779039 ps
CPU time 0.94 seconds
Started Apr 16 12:39:19 PM PDT 24
Finished Apr 16 12:39:22 PM PDT 24
Peak memory 200536 kb
Host smart-e50f356a-201c-4899-9d8e-146de3060c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298344399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1298344399
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2992383273
Short name T448
Test name
Test status
Simulation time 1234080926 ps
CPU time 5.32 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 218080 kb
Host smart-043dc4a0-8213-4f1d-b84e-7ae972502287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992383273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2992383273
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1618257827
Short name T391
Test name
Test status
Simulation time 244245715 ps
CPU time 1.02 seconds
Started Apr 16 12:39:08 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 217952 kb
Host smart-ac6b2c75-8b57-4698-9819-24ce18180c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618257827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1618257827
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.154710438
Short name T190
Test name
Test status
Simulation time 80527949 ps
CPU time 0.73 seconds
Started Apr 16 12:39:17 PM PDT 24
Finished Apr 16 12:39:19 PM PDT 24
Peak memory 200600 kb
Host smart-5a188854-46cf-46ba-8375-9fdf9d98fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154710438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.154710438
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3212193651
Short name T23
Test name
Test status
Simulation time 1717042320 ps
CPU time 6.5 seconds
Started Apr 16 12:39:17 PM PDT 24
Finished Apr 16 12:39:25 PM PDT 24
Peak memory 200936 kb
Host smart-694862d6-bd89-4152-86ef-cdd276e282f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212193651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3212193651
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.4238839148
Short name T240
Test name
Test status
Simulation time 108824114 ps
CPU time 1.05 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200820 kb
Host smart-bca655f8-2d29-4e01-aa53-75b1d388d290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238839148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4238839148
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.845025701
Short name T467
Test name
Test status
Simulation time 192900959 ps
CPU time 1.36 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200940 kb
Host smart-80f5ce03-64e0-4825-ab8e-963a877cc704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845025701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.845025701
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2386154656
Short name T209
Test name
Test status
Simulation time 4068516794 ps
CPU time 18.64 seconds
Started Apr 16 12:39:04 PM PDT 24
Finished Apr 16 12:39:26 PM PDT 24
Peak memory 200828 kb
Host smart-dd389fa5-9d9e-47b8-b512-13d0cfadbddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386154656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2386154656
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2353073491
Short name T377
Test name
Test status
Simulation time 316444635 ps
CPU time 2.03 seconds
Started Apr 16 12:39:09 PM PDT 24
Finished Apr 16 12:39:13 PM PDT 24
Peak memory 209004 kb
Host smart-427888d7-a5bd-4a20-964a-85579db0f4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353073491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2353073491
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2354076060
Short name T180
Test name
Test status
Simulation time 178946351 ps
CPU time 1.16 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 200804 kb
Host smart-cd338915-fd05-4a30-aa8c-07136da02e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354076060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2354076060
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1206534406
Short name T30
Test name
Test status
Simulation time 1211420023 ps
CPU time 6.15 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 218600 kb
Host smart-a3541ff2-67eb-4f6e-93a8-0f0f112dbfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206534406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1206534406
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.269827939
Short name T370
Test name
Test status
Simulation time 243899921 ps
CPU time 1.13 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 218092 kb
Host smart-b0ea9944-0b7a-473a-81d1-988682598ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269827939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.269827939
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1155996886
Short name T18
Test name
Test status
Simulation time 157274503 ps
CPU time 0.82 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 200592 kb
Host smart-b30ad720-0fdb-4b59-8c9e-4ed89fa75e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155996886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1155996886
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1269065840
Short name T73
Test name
Test status
Simulation time 1709210028 ps
CPU time 5.97 seconds
Started Apr 16 12:39:00 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 201000 kb
Host smart-fa79b832-5c4c-4a08-a246-cac100acb5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269065840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1269065840
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1954393121
Short name T68
Test name
Test status
Simulation time 8272393771 ps
CPU time 16.3 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:23 PM PDT 24
Peak memory 217692 kb
Host smart-2927956a-e93e-446b-a967-c5a50c78f397
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954393121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1954393121
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2881841946
Short name T222
Test name
Test status
Simulation time 177159134 ps
CPU time 1.16 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:00 PM PDT 24
Peak memory 200832 kb
Host smart-8992d592-5fe7-4fad-9a77-a0944592d15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881841946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2881841946
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1746673758
Short name T221
Test name
Test status
Simulation time 116778934 ps
CPU time 1.17 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200964 kb
Host smart-d24e1bfd-23b7-4fa3-a456-bf555644125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746673758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1746673758
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3834792563
Short name T194
Test name
Test status
Simulation time 3413438436 ps
CPU time 14.91 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:17 PM PDT 24
Peak memory 210024 kb
Host smart-489278ea-3ca1-40fc-89c4-14e7eb7b4d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834792563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3834792563
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.4166605667
Short name T197
Test name
Test status
Simulation time 365443495 ps
CPU time 2.06 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200772 kb
Host smart-db1b984b-172b-484e-a6d3-ab5e48208a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166605667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.4166605667
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1623523325
Short name T51
Test name
Test status
Simulation time 93956239 ps
CPU time 0.93 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 200688 kb
Host smart-2b84310c-34d5-4bdc-af1e-446d72f88bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623523325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1623523325
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2807610555
Short name T285
Test name
Test status
Simulation time 68240303 ps
CPU time 0.74 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:38:58 PM PDT 24
Peak memory 200500 kb
Host smart-0d97a3c1-f5a1-4924-b350-6fb2afcda95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807610555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2807610555
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.464682892
Short name T468
Test name
Test status
Simulation time 1892800047 ps
CPU time 7.4 seconds
Started Apr 16 12:39:41 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 222516 kb
Host smart-4b795513-3279-42e7-8c55-973a5ab9d697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464682892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.464682892
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.816921048
Short name T134
Test name
Test status
Simulation time 244325355 ps
CPU time 1.02 seconds
Started Apr 16 12:39:28 PM PDT 24
Finished Apr 16 12:39:31 PM PDT 24
Peak memory 218128 kb
Host smart-b48ea80f-09aa-4586-8711-c4b96d4ddee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816921048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.816921048
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.333573796
Short name T4
Test name
Test status
Simulation time 119535571 ps
CPU time 0.78 seconds
Started Apr 16 12:39:31 PM PDT 24
Finished Apr 16 12:39:33 PM PDT 24
Peak memory 200548 kb
Host smart-96ae51a2-8045-4cb4-853a-1a279517277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333573796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.333573796
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2492331370
Short name T99
Test name
Test status
Simulation time 2135210484 ps
CPU time 8.17 seconds
Started Apr 16 12:39:22 PM PDT 24
Finished Apr 16 12:39:31 PM PDT 24
Peak memory 201000 kb
Host smart-03c032bc-2061-4005-959f-cb911867a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492331370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2492331370
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1949557050
Short name T183
Test name
Test status
Simulation time 107872119 ps
CPU time 1.06 seconds
Started Apr 16 12:39:29 PM PDT 24
Finished Apr 16 12:39:32 PM PDT 24
Peak memory 200816 kb
Host smart-d11c3c3d-1715-471b-ac01-58c9d18bdd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949557050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1949557050
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.778796183
Short name T347
Test name
Test status
Simulation time 200993193 ps
CPU time 1.35 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 200888 kb
Host smart-cec2baf4-37d3-480f-8156-b146e8e349d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778796183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.778796183
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1926761776
Short name T393
Test name
Test status
Simulation time 4377275191 ps
CPU time 15.34 seconds
Started Apr 16 12:39:10 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 201016 kb
Host smart-44b7e913-5692-4634-9fcf-079339112743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926761776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1926761776
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2459883241
Short name T444
Test name
Test status
Simulation time 122498926 ps
CPU time 1.55 seconds
Started Apr 16 12:39:18 PM PDT 24
Finished Apr 16 12:39:22 PM PDT 24
Peak memory 208900 kb
Host smart-c9019f20-33cb-4486-a5df-a6c844172dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459883241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2459883241
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.4024803644
Short name T66
Test name
Test status
Simulation time 74229999 ps
CPU time 0.77 seconds
Started Apr 16 12:39:35 PM PDT 24
Finished Apr 16 12:39:38 PM PDT 24
Peak memory 200544 kb
Host smart-ffcd841f-afb8-4b5d-87ab-ba2f822541f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024803644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.4024803644
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1018503399
Short name T25
Test name
Test status
Simulation time 1903219640 ps
CPU time 7.15 seconds
Started Apr 16 12:39:29 PM PDT 24
Finished Apr 16 12:39:43 PM PDT 24
Peak memory 222432 kb
Host smart-94e10420-cd73-42b2-a094-a90750c26f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018503399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1018503399
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1156101106
Short name T148
Test name
Test status
Simulation time 243457979 ps
CPU time 1.1 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 218076 kb
Host smart-a9266560-76c6-4e74-81ba-5897bf62217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156101106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1156101106
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2687886011
Short name T195
Test name
Test status
Simulation time 238940257 ps
CPU time 0.93 seconds
Started Apr 16 12:39:39 PM PDT 24
Finished Apr 16 12:39:42 PM PDT 24
Peak memory 200560 kb
Host smart-38ea747e-e974-4c31-a8cc-3b88a64f3b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687886011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2687886011
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2485660588
Short name T2
Test name
Test status
Simulation time 2101379732 ps
CPU time 7.25 seconds
Started Apr 16 12:39:16 PM PDT 24
Finished Apr 16 12:39:25 PM PDT 24
Peak memory 200892 kb
Host smart-8285305e-1584-41c4-a666-10a67eb6a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485660588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2485660588
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2709563821
Short name T227
Test name
Test status
Simulation time 185565878 ps
CPU time 1.25 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 200820 kb
Host smart-b401f180-94fc-4fcc-9450-984ec73f42c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709563821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2709563821
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3950538258
Short name T431
Test name
Test status
Simulation time 123151799 ps
CPU time 1.22 seconds
Started Apr 16 12:39:11 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 200892 kb
Host smart-9400fc88-ce6d-4143-9df2-385758b9bc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950538258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3950538258
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2068381205
Short name T402
Test name
Test status
Simulation time 1250086689 ps
CPU time 5.69 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 209092 kb
Host smart-9f9ce1ac-8719-4f03-b4d5-655640806149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068381205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2068381205
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4287366712
Short name T366
Test name
Test status
Simulation time 146195862 ps
CPU time 1.83 seconds
Started Apr 16 12:39:08 PM PDT 24
Finished Apr 16 12:39:17 PM PDT 24
Peak memory 200760 kb
Host smart-4f30502f-63ca-40f5-bacd-2ffeeea9f19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287366712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4287366712
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.390797817
Short name T423
Test name
Test status
Simulation time 107908450 ps
CPU time 0.97 seconds
Started Apr 16 12:39:07 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200732 kb
Host smart-9a3db568-205b-47af-872b-2ecaef0934bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390797817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.390797817
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3575932939
Short name T226
Test name
Test status
Simulation time 79239140 ps
CPU time 0.78 seconds
Started Apr 16 12:39:09 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 200508 kb
Host smart-a6eef121-a676-498d-89a9-622911bb2487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575932939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3575932939
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2654059422
Short name T368
Test name
Test status
Simulation time 1224792192 ps
CPU time 6.03 seconds
Started Apr 16 12:39:23 PM PDT 24
Finished Apr 16 12:39:35 PM PDT 24
Peak memory 218500 kb
Host smart-c3856e64-f3eb-4263-9670-f9f5f567a059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654059422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2654059422
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3122549348
Short name T265
Test name
Test status
Simulation time 244707198 ps
CPU time 1.07 seconds
Started Apr 16 12:39:14 PM PDT 24
Finished Apr 16 12:39:17 PM PDT 24
Peak memory 218272 kb
Host smart-c81439ac-d666-40cb-9c45-72435c227367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122549348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3122549348
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3440898637
Short name T19
Test name
Test status
Simulation time 219615613 ps
CPU time 0.86 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 200556 kb
Host smart-a71e3bc9-ddd9-44d8-a66d-ae83d0020569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440898637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3440898637
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1891098261
Short name T219
Test name
Test status
Simulation time 920578326 ps
CPU time 4.34 seconds
Started Apr 16 12:39:30 PM PDT 24
Finished Apr 16 12:39:35 PM PDT 24
Peak memory 200904 kb
Host smart-8598258c-721f-4829-a8b4-d097d7a3e7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891098261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1891098261
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1400611135
Short name T262
Test name
Test status
Simulation time 162948826 ps
CPU time 1.17 seconds
Started Apr 16 12:39:20 PM PDT 24
Finished Apr 16 12:39:22 PM PDT 24
Peak memory 200796 kb
Host smart-87f6635f-b329-41cb-a284-abccb58f601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400611135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1400611135
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3460230861
Short name T503
Test name
Test status
Simulation time 200000685 ps
CPU time 1.43 seconds
Started Apr 16 12:39:16 PM PDT 24
Finished Apr 16 12:39:19 PM PDT 24
Peak memory 200992 kb
Host smart-3ee5d008-92a9-4e5b-bc4c-12e70a9c3de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460230861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3460230861
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.34811463
Short name T229
Test name
Test status
Simulation time 3051929226 ps
CPU time 10.51 seconds
Started Apr 16 12:39:24 PM PDT 24
Finished Apr 16 12:39:35 PM PDT 24
Peak memory 200972 kb
Host smart-a0cc687d-bb27-4ff7-863b-964e18561bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34811463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.34811463
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3248949209
Short name T54
Test name
Test status
Simulation time 377115251 ps
CPU time 2.09 seconds
Started Apr 16 12:39:35 PM PDT 24
Finished Apr 16 12:39:39 PM PDT 24
Peak memory 200616 kb
Host smart-ea614e1c-cbd1-428f-9369-5b832e1b2f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248949209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3248949209
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1586090272
Short name T77
Test name
Test status
Simulation time 273274796 ps
CPU time 1.39 seconds
Started Apr 16 12:39:27 PM PDT 24
Finished Apr 16 12:39:30 PM PDT 24
Peak memory 200772 kb
Host smart-42c60d35-d6eb-45fb-b9e8-7da7258d5b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586090272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1586090272
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1937048445
Short name T372
Test name
Test status
Simulation time 54155250 ps
CPU time 0.72 seconds
Started Apr 16 12:39:10 PM PDT 24
Finished Apr 16 12:39:12 PM PDT 24
Peak memory 200484 kb
Host smart-1e86e375-5b6f-4a06-abb5-1fd9207974dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937048445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1937048445
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1861145662
Short name T28
Test name
Test status
Simulation time 2363833259 ps
CPU time 7.81 seconds
Started Apr 16 12:39:18 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 218312 kb
Host smart-391a2bc3-7601-4180-8f8f-9a0f776e370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861145662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1861145662
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3225397953
Short name T5
Test name
Test status
Simulation time 243655437 ps
CPU time 1.04 seconds
Started Apr 16 12:39:10 PM PDT 24
Finished Apr 16 12:39:13 PM PDT 24
Peak memory 218132 kb
Host smart-ed5e6299-6fa4-4258-8656-04074330b5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225397953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3225397953
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2106396394
Short name T254
Test name
Test status
Simulation time 200198040 ps
CPU time 0.85 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200452 kb
Host smart-1c72ce54-cf24-4d39-be7a-a165aae9adba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106396394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2106396394
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.648671922
Short name T7
Test name
Test status
Simulation time 1261456071 ps
CPU time 5.62 seconds
Started Apr 16 12:39:08 PM PDT 24
Finished Apr 16 12:39:16 PM PDT 24
Peak memory 200940 kb
Host smart-c82e36a5-9616-4c73-aa83-256e09f80c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648671922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.648671922
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3128817967
Short name T135
Test name
Test status
Simulation time 102487901 ps
CPU time 0.97 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 200784 kb
Host smart-e337f23c-c753-487d-b04f-5ddf67342308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128817967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3128817967
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.507790879
Short name T404
Test name
Test status
Simulation time 113440010 ps
CPU time 1.17 seconds
Started Apr 16 12:39:27 PM PDT 24
Finished Apr 16 12:39:30 PM PDT 24
Peak memory 200964 kb
Host smart-6f22a7f0-7c2e-4b4e-b99a-2433f6e14324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507790879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.507790879
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2262102182
Short name T81
Test name
Test status
Simulation time 9198476192 ps
CPU time 31.36 seconds
Started Apr 16 12:39:27 PM PDT 24
Finished Apr 16 12:40:00 PM PDT 24
Peak memory 210832 kb
Host smart-a611b0c3-6038-4e51-aa09-c602b80d8f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262102182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2262102182
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2483367651
Short name T355
Test name
Test status
Simulation time 134915513 ps
CPU time 1.75 seconds
Started Apr 16 12:39:24 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 200780 kb
Host smart-6013e453-646a-49d6-82e6-b20beaea3c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483367651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2483367651
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.195016307
Short name T193
Test name
Test status
Simulation time 227447579 ps
CPU time 1.51 seconds
Started Apr 16 12:39:18 PM PDT 24
Finished Apr 16 12:39:21 PM PDT 24
Peak memory 201004 kb
Host smart-31dc72fc-df20-44aa-8655-bd067b73f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195016307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.195016307
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.77106484
Short name T382
Test name
Test status
Simulation time 72498359 ps
CPU time 0.78 seconds
Started Apr 16 12:39:13 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 200616 kb
Host smart-32bafe4e-e21f-4152-b80f-0199af65cd29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77106484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.77106484
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2893894388
Short name T367
Test name
Test status
Simulation time 2162372143 ps
CPU time 7.89 seconds
Started Apr 16 12:39:22 PM PDT 24
Finished Apr 16 12:39:31 PM PDT 24
Peak memory 218020 kb
Host smart-7bdfe9d1-f9d4-4995-9695-a8170ad19813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893894388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2893894388
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3999992864
Short name T283
Test name
Test status
Simulation time 244077986 ps
CPU time 1.06 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 218168 kb
Host smart-0db28d6a-a5bb-4792-924f-d69c8d3b5536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999992864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3999992864
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3973951946
Short name T365
Test name
Test status
Simulation time 132153037 ps
CPU time 0.8 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 200580 kb
Host smart-96b7fe3d-00c4-4622-9964-ccd61241897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973951946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3973951946
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1225330656
Short name T165
Test name
Test status
Simulation time 1454343636 ps
CPU time 5.43 seconds
Started Apr 16 12:39:28 PM PDT 24
Finished Apr 16 12:39:39 PM PDT 24
Peak memory 200884 kb
Host smart-a2a7c3ff-a135-4680-be0e-703958bc63d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225330656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1225330656
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.908584809
Short name T155
Test name
Test status
Simulation time 105695542 ps
CPU time 1.02 seconds
Started Apr 16 12:39:34 PM PDT 24
Finished Apr 16 12:39:37 PM PDT 24
Peak memory 200800 kb
Host smart-a27f24a0-df6a-4884-8ce6-7aacc910688a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908584809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.908584809
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2734001333
Short name T303
Test name
Test status
Simulation time 193874532 ps
CPU time 1.45 seconds
Started Apr 16 12:39:11 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 200928 kb
Host smart-bdda9fbe-f5f3-4a7a-a956-4d4fa954bba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734001333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2734001333
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.4174113370
Short name T488
Test name
Test status
Simulation time 9310141214 ps
CPU time 33.57 seconds
Started Apr 16 12:39:17 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 201048 kb
Host smart-c26cd9be-a942-47c2-89e4-616905d9ff84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174113370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4174113370
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2727864396
Short name T445
Test name
Test status
Simulation time 420739263 ps
CPU time 2.41 seconds
Started Apr 16 12:39:28 PM PDT 24
Finished Apr 16 12:39:32 PM PDT 24
Peak memory 208988 kb
Host smart-4bc68796-1bc1-4c87-867a-b1a49fab9090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727864396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2727864396
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3379329836
Short name T138
Test name
Test status
Simulation time 87202633 ps
CPU time 0.9 seconds
Started Apr 16 12:39:31 PM PDT 24
Finished Apr 16 12:39:34 PM PDT 24
Peak memory 200716 kb
Host smart-c9c8f4a1-f7cc-48dd-9624-3068fec7a748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379329836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3379329836
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1640885330
Short name T480
Test name
Test status
Simulation time 74524641 ps
CPU time 0.75 seconds
Started Apr 16 12:39:08 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 200600 kb
Host smart-6d5a0ed2-dbe9-4b55-ac61-9063712b9bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640885330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1640885330
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1453690422
Short name T362
Test name
Test status
Simulation time 245118149 ps
CPU time 1.07 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 218068 kb
Host smart-583a21b7-6836-4bd4-9e88-707fb1c8d761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453690422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1453690422
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3516653181
Short name T14
Test name
Test status
Simulation time 180658249 ps
CPU time 0.91 seconds
Started Apr 16 12:39:35 PM PDT 24
Finished Apr 16 12:39:38 PM PDT 24
Peak memory 200496 kb
Host smart-2989a99c-4666-4857-b2b4-9f2378ac8938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516653181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3516653181
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2509839423
Short name T498
Test name
Test status
Simulation time 950070621 ps
CPU time 4.92 seconds
Started Apr 16 12:39:22 PM PDT 24
Finished Apr 16 12:39:28 PM PDT 24
Peak memory 200944 kb
Host smart-1358ed56-4399-494c-b5a0-82873aa16d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509839423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2509839423
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3147835067
Short name T415
Test name
Test status
Simulation time 158239164 ps
CPU time 1.18 seconds
Started Apr 16 12:39:27 PM PDT 24
Finished Apr 16 12:39:30 PM PDT 24
Peak memory 200788 kb
Host smart-67562f0a-7a34-4d67-b86d-a451547b3da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147835067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3147835067
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3924918672
Short name T352
Test name
Test status
Simulation time 198238296 ps
CPU time 1.34 seconds
Started Apr 16 12:39:18 PM PDT 24
Finished Apr 16 12:39:21 PM PDT 24
Peak memory 200988 kb
Host smart-550b8103-a35d-43ae-adc8-d8e4c83fb71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924918672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3924918672
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1749583668
Short name T300
Test name
Test status
Simulation time 8836569174 ps
CPU time 31.96 seconds
Started Apr 16 12:39:04 PM PDT 24
Finished Apr 16 12:39:40 PM PDT 24
Peak memory 209156 kb
Host smart-fed647ab-b6c8-4cbc-a923-067c87deea82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749583668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1749583668
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.310504188
Short name T281
Test name
Test status
Simulation time 284833059 ps
CPU time 1.89 seconds
Started Apr 16 12:39:16 PM PDT 24
Finished Apr 16 12:39:20 PM PDT 24
Peak memory 200780 kb
Host smart-5256ff78-2925-4e75-95e1-4bedea07d1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310504188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.310504188
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3814386325
Short name T293
Test name
Test status
Simulation time 139105900 ps
CPU time 1.04 seconds
Started Apr 16 12:39:16 PM PDT 24
Finished Apr 16 12:39:18 PM PDT 24
Peak memory 200680 kb
Host smart-f6ab5324-d757-4351-a2d2-ee3dacccc80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814386325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3814386325
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1865690938
Short name T200
Test name
Test status
Simulation time 81869796 ps
CPU time 0.81 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 200508 kb
Host smart-e4ed2f8f-51ea-48e6-a61d-6aa831b451fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865690938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1865690938
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2905845148
Short name T123
Test name
Test status
Simulation time 2160887740 ps
CPU time 7.82 seconds
Started Apr 16 12:39:19 PM PDT 24
Finished Apr 16 12:39:28 PM PDT 24
Peak memory 218112 kb
Host smart-ce4158d5-3406-4473-87bb-cd7384df3cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905845148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2905845148
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.4199927644
Short name T460
Test name
Test status
Simulation time 243484979 ps
CPU time 1.14 seconds
Started Apr 16 12:39:26 PM PDT 24
Finished Apr 16 12:39:28 PM PDT 24
Peak memory 217240 kb
Host smart-561b84d9-b507-43bb-b6d3-0a82d18ed885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199927644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.4199927644
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.177564454
Short name T173
Test name
Test status
Simulation time 160656387 ps
CPU time 0.96 seconds
Started Apr 16 12:39:39 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 200584 kb
Host smart-b8055a37-e70f-41e1-bee4-c411fc871059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177564454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.177564454
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2926576268
Short name T174
Test name
Test status
Simulation time 1413337947 ps
CPU time 5.71 seconds
Started Apr 16 12:39:18 PM PDT 24
Finished Apr 16 12:39:25 PM PDT 24
Peak memory 200992 kb
Host smart-b1351c46-b6af-442b-a9f6-b0148354936b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926576268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2926576268
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3406478691
Short name T383
Test name
Test status
Simulation time 100412176 ps
CPU time 0.97 seconds
Started Apr 16 12:39:17 PM PDT 24
Finished Apr 16 12:39:19 PM PDT 24
Peak memory 200788 kb
Host smart-fcbc3228-b652-4c2e-a669-54879f952dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406478691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3406478691
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.330368944
Short name T439
Test name
Test status
Simulation time 261861102 ps
CPU time 1.45 seconds
Started Apr 16 12:39:26 PM PDT 24
Finished Apr 16 12:39:29 PM PDT 24
Peak memory 200940 kb
Host smart-4e2e2c47-4a74-4962-b237-32bdaaee6136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330368944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.330368944
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2751406937
Short name T302
Test name
Test status
Simulation time 4784567774 ps
CPU time 19.14 seconds
Started Apr 16 12:39:32 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 209192 kb
Host smart-31ffc5cc-52a1-4765-a7e6-622f1878aeda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751406937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2751406937
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1511289048
Short name T371
Test name
Test status
Simulation time 315084275 ps
CPU time 1.91 seconds
Started Apr 16 12:39:04 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 200612 kb
Host smart-be4b9dda-4bf9-4b35-862c-03736e5c193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511289048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1511289048
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.316380757
Short name T390
Test name
Test status
Simulation time 121651475 ps
CPU time 1.02 seconds
Started Apr 16 12:39:13 PM PDT 24
Finished Apr 16 12:39:16 PM PDT 24
Peak memory 200712 kb
Host smart-01b86412-0505-4e95-9451-0072ae2733d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316380757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.316380757
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.867798144
Short name T475
Test name
Test status
Simulation time 65373511 ps
CPU time 0.78 seconds
Started Apr 16 12:39:31 PM PDT 24
Finished Apr 16 12:39:39 PM PDT 24
Peak memory 200556 kb
Host smart-d186cd4f-0203-46a9-bb37-9ddd10d2df21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867798144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.867798144
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.570644828
Short name T27
Test name
Test status
Simulation time 1230823029 ps
CPU time 5.62 seconds
Started Apr 16 12:39:16 PM PDT 24
Finished Apr 16 12:39:23 PM PDT 24
Peak memory 222652 kb
Host smart-bf6b57d5-964c-433a-a248-b259b3715455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570644828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.570644828
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1937917104
Short name T318
Test name
Test status
Simulation time 243650746 ps
CPU time 1.15 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:14 PM PDT 24
Peak memory 218244 kb
Host smart-0b8636c5-51f3-4c4a-843b-4c0f22f2d398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937917104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1937917104
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1419397238
Short name T360
Test name
Test status
Simulation time 204360523 ps
CPU time 0.96 seconds
Started Apr 16 12:39:28 PM PDT 24
Finished Apr 16 12:39:31 PM PDT 24
Peak memory 200628 kb
Host smart-33662cc7-28a4-4e06-b6da-6fba01b6f43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419397238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1419397238
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3954504306
Short name T325
Test name
Test status
Simulation time 903407227 ps
CPU time 4.42 seconds
Started Apr 16 12:39:32 PM PDT 24
Finished Apr 16 12:39:38 PM PDT 24
Peak memory 200964 kb
Host smart-781d2caf-5328-4e45-a3bc-0b534dc991cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954504306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3954504306
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1422567405
Short name T294
Test name
Test status
Simulation time 101817117 ps
CPU time 0.96 seconds
Started Apr 16 12:39:11 PM PDT 24
Finished Apr 16 12:39:18 PM PDT 24
Peak memory 200804 kb
Host smart-3b02a6cd-016c-4c15-af2d-76f43e524e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422567405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1422567405
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3809818509
Short name T163
Test name
Test status
Simulation time 256028605 ps
CPU time 1.44 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 200900 kb
Host smart-dccfbde5-d01e-4e20-b04a-80c067873ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809818509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3809818509
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.678171775
Short name T327
Test name
Test status
Simulation time 6366916813 ps
CPU time 22.48 seconds
Started Apr 16 12:39:23 PM PDT 24
Finished Apr 16 12:39:46 PM PDT 24
Peak memory 200948 kb
Host smart-a18fc323-61d8-47ee-a156-6e0995dbde0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678171775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.678171775
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3152925156
Short name T406
Test name
Test status
Simulation time 126982848 ps
CPU time 1.63 seconds
Started Apr 16 12:39:20 PM PDT 24
Finished Apr 16 12:39:23 PM PDT 24
Peak memory 200704 kb
Host smart-6fccfd46-c5d2-4541-8779-302d6008cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152925156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3152925156
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.542852422
Short name T76
Test name
Test status
Simulation time 121369669 ps
CPU time 1.08 seconds
Started Apr 16 12:39:22 PM PDT 24
Finished Apr 16 12:39:24 PM PDT 24
Peak memory 200768 kb
Host smart-ed81d7e4-8209-4757-b04d-ae85fb66f57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542852422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.542852422
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2659576402
Short name T260
Test name
Test status
Simulation time 70909781 ps
CPU time 0.78 seconds
Started Apr 16 12:39:15 PM PDT 24
Finished Apr 16 12:39:17 PM PDT 24
Peak memory 200576 kb
Host smart-57985845-6b21-47fd-bf1b-791b753b9a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659576402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2659576402
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4238867052
Short name T441
Test name
Test status
Simulation time 1885959854 ps
CPU time 7.03 seconds
Started Apr 16 12:39:15 PM PDT 24
Finished Apr 16 12:39:23 PM PDT 24
Peak memory 217532 kb
Host smart-bdc42b7d-e360-4b16-8a66-ee5758825e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238867052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4238867052
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3595099093
Short name T426
Test name
Test status
Simulation time 243941871 ps
CPU time 1.13 seconds
Started Apr 16 12:39:17 PM PDT 24
Finished Apr 16 12:39:19 PM PDT 24
Peak memory 218048 kb
Host smart-dc0de045-9c11-4f41-8b3a-7e55e4e1baca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595099093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3595099093
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.272942184
Short name T538
Test name
Test status
Simulation time 134822618 ps
CPU time 0.83 seconds
Started Apr 16 12:39:23 PM PDT 24
Finished Apr 16 12:39:25 PM PDT 24
Peak memory 200612 kb
Host smart-89620a99-7fb6-477a-8e40-43442e72d879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272942184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.272942184
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2176356208
Short name T420
Test name
Test status
Simulation time 2086958118 ps
CPU time 8.36 seconds
Started Apr 16 12:39:20 PM PDT 24
Finished Apr 16 12:39:30 PM PDT 24
Peak memory 200992 kb
Host smart-1955a2c9-5667-4624-9379-d95d5e1b367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176356208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2176356208
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1038924320
Short name T363
Test name
Test status
Simulation time 108992422 ps
CPU time 1.08 seconds
Started Apr 16 12:39:37 PM PDT 24
Finished Apr 16 12:39:39 PM PDT 24
Peak memory 200688 kb
Host smart-47648dfe-4bef-4f68-a7c9-791e8f0934f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038924320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1038924320
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1962541597
Short name T252
Test name
Test status
Simulation time 119576764 ps
CPU time 1.16 seconds
Started Apr 16 12:39:18 PM PDT 24
Finished Apr 16 12:39:21 PM PDT 24
Peak memory 200996 kb
Host smart-e2ea86b8-60b8-4708-843c-c874c4cef466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962541597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1962541597
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1249848870
Short name T271
Test name
Test status
Simulation time 567084833 ps
CPU time 2.85 seconds
Started Apr 16 12:39:29 PM PDT 24
Finished Apr 16 12:39:33 PM PDT 24
Peak memory 200980 kb
Host smart-24c53977-0b46-40a6-a647-2fa642dccbbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249848870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1249848870
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1197030305
Short name T273
Test name
Test status
Simulation time 413370819 ps
CPU time 2.18 seconds
Started Apr 16 12:39:24 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 200808 kb
Host smart-60d6e8ba-353e-4088-bdd2-5fba4a8bedc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197030305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1197030305
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2662392672
Short name T149
Test name
Test status
Simulation time 76610109 ps
CPU time 0.83 seconds
Started Apr 16 12:39:27 PM PDT 24
Finished Apr 16 12:39:30 PM PDT 24
Peak memory 200784 kb
Host smart-03becc16-cac2-40a0-9800-db469b238a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662392672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2662392672
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3866636356
Short name T526
Test name
Test status
Simulation time 75746410 ps
CPU time 0.81 seconds
Started Apr 16 12:39:18 PM PDT 24
Finished Apr 16 12:39:21 PM PDT 24
Peak memory 200528 kb
Host smart-e12b085e-dad7-4280-a34d-eca8334d7d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866636356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3866636356
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3933829457
Short name T311
Test name
Test status
Simulation time 1223877555 ps
CPU time 5.59 seconds
Started Apr 16 12:39:32 PM PDT 24
Finished Apr 16 12:39:38 PM PDT 24
Peak memory 222168 kb
Host smart-53e9aa3f-c954-44ed-8914-1b61e1c7af3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933829457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3933829457
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3374846171
Short name T187
Test name
Test status
Simulation time 244108422 ps
CPU time 1.04 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 218148 kb
Host smart-0c6d850d-44c2-4bd6-b341-fb6a48d406ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374846171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3374846171
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2052050860
Short name T308
Test name
Test status
Simulation time 166787465 ps
CPU time 0.83 seconds
Started Apr 16 12:39:19 PM PDT 24
Finished Apr 16 12:39:21 PM PDT 24
Peak memory 200528 kb
Host smart-2851e203-bcca-4572-927e-a845eaa0eedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052050860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2052050860
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1612564857
Short name T314
Test name
Test status
Simulation time 1494074942 ps
CPU time 5.82 seconds
Started Apr 16 12:39:22 PM PDT 24
Finished Apr 16 12:39:28 PM PDT 24
Peak memory 200980 kb
Host smart-e1d23c9d-8d2e-4e99-959d-29f1b769fdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612564857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1612564857
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2562540220
Short name T74
Test name
Test status
Simulation time 150030883 ps
CPU time 1.12 seconds
Started Apr 16 12:39:37 PM PDT 24
Finished Apr 16 12:39:39 PM PDT 24
Peak memory 200792 kb
Host smart-4f7827ef-c45b-464d-93d3-47d823cf63c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562540220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2562540220
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2322247876
Short name T282
Test name
Test status
Simulation time 264495317 ps
CPU time 1.54 seconds
Started Apr 16 12:39:27 PM PDT 24
Finished Apr 16 12:39:30 PM PDT 24
Peak memory 200988 kb
Host smart-a928ed4b-b876-4f9a-a080-b345efc7228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322247876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2322247876
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3379815313
Short name T483
Test name
Test status
Simulation time 8214270549 ps
CPU time 35.12 seconds
Started Apr 16 12:39:24 PM PDT 24
Finished Apr 16 12:40:01 PM PDT 24
Peak memory 201036 kb
Host smart-6cecfaf0-5d3d-408d-b6eb-386f757a0b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379815313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3379815313
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2705629963
Short name T184
Test name
Test status
Simulation time 376699642 ps
CPU time 2.19 seconds
Started Apr 16 12:39:34 PM PDT 24
Finished Apr 16 12:39:37 PM PDT 24
Peak memory 200816 kb
Host smart-5d117149-e36b-489d-9ead-ad04d3089dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705629963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2705629963
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3755077017
Short name T72
Test name
Test status
Simulation time 77694279 ps
CPU time 0.84 seconds
Started Apr 16 12:39:16 PM PDT 24
Finished Apr 16 12:39:18 PM PDT 24
Peak memory 200708 kb
Host smart-e80f001d-15b8-41d0-8eac-ec7333e6245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755077017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3755077017
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3917586508
Short name T257
Test name
Test status
Simulation time 55859370 ps
CPU time 0.71 seconds
Started Apr 16 12:39:05 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 200484 kb
Host smart-2938fdf2-dbd8-43ef-952e-c40edb045397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917586508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3917586508
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1304508680
Short name T407
Test name
Test status
Simulation time 1221282846 ps
CPU time 5.9 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 222632 kb
Host smart-07f49c6c-9ad7-410f-ad0e-a05b099017aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304508680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1304508680
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.4055118208
Short name T323
Test name
Test status
Simulation time 244413926 ps
CPU time 1.04 seconds
Started Apr 16 12:39:04 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 218260 kb
Host smart-52a95134-c701-4123-9714-a94118797e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055118208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.4055118208
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.217018443
Short name T284
Test name
Test status
Simulation time 130076829 ps
CPU time 0.81 seconds
Started Apr 16 12:39:10 PM PDT 24
Finished Apr 16 12:39:12 PM PDT 24
Peak memory 200624 kb
Host smart-28a48a06-bf28-4ddb-9ea4-8ff4732360f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217018443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.217018443
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.946260546
Short name T378
Test name
Test status
Simulation time 820573695 ps
CPU time 4.05 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 200944 kb
Host smart-db199863-bcbf-4313-9afb-de216a94773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946260546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.946260546
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.4239198688
Short name T64
Test name
Test status
Simulation time 16502617520 ps
CPU time 29.91 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:39:29 PM PDT 24
Peak memory 217576 kb
Host smart-e9d70ded-3428-425f-a7ec-2115b4067623
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239198688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.4239198688
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2826067881
Short name T168
Test name
Test status
Simulation time 102490792 ps
CPU time 1.03 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 200668 kb
Host smart-1959747b-aa91-4a58-9e6d-b753f6fc558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826067881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2826067881
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.73038339
Short name T6
Test name
Test status
Simulation time 246291939 ps
CPU time 1.4 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 200900 kb
Host smart-3f6773d8-d078-4a69-b8f6-da5b49346cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73038339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.73038339
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3148198092
Short name T268
Test name
Test status
Simulation time 6782408477 ps
CPU time 24.42 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:28 PM PDT 24
Peak memory 201032 kb
Host smart-2e02a6a6-8cd4-4da8-bce6-4fae2a571a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148198092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3148198092
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1886758116
Short name T422
Test name
Test status
Simulation time 340819385 ps
CPU time 2.33 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 201040 kb
Host smart-7ebc6716-680e-496d-83ee-4c28245ea787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886758116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1886758116
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.68125337
Short name T291
Test name
Test status
Simulation time 147164422 ps
CPU time 1.15 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 200584 kb
Host smart-aaaffe50-2806-4b4a-a65a-63d3da9610df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68125337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.68125337
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2511907043
Short name T307
Test name
Test status
Simulation time 76701102 ps
CPU time 0.81 seconds
Started Apr 16 12:39:21 PM PDT 24
Finished Apr 16 12:39:23 PM PDT 24
Peak memory 200564 kb
Host smart-c73c94bb-2aaa-4386-8f3a-7873a8647707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511907043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2511907043
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3940980258
Short name T450
Test name
Test status
Simulation time 1892470631 ps
CPU time 7.17 seconds
Started Apr 16 12:39:35 PM PDT 24
Finished Apr 16 12:39:44 PM PDT 24
Peak memory 218588 kb
Host smart-38ba1b3a-4f23-4e04-bf5e-abd91d7b83d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940980258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3940980258
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3389516291
Short name T172
Test name
Test status
Simulation time 244654527 ps
CPU time 1.02 seconds
Started Apr 16 12:39:16 PM PDT 24
Finished Apr 16 12:39:18 PM PDT 24
Peak memory 218072 kb
Host smart-64370b78-03a7-47a9-bd55-f298bde51a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389516291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3389516291
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.445913528
Short name T527
Test name
Test status
Simulation time 82161662 ps
CPU time 0.77 seconds
Started Apr 16 12:39:34 PM PDT 24
Finished Apr 16 12:39:36 PM PDT 24
Peak memory 200604 kb
Host smart-d7a09716-21aa-4755-b0f8-2864b1a57f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445913528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.445913528
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.711476576
Short name T103
Test name
Test status
Simulation time 1203114889 ps
CPU time 5.29 seconds
Started Apr 16 12:39:35 PM PDT 24
Finished Apr 16 12:39:42 PM PDT 24
Peak memory 200932 kb
Host smart-a9a86a0b-453f-4a1d-8038-fc4c0e890e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711476576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.711476576
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3813102575
Short name T245
Test name
Test status
Simulation time 150235555 ps
CPU time 1.11 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 200740 kb
Host smart-6d831759-37e3-484d-816d-9d1b68badbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813102575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3813102575
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2290629213
Short name T36
Test name
Test status
Simulation time 119289766 ps
CPU time 1.17 seconds
Started Apr 16 12:39:31 PM PDT 24
Finished Apr 16 12:39:33 PM PDT 24
Peak memory 200960 kb
Host smart-0c1c7a66-4994-4736-bd31-ce29ff695dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290629213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2290629213
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.259472703
Short name T223
Test name
Test status
Simulation time 201943996 ps
CPU time 1.43 seconds
Started Apr 16 12:39:37 PM PDT 24
Finished Apr 16 12:39:40 PM PDT 24
Peak memory 200992 kb
Host smart-cced2e38-e327-47ec-bcd1-a9c92ddb0fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259472703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.259472703
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4060665579
Short name T332
Test name
Test status
Simulation time 308788358 ps
CPU time 1.94 seconds
Started Apr 16 12:39:34 PM PDT 24
Finished Apr 16 12:39:38 PM PDT 24
Peak memory 200712 kb
Host smart-d1d14408-ae6a-4ecf-b538-7c744802a32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060665579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4060665579
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1608469203
Short name T166
Test name
Test status
Simulation time 94119930 ps
CPU time 0.85 seconds
Started Apr 16 12:39:27 PM PDT 24
Finished Apr 16 12:39:30 PM PDT 24
Peak memory 200768 kb
Host smart-b9896980-525f-4054-a9b7-330fe82c03d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608469203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1608469203
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.674426870
Short name T132
Test name
Test status
Simulation time 71817430 ps
CPU time 0.76 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:47 PM PDT 24
Peak memory 200516 kb
Host smart-7364fe5a-ad64-44d7-9add-9713a3b35a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674426870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.674426870
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3194654841
Short name T24
Test name
Test status
Simulation time 1892762412 ps
CPU time 7.06 seconds
Started Apr 16 12:39:33 PM PDT 24
Finished Apr 16 12:39:42 PM PDT 24
Peak memory 222076 kb
Host smart-fb6e6f21-d7ca-4082-a3c0-30bbdcf8bbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194654841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3194654841
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2767345643
Short name T129
Test name
Test status
Simulation time 244278615 ps
CPU time 1.13 seconds
Started Apr 16 12:39:39 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 218052 kb
Host smart-acfc0fed-8ed3-44ef-8e23-29aaf8d143c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767345643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2767345643
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3538266466
Short name T380
Test name
Test status
Simulation time 103993599 ps
CPU time 0.81 seconds
Started Apr 16 12:39:22 PM PDT 24
Finished Apr 16 12:39:23 PM PDT 24
Peak memory 200600 kb
Host smart-280bb934-2a0c-412e-b966-3385702695d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538266466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3538266466
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.4225280373
Short name T384
Test name
Test status
Simulation time 1943506641 ps
CPU time 7.63 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:34 PM PDT 24
Peak memory 200876 kb
Host smart-0e1506fa-20c3-40f6-87fb-5c511dc8b462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225280373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4225280373
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2654756447
Short name T447
Test name
Test status
Simulation time 182664196 ps
CPU time 1.23 seconds
Started Apr 16 12:39:46 PM PDT 24
Finished Apr 16 12:39:49 PM PDT 24
Peak memory 200712 kb
Host smart-bc9b9ca9-1802-440e-940d-be79eadb7107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654756447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2654756447
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2207808891
Short name T211
Test name
Test status
Simulation time 114660377 ps
CPU time 1.2 seconds
Started Apr 16 12:39:33 PM PDT 24
Finished Apr 16 12:39:36 PM PDT 24
Peak memory 200844 kb
Host smart-a4900e72-2560-42a8-aa66-e45e12bdce71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207808891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2207808891
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2160924715
Short name T456
Test name
Test status
Simulation time 3047729410 ps
CPU time 12.84 seconds
Started Apr 16 12:39:46 PM PDT 24
Finished Apr 16 12:40:00 PM PDT 24
Peak memory 201032 kb
Host smart-58c038b4-4d10-49b4-bfb0-94390430d749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160924715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2160924715
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.4276037315
Short name T425
Test name
Test status
Simulation time 119859119 ps
CPU time 1.45 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 200788 kb
Host smart-6a31b5bc-bd42-4087-a2c3-6a9a6aa0a46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276037315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.4276037315
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3991330800
Short name T523
Test name
Test status
Simulation time 139621420 ps
CPU time 1.13 seconds
Started Apr 16 12:39:49 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 200764 kb
Host smart-290840dc-f517-43cf-94df-fd1826037328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991330800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3991330800
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2916930378
Short name T469
Test name
Test status
Simulation time 95820931 ps
CPU time 0.83 seconds
Started Apr 16 12:39:26 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 200508 kb
Host smart-1df989af-9087-461a-86de-b73acad43fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916930378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2916930378
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.4260643694
Short name T344
Test name
Test status
Simulation time 1229495541 ps
CPU time 5.59 seconds
Started Apr 16 12:39:30 PM PDT 24
Finished Apr 16 12:39:36 PM PDT 24
Peak memory 218604 kb
Host smart-c85397da-4ab1-499a-a37c-29610a6cb9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260643694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4260643694
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.786848855
Short name T199
Test name
Test status
Simulation time 243373135 ps
CPU time 1.14 seconds
Started Apr 16 12:39:43 PM PDT 24
Finished Apr 16 12:39:46 PM PDT 24
Peak memory 218044 kb
Host smart-f4175d93-2c1a-4bd6-bdcc-cecf56182387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786848855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.786848855
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4161344952
Short name T438
Test name
Test status
Simulation time 210696224 ps
CPU time 1.06 seconds
Started Apr 16 12:39:43 PM PDT 24
Finished Apr 16 12:39:46 PM PDT 24
Peak memory 200628 kb
Host smart-0aedd8ef-8499-4e88-9ada-5c97f99240ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161344952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4161344952
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1751210678
Short name T242
Test name
Test status
Simulation time 1417373098 ps
CPU time 5.52 seconds
Started Apr 16 12:39:38 PM PDT 24
Finished Apr 16 12:39:45 PM PDT 24
Peak memory 200972 kb
Host smart-e9090ff3-1677-4f68-88fb-fc24b6fbebb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751210678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1751210678
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1971156174
Short name T10
Test name
Test status
Simulation time 144407032 ps
CPU time 1.13 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200804 kb
Host smart-52141a7a-ed90-497d-a48d-d3755c61d352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971156174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1971156174
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.995887418
Short name T186
Test name
Test status
Simulation time 119445300 ps
CPU time 1.21 seconds
Started Apr 16 12:39:30 PM PDT 24
Finished Apr 16 12:39:32 PM PDT 24
Peak memory 201000 kb
Host smart-8cc7b024-843d-469e-8584-1b79e338887d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995887418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.995887418
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.391808372
Short name T436
Test name
Test status
Simulation time 7095081260 ps
CPU time 25.61 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:40:12 PM PDT 24
Peak memory 201096 kb
Host smart-64e58a92-00f2-4408-9e16-9a0f9e125cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391808372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.391808372
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3543783057
Short name T286
Test name
Test status
Simulation time 422875963 ps
CPU time 2.25 seconds
Started Apr 16 12:39:40 PM PDT 24
Finished Apr 16 12:39:45 PM PDT 24
Peak memory 200740 kb
Host smart-8ed4c24c-1599-4c3f-be89-94755562e368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543783057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3543783057
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3936751374
Short name T477
Test name
Test status
Simulation time 124697459 ps
CPU time 1.05 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 200748 kb
Host smart-bffdba36-581b-4fb5-af24-96c8f68eaad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936751374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3936751374
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3337198302
Short name T35
Test name
Test status
Simulation time 64743775 ps
CPU time 0.7 seconds
Started Apr 16 12:39:39 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 200624 kb
Host smart-7e318e98-e643-45ab-98bd-6e21b879f50b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337198302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3337198302
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2994691045
Short name T534
Test name
Test status
Simulation time 1233655690 ps
CPU time 5.47 seconds
Started Apr 16 12:39:37 PM PDT 24
Finished Apr 16 12:39:44 PM PDT 24
Peak memory 217936 kb
Host smart-fe9fe46f-418e-4769-b34b-089f42c887e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994691045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2994691045
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3918158752
Short name T539
Test name
Test status
Simulation time 245616120 ps
CPU time 1.03 seconds
Started Apr 16 12:39:39 PM PDT 24
Finished Apr 16 12:39:42 PM PDT 24
Peak memory 217968 kb
Host smart-558993f1-f764-49ad-bb52-6bd637ff967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918158752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3918158752
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.133526338
Short name T20
Test name
Test status
Simulation time 79121010 ps
CPU time 0.75 seconds
Started Apr 16 12:39:41 PM PDT 24
Finished Apr 16 12:39:44 PM PDT 24
Peak memory 200580 kb
Host smart-7bbd5984-a2fd-4b90-8a7e-b7ef823e2005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133526338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.133526338
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1799938085
Short name T102
Test name
Test status
Simulation time 1055454764 ps
CPU time 5.08 seconds
Started Apr 16 12:39:36 PM PDT 24
Finished Apr 16 12:39:43 PM PDT 24
Peak memory 200952 kb
Host smart-cc3589bb-9ee5-43a2-99f6-c487b5089f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799938085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1799938085
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1748525482
Short name T333
Test name
Test status
Simulation time 143943832 ps
CPU time 1.15 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:27 PM PDT 24
Peak memory 200756 kb
Host smart-ada3f37d-1494-41c6-91e6-bf4bac177d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748525482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1748525482
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1370043083
Short name T497
Test name
Test status
Simulation time 193368085 ps
CPU time 1.34 seconds
Started Apr 16 12:39:42 PM PDT 24
Finished Apr 16 12:39:44 PM PDT 24
Peak memory 201012 kb
Host smart-8337a776-45c4-4240-8303-18dc346f2ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370043083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1370043083
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2083959542
Short name T158
Test name
Test status
Simulation time 6119327201 ps
CPU time 22.36 seconds
Started Apr 16 12:39:34 PM PDT 24
Finished Apr 16 12:39:59 PM PDT 24
Peak memory 200968 kb
Host smart-2936ec4c-6f4d-479a-b09f-a795748a1952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083959542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2083959542
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1344090741
Short name T84
Test name
Test status
Simulation time 141239976 ps
CPU time 1.8 seconds
Started Apr 16 12:39:46 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 200728 kb
Host smart-02d38009-5493-4804-89bb-440725970ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344090741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1344090741
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2781546536
Short name T299
Test name
Test status
Simulation time 205120082 ps
CPU time 1.43 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:48 PM PDT 24
Peak memory 200664 kb
Host smart-c05fbe37-8a5a-45b1-b6e1-026ac36bda02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781546536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2781546536
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3765501066
Short name T154
Test name
Test status
Simulation time 66815730 ps
CPU time 0.76 seconds
Started Apr 16 12:39:37 PM PDT 24
Finished Apr 16 12:39:39 PM PDT 24
Peak memory 200548 kb
Host smart-20480b4e-4121-46a8-aedc-abaa32897ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765501066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3765501066
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.524006929
Short name T341
Test name
Test status
Simulation time 2362004847 ps
CPU time 8.33 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:40:00 PM PDT 24
Peak memory 218308 kb
Host smart-f8e45607-fdfb-4469-968e-67c01fa90135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524006929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.524006929
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2648499609
Short name T482
Test name
Test status
Simulation time 244608386 ps
CPU time 1.19 seconds
Started Apr 16 12:39:33 PM PDT 24
Finished Apr 16 12:39:35 PM PDT 24
Peak memory 218128 kb
Host smart-bdfbd9bb-c292-4929-93cc-59e4828d53aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648499609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2648499609
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3959773077
Short name T241
Test name
Test status
Simulation time 212491622 ps
CPU time 0.96 seconds
Started Apr 16 12:39:27 PM PDT 24
Finished Apr 16 12:39:29 PM PDT 24
Peak memory 200568 kb
Host smart-60a28fe9-2830-482e-93c0-b95d2252504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959773077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3959773077
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.582394669
Short name T201
Test name
Test status
Simulation time 1672676690 ps
CPU time 6.29 seconds
Started Apr 16 12:39:35 PM PDT 24
Finished Apr 16 12:39:43 PM PDT 24
Peak memory 200848 kb
Host smart-fcd2c040-9bb9-445f-a964-3388f98bcf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582394669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.582394669
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.4277248758
Short name T266
Test name
Test status
Simulation time 178447462 ps
CPU time 1.31 seconds
Started Apr 16 12:39:38 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 200776 kb
Host smart-0f901729-eaf4-4818-965c-e51c71c83d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277248758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.4277248758
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.263724792
Short name T410
Test name
Test status
Simulation time 127414456 ps
CPU time 1.24 seconds
Started Apr 16 12:39:41 PM PDT 24
Finished Apr 16 12:39:44 PM PDT 24
Peak memory 200800 kb
Host smart-a8953d3b-f48d-4403-b595-b86c35e47753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263724792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.263724792
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3688482732
Short name T78
Test name
Test status
Simulation time 17269744255 ps
CPU time 54.67 seconds
Started Apr 16 12:39:42 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 200972 kb
Host smart-eb0e2496-e34c-477d-b3bb-c1c704fd0ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688482732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3688482732
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1662422971
Short name T151
Test name
Test status
Simulation time 134775537 ps
CPU time 1.73 seconds
Started Apr 16 12:39:38 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 200804 kb
Host smart-178e9ce7-0e33-4109-8cab-dd689e3973d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662422971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1662422971
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.401726369
Short name T127
Test name
Test status
Simulation time 62736792 ps
CPU time 0.81 seconds
Started Apr 16 12:39:26 PM PDT 24
Finished Apr 16 12:39:28 PM PDT 24
Peak memory 200812 kb
Host smart-aa1a17be-668b-486c-b6af-0cd85601ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401726369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.401726369
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.960222849
Short name T379
Test name
Test status
Simulation time 63900827 ps
CPU time 0.76 seconds
Started Apr 16 12:39:41 PM PDT 24
Finished Apr 16 12:39:44 PM PDT 24
Peak memory 200516 kb
Host smart-5d98641b-45b8-4cd8-9ca5-66cbd779d930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960222849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.960222849
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1491156507
Short name T287
Test name
Test status
Simulation time 1905246315 ps
CPU time 7.36 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:40:04 PM PDT 24
Peak memory 222512 kb
Host smart-0842c157-43dd-43ed-9c11-d0c0fc432760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491156507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1491156507
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1589925476
Short name T251
Test name
Test status
Simulation time 244362996 ps
CPU time 1.11 seconds
Started Apr 16 12:39:34 PM PDT 24
Finished Apr 16 12:39:36 PM PDT 24
Peak memory 218172 kb
Host smart-7c7a7ad9-dc48-401e-958f-fca8daabb9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589925476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1589925476
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.4259409131
Short name T369
Test name
Test status
Simulation time 153481761 ps
CPU time 0.83 seconds
Started Apr 16 12:39:42 PM PDT 24
Finished Apr 16 12:39:44 PM PDT 24
Peak memory 200624 kb
Host smart-8c804359-3bf6-4b73-880e-25613dfc9210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259409131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.4259409131
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3105433009
Short name T96
Test name
Test status
Simulation time 1767373899 ps
CPU time 6.59 seconds
Started Apr 16 12:40:01 PM PDT 24
Finished Apr 16 12:40:08 PM PDT 24
Peak memory 200952 kb
Host smart-738817d5-f098-41a7-a7ec-1e54cc262ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105433009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3105433009
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.74566604
Short name T403
Test name
Test status
Simulation time 149734229 ps
CPU time 1.13 seconds
Started Apr 16 12:39:38 PM PDT 24
Finished Apr 16 12:39:40 PM PDT 24
Peak memory 200772 kb
Host smart-9cc3636c-fae8-42da-98ce-f68fcd54cd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74566604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.74566604
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.103973480
Short name T46
Test name
Test status
Simulation time 195564229 ps
CPU time 1.41 seconds
Started Apr 16 12:39:31 PM PDT 24
Finished Apr 16 12:39:34 PM PDT 24
Peak memory 200916 kb
Host smart-a406e434-9aa1-4107-8adb-45ef0f420db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103973480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.103973480
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3046987301
Short name T139
Test name
Test status
Simulation time 4434314034 ps
CPU time 17.5 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:40:10 PM PDT 24
Peak memory 210032 kb
Host smart-7d37d954-0113-423d-9f8c-a8f4ac94ce46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046987301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3046987301
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1659622941
Short name T350
Test name
Test status
Simulation time 124748201 ps
CPU time 1.57 seconds
Started Apr 16 12:39:49 PM PDT 24
Finished Apr 16 12:39:53 PM PDT 24
Peak memory 208976 kb
Host smart-4917c883-2e6d-4891-bb71-b6e33f577cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659622941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1659622941
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1635438946
Short name T418
Test name
Test status
Simulation time 116736509 ps
CPU time 1.07 seconds
Started Apr 16 12:39:38 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 200828 kb
Host smart-f910aa8d-a5b6-4a47-8d4e-ff58418b2ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635438946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1635438946
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3959525802
Short name T182
Test name
Test status
Simulation time 60874069 ps
CPU time 0.73 seconds
Started Apr 16 12:39:37 PM PDT 24
Finished Apr 16 12:39:40 PM PDT 24
Peak memory 200576 kb
Host smart-38ce7ca5-da75-4f3e-80a3-fef455b94936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959525802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3959525802
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2399816925
Short name T437
Test name
Test status
Simulation time 1227869436 ps
CPU time 5.69 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 222660 kb
Host smart-45b993f3-4fcf-4eac-be8a-24954826fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399816925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2399816925
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.4058543936
Short name T153
Test name
Test status
Simulation time 244910946 ps
CPU time 1.02 seconds
Started Apr 16 12:39:49 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 217984 kb
Host smart-e95b929c-059d-47b6-ae33-732926a5dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058543936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.4058543936
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.761880488
Short name T216
Test name
Test status
Simulation time 183871208 ps
CPU time 0.85 seconds
Started Apr 16 12:39:36 PM PDT 24
Finished Apr 16 12:39:38 PM PDT 24
Peak memory 200556 kb
Host smart-5b6a5729-1b52-464b-b01c-ad02d675b5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761880488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.761880488
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.569853777
Short name T263
Test name
Test status
Simulation time 1721466665 ps
CPU time 6.13 seconds
Started Apr 16 12:39:46 PM PDT 24
Finished Apr 16 12:39:53 PM PDT 24
Peak memory 200856 kb
Host smart-db3a6185-6431-4c3a-be87-3ebfa309071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569853777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.569853777
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2689801706
Short name T191
Test name
Test status
Simulation time 106820712 ps
CPU time 0.98 seconds
Started Apr 16 12:39:46 PM PDT 24
Finished Apr 16 12:39:49 PM PDT 24
Peak memory 200828 kb
Host smart-9f6306eb-5269-4020-9242-12db0cd4d1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689801706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2689801706
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3918353884
Short name T49
Test name
Test status
Simulation time 122035254 ps
CPU time 1.19 seconds
Started Apr 16 12:39:49 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 200972 kb
Host smart-4f674c80-fbc2-460c-8b18-88f668a4be4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918353884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3918353884
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1484929807
Short name T515
Test name
Test status
Simulation time 15507372083 ps
CPU time 50.51 seconds
Started Apr 16 12:39:39 PM PDT 24
Finished Apr 16 12:40:31 PM PDT 24
Peak memory 201044 kb
Host smart-ea030cea-eee6-4d8f-b31d-e85369e44988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484929807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1484929807
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.78988523
Short name T428
Test name
Test status
Simulation time 518371532 ps
CPU time 2.62 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 200824 kb
Host smart-5c89a7a0-b290-4718-aec3-1553f2c7c2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78988523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.78988523
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.308606554
Short name T373
Test name
Test status
Simulation time 117732823 ps
CPU time 1.03 seconds
Started Apr 16 12:39:46 PM PDT 24
Finished Apr 16 12:39:49 PM PDT 24
Peak memory 200712 kb
Host smart-2cad9440-c2a8-474e-9cce-e57dffc1df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308606554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.308606554
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1337404087
Short name T394
Test name
Test status
Simulation time 64818206 ps
CPU time 0.77 seconds
Started Apr 16 12:39:30 PM PDT 24
Finished Apr 16 12:39:33 PM PDT 24
Peak memory 200608 kb
Host smart-3bc0bcd6-6afc-48fc-ae71-62998d62387b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337404087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1337404087
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1214459590
Short name T31
Test name
Test status
Simulation time 1886054644 ps
CPU time 6.76 seconds
Started Apr 16 12:39:41 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 230340 kb
Host smart-91adc11c-c684-4a63-9d2f-8c925a3c3561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214459590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1214459590
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1341082163
Short name T324
Test name
Test status
Simulation time 244451428 ps
CPU time 1.14 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 218168 kb
Host smart-9d49157c-2399-48a6-9ce0-32ba68c98ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341082163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1341082163
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.892865162
Short name T331
Test name
Test status
Simulation time 169942791 ps
CPU time 0.89 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:49 PM PDT 24
Peak memory 200612 kb
Host smart-1cdd91a8-0751-4a6c-b396-9a8b24bbc09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892865162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.892865162
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1427513446
Short name T392
Test name
Test status
Simulation time 1594166557 ps
CPU time 6.74 seconds
Started Apr 16 12:39:40 PM PDT 24
Finished Apr 16 12:39:49 PM PDT 24
Peak memory 200928 kb
Host smart-485cb99d-10cd-49cc-9b9a-b384c5fa0723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427513446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1427513446
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.991795459
Short name T427
Test name
Test status
Simulation time 169898680 ps
CPU time 1.25 seconds
Started Apr 16 12:39:39 PM PDT 24
Finished Apr 16 12:39:42 PM PDT 24
Peak memory 201048 kb
Host smart-ee8f54c4-6990-4cfc-9093-289ddfac4999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991795459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.991795459
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1257838065
Short name T357
Test name
Test status
Simulation time 201704564 ps
CPU time 1.44 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:48 PM PDT 24
Peak memory 200972 kb
Host smart-5000797d-3312-4023-91e6-70ee01216927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257838065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1257838065
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3780932894
Short name T290
Test name
Test status
Simulation time 10568905103 ps
CPU time 37.49 seconds
Started Apr 16 12:39:43 PM PDT 24
Finished Apr 16 12:40:22 PM PDT 24
Peak memory 210964 kb
Host smart-58a47b39-d75e-433a-9f7d-0eab0a93988f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780932894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3780932894
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3380733379
Short name T196
Test name
Test status
Simulation time 319876558 ps
CPU time 2.14 seconds
Started Apr 16 12:39:41 PM PDT 24
Finished Apr 16 12:39:45 PM PDT 24
Peak memory 200768 kb
Host smart-4f1ae991-45f0-4a0b-8f4d-545576e19f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380733379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3380733379
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2537521862
Short name T340
Test name
Test status
Simulation time 185456190 ps
CPU time 1.22 seconds
Started Apr 16 12:39:38 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 201044 kb
Host smart-23b1d4c7-dd93-4141-8734-6e51064a761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537521862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2537521862
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2940249936
Short name T430
Test name
Test status
Simulation time 85233743 ps
CPU time 0.79 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:49 PM PDT 24
Peak memory 200504 kb
Host smart-2dd9cc8a-b506-4c2c-81da-f9159d8fb3aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940249936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2940249936
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.883074522
Short name T44
Test name
Test status
Simulation time 1898661961 ps
CPU time 6.85 seconds
Started Apr 16 12:39:42 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 217444 kb
Host smart-b0861bfb-1f3e-4d3e-825a-bda357063ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883074522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.883074522
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1094325027
Short name T233
Test name
Test status
Simulation time 245031599 ps
CPU time 1.04 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 218104 kb
Host smart-e3098d90-bb63-4628-b04e-9ace82345382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094325027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1094325027
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4138380744
Short name T335
Test name
Test status
Simulation time 88858250 ps
CPU time 0.76 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200512 kb
Host smart-251cdd63-0b1d-452e-a182-7cce49f2e9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138380744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4138380744
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.172159399
Short name T494
Test name
Test status
Simulation time 878364525 ps
CPU time 4.51 seconds
Started Apr 16 12:39:46 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 200984 kb
Host smart-2be9b142-bcd5-41ae-8744-b6251b66ceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172159399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.172159399
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.968228378
Short name T206
Test name
Test status
Simulation time 187366247 ps
CPU time 1.21 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:49 PM PDT 24
Peak memory 200732 kb
Host smart-614fa558-fa4d-467b-ba36-b334df39e94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968228378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.968228378
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3138412047
Short name T136
Test name
Test status
Simulation time 236577608 ps
CPU time 1.49 seconds
Started Apr 16 12:39:57 PM PDT 24
Finished Apr 16 12:40:00 PM PDT 24
Peak memory 200940 kb
Host smart-d73231ff-d668-4f48-818a-284ccd6fa088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138412047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3138412047
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.481615172
Short name T491
Test name
Test status
Simulation time 3624471263 ps
CPU time 13.9 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:40:00 PM PDT 24
Peak memory 200980 kb
Host smart-4aa572a5-1c82-41cd-ab22-c16904759f79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481615172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.481615172
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3459707200
Short name T535
Test name
Test status
Simulation time 131705885 ps
CPU time 1.63 seconds
Started Apr 16 12:39:43 PM PDT 24
Finished Apr 16 12:39:46 PM PDT 24
Peak memory 200776 kb
Host smart-093065d4-05b9-4eac-9351-bb37a24a0539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459707200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3459707200
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4183371139
Short name T320
Test name
Test status
Simulation time 282789402 ps
CPU time 1.5 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:48 PM PDT 24
Peak memory 200892 kb
Host smart-1f306c6a-cde9-44fd-b193-0b497fe1624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183371139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4183371139
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3550758183
Short name T276
Test name
Test status
Simulation time 63484832 ps
CPU time 0.82 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:47 PM PDT 24
Peak memory 200568 kb
Host smart-7a9decec-257b-4551-80f1-e9481cef4643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550758183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3550758183
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3129549037
Short name T43
Test name
Test status
Simulation time 1231091445 ps
CPU time 5.65 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:40:02 PM PDT 24
Peak memory 222604 kb
Host smart-4b4a8e8c-cf4e-4123-a968-e924632c7486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129549037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3129549037
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2629138397
Short name T328
Test name
Test status
Simulation time 244371368 ps
CPU time 1.11 seconds
Started Apr 16 12:39:38 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 218108 kb
Host smart-f763c0a3-4a48-4b70-afc0-aa7f0e98a3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629138397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2629138397
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2921991150
Short name T339
Test name
Test status
Simulation time 209314264 ps
CPU time 0.91 seconds
Started Apr 16 12:39:39 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 200528 kb
Host smart-036caf42-6468-4361-8423-ee2654810d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921991150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2921991150
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2676947878
Short name T464
Test name
Test status
Simulation time 163280960 ps
CPU time 1.14 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 200708 kb
Host smart-a8df663f-4355-4deb-b277-c9a61f71d16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676947878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2676947878
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3175260563
Short name T386
Test name
Test status
Simulation time 253358326 ps
CPU time 1.49 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 200952 kb
Host smart-3d89201a-a3e1-4d91-b8cb-83a3a2efa9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175260563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3175260563
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1021030788
Short name T98
Test name
Test status
Simulation time 12452055643 ps
CPU time 43.24 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:40:32 PM PDT 24
Peak memory 209764 kb
Host smart-ed0c862a-f987-400a-a76e-997dc256318b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021030788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1021030788
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2877665813
Short name T79
Test name
Test status
Simulation time 116647203 ps
CPU time 1.56 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 200820 kb
Host smart-59002814-e30c-4f46-970f-cd72c61db167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877665813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2877665813
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1357655389
Short name T274
Test name
Test status
Simulation time 159037249 ps
CPU time 1.23 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 200952 kb
Host smart-ac332fbd-c3d7-4566-bfb4-9733b1de8c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357655389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1357655389
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3760024619
Short name T432
Test name
Test status
Simulation time 58621807 ps
CPU time 0.76 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:55 PM PDT 24
Peak memory 200624 kb
Host smart-c6ccc3e2-54a3-4c2b-b853-9608040bb849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760024619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3760024619
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.670096273
Short name T41
Test name
Test status
Simulation time 1226709731 ps
CPU time 5.7 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 222432 kb
Host smart-c365d7b1-62b4-40c4-90a5-64a00f07c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670096273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.670096273
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3440493007
Short name T247
Test name
Test status
Simulation time 244532711 ps
CPU time 1.1 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 217920 kb
Host smart-61cc0f47-99f1-41f2-a334-56c77f9150a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440493007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3440493007
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.780834105
Short name T476
Test name
Test status
Simulation time 222733670 ps
CPU time 0.93 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 200604 kb
Host smart-d0cf9fd0-849f-4924-af80-d30fe3af4d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780834105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.780834105
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3239585645
Short name T506
Test name
Test status
Simulation time 928794453 ps
CPU time 4.78 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:12 PM PDT 24
Peak memory 200900 kb
Host smart-83e3db70-2963-44be-a3ee-55867d3197a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239585645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3239585645
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2934323296
Short name T62
Test name
Test status
Simulation time 8314232166 ps
CPU time 12.9 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:20 PM PDT 24
Peak memory 217672 kb
Host smart-2fb07ecc-f342-4265-a120-a3b66c219598
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934323296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2934323296
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3915143667
Short name T530
Test name
Test status
Simulation time 179997512 ps
CPU time 1.17 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 200816 kb
Host smart-4547488e-1af6-4de8-a1e7-0b84bcf4ac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915143667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3915143667
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2718463263
Short name T388
Test name
Test status
Simulation time 202826774 ps
CPU time 1.32 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 200968 kb
Host smart-aca7fee8-27b6-44c6-aad1-3e76e1c00805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718463263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2718463263
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1284393378
Short name T479
Test name
Test status
Simulation time 1836427863 ps
CPU time 8.02 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 200980 kb
Host smart-7d62e1a9-f3cc-43bd-9b60-dbf684a74123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284393378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1284393378
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.629604036
Short name T525
Test name
Test status
Simulation time 254197305 ps
CPU time 1.73 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:56 PM PDT 24
Peak memory 200804 kb
Host smart-d5765531-dd73-415e-923a-2a71bc232d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629604036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.629604036
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2713547743
Short name T298
Test name
Test status
Simulation time 99118538 ps
CPU time 0.95 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200780 kb
Host smart-70d375f7-88c0-4087-a197-f1f9f96acbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713547743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2713547743
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1790363469
Short name T246
Test name
Test status
Simulation time 65321680 ps
CPU time 0.76 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 200568 kb
Host smart-54e460bb-a4b2-4ba4-8f3c-f7261768031b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790363469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1790363469
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4261519635
Short name T449
Test name
Test status
Simulation time 2350628257 ps
CPU time 7.95 seconds
Started Apr 16 12:39:46 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 222736 kb
Host smart-cdfdc0d3-4a1d-487f-8465-27b3efb61717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261519635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4261519635
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1759014374
Short name T150
Test name
Test status
Simulation time 244202188 ps
CPU time 1.08 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:39:54 PM PDT 24
Peak memory 217992 kb
Host smart-43f127d4-7daa-484c-9255-198820b9330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759014374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1759014374
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2148013721
Short name T396
Test name
Test status
Simulation time 138244173 ps
CPU time 0.87 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200544 kb
Host smart-29a07cc6-3e4d-4d30-9ce2-976b558ff333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148013721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2148013721
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1991004169
Short name T359
Test name
Test status
Simulation time 1788247732 ps
CPU time 6.39 seconds
Started Apr 16 12:39:57 PM PDT 24
Finished Apr 16 12:40:05 PM PDT 24
Peak memory 200892 kb
Host smart-8c2cc5fb-1065-4cff-a079-b107b48f3fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991004169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1991004169
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1209920418
Short name T461
Test name
Test status
Simulation time 183026216 ps
CPU time 1.15 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 200732 kb
Host smart-f4d4f803-5e63-448f-8590-b1d1801dcf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209920418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1209920418
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1801625174
Short name T34
Test name
Test status
Simulation time 115537163 ps
CPU time 1.18 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 200944 kb
Host smart-665a7a93-76d6-4189-9141-e73bc9d18779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801625174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1801625174
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3294026967
Short name T361
Test name
Test status
Simulation time 2004788501 ps
CPU time 7.18 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:40:00 PM PDT 24
Peak memory 209160 kb
Host smart-a9f3164e-5d03-4b3f-ba81-a983dff8da9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294026967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3294026967
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2878380285
Short name T375
Test name
Test status
Simulation time 106954431 ps
CPU time 1.42 seconds
Started Apr 16 12:39:39 PM PDT 24
Finished Apr 16 12:39:42 PM PDT 24
Peak memory 200772 kb
Host smart-54123d3e-7f76-4b3c-9128-4e595a28e666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878380285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2878380285
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3480142141
Short name T389
Test name
Test status
Simulation time 243368910 ps
CPU time 1.46 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 200884 kb
Host smart-c50457e6-517c-49ee-9957-dcdcc4154797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480142141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3480142141
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1742333969
Short name T473
Test name
Test status
Simulation time 84201514 ps
CPU time 0.85 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 200600 kb
Host smart-4b0b375e-2262-49df-8aee-3a0efc504ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742333969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1742333969
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.103939239
Short name T29
Test name
Test status
Simulation time 1886787423 ps
CPU time 7.63 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:40:00 PM PDT 24
Peak memory 222532 kb
Host smart-d8766547-ed72-4b87-aa63-a400f1b56fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103939239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.103939239
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.505290745
Short name T231
Test name
Test status
Simulation time 244119246 ps
CPU time 1.2 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 218012 kb
Host smart-82339e2f-1981-4b17-8cd5-83a4cf148d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505290745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.505290745
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1818188055
Short name T474
Test name
Test status
Simulation time 191442553 ps
CPU time 0.84 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:39:53 PM PDT 24
Peak memory 200528 kb
Host smart-41ff5aec-845e-4803-b339-711087503616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818188055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1818188055
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3600728767
Short name T455
Test name
Test status
Simulation time 952922375 ps
CPU time 4.7 seconds
Started Apr 16 12:39:56 PM PDT 24
Finished Apr 16 12:40:02 PM PDT 24
Peak memory 200804 kb
Host smart-8237fb74-396b-422b-8b5b-5d62cf12f74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600728767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3600728767
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2206503565
Short name T313
Test name
Test status
Simulation time 139271926 ps
CPU time 1.08 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 200720 kb
Host smart-f0080762-add6-4601-a22e-fa22e8ee741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206503565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2206503565
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3618956759
Short name T400
Test name
Test status
Simulation time 117119111 ps
CPU time 1.15 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 200892 kb
Host smart-a0d46b94-cdfa-4155-bc04-ef05ad0870cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618956759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3618956759
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.750786655
Short name T452
Test name
Test status
Simulation time 4894954473 ps
CPU time 22.66 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:40:14 PM PDT 24
Peak memory 201052 kb
Host smart-ebe8f78a-55db-41e1-9447-630cfe9d5509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750786655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.750786655
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2133206828
Short name T336
Test name
Test status
Simulation time 114528878 ps
CPU time 1.52 seconds
Started Apr 16 12:39:49 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 200708 kb
Host smart-83c10ba8-f64c-49f8-8669-d6fd4b02dbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133206828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2133206828
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2653782363
Short name T205
Test name
Test status
Simulation time 89120257 ps
CPU time 0.91 seconds
Started Apr 16 12:39:38 PM PDT 24
Finished Apr 16 12:39:41 PM PDT 24
Peak memory 200728 kb
Host smart-e09f70b7-2382-4010-af0e-0ebfab977619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653782363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2653782363
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2309006562
Short name T236
Test name
Test status
Simulation time 67824624 ps
CPU time 0.78 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:39:54 PM PDT 24
Peak memory 200528 kb
Host smart-a2ccfeb1-a5e1-4e16-b510-d22e5597c3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309006562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2309006562
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.26682775
Short name T459
Test name
Test status
Simulation time 1891210406 ps
CPU time 6.51 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 222464 kb
Host smart-311c2edc-89f1-47fa-8656-eee64521a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26682775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.26682775
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1935730649
Short name T342
Test name
Test status
Simulation time 244073897 ps
CPU time 1.17 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 217992 kb
Host smart-5f1034a6-73ab-40e3-a323-09e4105a39ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935730649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1935730649
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1244985193
Short name T16
Test name
Test status
Simulation time 216996696 ps
CPU time 0.91 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:47 PM PDT 24
Peak memory 200592 kb
Host smart-2a79ce6a-2ec4-422f-8dba-8818028babc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244985193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1244985193
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2065049459
Short name T93
Test name
Test status
Simulation time 1633380480 ps
CPU time 5.75 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 200960 kb
Host smart-f9ff51b1-d0fb-4130-9039-cd03f041cde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065049459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2065049459
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2645152599
Short name T124
Test name
Test status
Simulation time 186189606 ps
CPU time 1.24 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200736 kb
Host smart-90a6aed3-348c-4ff7-92b4-789dbf5d7b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645152599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2645152599
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3893246668
Short name T157
Test name
Test status
Simulation time 121240496 ps
CPU time 1.19 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 200864 kb
Host smart-7782fe8b-4f3a-49a1-9448-a804136788a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893246668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3893246668
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2245525046
Short name T212
Test name
Test status
Simulation time 13223474386 ps
CPU time 42.34 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:40:28 PM PDT 24
Peak memory 201052 kb
Host smart-aeae86ad-3f2a-4fcc-a7ca-0377fee87f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245525046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2245525046
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1485296759
Short name T296
Test name
Test status
Simulation time 117115026 ps
CPU time 1.39 seconds
Started Apr 16 12:39:49 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 200728 kb
Host smart-9a0563ec-cfcd-4b7f-b37c-afe4f3b0be1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485296759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1485296759
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2843615351
Short name T161
Test name
Test status
Simulation time 97577856 ps
CPU time 0.95 seconds
Started Apr 16 12:39:44 PM PDT 24
Finished Apr 16 12:39:46 PM PDT 24
Peak memory 200768 kb
Host smart-86718e21-fd99-4e2c-ade2-54245dde1059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843615351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2843615351
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3427772065
Short name T309
Test name
Test status
Simulation time 77152589 ps
CPU time 0.78 seconds
Started Apr 16 12:39:55 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 200584 kb
Host smart-5b84cf63-981c-4f53-8053-e64da1994f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427772065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3427772065
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1600923341
Short name T334
Test name
Test status
Simulation time 2346716912 ps
CPU time 8.65 seconds
Started Apr 16 12:39:40 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 218332 kb
Host smart-f6a7bcd0-733e-4126-926c-0191ccd29267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600923341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1600923341
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3448254774
Short name T75
Test name
Test status
Simulation time 245582682 ps
CPU time 1.04 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:39:53 PM PDT 24
Peak memory 218140 kb
Host smart-6ed933fd-a224-4c1d-9c32-a8dd0f751238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448254774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3448254774
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1026266430
Short name T17
Test name
Test status
Simulation time 174324932 ps
CPU time 0.88 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 200288 kb
Host smart-6952b725-f36d-4cbd-a5f3-047156494ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026266430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1026266430
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.4281834006
Short name T429
Test name
Test status
Simulation time 814663113 ps
CPU time 4.35 seconds
Started Apr 16 12:39:49 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 200944 kb
Host smart-ba823339-3090-419b-97a7-5135d711dbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281834006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.4281834006
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3335559609
Short name T463
Test name
Test status
Simulation time 109566112 ps
CPU time 1.04 seconds
Started Apr 16 12:39:55 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 200684 kb
Host smart-61ae8413-4f11-4f6b-8630-d44e2b2adbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335559609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3335559609
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3435011097
Short name T258
Test name
Test status
Simulation time 264440667 ps
CPU time 1.53 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:39:53 PM PDT 24
Peak memory 200840 kb
Host smart-e6e8123a-1c56-4b8d-99c6-a7a8a0eda360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435011097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3435011097
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.117600873
Short name T214
Test name
Test status
Simulation time 5493373291 ps
CPU time 24.84 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:40:22 PM PDT 24
Peak memory 200980 kb
Host smart-9a831b3d-88d5-48f4-92e8-9f1c532b9b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117600873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.117600873
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3915377303
Short name T289
Test name
Test status
Simulation time 439786224 ps
CPU time 2.46 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200708 kb
Host smart-67a6dfdb-be10-40aa-bdd5-0519af8f29bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915377303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3915377303
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1322403246
Short name T275
Test name
Test status
Simulation time 234620508 ps
CPU time 1.41 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:39:54 PM PDT 24
Peak memory 200936 kb
Host smart-5b3c346a-9e06-4d3e-a2a6-6e4549906f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322403246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1322403246
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4272578143
Short name T484
Test name
Test status
Simulation time 83622502 ps
CPU time 0.83 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:48 PM PDT 24
Peak memory 200600 kb
Host smart-aab81382-88c3-4b22-a98c-d3e22700e172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272578143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4272578143
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3733682093
Short name T492
Test name
Test status
Simulation time 1231921387 ps
CPU time 5.59 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:40:01 PM PDT 24
Peak memory 217736 kb
Host smart-b518bdb1-915b-453c-9ce7-34b4809592ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733682093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3733682093
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3442285309
Short name T181
Test name
Test status
Simulation time 244565255 ps
CPU time 1.13 seconds
Started Apr 16 12:39:44 PM PDT 24
Finished Apr 16 12:39:47 PM PDT 24
Peak memory 218248 kb
Host smart-bd4489af-2e0d-4534-a95f-9f32b692b1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442285309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3442285309
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3885530798
Short name T354
Test name
Test status
Simulation time 179582401 ps
CPU time 0.85 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200616 kb
Host smart-1a5f85d0-88b2-427b-9114-4ee0f24ac642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885530798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3885530798
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.842433539
Short name T264
Test name
Test status
Simulation time 1837012988 ps
CPU time 6.82 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:39:59 PM PDT 24
Peak memory 200952 kb
Host smart-6e826edc-7935-4cab-82d2-dea4202edb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842433539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.842433539
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4247636934
Short name T419
Test name
Test status
Simulation time 99239272 ps
CPU time 0.96 seconds
Started Apr 16 12:39:42 PM PDT 24
Finished Apr 16 12:39:44 PM PDT 24
Peak memory 200768 kb
Host smart-3b072aa3-f218-4b46-a8d9-c9afae31b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247636934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.4247636934
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1394810376
Short name T147
Test name
Test status
Simulation time 201122385 ps
CPU time 1.33 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 200952 kb
Host smart-e9e59d69-45a2-41cb-be3b-2cfb5e0b5ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394810376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1394810376
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2971491705
Short name T471
Test name
Test status
Simulation time 4636727905 ps
CPU time 19.62 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:40:14 PM PDT 24
Peak memory 200996 kb
Host smart-509d5326-8b5c-4a3a-8a52-dfaa561df06e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971491705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2971491705
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.231994258
Short name T442
Test name
Test status
Simulation time 339399937 ps
CPU time 2 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 200784 kb
Host smart-bfd8f6ec-356b-4a02-be1e-f54bbb1a695a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231994258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.231994258
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1384355345
Short name T329
Test name
Test status
Simulation time 69357534 ps
CPU time 0.76 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 200712 kb
Host smart-333a3538-b9f7-48ba-8c02-828b427ac97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384355345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1384355345
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2108232702
Short name T160
Test name
Test status
Simulation time 60159092 ps
CPU time 0.77 seconds
Started Apr 16 12:39:56 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 200556 kb
Host smart-3d1c084b-8011-483e-9340-ee1e43456718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108232702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2108232702
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3904298076
Short name T502
Test name
Test status
Simulation time 1220711625 ps
CPU time 5.67 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 222644 kb
Host smart-7e65c5fe-4f33-4cc6-a40c-7406d247ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904298076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3904298076
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1059032989
Short name T485
Test name
Test status
Simulation time 245364886 ps
CPU time 1.13 seconds
Started Apr 16 12:40:18 PM PDT 24
Finished Apr 16 12:40:20 PM PDT 24
Peak memory 217904 kb
Host smart-e05c5f61-7c4b-4c43-8836-d37acbad2435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059032989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1059032989
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1852029669
Short name T288
Test name
Test status
Simulation time 178108853 ps
CPU time 0.84 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200548 kb
Host smart-1ec4448a-8d3f-412f-86f2-7ee48fc14348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852029669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1852029669
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3863609223
Short name T306
Test name
Test status
Simulation time 1461840416 ps
CPU time 6.27 seconds
Started Apr 16 12:40:00 PM PDT 24
Finished Apr 16 12:40:12 PM PDT 24
Peak memory 200948 kb
Host smart-41a654bc-f0db-484b-880d-0722329d08d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863609223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3863609223
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3476198376
Short name T125
Test name
Test status
Simulation time 142409193 ps
CPU time 1.08 seconds
Started Apr 16 12:39:55 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 200684 kb
Host smart-1c3a4535-0a18-4abd-8b31-fe882a998655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476198376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3476198376
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2467923987
Short name T33
Test name
Test status
Simulation time 220703413 ps
CPU time 1.41 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 200928 kb
Host smart-99abaf0a-cd95-44cd-a94a-5d51c53fe257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467923987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2467923987
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2132427423
Short name T235
Test name
Test status
Simulation time 2695672899 ps
CPU time 10.13 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:40:00 PM PDT 24
Peak memory 201000 kb
Host smart-ce94aee0-94c0-408e-a611-9ee26acdaea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132427423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2132427423
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1627378255
Short name T162
Test name
Test status
Simulation time 400868629 ps
CPU time 2.25 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 200796 kb
Host smart-6ec943a4-2e9c-4f6f-b385-123966cc68b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627378255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1627378255
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1565810828
Short name T353
Test name
Test status
Simulation time 69567033 ps
CPU time 0.75 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 200544 kb
Host smart-0b595e12-9fc7-40d0-a987-1eaaee398eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565810828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1565810828
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1248495444
Short name T312
Test name
Test status
Simulation time 62076502 ps
CPU time 0.81 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:50 PM PDT 24
Peak memory 200628 kb
Host smart-d0eaecc6-b287-43ef-84c7-03b5e0b31d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248495444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1248495444
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.432231678
Short name T326
Test name
Test status
Simulation time 1900203965 ps
CPU time 7.04 seconds
Started Apr 16 12:39:55 PM PDT 24
Finished Apr 16 12:40:04 PM PDT 24
Peak memory 222088 kb
Host smart-df3f8f33-e2e6-4450-8204-1671900450fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432231678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.432231678
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3481662995
Short name T213
Test name
Test status
Simulation time 243482590 ps
CPU time 1.11 seconds
Started Apr 16 12:40:04 PM PDT 24
Finished Apr 16 12:40:06 PM PDT 24
Peak memory 218020 kb
Host smart-a750dcd3-38c9-462d-8e7f-195109caf44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481662995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3481662995
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.635759829
Short name T511
Test name
Test status
Simulation time 161454462 ps
CPU time 0.83 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200536 kb
Host smart-10bd07a7-7aba-4c30-9bd2-8ee0e6e364f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635759829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.635759829
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2997855143
Short name T207
Test name
Test status
Simulation time 1377290324 ps
CPU time 5.38 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 200988 kb
Host smart-ad95cb9d-2214-4f2d-aead-a868bb263cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997855143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2997855143
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1251753876
Short name T269
Test name
Test status
Simulation time 165207271 ps
CPU time 1.15 seconds
Started Apr 16 12:40:01 PM PDT 24
Finished Apr 16 12:40:03 PM PDT 24
Peak memory 200832 kb
Host smart-9badf2eb-e3d4-48e1-a8ee-130f336c6359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251753876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1251753876
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.184178199
Short name T317
Test name
Test status
Simulation time 258570424 ps
CPU time 1.57 seconds
Started Apr 16 12:39:49 PM PDT 24
Finished Apr 16 12:39:52 PM PDT 24
Peak memory 200952 kb
Host smart-76ff69c9-5ef8-431b-aa9d-3dc64ef8ff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184178199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.184178199
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.898930900
Short name T519
Test name
Test status
Simulation time 2853254417 ps
CPU time 13.63 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:40:10 PM PDT 24
Peak memory 200964 kb
Host smart-951d7cff-f591-43b9-baf5-908030b6c4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898930900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.898930900
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2458871743
Short name T278
Test name
Test status
Simulation time 143323525 ps
CPU time 1.87 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 200792 kb
Host smart-e48fc659-016b-4bb3-a904-fbbbdd0a674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458871743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2458871743
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1146207271
Short name T256
Test name
Test status
Simulation time 103327680 ps
CPU time 0.94 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200860 kb
Host smart-9fc97dc6-9830-4673-80e8-842edfdf8704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146207271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1146207271
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1707229958
Short name T177
Test name
Test status
Simulation time 78737339 ps
CPU time 0.76 seconds
Started Apr 16 12:39:57 PM PDT 24
Finished Apr 16 12:39:59 PM PDT 24
Peak memory 200612 kb
Host smart-0666670d-6c75-4c90-8b73-35b102c490be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707229958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1707229958
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2585779544
Short name T381
Test name
Test status
Simulation time 1224160362 ps
CPU time 5.71 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:40:02 PM PDT 24
Peak memory 222124 kb
Host smart-51a4a5e5-c911-4996-8b29-375b89820153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585779544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2585779544
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3468687092
Short name T453
Test name
Test status
Simulation time 243860904 ps
CPU time 1.08 seconds
Started Apr 16 12:39:57 PM PDT 24
Finished Apr 16 12:40:00 PM PDT 24
Peak memory 218032 kb
Host smart-7f60dbcd-1766-4298-9247-88a293c9d527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468687092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3468687092
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.709658654
Short name T343
Test name
Test status
Simulation time 160570398 ps
CPU time 0.84 seconds
Started Apr 16 12:39:46 PM PDT 24
Finished Apr 16 12:39:48 PM PDT 24
Peak memory 200568 kb
Host smart-e7dfc41e-fd87-4064-95c3-6754a1988052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709658654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.709658654
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.144247152
Short name T95
Test name
Test status
Simulation time 1555535940 ps
CPU time 5.82 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 200916 kb
Host smart-70db6224-0647-440d-b27c-f8c2f1fbdca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144247152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.144247152
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4133559710
Short name T144
Test name
Test status
Simulation time 141580683 ps
CPU time 1.05 seconds
Started Apr 16 12:39:48 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 200764 kb
Host smart-a35435a5-d781-42b2-9752-84a88a96fde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133559710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4133559710
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1140905526
Short name T280
Test name
Test status
Simulation time 114739635 ps
CPU time 1.2 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:39:54 PM PDT 24
Peak memory 201000 kb
Host smart-7509a4b3-ffec-4334-838a-3ce55d02447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140905526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1140905526
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1602097591
Short name T156
Test name
Test status
Simulation time 917789849 ps
CPU time 4.71 seconds
Started Apr 16 12:39:55 PM PDT 24
Finished Apr 16 12:40:02 PM PDT 24
Peak memory 201052 kb
Host smart-fd422820-e686-44a0-a20c-91e3dc34ade9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602097591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1602097591
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.371369557
Short name T399
Test name
Test status
Simulation time 322206415 ps
CPU time 2.14 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 200512 kb
Host smart-213f607a-502f-4b49-a3b1-6ec49e8208a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371369557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.371369557
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4070516208
Short name T504
Test name
Test status
Simulation time 94027696 ps
CPU time 0.93 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 200772 kb
Host smart-24469ca0-2a84-4513-8f11-1c98231d2f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070516208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4070516208
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3452267524
Short name T188
Test name
Test status
Simulation time 70159483 ps
CPU time 0.74 seconds
Started Apr 16 12:39:56 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 200572 kb
Host smart-11392ac2-53f5-420b-8913-e8ef8096c620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452267524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3452267524
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.575607948
Short name T397
Test name
Test status
Simulation time 1222573108 ps
CPU time 5.71 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 218632 kb
Host smart-50edf657-31c8-42bd-a9ee-469a105bec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575607948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.575607948
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3169214763
Short name T501
Test name
Test status
Simulation time 243904516 ps
CPU time 1.12 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 218132 kb
Host smart-74035e9a-dbf4-4e00-a3b1-6df278c9187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169214763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3169214763
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2704688739
Short name T255
Test name
Test status
Simulation time 90109667 ps
CPU time 0.77 seconds
Started Apr 16 12:39:54 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 200544 kb
Host smart-a164568c-9936-47bf-8378-121aa1f258ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704688739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2704688739
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3697475029
Short name T176
Test name
Test status
Simulation time 1480382163 ps
CPU time 6.28 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 201044 kb
Host smart-daa7bd78-b116-4058-86ca-baa2da54674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697475029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3697475029
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2664151598
Short name T141
Test name
Test status
Simulation time 146531850 ps
CPU time 1.08 seconds
Started Apr 16 12:39:45 PM PDT 24
Finished Apr 16 12:39:48 PM PDT 24
Peak memory 201044 kb
Host smart-78f254ab-8581-4253-91b8-67fbcc456bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664151598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2664151598
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1314696338
Short name T433
Test name
Test status
Simulation time 198828321 ps
CPU time 1.37 seconds
Started Apr 16 12:39:51 PM PDT 24
Finished Apr 16 12:39:54 PM PDT 24
Peak memory 200612 kb
Host smart-1e158237-cb50-4e4c-94cf-c03fbe90041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314696338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1314696338
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.242504213
Short name T500
Test name
Test status
Simulation time 7489341391 ps
CPU time 28.14 seconds
Started Apr 16 12:39:55 PM PDT 24
Finished Apr 16 12:40:25 PM PDT 24
Peak memory 201096 kb
Host smart-95f2e840-e767-4ae4-87a5-54d458585159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242504213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.242504213
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4232037379
Short name T446
Test name
Test status
Simulation time 386580483 ps
CPU time 2.15 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:51 PM PDT 24
Peak memory 200756 kb
Host smart-9c4118b0-95c5-456a-8e76-6cae09a9ee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232037379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4232037379
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2042819262
Short name T130
Test name
Test status
Simulation time 130364165 ps
CPU time 1.02 seconds
Started Apr 16 12:40:11 PM PDT 24
Finished Apr 16 12:40:13 PM PDT 24
Peak memory 200756 kb
Host smart-d239e6f3-eb97-4bfa-badc-3017c3c62133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042819262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2042819262
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.935951317
Short name T133
Test name
Test status
Simulation time 65160496 ps
CPU time 0.76 seconds
Started Apr 16 12:39:56 PM PDT 24
Finished Apr 16 12:39:58 PM PDT 24
Peak memory 200532 kb
Host smart-befdce9d-c5c1-4232-811b-b67c867dfe53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935951317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.935951317
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1976988106
Short name T451
Test name
Test status
Simulation time 245120269 ps
CPU time 1.06 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 218188 kb
Host smart-9a1f98f3-5599-415d-a823-074f64f9ac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976988106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1976988106
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2038065570
Short name T164
Test name
Test status
Simulation time 139080539 ps
CPU time 0.8 seconds
Started Apr 16 12:39:50 PM PDT 24
Finished Apr 16 12:39:53 PM PDT 24
Peak memory 200624 kb
Host smart-25bc441c-6be1-41b1-8549-9083a9561e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038065570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2038065570
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1098840257
Short name T412
Test name
Test status
Simulation time 1012708733 ps
CPU time 5.41 seconds
Started Apr 16 12:39:47 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 200948 kb
Host smart-80c8bea7-0274-4e11-ae6e-f4c069b886f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098840257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1098840257
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2598070624
Short name T152
Test name
Test status
Simulation time 173583076 ps
CPU time 1.29 seconds
Started Apr 16 12:39:57 PM PDT 24
Finished Apr 16 12:39:59 PM PDT 24
Peak memory 200836 kb
Host smart-673baea1-539c-4b7a-bebd-2a78f5cfd262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598070624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2598070624
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2855997181
Short name T238
Test name
Test status
Simulation time 257701759 ps
CPU time 1.5 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:56 PM PDT 24
Peak memory 200816 kb
Host smart-5fa0a5a2-ed8d-4585-9e14-b51f403b7824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855997181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2855997181
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2787306402
Short name T528
Test name
Test status
Simulation time 1815964309 ps
CPU time 8.19 seconds
Started Apr 16 12:39:57 PM PDT 24
Finished Apr 16 12:40:07 PM PDT 24
Peak memory 200924 kb
Host smart-fd17e71e-1faf-44d1-ac26-4087e848e6fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787306402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2787306402
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.77657464
Short name T82
Test name
Test status
Simulation time 298699120 ps
CPU time 1.87 seconds
Started Apr 16 12:39:53 PM PDT 24
Finished Apr 16 12:39:57 PM PDT 24
Peak memory 208996 kb
Host smart-8f8ac603-38bd-4a4b-ab74-85d4225ec187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77657464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.77657464
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3361787129
Short name T208
Test name
Test status
Simulation time 104898860 ps
CPU time 0.95 seconds
Started Apr 16 12:39:52 PM PDT 24
Finished Apr 16 12:39:55 PM PDT 24
Peak memory 200720 kb
Host smart-69a054d3-a7df-49b2-8b5f-8a42c3fda337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361787129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3361787129
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1703442894
Short name T202
Test name
Test status
Simulation time 64366986 ps
CPU time 0.81 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 200484 kb
Host smart-519ea0ff-ba8b-476e-abdf-ab4a8ab680bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703442894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1703442894
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.664747052
Short name T401
Test name
Test status
Simulation time 1224383529 ps
CPU time 5.56 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:59 PM PDT 24
Peak memory 222608 kb
Host smart-537de7db-a6c4-4bb7-8248-88a080a98cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664747052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.664747052
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3131655744
Short name T466
Test name
Test status
Simulation time 243995772 ps
CPU time 1.07 seconds
Started Apr 16 12:39:00 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 218220 kb
Host smart-cce1de80-eede-40d8-85e0-87d09e025260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131655744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3131655744
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1568385594
Short name T279
Test name
Test status
Simulation time 210991790 ps
CPU time 0.92 seconds
Started Apr 16 12:39:05 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 200492 kb
Host smart-2418e40a-b55f-479e-a1bb-6e66a0abeb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568385594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1568385594
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1461259018
Short name T100
Test name
Test status
Simulation time 1089799050 ps
CPU time 4.84 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:59 PM PDT 24
Peak memory 200888 kb
Host smart-51a40537-031e-459d-8cf7-7afe9c8d548d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461259018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1461259018
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1065181786
Short name T316
Test name
Test status
Simulation time 167191765 ps
CPU time 1.27 seconds
Started Apr 16 12:39:04 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 200756 kb
Host smart-f544c8ba-04d2-42c5-93a3-089a54d27b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065181786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1065181786
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.4289811928
Short name T8
Test name
Test status
Simulation time 117494959 ps
CPU time 1.14 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:00 PM PDT 24
Peak memory 200752 kb
Host smart-e6747c11-ebf8-425d-92f5-87006e28e5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289811928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.4289811928
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2996149516
Short name T47
Test name
Test status
Simulation time 2161011744 ps
CPU time 7.78 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:06 PM PDT 24
Peak memory 201004 kb
Host smart-d4afa941-207d-47c4-a036-7611b679f66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996149516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2996149516
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3145840317
Short name T137
Test name
Test status
Simulation time 319249094 ps
CPU time 2.08 seconds
Started Apr 16 12:39:00 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 208880 kb
Host smart-033ac92e-2c08-4155-a39a-4ca96c2a76af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145840317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3145840317
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3055871503
Short name T13
Test name
Test status
Simulation time 171652000 ps
CPU time 1.26 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:56 PM PDT 24
Peak memory 200856 kb
Host smart-474c70d5-ec76-4833-8ea9-4cb81174456f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055871503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3055871503
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.4077772591
Short name T239
Test name
Test status
Simulation time 74457380 ps
CPU time 0.77 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 200484 kb
Host smart-088f8423-7890-44fe-8094-b34fb61867f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077772591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4077772591
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3839434582
Short name T405
Test name
Test status
Simulation time 1229912232 ps
CPU time 5.27 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 218488 kb
Host smart-45ccaa9a-d40e-4361-8ab0-727511b90e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839434582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3839434582
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1375501325
Short name T537
Test name
Test status
Simulation time 244079481 ps
CPU time 1.07 seconds
Started Apr 16 12:39:05 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 218108 kb
Host smart-0caa3c0d-7637-4d2b-b851-b918c62a0079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375501325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1375501325
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2306120889
Short name T348
Test name
Test status
Simulation time 101607897 ps
CPU time 0.73 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:53 PM PDT 24
Peak memory 200524 kb
Host smart-dc777a84-2142-4889-a957-c4dd1b69a04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306120889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2306120889
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3215214897
Short name T159
Test name
Test status
Simulation time 1839928802 ps
CPU time 6.26 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200840 kb
Host smart-5ac64ac0-9937-4ce3-96c7-a6ce28030e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215214897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3215214897
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1709357457
Short name T295
Test name
Test status
Simulation time 99159468 ps
CPU time 1.01 seconds
Started Apr 16 12:39:04 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 200788 kb
Host smart-98834e25-da5f-4fa3-9f69-4a32127fb1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709357457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1709357457
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1214028865
Short name T413
Test name
Test status
Simulation time 223116059 ps
CPU time 1.51 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:58 PM PDT 24
Peak memory 201020 kb
Host smart-fd9c0001-fc43-4100-a014-69412255cae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214028865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1214028865
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2527434545
Short name T259
Test name
Test status
Simulation time 3425349601 ps
CPU time 12.31 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 201048 kb
Host smart-90848690-b0ab-4343-b5fa-34427d5a579f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527434545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2527434545
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1520304938
Short name T536
Test name
Test status
Simulation time 475531602 ps
CPU time 2.54 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 208776 kb
Host smart-2dd9ea41-b688-4165-b76c-0da29c6e6467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520304938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1520304938
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2477661675
Short name T458
Test name
Test status
Simulation time 102697222 ps
CPU time 0.84 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:00 PM PDT 24
Peak memory 200532 kb
Host smart-bfbfeb26-b96b-44a8-b0b5-316d7268bfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477661675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2477661675
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1462694813
Short name T48
Test name
Test status
Simulation time 72622662 ps
CPU time 0.79 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:04 PM PDT 24
Peak memory 200576 kb
Host smart-c2cd6c21-cb04-4817-9b53-d0f306a8ccd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462694813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1462694813
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1044757922
Short name T26
Test name
Test status
Simulation time 2178844643 ps
CPU time 8.06 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:39:05 PM PDT 24
Peak memory 222632 kb
Host smart-b70546cb-baea-4eae-ac13-0bcf593bbeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044757922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1044757922
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.852961721
Short name T321
Test name
Test status
Simulation time 256070571 ps
CPU time 1.08 seconds
Started Apr 16 12:39:12 PM PDT 24
Finished Apr 16 12:39:15 PM PDT 24
Peak memory 217948 kb
Host smart-0c145f66-eef3-4d57-894f-e168985e34a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852961721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.852961721
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3531890062
Short name T198
Test name
Test status
Simulation time 105106727 ps
CPU time 0.77 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 200496 kb
Host smart-5c929080-d7f9-42aa-b615-ae7b085805bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531890062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3531890062
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.37563186
Short name T409
Test name
Test status
Simulation time 864254315 ps
CPU time 4.2 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:03 PM PDT 24
Peak memory 200940 kb
Host smart-7ba9dd3f-e379-4df2-bde8-ad5b17596823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37563186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.37563186
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.357066104
Short name T338
Test name
Test status
Simulation time 98243398 ps
CPU time 1 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 200776 kb
Host smart-2cc3de32-fba1-4610-aabb-2f5cc365a442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357066104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.357066104
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3247803696
Short name T261
Test name
Test status
Simulation time 254708490 ps
CPU time 1.5 seconds
Started Apr 16 12:38:50 PM PDT 24
Finished Apr 16 12:38:53 PM PDT 24
Peak memory 201004 kb
Host smart-dac493c0-6bbd-4a9d-bd5d-c11ff5aa02b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247803696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3247803696
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.400996261
Short name T292
Test name
Test status
Simulation time 9482854433 ps
CPU time 40.59 seconds
Started Apr 16 12:39:01 PM PDT 24
Finished Apr 16 12:39:46 PM PDT 24
Peak memory 210040 kb
Host smart-beb27566-b9ca-4c56-b999-3e2cfcd8ecd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400996261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.400996261
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3404811250
Short name T493
Test name
Test status
Simulation time 343623561 ps
CPU time 2.45 seconds
Started Apr 16 12:39:25 PM PDT 24
Finished Apr 16 12:39:28 PM PDT 24
Peak memory 200708 kb
Host smart-d60969a4-969c-4e23-b322-64ea5fae75f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404811250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3404811250
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1758125565
Short name T237
Test name
Test status
Simulation time 146898338 ps
CPU time 1.15 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:01 PM PDT 24
Peak memory 200696 kb
Host smart-3728cafb-5bd5-4869-b71a-79478bf4d18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758125565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1758125565
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3637542797
Short name T322
Test name
Test status
Simulation time 63484765 ps
CPU time 0.72 seconds
Started Apr 16 12:39:08 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 200572 kb
Host smart-7188ea7d-2eee-459a-af3e-edfdb9773dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637542797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3637542797
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.467945269
Short name T374
Test name
Test status
Simulation time 2148467872 ps
CPU time 9.17 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 218112 kb
Host smart-2e44b0e9-a991-4a76-a358-da635d3d8c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467945269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.467945269
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.825522818
Short name T297
Test name
Test status
Simulation time 244322694 ps
CPU time 1 seconds
Started Apr 16 12:39:04 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 218232 kb
Host smart-fa8dc600-3897-4ca3-b689-a9decda01058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825522818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.825522818
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3763854890
Short name T346
Test name
Test status
Simulation time 86910688 ps
CPU time 0.77 seconds
Started Apr 16 12:39:06 PM PDT 24
Finished Apr 16 12:39:10 PM PDT 24
Peak memory 200580 kb
Host smart-651a908f-81df-4c8a-bec0-693a9e207493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763854890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3763854890
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.813236933
Short name T495
Test name
Test status
Simulation time 634958468 ps
CPU time 3.45 seconds
Started Apr 16 12:39:30 PM PDT 24
Finished Apr 16 12:39:35 PM PDT 24
Peak memory 200896 kb
Host smart-223fe10b-f985-4636-b873-bb4a6c492503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813236933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.813236933
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3953367972
Short name T204
Test name
Test status
Simulation time 188689418 ps
CPU time 1.12 seconds
Started Apr 16 12:38:54 PM PDT 24
Finished Apr 16 12:38:57 PM PDT 24
Peak memory 200792 kb
Host smart-dd4a207a-aa16-4052-b41f-5a811a0d6727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953367972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3953367972
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.4283897861
Short name T277
Test name
Test status
Simulation time 230834167 ps
CPU time 1.56 seconds
Started Apr 16 12:38:52 PM PDT 24
Finished Apr 16 12:38:55 PM PDT 24
Peak memory 200888 kb
Host smart-f7c5d2e2-38fc-4452-878c-978ba280aaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283897861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4283897861
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1988218473
Short name T104
Test name
Test status
Simulation time 966707512 ps
CPU time 4.63 seconds
Started Apr 16 12:39:03 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 209176 kb
Host smart-8ad9c192-38fb-47a9-803d-83313fab5776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988218473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1988218473
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2600213271
Short name T509
Test name
Test status
Simulation time 509626081 ps
CPU time 2.88 seconds
Started Apr 16 12:39:05 PM PDT 24
Finished Apr 16 12:39:11 PM PDT 24
Peak memory 200812 kb
Host smart-2e2d1361-9300-4642-a59d-cc272c4f4619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600213271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2600213271
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.472833647
Short name T486
Test name
Test status
Simulation time 103735594 ps
CPU time 0.9 seconds
Started Apr 16 12:38:55 PM PDT 24
Finished Apr 16 12:38:59 PM PDT 24
Peak memory 200768 kb
Host smart-3a9f82ae-6c39-482d-93f8-d04c2bc251e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472833647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.472833647
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3891013835
Short name T140
Test name
Test status
Simulation time 88492822 ps
CPU time 0.87 seconds
Started Apr 16 12:39:00 PM PDT 24
Finished Apr 16 12:39:05 PM PDT 24
Peak memory 200584 kb
Host smart-e90a3d66-1200-4dfd-8721-35b349ce3892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891013835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3891013835
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2251443232
Short name T37
Test name
Test status
Simulation time 1228999436 ps
CPU time 5.65 seconds
Started Apr 16 12:38:59 PM PDT 24
Finished Apr 16 12:39:09 PM PDT 24
Peak memory 221780 kb
Host smart-7b7a8a85-563a-49a3-a8f5-9859ec054d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251443232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2251443232
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3339591714
Short name T45
Test name
Test status
Simulation time 244612879 ps
CPU time 1.04 seconds
Started Apr 16 12:38:57 PM PDT 24
Finished Apr 16 12:39:02 PM PDT 24
Peak memory 218084 kb
Host smart-f4a6cf46-72cd-4954-8ac9-9ad71e106c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339591714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3339591714
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3377295296
Short name T505
Test name
Test status
Simulation time 154200229 ps
CPU time 0.9 seconds
Started Apr 16 12:38:53 PM PDT 24
Finished Apr 16 12:38:55 PM PDT 24
Peak memory 200568 kb
Host smart-cf20f734-2f04-44a3-bbba-a3822f6a27b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377295296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3377295296
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3772990340
Short name T518
Test name
Test status
Simulation time 1318252878 ps
CPU time 5.83 seconds
Started Apr 16 12:38:58 PM PDT 24
Finished Apr 16 12:39:07 PM PDT 24
Peak memory 200996 kb
Host smart-d226530b-9df6-4d75-ac0f-469b31616227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772990340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3772990340
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3493053567
Short name T472
Test name
Test status
Simulation time 181821210 ps
CPU time 1.3 seconds
Started Apr 16 12:39:19 PM PDT 24
Finished Apr 16 12:39:22 PM PDT 24
Peak memory 200772 kb
Host smart-5be00d3a-7c16-4d15-bd98-86bc7b97c5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493053567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3493053567
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2044275724
Short name T457
Test name
Test status
Simulation time 198903309 ps
CPU time 1.43 seconds
Started Apr 16 12:39:24 PM PDT 24
Finished Apr 16 12:39:26 PM PDT 24
Peak memory 200836 kb
Host smart-2836d220-df76-4da9-bef0-14e5d1f31c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044275724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2044275724
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2717823743
Short name T145
Test name
Test status
Simulation time 2551002137 ps
CPU time 8.6 seconds
Started Apr 16 12:39:11 PM PDT 24
Finished Apr 16 12:39:21 PM PDT 24
Peak memory 209560 kb
Host smart-e26ebddd-8ae4-4b80-9855-f02c12bac3c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717823743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2717823743
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1028420815
Short name T220
Test name
Test status
Simulation time 364206083 ps
CPU time 2.06 seconds
Started Apr 16 12:39:02 PM PDT 24
Finished Apr 16 12:39:08 PM PDT 24
Peak memory 200640 kb
Host smart-3e853218-c05f-4433-b8cc-fce4997d33aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028420815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1028420815
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2045613030
Short name T253
Test name
Test status
Simulation time 133401382 ps
CPU time 1.15 seconds
Started Apr 16 12:38:56 PM PDT 24
Finished Apr 16 12:39:00 PM PDT 24
Peak memory 200684 kb
Host smart-03fe3dc4-0550-43af-bee2-1af369b2622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045613030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2045613030
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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