Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8672

1

T1

20

T3

15

T4

28

auto[1]

11586

1

T1

81

T2

4

T3

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6185	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6894	1			T1	27		T2	2		T3	1
reset_info_cp[2]	3085	1			T1	21		T2	1		T4	11
reset_info_cp[4]	4129	1			T1	10		T2	1		T4	10
reset_info_cp[8]	132	1			T1	2		T23	1		T63	3
reset_info_cp[16]	130	1			T3	1		T23	1		T63	1
reset_info_cp[32]	96	1			T1	1		T66	1		T72	1
reset_info_cp[64]	115	1			T3	1		T4	2		T23	1
reset_info_cp[128]	112	1			T4	1		T10	2		T11	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3283	1			T1	20		T4	8		T10	20
reset_info_cp[1]	auto[1]	2991	1			T1	6		T2	1		T4	13
reset_info_cp[2]	auto[0]	978	1			T4	6		T67	5		T68	2
reset_info_cp[2]	auto[1]	2107	1			T1	21		T2	1		T4	5
reset_info_cp[4]	auto[0]	1525	1			T4	8		T67	4		T68	3
reset_info_cp[4]	auto[1]	2604	1			T1	10		T2	1		T4	2
reset_info_cp[8]	auto[0]	54	1			T23	1		T63	3		T72	1
reset_info_cp[8]	auto[1]	78	1			T1	2		T68	1		T89	1
reset_info_cp[16]	auto[0]	56	1			T3	1		T23	1		T63	1
reset_info_cp[16]	auto[1]	74	1			T68	2		T72	1		T44	2
reset_info_cp[32]	auto[0]	43	1			T66	1		T72	1		T91	1
reset_info_cp[32]	auto[1]	53	1			T1	1		T90	1		T91	1
reset_info_cp[64]	auto[0]	45	1			T3	1		T23	1		T63	1
reset_info_cp[64]	auto[1]	70	1			T4	2		T25	1		T68	1
reset_info_cp[128]	auto[0]	41	1			T63	1		T87	1		T120	2
reset_info_cp[128]	auto[1]	71	1			T4	1		T10	2		T11	1