Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3842572271 Apr 18 01:35:15 PM PDT 24 Apr 18 01:35:23 PM PDT 24 1891763569 ps
T537 /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3620792146 Apr 18 01:35:16 PM PDT 24 Apr 18 01:35:19 PM PDT 24 172703337 ps
T538 /workspace/coverage/default/5.rstmgr_alert_test.2968915860 Apr 18 01:34:19 PM PDT 24 Apr 18 01:34:21 PM PDT 24 93737388 ps
T539 /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2695526017 Apr 18 01:34:22 PM PDT 24 Apr 18 01:34:24 PM PDT 24 113814726 ps
T540 /workspace/coverage/default/13.rstmgr_alert_test.626681106 Apr 18 01:34:26 PM PDT 24 Apr 18 01:34:30 PM PDT 24 60275548 ps
T48 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.987385861 Apr 18 01:33:49 PM PDT 24 Apr 18 01:33:52 PM PDT 24 477819861 ps
T52 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.991930381 Apr 18 01:33:55 PM PDT 24 Apr 18 01:33:58 PM PDT 24 511944420 ps
T49 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.362551281 Apr 18 01:33:43 PM PDT 24 Apr 18 01:33:45 PM PDT 24 144038718 ps
T50 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3717861393 Apr 18 01:33:57 PM PDT 24 Apr 18 01:33:58 PM PDT 24 59239661 ps
T51 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.672996487 Apr 18 01:34:04 PM PDT 24 Apr 18 01:34:07 PM PDT 24 502446477 ps
T53 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.842643080 Apr 18 01:33:34 PM PDT 24 Apr 18 01:33:38 PM PDT 24 423157298 ps
T86 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1041668258 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:45 PM PDT 24 889362754 ps
T112 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3609783096 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:46 PM PDT 24 268536799 ps
T103 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.940964036 Apr 18 01:33:58 PM PDT 24 Apr 18 01:33:59 PM PDT 24 72872261 ps
T78 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2166364739 Apr 18 01:33:38 PM PDT 24 Apr 18 01:33:40 PM PDT 24 114194708 ps
T79 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2340664135 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:45 PM PDT 24 933117824 ps
T104 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3921271737 Apr 18 01:33:48 PM PDT 24 Apr 18 01:33:49 PM PDT 24 61413112 ps
T80 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3319616133 Apr 18 01:34:15 PM PDT 24 Apr 18 01:34:19 PM PDT 24 915362865 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1262106446 Apr 18 01:33:32 PM PDT 24 Apr 18 01:33:33 PM PDT 24 105029140 ps
T81 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3581699449 Apr 18 01:33:40 PM PDT 24 Apr 18 01:33:43 PM PDT 24 163199104 ps
T105 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3675538835 Apr 18 01:33:43 PM PDT 24 Apr 18 01:33:45 PM PDT 24 73991816 ps
T106 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1502521173 Apr 18 01:34:15 PM PDT 24 Apr 18 01:34:17 PM PDT 24 135499350 ps
T82 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.360440633 Apr 18 01:33:39 PM PDT 24 Apr 18 01:33:41 PM PDT 24 428784783 ps
T542 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1261264936 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:50 PM PDT 24 1562172472 ps
T83 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1790809280 Apr 18 01:33:50 PM PDT 24 Apr 18 01:33:52 PM PDT 24 277356490 ps
T84 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2582440778 Apr 18 01:33:50 PM PDT 24 Apr 18 01:33:54 PM PDT 24 819295531 ps
T107 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2741274989 Apr 18 01:33:51 PM PDT 24 Apr 18 01:33:53 PM PDT 24 245443073 ps
T85 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1037612015 Apr 18 01:33:45 PM PDT 24 Apr 18 01:33:49 PM PDT 24 475914608 ps
T108 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1928422280 Apr 18 01:33:38 PM PDT 24 Apr 18 01:33:40 PM PDT 24 167358960 ps
T113 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3486337541 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:46 PM PDT 24 423870507 ps
T123 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1143281968 Apr 18 01:33:40 PM PDT 24 Apr 18 01:33:44 PM PDT 24 877789355 ps
T543 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1550567415 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:44 PM PDT 24 199571622 ps
T118 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2609958251 Apr 18 01:33:45 PM PDT 24 Apr 18 01:33:48 PM PDT 24 375163868 ps
T544 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1105698892 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:46 PM PDT 24 269409322 ps
T93 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2974351549 Apr 18 01:33:40 PM PDT 24 Apr 18 01:33:42 PM PDT 24 99109698 ps
T115 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4142224403 Apr 18 01:33:45 PM PDT 24 Apr 18 01:33:49 PM PDT 24 783278324 ps
T109 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1466357617 Apr 18 01:34:10 PM PDT 24 Apr 18 01:34:12 PM PDT 24 130404448 ps
T110 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.392382883 Apr 18 01:34:06 PM PDT 24 Apr 18 01:34:09 PM PDT 24 231041520 ps
T545 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.470268585 Apr 18 01:33:46 PM PDT 24 Apr 18 01:33:49 PM PDT 24 222112946 ps
T111 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.935910469 Apr 18 01:34:10 PM PDT 24 Apr 18 01:34:12 PM PDT 24 58287665 ps
T546 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4272680664 Apr 18 01:34:07 PM PDT 24 Apr 18 01:34:09 PM PDT 24 67319140 ps
T547 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4055030019 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:44 PM PDT 24 130440089 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2292923245 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:43 PM PDT 24 58696842 ps
T549 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1363887866 Apr 18 01:34:02 PM PDT 24 Apr 18 01:34:04 PM PDT 24 78147810 ps
T550 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.606175104 Apr 18 01:33:44 PM PDT 24 Apr 18 01:33:46 PM PDT 24 133533675 ps
T551 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.148113366 Apr 18 01:33:29 PM PDT 24 Apr 18 01:33:35 PM PDT 24 1033243596 ps
T552 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2382653269 Apr 18 01:34:00 PM PDT 24 Apr 18 01:34:01 PM PDT 24 231361619 ps
T553 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2946086487 Apr 18 01:33:53 PM PDT 24 Apr 18 01:33:55 PM PDT 24 146813802 ps
T116 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3442891140 Apr 18 01:34:15 PM PDT 24 Apr 18 01:34:18 PM PDT 24 778865170 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2147601561 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:43 PM PDT 24 208540178 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3433651508 Apr 18 01:33:35 PM PDT 24 Apr 18 01:33:37 PM PDT 24 145997036 ps
T556 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2065491329 Apr 18 01:34:01 PM PDT 24 Apr 18 01:34:03 PM PDT 24 86123717 ps
T557 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3664867899 Apr 18 01:33:45 PM PDT 24 Apr 18 01:33:47 PM PDT 24 90996618 ps
T558 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3006818415 Apr 18 01:34:03 PM PDT 24 Apr 18 01:34:05 PM PDT 24 136747485 ps
T559 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2806411444 Apr 18 01:34:05 PM PDT 24 Apr 18 01:34:08 PM PDT 24 153200211 ps
T560 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.826438901 Apr 18 01:33:47 PM PDT 24 Apr 18 01:33:49 PM PDT 24 79074215 ps
T561 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1168744531 Apr 18 01:33:58 PM PDT 24 Apr 18 01:34:00 PM PDT 24 198331796 ps
T562 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2602716111 Apr 18 01:34:06 PM PDT 24 Apr 18 01:34:08 PM PDT 24 179568827 ps
T563 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2636017548 Apr 18 01:33:53 PM PDT 24 Apr 18 01:33:56 PM PDT 24 264870443 ps
T564 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4161012750 Apr 18 01:33:52 PM PDT 24 Apr 18 01:33:55 PM PDT 24 195285063 ps
T565 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.226478363 Apr 18 01:33:43 PM PDT 24 Apr 18 01:33:45 PM PDT 24 251705190 ps
T117 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.4244657207 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:45 PM PDT 24 954826247 ps
T566 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3316020306 Apr 18 01:33:46 PM PDT 24 Apr 18 01:33:48 PM PDT 24 118285820 ps
T567 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1387900894 Apr 18 01:33:49 PM PDT 24 Apr 18 01:33:52 PM PDT 24 804949744 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2578186614 Apr 18 01:33:40 PM PDT 24 Apr 18 01:33:50 PM PDT 24 1525617179 ps
T569 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2893663179 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:45 PM PDT 24 126325330 ps
T570 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3674734800 Apr 18 01:33:37 PM PDT 24 Apr 18 01:33:39 PM PDT 24 74574387 ps
T571 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.753593749 Apr 18 01:33:38 PM PDT 24 Apr 18 01:33:41 PM PDT 24 240905228 ps
T572 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1187292354 Apr 18 01:34:09 PM PDT 24 Apr 18 01:34:11 PM PDT 24 144361759 ps
T573 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3275114316 Apr 18 01:33:40 PM PDT 24 Apr 18 01:33:43 PM PDT 24 270791826 ps
T574 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4162178219 Apr 18 01:33:43 PM PDT 24 Apr 18 01:33:45 PM PDT 24 148374373 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.215084619 Apr 18 01:33:35 PM PDT 24 Apr 18 01:33:38 PM PDT 24 247319592 ps
T576 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1245459706 Apr 18 01:33:44 PM PDT 24 Apr 18 01:33:46 PM PDT 24 129073228 ps
T94 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3384160448 Apr 18 01:33:43 PM PDT 24 Apr 18 01:33:44 PM PDT 24 58146514 ps
T577 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1668154099 Apr 18 01:33:52 PM PDT 24 Apr 18 01:33:54 PM PDT 24 423126883 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2779540466 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:46 PM PDT 24 448916757 ps
T579 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3008926292 Apr 18 01:33:40 PM PDT 24 Apr 18 01:33:42 PM PDT 24 175165251 ps
T580 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1230977754 Apr 18 01:33:49 PM PDT 24 Apr 18 01:33:50 PM PDT 24 71910216 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.919368975 Apr 18 01:33:30 PM PDT 24 Apr 18 01:33:32 PM PDT 24 177663180 ps
T114 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.90209694 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:44 PM PDT 24 468834267 ps
T582 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1209872791 Apr 18 01:34:15 PM PDT 24 Apr 18 01:34:17 PM PDT 24 84900848 ps
T583 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3313548398 Apr 18 01:34:01 PM PDT 24 Apr 18 01:34:03 PM PDT 24 115113260 ps
T584 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3144239353 Apr 18 01:33:43 PM PDT 24 Apr 18 01:33:45 PM PDT 24 65780569 ps
T585 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2515825850 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:44 PM PDT 24 138072131 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.370724947 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:44 PM PDT 24 247579015 ps
T587 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3672378415 Apr 18 01:33:52 PM PDT 24 Apr 18 01:33:54 PM PDT 24 113289175 ps
T588 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2538994336 Apr 18 01:33:37 PM PDT 24 Apr 18 01:33:39 PM PDT 24 69073180 ps
T589 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3060764972 Apr 18 01:33:40 PM PDT 24 Apr 18 01:33:43 PM PDT 24 468029625 ps
T590 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3266774110 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:44 PM PDT 24 77953195 ps
T591 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.699039204 Apr 18 01:33:45 PM PDT 24 Apr 18 01:33:47 PM PDT 24 238125261 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1662967686 Apr 18 01:33:35 PM PDT 24 Apr 18 01:33:37 PM PDT 24 133240239 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.383768990 Apr 18 01:33:44 PM PDT 24 Apr 18 01:33:45 PM PDT 24 144989647 ps
T594 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2189457330 Apr 18 01:34:06 PM PDT 24 Apr 18 01:34:09 PM PDT 24 253106531 ps
T595 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1092400869 Apr 18 01:34:14 PM PDT 24 Apr 18 01:34:17 PM PDT 24 494236280 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2858100943 Apr 18 01:33:48 PM PDT 24 Apr 18 01:33:50 PM PDT 24 118697369 ps
T597 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3209132940 Apr 18 01:33:50 PM PDT 24 Apr 18 01:33:54 PM PDT 24 402406938 ps
T598 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1750878617 Apr 18 01:34:14 PM PDT 24 Apr 18 01:34:17 PM PDT 24 158029047 ps
T599 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3875750113 Apr 18 01:33:40 PM PDT 24 Apr 18 01:33:44 PM PDT 24 283499409 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.657122490 Apr 18 01:33:40 PM PDT 24 Apr 18 01:33:43 PM PDT 24 166785648 ps
T601 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1635121483 Apr 18 01:33:31 PM PDT 24 Apr 18 01:33:35 PM PDT 24 905654531 ps
T602 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3301762733 Apr 18 01:33:38 PM PDT 24 Apr 18 01:33:41 PM PDT 24 241832953 ps
T603 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1531340124 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:48 PM PDT 24 185788708 ps
T604 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.699290895 Apr 18 01:33:43 PM PDT 24 Apr 18 01:33:45 PM PDT 24 122030977 ps
T605 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2593892946 Apr 18 01:33:33 PM PDT 24 Apr 18 01:33:34 PM PDT 24 57485502 ps
T606 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.205908388 Apr 18 01:34:06 PM PDT 24 Apr 18 01:34:10 PM PDT 24 399538408 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1466688875 Apr 18 01:33:41 PM PDT 24 Apr 18 01:33:43 PM PDT 24 87700177 ps
T608 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3455725890 Apr 18 01:33:38 PM PDT 24 Apr 18 01:33:40 PM PDT 24 82399951 ps
T609 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1811444050 Apr 18 01:33:34 PM PDT 24 Apr 18 01:33:35 PM PDT 24 99038538 ps
T610 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1408943104 Apr 18 01:34:24 PM PDT 24 Apr 18 01:34:34 PM PDT 24 123656177 ps
T611 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3885245336 Apr 18 01:33:45 PM PDT 24 Apr 18 01:33:47 PM PDT 24 65409275 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3564011593 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:45 PM PDT 24 233038632 ps
T613 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.362355164 Apr 18 01:34:04 PM PDT 24 Apr 18 01:34:05 PM PDT 24 207111298 ps
T614 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3417947828 Apr 18 01:33:58 PM PDT 24 Apr 18 01:33:59 PM PDT 24 107072728 ps
T122 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1449122411 Apr 18 01:34:06 PM PDT 24 Apr 18 01:34:10 PM PDT 24 905783585 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.806628908 Apr 18 01:33:42 PM PDT 24 Apr 18 01:33:46 PM PDT 24 881197510 ps
T616 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1314815656 Apr 18 01:34:16 PM PDT 24 Apr 18 01:34:18 PM PDT 24 63071433 ps
T617 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.221966936 Apr 18 01:33:38 PM PDT 24 Apr 18 01:33:40 PM PDT 24 117785184 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.353658553 Apr 18 01:34:26 PM PDT 24 Apr 18 01:34:32 PM PDT 24 940621713 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3553455412 Apr 18 01:33:43 PM PDT 24 Apr 18 01:33:46 PM PDT 24 420000756 ps
T620 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4281453596 Apr 18 01:34:05 PM PDT 24 Apr 18 01:34:07 PM PDT 24 113563859 ps

Test location /workspace/coverage/default/36.rstmgr_smoke.1104551655
Short name T9
Test name
Test status
Simulation time 116665792 ps
CPU time 1.18 seconds
Started Apr 18 01:35:15 PM PDT 24
Finished Apr 18 01:35:16 PM PDT 24
Peak memory 200976 kb
Host smart-b8b65d36-7244-44ad-a582-07be034326a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104551655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1104551655
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1649281702
Short name T67
Test name
Test status
Simulation time 2236055358 ps
CPU time 7.7 seconds
Started Apr 18 01:34:55 PM PDT 24
Finished Apr 18 01:35:03 PM PDT 24
Peak memory 201116 kb
Host smart-21b0d9a2-655f-4be3-8b2b-22876751d2ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649281702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1649281702
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3892718116
Short name T1
Test name
Test status
Simulation time 1224244904 ps
CPU time 5.66 seconds
Started Apr 18 01:34:49 PM PDT 24
Finished Apr 18 01:34:55 PM PDT 24
Peak memory 218056 kb
Host smart-a30575fc-04ff-4a59-b7df-570963db60f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892718116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3892718116
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3319616133
Short name T80
Test name
Test status
Simulation time 915362865 ps
CPU time 2.92 seconds
Started Apr 18 01:34:15 PM PDT 24
Finished Apr 18 01:34:19 PM PDT 24
Peak memory 201004 kb
Host smart-ec251c21-3a28-454e-b0ba-fe58c9f095f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319616133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3319616133
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.717276163
Short name T33
Test name
Test status
Simulation time 8650141856 ps
CPU time 13.02 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:40 PM PDT 24
Peak memory 217516 kb
Host smart-7b65d868-0a2e-4953-a5f8-af83fb43d3fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717276163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.717276163
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.687771009
Short name T7
Test name
Test status
Simulation time 355167369 ps
CPU time 2.19 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200800 kb
Host smart-c07d123e-e9b6-4abf-8205-94d0474f1a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687771009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.687771009
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.842643080
Short name T53
Test name
Test status
Simulation time 423157298 ps
CPU time 3 seconds
Started Apr 18 01:33:34 PM PDT 24
Finished Apr 18 01:33:38 PM PDT 24
Peak memory 209256 kb
Host smart-f22b7e66-e974-4a3a-a286-5e3c0376d29b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842643080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.842643080
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2333828790
Short name T90
Test name
Test status
Simulation time 12187335755 ps
CPU time 39.62 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:35:08 PM PDT 24
Peak memory 211028 kb
Host smart-b2fc7096-2a0d-4b26-85ee-b8ed5b22b857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333828790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2333828790
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1041668258
Short name T86
Test name
Test status
Simulation time 889362754 ps
CPU time 2.9 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 201028 kb
Host smart-640a511f-1770-4a7f-839f-9781fdb02df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041668258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1041668258
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3789501005
Short name T25
Test name
Test status
Simulation time 1886661621 ps
CPU time 7.06 seconds
Started Apr 18 01:34:55 PM PDT 24
Finished Apr 18 01:35:03 PM PDT 24
Peak memory 218588 kb
Host smart-d182995b-f4a5-4d70-ab67-3c639e2e85d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789501005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3789501005
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1792643436
Short name T129
Test name
Test status
Simulation time 153289432 ps
CPU time 1.07 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200732 kb
Host smart-67b1bb07-fd0f-422e-8205-17e42aee247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792643436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1792643436
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.838634176
Short name T134
Test name
Test status
Simulation time 62158105 ps
CPU time 0.71 seconds
Started Apr 18 01:34:04 PM PDT 24
Finished Apr 18 01:34:06 PM PDT 24
Peak memory 200484 kb
Host smart-df3ca68e-e323-4579-8464-6c150d8986fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838634176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.838634176
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3550402554
Short name T63
Test name
Test status
Simulation time 240903042 ps
CPU time 1.35 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200772 kb
Host smart-b9f046df-5a71-4264-9d20-ea3677ddb964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550402554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3550402554
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1037612015
Short name T85
Test name
Test status
Simulation time 475914608 ps
CPU time 3.16 seconds
Started Apr 18 01:33:45 PM PDT 24
Finished Apr 18 01:33:49 PM PDT 24
Peak memory 209300 kb
Host smart-97b5a1b2-195a-4a53-9c22-6e42d893ee50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037612015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1037612015
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1034425568
Short name T44
Test name
Test status
Simulation time 2168084714 ps
CPU time 8.33 seconds
Started Apr 18 01:35:17 PM PDT 24
Finished Apr 18 01:35:28 PM PDT 24
Peak memory 222636 kb
Host smart-d2ed1a7d-baf7-44ed-8368-18598578abb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034425568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1034425568
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.90209694
Short name T114
Test name
Test status
Simulation time 468834267 ps
CPU time 1.8 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:44 PM PDT 24
Peak memory 201132 kb
Host smart-8c2ebab9-e617-4573-9070-0f51dbcfdaa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90209694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.90209694
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2023733719
Short name T92
Test name
Test status
Simulation time 1952830460 ps
CPU time 6.88 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:38 PM PDT 24
Peak memory 200956 kb
Host smart-bcbff655-81a4-4533-ba8d-746c4dd30252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023733719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2023733719
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3442891140
Short name T116
Test name
Test status
Simulation time 778865170 ps
CPU time 2.76 seconds
Started Apr 18 01:34:15 PM PDT 24
Finished Apr 18 01:34:18 PM PDT 24
Peak memory 201120 kb
Host smart-64617495-c6ef-4d09-9ce8-d6a7770e5069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442891140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3442891140
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2741274989
Short name T107
Test name
Test status
Simulation time 245443073 ps
CPU time 1.67 seconds
Started Apr 18 01:33:51 PM PDT 24
Finished Apr 18 01:33:53 PM PDT 24
Peak memory 201132 kb
Host smart-e2394a44-d8c2-414e-bb83-0ce590574918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741274989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2741274989
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.279273717
Short name T14
Test name
Test status
Simulation time 157992754 ps
CPU time 0.91 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:26 PM PDT 24
Peak memory 200636 kb
Host smart-eb5e5542-9d22-4dc2-a5eb-45f6a8aeeb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279273717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.279273717
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2885111771
Short name T77
Test name
Test status
Simulation time 3025880961 ps
CPU time 12.8 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 201072 kb
Host smart-a40cd1d8-64d6-4a79-a7a2-7cc4a2f91320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885111771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2885111771
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.215084619
Short name T575
Test name
Test status
Simulation time 247319592 ps
CPU time 1.67 seconds
Started Apr 18 01:33:35 PM PDT 24
Finished Apr 18 01:33:38 PM PDT 24
Peak memory 201088 kb
Host smart-12840618-0507-48c9-8930-032972fa0a0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215084619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.215084619
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.148113366
Short name T551
Test name
Test status
Simulation time 1033243596 ps
CPU time 5.22 seconds
Started Apr 18 01:33:29 PM PDT 24
Finished Apr 18 01:33:35 PM PDT 24
Peak memory 201060 kb
Host smart-5de93801-de17-4e3a-8f62-f6653c1940e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148113366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.148113366
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1262106446
Short name T541
Test name
Test status
Simulation time 105029140 ps
CPU time 0.85 seconds
Started Apr 18 01:33:32 PM PDT 24
Finished Apr 18 01:33:33 PM PDT 24
Peak memory 200872 kb
Host smart-ed129747-4dd1-4bca-b40a-9fcd8fff4805
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262106446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
262106446
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.919368975
Short name T581
Test name
Test status
Simulation time 177663180 ps
CPU time 1.5 seconds
Started Apr 18 01:33:30 PM PDT 24
Finished Apr 18 01:33:32 PM PDT 24
Peak memory 209364 kb
Host smart-db34b1d2-dd70-4958-9801-416112ec206d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919368975 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.919368975
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2593892946
Short name T605
Test name
Test status
Simulation time 57485502 ps
CPU time 0.73 seconds
Started Apr 18 01:33:33 PM PDT 24
Finished Apr 18 01:33:34 PM PDT 24
Peak memory 200876 kb
Host smart-ac4bf358-6873-4e81-8eac-bcfe83db5129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593892946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2593892946
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3433651508
Short name T555
Test name
Test status
Simulation time 145997036 ps
CPU time 1.2 seconds
Started Apr 18 01:33:35 PM PDT 24
Finished Apr 18 01:33:37 PM PDT 24
Peak memory 200952 kb
Host smart-9fd33ff1-76f5-4b95-a85c-fa45b4929eb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433651508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3433651508
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.753593749
Short name T571
Test name
Test status
Simulation time 240905228 ps
CPU time 1.85 seconds
Started Apr 18 01:33:38 PM PDT 24
Finished Apr 18 01:33:41 PM PDT 24
Peak memory 209220 kb
Host smart-f5865b71-7df1-468f-8fb2-4ab1f5d25942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753593749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.753593749
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1635121483
Short name T601
Test name
Test status
Simulation time 905654531 ps
CPU time 3.09 seconds
Started Apr 18 01:33:31 PM PDT 24
Finished Apr 18 01:33:35 PM PDT 24
Peak memory 201040 kb
Host smart-041362bb-fed6-47dd-827a-64e3895ed031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635121483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1635121483
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3553455412
Short name T619
Test name
Test status
Simulation time 420000756 ps
CPU time 2.58 seconds
Started Apr 18 01:33:43 PM PDT 24
Finished Apr 18 01:33:46 PM PDT 24
Peak memory 201052 kb
Host smart-f8619aef-d85c-4a7d-bc40-b85766743fbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553455412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
553455412
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3609783096
Short name T112
Test name
Test status
Simulation time 268536799 ps
CPU time 3.22 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:46 PM PDT 24
Peak memory 200908 kb
Host smart-6c08a1fc-5dda-49b2-aef0-a869d7603d2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609783096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
609783096
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1811444050
Short name T609
Test name
Test status
Simulation time 99038538 ps
CPU time 0.83 seconds
Started Apr 18 01:33:34 PM PDT 24
Finished Apr 18 01:33:35 PM PDT 24
Peak memory 200908 kb
Host smart-39296ad8-055a-4e88-a99e-f4e8d5e477d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811444050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
811444050
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.657122490
Short name T600
Test name
Test status
Simulation time 166785648 ps
CPU time 1.42 seconds
Started Apr 18 01:33:40 PM PDT 24
Finished Apr 18 01:33:43 PM PDT 24
Peak memory 209404 kb
Host smart-d8e0324e-b419-4835-9a13-40295cda8481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657122490 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.657122490
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2292923245
Short name T548
Test name
Test status
Simulation time 58696842 ps
CPU time 0.77 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:43 PM PDT 24
Peak memory 200804 kb
Host smart-53624276-0cea-4665-9a97-ddb3c9535d12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292923245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2292923245
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3006818415
Short name T558
Test name
Test status
Simulation time 136747485 ps
CPU time 1.41 seconds
Started Apr 18 01:34:03 PM PDT 24
Finished Apr 18 01:34:05 PM PDT 24
Peak memory 201100 kb
Host smart-9f49e42b-757a-4a0d-aa1e-e1947ff23c02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006818415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3006818415
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3301762733
Short name T602
Test name
Test status
Simulation time 241832953 ps
CPU time 2.02 seconds
Started Apr 18 01:33:38 PM PDT 24
Finished Apr 18 01:33:41 PM PDT 24
Peak memory 209132 kb
Host smart-8610e207-4da2-4a99-b6eb-470c1f1b9355
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301762733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3301762733
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.360440633
Short name T82
Test name
Test status
Simulation time 428784783 ps
CPU time 1.7 seconds
Started Apr 18 01:33:39 PM PDT 24
Finished Apr 18 01:33:41 PM PDT 24
Peak memory 201124 kb
Host smart-06044672-3c2b-42a2-9a23-83333987276e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360440633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
360440633
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1531340124
Short name T603
Test name
Test status
Simulation time 185788708 ps
CPU time 1.22 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:48 PM PDT 24
Peak memory 209204 kb
Host smart-51e3714b-24aa-46d4-9553-e244f30edcce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531340124 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1531340124
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3144239353
Short name T584
Test name
Test status
Simulation time 65780569 ps
CPU time 0.75 seconds
Started Apr 18 01:33:43 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 200864 kb
Host smart-ff0c78c1-8230-4ca2-8391-e14c442f5233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144239353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3144239353
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3875750113
Short name T599
Test name
Test status
Simulation time 283499409 ps
CPU time 2.27 seconds
Started Apr 18 01:33:40 PM PDT 24
Finished Apr 18 01:33:44 PM PDT 24
Peak memory 209212 kb
Host smart-65673658-17f1-4dd8-9cd7-287f8d61a33d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875750113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3875750113
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.362551281
Short name T49
Test name
Test status
Simulation time 144038718 ps
CPU time 1.15 seconds
Started Apr 18 01:33:43 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 209204 kb
Host smart-2b135008-b266-4c5d-a406-90865e517269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362551281 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.362551281
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3717861393
Short name T50
Test name
Test status
Simulation time 59239661 ps
CPU time 0.79 seconds
Started Apr 18 01:33:57 PM PDT 24
Finished Apr 18 01:33:58 PM PDT 24
Peak memory 200832 kb
Host smart-db932dc7-1053-4782-9bb9-acc1f73d8787
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717861393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3717861393
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4162178219
Short name T574
Test name
Test status
Simulation time 148374373 ps
CPU time 1.1 seconds
Started Apr 18 01:33:43 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 200944 kb
Host smart-33652b59-51ac-47e7-bb4c-66fd69179cd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162178219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.4162178219
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4142224403
Short name T115
Test name
Test status
Simulation time 783278324 ps
CPU time 2.85 seconds
Started Apr 18 01:33:45 PM PDT 24
Finished Apr 18 01:33:49 PM PDT 24
Peak memory 201124 kb
Host smart-d153b30d-4354-4492-8d0f-6aad2dfe7f94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142224403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4142224403
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3672378415
Short name T587
Test name
Test status
Simulation time 113289175 ps
CPU time 0.93 seconds
Started Apr 18 01:33:52 PM PDT 24
Finished Apr 18 01:33:54 PM PDT 24
Peak memory 201048 kb
Host smart-cd30f0b6-7a99-4575-a0ac-509117bbc556
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672378415 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3672378415
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.826438901
Short name T560
Test name
Test status
Simulation time 79074215 ps
CPU time 0.81 seconds
Started Apr 18 01:33:47 PM PDT 24
Finished Apr 18 01:33:49 PM PDT 24
Peak memory 200824 kb
Host smart-3e27bed8-b5fc-49cb-8780-be8692fe84cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826438901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.826438901
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1187292354
Short name T572
Test name
Test status
Simulation time 144361759 ps
CPU time 1.07 seconds
Started Apr 18 01:34:09 PM PDT 24
Finished Apr 18 01:34:11 PM PDT 24
Peak memory 200944 kb
Host smart-d5fe3788-db14-47c4-8fc6-17b45482ae38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187292354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1187292354
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2893663179
Short name T569
Test name
Test status
Simulation time 126325330 ps
CPU time 1.74 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 209304 kb
Host smart-3b1573ad-7990-4c9f-a9fa-25432b5b38f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893663179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2893663179
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2582440778
Short name T84
Test name
Test status
Simulation time 819295531 ps
CPU time 2.85 seconds
Started Apr 18 01:33:50 PM PDT 24
Finished Apr 18 01:33:54 PM PDT 24
Peak memory 201060 kb
Host smart-9c75b4b1-fbfb-48e1-be2f-11d954a3c2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582440778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2582440778
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2946086487
Short name T553
Test name
Test status
Simulation time 146813802 ps
CPU time 1.07 seconds
Started Apr 18 01:33:53 PM PDT 24
Finished Apr 18 01:33:55 PM PDT 24
Peak memory 201108 kb
Host smart-da05ad9d-19b4-432e-a758-bac85a5bc214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946086487 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2946086487
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3921271737
Short name T104
Test name
Test status
Simulation time 61413112 ps
CPU time 0.8 seconds
Started Apr 18 01:33:48 PM PDT 24
Finished Apr 18 01:33:49 PM PDT 24
Peak memory 200880 kb
Host smart-c6c6491f-413f-455c-bf96-cd46a7e3acaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921271737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3921271737
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.940964036
Short name T103
Test name
Test status
Simulation time 72872261 ps
CPU time 0.95 seconds
Started Apr 18 01:33:58 PM PDT 24
Finished Apr 18 01:33:59 PM PDT 24
Peak memory 200972 kb
Host smart-9f0983af-b8c2-40f4-a002-f6417b179c75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940964036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.940964036
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2189457330
Short name T594
Test name
Test status
Simulation time 253106531 ps
CPU time 1.81 seconds
Started Apr 18 01:34:06 PM PDT 24
Finished Apr 18 01:34:09 PM PDT 24
Peak memory 209220 kb
Host smart-af01ae5f-2ba3-4044-ac09-691fdad062da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189457330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2189457330
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1449122411
Short name T122
Test name
Test status
Simulation time 905783585 ps
CPU time 2.9 seconds
Started Apr 18 01:34:06 PM PDT 24
Finished Apr 18 01:34:10 PM PDT 24
Peak memory 201020 kb
Host smart-ba71280f-f13a-49b5-8ac7-d9e1513df0be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449122411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1449122411
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4161012750
Short name T564
Test name
Test status
Simulation time 195285063 ps
CPU time 2.02 seconds
Started Apr 18 01:33:52 PM PDT 24
Finished Apr 18 01:33:55 PM PDT 24
Peak memory 209644 kb
Host smart-41b91227-4230-454e-8bd7-82b5c44c9a57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161012750 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4161012750
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1230977754
Short name T580
Test name
Test status
Simulation time 71910216 ps
CPU time 0.81 seconds
Started Apr 18 01:33:49 PM PDT 24
Finished Apr 18 01:33:50 PM PDT 24
Peak memory 200880 kb
Host smart-977d3b8b-5525-4f1e-8f9e-eeb726083f38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230977754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1230977754
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2382653269
Short name T552
Test name
Test status
Simulation time 231361619 ps
CPU time 1.52 seconds
Started Apr 18 01:34:00 PM PDT 24
Finished Apr 18 01:34:01 PM PDT 24
Peak memory 201032 kb
Host smart-eee1028c-9548-4e44-b9e5-e9e6bd44283b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382653269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2382653269
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1750878617
Short name T598
Test name
Test status
Simulation time 158029047 ps
CPU time 2.26 seconds
Started Apr 18 01:34:14 PM PDT 24
Finished Apr 18 01:34:17 PM PDT 24
Peak memory 209316 kb
Host smart-d5be6337-0b5a-4871-9c5c-883dc8ed8769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750878617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1750878617
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1387900894
Short name T567
Test name
Test status
Simulation time 804949744 ps
CPU time 2.83 seconds
Started Apr 18 01:33:49 PM PDT 24
Finished Apr 18 01:33:52 PM PDT 24
Peak memory 201224 kb
Host smart-9f5400ae-9559-4314-91c0-edcfb571a750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387900894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1387900894
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1168744531
Short name T561
Test name
Test status
Simulation time 198331796 ps
CPU time 1.25 seconds
Started Apr 18 01:33:58 PM PDT 24
Finished Apr 18 01:34:00 PM PDT 24
Peak memory 209196 kb
Host smart-97867f79-19a4-49b5-823c-42b33100da81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168744531 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1168744531
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4272680664
Short name T546
Test name
Test status
Simulation time 67319140 ps
CPU time 0.8 seconds
Started Apr 18 01:34:07 PM PDT 24
Finished Apr 18 01:34:09 PM PDT 24
Peak memory 200860 kb
Host smart-6f912ae5-f0cc-4caa-b547-c346e0c09718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272680664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.4272680664
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2858100943
Short name T596
Test name
Test status
Simulation time 118697369 ps
CPU time 1.06 seconds
Started Apr 18 01:33:48 PM PDT 24
Finished Apr 18 01:33:50 PM PDT 24
Peak memory 200916 kb
Host smart-818656ea-8bf7-4035-8ed8-c83239bbae58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858100943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2858100943
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3313548398
Short name T583
Test name
Test status
Simulation time 115113260 ps
CPU time 1.63 seconds
Started Apr 18 01:34:01 PM PDT 24
Finished Apr 18 01:34:03 PM PDT 24
Peak memory 209252 kb
Host smart-d3dde642-6f39-4a63-b9e6-4c5f160fc938
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313548398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3313548398
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.672996487
Short name T51
Test name
Test status
Simulation time 502446477 ps
CPU time 1.98 seconds
Started Apr 18 01:34:04 PM PDT 24
Finished Apr 18 01:34:07 PM PDT 24
Peak memory 201176 kb
Host smart-6423aae4-4b93-474d-9e3b-945497bb64f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672996487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.672996487
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3316020306
Short name T566
Test name
Test status
Simulation time 118285820 ps
CPU time 0.95 seconds
Started Apr 18 01:33:46 PM PDT 24
Finished Apr 18 01:33:48 PM PDT 24
Peak memory 200984 kb
Host smart-22d56176-4509-49f6-9d71-18aa3e92854d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316020306 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3316020306
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.935910469
Short name T111
Test name
Test status
Simulation time 58287665 ps
CPU time 0.74 seconds
Started Apr 18 01:34:10 PM PDT 24
Finished Apr 18 01:34:12 PM PDT 24
Peak memory 200792 kb
Host smart-ef3916a9-772a-499d-8d44-6611b26af63f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935910469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.935910469
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.362355164
Short name T613
Test name
Test status
Simulation time 207111298 ps
CPU time 1.53 seconds
Started Apr 18 01:34:04 PM PDT 24
Finished Apr 18 01:34:05 PM PDT 24
Peak memory 201072 kb
Host smart-e73a10b9-6aba-4823-ac80-85189a2ebe2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362355164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.362355164
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3209132940
Short name T597
Test name
Test status
Simulation time 402406938 ps
CPU time 2.98 seconds
Started Apr 18 01:33:50 PM PDT 24
Finished Apr 18 01:33:54 PM PDT 24
Peak memory 217240 kb
Host smart-f2da023d-e65a-47bd-8d5d-7022641bfee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209132940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3209132940
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1668154099
Short name T577
Test name
Test status
Simulation time 423126883 ps
CPU time 1.8 seconds
Started Apr 18 01:33:52 PM PDT 24
Finished Apr 18 01:33:54 PM PDT 24
Peak memory 201144 kb
Host smart-54e1a9f1-d98b-4d13-bde8-7a8d09cc6574
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668154099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1668154099
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3417947828
Short name T614
Test name
Test status
Simulation time 107072728 ps
CPU time 0.98 seconds
Started Apr 18 01:33:58 PM PDT 24
Finished Apr 18 01:33:59 PM PDT 24
Peak memory 200912 kb
Host smart-c192733b-3392-4494-8678-e43d899cd3f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417947828 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3417947828
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2065491329
Short name T556
Test name
Test status
Simulation time 86123717 ps
CPU time 0.89 seconds
Started Apr 18 01:34:01 PM PDT 24
Finished Apr 18 01:34:03 PM PDT 24
Peak memory 200908 kb
Host smart-68af056a-aec5-410b-bf2a-0af9a7e8b4be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065491329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2065491329
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1466357617
Short name T109
Test name
Test status
Simulation time 130404448 ps
CPU time 1.07 seconds
Started Apr 18 01:34:10 PM PDT 24
Finished Apr 18 01:34:12 PM PDT 24
Peak memory 200944 kb
Host smart-37150fb3-f292-431a-9e8b-44a0fa5adedb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466357617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1466357617
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2636017548
Short name T563
Test name
Test status
Simulation time 264870443 ps
CPU time 2.22 seconds
Started Apr 18 01:33:53 PM PDT 24
Finished Apr 18 01:33:56 PM PDT 24
Peak memory 211364 kb
Host smart-61fca1e4-c88c-4f86-8cf1-de4fe7eb216f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636017548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2636017548
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.987385861
Short name T48
Test name
Test status
Simulation time 477819861 ps
CPU time 2.2 seconds
Started Apr 18 01:33:49 PM PDT 24
Finished Apr 18 01:33:52 PM PDT 24
Peak memory 201044 kb
Host smart-c76b8bce-e30f-4662-9d05-17daf041e63d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987385861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.987385861
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1408943104
Short name T610
Test name
Test status
Simulation time 123656177 ps
CPU time 1.22 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 209140 kb
Host smart-34bb1557-df1a-452c-aaf4-dce373f2cb0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408943104 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1408943104
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1209872791
Short name T582
Test name
Test status
Simulation time 84900848 ps
CPU time 0.88 seconds
Started Apr 18 01:34:15 PM PDT 24
Finished Apr 18 01:34:17 PM PDT 24
Peak memory 200860 kb
Host smart-2b7b084f-195e-49d2-87fa-66c520491c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209872791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1209872791
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.392382883
Short name T110
Test name
Test status
Simulation time 231041520 ps
CPU time 1.51 seconds
Started Apr 18 01:34:06 PM PDT 24
Finished Apr 18 01:34:09 PM PDT 24
Peak memory 200972 kb
Host smart-03edee28-8fe1-4611-ac69-dc5898f22579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392382883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.392382883
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2806411444
Short name T559
Test name
Test status
Simulation time 153200211 ps
CPU time 2.17 seconds
Started Apr 18 01:34:05 PM PDT 24
Finished Apr 18 01:34:08 PM PDT 24
Peak memory 209228 kb
Host smart-82d09412-791c-43af-bb6c-bf936a456513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806411444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2806411444
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2602716111
Short name T562
Test name
Test status
Simulation time 179568827 ps
CPU time 1.25 seconds
Started Apr 18 01:34:06 PM PDT 24
Finished Apr 18 01:34:08 PM PDT 24
Peak memory 201208 kb
Host smart-a66e7e22-6679-4e4a-94ae-66b23474bc50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602716111 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2602716111
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1314815656
Short name T616
Test name
Test status
Simulation time 63071433 ps
CPU time 0.8 seconds
Started Apr 18 01:34:16 PM PDT 24
Finished Apr 18 01:34:18 PM PDT 24
Peak memory 200768 kb
Host smart-8c6f1d30-8133-4b1f-94c5-403f36fa9a0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314815656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1314815656
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1502521173
Short name T106
Test name
Test status
Simulation time 135499350 ps
CPU time 1.16 seconds
Started Apr 18 01:34:15 PM PDT 24
Finished Apr 18 01:34:17 PM PDT 24
Peak memory 200900 kb
Host smart-945a338c-ba62-4b73-bbb4-7cd1b28fe146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502521173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1502521173
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.205908388
Short name T606
Test name
Test status
Simulation time 399538408 ps
CPU time 2.76 seconds
Started Apr 18 01:34:06 PM PDT 24
Finished Apr 18 01:34:10 PM PDT 24
Peak memory 209292 kb
Host smart-d013b58a-d15c-4312-9610-e3b8b4459471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205908388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.205908388
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1092400869
Short name T595
Test name
Test status
Simulation time 494236280 ps
CPU time 2.08 seconds
Started Apr 18 01:34:14 PM PDT 24
Finished Apr 18 01:34:17 PM PDT 24
Peak memory 201060 kb
Host smart-502a8729-ae3c-46c6-a8af-911a68dffff7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092400869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1092400869
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1550567415
Short name T543
Test name
Test status
Simulation time 199571622 ps
CPU time 1.52 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:44 PM PDT 24
Peak memory 201112 kb
Host smart-fe58a691-04e7-4f18-b3a1-e816a656a9bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550567415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
550567415
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1105698892
Short name T544
Test name
Test status
Simulation time 269409322 ps
CPU time 3.09 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:46 PM PDT 24
Peak memory 201008 kb
Host smart-9eb2e3a3-1c5f-419e-aad3-a0ab2b10f0d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105698892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
105698892
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.383768990
Short name T593
Test name
Test status
Simulation time 144989647 ps
CPU time 0.91 seconds
Started Apr 18 01:33:44 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 200780 kb
Host smart-c1109638-ae9f-4fe5-895b-a4f13148bd7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383768990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.383768990
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2147601561
Short name T554
Test name
Test status
Simulation time 208540178 ps
CPU time 1.31 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:43 PM PDT 24
Peak memory 209184 kb
Host smart-796ce94a-09fd-45ef-be16-8d49afd5d42b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147601561 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2147601561
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2538994336
Short name T588
Test name
Test status
Simulation time 69073180 ps
CPU time 0.76 seconds
Started Apr 18 01:33:37 PM PDT 24
Finished Apr 18 01:33:39 PM PDT 24
Peak memory 200864 kb
Host smart-4e34822f-c399-4a38-a537-f5fe946071d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538994336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2538994336
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1245459706
Short name T576
Test name
Test status
Simulation time 129073228 ps
CPU time 1.33 seconds
Started Apr 18 01:33:44 PM PDT 24
Finished Apr 18 01:33:46 PM PDT 24
Peak memory 201108 kb
Host smart-22245c98-53c3-4a2c-91ac-c8a9710cadb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245459706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1245459706
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.991930381
Short name T52
Test name
Test status
Simulation time 511944420 ps
CPU time 3.23 seconds
Started Apr 18 01:33:55 PM PDT 24
Finished Apr 18 01:33:58 PM PDT 24
Peak memory 209296 kb
Host smart-40a77ffb-e76b-4f0d-b0b5-170c62843264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991930381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.991930381
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.806628908
Short name T615
Test name
Test status
Simulation time 881197510 ps
CPU time 3.01 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:46 PM PDT 24
Peak memory 201124 kb
Host smart-b9c9c75b-8e53-4cf0-9e25-0fc9c5981314
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806628908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
806628908
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.370724947
Short name T586
Test name
Test status
Simulation time 247579015 ps
CPU time 1.66 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:44 PM PDT 24
Peak memory 201008 kb
Host smart-8d1e31f3-fe18-4c87-8d05-4b2778fa4e7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370724947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.370724947
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1261264936
Short name T542
Test name
Test status
Simulation time 1562172472 ps
CPU time 7.78 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:50 PM PDT 24
Peak memory 209224 kb
Host smart-cee8280a-6b2d-4c14-98b3-51d7a4940d1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261264936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
261264936
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2974351549
Short name T93
Test name
Test status
Simulation time 99109698 ps
CPU time 0.8 seconds
Started Apr 18 01:33:40 PM PDT 24
Finished Apr 18 01:33:42 PM PDT 24
Peak memory 200844 kb
Host smart-13f371e9-385e-442c-8f5a-76919d1a38ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974351549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
974351549
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.699290895
Short name T604
Test name
Test status
Simulation time 122030977 ps
CPU time 1.31 seconds
Started Apr 18 01:33:43 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 209236 kb
Host smart-c4d46f45-37cc-480d-9e86-358f6d834683
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699290895 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.699290895
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3384160448
Short name T94
Test name
Test status
Simulation time 58146514 ps
CPU time 0.76 seconds
Started Apr 18 01:33:43 PM PDT 24
Finished Apr 18 01:33:44 PM PDT 24
Peak memory 200880 kb
Host smart-3b0cb815-ea10-45d1-ab81-c4b7458b018f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384160448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3384160448
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1662967686
Short name T592
Test name
Test status
Simulation time 133240239 ps
CPU time 1.22 seconds
Started Apr 18 01:33:35 PM PDT 24
Finished Apr 18 01:33:37 PM PDT 24
Peak memory 201160 kb
Host smart-c533fb8c-8ce7-4319-a8d0-c9eb2f6da046
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662967686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1662967686
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2609958251
Short name T118
Test name
Test status
Simulation time 375163868 ps
CPU time 2.49 seconds
Started Apr 18 01:33:45 PM PDT 24
Finished Apr 18 01:33:48 PM PDT 24
Peak memory 209336 kb
Host smart-9e57561b-c7b3-44a5-a653-1c1cb34683d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609958251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2609958251
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3564011593
Short name T612
Test name
Test status
Simulation time 233038632 ps
CPU time 1.62 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 201064 kb
Host smart-39767af8-b301-4d6f-a0b4-6b84da80a51b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564011593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
564011593
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2578186614
Short name T568
Test name
Test status
Simulation time 1525617179 ps
CPU time 8.15 seconds
Started Apr 18 01:33:40 PM PDT 24
Finished Apr 18 01:33:50 PM PDT 24
Peak memory 201068 kb
Host smart-0bcceda0-fd6b-417a-8381-262e30408c73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578186614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
578186614
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2515825850
Short name T585
Test name
Test status
Simulation time 138072131 ps
CPU time 0.91 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:44 PM PDT 24
Peak memory 200832 kb
Host smart-41f2739a-340d-4a42-b146-343432875707
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515825850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
515825850
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4281453596
Short name T620
Test name
Test status
Simulation time 113563859 ps
CPU time 0.98 seconds
Started Apr 18 01:34:05 PM PDT 24
Finished Apr 18 01:34:07 PM PDT 24
Peak memory 201000 kb
Host smart-13d001b3-8d48-4392-babd-aaf07e8e1837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281453596 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.4281453596
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3885245336
Short name T611
Test name
Test status
Simulation time 65409275 ps
CPU time 0.75 seconds
Started Apr 18 01:33:45 PM PDT 24
Finished Apr 18 01:33:47 PM PDT 24
Peak memory 200768 kb
Host smart-5054f2e5-e359-4291-8834-3643dfa9cd5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885245336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3885245336
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.226478363
Short name T565
Test name
Test status
Simulation time 251705190 ps
CPU time 1.49 seconds
Started Apr 18 01:33:43 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 201096 kb
Host smart-6655adf9-bb99-4a91-ab94-9bfef909f790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226478363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.226478363
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2779540466
Short name T578
Test name
Test status
Simulation time 448916757 ps
CPU time 3.38 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:46 PM PDT 24
Peak memory 209312 kb
Host smart-b104c2ef-71e9-4923-8f03-608ba91b9a61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779540466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2779540466
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.353658553
Short name T618
Test name
Test status
Simulation time 940621713 ps
CPU time 3.44 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 201200 kb
Host smart-8f81209e-4910-4478-88be-70fabd66327b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353658553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
353658553
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3581699449
Short name T81
Test name
Test status
Simulation time 163199104 ps
CPU time 1.31 seconds
Started Apr 18 01:33:40 PM PDT 24
Finished Apr 18 01:33:43 PM PDT 24
Peak memory 209304 kb
Host smart-b7f384dd-3166-4133-9efb-846ba8d2c597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581699449 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3581699449
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3674734800
Short name T570
Test name
Test status
Simulation time 74574387 ps
CPU time 0.8 seconds
Started Apr 18 01:33:37 PM PDT 24
Finished Apr 18 01:33:39 PM PDT 24
Peak memory 201088 kb
Host smart-66519575-f1d3-4e0a-b2c9-d9b3c3d42f11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674734800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3674734800
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4055030019
Short name T547
Test name
Test status
Simulation time 130440089 ps
CPU time 1.2 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:44 PM PDT 24
Peak memory 200972 kb
Host smart-ee7426da-5185-43e4-835f-191218dcbc9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055030019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4055030019
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.606175104
Short name T550
Test name
Test status
Simulation time 133533675 ps
CPU time 1.05 seconds
Started Apr 18 01:33:44 PM PDT 24
Finished Apr 18 01:33:46 PM PDT 24
Peak memory 201020 kb
Host smart-6fb2873f-cf36-40b1-ab20-1257911b90b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606175104 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.606175104
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1363887866
Short name T549
Test name
Test status
Simulation time 78147810 ps
CPU time 0.87 seconds
Started Apr 18 01:34:02 PM PDT 24
Finished Apr 18 01:34:04 PM PDT 24
Peak memory 200800 kb
Host smart-df2883b6-0e6d-4e68-96c9-9e16f21c9f2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363887866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1363887866
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1928422280
Short name T108
Test name
Test status
Simulation time 167358960 ps
CPU time 1.13 seconds
Started Apr 18 01:33:38 PM PDT 24
Finished Apr 18 01:33:40 PM PDT 24
Peak memory 200940 kb
Host smart-febb95bd-c015-4968-9c90-c934dd67be76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928422280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1928422280
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.470268585
Short name T545
Test name
Test status
Simulation time 222112946 ps
CPU time 1.71 seconds
Started Apr 18 01:33:46 PM PDT 24
Finished Apr 18 01:33:49 PM PDT 24
Peak memory 209284 kb
Host smart-c6688c40-9cfc-408f-a2f1-cb32ec85affd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470268585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.470268585
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1143281968
Short name T123
Test name
Test status
Simulation time 877789355 ps
CPU time 2.93 seconds
Started Apr 18 01:33:40 PM PDT 24
Finished Apr 18 01:33:44 PM PDT 24
Peak memory 201172 kb
Host smart-026cbec1-95f5-4ea7-9244-72a5e2e0bad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143281968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1143281968
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.221966936
Short name T617
Test name
Test status
Simulation time 117785184 ps
CPU time 0.96 seconds
Started Apr 18 01:33:38 PM PDT 24
Finished Apr 18 01:33:40 PM PDT 24
Peak memory 200924 kb
Host smart-0bcc1e5f-5776-4fb9-a0ad-a3f6391fe33c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221966936 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.221966936
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1466688875
Short name T607
Test name
Test status
Simulation time 87700177 ps
CPU time 0.8 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:43 PM PDT 24
Peak memory 200832 kb
Host smart-35da790d-c2d5-4cea-a923-00f38276a0dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466688875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1466688875
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.699039204
Short name T591
Test name
Test status
Simulation time 238125261 ps
CPU time 1.59 seconds
Started Apr 18 01:33:45 PM PDT 24
Finished Apr 18 01:33:47 PM PDT 24
Peak memory 201136 kb
Host smart-6769f17e-ce34-4c08-9cc9-cbe74338fbd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699039204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.699039204
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3486337541
Short name T113
Test name
Test status
Simulation time 423870507 ps
CPU time 3.14 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:46 PM PDT 24
Peak memory 209240 kb
Host smart-273c78d8-9020-4d76-817b-daf5d478b706
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486337541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3486337541
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.4244657207
Short name T117
Test name
Test status
Simulation time 954826247 ps
CPU time 3.15 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 201096 kb
Host smart-732b579a-af59-4b37-86b9-35d5d0a1fc65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244657207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.4244657207
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2166364739
Short name T78
Test name
Test status
Simulation time 114194708 ps
CPU time 0.95 seconds
Started Apr 18 01:33:38 PM PDT 24
Finished Apr 18 01:33:40 PM PDT 24
Peak memory 200900 kb
Host smart-6d8907cf-047d-44ff-bfae-65e36a4f7227
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166364739 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2166364739
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3266774110
Short name T590
Test name
Test status
Simulation time 77953195 ps
CPU time 0.85 seconds
Started Apr 18 01:33:42 PM PDT 24
Finished Apr 18 01:33:44 PM PDT 24
Peak memory 200744 kb
Host smart-3c443176-338b-4ce7-ac0c-af3d4faa39a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266774110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3266774110
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3664867899
Short name T557
Test name
Test status
Simulation time 90996618 ps
CPU time 1.16 seconds
Started Apr 18 01:33:45 PM PDT 24
Finished Apr 18 01:33:47 PM PDT 24
Peak memory 201180 kb
Host smart-b6b11f7e-277d-44c1-a4cf-019d753030db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664867899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3664867899
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1790809280
Short name T83
Test name
Test status
Simulation time 277356490 ps
CPU time 2.02 seconds
Started Apr 18 01:33:50 PM PDT 24
Finished Apr 18 01:33:52 PM PDT 24
Peak memory 217296 kb
Host smart-90cb1543-0366-46cd-b661-1130c9583102
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790809280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1790809280
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3060764972
Short name T589
Test name
Test status
Simulation time 468029625 ps
CPU time 1.79 seconds
Started Apr 18 01:33:40 PM PDT 24
Finished Apr 18 01:33:43 PM PDT 24
Peak memory 201132 kb
Host smart-9d45d4e8-2dab-4e81-a241-6ae8beb2c4df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060764972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3060764972
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3008926292
Short name T579
Test name
Test status
Simulation time 175165251 ps
CPU time 1.14 seconds
Started Apr 18 01:33:40 PM PDT 24
Finished Apr 18 01:33:42 PM PDT 24
Peak memory 200960 kb
Host smart-ea6c53b1-276b-4d1f-8525-a65bd10877e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008926292 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3008926292
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3455725890
Short name T608
Test name
Test status
Simulation time 82399951 ps
CPU time 0.84 seconds
Started Apr 18 01:33:38 PM PDT 24
Finished Apr 18 01:33:40 PM PDT 24
Peak memory 200872 kb
Host smart-79246337-a99d-4335-a7f3-dc3a4c366094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455725890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3455725890
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3675538835
Short name T105
Test name
Test status
Simulation time 73991816 ps
CPU time 0.92 seconds
Started Apr 18 01:33:43 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 200868 kb
Host smart-09768674-a0d6-4375-a4e9-3c8ccb775f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675538835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3675538835
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3275114316
Short name T573
Test name
Test status
Simulation time 270791826 ps
CPU time 2.22 seconds
Started Apr 18 01:33:40 PM PDT 24
Finished Apr 18 01:33:43 PM PDT 24
Peak memory 209204 kb
Host smart-e526eea4-c785-4fd8-ae28-8925dd794628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275114316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3275114316
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2340664135
Short name T79
Test name
Test status
Simulation time 933117824 ps
CPU time 3.19 seconds
Started Apr 18 01:33:41 PM PDT 24
Finished Apr 18 01:33:45 PM PDT 24
Peak memory 201068 kb
Host smart-6424761d-5a65-4709-92b7-a19ae03b846b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340664135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2340664135
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3891625840
Short name T193
Test name
Test status
Simulation time 68997364 ps
CPU time 0.8 seconds
Started Apr 18 01:34:08 PM PDT 24
Finished Apr 18 01:34:10 PM PDT 24
Peak memory 200624 kb
Host smart-0afc9e38-3bc5-4329-b13c-f119a619c701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891625840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3891625840
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3184602275
Short name T42
Test name
Test status
Simulation time 1219001126 ps
CPU time 5.3 seconds
Started Apr 18 01:34:20 PM PDT 24
Finished Apr 18 01:34:26 PM PDT 24
Peak memory 218012 kb
Host smart-4d8e7797-c4c6-4d75-a9d1-4ef39329f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184602275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3184602275
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.244992964
Short name T354
Test name
Test status
Simulation time 245070289 ps
CPU time 1.12 seconds
Started Apr 18 01:34:18 PM PDT 24
Finished Apr 18 01:34:19 PM PDT 24
Peak memory 218072 kb
Host smart-1f21974d-32fc-4b52-8430-d9984535c54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244992964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.244992964
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3570448295
Short name T200
Test name
Test status
Simulation time 2104126223 ps
CPU time 7.69 seconds
Started Apr 18 01:33:59 PM PDT 24
Finished Apr 18 01:34:07 PM PDT 24
Peak memory 200980 kb
Host smart-adbd0965-93e0-4fbe-ab81-2764ec7cd6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570448295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3570448295
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1851155361
Short name T493
Test name
Test status
Simulation time 150692843 ps
CPU time 1.14 seconds
Started Apr 18 01:34:20 PM PDT 24
Finished Apr 18 01:34:21 PM PDT 24
Peak memory 200812 kb
Host smart-4ab24a5b-d982-4cb6-99ac-bd49bbeded9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851155361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1851155361
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2047699959
Short name T426
Test name
Test status
Simulation time 198275125 ps
CPU time 1.39 seconds
Started Apr 18 01:34:13 PM PDT 24
Finished Apr 18 01:34:15 PM PDT 24
Peak memory 200992 kb
Host smart-a5ed385f-839d-4ed3-b440-3538088bff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047699959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2047699959
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1639017979
Short name T267
Test name
Test status
Simulation time 525030036 ps
CPU time 2.67 seconds
Started Apr 18 01:34:20 PM PDT 24
Finished Apr 18 01:34:23 PM PDT 24
Peak memory 200708 kb
Host smart-e2489956-a9db-4963-8b29-d6adfcfb41a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639017979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1639017979
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.689751895
Short name T275
Test name
Test status
Simulation time 231444040 ps
CPU time 1.36 seconds
Started Apr 18 01:34:04 PM PDT 24
Finished Apr 18 01:34:06 PM PDT 24
Peak memory 200964 kb
Host smart-085eee9e-58eb-472b-9fcd-c3b80a825757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689751895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.689751895
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2859139476
Short name T479
Test name
Test status
Simulation time 2166758082 ps
CPU time 7.42 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 222192 kb
Host smart-b42e9ca4-5ef6-4046-a576-04aa89cc63eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859139476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2859139476
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.227653513
Short name T187
Test name
Test status
Simulation time 244949786 ps
CPU time 1.08 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 218140 kb
Host smart-4aaac03c-3d86-4be0-9e2a-0d9cf1257c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227653513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.227653513
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2632679781
Short name T514
Test name
Test status
Simulation time 236540089 ps
CPU time 0.97 seconds
Started Apr 18 01:34:13 PM PDT 24
Finished Apr 18 01:34:15 PM PDT 24
Peak memory 200516 kb
Host smart-b2209189-7db1-485d-bad7-bae148b2a452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632679781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2632679781
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2893667561
Short name T506
Test name
Test status
Simulation time 1626499129 ps
CPU time 5.93 seconds
Started Apr 18 01:34:10 PM PDT 24
Finished Apr 18 01:34:17 PM PDT 24
Peak memory 200968 kb
Host smart-b3f7b8d3-f25f-4a1d-8d95-a45a27ab6bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893667561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2893667561
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3992366548
Short name T54
Test name
Test status
Simulation time 8320257127 ps
CPU time 12.88 seconds
Started Apr 18 01:34:19 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 217540 kb
Host smart-2b4d33f8-3f94-4f6b-8178-9737111d6cb3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992366548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3992366548
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.465031055
Short name T520
Test name
Test status
Simulation time 119528503 ps
CPU time 1.21 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 200916 kb
Host smart-f6446145-c2c2-4c29-b358-c708a92c84b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465031055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.465031055
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1999918544
Short name T483
Test name
Test status
Simulation time 12198290241 ps
CPU time 39.41 seconds
Started Apr 18 01:34:12 PM PDT 24
Finished Apr 18 01:34:52 PM PDT 24
Peak memory 209168 kb
Host smart-73d78cb0-e8ae-4dff-b970-522a256056e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999918544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1999918544
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2410770532
Short name T274
Test name
Test status
Simulation time 114902724 ps
CPU time 1.4 seconds
Started Apr 18 01:34:12 PM PDT 24
Finished Apr 18 01:34:14 PM PDT 24
Peak memory 200800 kb
Host smart-73799084-1686-455a-aced-8b3d25cb3ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410770532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2410770532
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3935876607
Short name T405
Test name
Test status
Simulation time 199653553 ps
CPU time 1.21 seconds
Started Apr 18 01:34:11 PM PDT 24
Finished Apr 18 01:34:12 PM PDT 24
Peak memory 200816 kb
Host smart-410e926c-50bc-4e6d-813d-691bce6b4981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935876607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3935876607
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.4275636270
Short name T181
Test name
Test status
Simulation time 64821414 ps
CPU time 0.76 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:26 PM PDT 24
Peak memory 200608 kb
Host smart-d45f33f1-6b1d-42fa-85d5-2f0cdad62ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275636270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4275636270
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.133606254
Short name T321
Test name
Test status
Simulation time 1223327958 ps
CPU time 6.09 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 222476 kb
Host smart-b2462a09-a89c-4f93-b6cb-98d88cf54737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133606254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.133606254
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2345948189
Short name T277
Test name
Test status
Simulation time 243904189 ps
CPU time 1.06 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 218080 kb
Host smart-8930ee3c-5ba2-4808-98ac-e1a917749a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345948189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2345948189
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1646506795
Short name T390
Test name
Test status
Simulation time 247119681 ps
CPU time 0.95 seconds
Started Apr 18 01:34:14 PM PDT 24
Finished Apr 18 01:34:16 PM PDT 24
Peak memory 200564 kb
Host smart-3dbbad38-f574-4f5a-a0da-ef785ca78c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646506795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1646506795
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2627699825
Short name T233
Test name
Test status
Simulation time 1251549502 ps
CPU time 5.28 seconds
Started Apr 18 01:34:12 PM PDT 24
Finished Apr 18 01:34:18 PM PDT 24
Peak memory 200952 kb
Host smart-ec71efa9-9069-4e24-9f4b-949c40342ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627699825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2627699825
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3100473665
Short name T155
Test name
Test status
Simulation time 153706199 ps
CPU time 1.18 seconds
Started Apr 18 01:34:21 PM PDT 24
Finished Apr 18 01:34:23 PM PDT 24
Peak memory 200824 kb
Host smart-4792832a-58c7-44b2-b464-115d53d5bdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100473665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3100473665
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1702148208
Short name T140
Test name
Test status
Simulation time 193280460 ps
CPU time 1.35 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200948 kb
Host smart-d8b41282-d16f-4ad6-a2ce-600b0ebfc271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702148208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1702148208
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.269213749
Short name T334
Test name
Test status
Simulation time 12097576386 ps
CPU time 38.66 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:35:04 PM PDT 24
Peak memory 210016 kb
Host smart-e2c0a781-53c9-49cf-a099-e9fb9af1a7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269213749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.269213749
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.635769829
Short name T262
Test name
Test status
Simulation time 365404655 ps
CPU time 2 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200776 kb
Host smart-cf088030-381f-418f-9399-35e7a29c51fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635769829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.635769829
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3902757799
Short name T276
Test name
Test status
Simulation time 60688486 ps
CPU time 0.72 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200596 kb
Host smart-23cdb906-6ccc-48c6-86ed-753e7be2b7a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902757799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3902757799
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1683269282
Short name T26
Test name
Test status
Simulation time 2350083084 ps
CPU time 7.72 seconds
Started Apr 18 01:34:38 PM PDT 24
Finished Apr 18 01:34:46 PM PDT 24
Peak memory 217812 kb
Host smart-69f02f0f-10fb-4592-86e5-287fd18efe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683269282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1683269282
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.105666067
Short name T174
Test name
Test status
Simulation time 244408425 ps
CPU time 1.12 seconds
Started Apr 18 01:34:19 PM PDT 24
Finished Apr 18 01:34:20 PM PDT 24
Peak memory 218040 kb
Host smart-b5201c2b-32c4-4fd0-8b67-437850f641da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105666067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.105666067
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3903161673
Short name T328
Test name
Test status
Simulation time 83689353 ps
CPU time 0.74 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 199880 kb
Host smart-d0260cd6-a391-4820-8ebb-ebdb03fa370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903161673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3903161673
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1273651280
Short name T295
Test name
Test status
Simulation time 1410784688 ps
CPU time 5.1 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:40 PM PDT 24
Peak memory 200984 kb
Host smart-7c349c51-c5ed-465a-ae40-525973860131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273651280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1273651280
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.760943593
Short name T236
Test name
Test status
Simulation time 141288420 ps
CPU time 1.02 seconds
Started Apr 18 01:34:33 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200072 kb
Host smart-4e394cea-3500-4388-b695-0b4656cbcbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760943593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.760943593
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.4181525135
Short name T408
Test name
Test status
Simulation time 115070105 ps
CPU time 1.32 seconds
Started Apr 18 01:34:13 PM PDT 24
Finished Apr 18 01:34:15 PM PDT 24
Peak memory 201008 kb
Host smart-cb214d78-40ec-4f36-9081-ff1ce0638aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181525135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.4181525135
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3013354967
Short name T68
Test name
Test status
Simulation time 2704128407 ps
CPU time 9.9 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 201084 kb
Host smart-05f87a53-bbc8-49b9-bbb9-9d5c42d25d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013354967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3013354967
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1325109736
Short name T435
Test name
Test status
Simulation time 109362757 ps
CPU time 0.88 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200800 kb
Host smart-f6b21bd9-539e-495b-8529-e7b233da3934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325109736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1325109736
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.181635094
Short name T180
Test name
Test status
Simulation time 66533723 ps
CPU time 0.73 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:23 PM PDT 24
Peak memory 200624 kb
Host smart-f1166a15-a56c-41ab-8dff-0bd080adad82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181635094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.181635094
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2884284001
Short name T32
Test name
Test status
Simulation time 1231243243 ps
CPU time 5.6 seconds
Started Apr 18 01:34:18 PM PDT 24
Finished Apr 18 01:34:24 PM PDT 24
Peak memory 218584 kb
Host smart-87544176-7a06-4148-ad1f-2602c1486a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884284001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2884284001
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4145929452
Short name T294
Test name
Test status
Simulation time 244190712 ps
CPU time 1.09 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 218164 kb
Host smart-d3c0ff08-622f-4fd9-88c2-d671f0efc726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145929452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4145929452
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1888403525
Short name T211
Test name
Test status
Simulation time 139908025 ps
CPU time 0.89 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200608 kb
Host smart-f35f0133-cd84-4602-b7c2-70424103074a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888403525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1888403525
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.4137283478
Short name T248
Test name
Test status
Simulation time 999533319 ps
CPU time 5.43 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 200968 kb
Host smart-5c93aec8-65c6-4c62-961d-b02c4e3463d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137283478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.4137283478
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2177386647
Short name T303
Test name
Test status
Simulation time 102771784 ps
CPU time 1.02 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 200836 kb
Host smart-963909b5-7602-4e03-81e8-3fde6b7c875c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177386647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2177386647
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3738694820
Short name T34
Test name
Test status
Simulation time 114906077 ps
CPU time 1.14 seconds
Started Apr 18 01:34:16 PM PDT 24
Finished Apr 18 01:34:18 PM PDT 24
Peak memory 200988 kb
Host smart-c3209a28-dfa6-4193-9c8e-bc6fa2b15481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738694820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3738694820
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.4120693070
Short name T302
Test name
Test status
Simulation time 3105356512 ps
CPU time 14.52 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 209244 kb
Host smart-6e2bc373-7737-40cb-809f-b7765685e460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120693070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.4120693070
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2338239244
Short name T235
Test name
Test status
Simulation time 113029241 ps
CPU time 1.41 seconds
Started Apr 18 01:34:21 PM PDT 24
Finished Apr 18 01:34:23 PM PDT 24
Peak memory 200820 kb
Host smart-a2a012fa-66dd-41d4-a5fa-fcab78ad488d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338239244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2338239244
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2425589167
Short name T243
Test name
Test status
Simulation time 154652140 ps
CPU time 1.13 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200756 kb
Host smart-c3d136db-cf50-4c1a-b5ba-8265ed1d0026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425589167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2425589167
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.626681106
Short name T540
Test name
Test status
Simulation time 60275548 ps
CPU time 0.75 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200600 kb
Host smart-a9bd1edd-ca07-44f5-9887-4de5125663fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626681106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.626681106
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.4190940421
Short name T472
Test name
Test status
Simulation time 1897095247 ps
CPU time 7.06 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 218580 kb
Host smart-784abc4f-0128-40aa-9b7b-8a926a5b0510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190940421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.4190940421
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3660940735
Short name T360
Test name
Test status
Simulation time 244660721 ps
CPU time 1.1 seconds
Started Apr 18 01:34:18 PM PDT 24
Finished Apr 18 01:34:19 PM PDT 24
Peak memory 218132 kb
Host smart-482cc481-f222-4d94-892b-8eb3831201d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660940735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3660940735
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.281693086
Short name T316
Test name
Test status
Simulation time 116619412 ps
CPU time 0.8 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200588 kb
Host smart-20abc687-7fbd-4086-837e-45f718ef8a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281693086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.281693086
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1658394815
Short name T488
Test name
Test status
Simulation time 143195501 ps
CPU time 1.05 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200792 kb
Host smart-bc604b2e-ff05-4ae0-88bc-5132f92adaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658394815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1658394815
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2692865399
Short name T221
Test name
Test status
Simulation time 118696214 ps
CPU time 1.14 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 200892 kb
Host smart-502370f9-49fe-42c6-b13a-f13d00203491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692865399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2692865399
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2984831767
Short name T325
Test name
Test status
Simulation time 1442798558 ps
CPU time 7.54 seconds
Started Apr 18 01:34:35 PM PDT 24
Finished Apr 18 01:34:43 PM PDT 24
Peak memory 210316 kb
Host smart-bb8a927a-e0dc-42c0-8e72-0bdcf056e1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984831767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2984831767
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.697806509
Short name T159
Test name
Test status
Simulation time 382406719 ps
CPU time 1.98 seconds
Started Apr 18 01:34:21 PM PDT 24
Finished Apr 18 01:34:24 PM PDT 24
Peak memory 200820 kb
Host smart-756b232e-e7f5-4a1f-96bf-b95af4539b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697806509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.697806509
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1982752166
Short name T388
Test name
Test status
Simulation time 121981293 ps
CPU time 1 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 200884 kb
Host smart-8b53f7fd-4302-4bb3-854c-6210938f4263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982752166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1982752166
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2788701179
Short name T218
Test name
Test status
Simulation time 78315002 ps
CPU time 0.82 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200604 kb
Host smart-51dcc2d0-5436-4061-a882-93ce29b187f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788701179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2788701179
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2861761008
Short name T503
Test name
Test status
Simulation time 1895418847 ps
CPU time 6.67 seconds
Started Apr 18 01:34:21 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 217988 kb
Host smart-348eaf86-da5c-49de-bd0c-d81a7eeca8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861761008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2861761008
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2627525360
Short name T415
Test name
Test status
Simulation time 244277263 ps
CPU time 1.1 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 218248 kb
Host smart-b59c325a-0344-48ab-8ffd-879174af3b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627525360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2627525360
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1602418490
Short name T16
Test name
Test status
Simulation time 144155742 ps
CPU time 0.83 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200580 kb
Host smart-b11a9481-5bb2-4196-8020-8604fc5a9d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602418490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1602418490
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2579625951
Short name T249
Test name
Test status
Simulation time 1788421693 ps
CPU time 7.2 seconds
Started Apr 18 01:34:21 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200952 kb
Host smart-ea4f7496-020a-4bf0-ac2c-317e63f3b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579625951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2579625951
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2695526017
Short name T539
Test name
Test status
Simulation time 113814726 ps
CPU time 1.06 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:24 PM PDT 24
Peak memory 200832 kb
Host smart-caabfd1c-b9b8-4d09-a576-7ae4f9b0f44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695526017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2695526017
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.637672862
Short name T232
Test name
Test status
Simulation time 123529587 ps
CPU time 1.16 seconds
Started Apr 18 01:34:21 PM PDT 24
Finished Apr 18 01:34:23 PM PDT 24
Peak memory 200948 kb
Host smart-96432d20-1a5d-4bb1-a3a9-5ec485fa73e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637672862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.637672862
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2575081099
Short name T4
Test name
Test status
Simulation time 1682006907 ps
CPU time 6.07 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200944 kb
Host smart-574a43af-1e52-4579-89d8-533243df3325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575081099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2575081099
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2906587220
Short name T350
Test name
Test status
Simulation time 424918420 ps
CPU time 2.29 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 209092 kb
Host smart-fb67d48d-8d40-4198-b604-3afcac33e445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906587220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2906587220
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1901360304
Short name T169
Test name
Test status
Simulation time 95580406 ps
CPU time 0.87 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200720 kb
Host smart-44e2c585-52e9-478e-97d4-96a87f551942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901360304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1901360304
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.169034201
Short name T467
Test name
Test status
Simulation time 61865417 ps
CPU time 0.75 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200616 kb
Host smart-c3c1a65c-ae9a-47a9-a6a7-629acba7cc6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169034201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.169034201
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2765486282
Short name T395
Test name
Test status
Simulation time 1888005175 ps
CPU time 6.6 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:38 PM PDT 24
Peak memory 217968 kb
Host smart-c7acfbc1-bea7-49f0-b29c-70c7c4a83e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765486282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2765486282
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.530982178
Short name T126
Test name
Test status
Simulation time 247205720 ps
CPU time 1 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 218108 kb
Host smart-d701b207-bec1-4c7d-87ba-8800502af5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530982178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.530982178
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2926833677
Short name T365
Test name
Test status
Simulation time 143452491 ps
CPU time 0.83 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200688 kb
Host smart-81050c7e-73aa-4eb0-9f18-034dd338550f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926833677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2926833677
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1195446444
Short name T226
Test name
Test status
Simulation time 817504207 ps
CPU time 4.04 seconds
Started Apr 18 01:34:14 PM PDT 24
Finished Apr 18 01:34:19 PM PDT 24
Peak memory 200928 kb
Host smart-979b4330-ab5c-4b31-9952-6b72632b8de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195446444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1195446444
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4241303371
Short name T519
Test name
Test status
Simulation time 171737431 ps
CPU time 1.12 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200832 kb
Host smart-b379b516-c00b-41fe-9f77-e391c256ac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241303371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4241303371
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.294518972
Short name T238
Test name
Test status
Simulation time 126784990 ps
CPU time 1.2 seconds
Started Apr 18 01:34:12 PM PDT 24
Finished Apr 18 01:34:14 PM PDT 24
Peak memory 201208 kb
Host smart-d2b987c2-11b3-49e3-b931-226e5b80e5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294518972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.294518972
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2061521157
Short name T251
Test name
Test status
Simulation time 5376868033 ps
CPU time 18.32 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:48 PM PDT 24
Peak memory 201068 kb
Host smart-fddc71ba-f1fb-4c6e-8bec-0d36bb8ba752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061521157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2061521157
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.160802208
Short name T513
Test name
Test status
Simulation time 314875121 ps
CPU time 1.98 seconds
Started Apr 18 01:34:14 PM PDT 24
Finished Apr 18 01:34:17 PM PDT 24
Peak memory 200744 kb
Host smart-088f3b50-ca0a-4dfa-bc20-b895cf021005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160802208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.160802208
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2206377481
Short name T237
Test name
Test status
Simulation time 174749979 ps
CPU time 1.29 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200940 kb
Host smart-9f42a36d-f80c-439b-8943-89a2b5da5776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206377481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2206377481
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.155478669
Short name T333
Test name
Test status
Simulation time 68813974 ps
CPU time 0.76 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200564 kb
Host smart-6e7e054e-bfd8-4c2c-85ee-698925bff3f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155478669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.155478669
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4184276737
Short name T10
Test name
Test status
Simulation time 1882800062 ps
CPU time 7.22 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 218596 kb
Host smart-36b3a460-cfde-4920-b565-b64d779e2382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184276737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4184276737
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2953710344
Short name T133
Test name
Test status
Simulation time 244787979 ps
CPU time 1.08 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 218152 kb
Host smart-5d65c93a-b09d-46c3-9e2a-12377c0cb88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953710344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2953710344
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2298677625
Short name T317
Test name
Test status
Simulation time 77156294 ps
CPU time 0.82 seconds
Started Apr 18 01:34:14 PM PDT 24
Finished Apr 18 01:34:16 PM PDT 24
Peak memory 200564 kb
Host smart-cd579b30-3baf-432d-a31c-6f3a23593683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298677625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2298677625
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.936412168
Short name T382
Test name
Test status
Simulation time 1038917845 ps
CPU time 4.87 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200964 kb
Host smart-f2fd102a-986e-4631-a820-666c529d86f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936412168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.936412168
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.517086957
Short name T300
Test name
Test status
Simulation time 141321195 ps
CPU time 1.09 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 200820 kb
Host smart-b1962a1b-85ed-4cf4-af21-423c3ca5c3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517086957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.517086957
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2681504648
Short name T329
Test name
Test status
Simulation time 239993739 ps
CPU time 1.5 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 201008 kb
Host smart-0752757d-a8dc-4b3e-96c8-85613804dd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681504648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2681504648
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3387461557
Short name T298
Test name
Test status
Simulation time 6415701155 ps
CPU time 22.35 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:54 PM PDT 24
Peak memory 208588 kb
Host smart-24696567-10fd-4cbf-bd9d-bc5058bd3437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387461557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3387461557
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2880622928
Short name T138
Test name
Test status
Simulation time 114992529 ps
CPU time 1.51 seconds
Started Apr 18 01:34:14 PM PDT 24
Finished Apr 18 01:34:16 PM PDT 24
Peak memory 200820 kb
Host smart-6d8460b1-14f0-4605-9e00-fb73101f2ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880622928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2880622928
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3049323602
Short name T156
Test name
Test status
Simulation time 198818157 ps
CPU time 1.22 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 200832 kb
Host smart-5ae19856-90ce-421e-a033-5e6b3fec259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049323602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3049323602
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1774605941
Short name T370
Test name
Test status
Simulation time 82539370 ps
CPU time 0.78 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200684 kb
Host smart-bc027c7e-d776-4b2d-a05e-8d8b39a8aad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774605941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1774605941
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.283778588
Short name T471
Test name
Test status
Simulation time 1891719032 ps
CPU time 7.49 seconds
Started Apr 18 01:34:17 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 217640 kb
Host smart-4887f9b5-bfbf-48b8-b880-47d0d5d0ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283778588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.283778588
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.131021527
Short name T175
Test name
Test status
Simulation time 245073558 ps
CPU time 1.05 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 218164 kb
Host smart-d17effad-b3c1-4338-aa0d-2402bfd1c82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131021527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.131021527
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3111048268
Short name T239
Test name
Test status
Simulation time 160999910 ps
CPU time 0.8 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200404 kb
Host smart-42a2c4e8-5cdf-45b5-ab73-8d9acf136a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111048268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3111048268
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3964665499
Short name T400
Test name
Test status
Simulation time 995490347 ps
CPU time 4.54 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200956 kb
Host smart-cb496b2e-661d-4844-86ae-4d00fa149d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964665499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3964665499
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1706234351
Short name T448
Test name
Test status
Simulation time 141245299 ps
CPU time 1.15 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200856 kb
Host smart-3c907f48-c036-4367-b5e2-c9337f858281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706234351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1706234351
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3264084345
Short name T301
Test name
Test status
Simulation time 186536712 ps
CPU time 1.27 seconds
Started Apr 18 01:34:42 PM PDT 24
Finished Apr 18 01:34:44 PM PDT 24
Peak memory 200924 kb
Host smart-8f4de352-68df-48e2-8330-18aca3c597d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264084345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3264084345
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3174660504
Short name T369
Test name
Test status
Simulation time 3421436678 ps
CPU time 16.4 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:42 PM PDT 24
Peak memory 201032 kb
Host smart-5c714ec0-1d76-4187-a25b-91737593b6f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174660504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3174660504
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2719996157
Short name T367
Test name
Test status
Simulation time 390620979 ps
CPU time 2.21 seconds
Started Apr 18 01:34:20 PM PDT 24
Finished Apr 18 01:34:23 PM PDT 24
Peak memory 200764 kb
Host smart-774496aa-d10b-4145-9997-8651a6ebb1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719996157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2719996157
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2877441997
Short name T120
Test name
Test status
Simulation time 156025576 ps
CPU time 1 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200804 kb
Host smart-62604c23-1f66-49bd-9f98-6ab179c0564f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877441997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2877441997
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3097824519
Short name T384
Test name
Test status
Simulation time 82272574 ps
CPU time 0.83 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:24 PM PDT 24
Peak memory 200848 kb
Host smart-83894ff8-c49b-46d1-a554-3b53128e77e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097824519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3097824519
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2789043591
Short name T43
Test name
Test status
Simulation time 1898876760 ps
CPU time 6.96 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 218588 kb
Host smart-63adca1d-e156-42bf-9d37-379cf3c5dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789043591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2789043591
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1093670879
Short name T259
Test name
Test status
Simulation time 244648363 ps
CPU time 1.04 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 218248 kb
Host smart-1429b405-a8fc-4f33-a37e-8568c93f480d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093670879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1093670879
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1696823674
Short name T183
Test name
Test status
Simulation time 109816343 ps
CPU time 0.8 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 200640 kb
Host smart-1197fa72-9d85-4f3e-9e8a-fb2299d3bab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696823674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1696823674
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3599734475
Short name T98
Test name
Test status
Simulation time 1899800518 ps
CPU time 7.31 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 201028 kb
Host smart-1c2a9649-dd84-48ed-b1ea-fe677a7878ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599734475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3599734475
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3524101012
Short name T417
Test name
Test status
Simulation time 97571803 ps
CPU time 0.97 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:23 PM PDT 24
Peak memory 200780 kb
Host smart-bbaa6e93-35c5-4b2e-ac09-050dc7c80a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524101012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3524101012
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.790393408
Short name T176
Test name
Test status
Simulation time 118452116 ps
CPU time 1.22 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 201024 kb
Host smart-8a554625-0b65-4821-b636-438f777fde49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790393408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.790393408
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.331193625
Short name T383
Test name
Test status
Simulation time 4692520360 ps
CPU time 17.64 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:48 PM PDT 24
Peak memory 209256 kb
Host smart-4252cdea-d2d4-49eb-80a3-50698ab11ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331193625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.331193625
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.976747675
Short name T280
Test name
Test status
Simulation time 360126919 ps
CPU time 1.92 seconds
Started Apr 18 01:34:31 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200780 kb
Host smart-f4bbf6af-8aed-454b-b7e4-15a7af796944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976747675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.976747675
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2989993796
Short name T320
Test name
Test status
Simulation time 98651426 ps
CPU time 0.83 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200704 kb
Host smart-1742160a-9d02-4c1c-8d24-50c67f9e0414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989993796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2989993796
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.67889891
Short name T423
Test name
Test status
Simulation time 55997102 ps
CPU time 0.7 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:26 PM PDT 24
Peak memory 200584 kb
Host smart-0bd527ff-190f-40ae-9bf2-732e59d75f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67889891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.67889891
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2805747405
Short name T442
Test name
Test status
Simulation time 2339141139 ps
CPU time 7.56 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:40 PM PDT 24
Peak memory 218616 kb
Host smart-c3447b2b-20da-43ef-926b-5cf3ffad5f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805747405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2805747405
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.453970197
Short name T166
Test name
Test status
Simulation time 245616785 ps
CPU time 1.02 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 217932 kb
Host smart-3cc1c88c-7487-4591-8c7c-2a7fb40f310a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453970197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.453970197
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2087197
Short name T18
Test name
Test status
Simulation time 124578784 ps
CPU time 0.75 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200596 kb
Host smart-4603519f-1867-4618-9910-78d9651050fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2087197
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2364750026
Short name T205
Test name
Test status
Simulation time 972583691 ps
CPU time 4.61 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:38 PM PDT 24
Peak memory 201000 kb
Host smart-856ec92d-abdc-41a0-800a-64b5d2a18a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364750026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2364750026
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1324928254
Short name T413
Test name
Test status
Simulation time 184279843 ps
CPU time 1.12 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200576 kb
Host smart-7403bb5d-7c92-4629-8ba3-6cf6ebda3547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324928254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1324928254
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2916054802
Short name T74
Test name
Test status
Simulation time 187403806 ps
CPU time 1.36 seconds
Started Apr 18 01:34:31 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200996 kb
Host smart-a16ad49d-07d1-486b-8354-78d8148dea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916054802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2916054802
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2408292815
Short name T491
Test name
Test status
Simulation time 12516545345 ps
CPU time 45.65 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:35:18 PM PDT 24
Peak memory 200880 kb
Host smart-021f5009-cf6f-4636-ba2e-f2b30e1de80d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408292815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2408292815
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.796713533
Short name T283
Test name
Test status
Simulation time 128360238 ps
CPU time 1.57 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200796 kb
Host smart-3398b5af-138c-4394-9e7c-f1f6ecbdc7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796713533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.796713533
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1422258504
Short name T229
Test name
Test status
Simulation time 96952706 ps
CPU time 0.87 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200784 kb
Host smart-e34b19a3-8f1c-48ba-9ab0-11c539d392d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422258504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1422258504
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2392791858
Short name T222
Test name
Test status
Simulation time 71063047 ps
CPU time 0.76 seconds
Started Apr 18 01:34:31 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200620 kb
Host smart-c9dd4dbb-7b3e-4a64-bfa1-2d9379e3ca54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392791858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2392791858
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3860187553
Short name T464
Test name
Test status
Simulation time 2179096044 ps
CPU time 7.76 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:41 PM PDT 24
Peak memory 222616 kb
Host smart-9c38c14e-92b4-40fb-aa99-016a6b4cf050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860187553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3860187553
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.744413785
Short name T481
Test name
Test status
Simulation time 244662689 ps
CPU time 1.1 seconds
Started Apr 18 01:34:13 PM PDT 24
Finished Apr 18 01:34:15 PM PDT 24
Peak memory 218036 kb
Host smart-85650bec-f262-4485-92a3-e6c56499084e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744413785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.744413785
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1549700688
Short name T420
Test name
Test status
Simulation time 206541162 ps
CPU time 0.87 seconds
Started Apr 18 01:34:18 PM PDT 24
Finished Apr 18 01:34:19 PM PDT 24
Peak memory 200632 kb
Host smart-e47b5a44-553e-40e9-a7ef-1b3f7470ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549700688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1549700688
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2085731706
Short name T510
Test name
Test status
Simulation time 1102457883 ps
CPU time 4.86 seconds
Started Apr 18 01:34:33 PM PDT 24
Finished Apr 18 01:34:40 PM PDT 24
Peak memory 201024 kb
Host smart-2d54b753-07d7-4a88-aed9-15ba4229f1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085731706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2085731706
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.387066143
Short name T60
Test name
Test status
Simulation time 16532444997 ps
CPU time 29.07 seconds
Started Apr 18 01:34:09 PM PDT 24
Finished Apr 18 01:34:38 PM PDT 24
Peak memory 218684 kb
Host smart-ab437407-687a-40f7-9927-28b171507e42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387066143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.387066143
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2695634970
Short name T213
Test name
Test status
Simulation time 152357980 ps
CPU time 1.13 seconds
Started Apr 18 01:34:38 PM PDT 24
Finished Apr 18 01:34:40 PM PDT 24
Peak memory 200796 kb
Host smart-2edd44ee-7f97-49b4-be6a-bbe16a63542c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695634970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2695634970
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2120207898
Short name T522
Test name
Test status
Simulation time 111739405 ps
CPU time 1.19 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 200992 kb
Host smart-ffc388e3-0f76-45d8-8b38-4b8e7e1983df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120207898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2120207898
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1780676522
Short name T372
Test name
Test status
Simulation time 1714667003 ps
CPU time 6.78 seconds
Started Apr 18 01:34:04 PM PDT 24
Finished Apr 18 01:34:11 PM PDT 24
Peak memory 200952 kb
Host smart-42791d19-082c-418e-840d-7e4a60a81afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780676522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1780676522
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2148698161
Short name T148
Test name
Test status
Simulation time 373821898 ps
CPU time 2.24 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 200780 kb
Host smart-465d442c-7382-4175-93b5-e00bfabc4685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148698161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2148698161
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2442726929
Short name T439
Test name
Test status
Simulation time 135942996 ps
CPU time 1.11 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200812 kb
Host smart-6659fef6-7d99-4324-b01f-1407769a01d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442726929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2442726929
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3405672227
Short name T254
Test name
Test status
Simulation time 96789032 ps
CPU time 0.84 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200608 kb
Host smart-3f4c0d24-a583-4eff-a510-e57d12f007d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405672227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3405672227
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3261564167
Short name T434
Test name
Test status
Simulation time 1897874785 ps
CPU time 6.87 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 222384 kb
Host smart-1002a571-caae-4873-b010-3973531893c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261564167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3261564167
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3168237303
Short name T296
Test name
Test status
Simulation time 244161546 ps
CPU time 1.05 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 218024 kb
Host smart-8a6895cd-231b-44b3-a2ed-627724291607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168237303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3168237303
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1027129468
Short name T20
Test name
Test status
Simulation time 138161478 ps
CPU time 0.8 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 200580 kb
Host smart-32915240-ffc7-42ae-9591-a2c425bf0f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027129468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1027129468
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.264240851
Short name T377
Test name
Test status
Simulation time 1598539785 ps
CPU time 6.08 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200992 kb
Host smart-30e9adbd-45bf-4e50-a877-5b8aef69a0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264240851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.264240851
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.96056923
Short name T414
Test name
Test status
Simulation time 107281232 ps
CPU time 0.97 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200620 kb
Host smart-d5c29c55-f371-44f9-9a3b-4409ce03ee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96056923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.96056923
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3613172178
Short name T145
Test name
Test status
Simulation time 199041029 ps
CPU time 1.4 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 201044 kb
Host smart-3eaa7107-5ba9-46ad-b7d4-2bb0962a504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613172178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3613172178
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.4087797308
Short name T431
Test name
Test status
Simulation time 3282190309 ps
CPU time 11.56 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:43 PM PDT 24
Peak memory 209136 kb
Host smart-c3b68b8b-cc98-4e2f-a159-16651ec727dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087797308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4087797308
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3776992771
Short name T416
Test name
Test status
Simulation time 146040168 ps
CPU time 1.82 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:26 PM PDT 24
Peak memory 200840 kb
Host smart-2d2d5ba9-0b4c-4547-ae18-0f5d407f424d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776992771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3776992771
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1100542894
Short name T484
Test name
Test status
Simulation time 243495885 ps
CPU time 1.39 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200808 kb
Host smart-2c5be2b0-e842-4f18-b0c7-784a269da268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100542894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1100542894
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3981961632
Short name T357
Test name
Test status
Simulation time 83039547 ps
CPU time 0.82 seconds
Started Apr 18 01:34:31 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200692 kb
Host smart-9b294e29-a984-42ce-8604-39434e8edae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981961632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3981961632
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3988601426
Short name T45
Test name
Test status
Simulation time 1226280798 ps
CPU time 5.49 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 222596 kb
Host smart-b98f6018-1a6a-4a23-8042-b9b10dcde6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988601426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3988601426
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3043475745
Short name T375
Test name
Test status
Simulation time 244403561 ps
CPU time 1.14 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 218132 kb
Host smart-7c5c1835-8eb5-45ac-90ca-bb42bb6b4291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043475745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3043475745
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2971502357
Short name T364
Test name
Test status
Simulation time 114783337 ps
CPU time 0.78 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:24 PM PDT 24
Peak memory 200612 kb
Host smart-973636c2-6ea7-44b9-bb7d-6d5d4a7b5a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971502357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2971502357
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3876045548
Short name T292
Test name
Test status
Simulation time 1929880932 ps
CPU time 6.56 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200944 kb
Host smart-7a4ac47a-d31b-4816-9b53-a5d39ec1d242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876045548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3876045548
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3259251384
Short name T279
Test name
Test status
Simulation time 151828429 ps
CPU time 1.13 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200852 kb
Host smart-a5ae7dfa-8882-49dc-954d-b06fed00f6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259251384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3259251384
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2846149466
Short name T387
Test name
Test status
Simulation time 250414740 ps
CPU time 1.41 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:26 PM PDT 24
Peak memory 200984 kb
Host smart-626d6bfe-1950-4650-9eaf-12ad7dcce6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846149466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2846149466
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.4094900739
Short name T396
Test name
Test status
Simulation time 9663818553 ps
CPU time 33.44 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:35:01 PM PDT 24
Peak memory 201196 kb
Host smart-258c8bc6-3476-4664-800e-2ab32466fa33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094900739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4094900739
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3213867841
Short name T208
Test name
Test status
Simulation time 423954989 ps
CPU time 2.21 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 209056 kb
Host smart-a0f7ccb9-00c2-470c-b127-dc809c7ef896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213867841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3213867841
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3730911739
Short name T227
Test name
Test status
Simulation time 113492858 ps
CPU time 0.96 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200768 kb
Host smart-13c92be8-936d-4249-8cda-4e4f506cfa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730911739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3730911739
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2251590804
Short name T355
Test name
Test status
Simulation time 71534222 ps
CPU time 0.74 seconds
Started Apr 18 01:34:31 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200632 kb
Host smart-286a6697-8794-41d1-85b6-c507e4caa1b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251590804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2251590804
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.889648803
Short name T288
Test name
Test status
Simulation time 1890928375 ps
CPU time 6.85 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 217552 kb
Host smart-e6df3946-ee82-49c2-a816-9cfef5dcb4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889648803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.889648803
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.186156217
Short name T412
Test name
Test status
Simulation time 243540012 ps
CPU time 1.09 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 218184 kb
Host smart-c57cda67-7f2e-418b-a2c9-aec345d9fab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186156217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.186156217
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2291456378
Short name T234
Test name
Test status
Simulation time 226201636 ps
CPU time 0.89 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200688 kb
Host smart-ab8ca77c-31e3-4e09-af1b-fbc0a4826955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291456378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2291456378
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1801336417
Short name T324
Test name
Test status
Simulation time 1269046045 ps
CPU time 5.09 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:39 PM PDT 24
Peak memory 200884 kb
Host smart-8667ea81-2137-4708-98ca-c27c3eb595dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801336417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1801336417
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3466452207
Short name T524
Test name
Test status
Simulation time 102664054 ps
CPU time 1.02 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 200824 kb
Host smart-f0bc85fe-bfc1-4d62-8ce4-8b11db04e4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466452207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3466452207
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3806416603
Short name T228
Test name
Test status
Simulation time 196484877 ps
CPU time 1.31 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 201016 kb
Host smart-16c6cbd2-89e9-46c7-8900-b8d76cd883c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806416603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3806416603
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.4084958762
Short name T191
Test name
Test status
Simulation time 8923721730 ps
CPU time 31.87 seconds
Started Apr 18 01:34:33 PM PDT 24
Finished Apr 18 01:35:07 PM PDT 24
Peak memory 209920 kb
Host smart-b7c30211-c910-4261-a81c-f59fba461b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084958762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.4084958762
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.493885326
Short name T371
Test name
Test status
Simulation time 140288404 ps
CPU time 1.76 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200828 kb
Host smart-25133263-1210-4556-b3d4-b997317ec933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493885326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.493885326
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3738548113
Short name T498
Test name
Test status
Simulation time 90416226 ps
CPU time 0.85 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200820 kb
Host smart-ecbca1d2-efec-4485-9bce-d59ed288f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738548113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3738548113
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1712137627
Short name T56
Test name
Test status
Simulation time 54408343 ps
CPU time 0.68 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200568 kb
Host smart-c06b8b4b-73c8-4eeb-8ba1-8f5d47fe3b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712137627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1712137627
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2882764743
Short name T323
Test name
Test status
Simulation time 1889339743 ps
CPU time 6.75 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:38 PM PDT 24
Peak memory 218380 kb
Host smart-8f695981-0196-4f61-a318-dfea745b1e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882764743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2882764743
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.240037866
Short name T190
Test name
Test status
Simulation time 246192577 ps
CPU time 1.1 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 218136 kb
Host smart-81dd9930-2870-4179-a40a-770848e586df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240037866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.240037866
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1789054404
Short name T225
Test name
Test status
Simulation time 145956422 ps
CPU time 0.83 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 199880 kb
Host smart-700a8936-dd03-45a8-a099-7a4fc38f4253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789054404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1789054404
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3154262986
Short name T87
Test name
Test status
Simulation time 804985731 ps
CPU time 3.85 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200920 kb
Host smart-e5650def-0103-4b87-b0f3-cc4925c85a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154262986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3154262986
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1025380124
Short name T465
Test name
Test status
Simulation time 138698433 ps
CPU time 1.05 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200772 kb
Host smart-b0515c14-ee4c-4f6f-9e70-c478ec064f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025380124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1025380124
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2776321813
Short name T389
Test name
Test status
Simulation time 253742402 ps
CPU time 1.52 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200920 kb
Host smart-683b5cca-1808-4a98-abd5-5fba012e56bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776321813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2776321813
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1208416374
Short name T284
Test name
Test status
Simulation time 2358220097 ps
CPU time 9.1 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:41 PM PDT 24
Peak memory 201076 kb
Host smart-f64b5d6f-6d4d-402e-9109-ab7fa9d5dde4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208416374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1208416374
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.4214962170
Short name T271
Test name
Test status
Simulation time 411614264 ps
CPU time 2.15 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 208940 kb
Host smart-90391c69-0f55-45de-a1e6-667e33f63065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214962170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.4214962170
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.825630914
Short name T268
Test name
Test status
Simulation time 118373770 ps
CPU time 0.97 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200748 kb
Host smart-bf33153c-3136-4531-928b-7fcb176c0966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825630914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.825630914
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1558130655
Short name T206
Test name
Test status
Simulation time 109691481 ps
CPU time 0.83 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200592 kb
Host smart-15deee3c-89ca-4564-b072-dbbef9cc7d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558130655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1558130655
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3330640092
Short name T463
Test name
Test status
Simulation time 1227708944 ps
CPU time 5.43 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 222580 kb
Host smart-eff494dc-caf1-4f8d-ba99-ab334bd811a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330640092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3330640092
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3230375239
Short name T203
Test name
Test status
Simulation time 244732650 ps
CPU time 1.08 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 218100 kb
Host smart-21069d02-e167-429e-aafb-3d81d3aea5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230375239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3230375239
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3351764634
Short name T419
Test name
Test status
Simulation time 186207205 ps
CPU time 0.83 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200596 kb
Host smart-6b277a79-278f-4b9a-8c2b-8a29f0727c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351764634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3351764634
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2692805385
Short name T331
Test name
Test status
Simulation time 1551661083 ps
CPU time 5.35 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200964 kb
Host smart-82755ec1-545d-4b88-91c6-64be7b28be11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692805385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2692805385
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1508373222
Short name T161
Test name
Test status
Simulation time 175987784 ps
CPU time 1.13 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200788 kb
Host smart-3d5ae638-756f-4a6d-b48d-c1647c16e68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508373222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1508373222
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.131050255
Short name T385
Test name
Test status
Simulation time 190402205 ps
CPU time 1.37 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200976 kb
Host smart-04a9e490-b983-46d8-9a6c-92e8d3ed745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131050255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.131050255
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.466061187
Short name T534
Test name
Test status
Simulation time 286321177 ps
CPU time 1.96 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 209032 kb
Host smart-bb0c6dc8-a940-4920-a982-38c6016efcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466061187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.466061187
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2622685538
Short name T393
Test name
Test status
Simulation time 90788861 ps
CPU time 0.92 seconds
Started Apr 18 01:34:33 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200736 kb
Host smart-d8062bcb-353f-4609-a432-54f9f204d85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622685538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2622685538
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2437872075
Short name T146
Test name
Test status
Simulation time 76316074 ps
CPU time 0.78 seconds
Started Apr 18 01:34:59 PM PDT 24
Finished Apr 18 01:35:01 PM PDT 24
Peak memory 200592 kb
Host smart-7c3c6621-97d0-4fd1-bd73-c2a4471a8593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437872075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2437872075
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.378131713
Short name T31
Test name
Test status
Simulation time 2355543283 ps
CPU time 8.43 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:41 PM PDT 24
Peak memory 218676 kb
Host smart-edf34190-79cf-49f9-acb4-d78dce388f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378131713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.378131713
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3062824735
Short name T312
Test name
Test status
Simulation time 243953085 ps
CPU time 1.11 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 218372 kb
Host smart-3bded693-6667-4c0f-bcae-a4d2272b2da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062824735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3062824735
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.540367967
Short name T352
Test name
Test status
Simulation time 148999001 ps
CPU time 0.86 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200640 kb
Host smart-67da1068-0a9a-4b42-b635-b52e1afe0d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540367967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.540367967
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1286338885
Short name T338
Test name
Test status
Simulation time 1128196570 ps
CPU time 4.99 seconds
Started Apr 18 01:34:31 PM PDT 24
Finished Apr 18 01:34:39 PM PDT 24
Peak memory 201032 kb
Host smart-76f3d63f-ff91-42d1-8c17-bcdb8ad73f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286338885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1286338885
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.694521759
Short name T62
Test name
Test status
Simulation time 108245317 ps
CPU time 0.95 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200828 kb
Host smart-f28b03fa-26ed-4cc8-bb7d-fa170ecbb3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694521759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.694521759
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3401240646
Short name T517
Test name
Test status
Simulation time 206035553 ps
CPU time 1.41 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200980 kb
Host smart-b3c49fe0-e277-433b-a1c1-6d0326c0b8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401240646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3401240646
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2105531066
Short name T245
Test name
Test status
Simulation time 1826746398 ps
CPU time 6.84 seconds
Started Apr 18 01:35:01 PM PDT 24
Finished Apr 18 01:35:08 PM PDT 24
Peak memory 201016 kb
Host smart-a3d0d4da-e3ff-4973-b5d8-f2acfce5a094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105531066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2105531066
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2567564652
Short name T257
Test name
Test status
Simulation time 145950944 ps
CPU time 1.64 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200848 kb
Host smart-5870ec2d-5a99-44ce-9548-be44ef00b7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567564652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2567564652
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1051742535
Short name T23
Test name
Test status
Simulation time 255441108 ps
CPU time 1.37 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 200720 kb
Host smart-dac758a1-a394-4441-9425-4823cae5bcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051742535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1051742535
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2355864932
Short name T127
Test name
Test status
Simulation time 61785040 ps
CPU time 0.72 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200540 kb
Host smart-aac87177-47cc-4d47-810d-3ebf664e31e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355864932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2355864932
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1007961062
Short name T380
Test name
Test status
Simulation time 1225838077 ps
CPU time 5.64 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 218556 kb
Host smart-0e242cc5-4509-4889-8fee-b30342609ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007961062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1007961062
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2882486946
Short name T326
Test name
Test status
Simulation time 245121139 ps
CPU time 1.09 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 218080 kb
Host smart-b2021f81-6c59-4e96-978f-83f8c7b6b534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882486946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2882486946
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2377449740
Short name T480
Test name
Test status
Simulation time 204359926 ps
CPU time 0.85 seconds
Started Apr 18 01:34:32 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200616 kb
Host smart-1c814231-6ded-4fff-93ab-7beaa9deb369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377449740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2377449740
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3305765136
Short name T100
Test name
Test status
Simulation time 1663091570 ps
CPU time 6.09 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200900 kb
Host smart-c5ed64b8-2395-4a0b-9a89-a8eaaf303715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305765136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3305765136
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1431230511
Short name T219
Test name
Test status
Simulation time 147360425 ps
CPU time 1.1 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200824 kb
Host smart-02d3aa44-eede-4c1d-b0bd-91cd360b344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431230511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1431230511
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1708073441
Short name T135
Test name
Test status
Simulation time 111695271 ps
CPU time 1.18 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200992 kb
Host smart-821ee246-2964-42db-96be-2e08a4dde054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708073441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1708073441
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2560832014
Short name T315
Test name
Test status
Simulation time 8606982878 ps
CPU time 35.88 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:35:01 PM PDT 24
Peak memory 209120 kb
Host smart-d489aec2-3d1c-4fe3-8ebc-58d13040183a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560832014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2560832014
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2320606863
Short name T73
Test name
Test status
Simulation time 533156199 ps
CPU time 2.71 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200832 kb
Host smart-c65252dc-4e9c-43ab-a9bd-7f512d23af82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320606863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2320606863
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2737177882
Short name T407
Test name
Test status
Simulation time 118242080 ps
CPU time 0.92 seconds
Started Apr 18 01:34:31 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200740 kb
Host smart-a47f7526-531c-48ad-a268-d7265debcafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737177882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2737177882
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.453765861
Short name T136
Test name
Test status
Simulation time 58413823 ps
CPU time 0.74 seconds
Started Apr 18 01:34:34 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200628 kb
Host smart-2418457b-c2f7-425e-b8ba-c6cfbb37f4f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453765861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.453765861
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3294080351
Short name T453
Test name
Test status
Simulation time 1230627246 ps
CPU time 5.42 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 222680 kb
Host smart-885514b1-9095-4cb2-8091-1e5c07e4ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294080351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3294080351
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2368471376
Short name T96
Test name
Test status
Simulation time 243451766 ps
CPU time 1.04 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 218100 kb
Host smart-ad2b6b47-9ff9-4451-82d4-ac67b4f102d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368471376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2368471376
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1335812985
Short name T289
Test name
Test status
Simulation time 231158863 ps
CPU time 0.89 seconds
Started Apr 18 01:34:32 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200644 kb
Host smart-f24e1ee2-053e-4bf5-b3a4-76fa89f9719c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335812985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1335812985
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2418698630
Short name T230
Test name
Test status
Simulation time 1524957798 ps
CPU time 5.49 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 201000 kb
Host smart-553bf2a3-cb1a-4955-8874-4dde596e8350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418698630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2418698630
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2133998226
Short name T65
Test name
Test status
Simulation time 104740614 ps
CPU time 1.01 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200832 kb
Host smart-259d3c23-9fb6-4299-839e-646d01c87262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133998226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2133998226
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1545210398
Short name T153
Test name
Test status
Simulation time 259408162 ps
CPU time 1.58 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200980 kb
Host smart-e8d5e2c4-637c-407c-a0e1-d87a1c758a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545210398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1545210398
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1275046580
Short name T201
Test name
Test status
Simulation time 10456983234 ps
CPU time 36.24 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:35:05 PM PDT 24
Peak memory 210224 kb
Host smart-bc0ee86a-c98a-489c-9573-73cfa95bb10b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275046580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1275046580
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1478012492
Short name T70
Test name
Test status
Simulation time 544034722 ps
CPU time 3.11 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200796 kb
Host smart-7c3604dd-cbed-4537-a997-2da7ad977a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478012492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1478012492
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1736896480
Short name T406
Test name
Test status
Simulation time 104699802 ps
CPU time 0.94 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200800 kb
Host smart-919aa5c3-37e7-44ef-9288-e597c2d3c176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736896480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1736896480
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3378848585
Short name T147
Test name
Test status
Simulation time 67161503 ps
CPU time 0.78 seconds
Started Apr 18 01:34:32 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200604 kb
Host smart-c121b334-be20-4f39-a2e5-6f8ddd731952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378848585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3378848585
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3659840320
Short name T38
Test name
Test status
Simulation time 1226580836 ps
CPU time 5.65 seconds
Started Apr 18 01:34:34 PM PDT 24
Finished Apr 18 01:34:41 PM PDT 24
Peak memory 217536 kb
Host smart-3cdf7743-5df7-4712-98fb-7ff4ef6c6a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659840320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3659840320
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.4188709135
Short name T215
Test name
Test status
Simulation time 244041017 ps
CPU time 1.07 seconds
Started Apr 18 01:34:35 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 218032 kb
Host smart-584d3c4e-83ce-42ac-bd2c-b9024d9bd827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188709135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.4188709135
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.690850867
Short name T403
Test name
Test status
Simulation time 180042174 ps
CPU time 0.89 seconds
Started Apr 18 01:34:25 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 200580 kb
Host smart-5ce313f2-c0ee-4dda-8e9e-dc114784e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690850867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.690850867
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.510552727
Short name T489
Test name
Test status
Simulation time 1311671882 ps
CPU time 5.43 seconds
Started Apr 18 01:35:00 PM PDT 24
Finished Apr 18 01:35:07 PM PDT 24
Peak memory 201024 kb
Host smart-a7cade74-ae69-4c15-895b-9894d2314a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510552727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.510552727
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.4217049663
Short name T462
Test name
Test status
Simulation time 146033227 ps
CPU time 1.07 seconds
Started Apr 18 01:34:33 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200828 kb
Host smart-659aadf6-cdeb-4341-8cba-889e627892cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217049663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.4217049663
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.686973120
Short name T36
Test name
Test status
Simulation time 225161620 ps
CPU time 1.35 seconds
Started Apr 18 01:34:31 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200972 kb
Host smart-bf0b89ae-f8d8-4144-84fa-df2d298d144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686973120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.686973120
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1474099483
Short name T209
Test name
Test status
Simulation time 3219509511 ps
CPU time 13.78 seconds
Started Apr 18 01:34:36 PM PDT 24
Finished Apr 18 01:34:50 PM PDT 24
Peak memory 209288 kb
Host smart-ac7866a1-b895-4b85-8c30-c2fc9d5ca566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474099483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1474099483
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1757645255
Short name T47
Test name
Test status
Simulation time 387362150 ps
CPU time 2.46 seconds
Started Apr 18 01:34:32 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 200760 kb
Host smart-1559b887-2bf4-4065-a284-ff93827b50f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757645255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1757645255
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2982144213
Short name T523
Test name
Test status
Simulation time 109748828 ps
CPU time 1.01 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 200828 kb
Host smart-08c25872-9705-4ebb-b532-5ba6719c78e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982144213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2982144213
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1919208324
Short name T394
Test name
Test status
Simulation time 58525900 ps
CPU time 0.73 seconds
Started Apr 18 01:34:32 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200520 kb
Host smart-a73f302f-79dc-4d2d-b1e1-5b08850e0006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919208324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1919208324
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.4019889218
Short name T177
Test name
Test status
Simulation time 2352169963 ps
CPU time 7.82 seconds
Started Apr 18 01:34:33 PM PDT 24
Finished Apr 18 01:34:42 PM PDT 24
Peak memory 218672 kb
Host smart-1f19b326-c165-416e-96dd-5f1671ac388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019889218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.4019889218
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3577697755
Short name T12
Test name
Test status
Simulation time 246773847 ps
CPU time 1.11 seconds
Started Apr 18 01:34:36 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 218140 kb
Host smart-edb7a9c7-5db8-4f07-8375-a41816fa0b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577697755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3577697755
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2010402286
Short name T401
Test name
Test status
Simulation time 253823124 ps
CPU time 0.98 seconds
Started Apr 18 01:34:34 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200644 kb
Host smart-daa52364-5045-46f2-bc29-afa494f70fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010402286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2010402286
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3918430493
Short name T246
Test name
Test status
Simulation time 1112251405 ps
CPU time 4.7 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200996 kb
Host smart-87deabfc-5a3b-49d9-bfb4-59591097f801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918430493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3918430493
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3575918550
Short name T402
Test name
Test status
Simulation time 144567358 ps
CPU time 1.11 seconds
Started Apr 18 01:34:58 PM PDT 24
Finished Apr 18 01:35:00 PM PDT 24
Peak memory 200796 kb
Host smart-d4a66751-94e5-4c14-a8d5-fc8cc4ab8eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575918550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3575918550
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2451875490
Short name T476
Test name
Test status
Simulation time 195453300 ps
CPU time 1.33 seconds
Started Apr 18 01:34:48 PM PDT 24
Finished Apr 18 01:34:50 PM PDT 24
Peak memory 200984 kb
Host smart-98a81e65-f9a7-45b7-b4e9-cb201cbd96ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451875490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2451875490
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2482825533
Short name T362
Test name
Test status
Simulation time 4034978841 ps
CPU time 16.91 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:49 PM PDT 24
Peak memory 201072 kb
Host smart-33560f4c-8ae8-478f-a966-5e9a560fbd16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482825533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2482825533
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2078489978
Short name T266
Test name
Test status
Simulation time 356167787 ps
CPU time 2.03 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 209040 kb
Host smart-7acb96bb-29f3-4e6c-9ff0-e12e16b8a773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078489978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2078489978
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3003555864
Short name T290
Test name
Test status
Simulation time 147372094 ps
CPU time 1.12 seconds
Started Apr 18 01:34:34 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 200832 kb
Host smart-9aa081da-d533-4981-97b4-a30d1da6cfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003555864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3003555864
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1865346489
Short name T521
Test name
Test status
Simulation time 61038615 ps
CPU time 0.73 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:29 PM PDT 24
Peak memory 200624 kb
Host smart-919fa66d-0739-4300-bab3-a6f9ad1ca2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865346489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1865346489
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3105770586
Short name T30
Test name
Test status
Simulation time 1237874716 ps
CPU time 5.74 seconds
Started Apr 18 01:34:08 PM PDT 24
Finished Apr 18 01:34:15 PM PDT 24
Peak memory 222652 kb
Host smart-b778aa93-9fff-4a7d-b564-d73b165a8ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105770586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3105770586
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.748146795
Short name T502
Test name
Test status
Simulation time 244289580 ps
CPU time 1.13 seconds
Started Apr 18 01:34:08 PM PDT 24
Finished Apr 18 01:34:10 PM PDT 24
Peak memory 218096 kb
Host smart-03bf2949-6b56-4f28-97ea-66236e11666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748146795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.748146795
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.220663217
Short name T497
Test name
Test status
Simulation time 224731299 ps
CPU time 0.99 seconds
Started Apr 18 01:34:04 PM PDT 24
Finished Apr 18 01:34:05 PM PDT 24
Peak memory 200636 kb
Host smart-a64cc1ee-d28d-4a7e-b8b6-f0c73649eb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220663217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.220663217
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3591717289
Short name T443
Test name
Test status
Simulation time 1504662890 ps
CPU time 5.77 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 201044 kb
Host smart-05e6454d-dda4-4614-819f-d2da05282cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591717289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3591717289
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1172175171
Short name T55
Test name
Test status
Simulation time 16706373044 ps
CPU time 24.22 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:50 PM PDT 24
Peak memory 218716 kb
Host smart-03360e69-8e73-44e6-88c7-e32e83b949e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172175171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1172175171
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3688928838
Short name T526
Test name
Test status
Simulation time 107320995 ps
CPU time 1.02 seconds
Started Apr 18 01:34:19 PM PDT 24
Finished Apr 18 01:34:21 PM PDT 24
Peak memory 200760 kb
Host smart-d472defb-3dad-4dbd-8769-bc4e85258eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688928838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3688928838
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2075940011
Short name T530
Test name
Test status
Simulation time 254159001 ps
CPU time 1.59 seconds
Started Apr 18 01:34:07 PM PDT 24
Finished Apr 18 01:34:09 PM PDT 24
Peak memory 200992 kb
Host smart-2ec928a5-35ac-47b2-a3f6-493553a020dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075940011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2075940011
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3087753800
Short name T223
Test name
Test status
Simulation time 9911113407 ps
CPU time 34.32 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:35:00 PM PDT 24
Peak memory 201072 kb
Host smart-5fdb050f-14c9-41ec-8214-b7dcaf1abbe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087753800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3087753800
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2543124265
Short name T282
Test name
Test status
Simulation time 134955764 ps
CPU time 1.82 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:25 PM PDT 24
Peak memory 200836 kb
Host smart-85b5514d-324d-4d12-9901-621e7be53942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543124265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2543124265
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.411095304
Short name T212
Test name
Test status
Simulation time 242818466 ps
CPU time 1.42 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200212 kb
Host smart-6ed294c1-3759-43ac-b7fa-9c5a100eef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411095304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.411095304
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.496836227
Short name T144
Test name
Test status
Simulation time 73207807 ps
CPU time 0.76 seconds
Started Apr 18 01:34:58 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 200600 kb
Host smart-14a80622-b2a9-46f4-9d79-b8ee60128414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496836227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.496836227
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1022882054
Short name T314
Test name
Test status
Simulation time 1884133452 ps
CPU time 7.25 seconds
Started Apr 18 01:34:56 PM PDT 24
Finished Apr 18 01:35:04 PM PDT 24
Peak memory 218048 kb
Host smart-284d30ca-bb79-4a85-bda2-617e73500aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022882054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1022882054
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3235591654
Short name T438
Test name
Test status
Simulation time 244282107 ps
CPU time 1.05 seconds
Started Apr 18 01:34:34 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 218100 kb
Host smart-7c4ccd1f-f2e4-4014-bcd3-5e0db6a89c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235591654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3235591654
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1898738839
Short name T293
Test name
Test status
Simulation time 90581909 ps
CPU time 0.71 seconds
Started Apr 18 01:34:29 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200596 kb
Host smart-4c18d5ba-692a-4d93-8f2a-ad083d46789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898738839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1898738839
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2511166341
Short name T231
Test name
Test status
Simulation time 965712782 ps
CPU time 5.32 seconds
Started Apr 18 01:34:36 PM PDT 24
Finished Apr 18 01:34:42 PM PDT 24
Peak memory 201220 kb
Host smart-d331f228-1c6f-43d9-a21b-554353f5f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511166341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2511166341
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1045332281
Short name T2
Test name
Test status
Simulation time 142237904 ps
CPU time 1.05 seconds
Started Apr 18 01:34:33 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 200776 kb
Host smart-f1a5d8cb-bed8-4d0a-8a7b-d238a8604c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045332281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1045332281
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3336087598
Short name T441
Test name
Test status
Simulation time 262207754 ps
CPU time 1.52 seconds
Started Apr 18 01:34:56 PM PDT 24
Finished Apr 18 01:34:58 PM PDT 24
Peak memory 200988 kb
Host smart-7ae0a572-858f-4fa0-a84a-657b3b95cec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336087598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3336087598
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.326633785
Short name T76
Test name
Test status
Simulation time 114981066 ps
CPU time 1.39 seconds
Started Apr 18 01:34:36 PM PDT 24
Finished Apr 18 01:34:38 PM PDT 24
Peak memory 200796 kb
Host smart-3ad327ba-4fd7-43a7-b296-e25547db948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326633785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.326633785
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3794097969
Short name T3
Test name
Test status
Simulation time 150980699 ps
CPU time 1.23 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 200788 kb
Host smart-0517f20b-9c37-43ac-b399-1845a38c266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794097969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3794097969
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.4280435429
Short name T137
Test name
Test status
Simulation time 74579881 ps
CPU time 0.87 seconds
Started Apr 18 01:34:43 PM PDT 24
Finished Apr 18 01:34:44 PM PDT 24
Peak memory 200600 kb
Host smart-4d4d1474-3ff8-4362-8d28-b58cc66660dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280435429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.4280435429
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1507508117
Short name T450
Test name
Test status
Simulation time 1240124031 ps
CPU time 5.6 seconds
Started Apr 18 01:34:55 PM PDT 24
Finished Apr 18 01:35:01 PM PDT 24
Peak memory 218604 kb
Host smart-ccc9abb2-5638-4b7c-a359-e61d50f8c661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507508117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1507508117
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3838413172
Short name T366
Test name
Test status
Simulation time 244583148 ps
CPU time 1.07 seconds
Started Apr 18 01:34:42 PM PDT 24
Finished Apr 18 01:34:44 PM PDT 24
Peak memory 218192 kb
Host smart-2fd0cf67-88bc-4d0a-87d0-02157eba911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838413172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3838413172
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.224864029
Short name T13
Test name
Test status
Simulation time 152362138 ps
CPU time 0.78 seconds
Started Apr 18 01:34:59 PM PDT 24
Finished Apr 18 01:35:00 PM PDT 24
Peak memory 200632 kb
Host smart-8fb9cde7-9010-4f81-ac91-413a64682b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224864029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.224864029
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1358479227
Short name T291
Test name
Test status
Simulation time 1009877123 ps
CPU time 5.03 seconds
Started Apr 18 01:34:34 PM PDT 24
Finished Apr 18 01:34:41 PM PDT 24
Peak memory 200956 kb
Host smart-e0a4ed9a-4106-4427-8dc6-167efefe787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358479227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1358479227
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.4208515497
Short name T8
Test name
Test status
Simulation time 148161230 ps
CPU time 1.13 seconds
Started Apr 18 01:34:43 PM PDT 24
Finished Apr 18 01:34:44 PM PDT 24
Peak memory 200808 kb
Host smart-440e1703-16ea-4557-8ca2-3b0e45d9b35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208515497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.4208515497
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3185563274
Short name T381
Test name
Test status
Simulation time 126122533 ps
CPU time 1.18 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 201012 kb
Host smart-b1ee70b2-f392-4e8d-9dc2-f299255b4e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185563274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3185563274
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3604522634
Short name T446
Test name
Test status
Simulation time 2073879596 ps
CPU time 10.01 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:35:07 PM PDT 24
Peak memory 209244 kb
Host smart-9984014c-82ae-4e08-b1ec-fbc5c770ccc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604522634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3604522634
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2818488861
Short name T473
Test name
Test status
Simulation time 268537401 ps
CPU time 1.89 seconds
Started Apr 18 01:34:42 PM PDT 24
Finished Apr 18 01:34:44 PM PDT 24
Peak memory 200748 kb
Host smart-d3f70389-eda4-44b8-8d49-8e051d5df4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818488861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2818488861
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1846158854
Short name T376
Test name
Test status
Simulation time 140833305 ps
CPU time 1.03 seconds
Started Apr 18 01:34:41 PM PDT 24
Finished Apr 18 01:34:42 PM PDT 24
Peak memory 200828 kb
Host smart-c7a41898-c041-4a02-97a2-bdf898f0afd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846158854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1846158854
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2526286576
Short name T216
Test name
Test status
Simulation time 69622033 ps
CPU time 0.76 seconds
Started Apr 18 01:34:45 PM PDT 24
Finished Apr 18 01:34:46 PM PDT 24
Peak memory 200580 kb
Host smart-57223af4-0553-4431-876a-809675369bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526286576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2526286576
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.909661983
Short name T319
Test name
Test status
Simulation time 2344339754 ps
CPU time 7.84 seconds
Started Apr 18 01:34:38 PM PDT 24
Finished Apr 18 01:34:46 PM PDT 24
Peak memory 218624 kb
Host smart-b5506ee0-78ef-43d0-8078-692f3ce48e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909661983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.909661983
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.798764888
Short name T308
Test name
Test status
Simulation time 243076035 ps
CPU time 1.05 seconds
Started Apr 18 01:34:38 PM PDT 24
Finished Apr 18 01:34:40 PM PDT 24
Peak memory 218184 kb
Host smart-0f500b71-171b-424c-a5e2-9773b988dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798764888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.798764888
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.440284510
Short name T260
Test name
Test status
Simulation time 220370086 ps
CPU time 0.97 seconds
Started Apr 18 01:34:39 PM PDT 24
Finished Apr 18 01:34:40 PM PDT 24
Peak memory 200592 kb
Host smart-e0757fa1-27c3-4132-8586-d6aa8334c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440284510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.440284510
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3057174605
Short name T399
Test name
Test status
Simulation time 884362073 ps
CPU time 4.35 seconds
Started Apr 18 01:35:07 PM PDT 24
Finished Apr 18 01:35:11 PM PDT 24
Peak memory 200996 kb
Host smart-e94e5dab-e1a4-41bd-b512-b558235bf74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057174605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3057174605
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2426089994
Short name T261
Test name
Test status
Simulation time 96774531 ps
CPU time 0.93 seconds
Started Apr 18 01:34:59 PM PDT 24
Finished Apr 18 01:35:00 PM PDT 24
Peak memory 200836 kb
Host smart-1fa53366-0359-44d2-b3ce-88550d0fff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426089994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2426089994
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.4131070436
Short name T474
Test name
Test status
Simulation time 112655286 ps
CPU time 1.27 seconds
Started Apr 18 01:34:42 PM PDT 24
Finished Apr 18 01:34:44 PM PDT 24
Peak memory 201000 kb
Host smart-4f20f62f-bc89-4ade-a2da-5e5dfe2274aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131070436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.4131070436
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3713872739
Short name T89
Test name
Test status
Simulation time 3435139697 ps
CPU time 15.8 seconds
Started Apr 18 01:35:04 PM PDT 24
Finished Apr 18 01:35:20 PM PDT 24
Peak memory 209312 kb
Host smart-1de44d4d-90c7-4919-bad8-a5b48b777eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713872739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3713872739
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4012992602
Short name T511
Test name
Test status
Simulation time 479247461 ps
CPU time 2.37 seconds
Started Apr 18 01:34:56 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 208956 kb
Host smart-0c23208c-d650-4e85-9b55-72615eb95447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012992602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4012992602
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.82298762
Short name T335
Test name
Test status
Simulation time 104829388 ps
CPU time 0.92 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:03 PM PDT 24
Peak memory 200764 kb
Host smart-72c663b0-c296-4ed8-b9ce-912410cd9f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82298762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.82298762
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1120901738
Short name T286
Test name
Test status
Simulation time 75782359 ps
CPU time 0.84 seconds
Started Apr 18 01:35:00 PM PDT 24
Finished Apr 18 01:35:02 PM PDT 24
Peak memory 200624 kb
Host smart-6037e6e5-b600-4b63-9650-6d16f31335bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120901738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1120901738
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2402181892
Short name T29
Test name
Test status
Simulation time 2348091082 ps
CPU time 8 seconds
Started Apr 18 01:35:08 PM PDT 24
Finished Apr 18 01:35:17 PM PDT 24
Peak memory 218380 kb
Host smart-43499c12-a7ba-495c-97db-c73ec33a9de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402181892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2402181892
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.305815539
Short name T253
Test name
Test status
Simulation time 244738487 ps
CPU time 1.01 seconds
Started Apr 18 01:34:58 PM PDT 24
Finished Apr 18 01:35:00 PM PDT 24
Peak memory 218068 kb
Host smart-58524c71-20a5-4e35-bd2d-d2358ec9d7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305815539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.305815539
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1059192986
Short name T478
Test name
Test status
Simulation time 95148733 ps
CPU time 0.77 seconds
Started Apr 18 01:35:05 PM PDT 24
Finished Apr 18 01:35:06 PM PDT 24
Peak memory 200656 kb
Host smart-29f7fddb-76f9-4f42-92f0-5854ff7e99c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059192986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1059192986
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3939434071
Short name T492
Test name
Test status
Simulation time 1572706670 ps
CPU time 6.16 seconds
Started Apr 18 01:35:11 PM PDT 24
Finished Apr 18 01:35:17 PM PDT 24
Peak memory 200964 kb
Host smart-d3fcf7e2-ec65-471a-b773-d856be4a6975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939434071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3939434071
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1938877225
Short name T164
Test name
Test status
Simulation time 143619014 ps
CPU time 1.14 seconds
Started Apr 18 01:34:44 PM PDT 24
Finished Apr 18 01:34:46 PM PDT 24
Peak memory 200840 kb
Host smart-a820457a-1725-4f17-8924-fcfc71bfa4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938877225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1938877225
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3203808229
Short name T458
Test name
Test status
Simulation time 201449575 ps
CPU time 1.35 seconds
Started Apr 18 01:34:42 PM PDT 24
Finished Apr 18 01:34:44 PM PDT 24
Peak memory 200940 kb
Host smart-dfbb4b41-5d0a-44a3-b538-b4023f76f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203808229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3203808229
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2691072793
Short name T332
Test name
Test status
Simulation time 417737578 ps
CPU time 1.87 seconds
Started Apr 18 01:34:44 PM PDT 24
Finished Apr 18 01:34:46 PM PDT 24
Peak memory 200984 kb
Host smart-3fa0b294-e135-46ca-9060-7905f5d8a51b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691072793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2691072793
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3813672308
Short name T204
Test name
Test status
Simulation time 542036555 ps
CPU time 2.7 seconds
Started Apr 18 01:35:08 PM PDT 24
Finished Apr 18 01:35:11 PM PDT 24
Peak memory 200808 kb
Host smart-708a89b1-b2c3-4de0-b8a6-4566d1ca2d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813672308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3813672308
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.370140475
Short name T141
Test name
Test status
Simulation time 264073750 ps
CPU time 1.52 seconds
Started Apr 18 01:35:01 PM PDT 24
Finished Apr 18 01:35:03 PM PDT 24
Peak memory 200776 kb
Host smart-9abbd0a6-e581-480a-bb73-f7ab3d62e472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370140475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.370140475
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2156034887
Short name T477
Test name
Test status
Simulation time 63443190 ps
CPU time 0.75 seconds
Started Apr 18 01:34:52 PM PDT 24
Finished Apr 18 01:34:54 PM PDT 24
Peak memory 200576 kb
Host smart-74ea7942-cb4e-4d44-9c60-a3d864df79d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156034887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2156034887
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3793825839
Short name T182
Test name
Test status
Simulation time 244118976 ps
CPU time 1.07 seconds
Started Apr 18 01:34:52 PM PDT 24
Finished Apr 18 01:34:54 PM PDT 24
Peak memory 218140 kb
Host smart-da370351-663a-4d4f-abd6-c625ae005e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793825839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3793825839
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3297999039
Short name T198
Test name
Test status
Simulation time 90359658 ps
CPU time 0.76 seconds
Started Apr 18 01:34:52 PM PDT 24
Finished Apr 18 01:34:53 PM PDT 24
Peak memory 200560 kb
Host smart-fd1aee8e-9603-47e0-8561-2121b4540169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297999039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3297999039
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3181562762
Short name T119
Test name
Test status
Simulation time 1732210902 ps
CPU time 6.28 seconds
Started Apr 18 01:35:00 PM PDT 24
Finished Apr 18 01:35:07 PM PDT 24
Peak memory 200896 kb
Host smart-e2146e3f-edd8-478c-9736-0e9a7dbe0e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181562762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3181562762
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1327194591
Short name T449
Test name
Test status
Simulation time 144905175 ps
CPU time 1.22 seconds
Started Apr 18 01:34:45 PM PDT 24
Finished Apr 18 01:34:47 PM PDT 24
Peak memory 200816 kb
Host smart-8de21bea-72d3-49fe-a990-abeddfd58a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327194591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1327194591
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.594904483
Short name T214
Test name
Test status
Simulation time 204817929 ps
CPU time 1.36 seconds
Started Apr 18 01:34:59 PM PDT 24
Finished Apr 18 01:35:01 PM PDT 24
Peak memory 200996 kb
Host smart-44c4606a-53d3-4867-9afa-44281771134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594904483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.594904483
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1995532785
Short name T252
Test name
Test status
Simulation time 7074580655 ps
CPU time 32.38 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:35 PM PDT 24
Peak memory 201120 kb
Host smart-1b2deb4f-866d-40be-89f1-b314fd47da24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995532785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1995532785
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1011728697
Short name T349
Test name
Test status
Simulation time 328286345 ps
CPU time 2.45 seconds
Started Apr 18 01:34:43 PM PDT 24
Finished Apr 18 01:34:46 PM PDT 24
Peak memory 200760 kb
Host smart-ebc3ef70-518c-4659-bbbf-8172d9ed79b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011728697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1011728697
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3764724467
Short name T162
Test name
Test status
Simulation time 98110343 ps
CPU time 0.9 seconds
Started Apr 18 01:34:46 PM PDT 24
Finished Apr 18 01:34:47 PM PDT 24
Peak memory 200804 kb
Host smart-4715149d-dc81-441c-8e57-4b25e31dbb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764724467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3764724467
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3974300777
Short name T451
Test name
Test status
Simulation time 67744546 ps
CPU time 0.76 seconds
Started Apr 18 01:34:52 PM PDT 24
Finished Apr 18 01:34:54 PM PDT 24
Peak memory 200584 kb
Host smart-3bc32c89-087d-4ecf-b15d-c6048aa56510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974300777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3974300777
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.229028764
Short name T359
Test name
Test status
Simulation time 1877007109 ps
CPU time 6.84 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:09 PM PDT 24
Peak memory 222648 kb
Host smart-736db218-25d3-4acf-acf8-fb6b8ebd3dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229028764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.229028764
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1871264578
Short name T242
Test name
Test status
Simulation time 243609255 ps
CPU time 1.03 seconds
Started Apr 18 01:35:00 PM PDT 24
Finished Apr 18 01:35:02 PM PDT 24
Peak memory 218112 kb
Host smart-b902c786-ddee-4d9d-923e-6d17f10f438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871264578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1871264578
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2868085310
Short name T361
Test name
Test status
Simulation time 160326484 ps
CPU time 0.84 seconds
Started Apr 18 01:34:53 PM PDT 24
Finished Apr 18 01:34:54 PM PDT 24
Peak memory 200600 kb
Host smart-828a34ba-28dc-46c7-9209-e9b935c60bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868085310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2868085310
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3874246343
Short name T340
Test name
Test status
Simulation time 1063659559 ps
CPU time 4.98 seconds
Started Apr 18 01:34:48 PM PDT 24
Finished Apr 18 01:34:54 PM PDT 24
Peak memory 201008 kb
Host smart-c361c49c-786c-4980-b56e-658cef09086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874246343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3874246343
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3865797293
Short name T258
Test name
Test status
Simulation time 166705468 ps
CPU time 1.13 seconds
Started Apr 18 01:34:50 PM PDT 24
Finished Apr 18 01:34:52 PM PDT 24
Peak memory 200836 kb
Host smart-2287a88f-8b90-4c37-9fae-e5459600bf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865797293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3865797293
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1361620883
Short name T264
Test name
Test status
Simulation time 110863703 ps
CPU time 1.22 seconds
Started Apr 18 01:34:48 PM PDT 24
Finished Apr 18 01:34:50 PM PDT 24
Peak memory 201032 kb
Host smart-38308554-6a3e-4d1a-abd9-ac9806938adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361620883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1361620883
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.283594789
Short name T244
Test name
Test status
Simulation time 7037050729 ps
CPU time 24.97 seconds
Started Apr 18 01:34:52 PM PDT 24
Finished Apr 18 01:35:18 PM PDT 24
Peak memory 201044 kb
Host smart-18b6ae72-390f-44d8-9a31-5e3ee30d5798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283594789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.283594789
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3221751508
Short name T272
Test name
Test status
Simulation time 128647771 ps
CPU time 1.62 seconds
Started Apr 18 01:35:17 PM PDT 24
Finished Apr 18 01:35:21 PM PDT 24
Peak memory 200784 kb
Host smart-740d5944-e78e-4704-bd39-a3720efb065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221751508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3221751508
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3345281449
Short name T343
Test name
Test status
Simulation time 114403969 ps
CPU time 0.95 seconds
Started Apr 18 01:35:09 PM PDT 24
Finished Apr 18 01:35:11 PM PDT 24
Peak memory 200816 kb
Host smart-7afeaba5-f54a-463a-8bbc-94cc3c4f8b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345281449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3345281449
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1371593541
Short name T427
Test name
Test status
Simulation time 73037905 ps
CPU time 0.74 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:24 PM PDT 24
Peak memory 200628 kb
Host smart-858cfffe-aacf-4d3a-bb3d-2990375b3bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371593541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1371593541
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1832316600
Short name T64
Test name
Test status
Simulation time 244525856 ps
CPU time 1.04 seconds
Started Apr 18 01:34:53 PM PDT 24
Finished Apr 18 01:34:55 PM PDT 24
Peak memory 218112 kb
Host smart-3db84f0c-b5be-452e-ac3c-09b22f142c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832316600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1832316600
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2538133198
Short name T19
Test name
Test status
Simulation time 121864224 ps
CPU time 0.76 seconds
Started Apr 18 01:35:11 PM PDT 24
Finished Apr 18 01:35:12 PM PDT 24
Peak memory 200620 kb
Host smart-152f7864-7c26-47b5-8547-19ad01930e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538133198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2538133198
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1887177904
Short name T172
Test name
Test status
Simulation time 1248042425 ps
CPU time 4.94 seconds
Started Apr 18 01:35:05 PM PDT 24
Finished Apr 18 01:35:10 PM PDT 24
Peak memory 201000 kb
Host smart-f4151816-79fc-4e55-af71-0a37deaac7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887177904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1887177904
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2595849655
Short name T173
Test name
Test status
Simulation time 145773956 ps
CPU time 1.04 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:18 PM PDT 24
Peak memory 200836 kb
Host smart-25f211d1-74c7-48c0-944b-cf87a36c159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595849655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2595849655
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1672367143
Short name T433
Test name
Test status
Simulation time 14846032454 ps
CPU time 49.67 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:36:06 PM PDT 24
Peak memory 200964 kb
Host smart-2b0a2e72-baca-488e-8cf9-f2fecc7bb55a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672367143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1672367143
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1714987760
Short name T379
Test name
Test status
Simulation time 126649265 ps
CPU time 1.58 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 209056 kb
Host smart-f98549e1-bdc1-4793-869d-aa1c0ed456af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714987760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1714987760
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3861889461
Short name T516
Test name
Test status
Simulation time 135616482 ps
CPU time 1.06 seconds
Started Apr 18 01:35:09 PM PDT 24
Finished Apr 18 01:35:10 PM PDT 24
Peak memory 200812 kb
Host smart-85a87c53-9878-423c-b63f-55129644acef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861889461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3861889461
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.963878902
Short name T509
Test name
Test status
Simulation time 68403786 ps
CPU time 0.74 seconds
Started Apr 18 01:35:04 PM PDT 24
Finished Apr 18 01:35:05 PM PDT 24
Peak memory 200576 kb
Host smart-5c4eb9e9-23b7-446b-80b9-39d498e75a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963878902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.963878902
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3081524410
Short name T500
Test name
Test status
Simulation time 1217712533 ps
CPU time 5.61 seconds
Started Apr 18 01:34:54 PM PDT 24
Finished Apr 18 01:35:01 PM PDT 24
Peak memory 218624 kb
Host smart-abb60cf5-16d6-44dd-bfe9-ade7791350e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081524410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3081524410
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4172496813
Short name T131
Test name
Test status
Simulation time 243773335 ps
CPU time 1.11 seconds
Started Apr 18 01:35:17 PM PDT 24
Finished Apr 18 01:35:20 PM PDT 24
Peak memory 218120 kb
Host smart-1327599f-dd38-45e0-b963-4b22d063bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172496813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4172496813
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.865059476
Short name T21
Test name
Test status
Simulation time 163027243 ps
CPU time 0.9 seconds
Started Apr 18 01:34:50 PM PDT 24
Finished Apr 18 01:34:52 PM PDT 24
Peak memory 200592 kb
Host smart-00db37db-e885-49ca-abb5-78f66c8113f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865059476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.865059476
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1351464053
Short name T188
Test name
Test status
Simulation time 1463992862 ps
CPU time 5.96 seconds
Started Apr 18 01:35:08 PM PDT 24
Finished Apr 18 01:35:15 PM PDT 24
Peak memory 200976 kb
Host smart-d72eabca-4f7b-4ff0-808e-341ded1ddace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351464053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1351464053
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3620792146
Short name T537
Test name
Test status
Simulation time 172703337 ps
CPU time 1.13 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 200828 kb
Host smart-9178ac2b-6888-4bbc-84a9-44b59cce8139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620792146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3620792146
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3600084001
Short name T150
Test name
Test status
Simulation time 112787629 ps
CPU time 1.18 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:04 PM PDT 24
Peak memory 200996 kb
Host smart-0b0ac22e-2b02-476f-b7a9-a12a59e1e607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600084001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3600084001
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.540368832
Short name T485
Test name
Test status
Simulation time 4098722871 ps
CPU time 17.16 seconds
Started Apr 18 01:35:20 PM PDT 24
Finished Apr 18 01:35:40 PM PDT 24
Peak memory 201060 kb
Host smart-5c7fccea-493f-4633-99e6-2cf1a2efc628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540368832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.540368832
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2256645446
Short name T263
Test name
Test status
Simulation time 124330995 ps
CPU time 1.55 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 209040 kb
Host smart-30270021-3f94-4dae-921c-39bb0cb7db53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256645446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2256645446
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2897896115
Short name T95
Test name
Test status
Simulation time 75534502 ps
CPU time 0.78 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 201032 kb
Host smart-119c9105-0de0-4c4d-9c06-613201b52430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897896115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2897896115
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3099634308
Short name T220
Test name
Test status
Simulation time 63442534 ps
CPU time 0.75 seconds
Started Apr 18 01:35:23 PM PDT 24
Finished Apr 18 01:35:26 PM PDT 24
Peak memory 200640 kb
Host smart-33b3c83c-654f-480b-ae55-0ef6aa63b8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099634308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3099634308
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3244846740
Short name T273
Test name
Test status
Simulation time 2365375737 ps
CPU time 8.42 seconds
Started Apr 18 01:34:59 PM PDT 24
Finished Apr 18 01:35:08 PM PDT 24
Peak memory 230716 kb
Host smart-d3948d1e-afa3-4029-8b70-6210a469f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244846740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3244846740
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2115369489
Short name T410
Test name
Test status
Simulation time 244862324 ps
CPU time 1.07 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 218100 kb
Host smart-86814c18-66a7-41fe-9590-91312be40c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115369489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2115369489
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2164687725
Short name T5
Test name
Test status
Simulation time 206665145 ps
CPU time 0.85 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 200676 kb
Host smart-b0fb252f-9d9d-40a4-a84e-5573239ce35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164687725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2164687725
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2546386326
Short name T102
Test name
Test status
Simulation time 1342169841 ps
CPU time 5.46 seconds
Started Apr 18 01:35:00 PM PDT 24
Finished Apr 18 01:35:07 PM PDT 24
Peak memory 200952 kb
Host smart-c74f1af6-1f13-40a9-b7c7-1c470e55e01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546386326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2546386326
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1627117533
Short name T185
Test name
Test status
Simulation time 165409261 ps
CPU time 1.13 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:34:58 PM PDT 24
Peak memory 200832 kb
Host smart-282d52a4-6688-44df-a993-45ca71ccba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627117533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1627117533
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4024992415
Short name T348
Test name
Test status
Simulation time 124413690 ps
CPU time 1.21 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:15 PM PDT 24
Peak memory 201000 kb
Host smart-22d2286b-5ea1-43ba-af7f-481fda400970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024992415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4024992415
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.955541549
Short name T269
Test name
Test status
Simulation time 725409533 ps
CPU time 3.48 seconds
Started Apr 18 01:35:18 PM PDT 24
Finished Apr 18 01:35:24 PM PDT 24
Peak memory 201092 kb
Host smart-30799ccd-f20a-4c2c-816b-4880cd1400fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955541549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.955541549
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.480237187
Short name T186
Test name
Test status
Simulation time 478573092 ps
CPU time 2.43 seconds
Started Apr 18 01:34:58 PM PDT 24
Finished Apr 18 01:35:01 PM PDT 24
Peak memory 209032 kb
Host smart-2f5af626-22db-4762-8f55-2e7cd25233c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480237187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.480237187
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2044190333
Short name T322
Test name
Test status
Simulation time 157611319 ps
CPU time 1.13 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:03 PM PDT 24
Peak memory 200880 kb
Host smart-57bf9b7a-db69-42fb-b813-546995802a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044190333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2044190333
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.916763539
Short name T142
Test name
Test status
Simulation time 64319221 ps
CPU time 0.76 seconds
Started Apr 18 01:35:01 PM PDT 24
Finished Apr 18 01:35:03 PM PDT 24
Peak memory 200580 kb
Host smart-f2ab1b6a-104b-4abc-91cb-cdb3ccdc4c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916763539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.916763539
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2141336340
Short name T39
Test name
Test status
Simulation time 2362724009 ps
CPU time 9.63 seconds
Started Apr 18 01:34:58 PM PDT 24
Finished Apr 18 01:35:08 PM PDT 24
Peak memory 222216 kb
Host smart-3da10f14-420a-42d5-858e-5b07ad8be6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141336340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2141336340
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.871228404
Short name T341
Test name
Test status
Simulation time 244523734 ps
CPU time 1.01 seconds
Started Apr 18 01:34:56 PM PDT 24
Finished Apr 18 01:34:57 PM PDT 24
Peak memory 218140 kb
Host smart-77be0e5f-1563-45d1-90b3-0d2f8da90770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871228404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.871228404
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1661936537
Short name T529
Test name
Test status
Simulation time 117239593 ps
CPU time 0.81 seconds
Started Apr 18 01:34:56 PM PDT 24
Finished Apr 18 01:34:58 PM PDT 24
Peak memory 200620 kb
Host smart-ccb1ddd0-934e-48e3-aa4f-51f3695f7834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661936537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1661936537
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2633392163
Short name T305
Test name
Test status
Simulation time 1409535215 ps
CPU time 6.22 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:20 PM PDT 24
Peak memory 201040 kb
Host smart-aae2a80b-fd89-465b-8ea3-59fca3bb490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633392163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2633392163
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1025388008
Short name T165
Test name
Test status
Simulation time 152200969 ps
CPU time 1.2 seconds
Started Apr 18 01:35:03 PM PDT 24
Finished Apr 18 01:35:04 PM PDT 24
Peak memory 200880 kb
Host smart-f67ac1fe-7142-4be5-a16b-b5f4e9cdb287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025388008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1025388008
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2452214809
Short name T440
Test name
Test status
Simulation time 127648272 ps
CPU time 1.19 seconds
Started Apr 18 01:35:18 PM PDT 24
Finished Apr 18 01:35:22 PM PDT 24
Peak memory 200988 kb
Host smart-3eea9edb-d36b-4ca4-928d-0f321dc70edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452214809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2452214809
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1873263521
Short name T327
Test name
Test status
Simulation time 5254400335 ps
CPU time 25.19 seconds
Started Apr 18 01:34:58 PM PDT 24
Finished Apr 18 01:35:24 PM PDT 24
Peak memory 209136 kb
Host smart-a8c72047-16de-445d-8c3c-9a0d406e21ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873263521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1873263521
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1345482589
Short name T459
Test name
Test status
Simulation time 259733565 ps
CPU time 1.72 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:35:00 PM PDT 24
Peak memory 200832 kb
Host smart-94712031-45c4-4136-9c7e-0d8fefaebe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345482589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1345482589
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3263728623
Short name T210
Test name
Test status
Simulation time 112160546 ps
CPU time 0.95 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 200824 kb
Host smart-ce51af83-ca9e-49d6-aa9b-c6ee56139d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263728623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3263728623
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.336693585
Short name T149
Test name
Test status
Simulation time 95620285 ps
CPU time 0.86 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200568 kb
Host smart-542e23bf-bc53-475f-a27d-e14ab6a668ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336693585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.336693585
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.799841662
Short name T504
Test name
Test status
Simulation time 1233079249 ps
CPU time 5.95 seconds
Started Apr 18 01:34:06 PM PDT 24
Finished Apr 18 01:34:13 PM PDT 24
Peak memory 218580 kb
Host smart-e4a15e96-9717-4043-961e-ecba94fe9715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799841662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.799841662
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4248525691
Short name T486
Test name
Test status
Simulation time 243648618 ps
CPU time 1.1 seconds
Started Apr 18 01:34:16 PM PDT 24
Finished Apr 18 01:34:18 PM PDT 24
Peak memory 218112 kb
Host smart-d438ea21-878e-40b6-b4d8-97687bf2fc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248525691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4248525691
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.344889343
Short name T194
Test name
Test status
Simulation time 117581866 ps
CPU time 0.75 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200580 kb
Host smart-b2851ec9-93ff-4d81-a084-e2c10da0d8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344889343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.344889343
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3618005393
Short name T353
Test name
Test status
Simulation time 1115245133 ps
CPU time 5.18 seconds
Started Apr 18 01:34:11 PM PDT 24
Finished Apr 18 01:34:17 PM PDT 24
Peak memory 201008 kb
Host smart-7bfd2ccf-3b2d-4569-b676-b73444179902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618005393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3618005393
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.307897090
Short name T61
Test name
Test status
Simulation time 9294234176 ps
CPU time 13.65 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:39 PM PDT 24
Peak memory 217944 kb
Host smart-3cdfeb17-7eb8-41b2-9268-5621b268736b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307897090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.307897090
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.4263256583
Short name T6
Test name
Test status
Simulation time 154624164 ps
CPU time 1.09 seconds
Started Apr 18 01:34:03 PM PDT 24
Finished Apr 18 01:34:05 PM PDT 24
Peak memory 200820 kb
Host smart-069e934c-a83c-4eb3-8754-fb2494da5b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263256583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.4263256583
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2675359116
Short name T278
Test name
Test status
Simulation time 245528778 ps
CPU time 1.44 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 201028 kb
Host smart-8d1eb726-c867-4e8d-bd42-3b4a2294e653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675359116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2675359116
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.219897955
Short name T196
Test name
Test status
Simulation time 269490378 ps
CPU time 1.3 seconds
Started Apr 18 01:34:11 PM PDT 24
Finished Apr 18 01:34:13 PM PDT 24
Peak memory 200816 kb
Host smart-6eb5e781-cfed-4c2a-92f4-fe6206faa824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219897955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.219897955
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2334354811
Short name T445
Test name
Test status
Simulation time 121865917 ps
CPU time 1.51 seconds
Started Apr 18 01:34:14 PM PDT 24
Finished Apr 18 01:34:16 PM PDT 24
Peak memory 200808 kb
Host smart-e4d96198-897f-4792-9cbd-c3ce915ec2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334354811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2334354811
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1612242446
Short name T167
Test name
Test status
Simulation time 102279615 ps
CPU time 1.02 seconds
Started Apr 18 01:34:07 PM PDT 24
Finished Apr 18 01:34:09 PM PDT 24
Peak memory 200780 kb
Host smart-47a4f3d3-1413-4bc3-b358-d39f54a5ba28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612242446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1612242446
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2713869316
Short name T58
Test name
Test status
Simulation time 89233184 ps
CPU time 0.79 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 200624 kb
Host smart-6e462882-40d2-471d-a608-24376d3c9baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713869316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2713869316
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2757323216
Short name T11
Test name
Test status
Simulation time 1221910941 ps
CPU time 5.31 seconds
Started Apr 18 01:35:00 PM PDT 24
Finished Apr 18 01:35:06 PM PDT 24
Peak memory 218540 kb
Host smart-57ba212a-c032-492b-8088-e1b21c966473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757323216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2757323216
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3001186581
Short name T59
Test name
Test status
Simulation time 243956049 ps
CPU time 1.06 seconds
Started Apr 18 01:35:21 PM PDT 24
Finished Apr 18 01:35:25 PM PDT 24
Peak memory 218100 kb
Host smart-7f365f4d-3859-4dba-aa67-3b6d21d90da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001186581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3001186581
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4137767480
Short name T494
Test name
Test status
Simulation time 208371627 ps
CPU time 0.91 seconds
Started Apr 18 01:35:22 PM PDT 24
Finished Apr 18 01:35:26 PM PDT 24
Peak memory 200640 kb
Host smart-bec5c426-c6a4-4b9f-bf63-970c56b41186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137767480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4137767480
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.215748293
Short name T373
Test name
Test status
Simulation time 2031428378 ps
CPU time 7.35 seconds
Started Apr 18 01:34:56 PM PDT 24
Finished Apr 18 01:35:04 PM PDT 24
Peak memory 201004 kb
Host smart-f870969a-2b1d-4fd1-9cb7-f47a05229c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215748293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.215748293
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2130051077
Short name T430
Test name
Test status
Simulation time 147866046 ps
CPU time 1.14 seconds
Started Apr 18 01:34:57 PM PDT 24
Finished Apr 18 01:34:59 PM PDT 24
Peak memory 200760 kb
Host smart-7c010dc4-74a1-49e9-bc7d-45271d3aa4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130051077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2130051077
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3733295935
Short name T69
Test name
Test status
Simulation time 241114089 ps
CPU time 1.45 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:04 PM PDT 24
Peak memory 200984 kb
Host smart-7b3d1772-03c5-4b94-9f07-f72bceb82146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733295935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3733295935
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2299388271
Short name T428
Test name
Test status
Simulation time 167498948 ps
CPU time 1.01 seconds
Started Apr 18 01:35:01 PM PDT 24
Finished Apr 18 01:35:03 PM PDT 24
Peak memory 200604 kb
Host smart-0989b643-349a-4f44-8657-5142a6965f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299388271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2299388271
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.271491059
Short name T391
Test name
Test status
Simulation time 149120980 ps
CPU time 1.85 seconds
Started Apr 18 01:34:58 PM PDT 24
Finished Apr 18 01:35:01 PM PDT 24
Peak memory 200748 kb
Host smart-625b735c-3844-4045-9ff3-3e8bbc2c8b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271491059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.271491059
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.293348465
Short name T531
Test name
Test status
Simulation time 170657959 ps
CPU time 1.35 seconds
Started Apr 18 01:34:58 PM PDT 24
Finished Apr 18 01:35:00 PM PDT 24
Peak memory 200900 kb
Host smart-07d8e9b2-06b7-4ede-b77f-c78ccd0a37c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293348465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.293348465
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1611113992
Short name T339
Test name
Test status
Simulation time 81123943 ps
CPU time 0.85 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:15 PM PDT 24
Peak memory 200600 kb
Host smart-cd1939ce-da5f-4767-9114-9be394aabbcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611113992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1611113992
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.235327500
Short name T37
Test name
Test status
Simulation time 1221205333 ps
CPU time 5.46 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:08 PM PDT 24
Peak memory 217536 kb
Host smart-26ff3c03-cb86-45b6-8875-9c7c0f99cc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235327500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.235327500
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1459158625
Short name T342
Test name
Test status
Simulation time 244075813 ps
CPU time 1.07 seconds
Started Apr 18 01:35:20 PM PDT 24
Finished Apr 18 01:35:25 PM PDT 24
Peak memory 218204 kb
Host smart-f5f07248-b235-4e37-a8c6-a4d0a2418d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459158625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1459158625
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1499539685
Short name T512
Test name
Test status
Simulation time 88492039 ps
CPU time 0.77 seconds
Started Apr 18 01:35:10 PM PDT 24
Finished Apr 18 01:35:11 PM PDT 24
Peak memory 200612 kb
Host smart-299ff092-5a32-4061-9c20-c8f3570fbe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499539685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1499539685
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1373662855
Short name T195
Test name
Test status
Simulation time 909869198 ps
CPU time 4.86 seconds
Started Apr 18 01:35:14 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 201004 kb
Host smart-fdeb0baf-a3aa-4b7f-adfc-16892760f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373662855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1373662855
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2361328232
Short name T505
Test name
Test status
Simulation time 104076023 ps
CPU time 1.07 seconds
Started Apr 18 01:35:11 PM PDT 24
Finished Apr 18 01:35:13 PM PDT 24
Peak memory 201028 kb
Host smart-2410d226-7d02-44ec-a039-e68876f94c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361328232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2361328232
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3032836551
Short name T168
Test name
Test status
Simulation time 210489027 ps
CPU time 1.45 seconds
Started Apr 18 01:35:09 PM PDT 24
Finished Apr 18 01:35:10 PM PDT 24
Peak memory 200992 kb
Host smart-ba3c51cd-efa7-427a-ada1-660b65b5be56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032836551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3032836551
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.459309320
Short name T72
Test name
Test status
Simulation time 11040032175 ps
CPU time 35.74 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:38 PM PDT 24
Peak memory 209268 kb
Host smart-8b02e42e-9198-4eb8-a835-7c518d5ec5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459309320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.459309320
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1651792925
Short name T345
Test name
Test status
Simulation time 386824983 ps
CPU time 2.3 seconds
Started Apr 18 01:35:22 PM PDT 24
Finished Apr 18 01:35:27 PM PDT 24
Peak memory 200784 kb
Host smart-b57e7675-8bc7-402f-a7ae-e25ccd66f439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651792925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1651792925
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.493480830
Short name T128
Test name
Test status
Simulation time 113981517 ps
CPU time 1.05 seconds
Started Apr 18 01:35:21 PM PDT 24
Finished Apr 18 01:35:25 PM PDT 24
Peak memory 200788 kb
Host smart-df5d9bc1-4562-49df-a81b-d1b566d9cb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493480830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.493480830
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.4017764464
Short name T482
Test name
Test status
Simulation time 64189543 ps
CPU time 0.71 seconds
Started Apr 18 01:35:07 PM PDT 24
Finished Apr 18 01:35:08 PM PDT 24
Peak memory 200628 kb
Host smart-158aebec-8c63-432e-8e5e-fa70a4ace353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017764464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.4017764464
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2267471061
Short name T40
Test name
Test status
Simulation time 1219419697 ps
CPU time 5.48 seconds
Started Apr 18 01:35:20 PM PDT 24
Finished Apr 18 01:35:29 PM PDT 24
Peak memory 218052 kb
Host smart-6ff04bf4-5fa9-438d-b963-2cfe5f1f2f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267471061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2267471061
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.4107538179
Short name T256
Test name
Test status
Simulation time 244742638 ps
CPU time 1.07 seconds
Started Apr 18 01:35:15 PM PDT 24
Finished Apr 18 01:35:17 PM PDT 24
Peak memory 218240 kb
Host smart-07997865-f6df-4ad5-9a6b-e3af56301813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107538179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.4107538179
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2757543311
Short name T241
Test name
Test status
Simulation time 213068734 ps
CPU time 0.87 seconds
Started Apr 18 01:35:17 PM PDT 24
Finished Apr 18 01:35:20 PM PDT 24
Peak memory 200636 kb
Host smart-aedb4c0b-c0ac-413c-8964-f693f87f61ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757543311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2757543311
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.363412942
Short name T452
Test name
Test status
Simulation time 901612066 ps
CPU time 4.61 seconds
Started Apr 18 01:35:00 PM PDT 24
Finished Apr 18 01:35:05 PM PDT 24
Peak memory 200984 kb
Host smart-767e8b27-6764-4040-962e-a59adb0d5256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363412942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.363412942
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.855841052
Short name T468
Test name
Test status
Simulation time 111029065 ps
CPU time 1.11 seconds
Started Apr 18 01:35:03 PM PDT 24
Finished Apr 18 01:35:04 PM PDT 24
Peak memory 200780 kb
Host smart-ccec864b-a834-4a3d-bd04-7ee57d4bf8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855841052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.855841052
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.4139226953
Short name T404
Test name
Test status
Simulation time 246785046 ps
CPU time 1.42 seconds
Started Apr 18 01:35:18 PM PDT 24
Finished Apr 18 01:35:22 PM PDT 24
Peak memory 200984 kb
Host smart-49a0309e-8048-43be-8a53-ea4b1401abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139226953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4139226953
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1944285239
Short name T496
Test name
Test status
Simulation time 3730594681 ps
CPU time 14.57 seconds
Started Apr 18 01:35:12 PM PDT 24
Finished Apr 18 01:35:28 PM PDT 24
Peak memory 201056 kb
Host smart-227c8fce-66e2-4a5a-865f-00f651750027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944285239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1944285239
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.757556183
Short name T217
Test name
Test status
Simulation time 136606194 ps
CPU time 1.72 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:15 PM PDT 24
Peak memory 200820 kb
Host smart-902320bb-1658-4f62-ae71-8e02349ae871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757556183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.757556183
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4090278541
Short name T347
Test name
Test status
Simulation time 139110898 ps
CPU time 1.24 seconds
Started Apr 18 01:35:15 PM PDT 24
Finished Apr 18 01:35:17 PM PDT 24
Peak memory 200780 kb
Host smart-8dd18fe4-c578-4938-9004-c9fbb397c837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090278541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4090278541
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3785366107
Short name T247
Test name
Test status
Simulation time 76192123 ps
CPU time 0.77 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:14 PM PDT 24
Peak memory 200600 kb
Host smart-4699b040-99de-4e7d-bca6-682eea9e19e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785366107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3785366107
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3669254298
Short name T41
Test name
Test status
Simulation time 2372962093 ps
CPU time 8.62 seconds
Started Apr 18 01:35:22 PM PDT 24
Finished Apr 18 01:35:34 PM PDT 24
Peak memory 221944 kb
Host smart-d067f639-9e87-46d7-bd8c-041d4ec7af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669254298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3669254298
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4106797559
Short name T158
Test name
Test status
Simulation time 245449388 ps
CPU time 1.02 seconds
Started Apr 18 01:35:21 PM PDT 24
Finished Apr 18 01:35:25 PM PDT 24
Peak memory 218236 kb
Host smart-a15f5627-3da3-4033-8305-b76446927339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106797559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4106797559
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.4202339355
Short name T306
Test name
Test status
Simulation time 137070650 ps
CPU time 0.84 seconds
Started Apr 18 01:35:22 PM PDT 24
Finished Apr 18 01:35:26 PM PDT 24
Peak memory 200604 kb
Host smart-0e3ab004-de5d-4890-888f-9747a3010645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202339355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.4202339355
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1777691950
Short name T437
Test name
Test status
Simulation time 1093372905 ps
CPU time 4.93 seconds
Started Apr 18 01:34:59 PM PDT 24
Finished Apr 18 01:35:04 PM PDT 24
Peak memory 200948 kb
Host smart-3cc1b47b-5022-43f2-bcbd-7070b1e4dabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777691950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1777691950
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.205393346
Short name T337
Test name
Test status
Simulation time 179415543 ps
CPU time 1.28 seconds
Started Apr 18 01:35:01 PM PDT 24
Finished Apr 18 01:35:03 PM PDT 24
Peak memory 200844 kb
Host smart-8e88fed3-96cf-4869-ab06-62c43b633904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205393346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.205393346
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3586498167
Short name T139
Test name
Test status
Simulation time 207525633 ps
CPU time 1.37 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:15 PM PDT 24
Peak memory 200984 kb
Host smart-55992be5-e0b8-47fa-bde0-1c709b77860c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586498167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3586498167
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1421435438
Short name T199
Test name
Test status
Simulation time 7267215568 ps
CPU time 25.45 seconds
Started Apr 18 01:35:20 PM PDT 24
Finished Apr 18 01:35:48 PM PDT 24
Peak memory 209268 kb
Host smart-303027a7-a2d6-40d2-8a95-62694c321d44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421435438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1421435438
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2444716809
Short name T121
Test name
Test status
Simulation time 473193833 ps
CPU time 2.68 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:05 PM PDT 24
Peak memory 200828 kb
Host smart-fae6891c-6a18-43b3-84d3-429a89559555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444716809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2444716809
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3620941823
Short name T297
Test name
Test status
Simulation time 142285080 ps
CPU time 1.1 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 200796 kb
Host smart-9d5b9a05-eaea-49a3-b97a-b90352547ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620941823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3620941823
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2519482906
Short name T525
Test name
Test status
Simulation time 115699558 ps
CPU time 0.85 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:18 PM PDT 24
Peak memory 200608 kb
Host smart-8d2e88ef-e6a5-4262-9260-534613acaeb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519482906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2519482906
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.925211240
Short name T24
Test name
Test status
Simulation time 2365750185 ps
CPU time 8.16 seconds
Started Apr 18 01:35:10 PM PDT 24
Finished Apr 18 01:35:18 PM PDT 24
Peak memory 222688 kb
Host smart-b19c5803-d5e5-48ec-805e-a887d99da371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925211240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.925211240
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3915158656
Short name T160
Test name
Test status
Simulation time 245498446 ps
CPU time 1.03 seconds
Started Apr 18 01:35:20 PM PDT 24
Finished Apr 18 01:35:25 PM PDT 24
Peak memory 218100 kb
Host smart-beae7313-3b49-42cb-b762-a700c3e22acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915158656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3915158656
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1063436659
Short name T250
Test name
Test status
Simulation time 209400380 ps
CPU time 1.01 seconds
Started Apr 18 01:35:02 PM PDT 24
Finished Apr 18 01:35:04 PM PDT 24
Peak memory 200644 kb
Host smart-d7c84e44-ae4a-4713-b658-791d8a3fc921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063436659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1063436659
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.281324418
Short name T356
Test name
Test status
Simulation time 1015788612 ps
CPU time 4.83 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:27 PM PDT 24
Peak memory 201056 kb
Host smart-0b1dbb18-0fbf-45e4-ae0e-c0a6af85ba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281324418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.281324418
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.943236590
Short name T35
Test name
Test status
Simulation time 147565300 ps
CPU time 1.12 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:15 PM PDT 24
Peak memory 200812 kb
Host smart-1a097bf7-ab09-4635-99a7-a2c4004f9bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943236590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.943236590
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2895554181
Short name T207
Test name
Test status
Simulation time 123993100 ps
CPU time 1.16 seconds
Started Apr 18 01:35:14 PM PDT 24
Finished Apr 18 01:35:16 PM PDT 24
Peak memory 201004 kb
Host smart-af8d0d07-9517-462f-90fe-f3e7483741a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895554181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2895554181
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.4010754467
Short name T240
Test name
Test status
Simulation time 15410942956 ps
CPU time 52.53 seconds
Started Apr 18 01:35:12 PM PDT 24
Finished Apr 18 01:36:05 PM PDT 24
Peak memory 201028 kb
Host smart-3a6a1967-c0ee-4859-b621-bebc65adbd16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010754467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.4010754467
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4058919511
Short name T71
Test name
Test status
Simulation time 299486276 ps
CPU time 1.94 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:24 PM PDT 24
Peak memory 209028 kb
Host smart-80b8f348-acc5-49e2-8466-22181833ab14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058919511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4058919511
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2862440885
Short name T515
Test name
Test status
Simulation time 282232143 ps
CPU time 1.49 seconds
Started Apr 18 01:35:12 PM PDT 24
Finished Apr 18 01:35:14 PM PDT 24
Peak memory 200988 kb
Host smart-5952b94c-70f3-4803-8423-bd6491623cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862440885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2862440885
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.844565708
Short name T351
Test name
Test status
Simulation time 55779925 ps
CPU time 0.71 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:22 PM PDT 24
Peak memory 200620 kb
Host smart-b4aa15cb-0b42-46da-9fb2-ab59f6a62e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844565708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.844565708
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.307289992
Short name T46
Test name
Test status
Simulation time 1230168606 ps
CPU time 5.39 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:27 PM PDT 24
Peak memory 222636 kb
Host smart-38e0a739-180a-4587-8fc1-1e7cf26f5811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307289992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.307289992
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3681374764
Short name T378
Test name
Test status
Simulation time 244315391 ps
CPU time 1.13 seconds
Started Apr 18 01:35:12 PM PDT 24
Finished Apr 18 01:35:13 PM PDT 24
Peak memory 218240 kb
Host smart-a56fa338-322e-4b1a-8faa-81cf86a1a39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681374764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3681374764
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3042289197
Short name T287
Test name
Test status
Simulation time 202775269 ps
CPU time 0.95 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:23 PM PDT 24
Peak memory 200640 kb
Host smart-32ff98c7-e488-4d49-af22-a33d27c0ad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042289197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3042289197
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1042980366
Short name T535
Test name
Test status
Simulation time 995587656 ps
CPU time 4.93 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 201020 kb
Host smart-7f62b9f8-341b-4e9b-9a9e-2e8e02ea0da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042980366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1042980366
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2529741739
Short name T518
Test name
Test status
Simulation time 189990060 ps
CPU time 1.17 seconds
Started Apr 18 01:35:20 PM PDT 24
Finished Apr 18 01:35:24 PM PDT 24
Peak memory 200808 kb
Host smart-b853b94d-abf1-43c5-843c-3bde6f1a5c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529741739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2529741739
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2339123038
Short name T143
Test name
Test status
Simulation time 205457511 ps
CPU time 1.44 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:15 PM PDT 24
Peak memory 201212 kb
Host smart-c90d7a53-d711-4398-994f-ccb14a85ebcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339123038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2339123038
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3130510029
Short name T358
Test name
Test status
Simulation time 7110996209 ps
CPU time 31.81 seconds
Started Apr 18 01:35:08 PM PDT 24
Finished Apr 18 01:35:40 PM PDT 24
Peak memory 217376 kb
Host smart-4f9c1573-426b-4863-bfd1-8b83257421ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130510029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3130510029
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1632509911
Short name T197
Test name
Test status
Simulation time 144608732 ps
CPU time 1.74 seconds
Started Apr 18 01:35:17 PM PDT 24
Finished Apr 18 01:35:20 PM PDT 24
Peak memory 200840 kb
Host smart-24899afd-f736-4a2e-a714-2ac167df9115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632509911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1632509911
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.4107997621
Short name T469
Test name
Test status
Simulation time 222285631 ps
CPU time 1.49 seconds
Started Apr 18 01:35:01 PM PDT 24
Finished Apr 18 01:35:03 PM PDT 24
Peak memory 200828 kb
Host smart-002c650f-8e46-416f-8995-f05033ac5208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107997621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4107997621
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3157972814
Short name T179
Test name
Test status
Simulation time 86242445 ps
CPU time 0.87 seconds
Started Apr 18 01:35:13 PM PDT 24
Finished Apr 18 01:35:14 PM PDT 24
Peak memory 200844 kb
Host smart-dcecd607-fd43-4a14-8b21-b77c6c2c92c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157972814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3157972814
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3427220085
Short name T27
Test name
Test status
Simulation time 1898247047 ps
CPU time 7.64 seconds
Started Apr 18 01:35:21 PM PDT 24
Finished Apr 18 01:35:32 PM PDT 24
Peak memory 218564 kb
Host smart-d7900a06-83a4-4dd4-b028-15e088d1fe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427220085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3427220085
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.767347555
Short name T346
Test name
Test status
Simulation time 244360331 ps
CPU time 1 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:23 PM PDT 24
Peak memory 218292 kb
Host smart-a2e28b43-aaa3-4fb6-8894-b07b1aabdb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767347555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.767347555
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2875991399
Short name T363
Test name
Test status
Simulation time 253286427 ps
CPU time 0.91 seconds
Started Apr 18 01:35:20 PM PDT 24
Finished Apr 18 01:35:24 PM PDT 24
Peak memory 200656 kb
Host smart-b4d541b3-def4-48b0-a8a7-4b106386c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875991399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2875991399
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2436637179
Short name T487
Test name
Test status
Simulation time 2055840137 ps
CPU time 7.01 seconds
Started Apr 18 01:35:14 PM PDT 24
Finished Apr 18 01:35:22 PM PDT 24
Peak memory 201008 kb
Host smart-cad72c51-719e-4814-ac09-053d7dda46cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436637179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2436637179
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1824029823
Short name T178
Test name
Test status
Simulation time 173359747 ps
CPU time 1.15 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:23 PM PDT 24
Peak memory 200776 kb
Host smart-ed8626bc-38bb-4e19-afce-36f9a31e7013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824029823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1824029823
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4237418078
Short name T157
Test name
Test status
Simulation time 240083761 ps
CPU time 1.44 seconds
Started Apr 18 01:35:18 PM PDT 24
Finished Apr 18 01:35:22 PM PDT 24
Peak memory 200992 kb
Host smart-59bd7251-943d-4a2f-8b6e-62c85caaa207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237418078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4237418078
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2042546381
Short name T91
Test name
Test status
Simulation time 3577809108 ps
CPU time 15.86 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:33 PM PDT 24
Peak memory 201052 kb
Host smart-04872519-e960-4f56-9b2a-24692e2e9220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042546381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2042546381
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.4248738452
Short name T411
Test name
Test status
Simulation time 134200116 ps
CPU time 1.68 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:20 PM PDT 24
Peak memory 209004 kb
Host smart-9d02a59f-69c7-4978-8a5a-7c0bf3e551b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248738452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.4248738452
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3585353559
Short name T163
Test name
Test status
Simulation time 102355874 ps
CPU time 0.97 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 200832 kb
Host smart-4f3690ba-2621-4cfa-8d87-ca22f6592df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585353559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3585353559
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.4247117963
Short name T285
Test name
Test status
Simulation time 288455870 ps
CPU time 1.22 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:18 PM PDT 24
Peak memory 200564 kb
Host smart-f9e43ca3-2cb4-496b-b93c-793e6ae497a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247117963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.4247117963
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2219625793
Short name T125
Test name
Test status
Simulation time 244117791 ps
CPU time 1.13 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:23 PM PDT 24
Peak memory 218164 kb
Host smart-ad672cb0-f743-44ca-86ae-e098d6d81f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219625793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2219625793
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2007680415
Short name T368
Test name
Test status
Simulation time 227903562 ps
CPU time 0.9 seconds
Started Apr 18 01:35:17 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 200640 kb
Host smart-0706e445-6773-4a44-88c4-45037e66ea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007680415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2007680415
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.900353883
Short name T336
Test name
Test status
Simulation time 1594548752 ps
CPU time 6.54 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:24 PM PDT 24
Peak memory 201004 kb
Host smart-7f9e1f7c-d8df-4d31-9743-0b54c8c90cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900353883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.900353883
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.396847072
Short name T392
Test name
Test status
Simulation time 157822169 ps
CPU time 1.14 seconds
Started Apr 18 01:35:18 PM PDT 24
Finished Apr 18 01:35:22 PM PDT 24
Peak memory 200832 kb
Host smart-8d0b03c3-0597-4810-85d1-6b9caa21df02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396847072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.396847072
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1635396521
Short name T528
Test name
Test status
Simulation time 117940892 ps
CPU time 1.18 seconds
Started Apr 18 01:35:22 PM PDT 24
Finished Apr 18 01:35:26 PM PDT 24
Peak memory 200976 kb
Host smart-1cf3d309-41ef-4dc0-9018-f7668df99e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635396521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1635396521
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.726539419
Short name T99
Test name
Test status
Simulation time 7626719143 ps
CPU time 25.4 seconds
Started Apr 18 01:35:20 PM PDT 24
Finished Apr 18 01:35:49 PM PDT 24
Peak memory 209244 kb
Host smart-a5e68897-5e3f-4237-b93c-0bce38942f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726539419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.726539419
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3139977356
Short name T532
Test name
Test status
Simulation time 149041307 ps
CPU time 1.83 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:20 PM PDT 24
Peak memory 200748 kb
Host smart-184f5a63-ac93-4677-863d-4a58dcb94daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139977356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3139977356
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2734824127
Short name T409
Test name
Test status
Simulation time 149033824 ps
CPU time 1.26 seconds
Started Apr 18 01:35:15 PM PDT 24
Finished Apr 18 01:35:18 PM PDT 24
Peak memory 201044 kb
Host smart-2807adb3-f743-4700-930f-6bdd16e85e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734824127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2734824127
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2565237945
Short name T57
Test name
Test status
Simulation time 88814658 ps
CPU time 0.79 seconds
Started Apr 18 01:35:22 PM PDT 24
Finished Apr 18 01:35:25 PM PDT 24
Peak memory 200600 kb
Host smart-c1719309-4192-4e66-b2d2-aea20e1f616c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565237945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2565237945
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1728460109
Short name T447
Test name
Test status
Simulation time 1236578621 ps
CPU time 5.94 seconds
Started Apr 18 01:35:17 PM PDT 24
Finished Apr 18 01:35:25 PM PDT 24
Peak memory 217524 kb
Host smart-dee14c73-dde0-4b75-b4bb-c8b9ad349b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728460109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1728460109
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3448896312
Short name T154
Test name
Test status
Simulation time 244831573 ps
CPU time 1.17 seconds
Started Apr 18 01:35:17 PM PDT 24
Finished Apr 18 01:35:20 PM PDT 24
Peak memory 218040 kb
Host smart-579efab2-a04c-4535-a975-cecaf68e154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448896312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3448896312
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2305102076
Short name T466
Test name
Test status
Simulation time 199707005 ps
CPU time 0.87 seconds
Started Apr 18 01:35:15 PM PDT 24
Finished Apr 18 01:35:16 PM PDT 24
Peak memory 200556 kb
Host smart-3dcbc060-d3b7-4574-aa4e-cc7676886d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305102076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2305102076
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2755099315
Short name T304
Test name
Test status
Simulation time 720163292 ps
CPU time 3.67 seconds
Started Apr 18 01:35:21 PM PDT 24
Finished Apr 18 01:35:28 PM PDT 24
Peak memory 200984 kb
Host smart-90453505-b4c1-4578-8b05-35b2d51cbc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755099315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2755099315
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3748321457
Short name T310
Test name
Test status
Simulation time 109618238 ps
CPU time 1 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:23 PM PDT 24
Peak memory 200880 kb
Host smart-70582315-afec-491c-b36c-ee3c3b5e52a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748321457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3748321457
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.459619224
Short name T318
Test name
Test status
Simulation time 115030380 ps
CPU time 1.19 seconds
Started Apr 18 01:35:15 PM PDT 24
Finished Apr 18 01:35:17 PM PDT 24
Peak memory 201008 kb
Host smart-56d4c72f-955e-4850-b09c-a411c3dafabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459619224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.459619224
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1953162948
Short name T309
Test name
Test status
Simulation time 3302272526 ps
CPU time 11.67 seconds
Started Apr 18 01:35:19 PM PDT 24
Finished Apr 18 01:35:34 PM PDT 24
Peak memory 201088 kb
Host smart-0631e0ab-1a8d-445a-9091-532653fb2ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953162948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1953162948
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.239505071
Short name T425
Test name
Test status
Simulation time 432156465 ps
CPU time 2.25 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 208960 kb
Host smart-f37ba696-185c-4e95-b503-c3a96ad29245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239505071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.239505071
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3356736733
Short name T398
Test name
Test status
Simulation time 289362153 ps
CPU time 1.44 seconds
Started Apr 18 01:35:12 PM PDT 24
Finished Apr 18 01:35:14 PM PDT 24
Peak memory 201020 kb
Host smart-dce9b5a3-7d59-4d6a-94cd-be7fb93b4476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356736733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3356736733
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2577564843
Short name T374
Test name
Test status
Simulation time 76947019 ps
CPU time 0.79 seconds
Started Apr 18 01:35:14 PM PDT 24
Finished Apr 18 01:35:15 PM PDT 24
Peak memory 200628 kb
Host smart-fa708ea2-2da6-4a99-ac3b-d5513460ea86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577564843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2577564843
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3842572271
Short name T536
Test name
Test status
Simulation time 1891763569 ps
CPU time 7.01 seconds
Started Apr 18 01:35:15 PM PDT 24
Finished Apr 18 01:35:23 PM PDT 24
Peak memory 218632 kb
Host smart-5e0c57a3-db36-44b4-9df7-ddbfa392efb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842572271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3842572271
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3514671324
Short name T457
Test name
Test status
Simulation time 244451364 ps
CPU time 1 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:18 PM PDT 24
Peak memory 218156 kb
Host smart-4a545bca-c0e1-4969-a0d7-78d624d128d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514671324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3514671324
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2611164441
Short name T224
Test name
Test status
Simulation time 155444889 ps
CPU time 0.84 seconds
Started Apr 18 01:35:20 PM PDT 24
Finished Apr 18 01:35:24 PM PDT 24
Peak memory 200640 kb
Host smart-d97ec199-06d6-4313-8c48-0002596f0131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611164441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2611164441
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.606212154
Short name T421
Test name
Test status
Simulation time 1331494139 ps
CPU time 5.71 seconds
Started Apr 18 01:35:18 PM PDT 24
Finished Apr 18 01:35:26 PM PDT 24
Peak memory 200988 kb
Host smart-36ccf5b9-fcc4-4bfc-a63b-66a39f6ac0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606212154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.606212154
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2631004329
Short name T152
Test name
Test status
Simulation time 150333075 ps
CPU time 1.11 seconds
Started Apr 18 01:35:12 PM PDT 24
Finished Apr 18 01:35:13 PM PDT 24
Peak memory 200808 kb
Host smart-f3bd81f8-1a6b-4617-80af-de95a12164fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631004329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2631004329
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2861834196
Short name T313
Test name
Test status
Simulation time 198574879 ps
CPU time 1.39 seconds
Started Apr 18 01:35:12 PM PDT 24
Finished Apr 18 01:35:14 PM PDT 24
Peak memory 200956 kb
Host smart-f140c484-eb79-43b2-a722-071a758f5d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861834196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2861834196
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.698384626
Short name T418
Test name
Test status
Simulation time 12910011943 ps
CPU time 40.12 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:58 PM PDT 24
Peak memory 211396 kb
Host smart-1e2436aa-ea59-4fdb-940e-7b913e53fb2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698384626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.698384626
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1801426187
Short name T307
Test name
Test status
Simulation time 399071663 ps
CPU time 2.18 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:19 PM PDT 24
Peak memory 200828 kb
Host smart-3c82d82f-9f2e-460c-b0c5-54662fe3ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801426187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1801426187
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2739744263
Short name T270
Test name
Test status
Simulation time 65996861 ps
CPU time 0.81 seconds
Started Apr 18 01:35:16 PM PDT 24
Finished Apr 18 01:35:18 PM PDT 24
Peak memory 200720 kb
Host smart-b27e2c49-e60c-4620-bbe8-4708e7180916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739744263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2739744263
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2968915860
Short name T538
Test name
Test status
Simulation time 93737388 ps
CPU time 0.8 seconds
Started Apr 18 01:34:19 PM PDT 24
Finished Apr 18 01:34:21 PM PDT 24
Peak memory 200628 kb
Host smart-29d5951f-bb31-4f24-8673-fff8e7df0f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968915860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2968915860
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.635581773
Short name T311
Test name
Test status
Simulation time 2355712439 ps
CPU time 8.12 seconds
Started Apr 18 01:34:17 PM PDT 24
Finished Apr 18 01:34:26 PM PDT 24
Peak memory 218616 kb
Host smart-19e60d35-1ae4-4f2e-bf2a-fa5ab4dbc9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635581773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.635581773
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.539559042
Short name T424
Test name
Test status
Simulation time 244996295 ps
CPU time 1.1 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 218096 kb
Host smart-76abddc0-d2ad-430f-80da-b63e462792e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539559042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.539559042
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.436445264
Short name T495
Test name
Test status
Simulation time 209694045 ps
CPU time 0.92 seconds
Started Apr 18 01:34:18 PM PDT 24
Finished Apr 18 01:34:19 PM PDT 24
Peak memory 200564 kb
Host smart-2e08210f-d020-47a3-a2a2-f790f0e75520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436445264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.436445264
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4248911641
Short name T501
Test name
Test status
Simulation time 1449956424 ps
CPU time 5.81 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 201012 kb
Host smart-50588b4c-c069-44c4-ad35-eb0ea5445a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248911641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4248911641
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1975964113
Short name T202
Test name
Test status
Simulation time 182447237 ps
CPU time 1.23 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200840 kb
Host smart-57cac5ce-34a0-41ba-95df-572cd805bdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975964113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1975964113
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.4071429731
Short name T192
Test name
Test status
Simulation time 108191603 ps
CPU time 1.22 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:24 PM PDT 24
Peak memory 200988 kb
Host smart-72f40e3f-0766-42f7-ac5e-03f047f53933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071429731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.4071429731
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1164365436
Short name T422
Test name
Test status
Simulation time 14292557897 ps
CPU time 48.23 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:35:14 PM PDT 24
Peak memory 200948 kb
Host smart-fa6b44ba-046f-4941-ba5f-7c7f163064b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164365436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1164365436
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2110574014
Short name T475
Test name
Test status
Simulation time 117032718 ps
CPU time 1.63 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:26 PM PDT 24
Peak memory 200780 kb
Host smart-4370141c-172a-4f37-a354-66f6665cdf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110574014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2110574014
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.4214085288
Short name T66
Test name
Test status
Simulation time 117981188 ps
CPU time 1.01 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200776 kb
Host smart-2a8d743d-337d-44bc-b8fb-8586947cbad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214085288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4214085288
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1656070344
Short name T189
Test name
Test status
Simulation time 68904932 ps
CPU time 0.73 seconds
Started Apr 18 01:34:37 PM PDT 24
Finished Apr 18 01:34:38 PM PDT 24
Peak memory 200588 kb
Host smart-06efdd41-a17b-4a17-a220-762d8ed89c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656070344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1656070344
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.4251284764
Short name T429
Test name
Test status
Simulation time 1886958764 ps
CPU time 6.96 seconds
Started Apr 18 01:34:26 PM PDT 24
Finished Apr 18 01:34:36 PM PDT 24
Peak memory 218584 kb
Host smart-c6cc0570-b451-4ae0-9b7e-07c70064485c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251284764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.4251284764
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.657700311
Short name T170
Test name
Test status
Simulation time 244449285 ps
CPU time 1.13 seconds
Started Apr 18 01:34:20 PM PDT 24
Finished Apr 18 01:34:21 PM PDT 24
Peak memory 218212 kb
Host smart-da460bc5-05b1-4690-b5d6-4d6f711cb405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657700311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.657700311
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3529420472
Short name T15
Test name
Test status
Simulation time 210955271 ps
CPU time 0.87 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200652 kb
Host smart-75a43522-30f6-4fdf-bd2d-995333dec614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529420472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3529420472
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2611612020
Short name T88
Test name
Test status
Simulation time 1460624258 ps
CPU time 5.5 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 201020 kb
Host smart-15ee57c9-b069-4973-8fd7-c58665318b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611612020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2611612020
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2854985448
Short name T436
Test name
Test status
Simulation time 104486042 ps
CPU time 1.06 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:24 PM PDT 24
Peak memory 201028 kb
Host smart-3e012c83-23b1-458d-8676-da178f4ba9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854985448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2854985448
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3644436067
Short name T508
Test name
Test status
Simulation time 192440583 ps
CPU time 1.26 seconds
Started Apr 18 01:34:12 PM PDT 24
Finished Apr 18 01:34:15 PM PDT 24
Peak memory 201000 kb
Host smart-546e0700-c997-466d-832c-ab037940858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644436067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3644436067
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.4103948650
Short name T461
Test name
Test status
Simulation time 5212615124 ps
CPU time 17.31 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:51 PM PDT 24
Peak memory 209316 kb
Host smart-5e36e41d-4b9c-42e8-87be-838dd2e7add4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103948650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.4103948650
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.768907019
Short name T22
Test name
Test status
Simulation time 298149582 ps
CPU time 2.06 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:37 PM PDT 24
Peak memory 208984 kb
Host smart-8f958b00-d340-4e0b-b149-9da2d2760b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768907019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.768907019
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.93053719
Short name T456
Test name
Test status
Simulation time 109945567 ps
CPU time 0.9 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200816 kb
Host smart-9333b5d6-4563-4018-ae99-820a5f1a7080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93053719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.93053719
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2186182341
Short name T124
Test name
Test status
Simulation time 65822486 ps
CPU time 0.76 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200628 kb
Host smart-4ad4a9e9-779a-4346-ab7f-38171e92836b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186182341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2186182341
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3564844214
Short name T265
Test name
Test status
Simulation time 1885577740 ps
CPU time 7.61 seconds
Started Apr 18 01:34:12 PM PDT 24
Finished Apr 18 01:34:21 PM PDT 24
Peak memory 218568 kb
Host smart-eb78e235-9267-4705-8953-4a145085baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564844214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3564844214
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1326193510
Short name T460
Test name
Test status
Simulation time 246291689 ps
CPU time 1.02 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 218096 kb
Host smart-69089e24-2cf3-436d-b87c-afb9245425c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326193510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1326193510
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2121130270
Short name T281
Test name
Test status
Simulation time 163315906 ps
CPU time 0.81 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:33 PM PDT 24
Peak memory 200688 kb
Host smart-1a6244b7-138f-44e0-847c-bcc84d6145cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121130270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2121130270
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.596755665
Short name T455
Test name
Test status
Simulation time 1396799924 ps
CPU time 6.17 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200944 kb
Host smart-fc5662e4-eae9-4755-a870-7893af7aeca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596755665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.596755665
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1793971036
Short name T151
Test name
Test status
Simulation time 136498279 ps
CPU time 1.11 seconds
Started Apr 18 01:34:58 PM PDT 24
Finished Apr 18 01:35:00 PM PDT 24
Peak memory 200824 kb
Host smart-0a1592bd-37e4-42de-a9a3-882c1536dcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793971036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1793971036
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4164231373
Short name T299
Test name
Test status
Simulation time 246406100 ps
CPU time 1.41 seconds
Started Apr 18 01:34:18 PM PDT 24
Finished Apr 18 01:34:20 PM PDT 24
Peak memory 200932 kb
Host smart-766ff300-72e3-4186-9ee5-361629a18258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164231373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4164231373
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.744186685
Short name T470
Test name
Test status
Simulation time 1770587248 ps
CPU time 6.43 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:30 PM PDT 24
Peak memory 200932 kb
Host smart-bf128333-2e2b-4cc3-a2b0-15fd0ad6d2fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744186685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.744186685
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3636102025
Short name T386
Test name
Test status
Simulation time 289523598 ps
CPU time 1.85 seconds
Started Apr 18 01:34:20 PM PDT 24
Finished Apr 18 01:34:22 PM PDT 24
Peak memory 209040 kb
Host smart-557bd7bd-8d47-4f20-94b1-ee9b1128d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636102025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3636102025
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3100558519
Short name T344
Test name
Test status
Simulation time 187403326 ps
CPU time 1.16 seconds
Started Apr 18 01:34:27 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200804 kb
Host smart-f49343c7-f5c0-4ea0-ad10-05bdf71454a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100558519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3100558519
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.646780243
Short name T130
Test name
Test status
Simulation time 69330706 ps
CPU time 0.79 seconds
Started Apr 18 01:34:16 PM PDT 24
Finished Apr 18 01:34:18 PM PDT 24
Peak memory 200628 kb
Host smart-79de9b4c-d699-4337-8980-64c9a8484048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646780243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.646780243
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1149078828
Short name T499
Test name
Test status
Simulation time 1226951897 ps
CPU time 5.56 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:28 PM PDT 24
Peak memory 222708 kb
Host smart-c32f9ece-f569-455e-b851-08591875ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149078828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1149078828
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3468091524
Short name T507
Test name
Test status
Simulation time 244289679 ps
CPU time 1.03 seconds
Started Apr 18 01:34:19 PM PDT 24
Finished Apr 18 01:34:21 PM PDT 24
Peak memory 218116 kb
Host smart-f01dcc78-0924-4aa4-8fb1-97b5b0112657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468091524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3468091524
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.882932076
Short name T490
Test name
Test status
Simulation time 191655641 ps
CPU time 0.91 seconds
Started Apr 18 01:34:19 PM PDT 24
Finished Apr 18 01:34:20 PM PDT 24
Peak memory 200616 kb
Host smart-030784de-ff7f-4a12-ad1d-de9f328d1963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882932076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.882932076
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.473715568
Short name T444
Test name
Test status
Simulation time 1692748007 ps
CPU time 6.28 seconds
Started Apr 18 01:34:32 PM PDT 24
Finished Apr 18 01:34:41 PM PDT 24
Peak memory 200996 kb
Host smart-bfa1a9f9-aee5-41cd-9acc-e511c18096f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473715568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.473715568
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.59680656
Short name T132
Test name
Test status
Simulation time 171861545 ps
CPU time 1.22 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200732 kb
Host smart-63fb96d7-bd27-492e-a9f7-e5e3a8171c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59680656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.59680656
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1331544628
Short name T184
Test name
Test status
Simulation time 114243872 ps
CPU time 1.11 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200996 kb
Host smart-34aec599-0ead-4181-9e67-5c138c56f527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331544628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1331544628
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2631316228
Short name T454
Test name
Test status
Simulation time 5455579956 ps
CPU time 23.34 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:50 PM PDT 24
Peak memory 200980 kb
Host smart-d5a35592-896e-4543-b0b5-b82889095a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631316228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2631316228
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3994404400
Short name T75
Test name
Test status
Simulation time 141665611 ps
CPU time 1.83 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200748 kb
Host smart-27ad4af5-e690-4709-9747-01131c59f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994404400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3994404400
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2721085125
Short name T171
Test name
Test status
Simulation time 134616920 ps
CPU time 1.17 seconds
Started Apr 18 01:34:32 PM PDT 24
Finished Apr 18 01:34:35 PM PDT 24
Peak memory 200880 kb
Host smart-13837fbe-4a54-4c45-aabe-73228b1753eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721085125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2721085125
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1830832132
Short name T330
Test name
Test status
Simulation time 92028400 ps
CPU time 0.77 seconds
Started Apr 18 01:34:24 PM PDT 24
Finished Apr 18 01:34:27 PM PDT 24
Peak memory 200604 kb
Host smart-6064f4a1-49d9-49c5-8427-fa45ad717453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830832132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1830832132
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3293087105
Short name T28
Test name
Test status
Simulation time 1227799070 ps
CPU time 5.74 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:41 PM PDT 24
Peak memory 222652 kb
Host smart-57b078e0-6b7b-4393-8054-017ccf3dc37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293087105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3293087105
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3574208232
Short name T97
Test name
Test status
Simulation time 244154172 ps
CPU time 1.08 seconds
Started Apr 18 01:34:22 PM PDT 24
Finished Apr 18 01:34:24 PM PDT 24
Peak memory 218224 kb
Host smart-68f488fc-918d-434d-a643-9f8f0ac8da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574208232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3574208232
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.4119416201
Short name T17
Test name
Test status
Simulation time 143407725 ps
CPU time 0.78 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 200616 kb
Host smart-85ac4644-ecf5-4694-a380-9b0bb63784e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119416201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4119416201
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.4092224170
Short name T101
Test name
Test status
Simulation time 1534664719 ps
CPU time 6.14 seconds
Started Apr 18 01:34:23 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200996 kb
Host smart-95311ce1-4d6f-4e6b-9289-12bdb69b889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092224170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.4092224170
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2224995556
Short name T527
Test name
Test status
Simulation time 143618096 ps
CPU time 1.07 seconds
Started Apr 18 01:34:30 PM PDT 24
Finished Apr 18 01:34:34 PM PDT 24
Peak memory 200876 kb
Host smart-09563a5d-c6be-43de-9f4b-d689447b03fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224995556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2224995556
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.233082297
Short name T397
Test name
Test status
Simulation time 246863572 ps
CPU time 1.55 seconds
Started Apr 18 01:34:28 PM PDT 24
Finished Apr 18 01:34:32 PM PDT 24
Peak memory 201028 kb
Host smart-6419db4e-148d-42f0-b240-f89fb8036356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233082297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.233082297
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1662805782
Short name T533
Test name
Test status
Simulation time 3662559429 ps
CPU time 15.42 seconds
Started Apr 18 01:34:14 PM PDT 24
Finished Apr 18 01:34:31 PM PDT 24
Peak memory 200980 kb
Host smart-77873b95-e4f5-439e-b53a-7a809854e464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662805782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1662805782
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3282979607
Short name T432
Test name
Test status
Simulation time 414361207 ps
CPU time 2.32 seconds
Started Apr 18 01:34:13 PM PDT 24
Finished Apr 18 01:34:16 PM PDT 24
Peak memory 200684 kb
Host smart-199d4012-8649-4e87-9c84-ca6beb845ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282979607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3282979607
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3779836437
Short name T255
Test name
Test status
Simulation time 142124393 ps
CPU time 0.99 seconds
Started Apr 18 01:34:21 PM PDT 24
Finished Apr 18 01:34:22 PM PDT 24
Peak memory 200752 kb
Host smart-12a8dfbc-89c4-4f14-8d23-c3d3c7fc43c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779836437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3779836437
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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