Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7740

1

T4

25

T5

25

T9

16

auto[1]

10863

1

T4

27

T5

21

T6

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5868	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6305	1			T1	1		T2	1		T3	1
reset_info_cp[2]	2817	1			T4	7		T5	5		T6	1
reset_info_cp[4]	3747	1			T4	9		T5	9		T6	1
reset_info_cp[8]	97	1			T9	1		T24	1		T34	1
reset_info_cp[16]	102	1			T22	2		T24	2		T34	3
reset_info_cp[32]	108	1			T24	1		T34	2		T27	1
reset_info_cp[64]	92	1			T12	2		T24	1		T34	3
reset_info_cp[128]	87	1			T4	1		T26	1		T54	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2996	1			T4	4		T5	9		T22	13
reset_info_cp[1]	auto[1]	2689	1			T4	14		T5	10		T6	1
reset_info_cp[2]	auto[0]	859	1			T4	5		T5	3		T24	13
reset_info_cp[2]	auto[1]	1958	1			T4	2		T5	2		T6	1
reset_info_cp[4]	auto[0]	1303	1			T4	4		T5	5		T24	23
reset_info_cp[4]	auto[1]	2444	1			T4	5		T5	4		T6	1
reset_info_cp[8]	auto[0]	37	1			T9	1		T24	1		T108	1
reset_info_cp[8]	auto[1]	60	1			T34	1		T26	1		T54	1
reset_info_cp[16]	auto[0]	36	1			T34	3		T87	1		T107	1
reset_info_cp[16]	auto[1]	66	1			T22	2		T24	2		T26	3
reset_info_cp[32]	auto[0]	40	1			T24	1		T134	1		T135	1
reset_info_cp[32]	auto[1]	68	1			T34	2		T27	1		T54	1
reset_info_cp[64]	auto[0]	35	1			T12	2		T24	1		T34	1
reset_info_cp[64]	auto[1]	57	1			T34	2		T25	1		T27	1
reset_info_cp[128]	auto[0]	34	1			T4	1		T108	2		T104	4
reset_info_cp[128]	auto[1]	53	1			T26	1		T54	1		T47	1