Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T534 /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1873075429 Apr 21 01:02:35 PM PDT 24 Apr 21 01:02:37 PM PDT 24 100455592 ps
T535 /workspace/coverage/default/39.rstmgr_alert_test.584096577 Apr 21 01:02:38 PM PDT 24 Apr 21 01:02:39 PM PDT 24 64790719 ps
T536 /workspace/coverage/default/26.rstmgr_reset.4257499635 Apr 21 01:02:13 PM PDT 24 Apr 21 01:02:21 PM PDT 24 1624005623 ps
T75 /workspace/coverage/default/4.rstmgr_sec_cm.2171431085 Apr 21 01:02:00 PM PDT 24 Apr 21 01:02:25 PM PDT 24 16671378365 ps
T537 /workspace/coverage/default/2.rstmgr_alert_test.3084008728 Apr 21 01:01:39 PM PDT 24 Apr 21 01:01:40 PM PDT 24 85993673 ps
T60 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1079678945 Apr 21 12:44:04 PM PDT 24 Apr 21 12:44:05 PM PDT 24 78234804 ps
T61 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2142596974 Apr 21 12:44:14 PM PDT 24 Apr 21 12:44:15 PM PDT 24 76037598 ps
T62 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3259508085 Apr 21 12:43:58 PM PDT 24 Apr 21 12:44:00 PM PDT 24 146453536 ps
T109 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.948742670 Apr 21 12:44:01 PM PDT 24 Apr 21 12:44:04 PM PDT 24 270664456 ps
T64 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4259828678 Apr 21 12:43:45 PM PDT 24 Apr 21 12:43:49 PM PDT 24 887667027 ps
T65 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2793020874 Apr 21 12:44:10 PM PDT 24 Apr 21 12:44:14 PM PDT 24 418326732 ps
T110 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.207995928 Apr 21 12:44:14 PM PDT 24 Apr 21 12:44:15 PM PDT 24 62994789 ps
T133 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1792326882 Apr 21 12:43:52 PM PDT 24 Apr 21 12:44:01 PM PDT 24 1580534614 ps
T538 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3701236288 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:04 PM PDT 24 345406767 ps
T66 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1458282970 Apr 21 12:44:14 PM PDT 24 Apr 21 12:44:17 PM PDT 24 417197095 ps
T539 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.832059085 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:01 PM PDT 24 96399709 ps
T67 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3358506443 Apr 21 12:44:05 PM PDT 24 Apr 21 12:44:07 PM PDT 24 182070595 ps
T540 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2228571340 Apr 21 12:43:50 PM PDT 24 Apr 21 12:43:52 PM PDT 24 130575788 ps
T111 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1721247923 Apr 21 12:44:01 PM PDT 24 Apr 21 12:44:03 PM PDT 24 61651939 ps
T68 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.277696832 Apr 21 12:43:57 PM PDT 24 Apr 21 12:44:01 PM PDT 24 293237890 ps
T92 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.97420985 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:09 PM PDT 24 884126968 ps
T112 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.653915714 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:03 PM PDT 24 155744308 ps
T113 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2652084813 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:13 PM PDT 24 75280252 ps
T93 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3336919673 Apr 21 12:44:02 PM PDT 24 Apr 21 12:44:05 PM PDT 24 180234025 ps
T114 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3016372497 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:01 PM PDT 24 258948636 ps
T94 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3829363121 Apr 21 12:43:58 PM PDT 24 Apr 21 12:44:00 PM PDT 24 117456087 ps
T115 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4101171944 Apr 21 12:44:12 PM PDT 24 Apr 21 12:44:14 PM PDT 24 70782159 ps
T116 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4066062924 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:03 PM PDT 24 287781642 ps
T95 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.885218997 Apr 21 12:44:01 PM PDT 24 Apr 21 12:44:06 PM PDT 24 515278249 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3545509058 Apr 21 12:43:48 PM PDT 24 Apr 21 12:43:51 PM PDT 24 200913851 ps
T96 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4280196417 Apr 21 12:44:15 PM PDT 24 Apr 21 12:44:20 PM PDT 24 621570761 ps
T97 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.512947765 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:13 PM PDT 24 892570354 ps
T98 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1342539822 Apr 21 12:43:56 PM PDT 24 Apr 21 12:44:00 PM PDT 24 513282863 ps
T131 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2680043737 Apr 21 12:43:57 PM PDT 24 Apr 21 12:44:00 PM PDT 24 497371450 ps
T542 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1822799495 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:11 PM PDT 24 208662024 ps
T543 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2884176211 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:09 PM PDT 24 170236375 ps
T544 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1154426279 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:01 PM PDT 24 148230519 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.242741652 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:09 PM PDT 24 354492700 ps
T120 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.193117776 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:14 PM PDT 24 941087967 ps
T546 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2008352327 Apr 21 12:43:57 PM PDT 24 Apr 21 12:44:00 PM PDT 24 362319576 ps
T547 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3897690174 Apr 21 12:43:58 PM PDT 24 Apr 21 12:44:00 PM PDT 24 85913998 ps
T548 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.927704924 Apr 21 12:44:10 PM PDT 24 Apr 21 12:44:12 PM PDT 24 128654386 ps
T549 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3521540852 Apr 21 12:43:54 PM PDT 24 Apr 21 12:43:57 PM PDT 24 554025412 ps
T550 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3175989584 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:05 PM PDT 24 135986822 ps
T551 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1594737248 Apr 21 12:44:01 PM PDT 24 Apr 21 12:44:03 PM PDT 24 236541989 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.405381530 Apr 21 12:43:54 PM PDT 24 Apr 21 12:43:56 PM PDT 24 91237985 ps
T553 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3206233014 Apr 21 12:44:18 PM PDT 24 Apr 21 12:44:20 PM PDT 24 513657343 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3258289114 Apr 21 12:43:54 PM PDT 24 Apr 21 12:43:59 PM PDT 24 803112444 ps
T117 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1809810504 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:09 PM PDT 24 533950694 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2413922180 Apr 21 12:44:21 PM PDT 24 Apr 21 12:44:23 PM PDT 24 57235981 ps
T556 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1159098538 Apr 21 12:44:12 PM PDT 24 Apr 21 12:44:15 PM PDT 24 494994559 ps
T118 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1625685252 Apr 21 12:43:58 PM PDT 24 Apr 21 12:44:02 PM PDT 24 885196524 ps
T557 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.302244033 Apr 21 12:43:48 PM PDT 24 Apr 21 12:43:51 PM PDT 24 85988712 ps
T558 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3943357857 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:10 PM PDT 24 475034053 ps
T559 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3772483629 Apr 21 12:43:54 PM PDT 24 Apr 21 12:43:57 PM PDT 24 100858311 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2658332923 Apr 21 12:43:47 PM PDT 24 Apr 21 12:43:50 PM PDT 24 82815960 ps
T561 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3081868594 Apr 21 12:44:07 PM PDT 24 Apr 21 12:44:09 PM PDT 24 131412229 ps
T562 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3256934635 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:15 PM PDT 24 83524239 ps
T563 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3312394045 Apr 21 12:43:58 PM PDT 24 Apr 21 12:43:59 PM PDT 24 69365643 ps
T564 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3226097205 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:14 PM PDT 24 118288052 ps
T565 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3233807704 Apr 21 12:43:54 PM PDT 24 Apr 21 12:43:57 PM PDT 24 390912043 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1399829008 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:08 PM PDT 24 60360339 ps
T567 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3238342769 Apr 21 12:43:52 PM PDT 24 Apr 21 12:43:54 PM PDT 24 109495186 ps
T568 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1480905540 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:11 PM PDT 24 89618944 ps
T569 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.515648786 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:08 PM PDT 24 81497681 ps
T570 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3745422612 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:10 PM PDT 24 503193148 ps
T571 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1178905179 Apr 21 12:44:20 PM PDT 24 Apr 21 12:44:22 PM PDT 24 443125285 ps
T572 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3091541687 Apr 21 12:43:56 PM PDT 24 Apr 21 12:43:58 PM PDT 24 79648574 ps
T573 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3145320784 Apr 21 12:44:05 PM PDT 24 Apr 21 12:44:09 PM PDT 24 417943203 ps
T574 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3562071947 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:11 PM PDT 24 201697539 ps
T575 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2889306509 Apr 21 12:44:17 PM PDT 24 Apr 21 12:44:19 PM PDT 24 91901639 ps
T576 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4208145643 Apr 21 12:43:55 PM PDT 24 Apr 21 12:43:57 PM PDT 24 111858462 ps
T577 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.419422209 Apr 21 12:43:58 PM PDT 24 Apr 21 12:44:00 PM PDT 24 105070949 ps
T578 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2294756144 Apr 21 12:44:04 PM PDT 24 Apr 21 12:44:09 PM PDT 24 998873527 ps
T132 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.496762947 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:02 PM PDT 24 535078574 ps
T579 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1213555369 Apr 21 12:44:13 PM PDT 24 Apr 21 12:44:17 PM PDT 24 567084621 ps
T580 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1343766700 Apr 21 12:44:01 PM PDT 24 Apr 21 12:44:03 PM PDT 24 65942100 ps
T581 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.171875788 Apr 21 12:44:12 PM PDT 24 Apr 21 12:44:13 PM PDT 24 168074668 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3104164904 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:01 PM PDT 24 103617692 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2824074999 Apr 21 12:43:50 PM PDT 24 Apr 21 12:43:52 PM PDT 24 109689224 ps
T584 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1952455825 Apr 21 12:43:47 PM PDT 24 Apr 21 12:43:53 PM PDT 24 275704294 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2499588287 Apr 21 12:44:10 PM PDT 24 Apr 21 12:44:12 PM PDT 24 421955093 ps
T586 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3278996904 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:01 PM PDT 24 82112849 ps
T587 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1543508544 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:02 PM PDT 24 124733196 ps
T588 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2570081388 Apr 21 12:44:05 PM PDT 24 Apr 21 12:44:06 PM PDT 24 110946132 ps
T589 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1115778614 Apr 21 12:44:13 PM PDT 24 Apr 21 12:44:15 PM PDT 24 119747462 ps
T590 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2460388503 Apr 21 12:43:49 PM PDT 24 Apr 21 12:44:00 PM PDT 24 2010041224 ps
T119 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1176550649 Apr 21 12:44:02 PM PDT 24 Apr 21 12:44:05 PM PDT 24 430121355 ps
T591 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.912443586 Apr 21 12:43:50 PM PDT 24 Apr 21 12:43:54 PM PDT 24 260694545 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2680145483 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:01 PM PDT 24 59614025 ps
T593 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1290399046 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:02 PM PDT 24 140583167 ps
T594 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1149430227 Apr 21 12:43:50 PM PDT 24 Apr 21 12:43:53 PM PDT 24 107981019 ps
T595 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4241184988 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:11 PM PDT 24 216317384 ps
T596 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2134775030 Apr 21 12:43:54 PM PDT 24 Apr 21 12:43:56 PM PDT 24 123329812 ps
T597 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3326492436 Apr 21 12:44:19 PM PDT 24 Apr 21 12:44:21 PM PDT 24 173481106 ps
T598 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3093392632 Apr 21 12:44:01 PM PDT 24 Apr 21 12:44:03 PM PDT 24 132732866 ps
T599 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.384201260 Apr 21 12:44:09 PM PDT 24 Apr 21 12:44:11 PM PDT 24 479662600 ps
T600 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2033669301 Apr 21 12:44:06 PM PDT 24 Apr 21 12:44:07 PM PDT 24 65777323 ps
T601 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1221543903 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:03 PM PDT 24 417904672 ps
T602 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2494543738 Apr 21 12:43:54 PM PDT 24 Apr 21 12:43:56 PM PDT 24 145024950 ps
T603 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1906981855 Apr 21 12:44:05 PM PDT 24 Apr 21 12:44:08 PM PDT 24 326780834 ps
T604 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.8600162 Apr 21 12:44:07 PM PDT 24 Apr 21 12:44:09 PM PDT 24 96072091 ps
T605 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.39787622 Apr 21 12:44:12 PM PDT 24 Apr 21 12:44:14 PM PDT 24 118731998 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1006403578 Apr 21 12:43:55 PM PDT 24 Apr 21 12:43:57 PM PDT 24 141606405 ps
T607 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2066918339 Apr 21 12:44:08 PM PDT 24 Apr 21 12:44:10 PM PDT 24 106608144 ps
T608 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2077000975 Apr 21 12:44:13 PM PDT 24 Apr 21 12:44:14 PM PDT 24 93371254 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1284423804 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:01 PM PDT 24 177997164 ps
T610 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3477232652 Apr 21 12:43:54 PM PDT 24 Apr 21 12:43:59 PM PDT 24 513112125 ps
T611 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.264761584 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:14 PM PDT 24 283410807 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1432212936 Apr 21 12:43:46 PM PDT 24 Apr 21 12:43:50 PM PDT 24 155073690 ps
T100 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1572371116 Apr 21 12:43:59 PM PDT 24 Apr 21 12:44:01 PM PDT 24 75319839 ps
T613 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4049387330 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:03 PM PDT 24 491778948 ps
T614 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1740131066 Apr 21 12:43:49 PM PDT 24 Apr 21 12:43:53 PM PDT 24 192484980 ps
T615 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2702581574 Apr 21 12:43:52 PM PDT 24 Apr 21 12:43:54 PM PDT 24 120333307 ps
T616 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2189469692 Apr 21 12:44:12 PM PDT 24 Apr 21 12:44:14 PM PDT 24 198950153 ps
T617 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4177201149 Apr 21 12:43:56 PM PDT 24 Apr 21 12:44:00 PM PDT 24 330777913 ps
T121 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.769768735 Apr 21 12:44:00 PM PDT 24 Apr 21 12:44:02 PM PDT 24 472368180 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1909743165 Apr 21 12:43:57 PM PDT 24 Apr 21 12:43:59 PM PDT 24 175663301 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1186277056 Apr 21 12:44:05 PM PDT 24 Apr 21 12:44:06 PM PDT 24 140572159 ps
T620 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2051922728 Apr 21 12:44:11 PM PDT 24 Apr 21 12:44:14 PM PDT 24 430108771 ps

Test location /workspace/coverage/default/14.rstmgr_smoke.4190244701
Short name T6
Test name
Test status
Simulation time 225991589 ps
CPU time 1.42 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200948 kb
Host smart-bfe7303d-a496-449f-a6ea-c1d7b225f3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190244701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4190244701
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3736268856
Short name T34
Test name
Test status
Simulation time 6907469257 ps
CPU time 30.33 seconds
Started Apr 21 01:02:11 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 209280 kb
Host smart-fe8429bd-cdc2-43bc-a163-df6dabfe0f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736268856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3736268856
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4280196417
Short name T96
Test name
Test status
Simulation time 621570761 ps
CPU time 3.79 seconds
Started Apr 21 12:44:15 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 209284 kb
Host smart-ec47b8b1-050d-46f5-8ab4-5c9200461c07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280196417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.4280196417
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.315821359
Short name T74
Test name
Test status
Simulation time 8296849578 ps
CPU time 15.97 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:01:59 PM PDT 24
Peak memory 217760 kb
Host smart-681afc6b-a0fd-4ca8-a27f-141f2ef42122
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315821359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.315821359
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.4087302242
Short name T85
Test name
Test status
Simulation time 385913407 ps
CPU time 2.21 seconds
Started Apr 21 01:01:44 PM PDT 24
Finished Apr 21 01:01:47 PM PDT 24
Peak memory 200820 kb
Host smart-95ca2ff8-54db-4ce8-961d-e55c5d1e85f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087302242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.4087302242
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1620453772
Short name T26
Test name
Test status
Simulation time 1902165312 ps
CPU time 7.33 seconds
Started Apr 21 01:02:54 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 218116 kb
Host smart-82d7c2e0-225b-4ae7-bbb6-14dce998481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620453772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1620453772
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4259828678
Short name T64
Test name
Test status
Simulation time 887667027 ps
CPU time 2.9 seconds
Started Apr 21 12:43:45 PM PDT 24
Finished Apr 21 12:43:49 PM PDT 24
Peak memory 201076 kb
Host smart-4b3b5895-741d-4643-a217-86748fc6de13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259828678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4259828678
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.786178102
Short name T72
Test name
Test status
Simulation time 76040006 ps
CPU time 0.81 seconds
Started Apr 21 01:02:10 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 200588 kb
Host smart-846b0c51-3cc7-4bec-ba24-e218d1db52da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786178102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.786178102
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.175069726
Short name T104
Test name
Test status
Simulation time 11404245267 ps
CPU time 36.63 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:38 PM PDT 24
Peak memory 209252 kb
Host smart-8e7878b8-7976-4fe6-93f2-edd0068bafcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175069726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.175069726
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1148271902
Short name T46
Test name
Test status
Simulation time 111331827 ps
CPU time 1.07 seconds
Started Apr 21 01:01:54 PM PDT 24
Finished Apr 21 01:01:56 PM PDT 24
Peak memory 200816 kb
Host smart-b222cc17-cbdc-446a-9853-cc6727fdd527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148271902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1148271902
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1172039856
Short name T29
Test name
Test status
Simulation time 1231618304 ps
CPU time 5.81 seconds
Started Apr 21 01:02:10 PM PDT 24
Finished Apr 21 01:02:17 PM PDT 24
Peak memory 218204 kb
Host smart-7791e952-7e84-4ea1-99e8-9c7f43e415c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172039856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1172039856
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3172580417
Short name T135
Test name
Test status
Simulation time 104318330 ps
CPU time 1.03 seconds
Started Apr 21 01:02:06 PM PDT 24
Finished Apr 21 01:02:08 PM PDT 24
Peak memory 200820 kb
Host smart-5d678452-7757-4ecd-8381-3ca3edff67da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172580417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3172580417
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.769768735
Short name T121
Test name
Test status
Simulation time 472368180 ps
CPU time 1.92 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:02 PM PDT 24
Peak memory 201040 kb
Host smart-8ebe145a-b35a-4548-9faf-9bba064151fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769768735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
769768735
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2943534499
Short name T25
Test name
Test status
Simulation time 1891963609 ps
CPU time 6.74 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:24 PM PDT 24
Peak memory 217604 kb
Host smart-1bed0f37-fa72-409d-b569-5063482b8bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943534499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2943534499
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.496762947
Short name T132
Test name
Test status
Simulation time 535078574 ps
CPU time 1.97 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:02 PM PDT 24
Peak memory 201120 kb
Host smart-78851d99-a4e6-4e1f-a9f5-a7aa7d769587
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496762947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.496762947
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2793020874
Short name T65
Test name
Test status
Simulation time 418326732 ps
CPU time 3.14 seconds
Started Apr 21 12:44:10 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 209328 kb
Host smart-27ab43af-82e2-442a-939e-0226fca09489
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793020874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2793020874
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1721247923
Short name T111
Test name
Test status
Simulation time 61651939 ps
CPU time 0.78 seconds
Started Apr 21 12:44:01 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 200776 kb
Host smart-ee0ebd60-5b34-4f94-b61b-7d8d3c6b8d6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721247923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1721247923
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2273660714
Short name T7
Test name
Test status
Simulation time 124909533 ps
CPU time 0.82 seconds
Started Apr 21 01:01:41 PM PDT 24
Finished Apr 21 01:01:42 PM PDT 24
Peak memory 200636 kb
Host smart-a8fd3afa-ae1e-4002-a03a-c9e93e038d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273660714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2273660714
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1809810504
Short name T117
Test name
Test status
Simulation time 533950694 ps
CPU time 1.91 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 201124 kb
Host smart-eff54799-7eaa-47e8-ba98-b69bd96c779c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809810504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1809810504
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.193117776
Short name T120
Test name
Test status
Simulation time 941087967 ps
CPU time 3 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 201156 kb
Host smart-209ed611-12d4-4095-9404-911fba4f41a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193117776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
193117776
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1563088236
Short name T255
Test name
Test status
Simulation time 5299038989 ps
CPU time 23.93 seconds
Started Apr 21 01:01:59 PM PDT 24
Finished Apr 21 01:02:23 PM PDT 24
Peak memory 201016 kb
Host smart-8e8dcffb-12cb-4a2e-afdc-c8761e2cbdab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563088236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1563088236
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3545509058
Short name T541
Test name
Test status
Simulation time 200913851 ps
CPU time 1.59 seconds
Started Apr 21 12:43:48 PM PDT 24
Finished Apr 21 12:43:51 PM PDT 24
Peak memory 201004 kb
Host smart-e013df18-91e4-4786-8bea-cef32353e7e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545509058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
545509058
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2460388503
Short name T590
Test name
Test status
Simulation time 2010041224 ps
CPU time 9.31 seconds
Started Apr 21 12:43:49 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 209256 kb
Host smart-63969995-895b-49ef-9510-6b5fc4413357
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460388503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
460388503
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.419422209
Short name T577
Test name
Test status
Simulation time 105070949 ps
CPU time 0.88 seconds
Started Apr 21 12:43:58 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 200788 kb
Host smart-2788a7eb-6c00-4d74-b347-ec0b486db1cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419422209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.419422209
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2570081388
Short name T588
Test name
Test status
Simulation time 110946132 ps
CPU time 0.94 seconds
Started Apr 21 12:44:05 PM PDT 24
Finished Apr 21 12:44:06 PM PDT 24
Peak memory 201024 kb
Host smart-0b533b3d-cbed-4da0-b4a7-83134dda886f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570081388 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2570081388
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3312394045
Short name T563
Test name
Test status
Simulation time 69365643 ps
CPU time 0.78 seconds
Started Apr 21 12:43:58 PM PDT 24
Finished Apr 21 12:43:59 PM PDT 24
Peak memory 200856 kb
Host smart-2a125878-e451-40b4-82d5-93e16d5bf039
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312394045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3312394045
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2494543738
Short name T602
Test name
Test status
Simulation time 145024950 ps
CPU time 1.32 seconds
Started Apr 21 12:43:54 PM PDT 24
Finished Apr 21 12:43:56 PM PDT 24
Peak memory 201084 kb
Host smart-3146da8b-c8d7-4a36-b2ad-3f05a8fb0f9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494543738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2494543738
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3477232652
Short name T610
Test name
Test status
Simulation time 513112125 ps
CPU time 3.44 seconds
Started Apr 21 12:43:54 PM PDT 24
Finished Apr 21 12:43:59 PM PDT 24
Peak memory 209200 kb
Host smart-6ca0ad63-ba19-4a81-aed9-92eb2abde871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477232652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3477232652
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1432212936
Short name T612
Test name
Test status
Simulation time 155073690 ps
CPU time 2 seconds
Started Apr 21 12:43:46 PM PDT 24
Finished Apr 21 12:43:50 PM PDT 24
Peak memory 200972 kb
Host smart-eb0d27da-4e76-4084-a446-64f6c67c2420
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432212936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
432212936
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3258289114
Short name T554
Test name
Test status
Simulation time 803112444 ps
CPU time 4.5 seconds
Started Apr 21 12:43:54 PM PDT 24
Finished Apr 21 12:43:59 PM PDT 24
Peak memory 201016 kb
Host smart-85c68772-78ed-48b0-b5ba-25923cdf1a45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258289114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
258289114
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1186277056
Short name T619
Test name
Test status
Simulation time 140572159 ps
CPU time 0.94 seconds
Started Apr 21 12:44:05 PM PDT 24
Finished Apr 21 12:44:06 PM PDT 24
Peak memory 200852 kb
Host smart-fa4bf0cc-aa92-475a-88c5-7a808ce93c77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186277056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
186277056
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2702581574
Short name T615
Test name
Test status
Simulation time 120333307 ps
CPU time 1.36 seconds
Started Apr 21 12:43:52 PM PDT 24
Finished Apr 21 12:43:54 PM PDT 24
Peak memory 209192 kb
Host smart-cee0807f-32ca-4217-af9e-534f5ff6837c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702581574 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2702581574
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2413922180
Short name T555
Test name
Test status
Simulation time 57235981 ps
CPU time 0.74 seconds
Started Apr 21 12:44:21 PM PDT 24
Finished Apr 21 12:44:23 PM PDT 24
Peak memory 200824 kb
Host smart-b1a42ddc-c4b1-48df-b945-074451e4c4c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413922180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2413922180
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1740131066
Short name T614
Test name
Test status
Simulation time 192484980 ps
CPU time 1.45 seconds
Started Apr 21 12:43:49 PM PDT 24
Finished Apr 21 12:43:53 PM PDT 24
Peak memory 201128 kb
Host smart-11c1170a-1f15-45dc-a973-450696d32245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740131066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1740131066
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3081868594
Short name T561
Test name
Test status
Simulation time 131412229 ps
CPU time 1.83 seconds
Started Apr 21 12:44:07 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 209360 kb
Host smart-b90cba3b-a618-4d39-b2a9-ee83e7c82fd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081868594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3081868594
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1115778614
Short name T589
Test name
Test status
Simulation time 119747462 ps
CPU time 1 seconds
Started Apr 21 12:44:13 PM PDT 24
Finished Apr 21 12:44:15 PM PDT 24
Peak memory 200920 kb
Host smart-242ae1f9-7804-4995-9054-8d79c9bc342b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115778614 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1115778614
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3897690174
Short name T547
Test name
Test status
Simulation time 85913998 ps
CPU time 1 seconds
Started Apr 21 12:43:58 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 200916 kb
Host smart-152e233e-6fe1-49fc-9b50-0dfd8426b533
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897690174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3897690174
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3745422612
Short name T570
Test name
Test status
Simulation time 503193148 ps
CPU time 3.18 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:10 PM PDT 24
Peak memory 209344 kb
Host smart-1f7307d7-0230-47f7-9557-42304cf3f12a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745422612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3745422612
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1159098538
Short name T556
Test name
Test status
Simulation time 494994559 ps
CPU time 1.87 seconds
Started Apr 21 12:44:12 PM PDT 24
Finished Apr 21 12:44:15 PM PDT 24
Peak memory 201132 kb
Host smart-a37ab97b-0ab0-4eae-99b4-d4b8ca882498
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159098538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1159098538
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1284423804
Short name T609
Test name
Test status
Simulation time 177997164 ps
CPU time 1.24 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 209184 kb
Host smart-03231113-ae02-43df-b840-181b16d542c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284423804 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1284423804
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4101171944
Short name T115
Test name
Test status
Simulation time 70782159 ps
CPU time 0.87 seconds
Started Apr 21 12:44:12 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 200880 kb
Host smart-0509b9de-82bb-4cf8-a192-3e92a7959d0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101171944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4101171944
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4241184988
Short name T595
Test name
Test status
Simulation time 216317384 ps
CPU time 1.46 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 200996 kb
Host smart-9d7bad4a-d106-4257-8ba4-7f329ee0d4b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241184988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.4241184988
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.39787622
Short name T605
Test name
Test status
Simulation time 118731998 ps
CPU time 0.97 seconds
Started Apr 21 12:44:12 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 200976 kb
Host smart-b4d3e74f-d155-45cf-81e5-bc486952133d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39787622 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.39787622
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.8600162
Short name T604
Test name
Test status
Simulation time 96072091 ps
CPU time 0.89 seconds
Started Apr 21 12:44:07 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 200808 kb
Host smart-9d8399ea-55cc-4b5b-aab4-0fda5ae00779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8600162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.8600162
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4066062924
Short name T116
Test name
Test status
Simulation time 287781642 ps
CPU time 1.76 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 201120 kb
Host smart-c36849c9-a6a5-4672-8e00-39cd2356a36d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066062924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4066062924
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3145320784
Short name T573
Test name
Test status
Simulation time 417943203 ps
CPU time 3.4 seconds
Started Apr 21 12:44:05 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 209196 kb
Host smart-011eda59-4908-4448-9276-b06c3b76b4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145320784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3145320784
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4049387330
Short name T613
Test name
Test status
Simulation time 491778948 ps
CPU time 1.92 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 201076 kb
Host smart-3a19bf79-f127-4668-8c2f-9e87d4373871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049387330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.4049387330
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.927704924
Short name T548
Test name
Test status
Simulation time 128654386 ps
CPU time 0.98 seconds
Started Apr 21 12:44:10 PM PDT 24
Finished Apr 21 12:44:12 PM PDT 24
Peak memory 200864 kb
Host smart-dabafa4f-867d-426c-b71b-75063baa94ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927704924 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.927704924
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3256934635
Short name T562
Test name
Test status
Simulation time 83524239 ps
CPU time 0.94 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:15 PM PDT 24
Peak memory 200764 kb
Host smart-27556569-6228-4e78-b1a5-bc64be6d8455
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256934635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3256934635
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1154426279
Short name T544
Test name
Test status
Simulation time 148230519 ps
CPU time 1.08 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 200936 kb
Host smart-fa0c857a-350e-4b83-90d1-43bd37794acc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154426279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1154426279
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1176550649
Short name T119
Test name
Test status
Simulation time 430121355 ps
CPU time 1.77 seconds
Started Apr 21 12:44:02 PM PDT 24
Finished Apr 21 12:44:05 PM PDT 24
Peak memory 201044 kb
Host smart-07e62891-8ad8-4d36-9858-c6075735fdf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176550649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1176550649
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2077000975
Short name T608
Test name
Test status
Simulation time 93371254 ps
CPU time 0.86 seconds
Started Apr 21 12:44:13 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 200996 kb
Host smart-b913eec2-dbb2-40db-93e6-41715eb9731c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077000975 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2077000975
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2652084813
Short name T113
Test name
Test status
Simulation time 75280252 ps
CPU time 0.86 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:13 PM PDT 24
Peak memory 200864 kb
Host smart-fda2c2ff-593d-4052-8249-e0ae3e93e2cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652084813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2652084813
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1079678945
Short name T60
Test name
Test status
Simulation time 78234804 ps
CPU time 0.98 seconds
Started Apr 21 12:44:04 PM PDT 24
Finished Apr 21 12:44:05 PM PDT 24
Peak memory 200860 kb
Host smart-ed61d928-6b61-41b4-9653-f5425a3aacf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079678945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1079678945
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3226097205
Short name T564
Test name
Test status
Simulation time 118288052 ps
CPU time 1.76 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 217244 kb
Host smart-aeebfa82-d689-4db3-bbce-6b188ab8d728
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226097205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3226097205
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1543508544
Short name T587
Test name
Test status
Simulation time 124733196 ps
CPU time 1.24 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:02 PM PDT 24
Peak memory 209160 kb
Host smart-637819d7-ead4-4714-b85d-75c6c0dc8250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543508544 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1543508544
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3091541687
Short name T572
Test name
Test status
Simulation time 79648574 ps
CPU time 0.83 seconds
Started Apr 21 12:43:56 PM PDT 24
Finished Apr 21 12:43:58 PM PDT 24
Peak memory 200792 kb
Host smart-af584f0d-a930-44cc-9eff-55515f7a6d56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091541687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3091541687
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3259508085
Short name T62
Test name
Test status
Simulation time 146453536 ps
CPU time 1.13 seconds
Started Apr 21 12:43:58 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 200832 kb
Host smart-943cc7d0-5446-4b09-a56d-b6eb4502087b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259508085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3259508085
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4177201149
Short name T617
Test name
Test status
Simulation time 330777913 ps
CPU time 2.75 seconds
Started Apr 21 12:43:56 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 212160 kb
Host smart-b645fbe8-e7e1-48ce-a54d-210fbc1fae3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177201149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4177201149
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2499588287
Short name T585
Test name
Test status
Simulation time 421955093 ps
CPU time 1.76 seconds
Started Apr 21 12:44:10 PM PDT 24
Finished Apr 21 12:44:12 PM PDT 24
Peak memory 201144 kb
Host smart-7f5b2132-01b1-413d-90a2-c48d111805f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499588287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2499588287
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.171875788
Short name T581
Test name
Test status
Simulation time 168074668 ps
CPU time 1.06 seconds
Started Apr 21 12:44:12 PM PDT 24
Finished Apr 21 12:44:13 PM PDT 24
Peak memory 200916 kb
Host smart-ae2bc3ce-7237-49a4-b5d6-b5786779eb08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171875788 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.171875788
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2142596974
Short name T61
Test name
Test status
Simulation time 76037598 ps
CPU time 0.84 seconds
Started Apr 21 12:44:14 PM PDT 24
Finished Apr 21 12:44:15 PM PDT 24
Peak memory 200808 kb
Host smart-e509a673-4545-41c5-89e8-5ee679319e11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142596974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2142596974
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3016372497
Short name T114
Test name
Test status
Simulation time 258948636 ps
CPU time 1.73 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 201092 kb
Host smart-78da7c76-ab32-4b0f-8ef4-07646c631e15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016372497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3016372497
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1213555369
Short name T579
Test name
Test status
Simulation time 567084621 ps
CPU time 3.62 seconds
Started Apr 21 12:44:13 PM PDT 24
Finished Apr 21 12:44:17 PM PDT 24
Peak memory 209276 kb
Host smart-0b99fed1-6b16-4557-8c88-c1c9dfd0b200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213555369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1213555369
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2051922728
Short name T620
Test name
Test status
Simulation time 430108771 ps
CPU time 1.74 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 201064 kb
Host smart-de151df2-8ab5-4b88-9121-d5e9d9e1f13c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051922728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2051922728
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3175989584
Short name T550
Test name
Test status
Simulation time 135986822 ps
CPU time 1.2 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:05 PM PDT 24
Peak memory 209104 kb
Host smart-46d2e8a5-273c-4949-a377-cdbe9e892c85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175989584 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3175989584
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2033669301
Short name T600
Test name
Test status
Simulation time 65777323 ps
CPU time 0.85 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:07 PM PDT 24
Peak memory 200844 kb
Host smart-b4a8ab9b-3e96-4644-8aee-4a5dfec0d1b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033669301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2033669301
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1822799495
Short name T542
Test name
Test status
Simulation time 208662024 ps
CPU time 1.49 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 201044 kb
Host smart-087e3e24-fa2f-438d-88f6-662bd4677156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822799495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1822799495
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.264761584
Short name T611
Test name
Test status
Simulation time 283410807 ps
CPU time 2.06 seconds
Started Apr 21 12:44:11 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 209356 kb
Host smart-efd441be-d35c-4f4c-999f-e75d12c87058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264761584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.264761584
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.512947765
Short name T97
Test name
Test status
Simulation time 892570354 ps
CPU time 3.32 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:13 PM PDT 24
Peak memory 200988 kb
Host smart-a4fc8c09-0af6-439a-adc4-3c6a36fc7fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512947765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.512947765
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3562071947
Short name T574
Test name
Test status
Simulation time 201697539 ps
CPU time 2.1 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 209344 kb
Host smart-64270c0a-5cb9-47a2-adc6-2f21076e622d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562071947 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3562071947
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.515648786
Short name T569
Test name
Test status
Simulation time 81497681 ps
CPU time 0.87 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:08 PM PDT 24
Peak memory 200788 kb
Host smart-03f61855-cf09-4cf4-8e9b-e66c21ae6362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515648786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.515648786
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2889306509
Short name T575
Test name
Test status
Simulation time 91901639 ps
CPU time 1.03 seconds
Started Apr 21 12:44:17 PM PDT 24
Finished Apr 21 12:44:19 PM PDT 24
Peak memory 200896 kb
Host smart-8505cb07-bdb5-4da7-ab68-40b87cc23f86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889306509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2889306509
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.885218997
Short name T95
Test name
Test status
Simulation time 515278249 ps
CPU time 3.54 seconds
Started Apr 21 12:44:01 PM PDT 24
Finished Apr 21 12:44:06 PM PDT 24
Peak memory 212932 kb
Host smart-a96e94af-7465-403e-9140-d691407e0799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885218997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.885218997
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1458282970
Short name T66
Test name
Test status
Simulation time 417197095 ps
CPU time 1.88 seconds
Started Apr 21 12:44:14 PM PDT 24
Finished Apr 21 12:44:17 PM PDT 24
Peak memory 201128 kb
Host smart-de54c945-bd0d-4a7c-aeaa-e01b2923e0ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458282970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1458282970
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2884176211
Short name T543
Test name
Test status
Simulation time 170236375 ps
CPU time 1.2 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 209180 kb
Host smart-2e1952ad-db44-4c21-9c5a-6ab46318a105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884176211 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2884176211
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1480905540
Short name T568
Test name
Test status
Simulation time 89618944 ps
CPU time 0.9 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 200880 kb
Host smart-f44a880e-b928-4ad8-9307-10009655b64e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480905540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1480905540
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1594737248
Short name T551
Test name
Test status
Simulation time 236541989 ps
CPU time 1.63 seconds
Started Apr 21 12:44:01 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 201104 kb
Host smart-06ecab80-1b55-4e9a-bbf0-07f4bb861fba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594737248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1594737248
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3326492436
Short name T597
Test name
Test status
Simulation time 173481106 ps
CPU time 2.49 seconds
Started Apr 21 12:44:19 PM PDT 24
Finished Apr 21 12:44:21 PM PDT 24
Peak memory 217540 kb
Host smart-bca22b44-5341-434b-8f37-7a0c39488af0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326492436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3326492436
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3521540852
Short name T549
Test name
Test status
Simulation time 554025412 ps
CPU time 2.07 seconds
Started Apr 21 12:43:54 PM PDT 24
Finished Apr 21 12:43:57 PM PDT 24
Peak memory 200956 kb
Host smart-377ac62a-cf4d-404e-b6ea-074a9f95ec4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521540852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3521540852
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3104164904
Short name T582
Test name
Test status
Simulation time 103617692 ps
CPU time 1.36 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 209232 kb
Host smart-deb339cd-2893-4a21-a083-b52997378541
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104164904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
104164904
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2294756144
Short name T578
Test name
Test status
Simulation time 998873527 ps
CPU time 4.72 seconds
Started Apr 21 12:44:04 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 201036 kb
Host smart-14ed20dd-00cf-4fdb-b31d-764c29041a4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294756144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
294756144
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.405381530
Short name T552
Test name
Test status
Simulation time 91237985 ps
CPU time 0.83 seconds
Started Apr 21 12:43:54 PM PDT 24
Finished Apr 21 12:43:56 PM PDT 24
Peak memory 200796 kb
Host smart-740b215d-5cb4-498d-aede-84466653b573
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405381530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.405381530
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2824074999
Short name T583
Test name
Test status
Simulation time 109689224 ps
CPU time 1.13 seconds
Started Apr 21 12:43:50 PM PDT 24
Finished Apr 21 12:43:52 PM PDT 24
Peak memory 209208 kb
Host smart-dbb0bb24-d748-49c9-af9e-9153130bcd0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824074999 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2824074999
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2658332923
Short name T560
Test name
Test status
Simulation time 82815960 ps
CPU time 0.93 seconds
Started Apr 21 12:43:47 PM PDT 24
Finished Apr 21 12:43:50 PM PDT 24
Peak memory 200780 kb
Host smart-1ad6b031-cda7-4b03-8502-be071c2aa4d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658332923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2658332923
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.912443586
Short name T591
Test name
Test status
Simulation time 260694545 ps
CPU time 1.51 seconds
Started Apr 21 12:43:50 PM PDT 24
Finished Apr 21 12:43:54 PM PDT 24
Peak memory 201072 kb
Host smart-a626558e-f86b-4dcf-85d6-39689467f3bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912443586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.912443586
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1342539822
Short name T98
Test name
Test status
Simulation time 513282863 ps
CPU time 3.06 seconds
Started Apr 21 12:43:56 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 209272 kb
Host smart-78cdcd51-ce27-4afc-a917-aff4db7ba270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342539822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1342539822
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.97420985
Short name T92
Test name
Test status
Simulation time 884126968 ps
CPU time 3.01 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 201160 kb
Host smart-efbd26c3-df5d-4b86-87b3-485d60c92641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97420985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.97420985
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.242741652
Short name T545
Test name
Test status
Simulation time 354492700 ps
CPU time 2.4 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:09 PM PDT 24
Peak memory 200984 kb
Host smart-7df2e4f9-0753-428d-a943-2cb8ac0632f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242741652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.242741652
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1792326882
Short name T133
Test name
Test status
Simulation time 1580534614 ps
CPU time 8.18 seconds
Started Apr 21 12:43:52 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 200968 kb
Host smart-aad28031-f5e7-4b86-a2ad-91b27008691d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792326882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
792326882
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.832059085
Short name T539
Test name
Test status
Simulation time 96399709 ps
CPU time 0.86 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 200860 kb
Host smart-537750d7-90f3-4de3-97d5-152f0115f992
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832059085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.832059085
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1006403578
Short name T606
Test name
Test status
Simulation time 141606405 ps
CPU time 1.09 seconds
Started Apr 21 12:43:55 PM PDT 24
Finished Apr 21 12:43:57 PM PDT 24
Peak memory 211304 kb
Host smart-a4a73a24-0598-4d27-b2d5-bd34180a1765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006403578 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1006403578
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2680145483
Short name T592
Test name
Test status
Simulation time 59614025 ps
CPU time 0.78 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 200780 kb
Host smart-2ff397e8-5d04-4d0d-80e7-fc4f1531bbde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680145483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2680145483
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1290399046
Short name T593
Test name
Test status
Simulation time 140583167 ps
CPU time 1.18 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:02 PM PDT 24
Peak memory 200836 kb
Host smart-39257b91-a08d-4386-8f9e-02b2fbef4c80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290399046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1290399046
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3238342769
Short name T567
Test name
Test status
Simulation time 109495186 ps
CPU time 1.62 seconds
Started Apr 21 12:43:52 PM PDT 24
Finished Apr 21 12:43:54 PM PDT 24
Peak memory 217428 kb
Host smart-a26e3ab6-61bd-476a-a31f-b707cce7b72d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238342769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3238342769
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2680043737
Short name T131
Test name
Test status
Simulation time 497371450 ps
CPU time 1.99 seconds
Started Apr 21 12:43:57 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 201052 kb
Host smart-773e53f1-cbdc-4fd9-a9ab-f6f4b6764a61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680043737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2680043737
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3701236288
Short name T538
Test name
Test status
Simulation time 345406767 ps
CPU time 2.43 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:04 PM PDT 24
Peak memory 200984 kb
Host smart-6aa4528d-bcb7-495d-a654-0a1d988816ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701236288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
701236288
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1952455825
Short name T584
Test name
Test status
Simulation time 275704294 ps
CPU time 3.34 seconds
Started Apr 21 12:43:47 PM PDT 24
Finished Apr 21 12:43:53 PM PDT 24
Peak memory 201064 kb
Host smart-5e4254e5-f0c9-421e-aac3-a3000dc5502c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952455825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
952455825
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2228571340
Short name T540
Test name
Test status
Simulation time 130575788 ps
CPU time 0.92 seconds
Started Apr 21 12:43:50 PM PDT 24
Finished Apr 21 12:43:52 PM PDT 24
Peak memory 200784 kb
Host smart-d169e172-6229-4c6c-a462-b8ed0d327e28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228571340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
228571340
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1909743165
Short name T618
Test name
Test status
Simulation time 175663301 ps
CPU time 1.14 seconds
Started Apr 21 12:43:57 PM PDT 24
Finished Apr 21 12:43:59 PM PDT 24
Peak memory 209256 kb
Host smart-8708615f-6f7d-4a92-a9d6-c2cdd0700920
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909743165 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1909743165
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1343766700
Short name T580
Test name
Test status
Simulation time 65942100 ps
CPU time 0.77 seconds
Started Apr 21 12:44:01 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 200852 kb
Host smart-0063de6f-ec7a-4a72-bb01-91dc681572c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343766700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1343766700
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3772483629
Short name T559
Test name
Test status
Simulation time 100858311 ps
CPU time 1.36 seconds
Started Apr 21 12:43:54 PM PDT 24
Finished Apr 21 12:43:57 PM PDT 24
Peak memory 201008 kb
Host smart-dd32c072-097f-4713-a295-cc1b9f12145b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772483629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3772483629
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.277696832
Short name T68
Test name
Test status
Simulation time 293237890 ps
CPU time 2.62 seconds
Started Apr 21 12:43:57 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 217456 kb
Host smart-2e491404-4b40-4fbc-812a-7dca00295523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277696832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.277696832
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2134775030
Short name T596
Test name
Test status
Simulation time 123329812 ps
CPU time 1 seconds
Started Apr 21 12:43:54 PM PDT 24
Finished Apr 21 12:43:56 PM PDT 24
Peak memory 200992 kb
Host smart-e74bb147-dd85-407e-9657-24222510851d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134775030 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2134775030
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3278996904
Short name T586
Test name
Test status
Simulation time 82112849 ps
CPU time 0.85 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 200868 kb
Host smart-2ad53c83-962a-4b78-943b-4aa37542ab86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278996904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3278996904
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4208145643
Short name T576
Test name
Test status
Simulation time 111858462 ps
CPU time 1.3 seconds
Started Apr 21 12:43:55 PM PDT 24
Finished Apr 21 12:43:57 PM PDT 24
Peak memory 201160 kb
Host smart-d66b7f2c-c66d-40a0-859a-1dc3ef8ac6ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208145643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4208145643
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3943357857
Short name T558
Test name
Test status
Simulation time 475034053 ps
CPU time 3.65 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:10 PM PDT 24
Peak memory 217188 kb
Host smart-e37c4956-ee1c-46bf-873e-272a645a4eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943357857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3943357857
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1625685252
Short name T118
Test name
Test status
Simulation time 885196524 ps
CPU time 3.28 seconds
Started Apr 21 12:43:58 PM PDT 24
Finished Apr 21 12:44:02 PM PDT 24
Peak memory 200976 kb
Host smart-443e1ad4-9ffe-4926-9cee-4cad54dfd228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625685252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1625685252
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2066918339
Short name T607
Test name
Test status
Simulation time 106608144 ps
CPU time 1.13 seconds
Started Apr 21 12:44:08 PM PDT 24
Finished Apr 21 12:44:10 PM PDT 24
Peak memory 209204 kb
Host smart-9ca53e10-cd82-403f-b4a8-8f1f9599190a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066918339 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2066918339
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1572371116
Short name T100
Test name
Test status
Simulation time 75319839 ps
CPU time 0.84 seconds
Started Apr 21 12:43:59 PM PDT 24
Finished Apr 21 12:44:01 PM PDT 24
Peak memory 200780 kb
Host smart-396a1907-2be1-4ee5-a54d-e77e8de7f264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572371116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1572371116
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3093392632
Short name T598
Test name
Test status
Simulation time 132732866 ps
CPU time 1.28 seconds
Started Apr 21 12:44:01 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 201120 kb
Host smart-64ad54e0-fec8-49b2-8f54-bf644f46f964
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093392632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3093392632
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3336919673
Short name T93
Test name
Test status
Simulation time 180234025 ps
CPU time 2.66 seconds
Started Apr 21 12:44:02 PM PDT 24
Finished Apr 21 12:44:05 PM PDT 24
Peak memory 209332 kb
Host smart-0eb7b9dc-b867-4a6e-89a3-e4aac3086d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336919673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3336919673
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3206233014
Short name T553
Test name
Test status
Simulation time 513657343 ps
CPU time 2.09 seconds
Started Apr 21 12:44:18 PM PDT 24
Finished Apr 21 12:44:20 PM PDT 24
Peak memory 201040 kb
Host smart-d6cbf6f1-90f8-4d73-889e-e4df9f1dab59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206233014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3206233014
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3358506443
Short name T67
Test name
Test status
Simulation time 182070595 ps
CPU time 1.23 seconds
Started Apr 21 12:44:05 PM PDT 24
Finished Apr 21 12:44:07 PM PDT 24
Peak memory 209096 kb
Host smart-a620290f-ba5b-4f0e-b674-75ea0ba3bff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358506443 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3358506443
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.302244033
Short name T557
Test name
Test status
Simulation time 85988712 ps
CPU time 0.89 seconds
Started Apr 21 12:43:48 PM PDT 24
Finished Apr 21 12:43:51 PM PDT 24
Peak memory 200772 kb
Host smart-e9f21ee8-3965-492f-9193-0dce2932b0a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302244033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.302244033
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1149430227
Short name T594
Test name
Test status
Simulation time 107981019 ps
CPU time 1.25 seconds
Started Apr 21 12:43:50 PM PDT 24
Finished Apr 21 12:43:53 PM PDT 24
Peak memory 201024 kb
Host smart-f6f5bd84-1f78-4dfd-ad06-9f19b485f452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149430227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1149430227
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2008352327
Short name T546
Test name
Test status
Simulation time 362319576 ps
CPU time 2.56 seconds
Started Apr 21 12:43:57 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 209256 kb
Host smart-a56de1ca-ac2c-4738-8be4-a64be64e4e54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008352327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2008352327
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1221543903
Short name T601
Test name
Test status
Simulation time 417904672 ps
CPU time 1.92 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 201036 kb
Host smart-8f7ad622-c10b-4ec8-9f53-2e3ddd58ecc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221543903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1221543903
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3829363121
Short name T94
Test name
Test status
Simulation time 117456087 ps
CPU time 0.93 seconds
Started Apr 21 12:43:58 PM PDT 24
Finished Apr 21 12:44:00 PM PDT 24
Peak memory 200876 kb
Host smart-de165b52-3e7a-4821-a042-8af328d73dd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829363121 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3829363121
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1399829008
Short name T566
Test name
Test status
Simulation time 60360339 ps
CPU time 0.76 seconds
Started Apr 21 12:44:06 PM PDT 24
Finished Apr 21 12:44:08 PM PDT 24
Peak memory 200776 kb
Host smart-09acf02b-6443-4295-becb-8c83babc54e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399829008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1399829008
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.948742670
Short name T109
Test name
Test status
Simulation time 270664456 ps
CPU time 1.75 seconds
Started Apr 21 12:44:01 PM PDT 24
Finished Apr 21 12:44:04 PM PDT 24
Peak memory 201124 kb
Host smart-e506a534-729a-4e23-84f4-6ac3b1892609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948742670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.948742670
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1906981855
Short name T603
Test name
Test status
Simulation time 326780834 ps
CPU time 2.46 seconds
Started Apr 21 12:44:05 PM PDT 24
Finished Apr 21 12:44:08 PM PDT 24
Peak memory 209312 kb
Host smart-9242cdb5-ea9f-4115-8660-93661d57e588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906981855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1906981855
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.384201260
Short name T599
Test name
Test status
Simulation time 479662600 ps
CPU time 1.88 seconds
Started Apr 21 12:44:09 PM PDT 24
Finished Apr 21 12:44:11 PM PDT 24
Peak memory 201080 kb
Host smart-a1b81837-8a41-4d76-adac-210a120f70bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384201260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
384201260
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2189469692
Short name T616
Test name
Test status
Simulation time 198950153 ps
CPU time 1.44 seconds
Started Apr 21 12:44:12 PM PDT 24
Finished Apr 21 12:44:14 PM PDT 24
Peak memory 209188 kb
Host smart-ce47cacb-e822-469c-a39d-8516096b94ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189469692 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2189469692
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.207995928
Short name T110
Test name
Test status
Simulation time 62994789 ps
CPU time 0.86 seconds
Started Apr 21 12:44:14 PM PDT 24
Finished Apr 21 12:44:15 PM PDT 24
Peak memory 200864 kb
Host smart-344ad08c-8944-4387-abcb-c10bd9e07ce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207995928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.207995928
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.653915714
Short name T112
Test name
Test status
Simulation time 155744308 ps
CPU time 1.27 seconds
Started Apr 21 12:44:00 PM PDT 24
Finished Apr 21 12:44:03 PM PDT 24
Peak memory 200940 kb
Host smart-4f3cc8ad-2497-418b-9d51-eeccf577ec0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653915714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.653915714
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3233807704
Short name T565
Test name
Test status
Simulation time 390912043 ps
CPU time 2.59 seconds
Started Apr 21 12:43:54 PM PDT 24
Finished Apr 21 12:43:57 PM PDT 24
Peak memory 209216 kb
Host smart-9ae504cf-0b4a-4606-be7a-f9a29034d466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233807704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3233807704
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1178905179
Short name T571
Test name
Test status
Simulation time 443125285 ps
CPU time 1.94 seconds
Started Apr 21 12:44:20 PM PDT 24
Finished Apr 21 12:44:22 PM PDT 24
Peak memory 201080 kb
Host smart-c5d822ed-dde9-4710-ab4a-8f1a2b797630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178905179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1178905179
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1795439254
Short name T372
Test name
Test status
Simulation time 74568855 ps
CPU time 0.76 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:01:44 PM PDT 24
Peak memory 200628 kb
Host smart-409e8349-2922-4eb2-8038-569ff20025bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795439254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1795439254
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.237665361
Short name T475
Test name
Test status
Simulation time 1900829275 ps
CPU time 6.64 seconds
Started Apr 21 01:01:44 PM PDT 24
Finished Apr 21 01:01:51 PM PDT 24
Peak memory 221664 kb
Host smart-0711ac26-e682-4889-a4cd-79d369d98bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237665361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.237665361
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4287644395
Short name T139
Test name
Test status
Simulation time 244106299 ps
CPU time 1.2 seconds
Started Apr 21 01:01:40 PM PDT 24
Finished Apr 21 01:01:42 PM PDT 24
Peak memory 218156 kb
Host smart-b884ee69-3959-4fa8-9e59-7bedd10037e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287644395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4287644395
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1939187219
Short name T532
Test name
Test status
Simulation time 119439802 ps
CPU time 0.82 seconds
Started Apr 21 01:01:38 PM PDT 24
Finished Apr 21 01:01:39 PM PDT 24
Peak memory 200680 kb
Host smart-dce66ed5-b516-40e7-a234-01ef548b544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939187219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1939187219
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1351232977
Short name T189
Test name
Test status
Simulation time 975988240 ps
CPU time 4.59 seconds
Started Apr 21 01:01:43 PM PDT 24
Finished Apr 21 01:01:49 PM PDT 24
Peak memory 201004 kb
Host smart-cbeffce7-a667-4eb4-ae8a-7f9336a4898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351232977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1351232977
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2792080602
Short name T81
Test name
Test status
Simulation time 105201477 ps
CPU time 1.02 seconds
Started Apr 21 01:01:38 PM PDT 24
Finished Apr 21 01:01:40 PM PDT 24
Peak memory 200836 kb
Host smart-86c44cb9-5616-4a66-b135-05240e0730e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792080602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2792080602
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1372977489
Short name T187
Test name
Test status
Simulation time 201324574 ps
CPU time 1.4 seconds
Started Apr 21 01:01:40 PM PDT 24
Finished Apr 21 01:01:42 PM PDT 24
Peak memory 200988 kb
Host smart-56fdb55e-94a7-4a62-9ed9-d30397417748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372977489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1372977489
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2767114202
Short name T508
Test name
Test status
Simulation time 3451483204 ps
CPU time 12.91 seconds
Started Apr 21 01:01:38 PM PDT 24
Finished Apr 21 01:01:52 PM PDT 24
Peak memory 201092 kb
Host smart-93668937-0799-486b-b5f4-5ac4c07c1a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767114202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2767114202
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1278082710
Short name T386
Test name
Test status
Simulation time 294083785 ps
CPU time 2.04 seconds
Started Apr 21 01:01:40 PM PDT 24
Finished Apr 21 01:01:43 PM PDT 24
Peak memory 200804 kb
Host smart-8ed314dc-c5f0-4a97-91df-1a9b4161ccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278082710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1278082710
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.133499595
Short name T467
Test name
Test status
Simulation time 185451763 ps
CPU time 1.19 seconds
Started Apr 21 01:01:37 PM PDT 24
Finished Apr 21 01:01:39 PM PDT 24
Peak memory 200788 kb
Host smart-a76deabe-60ed-482f-b297-05b87565cfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133499595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.133499595
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2721174262
Short name T477
Test name
Test status
Simulation time 69238255 ps
CPU time 0.74 seconds
Started Apr 21 01:01:41 PM PDT 24
Finished Apr 21 01:01:42 PM PDT 24
Peak memory 200632 kb
Host smart-fd4ff35a-0cd4-4b3c-bc7a-5d406d09ba8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721174262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2721174262
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2011913706
Short name T33
Test name
Test status
Simulation time 1233632081 ps
CPU time 5.78 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:01:49 PM PDT 24
Peak memory 218692 kb
Host smart-cbfe1714-36aa-4510-b250-139708173043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011913706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2011913706
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1757734315
Short name T137
Test name
Test status
Simulation time 244407296 ps
CPU time 1.03 seconds
Started Apr 21 01:01:40 PM PDT 24
Finished Apr 21 01:01:42 PM PDT 24
Peak memory 218128 kb
Host smart-edabdfbd-9c0f-4e09-a0e5-21f6b283ca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757734315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1757734315
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1450340103
Short name T194
Test name
Test status
Simulation time 936996893 ps
CPU time 4.48 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:01:47 PM PDT 24
Peak memory 200924 kb
Host smart-e464de4a-3eaf-481f-b76e-8facb40ef3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450340103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1450340103
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2413731996
Short name T71
Test name
Test status
Simulation time 17407919080 ps
CPU time 26.12 seconds
Started Apr 21 01:01:40 PM PDT 24
Finished Apr 21 01:02:07 PM PDT 24
Peak memory 218660 kb
Host smart-952e1f9f-ddd9-4e0b-b723-5f01da061c37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413731996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2413731996
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.932898871
Short name T168
Test name
Test status
Simulation time 141611291 ps
CPU time 1.13 seconds
Started Apr 21 01:01:41 PM PDT 24
Finished Apr 21 01:01:43 PM PDT 24
Peak memory 200780 kb
Host smart-733dbcb5-bf7f-4de7-a052-710d512fa482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932898871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.932898871
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1211810916
Short name T387
Test name
Test status
Simulation time 250459395 ps
CPU time 1.46 seconds
Started Apr 21 01:01:38 PM PDT 24
Finished Apr 21 01:01:40 PM PDT 24
Peak memory 201048 kb
Host smart-414b3d7e-2c10-465d-83cb-72693b5e4389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211810916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1211810916
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1733667812
Short name T429
Test name
Test status
Simulation time 9408064552 ps
CPU time 31.57 seconds
Started Apr 21 01:01:41 PM PDT 24
Finished Apr 21 01:02:13 PM PDT 24
Peak memory 201084 kb
Host smart-fcf9245a-7cd4-43f3-ae86-7d3c5cc709aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733667812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1733667812
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.75347507
Short name T458
Test name
Test status
Simulation time 149621042 ps
CPU time 1.05 seconds
Started Apr 21 01:01:40 PM PDT 24
Finished Apr 21 01:01:41 PM PDT 24
Peak memory 200816 kb
Host smart-676e157f-6635-46c2-b3d2-1bf4ac064036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75347507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.75347507
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.261093806
Short name T266
Test name
Test status
Simulation time 81701909 ps
CPU time 0.81 seconds
Started Apr 21 01:01:56 PM PDT 24
Finished Apr 21 01:01:57 PM PDT 24
Peak memory 200608 kb
Host smart-ab8ca4c1-d628-4aaf-b163-5e5a6e568f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261093806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.261093806
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.611494596
Short name T47
Test name
Test status
Simulation time 1224166923 ps
CPU time 5.54 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:02:01 PM PDT 24
Peak memory 222232 kb
Host smart-56ab43fb-b87b-489a-af19-e972466ef5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611494596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.611494596
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.173482019
Short name T159
Test name
Test status
Simulation time 244493150 ps
CPU time 1.04 seconds
Started Apr 21 01:01:54 PM PDT 24
Finished Apr 21 01:01:55 PM PDT 24
Peak memory 218244 kb
Host smart-09e33f16-e742-4eb6-bcb7-3afd3cc75563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173482019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.173482019
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3507245644
Short name T223
Test name
Test status
Simulation time 169951849 ps
CPU time 0.88 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:01:56 PM PDT 24
Peak memory 200568 kb
Host smart-01f833a0-8122-494d-bb7f-6af7e0f9271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507245644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3507245644
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1079197918
Short name T161
Test name
Test status
Simulation time 1746925294 ps
CPU time 6.72 seconds
Started Apr 21 01:01:57 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 200928 kb
Host smart-d0c287bc-fae4-43e6-aceb-69000cbe1c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079197918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1079197918
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2586497695
Short name T282
Test name
Test status
Simulation time 110064078 ps
CPU time 1.18 seconds
Started Apr 21 01:01:56 PM PDT 24
Finished Apr 21 01:01:58 PM PDT 24
Peak memory 201032 kb
Host smart-a272b225-b956-42aa-952e-539318b6712a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586497695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2586497695
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.760988368
Short name T78
Test name
Test status
Simulation time 625156808 ps
CPU time 2.72 seconds
Started Apr 21 01:01:56 PM PDT 24
Finished Apr 21 01:01:59 PM PDT 24
Peak memory 200996 kb
Host smart-386d9f7b-e2c9-4800-905b-bc41a08b6ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760988368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.760988368
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1701301163
Short name T479
Test name
Test status
Simulation time 148828080 ps
CPU time 1.92 seconds
Started Apr 21 01:01:53 PM PDT 24
Finished Apr 21 01:01:56 PM PDT 24
Peak memory 200812 kb
Host smart-5d2fd97a-2ae3-43d5-8382-fe332090be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701301163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1701301163
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.739052555
Short name T511
Test name
Test status
Simulation time 158613161 ps
CPU time 1.06 seconds
Started Apr 21 01:01:56 PM PDT 24
Finished Apr 21 01:01:58 PM PDT 24
Peak memory 200856 kb
Host smart-a69656a7-bab6-4120-8f16-c645aa8283e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739052555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.739052555
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1988722223
Short name T341
Test name
Test status
Simulation time 71493268 ps
CPU time 0.83 seconds
Started Apr 21 01:02:02 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 200628 kb
Host smart-c691838b-c6f2-4ff5-8fa5-1a59bb4ba5a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988722223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1988722223
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1280753728
Short name T31
Test name
Test status
Simulation time 1885804847 ps
CPU time 7.26 seconds
Started Apr 21 01:02:00 PM PDT 24
Finished Apr 21 01:02:08 PM PDT 24
Peak memory 222696 kb
Host smart-d74df002-e0f5-4ae3-93ea-ba263ead5d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280753728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1280753728
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1699295821
Short name T346
Test name
Test status
Simulation time 245402793 ps
CPU time 1.2 seconds
Started Apr 21 01:01:59 PM PDT 24
Finished Apr 21 01:02:01 PM PDT 24
Peak memory 218124 kb
Host smart-3792c7d1-f43b-4bfc-b91b-081c447a904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699295821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1699295821
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1356166164
Short name T439
Test name
Test status
Simulation time 213191722 ps
CPU time 0.92 seconds
Started Apr 21 01:01:56 PM PDT 24
Finished Apr 21 01:01:57 PM PDT 24
Peak memory 200644 kb
Host smart-1900a122-90cc-40b0-a9ff-dc6381067a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356166164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1356166164
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2958123119
Short name T441
Test name
Test status
Simulation time 1611077612 ps
CPU time 6.43 seconds
Started Apr 21 01:02:00 PM PDT 24
Finished Apr 21 01:02:07 PM PDT 24
Peak memory 201012 kb
Host smart-2bef1442-acb9-48c6-9185-77ff60810ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958123119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2958123119
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1822678388
Short name T375
Test name
Test status
Simulation time 149693694 ps
CPU time 1.13 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:02 PM PDT 24
Peak memory 200800 kb
Host smart-f68b18eb-f92d-42b1-8803-98b0247ac1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822678388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1822678388
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.4218902946
Short name T182
Test name
Test status
Simulation time 258453178 ps
CPU time 1.41 seconds
Started Apr 21 01:01:56 PM PDT 24
Finished Apr 21 01:01:58 PM PDT 24
Peak memory 200984 kb
Host smart-fcdd1ba7-3f9a-40a9-aee1-39bb680b5139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218902946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.4218902946
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3672961079
Short name T192
Test name
Test status
Simulation time 334246335 ps
CPU time 2.09 seconds
Started Apr 21 01:01:57 PM PDT 24
Finished Apr 21 01:01:59 PM PDT 24
Peak memory 209036 kb
Host smart-d533d8a3-ff5a-46d0-b3d7-ee845103c15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672961079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3672961079
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3408732110
Short name T435
Test name
Test status
Simulation time 280314716 ps
CPU time 1.42 seconds
Started Apr 21 01:01:58 PM PDT 24
Finished Apr 21 01:02:00 PM PDT 24
Peak memory 200836 kb
Host smart-4e2002d0-ae07-4542-916b-a9a138468446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408732110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3408732110
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2108822808
Short name T308
Test name
Test status
Simulation time 75493121 ps
CPU time 0.79 seconds
Started Apr 21 01:01:58 PM PDT 24
Finished Apr 21 01:01:59 PM PDT 24
Peak memory 200644 kb
Host smart-6ee5f246-57af-4453-928f-227166b49974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108822808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2108822808
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.4013247325
Short name T421
Test name
Test status
Simulation time 1222460042 ps
CPU time 5.53 seconds
Started Apr 21 01:01:57 PM PDT 24
Finished Apr 21 01:02:03 PM PDT 24
Peak memory 217632 kb
Host smart-96190172-33a2-407c-9299-ed34761d6117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013247325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.4013247325
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1509680911
Short name T57
Test name
Test status
Simulation time 245071418 ps
CPU time 1.05 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:01:57 PM PDT 24
Peak memory 218088 kb
Host smart-dc7ad689-a2d7-4adb-8f82-bc53e8ea0b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509680911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1509680911
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2596735375
Short name T493
Test name
Test status
Simulation time 156029411 ps
CPU time 0.91 seconds
Started Apr 21 01:01:56 PM PDT 24
Finished Apr 21 01:01:57 PM PDT 24
Peak memory 200648 kb
Host smart-9a2d531c-b6fd-4599-bdb5-5eefebbfafa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596735375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2596735375
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.995381863
Short name T318
Test name
Test status
Simulation time 1537131369 ps
CPU time 6.51 seconds
Started Apr 21 01:01:58 PM PDT 24
Finished Apr 21 01:02:05 PM PDT 24
Peak memory 200960 kb
Host smart-c45a595e-d4cc-4ce6-985a-0dbc64a1328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995381863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.995381863
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2304486271
Short name T281
Test name
Test status
Simulation time 99440208 ps
CPU time 1.04 seconds
Started Apr 21 01:01:59 PM PDT 24
Finished Apr 21 01:02:01 PM PDT 24
Peak memory 200840 kb
Host smart-26eb7267-af5d-4056-8ab8-3e8416ef9823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304486271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2304486271
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.402050114
Short name T226
Test name
Test status
Simulation time 120528144 ps
CPU time 1.36 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:03 PM PDT 24
Peak memory 201020 kb
Host smart-f453f34c-d70a-4292-8332-4d6b785620ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402050114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.402050114
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1283455804
Short name T84
Test name
Test status
Simulation time 7113046212 ps
CPU time 24.05 seconds
Started Apr 21 01:01:58 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 201020 kb
Host smart-b54233f3-6238-4080-ad1a-952225e38f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283455804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1283455804
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2220900517
Short name T241
Test name
Test status
Simulation time 114331056 ps
CPU time 1.56 seconds
Started Apr 21 01:02:00 PM PDT 24
Finished Apr 21 01:02:02 PM PDT 24
Peak memory 200828 kb
Host smart-8ca8e4b6-79ba-4d02-9c95-ff34dde9dcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220900517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2220900517
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3380851248
Short name T445
Test name
Test status
Simulation time 149908669 ps
CPU time 1.25 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:01:56 PM PDT 24
Peak memory 200824 kb
Host smart-4a4e33b4-707d-4bdd-89c2-288ff0905be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380851248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3380851248
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.74373476
Short name T452
Test name
Test status
Simulation time 62159614 ps
CPU time 0.75 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200580 kb
Host smart-a4c2a2ee-0252-4db5-ac8a-23b82e370151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74373476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.74373476
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3364174265
Short name T48
Test name
Test status
Simulation time 1225704561 ps
CPU time 5.87 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:07 PM PDT 24
Peak memory 217508 kb
Host smart-4cb92771-40c5-46e8-9fe3-5bdc6a72097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364174265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3364174265
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2268614781
Short name T450
Test name
Test status
Simulation time 243787557 ps
CPU time 1.13 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:05 PM PDT 24
Peak memory 218140 kb
Host smart-fea2f41c-77b5-4d47-a5a7-e6b44349367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268614781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2268614781
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2565935069
Short name T8
Test name
Test status
Simulation time 103205153 ps
CPU time 0.73 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:01:56 PM PDT 24
Peak memory 200632 kb
Host smart-a434f2d7-a610-43c4-8e2c-59bded4b8768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565935069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2565935069
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1112940847
Short name T252
Test name
Test status
Simulation time 1141921163 ps
CPU time 4.68 seconds
Started Apr 21 01:01:59 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 200984 kb
Host smart-48a68423-eb8d-4e0a-83ca-03f74e03fe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112940847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1112940847
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4058631799
Short name T350
Test name
Test status
Simulation time 109232649 ps
CPU time 0.99 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 200788 kb
Host smart-8662fb97-4831-43e5-acee-a9a7fd9c6324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058631799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4058631799
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1939528400
Short name T332
Test name
Test status
Simulation time 195904387 ps
CPU time 1.45 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:05 PM PDT 24
Peak memory 200992 kb
Host smart-e47d3b84-82f4-4e48-8b93-59d0cbf560ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939528400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1939528400
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2209456282
Short name T87
Test name
Test status
Simulation time 10387355022 ps
CPU time 36.7 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:41 PM PDT 24
Peak memory 209316 kb
Host smart-ee4d4771-a4c2-4604-8d47-ff27e813edaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209456282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2209456282
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.4029493233
Short name T342
Test name
Test status
Simulation time 492500740 ps
CPU time 2.75 seconds
Started Apr 21 01:01:58 PM PDT 24
Finished Apr 21 01:02:01 PM PDT 24
Peak memory 209220 kb
Host smart-88e002f4-894d-4782-8f95-492938e835c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029493233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.4029493233
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2970649640
Short name T304
Test name
Test status
Simulation time 84147317 ps
CPU time 0.79 seconds
Started Apr 21 01:02:07 PM PDT 24
Finished Apr 21 01:02:09 PM PDT 24
Peak memory 200784 kb
Host smart-960d1704-1d11-40d9-bfc7-587027df5a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970649640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2970649640
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1663665146
Short name T507
Test name
Test status
Simulation time 75327747 ps
CPU time 0.8 seconds
Started Apr 21 01:02:04 PM PDT 24
Finished Apr 21 01:02:05 PM PDT 24
Peak memory 200636 kb
Host smart-9c20269a-9f54-439b-8197-1f81cb4e33c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663665146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1663665146
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1901907991
Short name T313
Test name
Test status
Simulation time 2355344912 ps
CPU time 8.15 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 222764 kb
Host smart-46fc20da-7123-4a36-9622-ded79e24268b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901907991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1901907991
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3899301121
Short name T393
Test name
Test status
Simulation time 244370274 ps
CPU time 1.17 seconds
Started Apr 21 01:02:04 PM PDT 24
Finished Apr 21 01:02:06 PM PDT 24
Peak memory 218312 kb
Host smart-e4d53ed4-386e-4aa3-939d-083d2d48a824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899301121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3899301121
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1167199226
Short name T296
Test name
Test status
Simulation time 169230527 ps
CPU time 0.9 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:03 PM PDT 24
Peak memory 200660 kb
Host smart-e037011d-7467-4424-8ed7-b045cd901884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167199226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1167199226
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3669352733
Short name T228
Test name
Test status
Simulation time 1294996971 ps
CPU time 5.26 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:07 PM PDT 24
Peak memory 201012 kb
Host smart-f3355623-e60e-4dee-9627-c7f074201cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669352733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3669352733
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1237627159
Short name T480
Test name
Test status
Simulation time 94696071 ps
CPU time 1.03 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:02 PM PDT 24
Peak memory 200800 kb
Host smart-99249a37-65f9-4194-b2c2-802fecd76795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237627159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1237627159
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1238787048
Short name T512
Test name
Test status
Simulation time 10649245241 ps
CPU time 36.46 seconds
Started Apr 21 01:02:00 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 209248 kb
Host smart-128ade62-3791-4291-8a37-7ac1750b82bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238787048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1238787048
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1505938392
Short name T398
Test name
Test status
Simulation time 153566817 ps
CPU time 1.82 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 200776 kb
Host smart-31032a0e-017e-4edd-ad5c-6700ff6f594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505938392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1505938392
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.762677345
Short name T148
Test name
Test status
Simulation time 162611035 ps
CPU time 1.15 seconds
Started Apr 21 01:01:58 PM PDT 24
Finished Apr 21 01:01:59 PM PDT 24
Peak memory 201016 kb
Host smart-09f06ba2-3d1c-4cc8-ba23-1062259c081c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762677345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.762677345
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.4143937116
Short name T327
Test name
Test status
Simulation time 64615938 ps
CPU time 0.77 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 200592 kb
Host smart-0468c2a7-34ba-49d5-b54c-bb08031b73d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143937116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.4143937116
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1059482346
Short name T354
Test name
Test status
Simulation time 1228463702 ps
CPU time 6.09 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:09 PM PDT 24
Peak memory 218008 kb
Host smart-bcdb0ff2-f73f-4b9c-867b-cae5f83f38ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059482346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1059482346
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2096954839
Short name T220
Test name
Test status
Simulation time 244650112 ps
CPU time 1.04 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:05 PM PDT 24
Peak memory 218124 kb
Host smart-022cd029-cae3-45b7-9592-c0a8038fdbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096954839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2096954839
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.663093624
Short name T424
Test name
Test status
Simulation time 114955571 ps
CPU time 0.76 seconds
Started Apr 21 01:01:58 PM PDT 24
Finished Apr 21 01:02:00 PM PDT 24
Peak memory 200640 kb
Host smart-3645b60b-4251-42a2-a0a3-13194bd8df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663093624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.663093624
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2070277191
Short name T103
Test name
Test status
Simulation time 1055797898 ps
CPU time 5.03 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:08 PM PDT 24
Peak memory 201000 kb
Host smart-783724c1-bb96-4dcf-a575-998e7641eb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070277191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2070277191
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1460677597
Short name T383
Test name
Test status
Simulation time 142650561 ps
CPU time 1.11 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200788 kb
Host smart-94954225-4cff-446f-8aad-fd0775ec7437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460677597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1460677597
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.442828758
Short name T360
Test name
Test status
Simulation time 201998997 ps
CPU time 1.33 seconds
Started Apr 21 01:01:58 PM PDT 24
Finished Apr 21 01:01:59 PM PDT 24
Peak memory 201020 kb
Host smart-a2883c81-bd77-4d16-991c-5bca2398a962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442828758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.442828758
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3254603355
Short name T323
Test name
Test status
Simulation time 348916150 ps
CPU time 2.26 seconds
Started Apr 21 01:01:58 PM PDT 24
Finished Apr 21 01:02:01 PM PDT 24
Peak memory 200824 kb
Host smart-7bc5c7ec-e78f-42b7-9cc3-d1ed7cb9cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254603355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3254603355
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3973318023
Short name T247
Test name
Test status
Simulation time 72290996 ps
CPU time 0.8 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 200780 kb
Host smart-1e015a15-2756-4e3c-a8b5-66c07909d786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973318023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3973318023
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2828463614
Short name T211
Test name
Test status
Simulation time 101249068 ps
CPU time 0.84 seconds
Started Apr 21 01:02:05 PM PDT 24
Finished Apr 21 01:02:06 PM PDT 24
Peak memory 200616 kb
Host smart-a6cda4cd-5283-495f-a6a6-2710e0cafb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828463614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2828463614
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2977181147
Short name T209
Test name
Test status
Simulation time 1913930337 ps
CPU time 7.49 seconds
Started Apr 21 01:02:02 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 218100 kb
Host smart-70b3c1d9-b81f-49ea-a146-ba7067e93820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977181147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2977181147
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1403712242
Short name T141
Test name
Test status
Simulation time 243824098 ps
CPU time 1.09 seconds
Started Apr 21 01:02:46 PM PDT 24
Finished Apr 21 01:02:47 PM PDT 24
Peak memory 218116 kb
Host smart-ffb366e0-f247-4ba2-a283-9a601ac63cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403712242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1403712242
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2142873733
Short name T343
Test name
Test status
Simulation time 198945415 ps
CPU time 0.87 seconds
Started Apr 21 01:02:02 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 200584 kb
Host smart-d7ea0f88-0db9-4908-940a-372abf2f99f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142873733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2142873733
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.482774249
Short name T461
Test name
Test status
Simulation time 852410373 ps
CPU time 4.28 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:06 PM PDT 24
Peak memory 201188 kb
Host smart-d97bea5c-dcf2-41f9-95a3-ca46377646ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482774249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.482774249
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.292802515
Short name T353
Test name
Test status
Simulation time 99574338 ps
CPU time 0.96 seconds
Started Apr 21 01:02:02 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 200828 kb
Host smart-5f882d7d-8d9a-46fd-8a28-6a157ca18e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292802515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.292802515
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2700704931
Short name T167
Test name
Test status
Simulation time 201120139 ps
CPU time 1.35 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:05 PM PDT 24
Peak memory 201024 kb
Host smart-bd5f3338-5d7d-46af-8c35-0b10213e34f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700704931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2700704931
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.247969279
Short name T514
Test name
Test status
Simulation time 4455781990 ps
CPU time 21.12 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:24 PM PDT 24
Peak memory 209296 kb
Host smart-8d771f0c-5c7c-472e-91b6-33276acda3e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247969279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.247969279
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2664517706
Short name T336
Test name
Test status
Simulation time 152245679 ps
CPU time 1.84 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:05 PM PDT 24
Peak memory 200740 kb
Host smart-ff47a5dd-1ead-4031-a5b9-364332a5c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664517706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2664517706
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3417430510
Short name T214
Test name
Test status
Simulation time 69291078 ps
CPU time 0.78 seconds
Started Apr 21 01:02:02 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 200624 kb
Host smart-b3c530bf-e82f-40a5-854d-efefbea7c5fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417430510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3417430510
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2782558495
Short name T39
Test name
Test status
Simulation time 2360588614 ps
CPU time 8.12 seconds
Started Apr 21 01:02:04 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 222496 kb
Host smart-54abc12a-df54-4db6-9df7-5f14bab3313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782558495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2782558495
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2011723357
Short name T196
Test name
Test status
Simulation time 244662254 ps
CPU time 1.07 seconds
Started Apr 21 01:02:02 PM PDT 24
Finished Apr 21 01:02:03 PM PDT 24
Peak memory 218084 kb
Host smart-d8655f70-646e-4045-9d24-9353e0435b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011723357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2011723357
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4032274131
Short name T261
Test name
Test status
Simulation time 86980919 ps
CPU time 0.78 seconds
Started Apr 21 01:02:04 PM PDT 24
Finished Apr 21 01:02:05 PM PDT 24
Peak memory 200572 kb
Host smart-a52e01b1-b25d-4ad5-b621-88dfd4c8ea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032274131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4032274131
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3740425893
Short name T443
Test name
Test status
Simulation time 1457509143 ps
CPU time 5.92 seconds
Started Apr 21 01:02:04 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200984 kb
Host smart-fd6d2074-88f4-492c-98ae-2a2862ffaba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740425893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3740425893
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.519946782
Short name T279
Test name
Test status
Simulation time 144208002 ps
CPU time 1.13 seconds
Started Apr 21 01:02:05 PM PDT 24
Finished Apr 21 01:02:07 PM PDT 24
Peak memory 200820 kb
Host smart-e7619734-7532-478d-82cb-dbd54b6c5ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519946782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.519946782
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1566382829
Short name T280
Test name
Test status
Simulation time 125446524 ps
CPU time 1.39 seconds
Started Apr 21 01:02:07 PM PDT 24
Finished Apr 21 01:02:09 PM PDT 24
Peak memory 200992 kb
Host smart-11c3f22f-7ea5-40be-9b69-0c8ab4999d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566382829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1566382829
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.814771945
Short name T54
Test name
Test status
Simulation time 3976683180 ps
CPU time 20.61 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:31 PM PDT 24
Peak memory 209320 kb
Host smart-bbf38825-25de-45f9-8864-1cef7409123e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814771945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.814771945
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2757644802
Short name T438
Test name
Test status
Simulation time 331941233 ps
CPU time 2.26 seconds
Started Apr 21 01:02:06 PM PDT 24
Finished Apr 21 01:02:09 PM PDT 24
Peak memory 200816 kb
Host smart-3e9d685b-0640-4721-ba13-76d0760fc276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757644802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2757644802
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2631932779
Short name T249
Test name
Test status
Simulation time 163871464 ps
CPU time 1.09 seconds
Started Apr 21 01:02:07 PM PDT 24
Finished Apr 21 01:02:09 PM PDT 24
Peak memory 200780 kb
Host smart-8b43011f-ac14-4013-928a-94b1df64bdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631932779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2631932779
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.240197136
Short name T520
Test name
Test status
Simulation time 149731963 ps
CPU time 1.05 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 200560 kb
Host smart-b16a9806-8b22-47f2-abe6-deec011fc65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240197136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.240197136
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3720569063
Short name T53
Test name
Test status
Simulation time 2379393004 ps
CPU time 8.01 seconds
Started Apr 21 01:02:06 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 222740 kb
Host smart-f6dff655-ae11-435a-98e2-4b25b73a05be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720569063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3720569063
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4272852125
Short name T370
Test name
Test status
Simulation time 244113715 ps
CPU time 1.09 seconds
Started Apr 21 01:02:06 PM PDT 24
Finished Apr 21 01:02:08 PM PDT 24
Peak memory 218116 kb
Host smart-a2257e90-0f89-46ac-bef4-bf8f8e3be0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272852125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4272852125
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1067366977
Short name T294
Test name
Test status
Simulation time 187164321 ps
CPU time 0.88 seconds
Started Apr 21 01:02:03 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 200644 kb
Host smart-b535a54b-d08f-4ac6-a95b-14a90fc92512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067366977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1067366977
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.4101828267
Short name T454
Test name
Test status
Simulation time 1495672199 ps
CPU time 5.53 seconds
Started Apr 21 01:02:06 PM PDT 24
Finished Apr 21 01:02:13 PM PDT 24
Peak memory 201164 kb
Host smart-946dfca3-6348-4213-9f03-28aa29031dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101828267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.4101828267
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1389377498
Short name T13
Test name
Test status
Simulation time 98828056 ps
CPU time 0.99 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200804 kb
Host smart-2e39c5ab-5a79-4742-8da6-98c1d9d96b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389377498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1389377498
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1726809795
Short name T310
Test name
Test status
Simulation time 198832935 ps
CPU time 1.29 seconds
Started Apr 21 01:02:01 PM PDT 24
Finished Apr 21 01:02:03 PM PDT 24
Peak memory 200988 kb
Host smart-69fcb6dd-74a0-4d44-9713-0e35120049f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726809795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1726809795
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.831575580
Short name T340
Test name
Test status
Simulation time 3481512385 ps
CPU time 12.62 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:21 PM PDT 24
Peak memory 209276 kb
Host smart-66927826-4a15-40cb-a41b-2b2ea10b2ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831575580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.831575580
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1066673154
Short name T63
Test name
Test status
Simulation time 309331711 ps
CPU time 2.14 seconds
Started Apr 21 01:02:10 PM PDT 24
Finished Apr 21 01:02:13 PM PDT 24
Peak memory 208552 kb
Host smart-3096de3c-85b4-47e1-a976-0d4e525edd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066673154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1066673154
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.4189070076
Short name T300
Test name
Test status
Simulation time 175696978 ps
CPU time 1.35 seconds
Started Apr 21 01:02:06 PM PDT 24
Finished Apr 21 01:02:07 PM PDT 24
Peak memory 200744 kb
Host smart-d5100632-d2cd-4b0d-b637-c10f10956e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189070076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4189070076
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2646783273
Short name T277
Test name
Test status
Simulation time 66524875 ps
CPU time 0.77 seconds
Started Apr 21 01:02:06 PM PDT 24
Finished Apr 21 01:02:07 PM PDT 24
Peak memory 200628 kb
Host smart-501966fb-75bc-427f-a3a0-ef44acd08290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646783273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2646783273
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.520182666
Short name T468
Test name
Test status
Simulation time 1908762156 ps
CPU time 7.01 seconds
Started Apr 21 01:02:05 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 218672 kb
Host smart-0470198f-22ef-41a7-b6d9-c9f79f818cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520182666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.520182666
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2634337342
Short name T307
Test name
Test status
Simulation time 244527368 ps
CPU time 1.11 seconds
Started Apr 21 01:02:05 PM PDT 24
Finished Apr 21 01:02:06 PM PDT 24
Peak memory 218084 kb
Host smart-137e0cec-40a8-4e0f-930f-00340ff78440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634337342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2634337342
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3374048967
Short name T344
Test name
Test status
Simulation time 160320525 ps
CPU time 0.82 seconds
Started Apr 21 01:02:07 PM PDT 24
Finished Apr 21 01:02:08 PM PDT 24
Peak memory 200572 kb
Host smart-bd46f2b5-a472-40ef-a8f1-14cb1fab2fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374048967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3374048967
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3640787510
Short name T105
Test name
Test status
Simulation time 821622184 ps
CPU time 4.15 seconds
Started Apr 21 01:02:05 PM PDT 24
Finished Apr 21 01:02:09 PM PDT 24
Peak memory 201020 kb
Host smart-969c8f6a-dbfb-48d5-9d64-4f3ef5a1db3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640787510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3640787510
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2859878553
Short name T533
Test name
Test status
Simulation time 109862011 ps
CPU time 1.02 seconds
Started Apr 21 01:02:10 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 200756 kb
Host smart-472fefdd-2b4a-44a8-b0ce-9e0f27e4162a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859878553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2859878553
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.623237936
Short name T129
Test name
Test status
Simulation time 229821135 ps
CPU time 1.37 seconds
Started Apr 21 01:02:06 PM PDT 24
Finished Apr 21 01:02:08 PM PDT 24
Peak memory 200996 kb
Host smart-7ee54135-99b8-44f2-9120-32d9f5bd2f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623237936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.623237936
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3506305204
Short name T24
Test name
Test status
Simulation time 6430379816 ps
CPU time 25.93 seconds
Started Apr 21 01:02:07 PM PDT 24
Finished Apr 21 01:02:34 PM PDT 24
Peak memory 201080 kb
Host smart-325f28ee-0e0f-4398-93a7-e5a9c13a6d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506305204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3506305204
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.532109917
Short name T198
Test name
Test status
Simulation time 298322405 ps
CPU time 1.97 seconds
Started Apr 21 01:02:05 PM PDT 24
Finished Apr 21 01:02:07 PM PDT 24
Peak memory 200752 kb
Host smart-5c10ccff-5764-401e-a447-89e293f5fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532109917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.532109917
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3304838660
Short name T151
Test name
Test status
Simulation time 131940194 ps
CPU time 1.13 seconds
Started Apr 21 01:02:04 PM PDT 24
Finished Apr 21 01:02:06 PM PDT 24
Peak memory 200808 kb
Host smart-061f579a-2e27-4896-a4c2-2a953d6cb027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304838660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3304838660
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3084008728
Short name T537
Test name
Test status
Simulation time 85993673 ps
CPU time 0.8 seconds
Started Apr 21 01:01:39 PM PDT 24
Finished Apr 21 01:01:40 PM PDT 24
Peak memory 200624 kb
Host smart-8597664e-eecb-4d3d-aea2-34e64e84164e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084008728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3084008728
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3275945917
Short name T302
Test name
Test status
Simulation time 2171765960 ps
CPU time 8.62 seconds
Started Apr 21 01:01:44 PM PDT 24
Finished Apr 21 01:01:53 PM PDT 24
Peak memory 218160 kb
Host smart-2d39d08f-dee5-47a1-9bd9-2e4c1cc45db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275945917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3275945917
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1527946449
Short name T213
Test name
Test status
Simulation time 243902972 ps
CPU time 1.05 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:01:44 PM PDT 24
Peak memory 218260 kb
Host smart-83b2c12e-3c49-4b5a-9c7f-e34c91740c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527946449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1527946449
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2203344084
Short name T245
Test name
Test status
Simulation time 202703872 ps
CPU time 0.93 seconds
Started Apr 21 01:01:41 PM PDT 24
Finished Apr 21 01:01:43 PM PDT 24
Peak memory 200572 kb
Host smart-4a9fa4a6-e547-49ee-aacd-8cfc37c56259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203344084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2203344084
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2307920621
Short name T35
Test name
Test status
Simulation time 1518011243 ps
CPU time 5.85 seconds
Started Apr 21 01:01:43 PM PDT 24
Finished Apr 21 01:01:50 PM PDT 24
Peak memory 201004 kb
Host smart-83515d4f-3bca-4c1e-a734-4bbff3d6727c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307920621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2307920621
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2913982801
Short name T70
Test name
Test status
Simulation time 8293629401 ps
CPU time 13.28 seconds
Started Apr 21 01:01:43 PM PDT 24
Finished Apr 21 01:01:57 PM PDT 24
Peak memory 217668 kb
Host smart-faa34a62-8684-4a66-b512-206e8a4957e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913982801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2913982801
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.306536702
Short name T143
Test name
Test status
Simulation time 111287266 ps
CPU time 1.09 seconds
Started Apr 21 01:01:39 PM PDT 24
Finished Apr 21 01:01:41 PM PDT 24
Peak memory 200796 kb
Host smart-63a4af90-b2d8-4c77-94b3-fdbe8c5ca314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306536702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.306536702
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.887289651
Short name T273
Test name
Test status
Simulation time 193748983 ps
CPU time 1.36 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:01:45 PM PDT 24
Peak memory 200924 kb
Host smart-ddcb86af-e67a-4824-abdf-d8f711d7022d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887289651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.887289651
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2323235250
Short name T399
Test name
Test status
Simulation time 4017972649 ps
CPU time 13.08 seconds
Started Apr 21 01:01:40 PM PDT 24
Finished Apr 21 01:01:54 PM PDT 24
Peak memory 201036 kb
Host smart-a7d832c9-2164-4164-a93c-f1bccaa5d496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323235250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2323235250
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3593759155
Short name T505
Test name
Test status
Simulation time 124699445 ps
CPU time 1.65 seconds
Started Apr 21 01:01:43 PM PDT 24
Finished Apr 21 01:01:45 PM PDT 24
Peak memory 208968 kb
Host smart-c7fcf46a-4dbd-49e8-90a4-b7ce0967ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593759155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3593759155
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3285280524
Short name T490
Test name
Test status
Simulation time 82906410 ps
CPU time 0.86 seconds
Started Apr 21 01:01:40 PM PDT 24
Finished Apr 21 01:01:41 PM PDT 24
Peak memory 200832 kb
Host smart-541cca7f-bb6b-4f52-817c-47192bcfc63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285280524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3285280524
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3360435984
Short name T526
Test name
Test status
Simulation time 64022291 ps
CPU time 0.74 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200664 kb
Host smart-095c1029-ddda-4611-8de0-1ae15a05ce14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360435984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3360435984
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3218655830
Short name T40
Test name
Test status
Simulation time 1881328641 ps
CPU time 7.13 seconds
Started Apr 21 01:02:11 PM PDT 24
Finished Apr 21 01:02:19 PM PDT 24
Peak memory 218048 kb
Host smart-b05a9c3d-d3a1-4b5f-9473-c1d7aa4e0414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218655830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3218655830
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2598789215
Short name T265
Test name
Test status
Simulation time 244328150 ps
CPU time 1.08 seconds
Started Apr 21 01:02:10 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 218164 kb
Host smart-b2618e01-4173-4ced-8968-02b36e9246d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598789215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2598789215
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2442640283
Short name T288
Test name
Test status
Simulation time 147731847 ps
CPU time 0.84 seconds
Started Apr 21 01:02:07 PM PDT 24
Finished Apr 21 01:02:09 PM PDT 24
Peak memory 200656 kb
Host smart-d9c59a2e-2aab-4e19-aec7-c3edbe5efac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442640283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2442640283
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.287468674
Short name T229
Test name
Test status
Simulation time 965242986 ps
CPU time 5.11 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:13 PM PDT 24
Peak memory 201028 kb
Host smart-60a5293c-849b-426c-b695-bb4d6943df1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287468674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.287468674
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.539211750
Short name T303
Test name
Test status
Simulation time 108618166 ps
CPU time 1.08 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 200756 kb
Host smart-7c6a2a72-524b-47e1-a033-f9c13c9ff04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539211750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.539211750
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.894093589
Short name T453
Test name
Test status
Simulation time 192899535 ps
CPU time 1.31 seconds
Started Apr 21 01:02:07 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 200980 kb
Host smart-6b0c97f5-89b8-49c3-9e47-9f8008507b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894093589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.894093589
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.696680977
Short name T158
Test name
Test status
Simulation time 133481432 ps
CPU time 1.76 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 209060 kb
Host smart-80a155c3-b97c-4de2-918d-0979de70fe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696680977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.696680977
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3158995889
Short name T425
Test name
Test status
Simulation time 65361251 ps
CPU time 0.79 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 200860 kb
Host smart-7aa92248-d403-4fb6-8257-2f52446d0642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158995889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3158995889
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3003546400
Short name T371
Test name
Test status
Simulation time 90574929 ps
CPU time 0.79 seconds
Started Apr 21 01:02:10 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 200592 kb
Host smart-23ba1268-8bd9-47b5-ba93-a8b212e5a8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003546400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3003546400
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1672531519
Short name T460
Test name
Test status
Simulation time 1216549253 ps
CPU time 5.73 seconds
Started Apr 21 01:02:14 PM PDT 24
Finished Apr 21 01:02:20 PM PDT 24
Peak memory 222692 kb
Host smart-5f299059-154d-4675-99b7-0eea3a9fd46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672531519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1672531519
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1259324663
Short name T3
Test name
Test status
Simulation time 244281837 ps
CPU time 1.16 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 218184 kb
Host smart-f7b7892a-181c-4aaf-aea9-c98e01b162ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259324663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1259324663
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2876766633
Short name T19
Test name
Test status
Simulation time 173813877 ps
CPU time 0.92 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:10 PM PDT 24
Peak memory 200660 kb
Host smart-28a2605f-f470-4e50-8a27-cedc648dbf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876766633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2876766633
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.976713353
Short name T126
Test name
Test status
Simulation time 1590302839 ps
CPU time 5.72 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 200996 kb
Host smart-134abaff-141c-4ba9-8c3e-772414b40322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976713353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.976713353
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1469390310
Short name T433
Test name
Test status
Simulation time 153164893 ps
CPU time 1.24 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 200752 kb
Host smart-26119823-cc45-4ad5-9139-8112709fd862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469390310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1469390310
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2318993395
Short name T86
Test name
Test status
Simulation time 187653509 ps
CPU time 1.37 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 201012 kb
Host smart-c81f881a-f17b-40d8-9fef-5e688cd85045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318993395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2318993395
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2586562569
Short name T122
Test name
Test status
Simulation time 2553295470 ps
CPU time 8.66 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:17 PM PDT 24
Peak memory 201036 kb
Host smart-c0e6bdee-3671-4c67-a7a0-ba5f44ef993e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586562569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2586562569
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3138646031
Short name T314
Test name
Test status
Simulation time 382870550 ps
CPU time 2.07 seconds
Started Apr 21 01:02:11 PM PDT 24
Finished Apr 21 01:02:13 PM PDT 24
Peak memory 200860 kb
Host smart-8f7ba464-0a15-45f4-8416-cb9de590cc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138646031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3138646031
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.993075334
Short name T55
Test name
Test status
Simulation time 75357785 ps
CPU time 0.81 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200836 kb
Host smart-406160d2-1904-4d51-8063-94fb66b36aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993075334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.993075334
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.842187668
Short name T412
Test name
Test status
Simulation time 87782966 ps
CPU time 0.79 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200640 kb
Host smart-8c7cb55f-bc7f-4616-8d19-0d40eb47c498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842187668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.842187668
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3529826173
Short name T436
Test name
Test status
Simulation time 243917212 ps
CPU time 1.17 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 218184 kb
Host smart-cc0646bc-4ca1-48e3-9854-2cd9e2cb7235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529826173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3529826173
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4023856752
Short name T238
Test name
Test status
Simulation time 83707382 ps
CPU time 0.8 seconds
Started Apr 21 01:02:11 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 200684 kb
Host smart-17355e12-3bb4-462c-98eb-0ec62ca66db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023856752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4023856752
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2177810110
Short name T195
Test name
Test status
Simulation time 1154577411 ps
CPU time 5.12 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 201036 kb
Host smart-93002752-17c7-4dd6-ab0a-e7b7ce44f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177810110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2177810110
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2652335747
Short name T416
Test name
Test status
Simulation time 158357399 ps
CPU time 1.18 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200844 kb
Host smart-04f026a2-6c27-4f0e-acab-c924317d4e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652335747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2652335747
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3716943293
Short name T38
Test name
Test status
Simulation time 227272770 ps
CPU time 1.49 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 201000 kb
Host smart-c7730b2a-8702-43c2-99fb-169d6b0498db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716943293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3716943293
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3476576943
Short name T462
Test name
Test status
Simulation time 1093789556 ps
CPU time 5.96 seconds
Started Apr 21 01:02:12 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 210232 kb
Host smart-d7b47624-a459-4b9f-b3a2-60350a1971f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476576943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3476576943
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2316240453
Short name T363
Test name
Test status
Simulation time 145493250 ps
CPU time 1.81 seconds
Started Apr 21 01:02:12 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 200744 kb
Host smart-c1feeccb-c0c4-4253-a74a-1393b6a16d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316240453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2316240453
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2813777903
Short name T521
Test name
Test status
Simulation time 243289078 ps
CPU time 1.48 seconds
Started Apr 21 01:02:14 PM PDT 24
Finished Apr 21 01:02:17 PM PDT 24
Peak memory 200820 kb
Host smart-cb88e185-3a5a-4145-acdb-42960690ead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813777903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2813777903
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3199041030
Short name T177
Test name
Test status
Simulation time 87114521 ps
CPU time 0.84 seconds
Started Apr 21 01:02:19 PM PDT 24
Finished Apr 21 01:02:20 PM PDT 24
Peak memory 200632 kb
Host smart-485905c9-950b-40f0-8779-a0130eb7e758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199041030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3199041030
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.841538053
Short name T42
Test name
Test status
Simulation time 2173259171 ps
CPU time 8.42 seconds
Started Apr 21 01:02:14 PM PDT 24
Finished Apr 21 01:02:23 PM PDT 24
Peak memory 218700 kb
Host smart-8b491ceb-280d-4f6c-b78d-824e23fdd08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841538053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.841538053
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.595941006
Short name T140
Test name
Test status
Simulation time 248125288 ps
CPU time 1.04 seconds
Started Apr 21 01:02:12 PM PDT 24
Finished Apr 21 01:02:14 PM PDT 24
Peak memory 218148 kb
Host smart-096a2092-b797-440c-9525-e2de212a6369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595941006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.595941006
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.463029022
Short name T301
Test name
Test status
Simulation time 98647040 ps
CPU time 0.75 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200640 kb
Host smart-dd5b15c2-1bd0-429a-950b-3faa7e9568aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463029022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.463029022
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1173796224
Short name T4
Test name
Test status
Simulation time 1832715310 ps
CPU time 6.64 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:20 PM PDT 24
Peak memory 201000 kb
Host smart-5c809808-1ef0-4c49-8412-0f19209e2e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173796224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1173796224
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2007722236
Short name T483
Test name
Test status
Simulation time 183230773 ps
CPU time 1.17 seconds
Started Apr 21 01:02:12 PM PDT 24
Finished Apr 21 01:02:14 PM PDT 24
Peak memory 200836 kb
Host smart-8ab4d4d8-33e1-45b2-b4af-fe1e91aa5d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007722236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2007722236
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.4161328451
Short name T465
Test name
Test status
Simulation time 117284488 ps
CPU time 1.17 seconds
Started Apr 21 01:02:12 PM PDT 24
Finished Apr 21 01:02:14 PM PDT 24
Peak memory 200932 kb
Host smart-0c5c6e98-b46a-495f-982d-155018ab8493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161328451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4161328451
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2126907012
Short name T108
Test name
Test status
Simulation time 8113383847 ps
CPU time 30.12 seconds
Started Apr 21 01:02:10 PM PDT 24
Finished Apr 21 01:02:41 PM PDT 24
Peak memory 201048 kb
Host smart-2fa498d8-6906-40a8-a92f-8e63777e892b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126907012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2126907012
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.919250070
Short name T440
Test name
Test status
Simulation time 338041589 ps
CPU time 2.22 seconds
Started Apr 21 01:02:08 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200812 kb
Host smart-c2ea4d8d-428b-455c-a9c4-1abf7642a958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919250070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.919250070
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.592702919
Short name T215
Test name
Test status
Simulation time 85957195 ps
CPU time 0.88 seconds
Started Apr 21 01:02:11 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 200872 kb
Host smart-81b0e9ed-611e-40bf-a181-6e41d875a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592702919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.592702919
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.563181817
Short name T28
Test name
Test status
Simulation time 2348962161 ps
CPU time 7.77 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 218680 kb
Host smart-27301f3f-b6c0-42da-902f-d0b0799491c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563181817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.563181817
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.756195033
Short name T222
Test name
Test status
Simulation time 243915483 ps
CPU time 1.07 seconds
Started Apr 21 01:02:20 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 218120 kb
Host smart-13b51651-737d-41c9-90c8-18233f285cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756195033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.756195033
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1096114275
Short name T345
Test name
Test status
Simulation time 77035358 ps
CPU time 0.71 seconds
Started Apr 21 01:02:09 PM PDT 24
Finished Apr 21 01:02:11 PM PDT 24
Peak memory 200636 kb
Host smart-56b39ae8-03eb-45fe-8366-6e0d46fdeb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096114275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1096114275
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1063077469
Short name T476
Test name
Test status
Simulation time 1987833980 ps
CPU time 7.04 seconds
Started Apr 21 01:02:11 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 201016 kb
Host smart-620ff6bb-876d-4620-89d4-55717f4a5975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063077469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1063077469
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1401476257
Short name T136
Test name
Test status
Simulation time 143861204 ps
CPU time 1.06 seconds
Started Apr 21 01:02:15 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 200832 kb
Host smart-f69e54ca-e228-4804-8516-825abba93e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401476257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1401476257
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.105388722
Short name T157
Test name
Test status
Simulation time 114898474 ps
CPU time 1.19 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 201012 kb
Host smart-b3fd90f6-44bf-482c-a3fe-021729c169ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105388722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.105388722
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.264133987
Short name T102
Test name
Test status
Simulation time 4279391141 ps
CPU time 18.29 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:40 PM PDT 24
Peak memory 209320 kb
Host smart-812bf6f8-e619-4e64-bda3-87d3110e6b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264133987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.264133987
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1949979395
Short name T186
Test name
Test status
Simulation time 371117017 ps
CPU time 2.1 seconds
Started Apr 21 01:02:11 PM PDT 24
Finished Apr 21 01:02:14 PM PDT 24
Peak memory 200828 kb
Host smart-67ee418a-4c37-453f-a532-e73fbf92db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949979395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1949979395
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3868392298
Short name T417
Test name
Test status
Simulation time 91953750 ps
CPU time 0.91 seconds
Started Apr 21 01:02:16 PM PDT 24
Finished Apr 21 01:02:17 PM PDT 24
Peak memory 200812 kb
Host smart-f30975fb-ecd8-412d-be94-f97c2da6b7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868392298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3868392298
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2666203232
Short name T73
Test name
Test status
Simulation time 65985576 ps
CPU time 0.76 seconds
Started Apr 21 01:02:10 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 200668 kb
Host smart-c25ed6de-3288-40d7-9f79-e06d55c267f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666203232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2666203232
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1667492737
Short name T289
Test name
Test status
Simulation time 1881664606 ps
CPU time 6.89 seconds
Started Apr 21 01:02:12 PM PDT 24
Finished Apr 21 01:02:20 PM PDT 24
Peak memory 217524 kb
Host smart-60c8b8d2-92d9-40ce-811c-9048eaab4ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667492737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1667492737
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1515124570
Short name T267
Test name
Test status
Simulation time 244081269 ps
CPU time 1.09 seconds
Started Apr 21 01:02:20 PM PDT 24
Finished Apr 21 01:02:21 PM PDT 24
Peak memory 218172 kb
Host smart-8a1199b2-b084-4f5c-a48f-5fff5c53aa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515124570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1515124570
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3850558010
Short name T349
Test name
Test status
Simulation time 152899740 ps
CPU time 0.81 seconds
Started Apr 21 01:02:12 PM PDT 24
Finished Apr 21 01:02:14 PM PDT 24
Peak memory 200560 kb
Host smart-c0d7d60f-c5d5-40e3-b8ad-3d8ed3a6b77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850558010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3850558010
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3845861335
Short name T516
Test name
Test status
Simulation time 923293207 ps
CPU time 4.65 seconds
Started Apr 21 01:02:12 PM PDT 24
Finished Apr 21 01:02:17 PM PDT 24
Peak memory 200972 kb
Host smart-6f323f4c-d292-4b27-a411-f739dc45aaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845861335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3845861335
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3016402504
Short name T348
Test name
Test status
Simulation time 106748933 ps
CPU time 1 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:14 PM PDT 24
Peak memory 200788 kb
Host smart-f3cc5715-d23c-4f35-a946-f3dc95ba8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016402504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3016402504
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2378228242
Short name T515
Test name
Test status
Simulation time 118789630 ps
CPU time 1.21 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 200992 kb
Host smart-ffc7d0c8-7af8-43ce-98f4-cbdb2614d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378228242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2378228242
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2096241706
Short name T217
Test name
Test status
Simulation time 8832183783 ps
CPU time 31.47 seconds
Started Apr 21 01:02:11 PM PDT 24
Finished Apr 21 01:02:44 PM PDT 24
Peak memory 209260 kb
Host smart-8b20dc60-84fa-466d-9426-54d24d3c4604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096241706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2096241706
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1944445385
Short name T522
Test name
Test status
Simulation time 506028747 ps
CPU time 2.54 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 200804 kb
Host smart-23544029-0bab-4738-8813-560b16fc585a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944445385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1944445385
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1111452945
Short name T240
Test name
Test status
Simulation time 112453030 ps
CPU time 0.94 seconds
Started Apr 21 01:02:14 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 200856 kb
Host smart-9674dbaf-4080-4cd1-bd7d-f05c5a7d517f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111452945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1111452945
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1045665197
Short name T292
Test name
Test status
Simulation time 94273610 ps
CPU time 0.84 seconds
Started Apr 21 01:02:16 PM PDT 24
Finished Apr 21 01:02:17 PM PDT 24
Peak memory 200636 kb
Host smart-9631254d-b85e-4fc8-bf3e-7a1c6b2a5f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045665197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1045665197
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3436950372
Short name T333
Test name
Test status
Simulation time 2359088237 ps
CPU time 8.37 seconds
Started Apr 21 01:02:15 PM PDT 24
Finished Apr 21 01:02:24 PM PDT 24
Peak memory 222004 kb
Host smart-83a53d25-68b6-42d4-965e-411da09691ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436950372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3436950372
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1353827622
Short name T491
Test name
Test status
Simulation time 244117298 ps
CPU time 1.13 seconds
Started Apr 21 01:02:16 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 218188 kb
Host smart-9a279a4b-18d4-490a-9371-42bb2f398825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353827622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1353827622
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.147021575
Short name T205
Test name
Test status
Simulation time 196248216 ps
CPU time 0.91 seconds
Started Apr 21 01:02:14 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 200680 kb
Host smart-8479922c-4e01-400d-8070-6035a523ad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147021575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.147021575
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.4257499635
Short name T536
Test name
Test status
Simulation time 1624005623 ps
CPU time 7.2 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:21 PM PDT 24
Peak memory 200960 kb
Host smart-aab547e7-3bfb-4270-bb16-885d2c973e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257499635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.4257499635
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.104090624
Short name T58
Test name
Test status
Simulation time 104692532 ps
CPU time 0.96 seconds
Started Apr 21 01:02:14 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 200872 kb
Host smart-36948c2e-31a0-4c91-82ad-0d1eca9f7933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104090624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.104090624
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1601233373
Short name T82
Test name
Test status
Simulation time 233914700 ps
CPU time 1.41 seconds
Started Apr 21 01:02:12 PM PDT 24
Finished Apr 21 01:02:14 PM PDT 24
Peak memory 201048 kb
Host smart-779dd853-eb64-4468-b599-5a0295a42fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601233373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1601233373
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.4106469307
Short name T388
Test name
Test status
Simulation time 5363498380 ps
CPU time 23.22 seconds
Started Apr 21 01:02:16 PM PDT 24
Finished Apr 21 01:02:40 PM PDT 24
Peak memory 209248 kb
Host smart-472bf95b-4025-4c5c-b650-7a87466ce2a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106469307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.4106469307
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3088939186
Short name T378
Test name
Test status
Simulation time 320374936 ps
CPU time 2.13 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:20 PM PDT 24
Peak memory 200812 kb
Host smart-de0caed0-1b89-4c5a-8c78-e11e7ed5b0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088939186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3088939186
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.299702229
Short name T200
Test name
Test status
Simulation time 209277897 ps
CPU time 1.23 seconds
Started Apr 21 01:02:13 PM PDT 24
Finished Apr 21 01:02:15 PM PDT 24
Peak memory 200808 kb
Host smart-1381849d-a5b4-457b-9b47-7dfa8817ac0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299702229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.299702229
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1962416657
Short name T528
Test name
Test status
Simulation time 77946025 ps
CPU time 0.83 seconds
Started Apr 21 01:02:14 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 200652 kb
Host smart-47255a77-5c38-470b-b0e1-c21612d8910a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962416657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1962416657
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.809489986
Short name T513
Test name
Test status
Simulation time 243700043 ps
CPU time 1.08 seconds
Started Apr 21 01:02:16 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 218032 kb
Host smart-97cf8244-b466-4789-8f17-4fc0823f3a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809489986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.809489986
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.90399
Short name T328
Test name
Test status
Simulation time 83616675 ps
CPU time 0.75 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 200632 kb
Host smart-6639b1c9-9ead-4198-947a-1cce91c0c04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.90399
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2969886207
Short name T101
Test name
Test status
Simulation time 1840257130 ps
CPU time 6.96 seconds
Started Apr 21 01:02:16 PM PDT 24
Finished Apr 21 01:02:23 PM PDT 24
Peak memory 200988 kb
Host smart-f09b8420-09aa-4b75-9c23-2c915b3df920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969886207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2969886207
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3703937590
Short name T374
Test name
Test status
Simulation time 105703083 ps
CPU time 0.99 seconds
Started Apr 21 01:02:15 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 200792 kb
Host smart-c543c199-fc39-4e27-9ec7-25ba2981b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703937590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3703937590
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2334170322
Short name T494
Test name
Test status
Simulation time 244032184 ps
CPU time 1.49 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:23 PM PDT 24
Peak memory 201008 kb
Host smart-00726e66-4d2e-42c6-acb8-b42ba28b55ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334170322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2334170322
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1774508893
Short name T235
Test name
Test status
Simulation time 3295310776 ps
CPU time 12.72 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:31 PM PDT 24
Peak memory 200976 kb
Host smart-15bda850-0efc-4a2c-829a-2e5e7838d73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774508893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1774508893
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2400750566
Short name T430
Test name
Test status
Simulation time 248907724 ps
CPU time 1.76 seconds
Started Apr 21 01:02:15 PM PDT 24
Finished Apr 21 01:02:17 PM PDT 24
Peak memory 200740 kb
Host smart-f1158cf0-bf29-41e6-9625-13a1c9d95f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400750566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2400750566
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1651824230
Short name T286
Test name
Test status
Simulation time 63938348 ps
CPU time 0.8 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 200832 kb
Host smart-343fd9b4-3f30-4167-8c0d-31da6f55b4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651824230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1651824230
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1593999904
Short name T236
Test name
Test status
Simulation time 71231746 ps
CPU time 0.77 seconds
Started Apr 21 01:02:18 PM PDT 24
Finished Apr 21 01:02:19 PM PDT 24
Peak memory 200652 kb
Host smart-d243a2da-1204-4e2b-b165-eb51e714271b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593999904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1593999904
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3692890522
Short name T369
Test name
Test status
Simulation time 2373515601 ps
CPU time 8.45 seconds
Started Apr 21 01:02:14 PM PDT 24
Finished Apr 21 01:02:23 PM PDT 24
Peak memory 222048 kb
Host smart-f1751abf-4021-43f4-bf2f-6d789a7e56ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692890522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3692890522
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2809166853
Short name T488
Test name
Test status
Simulation time 244874718 ps
CPU time 1.03 seconds
Started Apr 21 01:02:23 PM PDT 24
Finished Apr 21 01:02:24 PM PDT 24
Peak memory 218272 kb
Host smart-501fee29-9f7a-4e8b-b990-5de3b536e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809166853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2809166853
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.386926945
Short name T16
Test name
Test status
Simulation time 190661885 ps
CPU time 0.88 seconds
Started Apr 21 01:02:15 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 200620 kb
Host smart-94087a6a-63b3-4213-a21b-4aa5c9108891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386926945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.386926945
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.830340708
Short name T401
Test name
Test status
Simulation time 1784881591 ps
CPU time 6.82 seconds
Started Apr 21 01:02:14 PM PDT 24
Finished Apr 21 01:02:27 PM PDT 24
Peak memory 201052 kb
Host smart-49657f2d-e089-4bca-a97c-08226193b633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830340708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.830340708
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2839761375
Short name T181
Test name
Test status
Simulation time 102992245 ps
CPU time 1.02 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 200832 kb
Host smart-c1460f83-c8e3-4258-8f34-93c95fc69160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839761375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2839761375
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.957342959
Short name T146
Test name
Test status
Simulation time 114025774 ps
CPU time 1.14 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 201000 kb
Host smart-6eb0ad59-1152-437c-9c33-89ab381efaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957342959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.957342959
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1052083657
Short name T356
Test name
Test status
Simulation time 4608522131 ps
CPU time 18.99 seconds
Started Apr 21 01:02:18 PM PDT 24
Finished Apr 21 01:02:38 PM PDT 24
Peak memory 209288 kb
Host smart-0bd694b8-f3e9-415e-9402-8b994fa300a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052083657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1052083657
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1649777969
Short name T309
Test name
Test status
Simulation time 422152097 ps
CPU time 2.33 seconds
Started Apr 21 01:02:15 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 209024 kb
Host smart-ef0ee131-be23-467c-a0b8-c42b99a216ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649777969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1649777969
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.565291204
Short name T449
Test name
Test status
Simulation time 101274732 ps
CPU time 1 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 200832 kb
Host smart-a08ca22c-b1da-4127-b6d5-caa9ddd2c264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565291204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.565291204
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2329345670
Short name T174
Test name
Test status
Simulation time 69733199 ps
CPU time 0.77 seconds
Started Apr 21 01:02:18 PM PDT 24
Finished Apr 21 01:02:19 PM PDT 24
Peak memory 200596 kb
Host smart-3eeedf62-3b8f-48bf-ba4d-418ca5acac82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329345670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2329345670
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.168489869
Short name T27
Test name
Test status
Simulation time 1898881859 ps
CPU time 6.9 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:28 PM PDT 24
Peak memory 222740 kb
Host smart-25094567-685d-4a1b-bbf7-3047d55f7321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168489869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.168489869
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3779473975
Short name T404
Test name
Test status
Simulation time 243864332 ps
CPU time 1.03 seconds
Started Apr 21 01:02:18 PM PDT 24
Finished Apr 21 01:02:19 PM PDT 24
Peak memory 218104 kb
Host smart-9ee3cfbc-cbbb-431a-a059-e98d29c7aa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779473975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3779473975
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2384803972
Short name T420
Test name
Test status
Simulation time 117028221 ps
CPU time 0.83 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:19 PM PDT 24
Peak memory 200604 kb
Host smart-d2476297-22fb-4061-8402-42c103e621a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384803972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2384803972
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3638683258
Short name T5
Test name
Test status
Simulation time 1346990346 ps
CPU time 5.1 seconds
Started Apr 21 01:02:19 PM PDT 24
Finished Apr 21 01:02:25 PM PDT 24
Peak memory 201004 kb
Host smart-a7828774-ce6c-4748-bb7f-f285db557fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638683258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3638683258
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1690059779
Short name T284
Test name
Test status
Simulation time 103987556 ps
CPU time 1.01 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:19 PM PDT 24
Peak memory 200832 kb
Host smart-f13eb168-72c9-4667-9741-03f05c8fbf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690059779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1690059779
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1832095529
Short name T496
Test name
Test status
Simulation time 194246605 ps
CPU time 1.45 seconds
Started Apr 21 01:02:16 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 200996 kb
Host smart-8be5beb2-e146-4ec8-af61-a1647921eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832095529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1832095529
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3010850805
Short name T293
Test name
Test status
Simulation time 9214897696 ps
CPU time 41.3 seconds
Started Apr 21 01:02:20 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 201092 kb
Host smart-217d95bc-b555-4bae-9d11-de05ea7f411e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010850805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3010850805
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.4292919829
Short name T385
Test name
Test status
Simulation time 141155699 ps
CPU time 1.84 seconds
Started Apr 21 01:02:23 PM PDT 24
Finished Apr 21 01:02:25 PM PDT 24
Peak memory 200808 kb
Host smart-9f0e4980-f1ca-4d2a-956d-429270a55b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292919829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.4292919829
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2992498234
Short name T218
Test name
Test status
Simulation time 88737193 ps
CPU time 0.79 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:18 PM PDT 24
Peak memory 200824 kb
Host smart-1424d4d7-a9c5-4bc4-a310-960470dbd2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992498234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2992498234
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.651187214
Short name T380
Test name
Test status
Simulation time 69871083 ps
CPU time 0.76 seconds
Started Apr 21 01:01:48 PM PDT 24
Finished Apr 21 01:01:49 PM PDT 24
Peak memory 200620 kb
Host smart-b6addc2e-c3aa-4e38-9367-f05d52fd1853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651187214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.651187214
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1204423614
Short name T364
Test name
Test status
Simulation time 1226330239 ps
CPU time 5.79 seconds
Started Apr 21 01:01:49 PM PDT 24
Finished Apr 21 01:01:55 PM PDT 24
Peak memory 218556 kb
Host smart-e5844358-9c4b-417a-a456-b56a121e33ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204423614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1204423614
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2349245296
Short name T329
Test name
Test status
Simulation time 245065860 ps
CPU time 1.03 seconds
Started Apr 21 01:01:46 PM PDT 24
Finished Apr 21 01:01:47 PM PDT 24
Peak memory 218132 kb
Host smart-2fc8eeed-303a-4b10-a652-aee6f5249c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349245296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2349245296
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.4161035843
Short name T20
Test name
Test status
Simulation time 225739605 ps
CPU time 0.9 seconds
Started Apr 21 01:01:43 PM PDT 24
Finished Apr 21 01:01:44 PM PDT 24
Peak memory 200648 kb
Host smart-ad850dd0-2b5e-4ea8-be97-733081ff0589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161035843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.4161035843
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.4207070351
Short name T390
Test name
Test status
Simulation time 1776209623 ps
CPU time 6.88 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:01:50 PM PDT 24
Peak memory 200980 kb
Host smart-70445733-39a0-4120-a264-83d9c047827a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207070351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4207070351
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.373397841
Short name T69
Test name
Test status
Simulation time 16749450440 ps
CPU time 29.53 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:02:12 PM PDT 24
Peak memory 217836 kb
Host smart-3e7fc3cf-e2af-4938-8fde-f7951554ff5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373397841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.373397841
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.633254911
Short name T405
Test name
Test status
Simulation time 153403263 ps
CPU time 1.2 seconds
Started Apr 21 01:01:47 PM PDT 24
Finished Apr 21 01:01:48 PM PDT 24
Peak memory 200812 kb
Host smart-e66be26c-2c54-46a9-b423-1eb2fbf0d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633254911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.633254911
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.250992200
Short name T377
Test name
Test status
Simulation time 256579824 ps
CPU time 1.42 seconds
Started Apr 21 01:01:41 PM PDT 24
Finished Apr 21 01:01:43 PM PDT 24
Peak memory 201008 kb
Host smart-859eb285-a797-4836-ae3b-e4253ff542a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250992200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.250992200
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3708246566
Short name T444
Test name
Test status
Simulation time 651836605 ps
CPU time 3.53 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:01:46 PM PDT 24
Peak memory 200960 kb
Host smart-414822c2-2e26-4ecf-ac8e-642ab58404c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708246566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3708246566
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.154852644
Short name T501
Test name
Test status
Simulation time 453292905 ps
CPU time 2.38 seconds
Started Apr 21 01:01:57 PM PDT 24
Finished Apr 21 01:02:00 PM PDT 24
Peak memory 200828 kb
Host smart-dca35b58-9ea9-4d16-a512-8448be9b48d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154852644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.154852644
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.837271684
Short name T80
Test name
Test status
Simulation time 93574476 ps
CPU time 0.93 seconds
Started Apr 21 01:01:57 PM PDT 24
Finished Apr 21 01:01:59 PM PDT 24
Peak memory 200820 kb
Host smart-0fe45a42-4f82-44a0-8908-3328ad8fd07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837271684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.837271684
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2982619269
Short name T406
Test name
Test status
Simulation time 66689536 ps
CPU time 0.79 seconds
Started Apr 21 01:02:35 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 200672 kb
Host smart-c182bbbe-b041-478d-9add-334218a37166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982619269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2982619269
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3320269442
Short name T502
Test name
Test status
Simulation time 2161633657 ps
CPU time 7.75 seconds
Started Apr 21 01:02:18 PM PDT 24
Finished Apr 21 01:02:26 PM PDT 24
Peak memory 218128 kb
Host smart-b06c4c89-3c66-4fa3-9387-ce9c64f4a5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320269442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3320269442
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1728827576
Short name T367
Test name
Test status
Simulation time 243622421 ps
CPU time 1.18 seconds
Started Apr 21 01:02:20 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 218112 kb
Host smart-fca4f53a-ecfe-4c5e-ab6e-f04ae1e6e4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728827576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1728827576
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2315408471
Short name T18
Test name
Test status
Simulation time 163532388 ps
CPU time 0.85 seconds
Started Apr 21 01:02:19 PM PDT 24
Finished Apr 21 01:02:20 PM PDT 24
Peak memory 200680 kb
Host smart-a9ac4d03-d3c4-402d-ac1d-8da280a6be5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315408471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2315408471
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2656767341
Short name T362
Test name
Test status
Simulation time 2204839911 ps
CPU time 8.03 seconds
Started Apr 21 01:02:17 PM PDT 24
Finished Apr 21 01:02:26 PM PDT 24
Peak memory 201064 kb
Host smart-349ba27c-fd21-41e2-91b1-dd339e98ffd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656767341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2656767341
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1676753211
Short name T23
Test name
Test status
Simulation time 170202399 ps
CPU time 1.3 seconds
Started Apr 21 01:02:48 PM PDT 24
Finished Apr 21 01:02:49 PM PDT 24
Peak memory 200832 kb
Host smart-62bcc0d4-0c56-4312-a9dd-30db66edc91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676753211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1676753211
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.68401878
Short name T306
Test name
Test status
Simulation time 199819390 ps
CPU time 1.39 seconds
Started Apr 21 01:02:19 PM PDT 24
Finished Apr 21 01:02:21 PM PDT 24
Peak memory 200996 kb
Host smart-9524e219-f7c3-42aa-a5ee-c8f60fed40cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68401878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.68401878
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1895060554
Short name T123
Test name
Test status
Simulation time 1364409737 ps
CPU time 5.02 seconds
Started Apr 21 01:02:18 PM PDT 24
Finished Apr 21 01:02:23 PM PDT 24
Peak memory 201044 kb
Host smart-b7b8d5e8-00e2-45e3-8639-2a9873be6d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895060554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1895060554
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.286338125
Short name T21
Test name
Test status
Simulation time 390332361 ps
CPU time 2.6 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:24 PM PDT 24
Peak memory 200808 kb
Host smart-b7e636c1-98d6-4256-ab19-ffefb8c2e8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286338125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.286338125
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1971849411
Short name T403
Test name
Test status
Simulation time 129574274 ps
CPU time 1.11 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 200816 kb
Host smart-466024cb-74c4-471f-853e-cdc6d70793c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971849411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1971849411
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.143411494
Short name T298
Test name
Test status
Simulation time 62361356 ps
CPU time 0.77 seconds
Started Apr 21 01:02:30 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 200668 kb
Host smart-9e3487ee-b4c1-47c5-ad4a-3490e6d0b67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143411494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.143411494
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1023831734
Short name T76
Test name
Test status
Simulation time 1219383298 ps
CPU time 5.51 seconds
Started Apr 21 01:02:33 PM PDT 24
Finished Apr 21 01:02:39 PM PDT 24
Peak memory 222684 kb
Host smart-677dff55-dce4-4abe-b5b9-343f4fdd9f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023831734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1023831734
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.813790987
Short name T190
Test name
Test status
Simulation time 244748673 ps
CPU time 1.03 seconds
Started Apr 21 01:02:22 PM PDT 24
Finished Apr 21 01:02:23 PM PDT 24
Peak memory 218264 kb
Host smart-f7944fc7-0960-45fb-b27d-656e6d5043d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813790987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.813790987
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1026348638
Short name T322
Test name
Test status
Simulation time 202617707 ps
CPU time 0.87 seconds
Started Apr 21 01:02:22 PM PDT 24
Finished Apr 21 01:02:23 PM PDT 24
Peak memory 200648 kb
Host smart-afa8343a-c380-4a34-99ab-73f300e17ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026348638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1026348638
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1728651878
Short name T269
Test name
Test status
Simulation time 1678170688 ps
CPU time 6.49 seconds
Started Apr 21 01:02:24 PM PDT 24
Finished Apr 21 01:02:31 PM PDT 24
Peak memory 200968 kb
Host smart-37884da2-06ea-4352-81ce-5f45d2f2fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728651878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1728651878
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2970836721
Short name T492
Test name
Test status
Simulation time 179278282 ps
CPU time 1.22 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 200840 kb
Host smart-ce065028-9fa5-40b8-b0c4-7ad35e9d4562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970836721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2970836721
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3208322051
Short name T519
Test name
Test status
Simulation time 120905364 ps
CPU time 1.14 seconds
Started Apr 21 01:02:20 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 200988 kb
Host smart-d0743223-e655-4020-8bd1-e93ad4f1e423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208322051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3208322051
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.717292467
Short name T352
Test name
Test status
Simulation time 2171374888 ps
CPU time 10.51 seconds
Started Apr 21 01:02:23 PM PDT 24
Finished Apr 21 01:02:34 PM PDT 24
Peak memory 201116 kb
Host smart-07961f74-f281-4357-b883-dd779c0a6c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717292467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.717292467
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1534643246
Short name T392
Test name
Test status
Simulation time 147704267 ps
CPU time 1.87 seconds
Started Apr 21 01:02:24 PM PDT 24
Finished Apr 21 01:02:26 PM PDT 24
Peak memory 200860 kb
Host smart-aa272771-dcff-4d9a-bd11-029615180076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534643246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1534643246
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1697051517
Short name T254
Test name
Test status
Simulation time 171539051 ps
CPU time 1.17 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:23 PM PDT 24
Peak memory 200808 kb
Host smart-35f8fe2b-8355-4191-b6ee-ff3255fad8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697051517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1697051517
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.461525715
Short name T184
Test name
Test status
Simulation time 59910930 ps
CPU time 0.76 seconds
Started Apr 21 01:02:23 PM PDT 24
Finished Apr 21 01:02:24 PM PDT 24
Peak memory 200632 kb
Host smart-4f2e3727-c88a-418f-a6c2-4a92a9624906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461525715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.461525715
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1639212379
Short name T83
Test name
Test status
Simulation time 1225627653 ps
CPU time 5.68 seconds
Started Apr 21 01:02:25 PM PDT 24
Finished Apr 21 01:02:31 PM PDT 24
Peak memory 217616 kb
Host smart-63c59770-60f0-4d72-a692-504569744d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639212379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1639212379
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3875652090
Short name T204
Test name
Test status
Simulation time 257414722 ps
CPU time 1.09 seconds
Started Apr 21 01:02:26 PM PDT 24
Finished Apr 21 01:02:28 PM PDT 24
Peak memory 218284 kb
Host smart-cf3af1db-e20b-4a55-92f9-4df57ca5f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875652090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3875652090
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2849078771
Short name T242
Test name
Test status
Simulation time 180981129 ps
CPU time 0.91 seconds
Started Apr 21 01:02:25 PM PDT 24
Finished Apr 21 01:02:26 PM PDT 24
Peak memory 200644 kb
Host smart-f3aa1663-d858-4530-bc89-1e4d88fbde9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849078771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2849078771
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2570885613
Short name T232
Test name
Test status
Simulation time 1011789228 ps
CPU time 5.17 seconds
Started Apr 21 01:02:24 PM PDT 24
Finished Apr 21 01:02:29 PM PDT 24
Peak memory 201048 kb
Host smart-b9cf46c8-7fa4-43c4-a3a2-01d2a9a5226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570885613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2570885613
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.4007278582
Short name T145
Test name
Test status
Simulation time 110787713 ps
CPU time 1 seconds
Started Apr 21 01:02:27 PM PDT 24
Finished Apr 21 01:02:28 PM PDT 24
Peak memory 200812 kb
Host smart-ad482e46-0c1f-4b4e-b7e1-39212145a33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007278582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.4007278582
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.4177279912
Short name T274
Test name
Test status
Simulation time 114900474 ps
CPU time 1.21 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 200964 kb
Host smart-beabbd74-22aa-40ff-9c3c-3aec7393b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177279912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.4177279912
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1820341628
Short name T498
Test name
Test status
Simulation time 1675593431 ps
CPU time 6.44 seconds
Started Apr 21 01:02:26 PM PDT 24
Finished Apr 21 01:02:33 PM PDT 24
Peak memory 201008 kb
Host smart-2dfdf021-d342-4e7a-aa46-438e28b306f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820341628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1820341628
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2617563505
Short name T422
Test name
Test status
Simulation time 529908123 ps
CPU time 2.78 seconds
Started Apr 21 01:02:21 PM PDT 24
Finished Apr 21 01:02:24 PM PDT 24
Peak memory 200816 kb
Host smart-d152adc8-334e-4c15-9654-3222f327ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617563505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2617563505
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3752175329
Short name T312
Test name
Test status
Simulation time 240245775 ps
CPU time 1.52 seconds
Started Apr 21 01:02:24 PM PDT 24
Finished Apr 21 01:02:26 PM PDT 24
Peak memory 200868 kb
Host smart-2ffb1ec0-f384-4baf-8a81-23847f7d060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752175329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3752175329
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2627727148
Short name T395
Test name
Test status
Simulation time 73278143 ps
CPU time 0.79 seconds
Started Apr 21 01:02:23 PM PDT 24
Finished Apr 21 01:02:24 PM PDT 24
Peak memory 200636 kb
Host smart-392a7d70-e00e-4928-aef2-cb313bacb278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627727148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2627727148
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1341686148
Short name T30
Test name
Test status
Simulation time 1223088406 ps
CPU time 6.27 seconds
Started Apr 21 01:02:29 PM PDT 24
Finished Apr 21 01:02:36 PM PDT 24
Peak memory 218596 kb
Host smart-5006820b-e1a6-482a-ac6b-37951ccd8d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341686148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1341686148
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3748806829
Short name T291
Test name
Test status
Simulation time 244414961 ps
CPU time 1.07 seconds
Started Apr 21 01:02:27 PM PDT 24
Finished Apr 21 01:02:28 PM PDT 24
Peak memory 218180 kb
Host smart-8edb91c5-ff77-483d-b3a8-bf07ac6479d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748806829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3748806829
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.321601001
Short name T338
Test name
Test status
Simulation time 129082538 ps
CPU time 0.8 seconds
Started Apr 21 01:02:26 PM PDT 24
Finished Apr 21 01:02:28 PM PDT 24
Peak memory 200636 kb
Host smart-e6ef97b5-514e-42a8-aec8-9b3d65839201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321601001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.321601001
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2847878370
Short name T259
Test name
Test status
Simulation time 1263157391 ps
CPU time 5.41 seconds
Started Apr 21 01:02:34 PM PDT 24
Finished Apr 21 01:02:45 PM PDT 24
Peak memory 201080 kb
Host smart-84fe94bd-fa5b-4aaa-b8dd-218cbba5abdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847878370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2847878370
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1200081019
Short name T319
Test name
Test status
Simulation time 159608654 ps
CPU time 1.14 seconds
Started Apr 21 01:02:30 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 200748 kb
Host smart-ef93cd77-0d6f-43cb-a312-6961707c69ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200081019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1200081019
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3974892675
Short name T276
Test name
Test status
Simulation time 124078864 ps
CPU time 1.21 seconds
Started Apr 21 01:02:20 PM PDT 24
Finished Apr 21 01:02:21 PM PDT 24
Peak memory 201020 kb
Host smart-98d26421-2dd0-4c9a-9026-021243519392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974892675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3974892675
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2485928164
Short name T275
Test name
Test status
Simulation time 1553214066 ps
CPU time 6.22 seconds
Started Apr 21 01:02:35 PM PDT 24
Finished Apr 21 01:02:41 PM PDT 24
Peak memory 200920 kb
Host smart-9cda0c23-bd5c-4be6-841e-f1acb171ba01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485928164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2485928164
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3883137621
Short name T193
Test name
Test status
Simulation time 121159189 ps
CPU time 1.47 seconds
Started Apr 21 01:02:28 PM PDT 24
Finished Apr 21 01:02:29 PM PDT 24
Peak memory 200816 kb
Host smart-7b3f6986-c9db-4807-9b09-e1f5e4c3bf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883137621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3883137621
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1419291058
Short name T12
Test name
Test status
Simulation time 100273363 ps
CPU time 0.86 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 200864 kb
Host smart-eb9eddc2-c9b4-4c7e-8f08-04cd0bfd232b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419291058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1419291058
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3540183701
Short name T191
Test name
Test status
Simulation time 56439325 ps
CPU time 0.72 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 200548 kb
Host smart-7173f9a0-6929-4e4b-92bf-05004a334939
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540183701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3540183701
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1267625621
Short name T44
Test name
Test status
Simulation time 2181380661 ps
CPU time 7.53 seconds
Started Apr 21 01:02:29 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 218148 kb
Host smart-487b2b25-9378-4206-be8a-a9f63810efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267625621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1267625621
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1532424204
Short name T77
Test name
Test status
Simulation time 244107856 ps
CPU time 1.09 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:38 PM PDT 24
Peak memory 218132 kb
Host smart-c733afd4-81c7-4879-8c86-3b5f0717cb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532424204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1532424204
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2858986559
Short name T324
Test name
Test status
Simulation time 148822125 ps
CPU time 0.82 seconds
Started Apr 21 01:02:35 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 200684 kb
Host smart-87b26412-2484-4e0f-b043-6b1afcf30fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858986559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2858986559
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.191058000
Short name T210
Test name
Test status
Simulation time 2051166837 ps
CPU time 7.48 seconds
Started Apr 21 01:02:29 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 200972 kb
Host smart-f00530ee-dddb-4a2c-b625-adee1c9347c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191058000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.191058000
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.64247568
Short name T152
Test name
Test status
Simulation time 136905857 ps
CPU time 1.14 seconds
Started Apr 21 01:02:30 PM PDT 24
Finished Apr 21 01:02:31 PM PDT 24
Peak memory 200748 kb
Host smart-a01c1ac1-79db-4bbd-9e6d-e8da7b74fb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64247568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.64247568
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1151821692
Short name T474
Test name
Test status
Simulation time 251317771 ps
CPU time 1.64 seconds
Started Apr 21 01:02:22 PM PDT 24
Finished Apr 21 01:02:24 PM PDT 24
Peak memory 201036 kb
Host smart-8c92106b-5991-4213-8974-d753dea374cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151821692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1151821692
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.387170860
Short name T394
Test name
Test status
Simulation time 6180837812 ps
CPU time 26.74 seconds
Started Apr 21 01:02:29 PM PDT 24
Finished Apr 21 01:02:56 PM PDT 24
Peak memory 209296 kb
Host smart-c10cf197-04e9-4970-b3f3-618727b70b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387170860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.387170860
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3254069087
Short name T272
Test name
Test status
Simulation time 136272937 ps
CPU time 1.82 seconds
Started Apr 21 01:02:30 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 200864 kb
Host smart-6b07aee5-a2b4-49e8-af9b-65afb03695ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254069087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3254069087
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3386748548
Short name T295
Test name
Test status
Simulation time 157995005 ps
CPU time 1.29 seconds
Started Apr 21 01:02:27 PM PDT 24
Finished Apr 21 01:02:28 PM PDT 24
Peak memory 200772 kb
Host smart-07797ae5-6dfd-4322-9f8b-9b904c1283f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386748548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3386748548
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3917482642
Short name T197
Test name
Test status
Simulation time 67815968 ps
CPU time 0.79 seconds
Started Apr 21 01:02:32 PM PDT 24
Finished Apr 21 01:02:34 PM PDT 24
Peak memory 200620 kb
Host smart-8eb2e4ed-50ae-45f7-9b0f-cc0c79c0b228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917482642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3917482642
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3837529558
Short name T472
Test name
Test status
Simulation time 1894877585 ps
CPU time 6.95 seconds
Started Apr 21 01:02:34 PM PDT 24
Finished Apr 21 01:02:41 PM PDT 24
Peak memory 222720 kb
Host smart-ae7f7edc-4156-40ff-b5e6-76e7d672ca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837529558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3837529558
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2943147897
Short name T199
Test name
Test status
Simulation time 246316484 ps
CPU time 1.03 seconds
Started Apr 21 01:02:28 PM PDT 24
Finished Apr 21 01:02:29 PM PDT 24
Peak memory 218124 kb
Host smart-cc238743-cf2c-4ff4-8343-68a4ed2b5872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943147897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2943147897
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.4129782781
Short name T287
Test name
Test status
Simulation time 119863243 ps
CPU time 0.82 seconds
Started Apr 21 01:02:30 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 200684 kb
Host smart-8088e679-d881-4c68-965a-a04225677fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129782781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.4129782781
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1318141639
Short name T107
Test name
Test status
Simulation time 1091792716 ps
CPU time 5.41 seconds
Started Apr 21 01:02:25 PM PDT 24
Finished Apr 21 01:02:30 PM PDT 24
Peak memory 201024 kb
Host smart-6087afbd-88df-4be5-85e7-bb8d79980f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318141639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1318141639
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4025148968
Short name T357
Test name
Test status
Simulation time 96415351 ps
CPU time 0.97 seconds
Started Apr 21 01:02:31 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 200840 kb
Host smart-651ae21b-0b71-43ce-a09b-523fac565a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025148968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4025148968
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1672754322
Short name T138
Test name
Test status
Simulation time 192740410 ps
CPU time 1.45 seconds
Started Apr 21 01:02:30 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 201036 kb
Host smart-cedf2eb8-6a90-422c-8cd1-a1ea4c3ece2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672754322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1672754322
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3026285702
Short name T125
Test name
Test status
Simulation time 7521887608 ps
CPU time 24.03 seconds
Started Apr 21 01:02:37 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 209184 kb
Host smart-75ffe09a-d181-4648-bb74-c8b60171aead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026285702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3026285702
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1056793972
Short name T246
Test name
Test status
Simulation time 398537490 ps
CPU time 2.13 seconds
Started Apr 21 01:02:31 PM PDT 24
Finished Apr 21 01:02:33 PM PDT 24
Peak memory 200796 kb
Host smart-cfe40965-9c9c-4686-bc4b-4b2a0d99a8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056793972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1056793972
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1873075429
Short name T534
Test name
Test status
Simulation time 100455592 ps
CPU time 0.86 seconds
Started Apr 21 01:02:35 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 200820 kb
Host smart-790c5480-f54d-41a2-b929-c8cc6b1e6bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873075429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1873075429
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.590349566
Short name T1
Test name
Test status
Simulation time 77022509 ps
CPU time 0.79 seconds
Started Apr 21 01:02:30 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 200676 kb
Host smart-e73ef2a3-786a-4794-a6c5-78a41d6ae66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590349566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.590349566
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2520411346
Short name T448
Test name
Test status
Simulation time 1891870095 ps
CPU time 6.88 seconds
Started Apr 21 01:02:35 PM PDT 24
Finished Apr 21 01:02:42 PM PDT 24
Peak memory 218608 kb
Host smart-cbf0aa3c-98d5-4e89-a213-72f3c20939a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520411346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2520411346
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.239851049
Short name T156
Test name
Test status
Simulation time 244663148 ps
CPU time 1.1 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 218148 kb
Host smart-417a3502-04ff-4563-bff8-0b22ceef06ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239851049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.239851049
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.60703878
Short name T183
Test name
Test status
Simulation time 107784964 ps
CPU time 0.78 seconds
Started Apr 21 01:02:31 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 200620 kb
Host smart-a266c9a9-e949-4443-a46e-ecf89cf13a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60703878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.60703878
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2276403282
Short name T221
Test name
Test status
Simulation time 1155001839 ps
CPU time 5.59 seconds
Started Apr 21 01:02:26 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 200960 kb
Host smart-8acb4a24-f7f8-4c17-acd1-bef7c4d093ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276403282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2276403282
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1293316528
Short name T456
Test name
Test status
Simulation time 187110675 ps
CPU time 1.19 seconds
Started Apr 21 01:02:34 PM PDT 24
Finished Apr 21 01:02:35 PM PDT 24
Peak memory 200800 kb
Host smart-1cb844a8-768c-4116-9fe1-3fbfa5145b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293316528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1293316528
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1294921625
Short name T216
Test name
Test status
Simulation time 243373763 ps
CPU time 1.49 seconds
Started Apr 21 01:02:35 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 201016 kb
Host smart-d8816ea0-bb27-4f18-9e04-22a75b6b593e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294921625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1294921625
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2505838014
Short name T337
Test name
Test status
Simulation time 4626309454 ps
CPU time 17.9 seconds
Started Apr 21 01:02:33 PM PDT 24
Finished Apr 21 01:02:51 PM PDT 24
Peak memory 201072 kb
Host smart-be35d5ac-4a50-4cd2-8ea4-38024db49d4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505838014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2505838014
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1612046314
Short name T258
Test name
Test status
Simulation time 341618682 ps
CPU time 2.13 seconds
Started Apr 21 01:02:28 PM PDT 24
Finished Apr 21 01:02:31 PM PDT 24
Peak memory 200840 kb
Host smart-06bf9a19-57c2-440f-ad60-17fbff3ccdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612046314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1612046314
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1655836178
Short name T234
Test name
Test status
Simulation time 115243740 ps
CPU time 0.94 seconds
Started Apr 21 01:02:34 PM PDT 24
Finished Apr 21 01:02:35 PM PDT 24
Peak memory 200860 kb
Host smart-05b949db-e3a7-4705-b1b2-3512de323c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655836178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1655836178
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.4235019651
Short name T523
Test name
Test status
Simulation time 62441367 ps
CPU time 0.72 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:38 PM PDT 24
Peak memory 200552 kb
Host smart-f670bb57-962d-43cd-9894-6babf468b106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235019651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4235019651
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.320221511
Short name T376
Test name
Test status
Simulation time 2172965624 ps
CPU time 7.89 seconds
Started Apr 21 01:02:37 PM PDT 24
Finished Apr 21 01:02:46 PM PDT 24
Peak memory 218644 kb
Host smart-d573aee9-acec-4f68-9156-252d1ce2d3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320221511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.320221511
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1544644114
Short name T431
Test name
Test status
Simulation time 245578376 ps
CPU time 1.08 seconds
Started Apr 21 01:02:41 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 218148 kb
Host smart-5650f6a1-014a-42da-9271-742ff0d01cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544644114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1544644114
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2381413890
Short name T237
Test name
Test status
Simulation time 191406481 ps
CPU time 1.02 seconds
Started Apr 21 01:02:43 PM PDT 24
Finished Apr 21 01:02:45 PM PDT 24
Peak memory 200640 kb
Host smart-e3bba89e-ff1a-4b63-be2c-a3b116cc4371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381413890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2381413890
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2812640703
Short name T413
Test name
Test status
Simulation time 1444751073 ps
CPU time 6.06 seconds
Started Apr 21 01:02:35 PM PDT 24
Finished Apr 21 01:02:42 PM PDT 24
Peak memory 200908 kb
Host smart-ca0c62ef-8067-499a-8b99-626a964cce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812640703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2812640703
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.4004108859
Short name T504
Test name
Test status
Simulation time 101872293 ps
CPU time 1.02 seconds
Started Apr 21 01:02:34 PM PDT 24
Finished Apr 21 01:02:36 PM PDT 24
Peak memory 200840 kb
Host smart-ce2fdce2-bb06-46da-a3dd-0ab837713292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004108859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.4004108859
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1987969138
Short name T500
Test name
Test status
Simulation time 206320668 ps
CPU time 1.4 seconds
Started Apr 21 01:02:33 PM PDT 24
Finished Apr 21 01:02:35 PM PDT 24
Peak memory 201016 kb
Host smart-54ddd498-89e5-4c93-88ca-e88f3a062967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987969138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1987969138
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2625012817
Short name T271
Test name
Test status
Simulation time 1881507935 ps
CPU time 8.36 seconds
Started Apr 21 01:02:37 PM PDT 24
Finished Apr 21 01:02:45 PM PDT 24
Peak memory 209184 kb
Host smart-d0b6e2ad-af9c-47a2-9b4d-793e45ef35b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625012817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2625012817
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2273594456
Short name T2
Test name
Test status
Simulation time 460941558 ps
CPU time 2.47 seconds
Started Apr 21 01:02:30 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 200812 kb
Host smart-5f5edb1a-0a7c-41aa-9436-fda5a1d7b7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273594456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2273594456
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2727892631
Short name T487
Test name
Test status
Simulation time 277573360 ps
CPU time 1.62 seconds
Started Apr 21 01:02:31 PM PDT 24
Finished Apr 21 01:02:33 PM PDT 24
Peak memory 200804 kb
Host smart-eb7dcace-ffb6-4d9f-97c8-8b4764d16758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727892631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2727892631
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3884783885
Short name T384
Test name
Test status
Simulation time 73787372 ps
CPU time 0.8 seconds
Started Apr 21 01:02:38 PM PDT 24
Finished Apr 21 01:02:39 PM PDT 24
Peak memory 200628 kb
Host smart-1a3c3870-cc35-4b58-9c70-70023e409bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884783885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3884783885
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3923700167
Short name T22
Test name
Test status
Simulation time 2154423679 ps
CPU time 7.72 seconds
Started Apr 21 01:02:39 PM PDT 24
Finished Apr 21 01:02:47 PM PDT 24
Peak memory 221732 kb
Host smart-fd9ce1ce-457d-4c66-b096-0d211c5caa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923700167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3923700167
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.655588599
Short name T426
Test name
Test status
Simulation time 243940657 ps
CPU time 1.12 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:38 PM PDT 24
Peak memory 218104 kb
Host smart-2b184432-ba7c-4e51-b6a6-0b53597334ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655588599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.655588599
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.871892554
Short name T311
Test name
Test status
Simulation time 195782969 ps
CPU time 0.87 seconds
Started Apr 21 01:02:33 PM PDT 24
Finished Apr 21 01:02:34 PM PDT 24
Peak memory 200660 kb
Host smart-17d4c04d-a103-4b30-9c84-3819c6bec114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871892554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.871892554
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3761405938
Short name T99
Test name
Test status
Simulation time 2018387766 ps
CPU time 7.34 seconds
Started Apr 21 01:02:29 PM PDT 24
Finished Apr 21 01:02:36 PM PDT 24
Peak memory 200996 kb
Host smart-af0e5fee-0ee0-4959-b457-4cc70385ed59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761405938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3761405938
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3172146873
Short name T402
Test name
Test status
Simulation time 152190408 ps
CPU time 1.12 seconds
Started Apr 21 01:02:32 PM PDT 24
Finished Apr 21 01:02:33 PM PDT 24
Peak memory 200852 kb
Host smart-59f0f69c-fe10-4dc6-849b-20f08501affc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172146873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3172146873
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3503112634
Short name T155
Test name
Test status
Simulation time 205492947 ps
CPU time 1.4 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:38 PM PDT 24
Peak memory 200964 kb
Host smart-8dbaa7c4-9f28-42b5-965f-db92fe6b071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503112634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3503112634
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.506003006
Short name T331
Test name
Test status
Simulation time 4797601168 ps
CPU time 20.08 seconds
Started Apr 21 01:02:38 PM PDT 24
Finished Apr 21 01:02:59 PM PDT 24
Peak memory 201096 kb
Host smart-bc06c6e9-2055-4863-899f-527cc9508ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506003006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.506003006
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2118050298
Short name T495
Test name
Test status
Simulation time 138160771 ps
CPU time 1.73 seconds
Started Apr 21 01:02:34 PM PDT 24
Finished Apr 21 01:02:36 PM PDT 24
Peak memory 200828 kb
Host smart-8a7dd71f-3c5f-42b5-980e-74069280f4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118050298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2118050298
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3541960980
Short name T134
Test name
Test status
Simulation time 182449960 ps
CPU time 1.26 seconds
Started Apr 21 01:02:32 PM PDT 24
Finished Apr 21 01:02:33 PM PDT 24
Peak memory 200808 kb
Host smart-56af4c61-3f29-459e-ad85-47802f89e046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541960980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3541960980
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.584096577
Short name T535
Test name
Test status
Simulation time 64790719 ps
CPU time 0.75 seconds
Started Apr 21 01:02:38 PM PDT 24
Finished Apr 21 01:02:39 PM PDT 24
Peak memory 200636 kb
Host smart-beea4fa3-d828-406b-a1f5-709dabf08eec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584096577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.584096577
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3827521683
Short name T49
Test name
Test status
Simulation time 1233947863 ps
CPU time 5.46 seconds
Started Apr 21 01:02:44 PM PDT 24
Finished Apr 21 01:02:50 PM PDT 24
Peak memory 222672 kb
Host smart-16fb175d-4db0-417b-a9fe-01022c687462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827521683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3827521683
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.65946979
Short name T260
Test name
Test status
Simulation time 244275982 ps
CPU time 1.09 seconds
Started Apr 21 01:02:31 PM PDT 24
Finished Apr 21 01:02:33 PM PDT 24
Peak memory 218108 kb
Host smart-4c4a294d-37ba-4a41-9a5a-859bab29909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65946979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.65946979
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.4205468360
Short name T330
Test name
Test status
Simulation time 97740680 ps
CPU time 0.75 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 200648 kb
Host smart-21c8b218-3502-4188-87c8-22054a157136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205468360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.4205468360
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1655435848
Short name T207
Test name
Test status
Simulation time 1485039774 ps
CPU time 5.63 seconds
Started Apr 21 01:02:37 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 201012 kb
Host smart-d91a0dd0-2897-48e8-8a97-8871281b00e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655435848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1655435848
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.844911953
Short name T154
Test name
Test status
Simulation time 100781697 ps
CPU time 0.98 seconds
Started Apr 21 01:02:37 PM PDT 24
Finished Apr 21 01:02:39 PM PDT 24
Peak memory 200840 kb
Host smart-581a3e6a-06ae-45a5-b10a-8e23fa630016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844911953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.844911953
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3867019498
Short name T250
Test name
Test status
Simulation time 187240245 ps
CPU time 1.4 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:38 PM PDT 24
Peak memory 201052 kb
Host smart-215e1d0f-5263-4558-aa1a-84259e72d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867019498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3867019498
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.862322140
Short name T469
Test name
Test status
Simulation time 2018592937 ps
CPU time 9.38 seconds
Started Apr 21 01:02:34 PM PDT 24
Finished Apr 21 01:02:44 PM PDT 24
Peak memory 200980 kb
Host smart-6c368e15-9add-4f35-9587-da46a7a2eb55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862322140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.862322140
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3501986721
Short name T90
Test name
Test status
Simulation time 310042116 ps
CPU time 2.07 seconds
Started Apr 21 01:02:29 PM PDT 24
Finished Apr 21 01:02:32 PM PDT 24
Peak memory 209048 kb
Host smart-f14b15de-2ece-47f5-9b22-9845216439fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501986721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3501986721
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2070725736
Short name T163
Test name
Test status
Simulation time 205575761 ps
CPU time 1.35 seconds
Started Apr 21 01:02:39 PM PDT 24
Finished Apr 21 01:02:41 PM PDT 24
Peak memory 200836 kb
Host smart-d9422ee5-fa61-47cd-bb5d-28a2ea9b5dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070725736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2070725736
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4199797561
Short name T432
Test name
Test status
Simulation time 81692160 ps
CPU time 0.8 seconds
Started Apr 21 01:01:44 PM PDT 24
Finished Apr 21 01:01:45 PM PDT 24
Peak memory 200596 kb
Host smart-8d9c7a4c-9e15-4a2d-96f0-64f9c9cee720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199797561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4199797561
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1212560143
Short name T290
Test name
Test status
Simulation time 1898423304 ps
CPU time 7.17 seconds
Started Apr 21 01:01:50 PM PDT 24
Finished Apr 21 01:01:58 PM PDT 24
Peak memory 217556 kb
Host smart-d2f63228-3ba3-4786-a876-6d0122b766ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212560143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1212560143
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3013288419
Short name T419
Test name
Test status
Simulation time 243457709 ps
CPU time 1.05 seconds
Started Apr 21 01:01:46 PM PDT 24
Finished Apr 21 01:01:48 PM PDT 24
Peak memory 218148 kb
Host smart-6d29744c-dd5d-43ac-af76-cf26678f8ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013288419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3013288419
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2808427210
Short name T408
Test name
Test status
Simulation time 141148052 ps
CPU time 0.86 seconds
Started Apr 21 01:02:00 PM PDT 24
Finished Apr 21 01:02:01 PM PDT 24
Peak memory 200652 kb
Host smart-9378a870-2bb8-4a1a-9453-6b80bdb022c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808427210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2808427210
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4138954324
Short name T485
Test name
Test status
Simulation time 1122913869 ps
CPU time 5.41 seconds
Started Apr 21 01:01:48 PM PDT 24
Finished Apr 21 01:01:54 PM PDT 24
Peak memory 200984 kb
Host smart-ea61652e-0dd3-4cda-9441-e5cf8c4ccc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138954324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4138954324
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2171431085
Short name T75
Test name
Test status
Simulation time 16671378365 ps
CPU time 24.99 seconds
Started Apr 21 01:02:00 PM PDT 24
Finished Apr 21 01:02:25 PM PDT 24
Peak memory 218756 kb
Host smart-0b1cf77b-dd69-487b-bafd-7e802696495e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171431085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2171431085
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2797676103
Short name T409
Test name
Test status
Simulation time 143706116 ps
CPU time 1.13 seconds
Started Apr 21 01:01:45 PM PDT 24
Finished Apr 21 01:01:47 PM PDT 24
Peak memory 200824 kb
Host smart-80b46d86-5637-49a2-a81a-e1a25aefb8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797676103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2797676103
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3832660268
Short name T230
Test name
Test status
Simulation time 114772476 ps
CPU time 1.19 seconds
Started Apr 21 01:01:44 PM PDT 24
Finished Apr 21 01:01:46 PM PDT 24
Peak memory 200960 kb
Host smart-bb686b3b-170b-40a6-b2c8-11b6316a693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832660268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3832660268
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1515330574
Short name T224
Test name
Test status
Simulation time 6424572452 ps
CPU time 23.29 seconds
Started Apr 21 01:01:44 PM PDT 24
Finished Apr 21 01:02:08 PM PDT 24
Peak memory 201052 kb
Host smart-4629cdc4-19a3-4003-a2f4-17ee76521f82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515330574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1515330574
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3841336874
Short name T415
Test name
Test status
Simulation time 259358778 ps
CPU time 1.79 seconds
Started Apr 21 01:01:48 PM PDT 24
Finished Apr 21 01:01:51 PM PDT 24
Peak memory 200800 kb
Host smart-9bcd8beb-b03d-4e6a-847c-25cf655063be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841336874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3841336874
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.963483791
Short name T176
Test name
Test status
Simulation time 201989086 ps
CPU time 1.32 seconds
Started Apr 21 01:01:42 PM PDT 24
Finished Apr 21 01:01:44 PM PDT 24
Peak memory 200812 kb
Host smart-d8ae8689-98bd-4a17-ac8e-ec017eb5e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963483791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.963483791
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.172958604
Short name T180
Test name
Test status
Simulation time 76777091 ps
CPU time 0.77 seconds
Started Apr 21 01:02:34 PM PDT 24
Finished Apr 21 01:02:35 PM PDT 24
Peak memory 200640 kb
Host smart-8f2727ab-aa4d-4250-afd1-b83d8d9cdc12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172958604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.172958604
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1974048824
Short name T51
Test name
Test status
Simulation time 1224250375 ps
CPU time 5.58 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:42 PM PDT 24
Peak memory 230864 kb
Host smart-9f2f8155-0810-4cc9-8565-1c46a0b3d854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974048824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1974048824
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.777421603
Short name T397
Test name
Test status
Simulation time 246667079 ps
CPU time 1.07 seconds
Started Apr 21 01:02:42 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 218172 kb
Host smart-81abf229-0e1e-4188-9e04-5f5c9d802d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777421603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.777421603
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2296960804
Short name T396
Test name
Test status
Simulation time 127205071 ps
CPU time 0.85 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 200652 kb
Host smart-9585f5cc-2993-40c5-b908-983909e70123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296960804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2296960804
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.311125067
Short name T382
Test name
Test status
Simulation time 1558911030 ps
CPU time 5.86 seconds
Started Apr 21 01:02:38 PM PDT 24
Finished Apr 21 01:02:45 PM PDT 24
Peak memory 200996 kb
Host smart-58412daf-3e8b-49c7-b792-e41bb33ab582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311125067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.311125067
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2743044085
Short name T253
Test name
Test status
Simulation time 179523245 ps
CPU time 1.25 seconds
Started Apr 21 01:02:39 PM PDT 24
Finished Apr 21 01:02:40 PM PDT 24
Peak memory 200844 kb
Host smart-8aeb5126-331d-49d6-8324-7c4854f8d180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743044085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2743044085
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2094861786
Short name T128
Test name
Test status
Simulation time 258494960 ps
CPU time 1.53 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:39 PM PDT 24
Peak memory 201020 kb
Host smart-b2ca4ae7-1a96-4d53-89fe-ff873c3aa1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094861786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2094861786
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.505933660
Short name T212
Test name
Test status
Simulation time 10076727204 ps
CPU time 31.93 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:03:09 PM PDT 24
Peak memory 201064 kb
Host smart-39c50e8d-1c12-4239-9543-71f226f3cd05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505933660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.505933660
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1094018463
Short name T203
Test name
Test status
Simulation time 340197678 ps
CPU time 2.27 seconds
Started Apr 21 01:02:37 PM PDT 24
Finished Apr 21 01:02:40 PM PDT 24
Peak memory 200828 kb
Host smart-31de2eb8-74cc-4e77-a27d-e80269701f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094018463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1094018463
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1852332304
Short name T268
Test name
Test status
Simulation time 165659388 ps
CPU time 1.12 seconds
Started Apr 21 01:02:33 PM PDT 24
Finished Apr 21 01:02:34 PM PDT 24
Peak memory 200856 kb
Host smart-47f63145-d502-421d-8018-18b2cb25372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852332304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1852332304
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3031477542
Short name T482
Test name
Test status
Simulation time 76867245 ps
CPU time 0.81 seconds
Started Apr 21 01:02:45 PM PDT 24
Finished Apr 21 01:02:46 PM PDT 24
Peak memory 200636 kb
Host smart-414ef3bb-738f-4b71-98bc-6bb3b3dc5e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031477542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3031477542
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1737321416
Short name T41
Test name
Test status
Simulation time 1226632109 ps
CPU time 5.58 seconds
Started Apr 21 01:02:37 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 217644 kb
Host smart-0c470328-bf62-4aeb-8b19-ace70c20fb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737321416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1737321416
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4262041627
Short name T144
Test name
Test status
Simulation time 244566989 ps
CPU time 1.12 seconds
Started Apr 21 01:02:49 PM PDT 24
Finished Apr 21 01:02:50 PM PDT 24
Peak memory 218140 kb
Host smart-fdd76ebe-2677-4371-9d9b-3c6ba933b264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262041627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4262041627
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3507015254
Short name T442
Test name
Test status
Simulation time 122943075 ps
CPU time 0.82 seconds
Started Apr 21 01:02:35 PM PDT 24
Finished Apr 21 01:02:36 PM PDT 24
Peak memory 200572 kb
Host smart-6e19d3b4-04e3-426c-9a03-2824f72b410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507015254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3507015254
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.914617632
Short name T455
Test name
Test status
Simulation time 1142371294 ps
CPU time 5.51 seconds
Started Apr 21 01:02:40 PM PDT 24
Finished Apr 21 01:02:46 PM PDT 24
Peak memory 201008 kb
Host smart-8f2ae475-fd4b-4729-b4f2-7c3f0d3c817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914617632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.914617632
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2501414528
Short name T10
Test name
Test status
Simulation time 103901275 ps
CPU time 0.98 seconds
Started Apr 21 01:02:39 PM PDT 24
Finished Apr 21 01:02:40 PM PDT 24
Peak memory 200840 kb
Host smart-42f1d465-ccd3-42de-8b6f-1e2625082811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501414528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2501414528
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3804109239
Short name T400
Test name
Test status
Simulation time 194118989 ps
CPU time 1.34 seconds
Started Apr 21 01:02:41 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 201012 kb
Host smart-20803043-ee19-44ef-9a76-96ef89266836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804109239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3804109239
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3379691890
Short name T478
Test name
Test status
Simulation time 6411912632 ps
CPU time 21.9 seconds
Started Apr 21 01:02:40 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 201012 kb
Host smart-d0767e67-99a9-440d-8131-2d1a81989582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379691890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3379691890
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.736552345
Short name T325
Test name
Test status
Simulation time 384074216 ps
CPU time 2.44 seconds
Started Apr 21 01:02:33 PM PDT 24
Finished Apr 21 01:02:36 PM PDT 24
Peak memory 200832 kb
Host smart-da611570-499d-4610-8f88-6df7bba5f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736552345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.736552345
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3696793264
Short name T142
Test name
Test status
Simulation time 126785778 ps
CPU time 1.05 seconds
Started Apr 21 01:02:51 PM PDT 24
Finished Apr 21 01:02:52 PM PDT 24
Peak memory 200824 kb
Host smart-8765c17f-928f-4a10-a9f5-d623b8a4fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696793264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3696793264
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1897454654
Short name T434
Test name
Test status
Simulation time 81535529 ps
CPU time 0.78 seconds
Started Apr 21 01:02:46 PM PDT 24
Finished Apr 21 01:02:48 PM PDT 24
Peak memory 200616 kb
Host smart-59b414f8-2d43-461a-b8b5-9f3942d98d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897454654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1897454654
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2431140516
Short name T486
Test name
Test status
Simulation time 2157581787 ps
CPU time 7.57 seconds
Started Apr 21 01:02:42 PM PDT 24
Finished Apr 21 01:02:50 PM PDT 24
Peak memory 218716 kb
Host smart-1d0e85b0-0512-459e-847b-c1280bd5973a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431140516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2431140516
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1047589919
Short name T79
Test name
Test status
Simulation time 243944656 ps
CPU time 1.05 seconds
Started Apr 21 01:02:37 PM PDT 24
Finished Apr 21 01:02:39 PM PDT 24
Peak memory 218292 kb
Host smart-8ffe6868-05c4-4799-8eea-a0f08358d653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047589919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1047589919
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2333002050
Short name T510
Test name
Test status
Simulation time 136990133 ps
CPU time 0.8 seconds
Started Apr 21 01:02:43 PM PDT 24
Finished Apr 21 01:02:44 PM PDT 24
Peak memory 200648 kb
Host smart-ddb9e3d8-7843-419f-94b9-67b1cb848c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333002050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2333002050
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3706410654
Short name T317
Test name
Test status
Simulation time 1284675771 ps
CPU time 5.43 seconds
Started Apr 21 01:02:45 PM PDT 24
Finished Apr 21 01:02:50 PM PDT 24
Peak memory 201052 kb
Host smart-57b94eba-2397-48a7-a346-2fb38a5c32a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706410654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3706410654
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3308956484
Short name T481
Test name
Test status
Simulation time 157999974 ps
CPU time 1.04 seconds
Started Apr 21 01:02:39 PM PDT 24
Finished Apr 21 01:02:40 PM PDT 24
Peak memory 200812 kb
Host smart-e6223c26-8f6b-4064-a569-1a55738e6015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308956484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3308956484
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.290828017
Short name T459
Test name
Test status
Simulation time 122985362 ps
CPU time 1.18 seconds
Started Apr 21 01:02:42 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 201044 kb
Host smart-8438b1a1-afa1-4ae1-a8d4-7141becf98a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290828017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.290828017
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1711415322
Short name T89
Test name
Test status
Simulation time 2839974429 ps
CPU time 13.51 seconds
Started Apr 21 01:02:47 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 217428 kb
Host smart-74527771-8c9d-4633-8030-92b55361db04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711415322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1711415322
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.325619968
Short name T264
Test name
Test status
Simulation time 446995063 ps
CPU time 2.59 seconds
Started Apr 21 01:02:41 PM PDT 24
Finished Apr 21 01:02:44 PM PDT 24
Peak memory 200832 kb
Host smart-fed485bc-5c27-4d01-b368-96b6c056993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325619968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.325619968
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2871390859
Short name T305
Test name
Test status
Simulation time 150207099 ps
CPU time 1.06 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:38 PM PDT 24
Peak memory 200840 kb
Host smart-8701b1a1-1482-42d6-96b8-4fa458e6e7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871390859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2871390859
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2599111804
Short name T368
Test name
Test status
Simulation time 70271551 ps
CPU time 0.71 seconds
Started Apr 21 01:02:46 PM PDT 24
Finished Apr 21 01:02:47 PM PDT 24
Peak memory 200616 kb
Host smart-877d4753-3652-426f-841c-c1c61a5fa468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599111804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2599111804
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3710755738
Short name T43
Test name
Test status
Simulation time 1227039591 ps
CPU time 5.42 seconds
Started Apr 21 01:02:49 PM PDT 24
Finished Apr 21 01:02:55 PM PDT 24
Peak memory 218628 kb
Host smart-d5ca732f-cf89-4443-af79-ec88eb788617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710755738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3710755738
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.606143457
Short name T497
Test name
Test status
Simulation time 244205724 ps
CPU time 1.14 seconds
Started Apr 21 01:02:42 PM PDT 24
Finished Apr 21 01:02:44 PM PDT 24
Peak memory 218328 kb
Host smart-8b1c2cd6-5d37-4db8-a727-f2e1df26fa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606143457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.606143457
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3890036610
Short name T231
Test name
Test status
Simulation time 118574451 ps
CPU time 0.81 seconds
Started Apr 21 01:02:36 PM PDT 24
Finished Apr 21 01:02:37 PM PDT 24
Peak memory 200648 kb
Host smart-28bb2954-76ad-4790-9020-a5b1e9834f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890036610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3890036610
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1302872065
Short name T37
Test name
Test status
Simulation time 1474617754 ps
CPU time 5.66 seconds
Started Apr 21 01:02:34 PM PDT 24
Finished Apr 21 01:02:40 PM PDT 24
Peak memory 201016 kb
Host smart-44e1f79f-e855-4ca0-8475-395d75a0decf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302872065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1302872065
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.145841112
Short name T164
Test name
Test status
Simulation time 191068402 ps
CPU time 1.14 seconds
Started Apr 21 01:02:41 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 200820 kb
Host smart-07f3f983-be16-427b-9189-3bb2e830e97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145841112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.145841112
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.4240343894
Short name T127
Test name
Test status
Simulation time 241357545 ps
CPU time 1.41 seconds
Started Apr 21 01:02:40 PM PDT 24
Finished Apr 21 01:02:42 PM PDT 24
Peak memory 200996 kb
Host smart-b673d2cf-37d6-46ba-9f2c-0f46d42e9806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240343894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.4240343894
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.530651323
Short name T530
Test name
Test status
Simulation time 8093476606 ps
CPU time 26.23 seconds
Started Apr 21 01:02:42 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 201084 kb
Host smart-f8d5e0eb-7006-416c-8c2d-af7a7947f789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530651323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.530651323
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.366768214
Short name T239
Test name
Test status
Simulation time 331412091 ps
CPU time 2.08 seconds
Started Apr 21 01:02:50 PM PDT 24
Finished Apr 21 01:02:53 PM PDT 24
Peak memory 200852 kb
Host smart-76a7222d-dcc5-40b5-a145-8fa8b0657ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366768214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.366768214
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.32808377
Short name T379
Test name
Test status
Simulation time 286070757 ps
CPU time 1.55 seconds
Started Apr 21 01:02:58 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 200920 kb
Host smart-a4c152ca-5925-4900-8ad6-65db06b35668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32808377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.32808377
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2518979061
Short name T248
Test name
Test status
Simulation time 97285916 ps
CPU time 0.88 seconds
Started Apr 21 01:02:39 PM PDT 24
Finished Apr 21 01:02:41 PM PDT 24
Peak memory 200632 kb
Host smart-bce4f6a9-c3af-4c50-836c-36e72f2fc388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518979061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2518979061
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1825236979
Short name T52
Test name
Test status
Simulation time 2360752444 ps
CPU time 8 seconds
Started Apr 21 01:02:52 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 218312 kb
Host smart-1f85577b-89cc-4b67-b6f3-736eaad0e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825236979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1825236979
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1346080787
Short name T321
Test name
Test status
Simulation time 244493834 ps
CPU time 1.07 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 218300 kb
Host smart-874e38c4-2bc0-4fb4-b505-2eaa0f26bf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346080787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1346080787
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1450643453
Short name T14
Test name
Test status
Simulation time 90820588 ps
CPU time 0.74 seconds
Started Apr 21 01:02:42 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 200684 kb
Host smart-f72a8c2e-f6f1-4814-b170-d97dc61cec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450643453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1450643453
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.4229818542
Short name T389
Test name
Test status
Simulation time 1448130890 ps
CPU time 5.49 seconds
Started Apr 21 01:02:42 PM PDT 24
Finished Apr 21 01:02:48 PM PDT 24
Peak memory 200984 kb
Host smart-43606d4c-81e0-4da6-8dde-1db3898b1df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229818542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4229818542
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3285273584
Short name T172
Test name
Test status
Simulation time 106231754 ps
CPU time 1.05 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 200868 kb
Host smart-a713d4fe-1684-4b48-87d9-5432044ccbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285273584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3285273584
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1112128015
Short name T59
Test name
Test status
Simulation time 198731326 ps
CPU time 1.4 seconds
Started Apr 21 01:02:52 PM PDT 24
Finished Apr 21 01:02:53 PM PDT 24
Peak memory 200980 kb
Host smart-d5b795e9-6637-46ab-91d2-c262a48a2169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112128015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1112128015
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2420207812
Short name T256
Test name
Test status
Simulation time 3750980265 ps
CPU time 17.01 seconds
Started Apr 21 01:02:45 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 201072 kb
Host smart-e90522c8-cfdc-422c-b9db-84c246d3c1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420207812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2420207812
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2909179675
Short name T373
Test name
Test status
Simulation time 272285928 ps
CPU time 2 seconds
Started Apr 21 01:02:39 PM PDT 24
Finished Apr 21 01:02:42 PM PDT 24
Peak memory 200820 kb
Host smart-38211ca0-e25c-4c82-8208-af8c24c74f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909179675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2909179675
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2281786727
Short name T251
Test name
Test status
Simulation time 86532195 ps
CPU time 0.82 seconds
Started Apr 21 01:02:47 PM PDT 24
Finished Apr 21 01:02:48 PM PDT 24
Peak memory 200796 kb
Host smart-eb23e284-09ba-4d28-88be-cbf589fe4c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281786727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2281786727
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4286240352
Short name T149
Test name
Test status
Simulation time 73830154 ps
CPU time 0.81 seconds
Started Apr 21 01:03:02 PM PDT 24
Finished Apr 21 01:03:03 PM PDT 24
Peak memory 200668 kb
Host smart-f6459093-0e10-498a-8fb1-1d50c1a79881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286240352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4286240352
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2257791761
Short name T517
Test name
Test status
Simulation time 243580778 ps
CPU time 1.2 seconds
Started Apr 21 01:02:45 PM PDT 24
Finished Apr 21 01:02:47 PM PDT 24
Peak memory 218304 kb
Host smart-c203eab0-d0b9-4475-b828-ea58616371c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257791761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2257791761
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.155350228
Short name T428
Test name
Test status
Simulation time 81321919 ps
CPU time 0.77 seconds
Started Apr 21 01:02:41 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 200612 kb
Host smart-df51a1a0-795e-4b4e-811a-96428cde4e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155350228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.155350228
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1571251491
Short name T160
Test name
Test status
Simulation time 1438048353 ps
CPU time 5.47 seconds
Started Apr 21 01:03:02 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 201048 kb
Host smart-6f4f204e-cb4a-45e9-b83b-92969f980b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571251491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1571251491
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2520691913
Short name T270
Test name
Test status
Simulation time 142982931 ps
CPU time 1.08 seconds
Started Apr 21 01:02:38 PM PDT 24
Finished Apr 21 01:02:40 PM PDT 24
Peak memory 200824 kb
Host smart-496447c8-c8ee-4bee-8b55-8d8f88fe2129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520691913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2520691913
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1002111017
Short name T457
Test name
Test status
Simulation time 198905382 ps
CPU time 1.35 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:02:58 PM PDT 24
Peak memory 201060 kb
Host smart-8b3c7f01-6bc5-4d49-a959-2dfda7c9ece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002111017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1002111017
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1021037095
Short name T411
Test name
Test status
Simulation time 2984963773 ps
CPU time 14.34 seconds
Started Apr 21 01:02:41 PM PDT 24
Finished Apr 21 01:02:55 PM PDT 24
Peak memory 209272 kb
Host smart-6dbd1c12-0f8d-4e3c-a0eb-3dc18dee9f42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021037095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1021037095
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.279438991
Short name T437
Test name
Test status
Simulation time 351357861 ps
CPU time 1.9 seconds
Started Apr 21 01:02:47 PM PDT 24
Finished Apr 21 01:02:49 PM PDT 24
Peak memory 200856 kb
Host smart-4e630e53-f71c-420a-828c-e91ad9bbf858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279438991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.279438991
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2205914066
Short name T484
Test name
Test status
Simulation time 106400295 ps
CPU time 0.97 seconds
Started Apr 21 01:02:56 PM PDT 24
Finished Apr 21 01:02:57 PM PDT 24
Peak memory 200840 kb
Host smart-74840d55-6d71-43c3-b1f0-61cf312b4d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205914066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2205914066
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.273621355
Short name T185
Test name
Test status
Simulation time 84402382 ps
CPU time 0.81 seconds
Started Apr 21 01:02:50 PM PDT 24
Finished Apr 21 01:02:51 PM PDT 24
Peak memory 200628 kb
Host smart-f095b89f-aeec-4071-8253-2194927c190b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273621355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.273621355
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3933162957
Short name T50
Test name
Test status
Simulation time 1903926880 ps
CPU time 7.4 seconds
Started Apr 21 01:02:54 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 230496 kb
Host smart-8d7477ae-2715-4f5a-b0ef-883a02f24938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933162957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3933162957
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1377938860
Short name T173
Test name
Test status
Simulation time 243370970 ps
CPU time 1.14 seconds
Started Apr 21 01:02:43 PM PDT 24
Finished Apr 21 01:02:45 PM PDT 24
Peak memory 218204 kb
Host smart-966d5f53-6dcf-4ace-a53d-934a375cc414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377938860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1377938860
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1169465982
Short name T15
Test name
Test status
Simulation time 114995264 ps
CPU time 0.84 seconds
Started Apr 21 01:02:45 PM PDT 24
Finished Apr 21 01:02:46 PM PDT 24
Peak memory 200664 kb
Host smart-db7e7c01-3456-4d29-b69c-9486ef4885f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169465982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1169465982
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1886894324
Short name T529
Test name
Test status
Simulation time 1465407751 ps
CPU time 5.45 seconds
Started Apr 21 01:02:55 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 201000 kb
Host smart-7449d01f-c83d-4624-9804-3860ab321db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886894324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1886894324
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.238402856
Short name T285
Test name
Test status
Simulation time 185911857 ps
CPU time 1.15 seconds
Started Apr 21 01:02:47 PM PDT 24
Finished Apr 21 01:02:48 PM PDT 24
Peak memory 200876 kb
Host smart-83026a78-5530-4846-bfcb-4e41f34b97eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238402856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.238402856
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4274683738
Short name T88
Test name
Test status
Simulation time 235999005 ps
CPU time 1.51 seconds
Started Apr 21 01:02:54 PM PDT 24
Finished Apr 21 01:02:56 PM PDT 24
Peak memory 201080 kb
Host smart-57f0b896-fa26-4ee4-a3f4-ce651ee91418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274683738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4274683738
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3172028414
Short name T423
Test name
Test status
Simulation time 5655500597 ps
CPU time 25.51 seconds
Started Apr 21 01:02:44 PM PDT 24
Finished Apr 21 01:03:10 PM PDT 24
Peak memory 209204 kb
Host smart-4bb04502-ae57-4f7e-a17e-f50b4c15f8d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172028414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3172028414
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1532761706
Short name T447
Test name
Test status
Simulation time 148778846 ps
CPU time 1.75 seconds
Started Apr 21 01:03:00 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 200828 kb
Host smart-711e3ab6-c0f2-41e0-9982-ab00356ad5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532761706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1532761706
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3646113261
Short name T527
Test name
Test status
Simulation time 134705372 ps
CPU time 1.05 seconds
Started Apr 21 01:03:03 PM PDT 24
Finished Apr 21 01:03:04 PM PDT 24
Peak memory 200800 kb
Host smart-45fa5a9c-2d86-4e86-873d-81db6e5d68ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646113261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3646113261
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2390602460
Short name T165
Test name
Test status
Simulation time 68441377 ps
CPU time 0.8 seconds
Started Apr 21 01:02:46 PM PDT 24
Finished Apr 21 01:02:47 PM PDT 24
Peak memory 200812 kb
Host smart-0ce6c809-c9a9-4fbb-af2d-9335ed885697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390602460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2390602460
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3580645012
Short name T414
Test name
Test status
Simulation time 1906338705 ps
CPU time 7.96 seconds
Started Apr 21 01:02:53 PM PDT 24
Finished Apr 21 01:03:01 PM PDT 24
Peak memory 218068 kb
Host smart-cd35a95c-df9c-4656-801c-2677dbefc1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580645012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3580645012
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3428177915
Short name T36
Test name
Test status
Simulation time 244206391 ps
CPU time 1.1 seconds
Started Apr 21 01:02:45 PM PDT 24
Finished Apr 21 01:02:46 PM PDT 24
Peak memory 218356 kb
Host smart-696d83d5-bd26-4be5-a3be-fc1ec4cab558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428177915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3428177915
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.81756846
Short name T227
Test name
Test status
Simulation time 125856321 ps
CPU time 0.79 seconds
Started Apr 21 01:02:45 PM PDT 24
Finished Apr 21 01:02:46 PM PDT 24
Peak memory 200676 kb
Host smart-ea3ac8f9-05ac-4ab5-a50f-c9d17d736d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81756846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.81756846
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.551984297
Short name T451
Test name
Test status
Simulation time 776535821 ps
CPU time 4.12 seconds
Started Apr 21 01:02:57 PM PDT 24
Finished Apr 21 01:03:02 PM PDT 24
Peak memory 200940 kb
Host smart-9bca607f-aeab-489e-a120-880149d170d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551984297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.551984297
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2674941131
Short name T170
Test name
Test status
Simulation time 154775344 ps
CPU time 1.26 seconds
Started Apr 21 01:02:52 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 200828 kb
Host smart-55b0d9d4-11ce-4b9c-a2d5-38b66356de69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674941131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2674941131
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.351346711
Short name T316
Test name
Test status
Simulation time 198820739 ps
CPU time 1.44 seconds
Started Apr 21 01:02:41 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 200976 kb
Host smart-e6fb5fc2-e71b-4e03-a498-42677d08eac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351346711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.351346711
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.380314013
Short name T320
Test name
Test status
Simulation time 978530362 ps
CPU time 4.8 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:12 PM PDT 24
Peak memory 201000 kb
Host smart-077ae733-d2c4-4f1f-ad16-8ffb58f976d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380314013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.380314013
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.475581986
Short name T243
Test name
Test status
Simulation time 386041014 ps
CPU time 2.07 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:09 PM PDT 24
Peak memory 200412 kb
Host smart-a8900234-ced6-47c1-9d4f-5123d1456e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475581986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.475581986
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.422087986
Short name T9
Test name
Test status
Simulation time 154066298 ps
CPU time 1.18 seconds
Started Apr 21 01:02:42 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 200848 kb
Host smart-93b6dada-af25-40f6-9b40-43031954a7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422087986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.422087986
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2764732265
Short name T169
Test name
Test status
Simulation time 68906326 ps
CPU time 0.75 seconds
Started Apr 21 01:02:47 PM PDT 24
Finished Apr 21 01:02:48 PM PDT 24
Peak memory 200600 kb
Host smart-9e755c98-9e5f-4e2d-9e18-899e382cddfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764732265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2764732265
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.420227495
Short name T278
Test name
Test status
Simulation time 1231499238 ps
CPU time 5.88 seconds
Started Apr 21 01:03:01 PM PDT 24
Finished Apr 21 01:03:07 PM PDT 24
Peak memory 222088 kb
Host smart-2befc6ea-62d7-4197-a3cb-41746581092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420227495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.420227495
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2948485253
Short name T166
Test name
Test status
Simulation time 244623734 ps
CPU time 1.08 seconds
Started Apr 21 01:03:04 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 218208 kb
Host smart-5ce3667c-c89b-4c7a-a15e-24e50e85d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948485253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2948485253
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2859304313
Short name T17
Test name
Test status
Simulation time 202910732 ps
CPU time 0.86 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 200208 kb
Host smart-96dbd15d-9871-41f6-b4e6-ae101a8e021f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859304313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2859304313
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1900196185
Short name T359
Test name
Test status
Simulation time 1243869179 ps
CPU time 4.9 seconds
Started Apr 21 01:03:09 PM PDT 24
Finished Apr 21 01:03:14 PM PDT 24
Peak memory 201008 kb
Host smart-e824aa84-0249-48eb-8de5-bb2e2814dab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900196185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1900196185
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3900387595
Short name T531
Test name
Test status
Simulation time 112816288 ps
CPU time 0.99 seconds
Started Apr 21 01:02:41 PM PDT 24
Finished Apr 21 01:02:42 PM PDT 24
Peak memory 200824 kb
Host smart-e3f2cd79-1781-4fce-b597-bbb322937775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900387595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3900387595
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3193735087
Short name T244
Test name
Test status
Simulation time 119906310 ps
CPU time 1.23 seconds
Started Apr 21 01:02:46 PM PDT 24
Finished Apr 21 01:02:48 PM PDT 24
Peak memory 201000 kb
Host smart-b69d0428-685e-457d-ba5a-4de8577c64d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193735087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3193735087
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1167413538
Short name T233
Test name
Test status
Simulation time 9435851524 ps
CPU time 30.11 seconds
Started Apr 21 01:02:50 PM PDT 24
Finished Apr 21 01:03:21 PM PDT 24
Peak memory 210160 kb
Host smart-fb03dce6-5c29-4388-83a2-adb0395b264f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167413538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1167413538
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.559294423
Short name T91
Test name
Test status
Simulation time 145995352 ps
CPU time 1.79 seconds
Started Apr 21 01:02:52 PM PDT 24
Finished Apr 21 01:02:54 PM PDT 24
Peak memory 200816 kb
Host smart-4a5cc9c6-5dfc-4e60-a20a-c569f6243506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559294423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.559294423
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2508828955
Short name T366
Test name
Test status
Simulation time 132485183 ps
CPU time 1 seconds
Started Apr 21 01:02:45 PM PDT 24
Finished Apr 21 01:02:46 PM PDT 24
Peak memory 200856 kb
Host smart-4001cd1e-aeab-47c1-b281-6cdf91193056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508828955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2508828955
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1294665786
Short name T178
Test name
Test status
Simulation time 85157815 ps
CPU time 0.83 seconds
Started Apr 21 01:03:06 PM PDT 24
Finished Apr 21 01:03:08 PM PDT 24
Peak memory 200624 kb
Host smart-d259ed73-0f60-4a10-baa6-4a3ce9d86698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294665786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1294665786
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.4065321686
Short name T466
Test name
Test status
Simulation time 1215615106 ps
CPU time 5.43 seconds
Started Apr 21 01:02:54 PM PDT 24
Finished Apr 21 01:03:00 PM PDT 24
Peak memory 221552 kb
Host smart-4819d14c-6ebf-4d2e-af05-1e63f1fc9803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065321686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4065321686
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1535505263
Short name T208
Test name
Test status
Simulation time 244399689 ps
CPU time 1.16 seconds
Started Apr 21 01:02:48 PM PDT 24
Finished Apr 21 01:02:50 PM PDT 24
Peak memory 218172 kb
Host smart-3e40024f-f2d8-4e63-b2ff-51eb359a4364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535505263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1535505263
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.146884130
Short name T179
Test name
Test status
Simulation time 156159379 ps
CPU time 0.81 seconds
Started Apr 21 01:02:43 PM PDT 24
Finished Apr 21 01:02:44 PM PDT 24
Peak memory 200568 kb
Host smart-2e79faf9-77e5-4c3d-a836-bb72e65c2368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146884130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.146884130
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1538878498
Short name T297
Test name
Test status
Simulation time 1568552270 ps
CPU time 5.91 seconds
Started Apr 21 01:02:59 PM PDT 24
Finished Apr 21 01:03:05 PM PDT 24
Peak memory 200976 kb
Host smart-96e3abad-65ec-40ef-8d1b-fd08436b34ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538878498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1538878498
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2496214913
Short name T45
Test name
Test status
Simulation time 154538814 ps
CPU time 1.22 seconds
Started Apr 21 01:02:51 PM PDT 24
Finished Apr 21 01:02:52 PM PDT 24
Peak memory 200828 kb
Host smart-1eeee3f9-a3f0-457e-abd2-e0fff12a001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496214913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2496214913
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3992430619
Short name T56
Test name
Test status
Simulation time 191115968 ps
CPU time 1.31 seconds
Started Apr 21 01:03:13 PM PDT 24
Finished Apr 21 01:03:15 PM PDT 24
Peak memory 201008 kb
Host smart-745f409a-30c3-49ea-a230-09cc57139b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992430619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3992430619
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1145558832
Short name T407
Test name
Test status
Simulation time 5272115208 ps
CPU time 22.61 seconds
Started Apr 21 01:02:43 PM PDT 24
Finished Apr 21 01:03:06 PM PDT 24
Peak memory 201084 kb
Host smart-c77fd2cd-25f5-4c5a-97f9-87a6a8b0779a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145558832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1145558832
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3198471714
Short name T326
Test name
Test status
Simulation time 295696656 ps
CPU time 2.02 seconds
Started Apr 21 01:02:50 PM PDT 24
Finished Apr 21 01:02:52 PM PDT 24
Peak memory 209056 kb
Host smart-9be14209-613f-4822-81e0-5460efe7530a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198471714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3198471714
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3167846623
Short name T153
Test name
Test status
Simulation time 97486633 ps
CPU time 0.92 seconds
Started Apr 21 01:02:41 PM PDT 24
Finished Apr 21 01:02:43 PM PDT 24
Peak memory 200840 kb
Host smart-f0c6506d-0d3f-4c11-b3a1-4e2c34dd201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167846623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3167846623
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.70856843
Short name T355
Test name
Test status
Simulation time 69235258 ps
CPU time 0.82 seconds
Started Apr 21 01:01:45 PM PDT 24
Finished Apr 21 01:01:47 PM PDT 24
Peak memory 200632 kb
Host smart-05e3e0b4-6d5f-40bb-aaad-9cf1ab82eaf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70856843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.70856843
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.585801594
Short name T347
Test name
Test status
Simulation time 2350682266 ps
CPU time 8.33 seconds
Started Apr 21 01:01:43 PM PDT 24
Finished Apr 21 01:01:52 PM PDT 24
Peak memory 218668 kb
Host smart-9029b403-a630-486d-adbf-e89f1482d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585801594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.585801594
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2552454493
Short name T315
Test name
Test status
Simulation time 243526643 ps
CPU time 1.1 seconds
Started Apr 21 01:01:46 PM PDT 24
Finished Apr 21 01:01:48 PM PDT 24
Peak memory 218140 kb
Host smart-26d38d2d-9ee8-4690-8ce2-7833b68f1dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552454493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2552454493
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.672918582
Short name T509
Test name
Test status
Simulation time 154499354 ps
CPU time 0.88 seconds
Started Apr 21 01:01:45 PM PDT 24
Finished Apr 21 01:01:46 PM PDT 24
Peak memory 200632 kb
Host smart-da4d2f7b-55b0-4d9f-bf31-ead81fd152db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672918582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.672918582
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3128960182
Short name T175
Test name
Test status
Simulation time 798869007 ps
CPU time 4.01 seconds
Started Apr 21 01:02:00 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 201024 kb
Host smart-a71cd9a4-8142-409a-b5cc-b66c80c2c8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128960182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3128960182
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3688195277
Short name T471
Test name
Test status
Simulation time 100156636 ps
CPU time 1.02 seconds
Started Apr 21 01:01:57 PM PDT 24
Finished Apr 21 01:01:59 PM PDT 24
Peak memory 200848 kb
Host smart-8db3eba7-c762-4148-b3e6-441ad698c795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688195277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3688195277
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1078610086
Short name T525
Test name
Test status
Simulation time 197273310 ps
CPU time 1.38 seconds
Started Apr 21 01:01:43 PM PDT 24
Finished Apr 21 01:01:45 PM PDT 24
Peak memory 200924 kb
Host smart-457fd793-af0a-45a9-9db1-15c21ceb9a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078610086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1078610086
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1907453648
Short name T381
Test name
Test status
Simulation time 5274482273 ps
CPU time 17.73 seconds
Started Apr 21 01:01:57 PM PDT 24
Finished Apr 21 01:02:16 PM PDT 24
Peak memory 217400 kb
Host smart-cd1c4e26-08c0-4d87-b37a-28cbd4d5e3a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907453648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1907453648
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1325212201
Short name T257
Test name
Test status
Simulation time 123983726 ps
CPU time 1.53 seconds
Started Apr 21 01:01:45 PM PDT 24
Finished Apr 21 01:01:48 PM PDT 24
Peak memory 200820 kb
Host smart-da702909-d102-4745-8a68-46acb0388f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325212201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1325212201
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.93140620
Short name T503
Test name
Test status
Simulation time 139741154 ps
CPU time 1.21 seconds
Started Apr 21 01:01:51 PM PDT 24
Finished Apr 21 01:01:52 PM PDT 24
Peak memory 200804 kb
Host smart-9ae1b196-bd91-458d-abce-68481a4a00b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93140620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.93140620
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2800338353
Short name T147
Test name
Test status
Simulation time 64234040 ps
CPU time 0.74 seconds
Started Apr 21 01:01:47 PM PDT 24
Finished Apr 21 01:01:48 PM PDT 24
Peak memory 200588 kb
Host smart-6607ea7c-9ac2-4397-a115-2a3ebaf9460b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800338353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2800338353
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2762504883
Short name T32
Test name
Test status
Simulation time 1896205726 ps
CPU time 7.02 seconds
Started Apr 21 01:01:50 PM PDT 24
Finished Apr 21 01:01:57 PM PDT 24
Peak memory 218116 kb
Host smart-bfc1c88b-5e15-4e74-a127-01b1527c04d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762504883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2762504883
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.704682315
Short name T464
Test name
Test status
Simulation time 243874685 ps
CPU time 1.17 seconds
Started Apr 21 01:02:50 PM PDT 24
Finished Apr 21 01:02:51 PM PDT 24
Peak memory 218136 kb
Host smart-235916f5-ef21-4d95-9d24-e651a423100d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704682315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.704682315
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1249478043
Short name T11
Test name
Test status
Simulation time 114313938 ps
CPU time 0.81 seconds
Started Apr 21 01:01:47 PM PDT 24
Finished Apr 21 01:01:49 PM PDT 24
Peak memory 200676 kb
Host smart-1bee6136-15dd-43d3-b1ef-525b3a0a3e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249478043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1249478043
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2894427547
Short name T473
Test name
Test status
Simulation time 721830284 ps
CPU time 3.71 seconds
Started Apr 21 01:01:47 PM PDT 24
Finished Apr 21 01:01:51 PM PDT 24
Peak memory 200976 kb
Host smart-c2e0701d-d90b-449d-8d6d-135570803158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894427547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2894427547
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.326044602
Short name T162
Test name
Test status
Simulation time 184276649 ps
CPU time 1.25 seconds
Started Apr 21 01:01:46 PM PDT 24
Finished Apr 21 01:01:48 PM PDT 24
Peak memory 200852 kb
Host smart-09f002c8-fcd9-4da7-92e1-97e4398aca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326044602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.326044602
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1307474496
Short name T334
Test name
Test status
Simulation time 125034960 ps
CPU time 1.33 seconds
Started Apr 21 01:01:48 PM PDT 24
Finished Apr 21 01:01:50 PM PDT 24
Peak memory 200980 kb
Host smart-31b59bb5-3172-4f0b-9d45-5e4e1f2ec209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307474496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1307474496
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2695940510
Short name T524
Test name
Test status
Simulation time 381324500 ps
CPU time 1.78 seconds
Started Apr 21 01:01:57 PM PDT 24
Finished Apr 21 01:02:00 PM PDT 24
Peak memory 201004 kb
Host smart-43344b4d-bdbb-4203-afb4-5d6cc3b563c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695940510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2695940510
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.517690192
Short name T219
Test name
Test status
Simulation time 327000903 ps
CPU time 2.1 seconds
Started Apr 21 01:01:49 PM PDT 24
Finished Apr 21 01:01:51 PM PDT 24
Peak memory 200804 kb
Host smart-067f4edf-caa2-4613-8ad7-2f7d46636eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517690192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.517690192
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.23243586
Short name T470
Test name
Test status
Simulation time 114948993 ps
CPU time 1.11 seconds
Started Apr 21 01:01:47 PM PDT 24
Finished Apr 21 01:01:49 PM PDT 24
Peak memory 200792 kb
Host smart-7ad3f1b0-e97e-4c12-87ad-eb6fea97049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23243586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.23243586
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2650058952
Short name T283
Test name
Test status
Simulation time 71197627 ps
CPU time 0.78 seconds
Started Apr 21 01:01:52 PM PDT 24
Finished Apr 21 01:01:53 PM PDT 24
Peak memory 200544 kb
Host smart-36a904db-056b-4314-9432-841574fda0a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650058952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2650058952
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2657432594
Short name T262
Test name
Test status
Simulation time 1225788905 ps
CPU time 5.46 seconds
Started Apr 21 01:01:53 PM PDT 24
Finished Apr 21 01:01:59 PM PDT 24
Peak memory 218088 kb
Host smart-5733b482-f1db-425a-84da-b5418ad6abeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657432594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2657432594
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1666086347
Short name T202
Test name
Test status
Simulation time 244737886 ps
CPU time 1.09 seconds
Started Apr 21 01:01:53 PM PDT 24
Finished Apr 21 01:01:54 PM PDT 24
Peak memory 218200 kb
Host smart-55d47780-9f4a-419b-9b92-fa4a699af42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666086347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1666086347
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3077213690
Short name T188
Test name
Test status
Simulation time 148818839 ps
CPU time 0.85 seconds
Started Apr 21 01:01:46 PM PDT 24
Finished Apr 21 01:01:48 PM PDT 24
Peak memory 200652 kb
Host smart-8909081c-cb5d-45c0-bfb9-007ff6c5758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077213690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3077213690
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3133016202
Short name T106
Test name
Test status
Simulation time 1586284011 ps
CPU time 6.11 seconds
Started Apr 21 01:01:47 PM PDT 24
Finished Apr 21 01:01:53 PM PDT 24
Peak memory 201020 kb
Host smart-c54f50b5-655a-4370-b7b6-b066678b836a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133016202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3133016202
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1185800534
Short name T171
Test name
Test status
Simulation time 98080262 ps
CPU time 1 seconds
Started Apr 21 01:01:50 PM PDT 24
Finished Apr 21 01:01:51 PM PDT 24
Peak memory 200872 kb
Host smart-f03d49bd-6cdc-4983-889d-f2423389f8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185800534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1185800534
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.565816068
Short name T206
Test name
Test status
Simulation time 180746793 ps
CPU time 1.37 seconds
Started Apr 21 01:01:45 PM PDT 24
Finished Apr 21 01:01:47 PM PDT 24
Peak memory 200996 kb
Host smart-92a41764-a1ba-4ad5-a3f8-7331f6d62eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565816068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.565816068
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1027137793
Short name T518
Test name
Test status
Simulation time 3067972428 ps
CPU time 11.56 seconds
Started Apr 21 01:01:50 PM PDT 24
Finished Apr 21 01:02:02 PM PDT 24
Peak memory 200984 kb
Host smart-d72cc132-ceab-4eba-9542-68877aa4802c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027137793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1027137793
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2250351527
Short name T339
Test name
Test status
Simulation time 121071400 ps
CPU time 1.54 seconds
Started Apr 21 01:01:50 PM PDT 24
Finished Apr 21 01:01:52 PM PDT 24
Peak memory 209044 kb
Host smart-cab24e53-1768-4e01-9319-1f7bf53ea8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250351527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2250351527
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.797403339
Short name T150
Test name
Test status
Simulation time 91947617 ps
CPU time 0.93 seconds
Started Apr 21 01:01:46 PM PDT 24
Finished Apr 21 01:01:47 PM PDT 24
Peak memory 200808 kb
Host smart-019fb4dd-9bbe-49ab-9ba1-8fcedb0aa406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797403339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.797403339
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2429822771
Short name T391
Test name
Test status
Simulation time 184497056 ps
CPU time 0.95 seconds
Started Apr 21 01:01:50 PM PDT 24
Finished Apr 21 01:01:52 PM PDT 24
Peak memory 200632 kb
Host smart-20c226a1-bfbd-4c8f-86c3-12e67d3765fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429822771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2429822771
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3765011936
Short name T361
Test name
Test status
Simulation time 1908674931 ps
CPU time 6.74 seconds
Started Apr 21 01:01:54 PM PDT 24
Finished Apr 21 01:02:01 PM PDT 24
Peak memory 222628 kb
Host smart-4ae706be-5186-48de-9485-2f31141f4b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765011936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3765011936
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3432306095
Short name T489
Test name
Test status
Simulation time 246900192 ps
CPU time 1.02 seconds
Started Apr 21 01:01:51 PM PDT 24
Finished Apr 21 01:01:52 PM PDT 24
Peak memory 218160 kb
Host smart-83e5ecf6-c7ba-4999-9aad-6ebcbcae77e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432306095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3432306095
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3585159029
Short name T463
Test name
Test status
Simulation time 76405861 ps
CPU time 0.73 seconds
Started Apr 21 01:01:50 PM PDT 24
Finished Apr 21 01:01:51 PM PDT 24
Peak memory 200620 kb
Host smart-0b0c5a45-9df7-429a-a78e-0596ce6ec6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585159029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3585159029
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2657740313
Short name T499
Test name
Test status
Simulation time 801081038 ps
CPU time 4.3 seconds
Started Apr 21 01:01:47 PM PDT 24
Finished Apr 21 01:01:52 PM PDT 24
Peak memory 201000 kb
Host smart-dd557c45-e1ef-48e8-ac56-3dcb776907a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657740313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2657740313
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4124235391
Short name T410
Test name
Test status
Simulation time 149313758 ps
CPU time 1.16 seconds
Started Apr 21 01:01:52 PM PDT 24
Finished Apr 21 01:01:54 PM PDT 24
Peak memory 200836 kb
Host smart-8fb52c93-71f7-4c49-874a-b87af756fbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124235391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4124235391
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2496381694
Short name T358
Test name
Test status
Simulation time 266689734 ps
CPU time 1.54 seconds
Started Apr 21 01:01:53 PM PDT 24
Finished Apr 21 01:01:55 PM PDT 24
Peak memory 201004 kb
Host smart-dd6200f7-c2a3-414d-9b49-bc55f5a652d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496381694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2496381694
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.637616742
Short name T124
Test name
Test status
Simulation time 1871414726 ps
CPU time 7.46 seconds
Started Apr 21 01:01:53 PM PDT 24
Finished Apr 21 01:02:01 PM PDT 24
Peak memory 209232 kb
Host smart-9601a50c-6206-4298-b9a5-b7677f8974c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637616742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.637616742
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2385730481
Short name T351
Test name
Test status
Simulation time 269787530 ps
CPU time 1.84 seconds
Started Apr 21 01:01:50 PM PDT 24
Finished Apr 21 01:01:53 PM PDT 24
Peak memory 200772 kb
Host smart-dec96775-2495-46de-9437-4d51d5accad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385730481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2385730481
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1389460519
Short name T427
Test name
Test status
Simulation time 60741905 ps
CPU time 0.75 seconds
Started Apr 21 01:01:53 PM PDT 24
Finished Apr 21 01:01:54 PM PDT 24
Peak memory 200812 kb
Host smart-de47bfa4-d0b6-49a3-8f45-b709642dcd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389460519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1389460519
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3077472665
Short name T418
Test name
Test status
Simulation time 82483999 ps
CPU time 0.94 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:01:57 PM PDT 24
Peak memory 200628 kb
Host smart-89289f98-8f38-4276-b133-3769aa4c863e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077472665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3077472665
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1955529101
Short name T130
Test name
Test status
Simulation time 1901875704 ps
CPU time 6.77 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:02:02 PM PDT 24
Peak memory 218112 kb
Host smart-c2f28af1-e4b8-4cd3-bf25-1e4f3c8adb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955529101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1955529101
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2282138243
Short name T506
Test name
Test status
Simulation time 244194634 ps
CPU time 1.16 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:01:57 PM PDT 24
Peak memory 218108 kb
Host smart-d3691d89-f4f2-4065-84e1-2614ec889f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282138243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2282138243
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.116987222
Short name T365
Test name
Test status
Simulation time 122444441 ps
CPU time 0.79 seconds
Started Apr 21 01:01:50 PM PDT 24
Finished Apr 21 01:01:51 PM PDT 24
Peak memory 200644 kb
Host smart-f480e847-b04d-4e1b-8088-f8e61e3cf84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116987222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.116987222
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3058879914
Short name T263
Test name
Test status
Simulation time 1097784167 ps
CPU time 4.91 seconds
Started Apr 21 01:01:53 PM PDT 24
Finished Apr 21 01:01:58 PM PDT 24
Peak memory 201004 kb
Host smart-1d466d56-ac60-4b17-a6c2-10f7ea07a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058879914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3058879914
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1249177965
Short name T299
Test name
Test status
Simulation time 106869258 ps
CPU time 1.14 seconds
Started Apr 21 01:01:54 PM PDT 24
Finished Apr 21 01:01:56 PM PDT 24
Peak memory 200828 kb
Host smart-1ea84d47-d975-4e03-9656-41f85d38e771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249177965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1249177965
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1981583822
Short name T201
Test name
Test status
Simulation time 203400331 ps
CPU time 1.37 seconds
Started Apr 21 01:01:53 PM PDT 24
Finished Apr 21 01:01:55 PM PDT 24
Peak memory 200992 kb
Host smart-3ce4438c-1656-4923-b48e-37575890dcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981583822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1981583822
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1333043965
Short name T446
Test name
Test status
Simulation time 2096711686 ps
CPU time 8.83 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:02:04 PM PDT 24
Peak memory 200912 kb
Host smart-6a071145-2a5d-4da0-8687-611e40caf7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333043965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1333043965
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1271471074
Short name T225
Test name
Test status
Simulation time 148648176 ps
CPU time 1.8 seconds
Started Apr 21 01:01:55 PM PDT 24
Finished Apr 21 01:01:58 PM PDT 24
Peak memory 200752 kb
Host smart-dd722585-3472-4356-ac68-16394310b94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271471074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1271471074
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3218225877
Short name T335
Test name
Test status
Simulation time 110068660 ps
CPU time 0.91 seconds
Started Apr 21 01:01:49 PM PDT 24
Finished Apr 21 01:01:50 PM PDT 24
Peak memory 200836 kb
Host smart-4cd29eb0-0f4b-497b-9dc5-24e52ee27624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218225877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3218225877
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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