Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9089

1

T1

59

T4

28

T56

5

auto[1]

11781

1

T1

77

T2

4

T3

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6377	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	7078	1			T1	54		T2	2		T3	2
reset_info_cp[2]	3180	1			T1	23		T2	1		T3	1
reset_info_cp[4]	4261	1			T1	26		T2	1		T3	1
reset_info_cp[8]	126	1			T1	1		T59	1		T93	1
reset_info_cp[16]	107	1			T59	1		T37	1		T49	1
reset_info_cp[32]	115	1			T12	1		T56	1		T34	1
reset_info_cp[64]	122	1			T1	1		T64	1		T24	1
reset_info_cp[128]	124	1			T1	2		T56	1		T59	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3455	1			T1	22		T4	8		T59	22
reset_info_cp[1]	auto[1]	3003	1			T1	31		T2	1		T3	1
reset_info_cp[2]	auto[0]	1090	1			T1	10		T4	2		T34	6
reset_info_cp[2]	auto[1]	2090	1			T1	13		T2	1		T3	1
reset_info_cp[4]	auto[0]	1576	1			T1	12		T4	9		T34	9
reset_info_cp[4]	auto[1]	2685	1			T1	14		T2	1		T3	1
reset_info_cp[8]	auto[0]	54	1			T94	1		T95	1		T138	1
reset_info_cp[8]	auto[1]	72	1			T1	1		T59	1		T93	1
reset_info_cp[16]	auto[0]	41	1			T131	1		T132	1		T139	2
reset_info_cp[16]	auto[1]	66	1			T59	1		T37	1		T49	1
reset_info_cp[32]	auto[0]	44	1			T56	1		T34	1		T94	1
reset_info_cp[32]	auto[1]	71	1			T12	1		T41	1		T94	1
reset_info_cp[64]	auto[0]	44	1			T64	1		T138	1		T96	1
reset_info_cp[64]	auto[1]	78	1			T1	1		T24	1		T37	1
reset_info_cp[128]	auto[0]	54	1			T56	1		T51	2		T131	1
reset_info_cp[128]	auto[1]	70	1			T1	2		T59	1		T94	1