Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T537 /workspace/coverage/default/4.rstmgr_smoke.948159333 Apr 23 02:32:19 PM PDT 24 Apr 23 02:32:21 PM PDT 24 124329705 ps
T538 /workspace/coverage/default/13.rstmgr_alert_test.1556700463 Apr 23 02:33:00 PM PDT 24 Apr 23 02:33:01 PM PDT 24 67529828 ps
T539 /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.4133863813 Apr 23 02:34:18 PM PDT 24 Apr 23 02:34:27 PM PDT 24 1900461256 ps
T540 /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.923472974 Apr 23 02:33:35 PM PDT 24 Apr 23 02:33:37 PM PDT 24 176990797 ps
T541 /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1692219283 Apr 23 02:33:54 PM PDT 24 Apr 23 02:34:03 PM PDT 24 2384598796 ps
T79 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3396853397 Apr 23 02:25:50 PM PDT 24 Apr 23 02:25:52 PM PDT 24 259912494 ps
T73 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1005121237 Apr 23 02:25:53 PM PDT 24 Apr 23 02:25:55 PM PDT 24 120947431 ps
T74 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3556942039 Apr 23 02:25:43 PM PDT 24 Apr 23 02:25:45 PM PDT 24 148566590 ps
T75 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4097701259 Apr 23 02:25:54 PM PDT 24 Apr 23 02:25:56 PM PDT 24 69397854 ps
T77 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3183343567 Apr 23 02:25:41 PM PDT 24 Apr 23 02:25:42 PM PDT 24 68245468 ps
T76 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2614478437 Apr 23 02:25:39 PM PDT 24 Apr 23 02:25:41 PM PDT 24 152070914 ps
T78 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2339365475 Apr 23 02:25:35 PM PDT 24 Apr 23 02:25:37 PM PDT 24 124326058 ps
T137 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3308553259 Apr 23 02:25:38 PM PDT 24 Apr 23 02:25:49 PM PDT 24 2282725656 ps
T80 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2722977523 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:44 PM PDT 24 465907376 ps
T87 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1008360686 Apr 23 02:26:01 PM PDT 24 Apr 23 02:26:03 PM PDT 24 119402974 ps
T81 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3228769988 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:46 PM PDT 24 433900144 ps
T82 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3451565528 Apr 23 02:25:36 PM PDT 24 Apr 23 02:25:40 PM PDT 24 892154990 ps
T88 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2704978170 Apr 23 02:25:49 PM PDT 24 Apr 23 02:25:53 PM PDT 24 206041891 ps
T108 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.95693401 Apr 23 02:26:00 PM PDT 24 Apr 23 02:26:02 PM PDT 24 104986622 ps
T109 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2399765520 Apr 23 02:25:51 PM PDT 24 Apr 23 02:25:53 PM PDT 24 270281091 ps
T110 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3798909161 Apr 23 02:25:44 PM PDT 24 Apr 23 02:25:46 PM PDT 24 86742227 ps
T111 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1226346579 Apr 23 02:25:51 PM PDT 24 Apr 23 02:25:53 PM PDT 24 175326486 ps
T112 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1345537689 Apr 23 02:25:45 PM PDT 24 Apr 23 02:25:47 PM PDT 24 81527637 ps
T89 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.294414659 Apr 23 02:25:46 PM PDT 24 Apr 23 02:25:47 PM PDT 24 139204989 ps
T90 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3043177065 Apr 23 02:25:46 PM PDT 24 Apr 23 02:25:50 PM PDT 24 454080728 ps
T91 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1019908199 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:45 PM PDT 24 186567961 ps
T113 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3376819508 Apr 23 02:25:47 PM PDT 24 Apr 23 02:25:49 PM PDT 24 226329715 ps
T92 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.366567461 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:44 PM PDT 24 153529494 ps
T542 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.544906479 Apr 23 02:25:46 PM PDT 24 Apr 23 02:25:48 PM PDT 24 187482944 ps
T114 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.375166566 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:53 PM PDT 24 78198974 ps
T115 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2669982877 Apr 23 02:25:39 PM PDT 24 Apr 23 02:25:42 PM PDT 24 786195465 ps
T118 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2542803281 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:57 PM PDT 24 876535899 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3555892807 Apr 23 02:25:39 PM PDT 24 Apr 23 02:25:43 PM PDT 24 474901021 ps
T544 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1498257105 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:44 PM PDT 24 130859312 ps
T545 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1833268739 Apr 23 02:25:43 PM PDT 24 Apr 23 02:25:46 PM PDT 24 190023229 ps
T546 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2507339734 Apr 23 02:25:49 PM PDT 24 Apr 23 02:25:50 PM PDT 24 89035781 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3333211672 Apr 23 02:25:40 PM PDT 24 Apr 23 02:25:48 PM PDT 24 1548783218 ps
T548 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2600157521 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:54 PM PDT 24 611321535 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.228540859 Apr 23 02:25:36 PM PDT 24 Apr 23 02:25:37 PM PDT 24 71572342 ps
T550 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.223459236 Apr 23 02:25:44 PM PDT 24 Apr 23 02:25:45 PM PDT 24 68615321 ps
T551 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3046889258 Apr 23 02:25:53 PM PDT 24 Apr 23 02:25:56 PM PDT 24 533361777 ps
T125 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2133052033 Apr 23 02:25:50 PM PDT 24 Apr 23 02:25:53 PM PDT 24 142451872 ps
T552 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3972647237 Apr 23 02:25:44 PM PDT 24 Apr 23 02:25:46 PM PDT 24 196324380 ps
T553 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1961229002 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:55 PM PDT 24 465702205 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1876389260 Apr 23 02:25:39 PM PDT 24 Apr 23 02:25:41 PM PDT 24 267360225 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.741196248 Apr 23 02:25:36 PM PDT 24 Apr 23 02:25:38 PM PDT 24 191533450 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3185314645 Apr 23 02:25:38 PM PDT 24 Apr 23 02:25:39 PM PDT 24 125290429 ps
T557 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1689094288 Apr 23 02:25:48 PM PDT 24 Apr 23 02:25:50 PM PDT 24 132612835 ps
T558 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1317549990 Apr 23 02:25:47 PM PDT 24 Apr 23 02:25:48 PM PDT 24 132372240 ps
T559 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2896640347 Apr 23 02:25:49 PM PDT 24 Apr 23 02:25:50 PM PDT 24 79366090 ps
T560 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4263075664 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:54 PM PDT 24 107619739 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3468216824 Apr 23 02:25:40 PM PDT 24 Apr 23 02:25:42 PM PDT 24 119031602 ps
T562 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1256259989 Apr 23 02:25:46 PM PDT 24 Apr 23 02:25:49 PM PDT 24 174451505 ps
T563 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3678867322 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:44 PM PDT 24 121748668 ps
T564 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3524882573 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:55 PM PDT 24 253237599 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1711825860 Apr 23 02:25:46 PM PDT 24 Apr 23 02:25:47 PM PDT 24 65022272 ps
T566 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.170898717 Apr 23 02:25:55 PM PDT 24 Apr 23 02:25:58 PM PDT 24 167826727 ps
T116 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2042026591 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:56 PM PDT 24 818501315 ps
T567 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4100348003 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:54 PM PDT 24 71485853 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.918240316 Apr 23 02:25:43 PM PDT 24 Apr 23 02:25:47 PM PDT 24 542158160 ps
T569 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1695685738 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:44 PM PDT 24 197733525 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.33809909 Apr 23 02:25:41 PM PDT 24 Apr 23 02:25:43 PM PDT 24 227082391 ps
T571 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2623954595 Apr 23 02:25:48 PM PDT 24 Apr 23 02:25:51 PM PDT 24 140445919 ps
T572 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3054893130 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:44 PM PDT 24 90488394 ps
T120 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3794979524 Apr 23 02:25:43 PM PDT 24 Apr 23 02:25:48 PM PDT 24 789997334 ps
T121 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3932075433 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:45 PM PDT 24 428532179 ps
T573 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.930053867 Apr 23 02:25:44 PM PDT 24 Apr 23 02:25:46 PM PDT 24 65786194 ps
T574 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4161588765 Apr 23 02:25:36 PM PDT 24 Apr 23 02:25:39 PM PDT 24 345036834 ps
T575 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2918628414 Apr 23 02:25:44 PM PDT 24 Apr 23 02:25:48 PM PDT 24 537984125 ps
T576 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.988527764 Apr 23 02:25:41 PM PDT 24 Apr 23 02:25:46 PM PDT 24 812167759 ps
T136 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2381543784 Apr 23 02:25:48 PM PDT 24 Apr 23 02:25:50 PM PDT 24 430043018 ps
T577 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.856597588 Apr 23 02:25:39 PM PDT 24 Apr 23 02:25:40 PM PDT 24 91398558 ps
T578 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3718426591 Apr 23 02:25:47 PM PDT 24 Apr 23 02:25:49 PM PDT 24 106536114 ps
T579 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.993439988 Apr 23 02:25:37 PM PDT 24 Apr 23 02:25:43 PM PDT 24 490709764 ps
T580 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2933459834 Apr 23 02:25:37 PM PDT 24 Apr 23 02:25:39 PM PDT 24 196791798 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2848355796 Apr 23 02:25:40 PM PDT 24 Apr 23 02:25:41 PM PDT 24 98745996 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1405306529 Apr 23 02:25:37 PM PDT 24 Apr 23 02:25:40 PM PDT 24 356611728 ps
T583 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.299668075 Apr 23 02:25:49 PM PDT 24 Apr 23 02:25:51 PM PDT 24 411334523 ps
T584 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2132053955 Apr 23 02:25:53 PM PDT 24 Apr 23 02:25:55 PM PDT 24 120648665 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2766752172 Apr 23 02:25:53 PM PDT 24 Apr 23 02:25:55 PM PDT 24 207408730 ps
T122 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2727149671 Apr 23 02:25:51 PM PDT 24 Apr 23 02:25:54 PM PDT 24 489234618 ps
T586 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2182212372 Apr 23 02:25:49 PM PDT 24 Apr 23 02:25:51 PM PDT 24 207162480 ps
T587 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.710466329 Apr 23 02:25:43 PM PDT 24 Apr 23 02:25:45 PM PDT 24 93317660 ps
T588 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3041213545 Apr 23 02:25:36 PM PDT 24 Apr 23 02:25:38 PM PDT 24 65996315 ps
T123 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1498113214 Apr 23 02:25:44 PM PDT 24 Apr 23 02:25:48 PM PDT 24 924005419 ps
T589 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1909861319 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:54 PM PDT 24 223415037 ps
T590 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3717041925 Apr 23 02:25:53 PM PDT 24 Apr 23 02:25:55 PM PDT 24 75778113 ps
T124 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2546203842 Apr 23 02:25:44 PM PDT 24 Apr 23 02:25:48 PM PDT 24 773995149 ps
T591 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.815324136 Apr 23 02:25:44 PM PDT 24 Apr 23 02:25:48 PM PDT 24 210576986 ps
T592 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3831970438 Apr 23 02:25:54 PM PDT 24 Apr 23 02:25:56 PM PDT 24 176952898 ps
T593 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.788142804 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:44 PM PDT 24 216408382 ps
T119 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1682227113 Apr 23 02:25:43 PM PDT 24 Apr 23 02:25:47 PM PDT 24 876034460 ps
T594 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1268352458 Apr 23 02:25:53 PM PDT 24 Apr 23 02:25:55 PM PDT 24 92497195 ps
T595 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1070558154 Apr 23 02:25:44 PM PDT 24 Apr 23 02:25:47 PM PDT 24 176025020 ps
T596 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1180011990 Apr 23 02:25:37 PM PDT 24 Apr 23 02:25:39 PM PDT 24 83313297 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.234344635 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:44 PM PDT 24 120030081 ps
T598 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3098486133 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:44 PM PDT 24 78612587 ps
T599 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1418728961 Apr 23 02:25:48 PM PDT 24 Apr 23 02:25:50 PM PDT 24 491367835 ps
T600 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1566818473 Apr 23 02:25:37 PM PDT 24 Apr 23 02:25:38 PM PDT 24 98908298 ps
T601 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1703399975 Apr 23 02:25:34 PM PDT 24 Apr 23 02:25:36 PM PDT 24 102287552 ps
T602 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1137059045 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:52 PM PDT 24 2285043063 ps
T603 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3127941607 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:53 PM PDT 24 81111259 ps
T604 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1849144771 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:54 PM PDT 24 118958151 ps
T605 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.745005127 Apr 23 02:25:46 PM PDT 24 Apr 23 02:25:48 PM PDT 24 83946738 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1214758919 Apr 23 02:25:43 PM PDT 24 Apr 23 02:25:44 PM PDT 24 82740837 ps
T607 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2433756509 Apr 23 02:25:41 PM PDT 24 Apr 23 02:25:42 PM PDT 24 126204613 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1271411351 Apr 23 02:25:40 PM PDT 24 Apr 23 02:25:41 PM PDT 24 102410357 ps
T609 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3592666053 Apr 23 02:25:53 PM PDT 24 Apr 23 02:25:55 PM PDT 24 81537307 ps
T610 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.644273271 Apr 23 02:25:34 PM PDT 24 Apr 23 02:25:38 PM PDT 24 910161751 ps
T611 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4078808565 Apr 23 02:25:47 PM PDT 24 Apr 23 02:25:49 PM PDT 24 94694783 ps
T612 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.44022163 Apr 23 02:25:42 PM PDT 24 Apr 23 02:25:45 PM PDT 24 205331306 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.809728820 Apr 23 02:25:41 PM PDT 24 Apr 23 02:25:44 PM PDT 24 284195681 ps
T117 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1671326529 Apr 23 02:25:47 PM PDT 24 Apr 23 02:25:50 PM PDT 24 781624079 ps
T614 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3614286407 Apr 23 02:25:51 PM PDT 24 Apr 23 02:25:54 PM PDT 24 194778010 ps
T615 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4182644716 Apr 23 02:25:45 PM PDT 24 Apr 23 02:25:46 PM PDT 24 65650474 ps
T616 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.902691995 Apr 23 02:25:49 PM PDT 24 Apr 23 02:25:51 PM PDT 24 187576651 ps
T617 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4143344268 Apr 23 02:25:52 PM PDT 24 Apr 23 02:25:56 PM PDT 24 529121853 ps
T618 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1799094418 Apr 23 02:25:43 PM PDT 24 Apr 23 02:25:44 PM PDT 24 99321676 ps
T619 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4096543354 Apr 23 02:25:38 PM PDT 24 Apr 23 02:25:40 PM PDT 24 112398950 ps
T620 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4016970043 Apr 23 02:25:38 PM PDT 24 Apr 23 02:25:42 PM PDT 24 773610722 ps

Test location /workspace/coverage/default/3.rstmgr_stress_all.1458023871
Short name T1
Test name
Test status
Simulation time 2826052763 ps
CPU time 14.04 seconds
Started Apr 23 02:32:19 PM PDT 24
Finished Apr 23 02:32:34 PM PDT 24
Peak memory 200940 kb
Host smart-8d5641bd-2ae8-43ea-9c16-c0202fbafec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458023871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1458023871
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.399706488
Short name T6
Test name
Test status
Simulation time 131826059 ps
CPU time 1.74 seconds
Started Apr 23 02:34:01 PM PDT 24
Finished Apr 23 02:34:03 PM PDT 24
Peak memory 209032 kb
Host smart-ed6cbe1d-5496-4608-8082-3ff35eedbb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399706488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.399706488
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3451565528
Short name T82
Test name
Test status
Simulation time 892154990 ps
CPU time 2.84 seconds
Started Apr 23 02:25:36 PM PDT 24
Finished Apr 23 02:25:40 PM PDT 24
Peak memory 201020 kb
Host smart-b3a00fbe-5985-4430-9e79-3d50ee44c7f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451565528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3451565528
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3984514055
Short name T55
Test name
Test status
Simulation time 8294010478 ps
CPU time 13.37 seconds
Started Apr 23 02:32:05 PM PDT 24
Finished Apr 23 02:32:19 PM PDT 24
Peak memory 217580 kb
Host smart-7c0b932e-3e7f-4572-a151-2a93b891b7d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984514055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3984514055
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.690420637
Short name T59
Test name
Test status
Simulation time 2358378990 ps
CPU time 7.71 seconds
Started Apr 23 02:33:24 PM PDT 24
Finished Apr 23 02:33:32 PM PDT 24
Peak memory 218632 kb
Host smart-00ca39df-d7ed-4646-9ebf-8a06621ffe8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690420637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.690420637
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3228769988
Short name T81
Test name
Test status
Simulation time 433900144 ps
CPU time 2.93 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:46 PM PDT 24
Peak memory 209324 kb
Host smart-7c1bb933-e795-41aa-a767-9e336697b5d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228769988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3228769988
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2893028098
Short name T98
Test name
Test status
Simulation time 3415388042 ps
CPU time 12.43 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:50 PM PDT 24
Peak memory 201060 kb
Host smart-6a8b6c55-4d50-4513-b5ff-a9ac47b8f5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893028098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2893028098
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2003029862
Short name T138
Test name
Test status
Simulation time 160081321 ps
CPU time 1.19 seconds
Started Apr 23 02:32:07 PM PDT 24
Finished Apr 23 02:32:08 PM PDT 24
Peak memory 201072 kb
Host smart-5f056086-fd59-4a26-a224-c7bb3efd2c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003029862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2003029862
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2282933080
Short name T40
Test name
Test status
Simulation time 55953405 ps
CPU time 0.78 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 200632 kb
Host smart-e2e6e489-bb96-480e-9f7b-e4419682a71a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282933080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2282933080
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3764853768
Short name T143
Test name
Test status
Simulation time 182782376 ps
CPU time 1.23 seconds
Started Apr 23 02:32:48 PM PDT 24
Finished Apr 23 02:32:50 PM PDT 24
Peak memory 200808 kb
Host smart-3c4e8cdb-861a-4ea0-a776-75c52b50721d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764853768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3764853768
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3009287709
Short name T27
Test name
Test status
Simulation time 1888048221 ps
CPU time 7.28 seconds
Started Apr 23 02:32:22 PM PDT 24
Finished Apr 23 02:32:30 PM PDT 24
Peak memory 218624 kb
Host smart-0c3cb631-5845-46b1-9abe-d7d895ec2de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009287709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3009287709
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1682227113
Short name T119
Test name
Test status
Simulation time 876034460 ps
CPU time 2.99 seconds
Started Apr 23 02:25:43 PM PDT 24
Finished Apr 23 02:25:47 PM PDT 24
Peak memory 201080 kb
Host smart-521f4022-ba88-4531-87c8-185b08510205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682227113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1682227113
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.366567461
Short name T92
Test name
Test status
Simulation time 153529494 ps
CPU time 2.09 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 209284 kb
Host smart-81b94de8-343c-482f-96ab-74d2877c81d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366567461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.366567461
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.4100735283
Short name T319
Test name
Test status
Simulation time 1223507875 ps
CPU time 5.7 seconds
Started Apr 23 02:32:03 PM PDT 24
Finished Apr 23 02:32:09 PM PDT 24
Peak memory 222272 kb
Host smart-6fc0b734-6f12-4817-a513-a2c3000c41c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100735283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4100735283
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4016970043
Short name T620
Test name
Test status
Simulation time 773610722 ps
CPU time 3.04 seconds
Started Apr 23 02:25:38 PM PDT 24
Finished Apr 23 02:25:42 PM PDT 24
Peak memory 201144 kb
Host smart-48495789-20ca-41e3-9646-1233d5e1a5f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016970043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.4016970043
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2339365475
Short name T78
Test name
Test status
Simulation time 124326058 ps
CPU time 1.09 seconds
Started Apr 23 02:25:35 PM PDT 24
Finished Apr 23 02:25:37 PM PDT 24
Peak memory 200920 kb
Host smart-7bf9d713-fb2c-4b2f-8037-7f773e388dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339365475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2339365475
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3870192309
Short name T19
Test name
Test status
Simulation time 196858574 ps
CPU time 0.89 seconds
Started Apr 23 02:32:57 PM PDT 24
Finished Apr 23 02:32:58 PM PDT 24
Peak memory 200668 kb
Host smart-d4000c72-4794-4afa-918e-e40d42bc6eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870192309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3870192309
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.996294027
Short name T38
Test name
Test status
Simulation time 1529175319 ps
CPU time 6.08 seconds
Started Apr 23 02:32:58 PM PDT 24
Finished Apr 23 02:33:05 PM PDT 24
Peak memory 201004 kb
Host smart-3bafcdf5-7f03-4f54-a080-ce4f366c3f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996294027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.996294027
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.776296447
Short name T41
Test name
Test status
Simulation time 1228133476 ps
CPU time 5.66 seconds
Started Apr 23 02:31:52 PM PDT 24
Finished Apr 23 02:31:58 PM PDT 24
Peak memory 218560 kb
Host smart-ec72ba0f-fc93-4e0f-b06b-7c3896ab6f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776296447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.776296447
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3846512069
Short name T180
Test name
Test status
Simulation time 243666215 ps
CPU time 1.13 seconds
Started Apr 23 02:32:56 PM PDT 24
Finished Apr 23 02:32:57 PM PDT 24
Peak memory 218140 kb
Host smart-9b26cd55-5e65-459e-aeab-b5266cff0dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846512069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3846512069
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2546203842
Short name T124
Test name
Test status
Simulation time 773995149 ps
CPU time 3.1 seconds
Started Apr 23 02:25:44 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 201136 kb
Host smart-a7d7abd2-d0bc-4f2f-b380-7c4f70f5abfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546203842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2546203842
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2933459834
Short name T580
Test name
Test status
Simulation time 196791798 ps
CPU time 1.53 seconds
Started Apr 23 02:25:37 PM PDT 24
Finished Apr 23 02:25:39 PM PDT 24
Peak memory 201032 kb
Host smart-c76b504d-c373-47b2-968e-b58d11e6e458
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933459834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
933459834
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3333211672
Short name T547
Test name
Test status
Simulation time 1548783218 ps
CPU time 7.94 seconds
Started Apr 23 02:25:40 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 201096 kb
Host smart-9e6b8a47-c86a-45a9-9fc8-41decff63953
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333211672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
333211672
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1566818473
Short name T600
Test name
Test status
Simulation time 98908298 ps
CPU time 0.87 seconds
Started Apr 23 02:25:37 PM PDT 24
Finished Apr 23 02:25:38 PM PDT 24
Peak memory 200820 kb
Host smart-85026923-6f4f-4d08-a1c3-4874216567b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566818473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
566818473
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.741196248
Short name T555
Test name
Test status
Simulation time 191533450 ps
CPU time 1.23 seconds
Started Apr 23 02:25:36 PM PDT 24
Finished Apr 23 02:25:38 PM PDT 24
Peak memory 209212 kb
Host smart-9d9884ec-d393-49ce-bab0-6a8dc4acb92b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741196248 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.741196248
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3041213545
Short name T588
Test name
Test status
Simulation time 65996315 ps
CPU time 0.82 seconds
Started Apr 23 02:25:36 PM PDT 24
Finished Apr 23 02:25:38 PM PDT 24
Peak memory 200856 kb
Host smart-30cacdd8-a0ea-4856-acee-9ead291b6fec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041213545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3041213545
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1405306529
Short name T582
Test name
Test status
Simulation time 356611728 ps
CPU time 2.66 seconds
Started Apr 23 02:25:37 PM PDT 24
Finished Apr 23 02:25:40 PM PDT 24
Peak memory 209268 kb
Host smart-54ff6a59-bed5-495f-9a5e-7274f209cae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405306529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1405306529
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.644273271
Short name T610
Test name
Test status
Simulation time 910161751 ps
CPU time 3.02 seconds
Started Apr 23 02:25:34 PM PDT 24
Finished Apr 23 02:25:38 PM PDT 24
Peak memory 201116 kb
Host smart-8409c079-905b-4996-bd98-59e33f9c29f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644273271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
644273271
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4161588765
Short name T574
Test name
Test status
Simulation time 345036834 ps
CPU time 2.29 seconds
Started Apr 23 02:25:36 PM PDT 24
Finished Apr 23 02:25:39 PM PDT 24
Peak memory 201068 kb
Host smart-756aec34-ac09-46f3-a062-f934f9e01a8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161588765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.4
161588765
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3308553259
Short name T137
Test name
Test status
Simulation time 2282725656 ps
CPU time 9.81 seconds
Started Apr 23 02:25:38 PM PDT 24
Finished Apr 23 02:25:49 PM PDT 24
Peak memory 201240 kb
Host smart-bd889eb0-c6b4-4c50-8f19-ab081f753a76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308553259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
308553259
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1180011990
Short name T596
Test name
Test status
Simulation time 83313297 ps
CPU time 0.79 seconds
Started Apr 23 02:25:37 PM PDT 24
Finished Apr 23 02:25:39 PM PDT 24
Peak memory 200844 kb
Host smart-e7225473-200a-4b5f-a31e-41a6d29db10f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180011990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
180011990
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3185314645
Short name T556
Test name
Test status
Simulation time 125290429 ps
CPU time 0.95 seconds
Started Apr 23 02:25:38 PM PDT 24
Finished Apr 23 02:25:39 PM PDT 24
Peak memory 200916 kb
Host smart-958b8f58-1cd8-40ea-a66f-3ab26ed1e44a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185314645 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3185314645
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.228540859
Short name T549
Test name
Test status
Simulation time 71572342 ps
CPU time 0.78 seconds
Started Apr 23 02:25:36 PM PDT 24
Finished Apr 23 02:25:37 PM PDT 24
Peak memory 200848 kb
Host smart-064d2b64-269f-49a4-aa2d-675fa88f2dbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228540859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.228540859
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1876389260
Short name T554
Test name
Test status
Simulation time 267360225 ps
CPU time 1.54 seconds
Started Apr 23 02:25:39 PM PDT 24
Finished Apr 23 02:25:41 PM PDT 24
Peak memory 201048 kb
Host smart-7c5baad0-a6c1-4269-9b1a-5e061ce595b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876389260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1876389260
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1703399975
Short name T601
Test name
Test status
Simulation time 102287552 ps
CPU time 1.34 seconds
Started Apr 23 02:25:34 PM PDT 24
Finished Apr 23 02:25:36 PM PDT 24
Peak memory 209224 kb
Host smart-11318d5e-5abc-40e6-a95c-35470ec7bb48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703399975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1703399975
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1317549990
Short name T558
Test name
Test status
Simulation time 132372240 ps
CPU time 1.05 seconds
Started Apr 23 02:25:47 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 209188 kb
Host smart-170a53aa-3ad6-4c51-a7a1-9ea5033538eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317549990 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1317549990
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.745005127
Short name T605
Test name
Test status
Simulation time 83946738 ps
CPU time 0.9 seconds
Started Apr 23 02:25:46 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 200864 kb
Host smart-78013fa4-05a6-4d69-9291-8a37583e8bb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745005127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.745005127
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1345537689
Short name T112
Test name
Test status
Simulation time 81527637 ps
CPU time 0.95 seconds
Started Apr 23 02:25:45 PM PDT 24
Finished Apr 23 02:25:47 PM PDT 24
Peak memory 200928 kb
Host smart-5ffd8d17-6080-4abf-94c0-4029a6770e12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345537689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1345537689
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2918628414
Short name T575
Test name
Test status
Simulation time 537984125 ps
CPU time 3.68 seconds
Started Apr 23 02:25:44 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 201156 kb
Host smart-9c21c0a1-13c4-4684-a05f-23d6c4313bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918628414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2918628414
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3794979524
Short name T120
Test name
Test status
Simulation time 789997334 ps
CPU time 3.13 seconds
Started Apr 23 02:25:43 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 201160 kb
Host smart-78eb4044-7b58-4bbc-99f6-33793af512d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794979524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3794979524
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.902691995
Short name T616
Test name
Test status
Simulation time 187576651 ps
CPU time 1.28 seconds
Started Apr 23 02:25:49 PM PDT 24
Finished Apr 23 02:25:51 PM PDT 24
Peak memory 209232 kb
Host smart-d923facf-6815-4d17-818c-5320979a164b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902691995 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.902691995
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4182644716
Short name T615
Test name
Test status
Simulation time 65650474 ps
CPU time 0.82 seconds
Started Apr 23 02:25:45 PM PDT 24
Finished Apr 23 02:25:46 PM PDT 24
Peak memory 200864 kb
Host smart-f124a682-86f5-4456-a3b4-498c659a8071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182644716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4182644716
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3718426591
Short name T578
Test name
Test status
Simulation time 106536114 ps
CPU time 1.2 seconds
Started Apr 23 02:25:47 PM PDT 24
Finished Apr 23 02:25:49 PM PDT 24
Peak memory 201120 kb
Host smart-b381307f-b676-47fa-87ef-5fcc589ac716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718426591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3718426591
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2623954595
Short name T571
Test name
Test status
Simulation time 140445919 ps
CPU time 1.99 seconds
Started Apr 23 02:25:48 PM PDT 24
Finished Apr 23 02:25:51 PM PDT 24
Peak memory 209316 kb
Host smart-8ea725f4-7bb5-4e6a-8507-b15f76136cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623954595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2623954595
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1418728961
Short name T599
Test name
Test status
Simulation time 491367835 ps
CPU time 2.21 seconds
Started Apr 23 02:25:48 PM PDT 24
Finished Apr 23 02:25:50 PM PDT 24
Peak memory 201196 kb
Host smart-bc919203-b33e-418a-be6f-c6455f6482d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418728961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1418728961
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.544906479
Short name T542
Test name
Test status
Simulation time 187482944 ps
CPU time 1.7 seconds
Started Apr 23 02:25:46 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 213044 kb
Host smart-eb3a3f6d-ca7a-43e1-b7e8-55cd018f8e7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544906479 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.544906479
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2507339734
Short name T546
Test name
Test status
Simulation time 89035781 ps
CPU time 0.89 seconds
Started Apr 23 02:25:49 PM PDT 24
Finished Apr 23 02:25:50 PM PDT 24
Peak memory 200884 kb
Host smart-ad73addb-febe-40a8-8362-9779766174bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507339734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2507339734
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3376819508
Short name T113
Test name
Test status
Simulation time 226329715 ps
CPU time 1.57 seconds
Started Apr 23 02:25:47 PM PDT 24
Finished Apr 23 02:25:49 PM PDT 24
Peak memory 209268 kb
Host smart-bda7195f-9626-458d-8345-c60da2b72fdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376819508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3376819508
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4078808565
Short name T611
Test name
Test status
Simulation time 94694783 ps
CPU time 1.24 seconds
Started Apr 23 02:25:47 PM PDT 24
Finished Apr 23 02:25:49 PM PDT 24
Peak memory 209148 kb
Host smart-ef6ddad5-a453-44a7-97a3-401e6bab6bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078808565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4078808565
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2381543784
Short name T136
Test name
Test status
Simulation time 430043018 ps
CPU time 1.79 seconds
Started Apr 23 02:25:48 PM PDT 24
Finished Apr 23 02:25:50 PM PDT 24
Peak memory 201160 kb
Host smart-d58a3bb8-5d13-46bf-9227-4263dca7528e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381543784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2381543784
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1689094288
Short name T557
Test name
Test status
Simulation time 132612835 ps
CPU time 1.39 seconds
Started Apr 23 02:25:48 PM PDT 24
Finished Apr 23 02:25:50 PM PDT 24
Peak memory 209320 kb
Host smart-26ccf5b7-7230-46d7-ba27-d9b14e1d0b46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689094288 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1689094288
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2896640347
Short name T559
Test name
Test status
Simulation time 79366090 ps
CPU time 0.83 seconds
Started Apr 23 02:25:49 PM PDT 24
Finished Apr 23 02:25:50 PM PDT 24
Peak memory 200952 kb
Host smart-bff2d74c-8b2d-40d6-87a0-7979bdf616e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896640347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2896640347
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2182212372
Short name T586
Test name
Test status
Simulation time 207162480 ps
CPU time 1.47 seconds
Started Apr 23 02:25:49 PM PDT 24
Finished Apr 23 02:25:51 PM PDT 24
Peak memory 201144 kb
Host smart-a4bb493f-a74e-4b26-974a-befa4e636d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182212372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2182212372
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3396853397
Short name T79
Test name
Test status
Simulation time 259912494 ps
CPU time 2.04 seconds
Started Apr 23 02:25:50 PM PDT 24
Finished Apr 23 02:25:52 PM PDT 24
Peak memory 209344 kb
Host smart-9fc37a24-b09c-44c2-a0d9-f0905d5e2818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396853397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3396853397
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2542803281
Short name T118
Test name
Test status
Simulation time 876535899 ps
CPU time 3.32 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:57 PM PDT 24
Peak memory 201196 kb
Host smart-dd070535-8f82-4fca-9c40-b7923c159a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542803281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2542803281
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4263075664
Short name T560
Test name
Test status
Simulation time 107619739 ps
CPU time 1.07 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:54 PM PDT 24
Peak memory 212064 kb
Host smart-b0132ccc-a863-4c15-8433-239382a08533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263075664 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4263075664
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4097701259
Short name T75
Test name
Test status
Simulation time 69397854 ps
CPU time 0.78 seconds
Started Apr 23 02:25:54 PM PDT 24
Finished Apr 23 02:25:56 PM PDT 24
Peak memory 200844 kb
Host smart-bff0884d-7d6c-45f3-8e5a-0e670240d389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097701259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.4097701259
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1849144771
Short name T604
Test name
Test status
Simulation time 118958151 ps
CPU time 1.05 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:54 PM PDT 24
Peak memory 200892 kb
Host smart-607d679b-cf6a-4093-8ba6-b2b198ff331f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849144771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1849144771
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2133052033
Short name T125
Test name
Test status
Simulation time 142451872 ps
CPU time 2.06 seconds
Started Apr 23 02:25:50 PM PDT 24
Finished Apr 23 02:25:53 PM PDT 24
Peak memory 217360 kb
Host smart-f703bd86-7997-46f1-897a-fea2012e07a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133052033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2133052033
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2600157521
Short name T548
Test name
Test status
Simulation time 611321535 ps
CPU time 2.13 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:54 PM PDT 24
Peak memory 201124 kb
Host smart-adf440f1-8901-4540-8a83-b17a8c82072e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600157521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2600157521
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1005121237
Short name T73
Test name
Test status
Simulation time 120947431 ps
CPU time 1.31 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:25:55 PM PDT 24
Peak memory 208576 kb
Host smart-b17dc6bf-1558-4bd3-b85f-b5a46de02d82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005121237 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1005121237
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3717041925
Short name T590
Test name
Test status
Simulation time 75778113 ps
CPU time 0.79 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:25:55 PM PDT 24
Peak memory 200756 kb
Host smart-dd796804-01d0-4514-a673-e2507672d208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717041925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3717041925
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3127941607
Short name T603
Test name
Test status
Simulation time 81111259 ps
CPU time 1.04 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:53 PM PDT 24
Peak memory 200892 kb
Host smart-dee9fc6f-cb97-4179-bc0c-ba224383ccc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127941607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3127941607
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2766752172
Short name T585
Test name
Test status
Simulation time 207408730 ps
CPU time 1.76 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:25:55 PM PDT 24
Peak memory 211504 kb
Host smart-2edbdafa-329b-4fa4-8a54-e4e993bf5fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766752172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2766752172
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.299668075
Short name T583
Test name
Test status
Simulation time 411334523 ps
CPU time 1.67 seconds
Started Apr 23 02:25:49 PM PDT 24
Finished Apr 23 02:25:51 PM PDT 24
Peak memory 201148 kb
Host smart-51a521bc-9dd6-429e-b161-24a91f0ff449
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299668075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.299668075
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2132053955
Short name T584
Test name
Test status
Simulation time 120648665 ps
CPU time 0.98 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:25:55 PM PDT 24
Peak memory 200444 kb
Host smart-fa63b1c8-1459-4b2e-9fe2-85c9cb8b2991
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132053955 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2132053955
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3592666053
Short name T609
Test name
Test status
Simulation time 81537307 ps
CPU time 0.9 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:25:55 PM PDT 24
Peak memory 199868 kb
Host smart-a660bae5-d7b6-443a-8ad3-32f9d0fef98c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592666053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3592666053
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1226346579
Short name T111
Test name
Test status
Simulation time 175326486 ps
CPU time 1.2 seconds
Started Apr 23 02:25:51 PM PDT 24
Finished Apr 23 02:25:53 PM PDT 24
Peak memory 200928 kb
Host smart-f0a9e313-14a6-4ee7-b989-5262aafa20a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226346579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1226346579
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4143344268
Short name T617
Test name
Test status
Simulation time 529121853 ps
CPU time 3.2 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:56 PM PDT 24
Peak memory 217392 kb
Host smart-41068c73-7dd1-4e35-90f8-651b1e032641
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143344268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4143344268
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3046889258
Short name T551
Test name
Test status
Simulation time 533361777 ps
CPU time 1.85 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:25:56 PM PDT 24
Peak memory 201092 kb
Host smart-8ee352a9-0caa-4373-8476-f726f1171a83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046889258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3046889258
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3614286407
Short name T614
Test name
Test status
Simulation time 194778010 ps
CPU time 1.95 seconds
Started Apr 23 02:25:51 PM PDT 24
Finished Apr 23 02:25:54 PM PDT 24
Peak memory 209452 kb
Host smart-d9f38317-c31f-4f03-9791-db02998566a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614286407 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3614286407
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.375166566
Short name T114
Test name
Test status
Simulation time 78198974 ps
CPU time 0.82 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:53 PM PDT 24
Peak memory 200856 kb
Host smart-e5397dbb-a04d-4371-8328-da40ca71bf99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375166566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.375166566
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2399765520
Short name T109
Test name
Test status
Simulation time 270281091 ps
CPU time 1.56 seconds
Started Apr 23 02:25:51 PM PDT 24
Finished Apr 23 02:25:53 PM PDT 24
Peak memory 201092 kb
Host smart-392270b7-c11c-4209-ba44-c66e21430de9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399765520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2399765520
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2704978170
Short name T88
Test name
Test status
Simulation time 206041891 ps
CPU time 3.03 seconds
Started Apr 23 02:25:49 PM PDT 24
Finished Apr 23 02:25:53 PM PDT 24
Peak memory 209304 kb
Host smart-f8c5e917-2077-4590-905b-d3167f065955
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704978170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2704978170
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2727149671
Short name T122
Test name
Test status
Simulation time 489234618 ps
CPU time 2.04 seconds
Started Apr 23 02:25:51 PM PDT 24
Finished Apr 23 02:25:54 PM PDT 24
Peak memory 201096 kb
Host smart-0405db3d-a340-4b23-94f4-ee35e8ec6301
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727149671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2727149671
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1008360686
Short name T87
Test name
Test status
Simulation time 119402974 ps
CPU time 0.93 seconds
Started Apr 23 02:26:01 PM PDT 24
Finished Apr 23 02:26:03 PM PDT 24
Peak memory 201008 kb
Host smart-6865e11e-71b2-4f9d-817d-d12b81184be8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008360686 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1008360686
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1268352458
Short name T594
Test name
Test status
Simulation time 92497195 ps
CPU time 0.89 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:25:55 PM PDT 24
Peak memory 200892 kb
Host smart-f8c378f1-40fc-4e0b-9841-8b0478b2eacf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268352458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1268352458
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1909861319
Short name T589
Test name
Test status
Simulation time 223415037 ps
CPU time 1.62 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:54 PM PDT 24
Peak memory 201132 kb
Host smart-63fbb763-4bba-4a51-9796-46873a4d3ab2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909861319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1909861319
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3524882573
Short name T564
Test name
Test status
Simulation time 253237599 ps
CPU time 1.99 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:55 PM PDT 24
Peak memory 209264 kb
Host smart-ca78d286-a4bb-4430-8ffe-7b2dcd281684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524882573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3524882573
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2042026591
Short name T116
Test name
Test status
Simulation time 818501315 ps
CPU time 2.74 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:56 PM PDT 24
Peak memory 201008 kb
Host smart-d8e65341-e8d0-4066-878e-7e88a75816fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042026591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2042026591
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3831970438
Short name T592
Test name
Test status
Simulation time 176952898 ps
CPU time 1.84 seconds
Started Apr 23 02:25:54 PM PDT 24
Finished Apr 23 02:25:56 PM PDT 24
Peak memory 209440 kb
Host smart-0dfbfca4-95b0-4e00-aca2-f0a7e861cc5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831970438 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3831970438
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4100348003
Short name T567
Test name
Test status
Simulation time 71485853 ps
CPU time 0.8 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:54 PM PDT 24
Peak memory 200812 kb
Host smart-8dab3a1c-3227-42c7-9748-8b17a9420770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100348003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.4100348003
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.95693401
Short name T108
Test name
Test status
Simulation time 104986622 ps
CPU time 1.22 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:26:02 PM PDT 24
Peak memory 201128 kb
Host smart-c8e6ba8d-2aa1-4464-b906-18527b38a013
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95693401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sam
e_csr_outstanding.95693401
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.170898717
Short name T566
Test name
Test status
Simulation time 167826727 ps
CPU time 2.43 seconds
Started Apr 23 02:25:55 PM PDT 24
Finished Apr 23 02:25:58 PM PDT 24
Peak memory 217316 kb
Host smart-696c5be2-90ca-445c-ad75-7750afe69ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170898717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.170898717
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1961229002
Short name T553
Test name
Test status
Simulation time 465702205 ps
CPU time 1.72 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:55 PM PDT 24
Peak memory 201124 kb
Host smart-85ac7ffe-aec8-44e5-93f0-df8b87a8757a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961229002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1961229002
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2614478437
Short name T76
Test name
Test status
Simulation time 152070914 ps
CPU time 1.94 seconds
Started Apr 23 02:25:39 PM PDT 24
Finished Apr 23 02:25:41 PM PDT 24
Peak memory 201088 kb
Host smart-b8756d7c-02b9-49bb-9643-c00f0cb36237
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614478437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
614478437
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.993439988
Short name T579
Test name
Test status
Simulation time 490709764 ps
CPU time 5.58 seconds
Started Apr 23 02:25:37 PM PDT 24
Finished Apr 23 02:25:43 PM PDT 24
Peak memory 201108 kb
Host smart-01f7a9d7-b1cf-4da3-b965-bca122472057
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993439988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.993439988
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2848355796
Short name T581
Test name
Test status
Simulation time 98745996 ps
CPU time 0.81 seconds
Started Apr 23 02:25:40 PM PDT 24
Finished Apr 23 02:25:41 PM PDT 24
Peak memory 200808 kb
Host smart-2680b34f-f991-4c2b-91b5-8b66e6081098
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848355796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
848355796
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1695685738
Short name T569
Test name
Test status
Simulation time 197733525 ps
CPU time 1.29 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 209532 kb
Host smart-8744072a-3b5b-4954-b62d-d551d1ceec7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695685738 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1695685738
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1214758919
Short name T606
Test name
Test status
Simulation time 82740837 ps
CPU time 0.87 seconds
Started Apr 23 02:25:43 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 200788 kb
Host smart-03a00704-c2a0-4d42-9780-334d1ca3c8c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214758919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1214758919
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3468216824
Short name T561
Test name
Test status
Simulation time 119031602 ps
CPU time 1.24 seconds
Started Apr 23 02:25:40 PM PDT 24
Finished Apr 23 02:25:42 PM PDT 24
Peak memory 201068 kb
Host smart-9967b8bc-0fad-4cba-a946-0f0287ee677c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468216824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3468216824
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.33809909
Short name T570
Test name
Test status
Simulation time 227082391 ps
CPU time 1.88 seconds
Started Apr 23 02:25:41 PM PDT 24
Finished Apr 23 02:25:43 PM PDT 24
Peak memory 209256 kb
Host smart-1a1ebc10-2303-4d85-ba75-3f5f834ce18e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33809909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.33809909
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3932075433
Short name T121
Test name
Test status
Simulation time 428532179 ps
CPU time 1.82 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:45 PM PDT 24
Peak memory 201092 kb
Host smart-2f708f45-62b1-47cd-bfc2-35938dacb27c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932075433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3932075433
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.788142804
Short name T593
Test name
Test status
Simulation time 216408382 ps
CPU time 1.55 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 209168 kb
Host smart-4359f543-a1ef-41c6-8158-65691048493e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788142804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.788142804
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1137059045
Short name T602
Test name
Test status
Simulation time 2285043063 ps
CPU time 9.28 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:52 PM PDT 24
Peak memory 201144 kb
Host smart-c08020ff-932b-4679-b333-933d35453a9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137059045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
137059045
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.856597588
Short name T577
Test name
Test status
Simulation time 91398558 ps
CPU time 0.82 seconds
Started Apr 23 02:25:39 PM PDT 24
Finished Apr 23 02:25:40 PM PDT 24
Peak memory 200824 kb
Host smart-d595ac68-5df7-416e-bdd9-237074038cd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856597588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.856597588
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.234344635
Short name T597
Test name
Test status
Simulation time 120030081 ps
CPU time 1.03 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 201004 kb
Host smart-ae9dbf2a-c94d-4bcf-9838-3dcd54ec85a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234344635 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.234344635
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3054893130
Short name T572
Test name
Test status
Simulation time 90488394 ps
CPU time 0.87 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 200776 kb
Host smart-eb3f8658-7566-4ebb-8061-90c3efc1b965
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054893130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3054893130
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4096543354
Short name T619
Test name
Test status
Simulation time 112398950 ps
CPU time 1.24 seconds
Started Apr 23 02:25:38 PM PDT 24
Finished Apr 23 02:25:40 PM PDT 24
Peak memory 201076 kb
Host smart-e9b789e3-5edc-4b1a-9519-de20793fb52c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096543354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4096543354
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2669982877
Short name T115
Test name
Test status
Simulation time 786195465 ps
CPU time 3.09 seconds
Started Apr 23 02:25:39 PM PDT 24
Finished Apr 23 02:25:42 PM PDT 24
Peak memory 201188 kb
Host smart-f9fe8344-f4d0-4fba-8cce-d4966c907d76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669982877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2669982877
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3555892807
Short name T543
Test name
Test status
Simulation time 474901021 ps
CPU time 2.61 seconds
Started Apr 23 02:25:39 PM PDT 24
Finished Apr 23 02:25:43 PM PDT 24
Peak memory 201076 kb
Host smart-29e6628f-72cc-4746-9eb4-0ff010f7293a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555892807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
555892807
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.988527764
Short name T576
Test name
Test status
Simulation time 812167759 ps
CPU time 4.53 seconds
Started Apr 23 02:25:41 PM PDT 24
Finished Apr 23 02:25:46 PM PDT 24
Peak memory 201060 kb
Host smart-3829ade9-4811-491e-98dd-a7ac7f7b6940
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988527764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.988527764
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1271411351
Short name T608
Test name
Test status
Simulation time 102410357 ps
CPU time 0.88 seconds
Started Apr 23 02:25:40 PM PDT 24
Finished Apr 23 02:25:41 PM PDT 24
Peak memory 200764 kb
Host smart-1460c897-3449-49a1-9f96-b69b00b8d7ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271411351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
271411351
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2433756509
Short name T607
Test name
Test status
Simulation time 126204613 ps
CPU time 1.04 seconds
Started Apr 23 02:25:41 PM PDT 24
Finished Apr 23 02:25:42 PM PDT 24
Peak memory 209132 kb
Host smart-9f81bdd1-6c72-4a7c-8f9f-193f82715e70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433756509 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2433756509
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3183343567
Short name T77
Test name
Test status
Simulation time 68245468 ps
CPU time 0.85 seconds
Started Apr 23 02:25:41 PM PDT 24
Finished Apr 23 02:25:42 PM PDT 24
Peak memory 200856 kb
Host smart-27ef2b70-e0c8-4d55-bcfb-fcefebd9836c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183343567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3183343567
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.809728820
Short name T613
Test name
Test status
Simulation time 284195681 ps
CPU time 1.61 seconds
Started Apr 23 02:25:41 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 201020 kb
Host smart-a192b37e-d88b-4476-ada7-24a6de7c1b18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809728820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.809728820
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.918240316
Short name T568
Test name
Test status
Simulation time 542158160 ps
CPU time 3.38 seconds
Started Apr 23 02:25:43 PM PDT 24
Finished Apr 23 02:25:47 PM PDT 24
Peak memory 217288 kb
Host smart-7c65982f-dd41-4e8f-872b-ad43f696be46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918240316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.918240316
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3678867322
Short name T563
Test name
Test status
Simulation time 121748668 ps
CPU time 0.96 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 200936 kb
Host smart-8a932c7f-60b0-4579-aa81-521ad4b45560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678867322 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3678867322
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.223459236
Short name T550
Test name
Test status
Simulation time 68615321 ps
CPU time 0.84 seconds
Started Apr 23 02:25:44 PM PDT 24
Finished Apr 23 02:25:45 PM PDT 24
Peak memory 200804 kb
Host smart-e1503876-a9bc-491a-9bed-b5eb13d221b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223459236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.223459236
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.44022163
Short name T612
Test name
Test status
Simulation time 205331306 ps
CPU time 1.52 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:45 PM PDT 24
Peak memory 201116 kb
Host smart-8ef9b66c-a1e1-463e-a20e-184541617554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44022163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same
_csr_outstanding.44022163
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1019908199
Short name T91
Test name
Test status
Simulation time 186567961 ps
CPU time 2.62 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:45 PM PDT 24
Peak memory 212884 kb
Host smart-cc6da269-3a8e-4553-85f7-e5bc6ae4c97f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019908199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1019908199
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2722977523
Short name T80
Test name
Test status
Simulation time 465907376 ps
CPU time 2.04 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 201164 kb
Host smart-5f796c5b-faee-48af-809d-b6ee1dda83c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722977523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2722977523
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1799094418
Short name T618
Test name
Test status
Simulation time 99321676 ps
CPU time 0.86 seconds
Started Apr 23 02:25:43 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 200988 kb
Host smart-0358c4f0-c84d-4bd1-9b74-e064d38529e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799094418 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1799094418
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3098486133
Short name T598
Test name
Test status
Simulation time 78612587 ps
CPU time 0.81 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 200888 kb
Host smart-cb64a4aa-1160-4a03-88bc-8ea1d9c82512
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098486133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3098486133
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1498257105
Short name T544
Test name
Test status
Simulation time 130859312 ps
CPU time 1.33 seconds
Started Apr 23 02:25:42 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 217608 kb
Host smart-bb6db328-e36b-4494-bad7-aa8a52be2a4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498257105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1498257105
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3556942039
Short name T74
Test name
Test status
Simulation time 148566590 ps
CPU time 1.07 seconds
Started Apr 23 02:25:43 PM PDT 24
Finished Apr 23 02:25:45 PM PDT 24
Peak memory 211004 kb
Host smart-7cd910b5-249e-48a7-a886-3dd430633aea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556942039 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3556942039
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.710466329
Short name T587
Test name
Test status
Simulation time 93317660 ps
CPU time 0.9 seconds
Started Apr 23 02:25:43 PM PDT 24
Finished Apr 23 02:25:45 PM PDT 24
Peak memory 200884 kb
Host smart-ef3fd3d5-3958-4395-93fd-373faaaa9c44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710466329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.710466329
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3972647237
Short name T552
Test name
Test status
Simulation time 196324380 ps
CPU time 1.48 seconds
Started Apr 23 02:25:44 PM PDT 24
Finished Apr 23 02:25:46 PM PDT 24
Peak memory 201116 kb
Host smart-d872785f-9258-403e-adbb-41d3c8b6281b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972647237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3972647237
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1070558154
Short name T595
Test name
Test status
Simulation time 176025020 ps
CPU time 2.37 seconds
Started Apr 23 02:25:44 PM PDT 24
Finished Apr 23 02:25:47 PM PDT 24
Peak memory 209284 kb
Host smart-7b4d8a48-99fc-416a-b775-8a1d90edcfab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070558154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1070558154
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.294414659
Short name T89
Test name
Test status
Simulation time 139204989 ps
CPU time 1.06 seconds
Started Apr 23 02:25:46 PM PDT 24
Finished Apr 23 02:25:47 PM PDT 24
Peak memory 201404 kb
Host smart-77c159a0-76c4-4bd7-951e-88c78cf5c218
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294414659 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.294414659
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1711825860
Short name T565
Test name
Test status
Simulation time 65022272 ps
CPU time 0.81 seconds
Started Apr 23 02:25:46 PM PDT 24
Finished Apr 23 02:25:47 PM PDT 24
Peak memory 200832 kb
Host smart-b64283b1-f88f-460c-9af2-0b168a409a15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711825860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1711825860
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3798909161
Short name T110
Test name
Test status
Simulation time 86742227 ps
CPU time 0.96 seconds
Started Apr 23 02:25:44 PM PDT 24
Finished Apr 23 02:25:46 PM PDT 24
Peak memory 200960 kb
Host smart-0476f1c7-121e-4751-b0ad-a36918b90171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798909161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3798909161
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.815324136
Short name T591
Test name
Test status
Simulation time 210576986 ps
CPU time 2.81 seconds
Started Apr 23 02:25:44 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 209260 kb
Host smart-52a580bd-8996-4c7a-b20f-22ba85fec7e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815324136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.815324136
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1498113214
Short name T123
Test name
Test status
Simulation time 924005419 ps
CPU time 2.97 seconds
Started Apr 23 02:25:44 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 201124 kb
Host smart-59627a52-f79b-4961-9c6a-33ab6bd4315c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498113214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1498113214
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1256259989
Short name T562
Test name
Test status
Simulation time 174451505 ps
CPU time 1.69 seconds
Started Apr 23 02:25:46 PM PDT 24
Finished Apr 23 02:25:49 PM PDT 24
Peak memory 209328 kb
Host smart-e90179a0-7c82-4b9a-b003-6c6b987512dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256259989 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1256259989
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.930053867
Short name T573
Test name
Test status
Simulation time 65786194 ps
CPU time 0.78 seconds
Started Apr 23 02:25:44 PM PDT 24
Finished Apr 23 02:25:46 PM PDT 24
Peak memory 200852 kb
Host smart-d350d105-c7a4-4001-b757-a90f4da23e7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930053867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.930053867
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1833268739
Short name T545
Test name
Test status
Simulation time 190023229 ps
CPU time 1.36 seconds
Started Apr 23 02:25:43 PM PDT 24
Finished Apr 23 02:25:46 PM PDT 24
Peak memory 201188 kb
Host smart-45e0af4d-6ce0-4b07-9567-64c084cc8e7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833268739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1833268739
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3043177065
Short name T90
Test name
Test status
Simulation time 454080728 ps
CPU time 3.32 seconds
Started Apr 23 02:25:46 PM PDT 24
Finished Apr 23 02:25:50 PM PDT 24
Peak memory 209244 kb
Host smart-dd04c3b3-e3b2-4914-ab26-ced626793964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043177065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3043177065
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1671326529
Short name T117
Test name
Test status
Simulation time 781624079 ps
CPU time 2.86 seconds
Started Apr 23 02:25:47 PM PDT 24
Finished Apr 23 02:25:50 PM PDT 24
Peak memory 201056 kb
Host smart-28927b6c-237c-43dd-bcca-1b03f38ab604
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671326529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1671326529
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2062156065
Short name T274
Test name
Test status
Simulation time 79076784 ps
CPU time 0.75 seconds
Started Apr 23 02:31:53 PM PDT 24
Finished Apr 23 02:31:54 PM PDT 24
Peak memory 200612 kb
Host smart-cc78667d-2ff9-421e-8685-44254261623d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062156065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2062156065
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3417904814
Short name T232
Test name
Test status
Simulation time 244620892 ps
CPU time 1.08 seconds
Started Apr 23 02:31:54 PM PDT 24
Finished Apr 23 02:31:55 PM PDT 24
Peak memory 218196 kb
Host smart-0d05d361-f7a3-4902-a089-9f2fae9fc482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417904814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3417904814
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.978954658
Short name T518
Test name
Test status
Simulation time 96614846 ps
CPU time 0.76 seconds
Started Apr 23 02:31:47 PM PDT 24
Finished Apr 23 02:31:48 PM PDT 24
Peak memory 200604 kb
Host smart-f5907994-bfa2-4566-9449-ba01f944fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978954658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.978954658
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1527797091
Short name T169
Test name
Test status
Simulation time 766250787 ps
CPU time 3.81 seconds
Started Apr 23 02:31:49 PM PDT 24
Finished Apr 23 02:31:53 PM PDT 24
Peak memory 200984 kb
Host smart-3777a398-b164-4523-a8cd-11941a436b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527797091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1527797091
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3177331142
Short name T86
Test name
Test status
Simulation time 17463413454 ps
CPU time 24.02 seconds
Started Apr 23 02:31:52 PM PDT 24
Finished Apr 23 02:32:17 PM PDT 24
Peak memory 217812 kb
Host smart-9b1b7c70-e8f4-4c4b-b75a-bd00b49b73f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177331142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3177331142
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3115038773
Short name T388
Test name
Test status
Simulation time 161191589 ps
CPU time 1.06 seconds
Started Apr 23 02:31:48 PM PDT 24
Finished Apr 23 02:31:50 PM PDT 24
Peak memory 200816 kb
Host smart-dec9a5d0-ddbf-476e-a13a-e075d2220489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115038773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3115038773
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2198966107
Short name T284
Test name
Test status
Simulation time 118624473 ps
CPU time 1.17 seconds
Started Apr 23 02:31:46 PM PDT 24
Finished Apr 23 02:31:48 PM PDT 24
Peak memory 200996 kb
Host smart-c4a25198-a9a9-450d-8724-a0549668786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198966107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2198966107
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.65933150
Short name T326
Test name
Test status
Simulation time 1137369579 ps
CPU time 5.4 seconds
Started Apr 23 02:31:52 PM PDT 24
Finished Apr 23 02:31:58 PM PDT 24
Peak memory 209412 kb
Host smart-c6273a09-0e03-45cd-8595-65f58cf93303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65933150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.65933150
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2768572350
Short name T322
Test name
Test status
Simulation time 387782212 ps
CPU time 2.17 seconds
Started Apr 23 02:31:48 PM PDT 24
Finished Apr 23 02:31:51 PM PDT 24
Peak memory 200768 kb
Host smart-aeba8727-8038-471e-9c6c-cfc9060ea7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768572350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2768572350
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.580839580
Short name T191
Test name
Test status
Simulation time 94499500 ps
CPU time 0.85 seconds
Started Apr 23 02:31:50 PM PDT 24
Finished Apr 23 02:31:51 PM PDT 24
Peak memory 200828 kb
Host smart-8d8078c5-e6aa-4c9e-abe8-ba2def827a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580839580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.580839580
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3974670561
Short name T155
Test name
Test status
Simulation time 64122159 ps
CPU time 0.77 seconds
Started Apr 23 02:32:06 PM PDT 24
Finished Apr 23 02:32:07 PM PDT 24
Peak memory 200600 kb
Host smart-6058041e-b5fb-45d5-9551-5925f60a102b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974670561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3974670561
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3465100610
Short name T383
Test name
Test status
Simulation time 244450379 ps
CPU time 1.12 seconds
Started Apr 23 02:32:05 PM PDT 24
Finished Apr 23 02:32:06 PM PDT 24
Peak memory 218072 kb
Host smart-16509d49-992d-4cd8-b601-4aa0ce41c3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465100610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3465100610
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3581810267
Short name T283
Test name
Test status
Simulation time 236024468 ps
CPU time 0.93 seconds
Started Apr 23 02:31:56 PM PDT 24
Finished Apr 23 02:31:57 PM PDT 24
Peak memory 200644 kb
Host smart-90e457b8-263d-431e-b1a0-908f7553571c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581810267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3581810267
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1995548409
Short name T102
Test name
Test status
Simulation time 1530909702 ps
CPU time 5.28 seconds
Started Apr 23 02:31:59 PM PDT 24
Finished Apr 23 02:32:04 PM PDT 24
Peak memory 200940 kb
Host smart-b822444f-4b11-4ca1-a07a-4485ed28eb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995548409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1995548409
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1453300036
Short name T160
Test name
Test status
Simulation time 103916450 ps
CPU time 1.02 seconds
Started Apr 23 02:32:02 PM PDT 24
Finished Apr 23 02:32:03 PM PDT 24
Peak memory 200836 kb
Host smart-2589fab6-525f-453b-90d7-2df26fbc9e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453300036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1453300036
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1864661489
Short name T8
Test name
Test status
Simulation time 115357659 ps
CPU time 1.17 seconds
Started Apr 23 02:31:57 PM PDT 24
Finished Apr 23 02:31:58 PM PDT 24
Peak memory 201004 kb
Host smart-c43c3ab8-1bfd-49db-8964-6575bf37db60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864661489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1864661489
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1751990380
Short name T405
Test name
Test status
Simulation time 12213664959 ps
CPU time 44.72 seconds
Started Apr 23 02:32:06 PM PDT 24
Finished Apr 23 02:32:51 PM PDT 24
Peak memory 209228 kb
Host smart-6227cd2a-d51e-45c5-b3d2-55b1c3bc43fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751990380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1751990380
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1567207272
Short name T290
Test name
Test status
Simulation time 298207259 ps
CPU time 1.81 seconds
Started Apr 23 02:32:03 PM PDT 24
Finished Apr 23 02:32:05 PM PDT 24
Peak memory 200812 kb
Host smart-ea72a021-c5b5-4e4b-add7-a97360b952fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567207272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1567207272
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.793549658
Short name T242
Test name
Test status
Simulation time 157373572 ps
CPU time 1.04 seconds
Started Apr 23 02:32:02 PM PDT 24
Finished Apr 23 02:32:03 PM PDT 24
Peak memory 200840 kb
Host smart-5c11919f-03e7-4faa-88f8-f9349b53b748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793549658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.793549658
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1317852024
Short name T140
Test name
Test status
Simulation time 95032993 ps
CPU time 0.77 seconds
Started Apr 23 02:32:50 PM PDT 24
Finished Apr 23 02:32:51 PM PDT 24
Peak memory 200636 kb
Host smart-8e3d1a95-8dd5-4fb7-bd8a-6d7f929efe31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317852024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1317852024
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3918061589
Short name T471
Test name
Test status
Simulation time 1224876437 ps
CPU time 5.7 seconds
Started Apr 23 02:32:51 PM PDT 24
Finished Apr 23 02:32:57 PM PDT 24
Peak memory 218020 kb
Host smart-c7597c7e-c0e7-4f6d-8819-05583e55b9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918061589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3918061589
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.584856535
Short name T184
Test name
Test status
Simulation time 151999650 ps
CPU time 0.81 seconds
Started Apr 23 02:32:52 PM PDT 24
Finished Apr 23 02:32:53 PM PDT 24
Peak memory 200644 kb
Host smart-c16daee3-73a9-41f7-9dea-071b051dba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584856535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.584856535
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1233880819
Short name T106
Test name
Test status
Simulation time 1445494679 ps
CPU time 5.78 seconds
Started Apr 23 02:32:51 PM PDT 24
Finished Apr 23 02:32:57 PM PDT 24
Peak memory 200968 kb
Host smart-da16deef-c929-4efb-9091-c218d6d2cb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233880819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1233880819
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2492168403
Short name T483
Test name
Test status
Simulation time 109321003 ps
CPU time 0.99 seconds
Started Apr 23 02:32:49 PM PDT 24
Finished Apr 23 02:32:51 PM PDT 24
Peak memory 200784 kb
Host smart-270b1351-7169-443b-8d75-c6c834769b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492168403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2492168403
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.150325039
Short name T134
Test name
Test status
Simulation time 258329601 ps
CPU time 1.4 seconds
Started Apr 23 02:32:47 PM PDT 24
Finished Apr 23 02:32:49 PM PDT 24
Peak memory 201056 kb
Host smart-07ef1ab4-f4d6-4de1-950d-9291353f44e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150325039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.150325039
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3356437943
Short name T480
Test name
Test status
Simulation time 11443826355 ps
CPU time 35.21 seconds
Started Apr 23 02:32:50 PM PDT 24
Finished Apr 23 02:33:25 PM PDT 24
Peak memory 209292 kb
Host smart-588a3b5e-047c-4db5-ad0d-27b90469b395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356437943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3356437943
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.408572084
Short name T329
Test name
Test status
Simulation time 269191966 ps
CPU time 1.74 seconds
Started Apr 23 02:32:52 PM PDT 24
Finished Apr 23 02:32:54 PM PDT 24
Peak memory 200784 kb
Host smart-a1cd8c3c-725f-4b83-a616-6f62f86eab05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408572084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.408572084
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4104944085
Short name T266
Test name
Test status
Simulation time 162452362 ps
CPU time 1.05 seconds
Started Apr 23 02:32:52 PM PDT 24
Finished Apr 23 02:32:53 PM PDT 24
Peak memory 200800 kb
Host smart-54e337d3-b456-410e-bac4-09d02e6ffa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104944085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4104944085
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1524108478
Short name T440
Test name
Test status
Simulation time 76317734 ps
CPU time 0.76 seconds
Started Apr 23 02:32:54 PM PDT 24
Finished Apr 23 02:32:55 PM PDT 24
Peak memory 200588 kb
Host smart-9b021f8a-5295-4cfe-a625-1d3f2b34195b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524108478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1524108478
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1393330098
Short name T482
Test name
Test status
Simulation time 1232412814 ps
CPU time 5.35 seconds
Started Apr 23 02:32:51 PM PDT 24
Finished Apr 23 02:32:56 PM PDT 24
Peak memory 222684 kb
Host smart-ac172ae8-fb3b-410f-8c02-50c797090f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393330098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1393330098
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1243675544
Short name T154
Test name
Test status
Simulation time 243608097 ps
CPU time 1.03 seconds
Started Apr 23 02:32:58 PM PDT 24
Finished Apr 23 02:33:00 PM PDT 24
Peak memory 218140 kb
Host smart-3aed8873-2fbc-4216-9c71-1793e723d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243675544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1243675544
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1536272727
Short name T188
Test name
Test status
Simulation time 85205663 ps
CPU time 0.72 seconds
Started Apr 23 02:32:50 PM PDT 24
Finished Apr 23 02:32:51 PM PDT 24
Peak memory 200572 kb
Host smart-903df9b2-dea5-4936-bb0b-fd8945d30908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536272727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1536272727
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1945182112
Short name T421
Test name
Test status
Simulation time 1405501426 ps
CPU time 5.48 seconds
Started Apr 23 02:32:48 PM PDT 24
Finished Apr 23 02:32:54 PM PDT 24
Peak memory 200988 kb
Host smart-e84d5d9f-01e4-430d-a148-5d5f0bf0ef17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945182112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1945182112
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3544443189
Short name T339
Test name
Test status
Simulation time 116245620 ps
CPU time 1.18 seconds
Started Apr 23 02:32:52 PM PDT 24
Finished Apr 23 02:32:54 PM PDT 24
Peak memory 200976 kb
Host smart-47d411b0-af5f-4b33-9634-1c85a2c0df57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544443189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3544443189
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3934895159
Short name T453
Test name
Test status
Simulation time 5101984294 ps
CPU time 20.87 seconds
Started Apr 23 02:32:52 PM PDT 24
Finished Apr 23 02:33:14 PM PDT 24
Peak memory 210084 kb
Host smart-2b58b2fc-00d6-4883-a311-2226435a08dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934895159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3934895159
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.966555954
Short name T194
Test name
Test status
Simulation time 347125217 ps
CPU time 2.31 seconds
Started Apr 23 02:32:56 PM PDT 24
Finished Apr 23 02:33:00 PM PDT 24
Peak memory 200824 kb
Host smart-9bca418e-7884-459a-b3f8-6cde052ef129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966555954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.966555954
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2036652916
Short name T488
Test name
Test status
Simulation time 151414017 ps
CPU time 1.11 seconds
Started Apr 23 02:32:51 PM PDT 24
Finished Apr 23 02:32:53 PM PDT 24
Peak memory 200780 kb
Host smart-f3c577f5-063f-4233-a75a-ff7297c76bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036652916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2036652916
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3710585351
Short name T162
Test name
Test status
Simulation time 78163578 ps
CPU time 0.78 seconds
Started Apr 23 02:32:56 PM PDT 24
Finished Apr 23 02:32:57 PM PDT 24
Peak memory 200672 kb
Host smart-09005dd7-6e28-4741-9342-5098c477f573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710585351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3710585351
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.587644480
Short name T32
Test name
Test status
Simulation time 1223048242 ps
CPU time 5.24 seconds
Started Apr 23 02:32:53 PM PDT 24
Finished Apr 23 02:32:59 PM PDT 24
Peak memory 222688 kb
Host smart-e354412b-29a3-49e0-99a4-65c522d858b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587644480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.587644480
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1986355140
Short name T418
Test name
Test status
Simulation time 243584369 ps
CPU time 1.06 seconds
Started Apr 23 02:32:58 PM PDT 24
Finished Apr 23 02:33:00 PM PDT 24
Peak memory 218056 kb
Host smart-4f4f945a-dd01-4f54-b470-bd2518c7c1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986355140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1986355140
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2109200839
Short name T311
Test name
Test status
Simulation time 141106538 ps
CPU time 0.78 seconds
Started Apr 23 02:32:52 PM PDT 24
Finished Apr 23 02:32:53 PM PDT 24
Peak memory 200616 kb
Host smart-2841614a-650e-4282-99c4-1527b55c2880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109200839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2109200839
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.76126636
Short name T356
Test name
Test status
Simulation time 1599123163 ps
CPU time 5.8 seconds
Started Apr 23 02:32:52 PM PDT 24
Finished Apr 23 02:32:58 PM PDT 24
Peak memory 201008 kb
Host smart-2c4dd5eb-8f7e-4926-87b0-fb27d9603e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76126636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.76126636
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.212676835
Short name T509
Test name
Test status
Simulation time 141581673 ps
CPU time 1.11 seconds
Started Apr 23 02:32:53 PM PDT 24
Finished Apr 23 02:32:55 PM PDT 24
Peak memory 200836 kb
Host smart-92b9cfdc-c7cb-4764-9fab-7809b2f44368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212676835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.212676835
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2613660785
Short name T141
Test name
Test status
Simulation time 203485985 ps
CPU time 1.48 seconds
Started Apr 23 02:32:58 PM PDT 24
Finished Apr 23 02:33:00 PM PDT 24
Peak memory 201044 kb
Host smart-cca1f478-3a70-4a8a-8a89-5757727d3634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613660785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2613660785
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3015150488
Short name T362
Test name
Test status
Simulation time 12131422846 ps
CPU time 40 seconds
Started Apr 23 02:32:58 PM PDT 24
Finished Apr 23 02:33:38 PM PDT 24
Peak memory 201144 kb
Host smart-64db64b6-e3d4-4974-a2f6-b014013bb6a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015150488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3015150488
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3739478571
Short name T445
Test name
Test status
Simulation time 134196959 ps
CPU time 1.51 seconds
Started Apr 23 02:32:53 PM PDT 24
Finished Apr 23 02:32:55 PM PDT 24
Peak memory 209016 kb
Host smart-5795e88a-a607-4fb2-a2cf-ec5e8163a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739478571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3739478571
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.305191676
Short name T214
Test name
Test status
Simulation time 184372050 ps
CPU time 1.17 seconds
Started Apr 23 02:32:57 PM PDT 24
Finished Apr 23 02:32:59 PM PDT 24
Peak memory 200828 kb
Host smart-9c28ad6f-9b93-4888-9330-edcc16ccab17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305191676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.305191676
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1556700463
Short name T538
Test name
Test status
Simulation time 67529828 ps
CPU time 0.77 seconds
Started Apr 23 02:33:00 PM PDT 24
Finished Apr 23 02:33:01 PM PDT 24
Peak memory 200604 kb
Host smart-45eb13ee-7985-4246-897f-6f6c2e6c319f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556700463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1556700463
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2501285669
Short name T47
Test name
Test status
Simulation time 2360502861 ps
CPU time 7.83 seconds
Started Apr 23 02:33:00 PM PDT 24
Finished Apr 23 02:33:09 PM PDT 24
Peak memory 222804 kb
Host smart-26368433-29d0-445d-8e39-76d213fcf963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501285669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2501285669
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.870335434
Short name T58
Test name
Test status
Simulation time 244156283 ps
CPU time 0.99 seconds
Started Apr 23 02:32:57 PM PDT 24
Finished Apr 23 02:32:59 PM PDT 24
Peak memory 218112 kb
Host smart-c5bdf1ee-f150-44ab-9e25-b65dff3a8487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870335434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.870335434
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1248374447
Short name T181
Test name
Test status
Simulation time 1768375148 ps
CPU time 6.44 seconds
Started Apr 23 02:32:56 PM PDT 24
Finished Apr 23 02:33:03 PM PDT 24
Peak memory 201028 kb
Host smart-5a3a4d07-98d2-4843-b241-aac3b242585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248374447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1248374447
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.349405374
Short name T230
Test name
Test status
Simulation time 102953964 ps
CPU time 0.94 seconds
Started Apr 23 02:32:58 PM PDT 24
Finished Apr 23 02:32:59 PM PDT 24
Peak memory 200808 kb
Host smart-2edd0996-9139-4fe5-acef-bfb6aec8e906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349405374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.349405374
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2595031688
Short name T225
Test name
Test status
Simulation time 186119302 ps
CPU time 1.32 seconds
Started Apr 23 02:32:55 PM PDT 24
Finished Apr 23 02:32:57 PM PDT 24
Peak memory 200976 kb
Host smart-d26130dd-1b40-4beb-b309-48e277d684fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595031688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2595031688
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1540443384
Short name T213
Test name
Test status
Simulation time 3230718009 ps
CPU time 11.8 seconds
Started Apr 23 02:32:59 PM PDT 24
Finished Apr 23 02:33:11 PM PDT 24
Peak memory 201008 kb
Host smart-98abe777-27b8-406c-a46b-c9c9a62da344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540443384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1540443384
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2332469349
Short name T54
Test name
Test status
Simulation time 142944481 ps
CPU time 1.64 seconds
Started Apr 23 02:32:56 PM PDT 24
Finished Apr 23 02:32:59 PM PDT 24
Peak memory 200832 kb
Host smart-c966f110-cf2a-4b42-90e2-5754d029ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332469349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2332469349
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1404264525
Short name T131
Test name
Test status
Simulation time 212163329 ps
CPU time 1.33 seconds
Started Apr 23 02:32:55 PM PDT 24
Finished Apr 23 02:32:57 PM PDT 24
Peak memory 200800 kb
Host smart-c994c879-9945-4cdc-aadb-b7b022b4b1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404264525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1404264525
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3145872421
Short name T415
Test name
Test status
Simulation time 60492394 ps
CPU time 0.74 seconds
Started Apr 23 02:33:02 PM PDT 24
Finished Apr 23 02:33:03 PM PDT 24
Peak memory 200656 kb
Host smart-26aa3898-e0b7-4b2e-bab1-bed690e76d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145872421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3145872421
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1779072868
Short name T529
Test name
Test status
Simulation time 2365461541 ps
CPU time 8.52 seconds
Started Apr 23 02:32:59 PM PDT 24
Finished Apr 23 02:33:08 PM PDT 24
Peak memory 218776 kb
Host smart-1e31b626-584c-4a8b-a71c-9f8aff2c00df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779072868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1779072868
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.184909583
Short name T419
Test name
Test status
Simulation time 243817446 ps
CPU time 1.03 seconds
Started Apr 23 02:33:08 PM PDT 24
Finished Apr 23 02:33:11 PM PDT 24
Peak memory 218236 kb
Host smart-abb64863-f379-4db3-a99b-fb6ccccd7a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184909583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.184909583
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.964282586
Short name T13
Test name
Test status
Simulation time 107272589 ps
CPU time 0.81 seconds
Started Apr 23 02:33:00 PM PDT 24
Finished Apr 23 02:33:01 PM PDT 24
Peak memory 200644 kb
Host smart-fd0319d4-19a6-4495-9367-bfd06e329b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964282586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.964282586
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2046043151
Short name T226
Test name
Test status
Simulation time 159945614 ps
CPU time 1.18 seconds
Started Apr 23 02:32:59 PM PDT 24
Finished Apr 23 02:33:01 PM PDT 24
Peak memory 200844 kb
Host smart-d83947ba-0908-45b8-ace7-986770eec6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046043151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2046043151
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3818419490
Short name T366
Test name
Test status
Simulation time 249122114 ps
CPU time 1.5 seconds
Started Apr 23 02:33:00 PM PDT 24
Finished Apr 23 02:33:02 PM PDT 24
Peak memory 200964 kb
Host smart-eb6c4926-16f2-4060-b27f-c744d33d1717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818419490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3818419490
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.851258488
Short name T103
Test name
Test status
Simulation time 11618322314 ps
CPU time 37.83 seconds
Started Apr 23 02:33:01 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 201068 kb
Host smart-8b52b293-05c9-4f0f-a735-af63b2718596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851258488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.851258488
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1161462920
Short name T297
Test name
Test status
Simulation time 135072172 ps
CPU time 1.82 seconds
Started Apr 23 02:33:00 PM PDT 24
Finished Apr 23 02:33:03 PM PDT 24
Peak memory 200792 kb
Host smart-87f9563d-9172-4468-9c96-313602213edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161462920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1161462920
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2105440484
Short name T310
Test name
Test status
Simulation time 205414157 ps
CPU time 1.19 seconds
Started Apr 23 02:32:59 PM PDT 24
Finished Apr 23 02:33:01 PM PDT 24
Peak memory 200844 kb
Host smart-1cb5de60-1770-4148-b080-b5b38a755c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105440484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2105440484
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3572524067
Short name T349
Test name
Test status
Simulation time 84068840 ps
CPU time 0.8 seconds
Started Apr 23 02:33:04 PM PDT 24
Finished Apr 23 02:33:05 PM PDT 24
Peak memory 200632 kb
Host smart-c35cc4e4-5b4a-4d3c-82ac-c4bf22050e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572524067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3572524067
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1308990854
Short name T70
Test name
Test status
Simulation time 1884751086 ps
CPU time 6.96 seconds
Started Apr 23 02:33:02 PM PDT 24
Finished Apr 23 02:33:09 PM PDT 24
Peak memory 218052 kb
Host smart-2aa57802-690c-4a45-acd5-1b165c18a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308990854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1308990854
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3644665571
Short name T157
Test name
Test status
Simulation time 244358318 ps
CPU time 1.03 seconds
Started Apr 23 02:33:03 PM PDT 24
Finished Apr 23 02:33:05 PM PDT 24
Peak memory 218040 kb
Host smart-ae672efd-beb5-477d-bc47-f95927fc36f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644665571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3644665571
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3469290247
Short name T16
Test name
Test status
Simulation time 253864395 ps
CPU time 0.94 seconds
Started Apr 23 02:33:07 PM PDT 24
Finished Apr 23 02:33:08 PM PDT 24
Peak memory 200604 kb
Host smart-fccad65a-fafe-411c-a91d-bbf54a230b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469290247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3469290247
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.124548892
Short name T200
Test name
Test status
Simulation time 734869376 ps
CPU time 4.09 seconds
Started Apr 23 02:33:03 PM PDT 24
Finished Apr 23 02:33:07 PM PDT 24
Peak memory 200988 kb
Host smart-9ca4bc63-3bed-4262-a99c-945d4da7963e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124548892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.124548892
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2969908893
Short name T171
Test name
Test status
Simulation time 102995860 ps
CPU time 1.02 seconds
Started Apr 23 02:33:00 PM PDT 24
Finished Apr 23 02:33:01 PM PDT 24
Peak memory 200836 kb
Host smart-cc24c2c9-d33e-4aed-8c87-78df28bb5572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969908893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2969908893
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.579061972
Short name T220
Test name
Test status
Simulation time 236314729 ps
CPU time 1.44 seconds
Started Apr 23 02:33:04 PM PDT 24
Finished Apr 23 02:33:06 PM PDT 24
Peak memory 200940 kb
Host smart-13c86ae1-1206-486a-9f92-2c5637311b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579061972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.579061972
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2944103110
Short name T93
Test name
Test status
Simulation time 3871931482 ps
CPU time 16.93 seconds
Started Apr 23 02:33:07 PM PDT 24
Finished Apr 23 02:33:24 PM PDT 24
Peak memory 211056 kb
Host smart-4148225e-9ee1-4092-b1b0-abf259b16844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944103110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2944103110
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2521439759
Short name T295
Test name
Test status
Simulation time 148400442 ps
CPU time 1.7 seconds
Started Apr 23 02:33:01 PM PDT 24
Finished Apr 23 02:33:03 PM PDT 24
Peak memory 200760 kb
Host smart-c3bb71ed-ef87-42e7-80fd-64050e7f35e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521439759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2521439759
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2178523244
Short name T247
Test name
Test status
Simulation time 72195515 ps
CPU time 0.82 seconds
Started Apr 23 02:33:01 PM PDT 24
Finished Apr 23 02:33:02 PM PDT 24
Peak memory 200684 kb
Host smart-34593ac0-c177-4c53-81fb-df60cb265638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178523244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2178523244
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.27373391
Short name T377
Test name
Test status
Simulation time 79980643 ps
CPU time 0.78 seconds
Started Apr 23 02:33:08 PM PDT 24
Finished Apr 23 02:33:11 PM PDT 24
Peak memory 200636 kb
Host smart-daf33062-3091-4e3a-9a13-84105956334b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27373391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.27373391
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1854482864
Short name T42
Test name
Test status
Simulation time 1219080035 ps
CPU time 5.34 seconds
Started Apr 23 02:33:10 PM PDT 24
Finished Apr 23 02:33:16 PM PDT 24
Peak memory 218044 kb
Host smart-d87a1680-b06b-4e64-ad3f-7a7c0f855ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854482864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1854482864
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3950163746
Short name T192
Test name
Test status
Simulation time 245234532 ps
CPU time 1.06 seconds
Started Apr 23 02:33:09 PM PDT 24
Finished Apr 23 02:33:11 PM PDT 24
Peak memory 218076 kb
Host smart-14b6561f-47ff-40be-9309-7f6b2c0fb759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950163746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3950163746
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2494196003
Short name T302
Test name
Test status
Simulation time 181691520 ps
CPU time 0.85 seconds
Started Apr 23 02:33:04 PM PDT 24
Finished Apr 23 02:33:05 PM PDT 24
Peak memory 200640 kb
Host smart-1e0e2067-4f88-4632-be02-24a458a1a3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494196003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2494196003
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1114204778
Short name T253
Test name
Test status
Simulation time 1444367219 ps
CPU time 6.07 seconds
Started Apr 23 02:33:04 PM PDT 24
Finished Apr 23 02:33:11 PM PDT 24
Peak memory 201000 kb
Host smart-50c9fc3f-1530-44f8-9b81-1b4662f4bdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114204778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1114204778
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2646543870
Short name T281
Test name
Test status
Simulation time 183288647 ps
CPU time 1.18 seconds
Started Apr 23 02:33:09 PM PDT 24
Finished Apr 23 02:33:11 PM PDT 24
Peak memory 200824 kb
Host smart-a9731db9-3e8d-4698-80df-592043026367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646543870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2646543870
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1740594091
Short name T2
Test name
Test status
Simulation time 124902460 ps
CPU time 1.17 seconds
Started Apr 23 02:33:07 PM PDT 24
Finished Apr 23 02:33:08 PM PDT 24
Peak memory 201008 kb
Host smart-3b0b721f-15e5-4fb5-b0fd-adeee60a3e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740594091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1740594091
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.4196122582
Short name T126
Test name
Test status
Simulation time 2166959814 ps
CPU time 8.44 seconds
Started Apr 23 02:33:08 PM PDT 24
Finished Apr 23 02:33:18 PM PDT 24
Peak memory 201028 kb
Host smart-d0af911b-4153-4869-8c71-73b9da44c388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196122582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.4196122582
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.104066818
Short name T477
Test name
Test status
Simulation time 268317910 ps
CPU time 1.74 seconds
Started Apr 23 02:33:07 PM PDT 24
Finished Apr 23 02:33:09 PM PDT 24
Peak memory 200800 kb
Host smart-a90afc73-6baa-400d-bc88-72cf27e00355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104066818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.104066818
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3654332030
Short name T246
Test name
Test status
Simulation time 163871502 ps
CPU time 1.2 seconds
Started Apr 23 02:33:05 PM PDT 24
Finished Apr 23 02:33:07 PM PDT 24
Peak memory 200996 kb
Host smart-96315dec-e43a-41d1-a247-a936d58afc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654332030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3654332030
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4089668923
Short name T248
Test name
Test status
Simulation time 75819566 ps
CPU time 0.77 seconds
Started Apr 23 02:33:10 PM PDT 24
Finished Apr 23 02:33:12 PM PDT 24
Peak memory 200624 kb
Host smart-bfbe875f-f926-43df-a43b-62fde98208ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089668923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4089668923
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3932583105
Short name T267
Test name
Test status
Simulation time 2164843179 ps
CPU time 8.24 seconds
Started Apr 23 02:33:11 PM PDT 24
Finished Apr 23 02:33:20 PM PDT 24
Peak memory 222144 kb
Host smart-62145083-c5da-4b3b-96f5-2dc492827280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932583105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3932583105
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3526784498
Short name T516
Test name
Test status
Simulation time 244998096 ps
CPU time 1 seconds
Started Apr 23 02:33:11 PM PDT 24
Finished Apr 23 02:33:12 PM PDT 24
Peak memory 218180 kb
Host smart-26ab0601-153e-4992-beca-3a37cc393a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526784498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3526784498
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.737587811
Short name T229
Test name
Test status
Simulation time 118899042 ps
CPU time 0.85 seconds
Started Apr 23 02:33:09 PM PDT 24
Finished Apr 23 02:33:11 PM PDT 24
Peak memory 200648 kb
Host smart-7c72787c-b1ee-4714-9e91-7482d097fd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737587811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.737587811
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1857528579
Short name T216
Test name
Test status
Simulation time 793209006 ps
CPU time 4.12 seconds
Started Apr 23 02:33:07 PM PDT 24
Finished Apr 23 02:33:12 PM PDT 24
Peak memory 201032 kb
Host smart-0bc840d5-5576-43ab-89a6-6cdcbaad6a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857528579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1857528579
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4182311899
Short name T3
Test name
Test status
Simulation time 161620866 ps
CPU time 1.09 seconds
Started Apr 23 02:33:11 PM PDT 24
Finished Apr 23 02:33:12 PM PDT 24
Peak memory 200844 kb
Host smart-cf07a0df-bbf7-4815-81f0-74bb26fea243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182311899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4182311899
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2382153119
Short name T166
Test name
Test status
Simulation time 186041521 ps
CPU time 1.34 seconds
Started Apr 23 02:33:11 PM PDT 24
Finished Apr 23 02:33:13 PM PDT 24
Peak memory 200980 kb
Host smart-c92f5173-b220-4365-ac9f-ba7b7d7e54a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382153119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2382153119
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1678477208
Short name T206
Test name
Test status
Simulation time 11315285278 ps
CPU time 43.65 seconds
Started Apr 23 02:33:11 PM PDT 24
Finished Apr 23 02:33:56 PM PDT 24
Peak memory 209792 kb
Host smart-228a2e0f-6558-4ae4-9439-0badc2539206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678477208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1678477208
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2240195193
Short name T133
Test name
Test status
Simulation time 350281767 ps
CPU time 1.89 seconds
Started Apr 23 02:33:08 PM PDT 24
Finished Apr 23 02:33:11 PM PDT 24
Peak memory 200808 kb
Host smart-4b33b0df-b21f-4a4c-8902-b3caf0811b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240195193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2240195193
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1475785556
Short name T244
Test name
Test status
Simulation time 111666480 ps
CPU time 1.02 seconds
Started Apr 23 02:33:08 PM PDT 24
Finished Apr 23 02:33:11 PM PDT 24
Peak memory 200780 kb
Host smart-e3516973-9757-43aa-9344-76365344b296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475785556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1475785556
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3327954549
Short name T456
Test name
Test status
Simulation time 90320523 ps
CPU time 0.84 seconds
Started Apr 23 02:33:19 PM PDT 24
Finished Apr 23 02:33:21 PM PDT 24
Peak memory 200616 kb
Host smart-1f0a9af8-ee4e-4678-84d5-050aa502488e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327954549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3327954549
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.137442606
Short name T515
Test name
Test status
Simulation time 1890462998 ps
CPU time 7.2 seconds
Started Apr 23 02:33:14 PM PDT 24
Finished Apr 23 02:33:22 PM PDT 24
Peak memory 218632 kb
Host smart-0585f782-79e2-4a88-81b7-20b7c8c039d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137442606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.137442606
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.96924006
Short name T463
Test name
Test status
Simulation time 244904438 ps
CPU time 1.03 seconds
Started Apr 23 02:33:14 PM PDT 24
Finished Apr 23 02:33:15 PM PDT 24
Peak memory 218344 kb
Host smart-67c10b12-01c5-4c5a-81e5-d7330dc020fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96924006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.96924006
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.440827332
Short name T495
Test name
Test status
Simulation time 109825527 ps
CPU time 0.74 seconds
Started Apr 23 02:33:13 PM PDT 24
Finished Apr 23 02:33:14 PM PDT 24
Peak memory 200656 kb
Host smart-43d4f9e8-e766-4194-8773-6bfeb8c40164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440827332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.440827332
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2845478481
Short name T315
Test name
Test status
Simulation time 1099955459 ps
CPU time 4.88 seconds
Started Apr 23 02:33:14 PM PDT 24
Finished Apr 23 02:33:19 PM PDT 24
Peak memory 201000 kb
Host smart-3572398d-3281-4b5e-9e9b-71895bd341ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845478481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2845478481
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1598315045
Short name T469
Test name
Test status
Simulation time 101368506 ps
CPU time 0.97 seconds
Started Apr 23 02:33:13 PM PDT 24
Finished Apr 23 02:33:15 PM PDT 24
Peak memory 200836 kb
Host smart-f8e07c2e-094a-4d33-9c54-473858a9779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598315045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1598315045
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.381978309
Short name T341
Test name
Test status
Simulation time 249444014 ps
CPU time 1.46 seconds
Started Apr 23 02:33:13 PM PDT 24
Finished Apr 23 02:33:15 PM PDT 24
Peak memory 200976 kb
Host smart-1161b25a-655d-4e19-b563-308c5e14f686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381978309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.381978309
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2855521387
Short name T313
Test name
Test status
Simulation time 16513913963 ps
CPU time 54.71 seconds
Started Apr 23 02:33:16 PM PDT 24
Finished Apr 23 02:34:11 PM PDT 24
Peak memory 201024 kb
Host smart-0d7711ed-2c68-4607-8c19-4980ad777655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855521387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2855521387
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2034615052
Short name T520
Test name
Test status
Simulation time 409456708 ps
CPU time 2.28 seconds
Started Apr 23 02:33:13 PM PDT 24
Finished Apr 23 02:33:16 PM PDT 24
Peak memory 208892 kb
Host smart-c2c08a5c-63ff-4f06-8f88-de54eeb1b06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034615052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2034615052
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3029643051
Short name T345
Test name
Test status
Simulation time 177706189 ps
CPU time 1.09 seconds
Started Apr 23 02:33:13 PM PDT 24
Finished Apr 23 02:33:15 PM PDT 24
Peak memory 200836 kb
Host smart-63739161-33fa-4325-8661-5cb3a5636119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029643051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3029643051
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1463643500
Short name T438
Test name
Test status
Simulation time 76317219 ps
CPU time 0.77 seconds
Started Apr 23 02:33:25 PM PDT 24
Finished Apr 23 02:33:26 PM PDT 24
Peak memory 200668 kb
Host smart-e9339188-31b7-4c7f-81aa-60cd7ec1e43a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463643500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1463643500
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.688309542
Short name T29
Test name
Test status
Simulation time 1226784170 ps
CPU time 5.37 seconds
Started Apr 23 02:33:21 PM PDT 24
Finished Apr 23 02:33:27 PM PDT 24
Peak memory 222744 kb
Host smart-def26e4e-683a-4126-815f-712f913ef6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688309542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.688309542
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1807659150
Short name T464
Test name
Test status
Simulation time 244541557 ps
CPU time 1.03 seconds
Started Apr 23 02:33:20 PM PDT 24
Finished Apr 23 02:33:22 PM PDT 24
Peak memory 218152 kb
Host smart-2b2eeee3-6361-4ab7-998f-fb4868ad8f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807659150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1807659150
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2517652315
Short name T459
Test name
Test status
Simulation time 124574626 ps
CPU time 0.79 seconds
Started Apr 23 02:33:16 PM PDT 24
Finished Apr 23 02:33:17 PM PDT 24
Peak memory 200604 kb
Host smart-68c233ab-20fe-42ce-b538-8f4667af3fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517652315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2517652315
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2488427898
Short name T474
Test name
Test status
Simulation time 845574640 ps
CPU time 4.44 seconds
Started Apr 23 02:33:22 PM PDT 24
Finished Apr 23 02:33:27 PM PDT 24
Peak memory 201004 kb
Host smart-b5464bcd-285f-4507-925d-096ed10a1bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488427898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2488427898
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1102913285
Short name T215
Test name
Test status
Simulation time 98031106 ps
CPU time 1.18 seconds
Started Apr 23 02:33:27 PM PDT 24
Finished Apr 23 02:33:29 PM PDT 24
Peak memory 200848 kb
Host smart-55f8bdc8-ce8c-4232-a595-81272cd8af82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102913285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1102913285
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2199882062
Short name T285
Test name
Test status
Simulation time 221458061 ps
CPU time 1.38 seconds
Started Apr 23 02:33:18 PM PDT 24
Finished Apr 23 02:33:20 PM PDT 24
Peak memory 201036 kb
Host smart-18e1f3f5-0079-44a6-94d4-5199bb7a45ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199882062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2199882062
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.252855251
Short name T99
Test name
Test status
Simulation time 5869873437 ps
CPU time 24.67 seconds
Started Apr 23 02:33:20 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 209240 kb
Host smart-73998da7-c911-4c2d-9879-74bce70f3fed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252855251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.252855251
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.245197672
Short name T370
Test name
Test status
Simulation time 504498819 ps
CPU time 2.78 seconds
Started Apr 23 02:33:19 PM PDT 24
Finished Apr 23 02:33:23 PM PDT 24
Peak memory 200816 kb
Host smart-69500d32-23e0-434a-863c-9b3d837dba18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245197672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.245197672
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4141674759
Short name T228
Test name
Test status
Simulation time 96124844 ps
CPU time 0.92 seconds
Started Apr 23 02:33:22 PM PDT 24
Finished Apr 23 02:33:24 PM PDT 24
Peak memory 200800 kb
Host smart-56d92eeb-506b-4bd9-98b7-120754723928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141674759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4141674759
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4215087349
Short name T510
Test name
Test status
Simulation time 75287880 ps
CPU time 0.73 seconds
Started Apr 23 02:32:12 PM PDT 24
Finished Apr 23 02:32:13 PM PDT 24
Peak memory 200584 kb
Host smart-96f6fcf8-cbfa-4318-9ee6-cd6e135cd0c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215087349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4215087349
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3922048313
Short name T375
Test name
Test status
Simulation time 1881386495 ps
CPU time 7.15 seconds
Started Apr 23 02:32:11 PM PDT 24
Finished Apr 23 02:32:18 PM PDT 24
Peak memory 222692 kb
Host smart-1fb78e7f-b57a-44b6-bf72-61d4228ea35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922048313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3922048313
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.374847735
Short name T161
Test name
Test status
Simulation time 244320207 ps
CPU time 1.05 seconds
Started Apr 23 02:32:10 PM PDT 24
Finished Apr 23 02:32:12 PM PDT 24
Peak memory 218332 kb
Host smart-ce7fe50a-b44c-4ceb-b940-44feb030e2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374847735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.374847735
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1278712376
Short name T21
Test name
Test status
Simulation time 152330647 ps
CPU time 0.81 seconds
Started Apr 23 02:32:08 PM PDT 24
Finished Apr 23 02:32:09 PM PDT 24
Peak memory 200620 kb
Host smart-2aad9336-bcad-4d55-b462-15aff03cb5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278712376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1278712376
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3978463425
Short name T224
Test name
Test status
Simulation time 799036733 ps
CPU time 4.3 seconds
Started Apr 23 02:32:09 PM PDT 24
Finished Apr 23 02:32:13 PM PDT 24
Peak memory 201040 kb
Host smart-1ef1fac2-98b2-4c3d-a55a-d945ed1148e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978463425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3978463425
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.4236129618
Short name T83
Test name
Test status
Simulation time 8387964941 ps
CPU time 12.51 seconds
Started Apr 23 02:32:11 PM PDT 24
Finished Apr 23 02:32:24 PM PDT 24
Peak memory 217744 kb
Host smart-b8161d20-0495-4fa0-99e2-aa71cc8a447a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236129618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.4236129618
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4165624187
Short name T531
Test name
Test status
Simulation time 110995966 ps
CPU time 1 seconds
Started Apr 23 02:32:10 PM PDT 24
Finished Apr 23 02:32:11 PM PDT 24
Peak memory 200844 kb
Host smart-e0426887-3591-4661-a841-1bec0af303dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165624187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4165624187
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3739544115
Short name T292
Test name
Test status
Simulation time 199566002 ps
CPU time 1.36 seconds
Started Apr 23 02:32:04 PM PDT 24
Finished Apr 23 02:32:06 PM PDT 24
Peak memory 200992 kb
Host smart-3eac2fef-1107-437c-8ab1-5d01d0caf133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739544115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3739544115
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2224583700
Short name T460
Test name
Test status
Simulation time 7240844201 ps
CPU time 32.68 seconds
Started Apr 23 02:32:11 PM PDT 24
Finished Apr 23 02:32:44 PM PDT 24
Peak memory 210880 kb
Host smart-f1d50b30-7d6d-4fa9-95cc-c3a4df9dc9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224583700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2224583700
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.534618644
Short name T53
Test name
Test status
Simulation time 110276038 ps
CPU time 1.47 seconds
Started Apr 23 02:32:17 PM PDT 24
Finished Apr 23 02:32:19 PM PDT 24
Peak memory 200828 kb
Host smart-b214185c-c52b-4f42-87e6-3ee5cd1a232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534618644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.534618644
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.364005058
Short name T364
Test name
Test status
Simulation time 62733085 ps
CPU time 0.74 seconds
Started Apr 23 02:33:24 PM PDT 24
Finished Apr 23 02:33:25 PM PDT 24
Peak memory 200580 kb
Host smart-ec179db9-ea3b-43d5-a484-29d7d89d479f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364005058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.364005058
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3051919821
Short name T255
Test name
Test status
Simulation time 243318445 ps
CPU time 1.06 seconds
Started Apr 23 02:33:22 PM PDT 24
Finished Apr 23 02:33:24 PM PDT 24
Peak memory 218332 kb
Host smart-6c2ed2be-8474-4e30-9def-5f56fb1164df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051919821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3051919821
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3397891628
Short name T222
Test name
Test status
Simulation time 184124739 ps
CPU time 0.88 seconds
Started Apr 23 02:33:23 PM PDT 24
Finished Apr 23 02:33:25 PM PDT 24
Peak memory 200604 kb
Host smart-2a2d2e1a-7540-4710-b58f-b0f492f19e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397891628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3397891628
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2461879921
Short name T475
Test name
Test status
Simulation time 2014578821 ps
CPU time 7.78 seconds
Started Apr 23 02:33:23 PM PDT 24
Finished Apr 23 02:33:32 PM PDT 24
Peak memory 200988 kb
Host smart-c1a177d1-4e5a-4cb4-94bd-524584c0f920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461879921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2461879921
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3600139855
Short name T427
Test name
Test status
Simulation time 146908867 ps
CPU time 1.09 seconds
Started Apr 23 02:33:24 PM PDT 24
Finished Apr 23 02:33:26 PM PDT 24
Peak memory 200852 kb
Host smart-5b18f2b6-c704-48da-854e-5435a373afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600139855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3600139855
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.789082586
Short name T407
Test name
Test status
Simulation time 226071894 ps
CPU time 1.47 seconds
Started Apr 23 02:33:22 PM PDT 24
Finished Apr 23 02:33:24 PM PDT 24
Peak memory 201008 kb
Host smart-0ce97dba-ea7a-4c71-9be3-a70b725415c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789082586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.789082586
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3410977149
Short name T96
Test name
Test status
Simulation time 8459562732 ps
CPU time 33.88 seconds
Started Apr 23 02:33:24 PM PDT 24
Finished Apr 23 02:33:58 PM PDT 24
Peak memory 209136 kb
Host smart-bb156b2b-28f5-401a-b746-8a9ffd06a85a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410977149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3410977149
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3074368249
Short name T454
Test name
Test status
Simulation time 115236383 ps
CPU time 1.44 seconds
Started Apr 23 02:33:25 PM PDT 24
Finished Apr 23 02:33:27 PM PDT 24
Peak memory 200824 kb
Host smart-e7a8faf5-545f-42a6-9790-5fbb4de66d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074368249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3074368249
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.78143236
Short name T416
Test name
Test status
Simulation time 151372927 ps
CPU time 1.12 seconds
Started Apr 23 02:33:24 PM PDT 24
Finished Apr 23 02:33:26 PM PDT 24
Peak memory 200820 kb
Host smart-9cf5f1fc-c960-42c3-8756-ed2b1bfd66cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78143236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.78143236
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3846764346
Short name T458
Test name
Test status
Simulation time 93737857 ps
CPU time 0.81 seconds
Started Apr 23 02:33:31 PM PDT 24
Finished Apr 23 02:33:32 PM PDT 24
Peak memory 200644 kb
Host smart-867f370b-6450-420b-8425-7ba3af5be18f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846764346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3846764346
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.211179816
Short name T61
Test name
Test status
Simulation time 2362720613 ps
CPU time 8.9 seconds
Started Apr 23 02:33:26 PM PDT 24
Finished Apr 23 02:33:36 PM PDT 24
Peak memory 222492 kb
Host smart-5c268937-3ed8-4600-987f-44c2e7eb3c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211179816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.211179816
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1047102989
Short name T394
Test name
Test status
Simulation time 243787061 ps
CPU time 1.03 seconds
Started Apr 23 02:33:25 PM PDT 24
Finished Apr 23 02:33:27 PM PDT 24
Peak memory 218132 kb
Host smart-4b619ce1-47e1-450d-a18b-9ca6ce41795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047102989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1047102989
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2580755828
Short name T528
Test name
Test status
Simulation time 229654063 ps
CPU time 0.89 seconds
Started Apr 23 02:33:26 PM PDT 24
Finished Apr 23 02:33:28 PM PDT 24
Peak memory 200644 kb
Host smart-6b977c9f-ee9c-4b1c-8489-058151d50b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580755828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2580755828
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2417148876
Short name T307
Test name
Test status
Simulation time 727828944 ps
CPU time 3.96 seconds
Started Apr 23 02:33:24 PM PDT 24
Finished Apr 23 02:33:29 PM PDT 24
Peak memory 201004 kb
Host smart-19963b43-2b28-4e29-8e9d-94225be262fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417148876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2417148876
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.762850557
Short name T308
Test name
Test status
Simulation time 116107303 ps
CPU time 1.04 seconds
Started Apr 23 02:33:31 PM PDT 24
Finished Apr 23 02:33:33 PM PDT 24
Peak memory 200844 kb
Host smart-d4a346e0-d526-4120-b97d-5dfec81a9197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762850557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.762850557
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1135917719
Short name T387
Test name
Test status
Simulation time 126898269 ps
CPU time 1.21 seconds
Started Apr 23 02:33:22 PM PDT 24
Finished Apr 23 02:33:24 PM PDT 24
Peak memory 201040 kb
Host smart-ad4b0f60-b57e-44f6-b01e-6afa0bd8318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135917719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1135917719
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.702791222
Short name T196
Test name
Test status
Simulation time 531748913 ps
CPU time 2.38 seconds
Started Apr 23 02:33:27 PM PDT 24
Finished Apr 23 02:33:30 PM PDT 24
Peak memory 200968 kb
Host smart-fd970fdd-5ac4-4077-8e25-c35c6af21288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702791222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.702791222
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1437325273
Short name T135
Test name
Test status
Simulation time 503953861 ps
CPU time 2.62 seconds
Started Apr 23 02:33:34 PM PDT 24
Finished Apr 23 02:33:37 PM PDT 24
Peak memory 200796 kb
Host smart-b25ec4e8-a2f8-44b9-8040-29cc89a9cad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437325273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1437325273
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2045533892
Short name T203
Test name
Test status
Simulation time 100201306 ps
CPU time 0.87 seconds
Started Apr 23 02:33:26 PM PDT 24
Finished Apr 23 02:33:27 PM PDT 24
Peak memory 200832 kb
Host smart-229912cc-3d3e-4aa9-8348-a2902c5ecc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045533892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2045533892
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.125106935
Short name T30
Test name
Test status
Simulation time 2366431175 ps
CPU time 7.69 seconds
Started Apr 23 02:33:26 PM PDT 24
Finished Apr 23 02:33:35 PM PDT 24
Peak memory 218400 kb
Host smart-bce429a1-d09c-4e92-af6b-d3d300b78a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125106935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.125106935
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1391060544
Short name T199
Test name
Test status
Simulation time 243773712 ps
CPU time 1.08 seconds
Started Apr 23 02:33:32 PM PDT 24
Finished Apr 23 02:33:33 PM PDT 24
Peak memory 218072 kb
Host smart-08d19652-dcab-45fc-979e-13a76168184b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391060544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1391060544
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3747635943
Short name T450
Test name
Test status
Simulation time 138117184 ps
CPU time 0.78 seconds
Started Apr 23 02:33:27 PM PDT 24
Finished Apr 23 02:33:28 PM PDT 24
Peak memory 200548 kb
Host smart-581e8528-a784-47db-8582-e781dc3a1b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747635943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3747635943
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.470101582
Short name T127
Test name
Test status
Simulation time 1703886254 ps
CPU time 6.6 seconds
Started Apr 23 02:33:26 PM PDT 24
Finished Apr 23 02:33:33 PM PDT 24
Peak memory 200940 kb
Host smart-d40600aa-613d-48c5-acf7-6dacc7020ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470101582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.470101582
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1819871763
Short name T48
Test name
Test status
Simulation time 175287939 ps
CPU time 1.25 seconds
Started Apr 23 02:33:31 PM PDT 24
Finished Apr 23 02:33:32 PM PDT 24
Peak memory 200840 kb
Host smart-6ebdecde-494d-45a9-8329-755d6d459963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819871763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1819871763
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.140878294
Short name T236
Test name
Test status
Simulation time 218658902 ps
CPU time 1.39 seconds
Started Apr 23 02:33:27 PM PDT 24
Finished Apr 23 02:33:29 PM PDT 24
Peak memory 201000 kb
Host smart-7f94bce6-8bd3-4bc7-91eb-4400b83010d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140878294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.140878294
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.413061497
Short name T481
Test name
Test status
Simulation time 3430227472 ps
CPU time 12.11 seconds
Started Apr 23 02:33:35 PM PDT 24
Finished Apr 23 02:33:48 PM PDT 24
Peak memory 210784 kb
Host smart-20bbf27e-436c-4e13-af1d-09df48ad8545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413061497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.413061497
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2737110555
Short name T36
Test name
Test status
Simulation time 360785420 ps
CPU time 1.96 seconds
Started Apr 23 02:33:32 PM PDT 24
Finished Apr 23 02:33:34 PM PDT 24
Peak memory 200820 kb
Host smart-21d1c22e-b43d-496f-b2dd-3866238ba145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737110555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2737110555
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1186815675
Short name T139
Test name
Test status
Simulation time 130619469 ps
CPU time 1.06 seconds
Started Apr 23 02:33:27 PM PDT 24
Finished Apr 23 02:33:28 PM PDT 24
Peak memory 200772 kb
Host smart-4071b428-bab3-4014-b844-8784b1dc154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186815675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1186815675
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.755552126
Short name T373
Test name
Test status
Simulation time 92273875 ps
CPU time 0.88 seconds
Started Apr 23 02:33:35 PM PDT 24
Finished Apr 23 02:33:37 PM PDT 24
Peak memory 200624 kb
Host smart-881c9d4f-e142-4f9f-ade6-cedae030af91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755552126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.755552126
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3349189038
Short name T330
Test name
Test status
Simulation time 1895589775 ps
CPU time 7.03 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 218060 kb
Host smart-9a9d394d-dcbf-43f8-9eba-df9b7ca86c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349189038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3349189038
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4147422756
Short name T379
Test name
Test status
Simulation time 244325297 ps
CPU time 1.12 seconds
Started Apr 23 02:33:34 PM PDT 24
Finished Apr 23 02:33:35 PM PDT 24
Peak memory 218176 kb
Host smart-bcb9314f-8a92-4b17-a68a-3393d2a1513a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147422756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4147422756
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1879314067
Short name T487
Test name
Test status
Simulation time 123983205 ps
CPU time 0.77 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 200640 kb
Host smart-0d6d4c1c-b25b-438e-88c7-4287b592a428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879314067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1879314067
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.159880791
Short name T522
Test name
Test status
Simulation time 1982373614 ps
CPU time 7.1 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 201000 kb
Host smart-924b09f7-e3ab-444f-94ef-43d2f2c8d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159880791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.159880791
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.690454071
Short name T512
Test name
Test status
Simulation time 158611438 ps
CPU time 1.07 seconds
Started Apr 23 02:33:34 PM PDT 24
Finished Apr 23 02:33:35 PM PDT 24
Peak memory 200836 kb
Host smart-fa349fda-1956-4640-ab81-c24e464f9636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690454071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.690454071
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1915647299
Short name T195
Test name
Test status
Simulation time 124483728 ps
CPU time 1.31 seconds
Started Apr 23 02:33:34 PM PDT 24
Finished Apr 23 02:33:36 PM PDT 24
Peak memory 201032 kb
Host smart-ef818ec8-87b3-4f97-8454-8eea12095205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915647299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1915647299
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1632402936
Short name T104
Test name
Test status
Simulation time 5153157888 ps
CPU time 22.34 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:59 PM PDT 24
Peak memory 201044 kb
Host smart-5641fb11-0cb0-4670-aa6f-ad2060cf4b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632402936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1632402936
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.170596057
Short name T249
Test name
Test status
Simulation time 537001360 ps
CPU time 2.67 seconds
Started Apr 23 02:33:28 PM PDT 24
Finished Apr 23 02:33:31 PM PDT 24
Peak memory 200796 kb
Host smart-f6594efa-1c23-49d8-9819-bb8151bf5e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170596057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.170596057
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2923671926
Short name T355
Test name
Test status
Simulation time 102743007 ps
CPU time 0.84 seconds
Started Apr 23 02:33:38 PM PDT 24
Finished Apr 23 02:33:40 PM PDT 24
Peak memory 200808 kb
Host smart-8783079a-e186-4ac2-be0b-71bd6af673ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923671926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2923671926
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3999866913
Short name T235
Test name
Test status
Simulation time 80985723 ps
CPU time 0.9 seconds
Started Apr 23 02:33:43 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 200644 kb
Host smart-8f94de11-1cc0-4309-9813-83b5ab92ba99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999866913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3999866913
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.344637291
Short name T33
Test name
Test status
Simulation time 1900786153 ps
CPU time 7.17 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 217932 kb
Host smart-fb23bbaf-48b8-4dd3-a933-fdb7016988ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344637291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.344637291
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3470668419
Short name T279
Test name
Test status
Simulation time 246411751 ps
CPU time 1.06 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 217960 kb
Host smart-b917f6c2-4c37-403a-8683-f9cf485bf0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470668419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3470668419
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.509772383
Short name T265
Test name
Test status
Simulation time 109414790 ps
CPU time 0.75 seconds
Started Apr 23 02:33:33 PM PDT 24
Finished Apr 23 02:33:34 PM PDT 24
Peak memory 200652 kb
Host smart-b3e9207e-14d4-4ea7-bea6-f61d97f9c23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509772383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.509772383
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.621417475
Short name T129
Test name
Test status
Simulation time 2012208426 ps
CPU time 6.87 seconds
Started Apr 23 02:33:35 PM PDT 24
Finished Apr 23 02:33:43 PM PDT 24
Peak memory 201000 kb
Host smart-c3b1780e-7e41-4681-b982-617e9d0131ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621417475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.621417475
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.656972050
Short name T414
Test name
Test status
Simulation time 106068703 ps
CPU time 1.03 seconds
Started Apr 23 02:33:38 PM PDT 24
Finished Apr 23 02:33:40 PM PDT 24
Peak memory 200800 kb
Host smart-ef61ad51-5c58-42bd-a59d-b3a29e64339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656972050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.656972050
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2650688696
Short name T233
Test name
Test status
Simulation time 121029305 ps
CPU time 1.19 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 200984 kb
Host smart-566e3a57-41a5-40a6-8db9-af94fb4410a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650688696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2650688696
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1706935539
Short name T168
Test name
Test status
Simulation time 320325276 ps
CPU time 2.1 seconds
Started Apr 23 02:33:39 PM PDT 24
Finished Apr 23 02:33:42 PM PDT 24
Peak memory 200784 kb
Host smart-3736a9a0-e8e8-424d-ab7e-dd66ba1b82ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706935539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1706935539
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2798931832
Short name T156
Test name
Test status
Simulation time 58540413 ps
CPU time 0.72 seconds
Started Apr 23 02:33:35 PM PDT 24
Finished Apr 23 02:33:36 PM PDT 24
Peak memory 200792 kb
Host smart-3db915a6-db7b-4924-aced-4d5d7f2abfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798931832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2798931832
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1473833258
Short name T167
Test name
Test status
Simulation time 91037462 ps
CPU time 0.8 seconds
Started Apr 23 02:33:38 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 200632 kb
Host smart-68c434c7-43f2-4dc9-b548-82b6c0a53355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473833258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1473833258
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3249931051
Short name T404
Test name
Test status
Simulation time 2349838862 ps
CPU time 8.16 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 218632 kb
Host smart-29b26b21-cef4-46e0-831f-7cdadb465611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249931051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3249931051
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4076509212
Short name T499
Test name
Test status
Simulation time 244525237 ps
CPU time 1 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 218332 kb
Host smart-2d8d0edc-6933-4ae5-ae2d-9c8a21429966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076509212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4076509212
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.4236155588
Short name T536
Test name
Test status
Simulation time 212080388 ps
CPU time 0.97 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 200628 kb
Host smart-d7d89236-231a-4dde-b0a8-64cae371893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236155588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.4236155588
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.4143483714
Short name T351
Test name
Test status
Simulation time 2040663253 ps
CPU time 6.85 seconds
Started Apr 23 02:33:33 PM PDT 24
Finished Apr 23 02:33:40 PM PDT 24
Peak memory 200980 kb
Host smart-6cf265cd-79ce-4323-a9f8-42d18570badd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143483714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4143483714
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.923472974
Short name T540
Test name
Test status
Simulation time 176990797 ps
CPU time 1.21 seconds
Started Apr 23 02:33:35 PM PDT 24
Finished Apr 23 02:33:37 PM PDT 24
Peak memory 200828 kb
Host smart-937e3ca5-5367-41ca-9eac-530d97b5d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923472974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.923472974
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2643060950
Short name T260
Test name
Test status
Simulation time 201913068 ps
CPU time 1.36 seconds
Started Apr 23 02:33:35 PM PDT 24
Finished Apr 23 02:33:37 PM PDT 24
Peak memory 201004 kb
Host smart-1dcaaa2b-a32b-4b0c-ae49-648fb7a9a16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643060950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2643060950
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3886510541
Short name T94
Test name
Test status
Simulation time 3942142491 ps
CPU time 17.69 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:55 PM PDT 24
Peak memory 209200 kb
Host smart-71461458-d0d3-434f-be36-0d6f537a6511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886510541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3886510541
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2804060009
Short name T498
Test name
Test status
Simulation time 296162468 ps
CPU time 1.89 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 209008 kb
Host smart-7f2bb2fd-26f6-4ee5-b84b-ebba4184ea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804060009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2804060009
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.860191165
Short name T296
Test name
Test status
Simulation time 215324937 ps
CPU time 1.32 seconds
Started Apr 23 02:33:39 PM PDT 24
Finished Apr 23 02:33:41 PM PDT 24
Peak memory 200792 kb
Host smart-1c7f7ef0-f87c-4c76-a8dd-395da7ac2d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860191165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.860191165
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1957104745
Short name T193
Test name
Test status
Simulation time 75569906 ps
CPU time 0.79 seconds
Started Apr 23 02:33:43 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 200644 kb
Host smart-abfb6124-002c-4142-885b-f81bdb8ba9a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957104745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1957104745
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2774355803
Short name T428
Test name
Test status
Simulation time 2361013882 ps
CPU time 7.95 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:46 PM PDT 24
Peak memory 221964 kb
Host smart-54043d32-516d-473f-a1c2-3453f41e0a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774355803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2774355803
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2550154992
Short name T268
Test name
Test status
Simulation time 244733089 ps
CPU time 1.12 seconds
Started Apr 23 02:33:43 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 218196 kb
Host smart-4ecaee7e-3066-490e-a2a1-f6aa8000cfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550154992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2550154992
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.977251339
Short name T468
Test name
Test status
Simulation time 100733859 ps
CPU time 0.74 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:37 PM PDT 24
Peak memory 200664 kb
Host smart-c3b0f609-5f9b-4d4b-852b-fa0318a778b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977251339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.977251339
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2941980736
Short name T496
Test name
Test status
Simulation time 811246986 ps
CPU time 3.89 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:41 PM PDT 24
Peak memory 200944 kb
Host smart-97d37d84-bd2a-45d7-9064-089094b4185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941980736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2941980736
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2810976204
Short name T328
Test name
Test status
Simulation time 190694821 ps
CPU time 1.31 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:38 PM PDT 24
Peak memory 200856 kb
Host smart-f22eb8ae-2e6b-4611-99cd-1d7ff221d267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810976204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2810976204
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3528165083
Short name T245
Test name
Test status
Simulation time 203821606 ps
CPU time 1.39 seconds
Started Apr 23 02:33:35 PM PDT 24
Finished Apr 23 02:33:37 PM PDT 24
Peak memory 201072 kb
Host smart-a1154a70-c176-4eca-be5a-4928de3c1be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528165083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3528165083
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1882731301
Short name T410
Test name
Test status
Simulation time 1158950426 ps
CPU time 5.09 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:43 PM PDT 24
Peak memory 200968 kb
Host smart-041dd855-6bff-4ee3-be56-26e84f1a0809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882731301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1882731301
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.4220994908
Short name T314
Test name
Test status
Simulation time 323326233 ps
CPU time 2.05 seconds
Started Apr 23 02:33:38 PM PDT 24
Finished Apr 23 02:33:41 PM PDT 24
Peak memory 200820 kb
Host smart-f053c8ad-90d4-4a1a-8aa1-df68c6efa71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220994908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4220994908
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.937515947
Short name T174
Test name
Test status
Simulation time 110195858 ps
CPU time 0.99 seconds
Started Apr 23 02:33:42 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 200832 kb
Host smart-e9621b39-72d2-45cc-bca3-e60c39a4b5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937515947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.937515947
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.4103808874
Short name T333
Test name
Test status
Simulation time 101122076 ps
CPU time 0.86 seconds
Started Apr 23 02:33:40 PM PDT 24
Finished Apr 23 02:33:41 PM PDT 24
Peak memory 200560 kb
Host smart-a0abb5c0-a81a-4af8-a860-a737fbd6eaa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103808874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.4103808874
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3439271830
Short name T26
Test name
Test status
Simulation time 1227786354 ps
CPU time 5.69 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:43 PM PDT 24
Peak memory 230520 kb
Host smart-69520652-208b-49dd-849d-cbe163f6948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439271830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3439271830
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2817460391
Short name T259
Test name
Test status
Simulation time 244576692 ps
CPU time 1.06 seconds
Started Apr 23 02:33:38 PM PDT 24
Finished Apr 23 02:33:40 PM PDT 24
Peak memory 218080 kb
Host smart-0715cdd6-b464-449a-b89d-7cf8f1589421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817460391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2817460391
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1974790616
Short name T5
Test name
Test status
Simulation time 147736565 ps
CPU time 0.85 seconds
Started Apr 23 02:33:36 PM PDT 24
Finished Apr 23 02:33:38 PM PDT 24
Peak memory 200620 kb
Host smart-fb90faa0-eb65-4dcf-b923-647c93538c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974790616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1974790616
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.191366053
Short name T479
Test name
Test status
Simulation time 766712502 ps
CPU time 3.69 seconds
Started Apr 23 02:33:39 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 201004 kb
Host smart-98df7b16-a9b8-4664-9ff7-9c9a89945344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191366053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.191366053
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2780825375
Short name T461
Test name
Test status
Simulation time 174399770 ps
CPU time 1.19 seconds
Started Apr 23 02:33:41 PM PDT 24
Finished Apr 23 02:33:43 PM PDT 24
Peak memory 200808 kb
Host smart-8cb351fe-6b83-4ff5-9870-0e11c83c2090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780825375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2780825375
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2142089850
Short name T534
Test name
Test status
Simulation time 109028705 ps
CPU time 1.12 seconds
Started Apr 23 02:33:37 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 200948 kb
Host smart-2aa8f549-fd7b-48b6-8f81-5f3a705e6da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142089850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2142089850
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2081216327
Short name T506
Test name
Test status
Simulation time 5935696137 ps
CPU time 26.05 seconds
Started Apr 23 02:33:40 PM PDT 24
Finished Apr 23 02:34:06 PM PDT 24
Peak memory 209276 kb
Host smart-15c0a70b-8a30-4af7-b005-81b5c9840e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081216327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2081216327
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1936314572
Short name T301
Test name
Test status
Simulation time 145287492 ps
CPU time 1.74 seconds
Started Apr 23 02:33:39 PM PDT 24
Finished Apr 23 02:33:41 PM PDT 24
Peak memory 200776 kb
Host smart-772dbf51-23c0-4211-a65f-217504c0549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936314572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1936314572
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4028565126
Short name T357
Test name
Test status
Simulation time 102816784 ps
CPU time 1 seconds
Started Apr 23 02:33:42 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 200832 kb
Host smart-b5039380-3924-4d59-8b55-35d751864a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028565126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4028565126
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1558007098
Short name T402
Test name
Test status
Simulation time 69950718 ps
CPU time 0.82 seconds
Started Apr 23 02:33:43 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 200640 kb
Host smart-dfb882d9-7847-4551-9ea0-4cc8211ee5f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558007098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1558007098
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.903023177
Short name T491
Test name
Test status
Simulation time 1901249524 ps
CPU time 7.65 seconds
Started Apr 23 02:33:40 PM PDT 24
Finished Apr 23 02:33:48 PM PDT 24
Peak memory 230864 kb
Host smart-5bca0e89-c010-4e8b-bf0b-ff68ad3419a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903023177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.903023177
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1319424797
Short name T172
Test name
Test status
Simulation time 244330161 ps
CPU time 1.03 seconds
Started Apr 23 02:33:40 PM PDT 24
Finished Apr 23 02:33:42 PM PDT 24
Peak memory 218068 kb
Host smart-14055eb7-058b-4b0a-a0ed-df23ea8a77be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319424797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1319424797
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2514539441
Short name T217
Test name
Test status
Simulation time 206944703 ps
CPU time 0.93 seconds
Started Apr 23 02:33:46 PM PDT 24
Finished Apr 23 02:33:47 PM PDT 24
Peak memory 200648 kb
Host smart-b2a9d9b8-36c8-4bb6-ab2b-0514819f5b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514539441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2514539441
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3512606060
Short name T204
Test name
Test status
Simulation time 851083653 ps
CPU time 4.48 seconds
Started Apr 23 02:33:40 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 200924 kb
Host smart-a3e3aa24-24e9-4f37-ba39-25b7facb2f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512606060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3512606060
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.117187687
Short name T289
Test name
Test status
Simulation time 149039336 ps
CPU time 1.03 seconds
Started Apr 23 02:33:42 PM PDT 24
Finished Apr 23 02:33:43 PM PDT 24
Peak memory 200860 kb
Host smart-742e4b97-32f4-4975-85f6-31b97cfe3804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117187687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.117187687
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2656531240
Short name T147
Test name
Test status
Simulation time 111204078 ps
CPU time 1.17 seconds
Started Apr 23 02:33:38 PM PDT 24
Finished Apr 23 02:33:40 PM PDT 24
Peak memory 201012 kb
Host smart-e56943b6-03d3-4728-8d0c-9da2992db093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656531240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2656531240
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.464614502
Short name T250
Test name
Test status
Simulation time 6770461147 ps
CPU time 30.7 seconds
Started Apr 23 02:33:45 PM PDT 24
Finished Apr 23 02:34:16 PM PDT 24
Peak memory 201088 kb
Host smart-155fd140-cfd3-476d-976d-a6c857727840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464614502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.464614502
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3172013386
Short name T71
Test name
Test status
Simulation time 142493059 ps
CPU time 1.87 seconds
Started Apr 23 02:33:42 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 200800 kb
Host smart-bffedca0-866f-491e-af47-af338c535539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172013386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3172013386
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.38797910
Short name T354
Test name
Test status
Simulation time 273275414 ps
CPU time 1.4 seconds
Started Apr 23 02:33:39 PM PDT 24
Finished Apr 23 02:33:42 PM PDT 24
Peak memory 200840 kb
Host smart-7a9580b3-85d8-4234-adf9-3f64d6a46da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38797910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.38797910
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.319823164
Short name T35
Test name
Test status
Simulation time 79408792 ps
CPU time 0.73 seconds
Started Apr 23 02:33:44 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 200624 kb
Host smart-da41d3c9-0536-47fc-ac51-b466dccd8ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319823164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.319823164
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1368884182
Short name T25
Test name
Test status
Simulation time 1221167166 ps
CPU time 5.37 seconds
Started Apr 23 02:33:40 PM PDT 24
Finished Apr 23 02:33:46 PM PDT 24
Peak memory 218120 kb
Host smart-1893099d-885c-4e56-ba40-6e02dc959d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368884182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1368884182
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2482932653
Short name T252
Test name
Test status
Simulation time 244569711 ps
CPU time 0.99 seconds
Started Apr 23 02:33:42 PM PDT 24
Finished Apr 23 02:33:43 PM PDT 24
Peak memory 218172 kb
Host smart-46bcf10e-a643-43f7-bf9c-3eebf68c3528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482932653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2482932653
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2572500193
Short name T14
Test name
Test status
Simulation time 192412750 ps
CPU time 0.87 seconds
Started Apr 23 02:33:40 PM PDT 24
Finished Apr 23 02:33:42 PM PDT 24
Peak memory 200604 kb
Host smart-b90cbac7-4c4f-4acc-8251-6504ef860f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572500193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2572500193
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1127674333
Short name T530
Test name
Test status
Simulation time 1009962976 ps
CPU time 5.08 seconds
Started Apr 23 02:33:40 PM PDT 24
Finished Apr 23 02:33:46 PM PDT 24
Peak memory 200960 kb
Host smart-694472d0-beb9-4db5-95b5-9850f7672f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127674333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1127674333
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1633608043
Short name T380
Test name
Test status
Simulation time 176488644 ps
CPU time 1.16 seconds
Started Apr 23 02:33:42 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 200860 kb
Host smart-229c62e6-312a-481a-92ae-7e3d09d2cc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633608043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1633608043
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1282684775
Short name T305
Test name
Test status
Simulation time 111572229 ps
CPU time 1.13 seconds
Started Apr 23 02:33:42 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 200952 kb
Host smart-bfdd81e9-a75b-4906-aeb7-fc421079ce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282684775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1282684775
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2317509625
Short name T211
Test name
Test status
Simulation time 9574894055 ps
CPU time 34.96 seconds
Started Apr 23 02:33:43 PM PDT 24
Finished Apr 23 02:34:19 PM PDT 24
Peak memory 209348 kb
Host smart-904b5ba7-d10f-4cc1-ae51-1a895dc43d95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317509625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2317509625
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1214109348
Short name T219
Test name
Test status
Simulation time 128494759 ps
CPU time 1.6 seconds
Started Apr 23 02:33:42 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 200764 kb
Host smart-19c13736-2349-419e-879f-2a7fba2c89b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214109348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1214109348
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.4189043319
Short name T56
Test name
Test status
Simulation time 98245322 ps
CPU time 0.88 seconds
Started Apr 23 02:33:40 PM PDT 24
Finished Apr 23 02:33:42 PM PDT 24
Peak memory 200816 kb
Host smart-32ff5b61-ba59-4511-a5f3-9c94e9f6f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189043319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.4189043319
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3344536002
Short name T398
Test name
Test status
Simulation time 78080080 ps
CPU time 0.79 seconds
Started Apr 23 02:32:19 PM PDT 24
Finished Apr 23 02:32:21 PM PDT 24
Peak memory 200600 kb
Host smart-5d0ca911-c051-4529-96d6-6aa282f440d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344536002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3344536002
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2621584082
Short name T478
Test name
Test status
Simulation time 2360427127 ps
CPU time 8.02 seconds
Started Apr 23 02:32:17 PM PDT 24
Finished Apr 23 02:32:25 PM PDT 24
Peak memory 222716 kb
Host smart-d2d7c743-681e-4ad7-92f7-e3f805fc268c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621584082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2621584082
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.721118420
Short name T263
Test name
Test status
Simulation time 244403072 ps
CPU time 1.03 seconds
Started Apr 23 02:32:20 PM PDT 24
Finished Apr 23 02:32:22 PM PDT 24
Peak memory 218228 kb
Host smart-320fa4c7-0b4b-4488-a1fb-daa06098501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721118420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.721118420
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2410179429
Short name T449
Test name
Test status
Simulation time 168121643 ps
CPU time 0.83 seconds
Started Apr 23 02:32:15 PM PDT 24
Finished Apr 23 02:32:17 PM PDT 24
Peak memory 200616 kb
Host smart-f3c96c0b-16e9-4aa5-8225-40c307528e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410179429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2410179429
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1882766397
Short name T371
Test name
Test status
Simulation time 1020381643 ps
CPU time 5.29 seconds
Started Apr 23 02:32:16 PM PDT 24
Finished Apr 23 02:32:22 PM PDT 24
Peak memory 201068 kb
Host smart-d62247b8-012c-4b3c-86a2-f56e6ca0b964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882766397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1882766397
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2970660041
Short name T84
Test name
Test status
Simulation time 8361379906 ps
CPU time 13.7 seconds
Started Apr 23 02:32:20 PM PDT 24
Finished Apr 23 02:32:35 PM PDT 24
Peak memory 217564 kb
Host smart-8eae2592-4541-46f3-a417-dbde5e0c7825
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970660041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2970660041
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.19806401
Short name T264
Test name
Test status
Simulation time 170698269 ps
CPU time 1.1 seconds
Started Apr 23 02:32:20 PM PDT 24
Finished Apr 23 02:32:21 PM PDT 24
Peak memory 200716 kb
Host smart-16140446-bfb2-4871-b5f9-6310d19b44cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19806401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.19806401
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2445460514
Short name T63
Test name
Test status
Simulation time 257609898 ps
CPU time 1.49 seconds
Started Apr 23 02:32:14 PM PDT 24
Finished Apr 23 02:32:16 PM PDT 24
Peak memory 200972 kb
Host smart-e0983269-3e5e-45ac-896c-86f948ce24f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445460514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2445460514
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2821485950
Short name T378
Test name
Test status
Simulation time 145236290 ps
CPU time 1.79 seconds
Started Apr 23 02:32:17 PM PDT 24
Finished Apr 23 02:32:20 PM PDT 24
Peak memory 200836 kb
Host smart-a36fd816-5891-4e36-aed4-e5b7de629c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821485950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2821485950
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1417501786
Short name T455
Test name
Test status
Simulation time 134737157 ps
CPU time 1.08 seconds
Started Apr 23 02:32:17 PM PDT 24
Finished Apr 23 02:32:18 PM PDT 24
Peak memory 200808 kb
Host smart-b595e7c3-977e-4572-a1cc-288b365f584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417501786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1417501786
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3810590593
Short name T270
Test name
Test status
Simulation time 74695517 ps
CPU time 0.72 seconds
Started Apr 23 02:33:52 PM PDT 24
Finished Apr 23 02:33:53 PM PDT 24
Peak memory 200604 kb
Host smart-7dc9f9d7-9f05-4daf-9131-3dbce1dfd073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810590593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3810590593
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2083803829
Short name T353
Test name
Test status
Simulation time 2361888797 ps
CPU time 8.36 seconds
Started Apr 23 02:33:44 PM PDT 24
Finished Apr 23 02:33:53 PM PDT 24
Peak memory 217952 kb
Host smart-5c7578ff-8fd9-4ce3-b649-d305388ab761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083803829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2083803829
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3017484169
Short name T524
Test name
Test status
Simulation time 245035921 ps
CPU time 1 seconds
Started Apr 23 02:33:49 PM PDT 24
Finished Apr 23 02:33:50 PM PDT 24
Peak memory 218292 kb
Host smart-1c3ecf22-e609-485a-b312-998fbc4c858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017484169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3017484169
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1461936521
Short name T472
Test name
Test status
Simulation time 79826728 ps
CPU time 0.72 seconds
Started Apr 23 02:33:43 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 200632 kb
Host smart-67144c55-acd9-4b39-9d8b-305c1d4214e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461936521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1461936521
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.289295170
Short name T467
Test name
Test status
Simulation time 673407029 ps
CPU time 3.53 seconds
Started Apr 23 02:33:44 PM PDT 24
Finished Apr 23 02:33:48 PM PDT 24
Peak memory 201028 kb
Host smart-b9d669b5-a794-407c-9e2c-fd9a37e03487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289295170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.289295170
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.4103755989
Short name T435
Test name
Test status
Simulation time 168868874 ps
CPU time 1.24 seconds
Started Apr 23 02:33:48 PM PDT 24
Finished Apr 23 02:33:49 PM PDT 24
Peak memory 200840 kb
Host smart-b0af6c18-b1db-4705-8ddc-5f151b96d7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103755989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.4103755989
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2329159028
Short name T343
Test name
Test status
Simulation time 196914683 ps
CPU time 1.34 seconds
Started Apr 23 02:33:43 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 200996 kb
Host smart-714a42d9-9f7c-4421-bc96-7955cce930f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329159028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2329159028
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.700670271
Short name T350
Test name
Test status
Simulation time 1427991664 ps
CPU time 6.12 seconds
Started Apr 23 02:33:49 PM PDT 24
Finished Apr 23 02:33:55 PM PDT 24
Peak memory 201028 kb
Host smart-cd81ff28-3758-4037-8def-9af84291a3c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700670271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.700670271
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.887431511
Short name T420
Test name
Test status
Simulation time 154663416 ps
CPU time 1.85 seconds
Started Apr 23 02:33:45 PM PDT 24
Finished Apr 23 02:33:48 PM PDT 24
Peak memory 200776 kb
Host smart-87844f95-a809-414d-83ca-f768a663c7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887431511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.887431511
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1084746370
Short name T182
Test name
Test status
Simulation time 84905373 ps
CPU time 0.81 seconds
Started Apr 23 02:33:42 PM PDT 24
Finished Apr 23 02:33:44 PM PDT 24
Peak memory 200868 kb
Host smart-2574f042-7462-40ec-a146-c640c10ad611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084746370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1084746370
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.4091989177
Short name T10
Test name
Test status
Simulation time 65489102 ps
CPU time 0.79 seconds
Started Apr 23 02:33:54 PM PDT 24
Finished Apr 23 02:33:55 PM PDT 24
Peak memory 200668 kb
Host smart-a0b574b4-4c0f-421b-9622-62867690fda8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091989177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.4091989177
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1692219283
Short name T541
Test name
Test status
Simulation time 2384598796 ps
CPU time 8.34 seconds
Started Apr 23 02:33:54 PM PDT 24
Finished Apr 23 02:34:03 PM PDT 24
Peak memory 222660 kb
Host smart-10c51892-7e23-4544-8eee-db90e14fc087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692219283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1692219283
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3221043429
Short name T62
Test name
Test status
Simulation time 244577802 ps
CPU time 1.15 seconds
Started Apr 23 02:33:53 PM PDT 24
Finished Apr 23 02:33:55 PM PDT 24
Peak memory 218264 kb
Host smart-88eebd1e-0c5a-4a91-8a8d-a92f62be84f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221043429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3221043429
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1147796355
Short name T17
Test name
Test status
Simulation time 169954614 ps
CPU time 0.85 seconds
Started Apr 23 02:33:50 PM PDT 24
Finished Apr 23 02:33:51 PM PDT 24
Peak memory 200684 kb
Host smart-00dd8350-7b1c-4cf7-aa8c-eac249c873b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147796355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1147796355
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2196360278
Short name T324
Test name
Test status
Simulation time 686824603 ps
CPU time 3.46 seconds
Started Apr 23 02:33:52 PM PDT 24
Finished Apr 23 02:33:56 PM PDT 24
Peak memory 200996 kb
Host smart-5812e43b-bf8f-4f56-bde8-93561093cb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196360278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2196360278
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.975227676
Short name T275
Test name
Test status
Simulation time 188285170 ps
CPU time 1.12 seconds
Started Apr 23 02:33:54 PM PDT 24
Finished Apr 23 02:33:55 PM PDT 24
Peak memory 200784 kb
Host smart-5e361db3-6e0e-49df-9bd3-25ea538b9839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975227676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.975227676
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2388284205
Short name T130
Test name
Test status
Simulation time 223946025 ps
CPU time 1.51 seconds
Started Apr 23 02:33:50 PM PDT 24
Finished Apr 23 02:33:52 PM PDT 24
Peak memory 201016 kb
Host smart-fbd98009-ebc3-4fef-9fe8-19c0f971f91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388284205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2388284205
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.19310687
Short name T107
Test name
Test status
Simulation time 3362720595 ps
CPU time 12.99 seconds
Started Apr 23 02:33:53 PM PDT 24
Finished Apr 23 02:34:06 PM PDT 24
Peak memory 209292 kb
Host smart-3f09b98b-293c-413a-9d4e-e10372cc760d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19310687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.19310687
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2220671924
Short name T336
Test name
Test status
Simulation time 128660302 ps
CPU time 1.62 seconds
Started Apr 23 02:33:53 PM PDT 24
Finished Apr 23 02:33:56 PM PDT 24
Peak memory 200852 kb
Host smart-0b4c9b8f-5068-4732-97de-dadc09d2609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220671924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2220671924
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1098092492
Short name T443
Test name
Test status
Simulation time 175038174 ps
CPU time 1.33 seconds
Started Apr 23 02:33:55 PM PDT 24
Finished Apr 23 02:33:57 PM PDT 24
Peak memory 200984 kb
Host smart-8ae5fe02-2372-4a04-b578-cf44c6c52bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098092492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1098092492
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3413138629
Short name T360
Test name
Test status
Simulation time 71313746 ps
CPU time 0.74 seconds
Started Apr 23 02:33:54 PM PDT 24
Finished Apr 23 02:33:56 PM PDT 24
Peak memory 200624 kb
Host smart-375d3e73-cc63-487c-9f9f-5e588486c85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413138629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3413138629
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3376125144
Short name T344
Test name
Test status
Simulation time 1883263199 ps
CPU time 7.04 seconds
Started Apr 23 02:33:53 PM PDT 24
Finished Apr 23 02:34:01 PM PDT 24
Peak memory 218036 kb
Host smart-ad8a022a-e07f-47ba-bf76-87b7b31b6ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376125144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3376125144
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1122093405
Short name T503
Test name
Test status
Simulation time 244166103 ps
CPU time 1.06 seconds
Started Apr 23 02:33:54 PM PDT 24
Finished Apr 23 02:33:56 PM PDT 24
Peak memory 218104 kb
Host smart-5cc89abd-e6d4-443d-ba0b-14f17cbcd7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122093405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1122093405
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1803327516
Short name T18
Test name
Test status
Simulation time 218412729 ps
CPU time 0.87 seconds
Started Apr 23 02:33:53 PM PDT 24
Finished Apr 23 02:33:54 PM PDT 24
Peak memory 200648 kb
Host smart-02209db3-13c9-4bde-807d-3799946c463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803327516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1803327516
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1237155504
Short name T95
Test name
Test status
Simulation time 1428551876 ps
CPU time 5.28 seconds
Started Apr 23 02:33:54 PM PDT 24
Finished Apr 23 02:34:00 PM PDT 24
Peak memory 201008 kb
Host smart-4b44e290-4f7b-49bc-957a-592b297681a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237155504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1237155504
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2440551586
Short name T391
Test name
Test status
Simulation time 174372855 ps
CPU time 1.14 seconds
Started Apr 23 02:33:53 PM PDT 24
Finished Apr 23 02:33:55 PM PDT 24
Peak memory 200852 kb
Host smart-dd4498b6-7497-4a01-85a1-9b115bd648d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440551586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2440551586
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1885989505
Short name T413
Test name
Test status
Simulation time 201495986 ps
CPU time 1.34 seconds
Started Apr 23 02:33:54 PM PDT 24
Finished Apr 23 02:33:56 PM PDT 24
Peak memory 200992 kb
Host smart-9b1240fd-77ad-4c37-981e-9dd600e2f39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885989505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1885989505
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3781420083
Short name T489
Test name
Test status
Simulation time 6394120587 ps
CPU time 27.84 seconds
Started Apr 23 02:33:53 PM PDT 24
Finished Apr 23 02:34:22 PM PDT 24
Peak memory 201044 kb
Host smart-c0e1809a-dd00-4ade-811b-7c18d0a5f0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781420083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3781420083
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3724976023
Short name T223
Test name
Test status
Simulation time 386793131 ps
CPU time 2.4 seconds
Started Apr 23 02:33:54 PM PDT 24
Finished Apr 23 02:33:57 PM PDT 24
Peak memory 200800 kb
Host smart-bdd0c002-67b3-455a-8f6b-409376c4a968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724976023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3724976023
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3145562947
Short name T385
Test name
Test status
Simulation time 62489631 ps
CPU time 0.82 seconds
Started Apr 23 02:33:56 PM PDT 24
Finished Apr 23 02:33:58 PM PDT 24
Peak memory 200804 kb
Host smart-805ac4d0-31fc-4958-84d2-7b92804875bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145562947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3145562947
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3543549010
Short name T165
Test name
Test status
Simulation time 70995619 ps
CPU time 0.85 seconds
Started Apr 23 02:34:01 PM PDT 24
Finished Apr 23 02:34:02 PM PDT 24
Peak memory 200584 kb
Host smart-ef8ff01a-2373-438f-8f3c-5376c9450561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543549010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3543549010
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3866902376
Short name T46
Test name
Test status
Simulation time 1219699066 ps
CPU time 5.41 seconds
Started Apr 23 02:33:58 PM PDT 24
Finished Apr 23 02:34:04 PM PDT 24
Peak memory 222688 kb
Host smart-d4b7dcc0-bf5a-404e-ab0b-405abc5eb6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866902376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3866902376
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2645058386
Short name T272
Test name
Test status
Simulation time 243791135 ps
CPU time 1.04 seconds
Started Apr 23 02:33:59 PM PDT 24
Finished Apr 23 02:34:01 PM PDT 24
Peak memory 218124 kb
Host smart-736d029e-dae5-476e-8fbd-fdbb3eae50d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645058386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2645058386
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2474987197
Short name T466
Test name
Test status
Simulation time 103189596 ps
CPU time 0.78 seconds
Started Apr 23 02:33:59 PM PDT 24
Finished Apr 23 02:34:01 PM PDT 24
Peak memory 200648 kb
Host smart-89ee79b1-7f61-45ff-be7d-b2d5a77bd779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474987197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2474987197
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2022309234
Short name T175
Test name
Test status
Simulation time 714749289 ps
CPU time 3.88 seconds
Started Apr 23 02:34:01 PM PDT 24
Finished Apr 23 02:34:06 PM PDT 24
Peak memory 200960 kb
Host smart-e2d7f156-927c-4bc7-8723-bdf1a592e1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022309234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2022309234
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.502237735
Short name T504
Test name
Test status
Simulation time 99153580 ps
CPU time 1.01 seconds
Started Apr 23 02:33:58 PM PDT 24
Finished Apr 23 02:33:59 PM PDT 24
Peak memory 200844 kb
Host smart-2bd7c82b-d063-499d-b3dd-b181694408cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502237735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.502237735
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3344263815
Short name T470
Test name
Test status
Simulation time 199617525 ps
CPU time 1.35 seconds
Started Apr 23 02:33:59 PM PDT 24
Finished Apr 23 02:34:01 PM PDT 24
Peak memory 201000 kb
Host smart-56aa83a1-d07a-4aed-ba04-5f7c2915e2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344263815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3344263815
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2201008562
Short name T254
Test name
Test status
Simulation time 12415841977 ps
CPU time 44.41 seconds
Started Apr 23 02:34:02 PM PDT 24
Finished Apr 23 02:34:47 PM PDT 24
Peak memory 209184 kb
Host smart-4abeb3eb-ed5b-43be-8a18-f5b4d077f551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201008562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2201008562
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3363361474
Short name T153
Test name
Test status
Simulation time 146071794 ps
CPU time 1.83 seconds
Started Apr 23 02:33:57 PM PDT 24
Finished Apr 23 02:33:59 PM PDT 24
Peak memory 200772 kb
Host smart-f9f71984-cc62-482e-87e5-85252a0516de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363361474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3363361474
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2111845215
Short name T271
Test name
Test status
Simulation time 171412711 ps
CPU time 1.12 seconds
Started Apr 23 02:33:58 PM PDT 24
Finished Apr 23 02:34:00 PM PDT 24
Peak memory 200760 kb
Host smart-1950175f-f140-44b2-9196-ac7eece1cd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111845215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2111845215
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.315653413
Short name T511
Test name
Test status
Simulation time 128610108 ps
CPU time 0.86 seconds
Started Apr 23 02:34:00 PM PDT 24
Finished Apr 23 02:34:01 PM PDT 24
Peak memory 200620 kb
Host smart-d72425f6-a8d7-40d9-964c-2dfa3ab1d190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315653413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.315653413
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.732193992
Short name T31
Test name
Test status
Simulation time 1217911632 ps
CPU time 5.59 seconds
Started Apr 23 02:33:57 PM PDT 24
Finished Apr 23 02:34:03 PM PDT 24
Peak memory 218628 kb
Host smart-e5eeb626-9add-4f89-a2c0-fd28c72e5d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732193992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.732193992
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3377632682
Short name T382
Test name
Test status
Simulation time 246363483 ps
CPU time 1.01 seconds
Started Apr 23 02:33:58 PM PDT 24
Finished Apr 23 02:33:59 PM PDT 24
Peak memory 218128 kb
Host smart-96d83409-e45a-41b4-a029-3efb5cc54b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377632682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3377632682
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3768935268
Short name T505
Test name
Test status
Simulation time 191907808 ps
CPU time 0.93 seconds
Started Apr 23 02:33:57 PM PDT 24
Finished Apr 23 02:33:58 PM PDT 24
Peak memory 200620 kb
Host smart-82a1fa40-3753-43ce-9432-6bc086852ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768935268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3768935268
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3182987670
Short name T128
Test name
Test status
Simulation time 1921423537 ps
CPU time 6.87 seconds
Started Apr 23 02:33:57 PM PDT 24
Finished Apr 23 02:34:04 PM PDT 24
Peak memory 201064 kb
Host smart-e95b785a-55cf-4b24-8d4a-ec6e39b5a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182987670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3182987670
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.681821759
Short name T287
Test name
Test status
Simulation time 99164653 ps
CPU time 1 seconds
Started Apr 23 02:34:00 PM PDT 24
Finished Apr 23 02:34:01 PM PDT 24
Peak memory 200832 kb
Host smart-95fbcf25-27d6-4345-8421-9ec3aaf27239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681821759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.681821759
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.4119158974
Short name T401
Test name
Test status
Simulation time 258410724 ps
CPU time 1.5 seconds
Started Apr 23 02:33:56 PM PDT 24
Finished Apr 23 02:33:58 PM PDT 24
Peak memory 201040 kb
Host smart-12a7dfef-0720-45b1-9a7f-10e23c27e2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119158974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.4119158974
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2216375123
Short name T441
Test name
Test status
Simulation time 7095256627 ps
CPU time 31.02 seconds
Started Apr 23 02:34:02 PM PDT 24
Finished Apr 23 02:34:33 PM PDT 24
Peak memory 201064 kb
Host smart-2112d64c-179a-42bc-badc-da9972bb06ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216375123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2216375123
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3517791253
Short name T234
Test name
Test status
Simulation time 384618384 ps
CPU time 2.52 seconds
Started Apr 23 02:33:56 PM PDT 24
Finished Apr 23 02:33:59 PM PDT 24
Peak memory 200824 kb
Host smart-1ed6c501-33ec-4b4e-ba0a-0d6f43f8bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517791253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3517791253
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.4233665660
Short name T269
Test name
Test status
Simulation time 97990191 ps
CPU time 0.92 seconds
Started Apr 23 02:33:58 PM PDT 24
Finished Apr 23 02:34:00 PM PDT 24
Peak memory 200756 kb
Host smart-dfd3b8f2-2cbf-4c5b-9d84-c4f7558fab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233665660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4233665660
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1677614059
Short name T227
Test name
Test status
Simulation time 65246041 ps
CPU time 0.75 seconds
Started Apr 23 02:34:03 PM PDT 24
Finished Apr 23 02:34:04 PM PDT 24
Peak memory 200672 kb
Host smart-5219f0a5-7bcd-47ee-ad0a-ba125beb8530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677614059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1677614059
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2537691050
Short name T68
Test name
Test status
Simulation time 1231451280 ps
CPU time 5.5 seconds
Started Apr 23 02:34:01 PM PDT 24
Finished Apr 23 02:34:07 PM PDT 24
Peak memory 218056 kb
Host smart-2287c22b-100b-4c3c-9f93-a52e68c7a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537691050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2537691050
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1190049641
Short name T321
Test name
Test status
Simulation time 243231619 ps
CPU time 1.16 seconds
Started Apr 23 02:34:03 PM PDT 24
Finished Apr 23 02:34:04 PM PDT 24
Peak memory 218344 kb
Host smart-c1358d5e-3d4d-485c-accc-7bea7f73ec77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190049641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1190049641
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.422595065
Short name T20
Test name
Test status
Simulation time 161689221 ps
CPU time 0.82 seconds
Started Apr 23 02:33:59 PM PDT 24
Finished Apr 23 02:34:00 PM PDT 24
Peak memory 200592 kb
Host smart-6f325dac-470a-4582-9c3e-b0cc5327145b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422595065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.422595065
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.71342670
Short name T101
Test name
Test status
Simulation time 686198416 ps
CPU time 3.67 seconds
Started Apr 23 02:34:02 PM PDT 24
Finished Apr 23 02:34:06 PM PDT 24
Peak memory 200980 kb
Host smart-aac807c4-ca7e-47e8-a161-7d5c3e2a9ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71342670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.71342670
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2197494624
Short name T158
Test name
Test status
Simulation time 152333368 ps
CPU time 1.14 seconds
Started Apr 23 02:34:04 PM PDT 24
Finished Apr 23 02:34:05 PM PDT 24
Peak memory 200748 kb
Host smart-68c46307-5246-4834-9481-85d525f0f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197494624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2197494624
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3346193520
Short name T12
Test name
Test status
Simulation time 202415812 ps
CPU time 1.3 seconds
Started Apr 23 02:33:56 PM PDT 24
Finished Apr 23 02:33:58 PM PDT 24
Peak memory 201040 kb
Host smart-906b4e9e-b385-4fd1-8088-9cbeaea9c296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346193520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3346193520
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.264618792
Short name T239
Test name
Test status
Simulation time 5637001649 ps
CPU time 25.28 seconds
Started Apr 23 02:34:00 PM PDT 24
Finished Apr 23 02:34:26 PM PDT 24
Peak memory 209284 kb
Host smart-4b9c530d-0066-4e13-8116-ea8a4824facb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264618792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.264618792
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1441679091
Short name T323
Test name
Test status
Simulation time 302448513 ps
CPU time 1.6 seconds
Started Apr 23 02:34:04 PM PDT 24
Finished Apr 23 02:34:06 PM PDT 24
Peak memory 200988 kb
Host smart-2e3a5714-ffe8-4cbb-bee3-9f9bb692d308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441679091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1441679091
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2360589630
Short name T411
Test name
Test status
Simulation time 93123295 ps
CPU time 0.79 seconds
Started Apr 23 02:34:06 PM PDT 24
Finished Apr 23 02:34:07 PM PDT 24
Peak memory 200624 kb
Host smart-4cf09072-2ca0-40f1-859b-3e2c34066962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360589630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2360589630
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.409706987
Short name T43
Test name
Test status
Simulation time 1887463797 ps
CPU time 7.48 seconds
Started Apr 23 02:34:10 PM PDT 24
Finished Apr 23 02:34:18 PM PDT 24
Peak memory 218632 kb
Host smart-fda0a115-1620-4a57-9c5a-6b6044431cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409706987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.409706987
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1396027306
Short name T258
Test name
Test status
Simulation time 245026702 ps
CPU time 1.08 seconds
Started Apr 23 02:34:04 PM PDT 24
Finished Apr 23 02:34:05 PM PDT 24
Peak memory 218192 kb
Host smart-18179cb5-8310-4fed-a794-2caa1d6b5725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396027306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1396027306
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.943857302
Short name T187
Test name
Test status
Simulation time 137690338 ps
CPU time 0.77 seconds
Started Apr 23 02:34:04 PM PDT 24
Finished Apr 23 02:34:05 PM PDT 24
Peak memory 200660 kb
Host smart-8aca2b92-1e79-46f7-afe5-937ea8c88df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943857302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.943857302
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2307331548
Short name T4
Test name
Test status
Simulation time 1325833416 ps
CPU time 4.98 seconds
Started Apr 23 02:34:03 PM PDT 24
Finished Apr 23 02:34:08 PM PDT 24
Peak memory 201052 kb
Host smart-1cda8c9d-e8bf-4aff-9073-f698a9e4ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307331548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2307331548
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2904012657
Short name T23
Test name
Test status
Simulation time 142902384 ps
CPU time 1.11 seconds
Started Apr 23 02:34:04 PM PDT 24
Finished Apr 23 02:34:06 PM PDT 24
Peak memory 200836 kb
Host smart-afe5face-b3dc-4195-a248-304beccd2497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904012657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2904012657
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2697928943
Short name T278
Test name
Test status
Simulation time 123744946 ps
CPU time 1.15 seconds
Started Apr 23 02:34:07 PM PDT 24
Finished Apr 23 02:34:08 PM PDT 24
Peak memory 200992 kb
Host smart-a4b84d01-963d-4e2c-aaf6-c41e3b518e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697928943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2697928943
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2124872398
Short name T494
Test name
Test status
Simulation time 8578425916 ps
CPU time 30.36 seconds
Started Apr 23 02:34:03 PM PDT 24
Finished Apr 23 02:34:34 PM PDT 24
Peak memory 209304 kb
Host smart-8a6d2efa-2477-4b88-8470-1532068c05d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124872398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2124872398
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3511670457
Short name T389
Test name
Test status
Simulation time 144366666 ps
CPU time 1.75 seconds
Started Apr 23 02:34:06 PM PDT 24
Finished Apr 23 02:34:08 PM PDT 24
Peak memory 200788 kb
Host smart-ddbfa20b-4ec2-42a0-be3b-bfb9c3f1a4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511670457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3511670457
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2422667292
Short name T276
Test name
Test status
Simulation time 198865431 ps
CPU time 1.22 seconds
Started Apr 23 02:34:03 PM PDT 24
Finished Apr 23 02:34:05 PM PDT 24
Peak memory 200772 kb
Host smart-d282cdfc-cf39-4727-aa2f-0add8bdc31d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422667292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2422667292
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1026138633
Short name T291
Test name
Test status
Simulation time 79740296 ps
CPU time 0.8 seconds
Started Apr 23 02:34:06 PM PDT 24
Finished Apr 23 02:34:07 PM PDT 24
Peak memory 200628 kb
Host smart-e0449f1a-8ba5-406e-a2ec-1cb83d0b00d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026138633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1026138633
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3086713410
Short name T37
Test name
Test status
Simulation time 1886842998 ps
CPU time 6.66 seconds
Started Apr 23 02:34:09 PM PDT 24
Finished Apr 23 02:34:16 PM PDT 24
Peak memory 218008 kb
Host smart-b8d7724f-1ee6-444e-b4c9-5d6d31a7b263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086713410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3086713410
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3398628610
Short name T205
Test name
Test status
Simulation time 245873232 ps
CPU time 1.09 seconds
Started Apr 23 02:34:09 PM PDT 24
Finished Apr 23 02:34:11 PM PDT 24
Peak memory 218136 kb
Host smart-9e5197a7-91a3-45b6-96e6-3f976e25d96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398628610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3398628610
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2732650787
Short name T300
Test name
Test status
Simulation time 220206768 ps
CPU time 0.9 seconds
Started Apr 23 02:34:03 PM PDT 24
Finished Apr 23 02:34:04 PM PDT 24
Peak memory 200620 kb
Host smart-abb47bc8-5bd7-4b2e-8fc2-7b098d72029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732650787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2732650787
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2087991201
Short name T34
Test name
Test status
Simulation time 1280462210 ps
CPU time 4.93 seconds
Started Apr 23 02:34:07 PM PDT 24
Finished Apr 23 02:34:12 PM PDT 24
Peak memory 200980 kb
Host smart-c6441780-8d4a-44b6-b037-150de017cc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087991201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2087991201
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3781686272
Short name T422
Test name
Test status
Simulation time 109407956 ps
CPU time 0.99 seconds
Started Apr 23 02:34:07 PM PDT 24
Finished Apr 23 02:34:08 PM PDT 24
Peak memory 200824 kb
Host smart-bcd798e6-b17e-4661-8c15-50c79b5de044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781686272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3781686272
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3499307378
Short name T327
Test name
Test status
Simulation time 200858291 ps
CPU time 1.34 seconds
Started Apr 23 02:34:04 PM PDT 24
Finished Apr 23 02:34:06 PM PDT 24
Peak memory 201024 kb
Host smart-3b70d229-31ec-4847-94cc-5e7d90390f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499307378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3499307378
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3548775264
Short name T433
Test name
Test status
Simulation time 6108125365 ps
CPU time 22.51 seconds
Started Apr 23 02:34:06 PM PDT 24
Finished Apr 23 02:34:29 PM PDT 24
Peak memory 209240 kb
Host smart-f9dd641b-377f-4eba-af5d-3d902c0461ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548775264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3548775264
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1079629566
Short name T523
Test name
Test status
Simulation time 130072246 ps
CPU time 1.51 seconds
Started Apr 23 02:34:06 PM PDT 24
Finished Apr 23 02:34:08 PM PDT 24
Peak memory 200828 kb
Host smart-c858c824-6cb2-4b17-ba21-a8ea31e3a231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079629566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1079629566
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1116677000
Short name T409
Test name
Test status
Simulation time 227706782 ps
CPU time 1.38 seconds
Started Apr 23 02:34:08 PM PDT 24
Finished Apr 23 02:34:11 PM PDT 24
Peak memory 200792 kb
Host smart-e86d15f1-9c1c-443b-a729-29024c9d69d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116677000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1116677000
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2692191604
Short name T320
Test name
Test status
Simulation time 60985509 ps
CPU time 0.78 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:14 PM PDT 24
Peak memory 200664 kb
Host smart-653df94f-1997-4e43-8e14-e633d84bee89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692191604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2692191604
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1745782583
Short name T24
Test name
Test status
Simulation time 1231040865 ps
CPU time 5.33 seconds
Started Apr 23 02:34:10 PM PDT 24
Finished Apr 23 02:34:16 PM PDT 24
Peak memory 222164 kb
Host smart-e5296ef1-21c9-4733-ac66-dffad88e9b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745782583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1745782583
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.214956225
Short name T176
Test name
Test status
Simulation time 244067182 ps
CPU time 1.09 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:15 PM PDT 24
Peak memory 218164 kb
Host smart-c72e6381-1d6e-4eff-bcd7-0b349ba5a51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214956225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.214956225
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.231087948
Short name T177
Test name
Test status
Simulation time 93945604 ps
CPU time 0.72 seconds
Started Apr 23 02:34:08 PM PDT 24
Finished Apr 23 02:34:10 PM PDT 24
Peak memory 200612 kb
Host smart-dff16b7d-227b-408c-bb99-7cda6d759408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231087948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.231087948
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1676892572
Short name T400
Test name
Test status
Simulation time 1162738571 ps
CPU time 4.73 seconds
Started Apr 23 02:34:05 PM PDT 24
Finished Apr 23 02:34:10 PM PDT 24
Peak memory 200960 kb
Host smart-b8ec5b90-3f7e-4c6a-a3f0-186746ea8208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676892572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1676892572
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.569273951
Short name T376
Test name
Test status
Simulation time 157023362 ps
CPU time 1.09 seconds
Started Apr 23 02:34:07 PM PDT 24
Finished Apr 23 02:34:09 PM PDT 24
Peak memory 200800 kb
Host smart-f449eef2-b854-4273-b10a-ac0d82d2c75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569273951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.569273951
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2298576660
Short name T535
Test name
Test status
Simulation time 247706932 ps
CPU time 1.47 seconds
Started Apr 23 02:34:08 PM PDT 24
Finished Apr 23 02:34:10 PM PDT 24
Peak memory 201012 kb
Host smart-83e0b514-7819-480b-8452-a3a1e96d6ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298576660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2298576660
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2774478583
Short name T337
Test name
Test status
Simulation time 4726366468 ps
CPU time 21.31 seconds
Started Apr 23 02:34:11 PM PDT 24
Finished Apr 23 02:34:33 PM PDT 24
Peak memory 217044 kb
Host smart-2708a7a5-143a-4c61-b357-c86e4793d612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774478583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2774478583
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.27058420
Short name T240
Test name
Test status
Simulation time 138073468 ps
CPU time 1.67 seconds
Started Apr 23 02:34:12 PM PDT 24
Finished Apr 23 02:34:14 PM PDT 24
Peak memory 200788 kb
Host smart-ac429c51-1e43-40fb-bab4-5da16a9f05a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27058420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.27058420
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2639848062
Short name T452
Test name
Test status
Simulation time 157399212 ps
CPU time 1.18 seconds
Started Apr 23 02:34:08 PM PDT 24
Finished Apr 23 02:34:09 PM PDT 24
Peak memory 200828 kb
Host smart-60828f3e-23c9-484e-bd5a-84d1a94e68f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639848062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2639848062
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3226224178
Short name T243
Test name
Test status
Simulation time 85538821 ps
CPU time 0.8 seconds
Started Apr 23 02:34:11 PM PDT 24
Finished Apr 23 02:34:13 PM PDT 24
Peak memory 200592 kb
Host smart-7534879d-6316-40f7-ac49-ca9f0415112d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226224178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3226224178
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3930295730
Short name T417
Test name
Test status
Simulation time 2160124927 ps
CPU time 7.44 seconds
Started Apr 23 02:34:11 PM PDT 24
Finished Apr 23 02:34:19 PM PDT 24
Peak memory 218152 kb
Host smart-c6f3895f-a4fe-4986-a606-e2bf6d1731da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930295730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3930295730
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.4229779406
Short name T359
Test name
Test status
Simulation time 244153851 ps
CPU time 1.08 seconds
Started Apr 23 02:34:15 PM PDT 24
Finished Apr 23 02:34:17 PM PDT 24
Peak memory 218104 kb
Host smart-c41ebc46-1fee-4ca9-8dfa-42100b80393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229779406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.4229779406
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1704026717
Short name T521
Test name
Test status
Simulation time 151080386 ps
CPU time 0.83 seconds
Started Apr 23 02:34:11 PM PDT 24
Finished Apr 23 02:34:12 PM PDT 24
Peak memory 200636 kb
Host smart-e3c8a678-1dfc-492f-8c93-a615464dcba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704026717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1704026717
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1744996279
Short name T208
Test name
Test status
Simulation time 1591384621 ps
CPU time 6.07 seconds
Started Apr 23 02:34:14 PM PDT 24
Finished Apr 23 02:34:20 PM PDT 24
Peak memory 200956 kb
Host smart-15cd5fff-297c-4b18-8582-f1d2cbe96ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744996279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1744996279
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2137241220
Short name T423
Test name
Test status
Simulation time 172370094 ps
CPU time 1.12 seconds
Started Apr 23 02:34:12 PM PDT 24
Finished Apr 23 02:34:13 PM PDT 24
Peak memory 200868 kb
Host smart-11d72ff0-0e0b-482c-9669-df566e3246c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137241220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2137241220
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2112446975
Short name T9
Test name
Test status
Simulation time 111952490 ps
CPU time 1.17 seconds
Started Apr 23 02:34:14 PM PDT 24
Finished Apr 23 02:34:15 PM PDT 24
Peak memory 200976 kb
Host smart-2237f7b4-c3c6-4fb9-ae92-2dc6ab15eae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112446975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2112446975
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1122719338
Short name T412
Test name
Test status
Simulation time 1881620834 ps
CPU time 7.5 seconds
Started Apr 23 02:34:10 PM PDT 24
Finished Apr 23 02:34:18 PM PDT 24
Peak memory 209188 kb
Host smart-c9017051-adb7-4c24-8c53-ffdd2ab0700b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122719338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1122719338
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2308488225
Short name T72
Test name
Test status
Simulation time 130114122 ps
CPU time 1.59 seconds
Started Apr 23 02:34:15 PM PDT 24
Finished Apr 23 02:34:17 PM PDT 24
Peak memory 200796 kb
Host smart-71bcc0b4-ca54-4a52-a1c8-dcfd3632a70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308488225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2308488225
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3473104473
Short name T384
Test name
Test status
Simulation time 83830905 ps
CPU time 0.88 seconds
Started Apr 23 02:34:18 PM PDT 24
Finished Apr 23 02:34:20 PM PDT 24
Peak memory 200820 kb
Host smart-d6d561bc-42d2-4272-a739-e68b1969278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473104473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3473104473
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1556470512
Short name T146
Test name
Test status
Simulation time 69231364 ps
CPU time 0.75 seconds
Started Apr 23 02:32:23 PM PDT 24
Finished Apr 23 02:32:25 PM PDT 24
Peak memory 200580 kb
Host smart-a726a130-3394-4478-a4ed-808ac8665530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556470512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1556470512
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.293566662
Short name T163
Test name
Test status
Simulation time 244277190 ps
CPU time 1 seconds
Started Apr 23 02:32:22 PM PDT 24
Finished Apr 23 02:32:23 PM PDT 24
Peak memory 218108 kb
Host smart-fda4168f-7a03-4758-81d2-14f1843d9221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293566662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.293566662
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4146946070
Short name T365
Test name
Test status
Simulation time 234542475 ps
CPU time 0.87 seconds
Started Apr 23 02:32:19 PM PDT 24
Finished Apr 23 02:32:20 PM PDT 24
Peak memory 200660 kb
Host smart-db76e149-05d6-4b37-b3d7-8933ff794817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146946070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4146946070
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1870466283
Short name T334
Test name
Test status
Simulation time 847541210 ps
CPU time 4.14 seconds
Started Apr 23 02:32:20 PM PDT 24
Finished Apr 23 02:32:25 PM PDT 24
Peak memory 201028 kb
Host smart-3db72316-2348-4d4b-8242-a7f87843aea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870466283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1870466283
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2723492013
Short name T85
Test name
Test status
Simulation time 8925399632 ps
CPU time 13.84 seconds
Started Apr 23 02:32:22 PM PDT 24
Finished Apr 23 02:32:36 PM PDT 24
Peak memory 217868 kb
Host smart-7c9369cc-cb37-46b8-81da-3d973c6fcbb0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723492013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2723492013
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3264602034
Short name T446
Test name
Test status
Simulation time 96188375 ps
CPU time 0.94 seconds
Started Apr 23 02:32:23 PM PDT 24
Finished Apr 23 02:32:24 PM PDT 24
Peak memory 200788 kb
Host smart-2ee5c85a-356f-4256-b4f4-91a7b86eb952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264602034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3264602034
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.948159333
Short name T537
Test name
Test status
Simulation time 124329705 ps
CPU time 1.15 seconds
Started Apr 23 02:32:19 PM PDT 24
Finished Apr 23 02:32:21 PM PDT 24
Peak memory 200944 kb
Host smart-cdc1f607-ffda-485f-8182-09be6e28e090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948159333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.948159333
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2765189760
Short name T519
Test name
Test status
Simulation time 11628133571 ps
CPU time 34.75 seconds
Started Apr 23 02:32:24 PM PDT 24
Finished Apr 23 02:32:59 PM PDT 24
Peak memory 200932 kb
Host smart-8ce15679-522c-47a1-9533-f13f27043e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765189760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2765189760
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2268102098
Short name T426
Test name
Test status
Simulation time 113325533 ps
CPU time 1.5 seconds
Started Apr 23 02:32:20 PM PDT 24
Finished Apr 23 02:32:22 PM PDT 24
Peak memory 200772 kb
Host smart-efa477ea-197d-429b-b8df-6ec718416207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268102098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2268102098
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1060289966
Short name T500
Test name
Test status
Simulation time 297691388 ps
CPU time 1.47 seconds
Started Apr 23 02:32:18 PM PDT 24
Finished Apr 23 02:32:20 PM PDT 24
Peak memory 201036 kb
Host smart-e5ec2d41-450b-45e5-a950-dff102f9db1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060289966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1060289966
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.414308500
Short name T39
Test name
Test status
Simulation time 67534252 ps
CPU time 0.75 seconds
Started Apr 23 02:34:12 PM PDT 24
Finished Apr 23 02:34:14 PM PDT 24
Peak memory 200588 kb
Host smart-a888d1b3-fdc8-4d73-ab9f-82ba74919725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414308500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.414308500
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3287347767
Short name T437
Test name
Test status
Simulation time 1231541362 ps
CPU time 5.28 seconds
Started Apr 23 02:34:10 PM PDT 24
Finished Apr 23 02:34:16 PM PDT 24
Peak memory 222704 kb
Host smart-6d33fe77-fd02-43a8-a3df-fca2081e8fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287347767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3287347767
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.716961844
Short name T462
Test name
Test status
Simulation time 245324263 ps
CPU time 1.22 seconds
Started Apr 23 02:34:18 PM PDT 24
Finished Apr 23 02:34:20 PM PDT 24
Peak memory 218276 kb
Host smart-4c7041b1-a628-4369-ae13-878b8ac03079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716961844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.716961844
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1196620031
Short name T303
Test name
Test status
Simulation time 165735486 ps
CPU time 0.85 seconds
Started Apr 23 02:34:11 PM PDT 24
Finished Apr 23 02:34:13 PM PDT 24
Peak memory 200604 kb
Host smart-c59666e3-8d22-4400-9837-dfa2220cc72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196620031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1196620031
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2945839730
Short name T465
Test name
Test status
Simulation time 1847583533 ps
CPU time 6.76 seconds
Started Apr 23 02:34:09 PM PDT 24
Finished Apr 23 02:34:17 PM PDT 24
Peak memory 200980 kb
Host smart-b1e69345-4dfd-45d4-b00b-baf524a3fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945839730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2945839730
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.117624098
Short name T212
Test name
Test status
Simulation time 138623547 ps
CPU time 1.05 seconds
Started Apr 23 02:34:10 PM PDT 24
Finished Apr 23 02:34:12 PM PDT 24
Peak memory 200772 kb
Host smart-c5d821fd-653d-4e1f-a487-c3721cc555ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117624098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.117624098
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3621028872
Short name T346
Test name
Test status
Simulation time 256859787 ps
CPU time 1.49 seconds
Started Apr 23 02:34:10 PM PDT 24
Finished Apr 23 02:34:12 PM PDT 24
Peak memory 201008 kb
Host smart-bc2aaa3d-7d4b-4128-b484-c324eb78514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621028872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3621028872
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.210471647
Short name T304
Test name
Test status
Simulation time 2414516666 ps
CPU time 10.85 seconds
Started Apr 23 02:34:11 PM PDT 24
Finished Apr 23 02:34:23 PM PDT 24
Peak memory 201100 kb
Host smart-b3b53295-69d4-43c8-9149-38415139e395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210471647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.210471647
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2330810778
Short name T447
Test name
Test status
Simulation time 282322429 ps
CPU time 2.06 seconds
Started Apr 23 02:34:14 PM PDT 24
Finished Apr 23 02:34:16 PM PDT 24
Peak memory 200800 kb
Host smart-4acb83e1-4a4f-4c98-a408-8fdcb1c1c529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330810778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2330810778
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.276727416
Short name T201
Test name
Test status
Simulation time 68106636 ps
CPU time 0.76 seconds
Started Apr 23 02:34:14 PM PDT 24
Finished Apr 23 02:34:15 PM PDT 24
Peak memory 200732 kb
Host smart-879041bf-13bb-436d-a94b-cb2671ebd1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276727416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.276727416
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2339951151
Short name T237
Test name
Test status
Simulation time 58481276 ps
CPU time 0.74 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:14 PM PDT 24
Peak memory 200636 kb
Host smart-28d38470-0fb7-401a-90fe-e1e939929752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339951151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2339951151
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.4133863813
Short name T539
Test name
Test status
Simulation time 1900461256 ps
CPU time 7.73 seconds
Started Apr 23 02:34:18 PM PDT 24
Finished Apr 23 02:34:27 PM PDT 24
Peak memory 217352 kb
Host smart-8baf085e-7f07-40b6-bebf-99a798785a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133863813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.4133863813
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3202164362
Short name T372
Test name
Test status
Simulation time 244401623 ps
CPU time 1.11 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:15 PM PDT 24
Peak memory 218140 kb
Host smart-80da9c4d-ae1d-432d-a1e4-e0e82ca038d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202164362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3202164362
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1235427585
Short name T348
Test name
Test status
Simulation time 152041586 ps
CPU time 0.8 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:14 PM PDT 24
Peak memory 200612 kb
Host smart-4bb5c72e-4371-49cb-bc6d-25e47666a3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235427585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1235427585
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3938961739
Short name T170
Test name
Test status
Simulation time 1618952744 ps
CPU time 6.56 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:20 PM PDT 24
Peak memory 201044 kb
Host smart-2f260de3-0f3d-43bc-81cf-886592a24670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938961739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3938961739
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3756072956
Short name T241
Test name
Test status
Simulation time 149782865 ps
CPU time 1.09 seconds
Started Apr 23 02:34:14 PM PDT 24
Finished Apr 23 02:34:16 PM PDT 24
Peak memory 200860 kb
Host smart-d59513c8-7016-4989-8129-96cf69b4f3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756072956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3756072956
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2904824784
Short name T261
Test name
Test status
Simulation time 118620001 ps
CPU time 1.22 seconds
Started Apr 23 02:34:14 PM PDT 24
Finished Apr 23 02:34:16 PM PDT 24
Peak memory 201016 kb
Host smart-d87f5459-0d19-4ec3-84dd-d0c4f9dec1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904824784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2904824784
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3822827557
Short name T374
Test name
Test status
Simulation time 3960439412 ps
CPU time 13.27 seconds
Started Apr 23 02:34:18 PM PDT 24
Finished Apr 23 02:34:32 PM PDT 24
Peak memory 201044 kb
Host smart-69fbca8b-1c38-4ab2-8073-55cd5ab59e7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822827557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3822827557
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1670881317
Short name T386
Test name
Test status
Simulation time 489281921 ps
CPU time 2.69 seconds
Started Apr 23 02:34:15 PM PDT 24
Finished Apr 23 02:34:19 PM PDT 24
Peak memory 200776 kb
Host smart-d54cffb4-a056-4483-81ec-59d25ddd926d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670881317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1670881317
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.4009685059
Short name T51
Test name
Test status
Simulation time 249821560 ps
CPU time 1.42 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:15 PM PDT 24
Peak memory 200852 kb
Host smart-51e22f56-4d21-4667-8835-b8afe8ef0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009685059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.4009685059
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3717115684
Short name T145
Test name
Test status
Simulation time 76233258 ps
CPU time 0.8 seconds
Started Apr 23 02:34:21 PM PDT 24
Finished Apr 23 02:34:22 PM PDT 24
Peak memory 200604 kb
Host smart-b9f32c71-46b5-405a-994a-0b77ccd66582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717115684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3717115684
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3080802142
Short name T513
Test name
Test status
Simulation time 1886471151 ps
CPU time 7.1 seconds
Started Apr 23 02:34:15 PM PDT 24
Finished Apr 23 02:34:22 PM PDT 24
Peak memory 218596 kb
Host smart-2394a3d2-ef01-4d92-bc77-e2f67688db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080802142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3080802142
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.4259402136
Short name T65
Test name
Test status
Simulation time 244275942 ps
CPU time 1.02 seconds
Started Apr 23 02:34:17 PM PDT 24
Finished Apr 23 02:34:18 PM PDT 24
Peak memory 218148 kb
Host smart-88b8edd2-fc12-4f9a-af9e-59f93e55ba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259402136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.4259402136
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1291847429
Short name T429
Test name
Test status
Simulation time 191327324 ps
CPU time 0.98 seconds
Started Apr 23 02:34:15 PM PDT 24
Finished Apr 23 02:34:16 PM PDT 24
Peak memory 200668 kb
Host smart-d9ad06e2-c4bb-40e3-bbfc-295c8fbdddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291847429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1291847429
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.117824616
Short name T393
Test name
Test status
Simulation time 1146532058 ps
CPU time 5.33 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:19 PM PDT 24
Peak memory 200968 kb
Host smart-24c499e8-203d-4cbc-9fe4-82f0f74d7217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117824616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.117824616
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.841793272
Short name T251
Test name
Test status
Simulation time 153747527 ps
CPU time 1.07 seconds
Started Apr 23 02:34:15 PM PDT 24
Finished Apr 23 02:34:16 PM PDT 24
Peak memory 200808 kb
Host smart-80ac642b-96c4-4795-aea5-89cdd4b7167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841793272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.841793272
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3283033337
Short name T152
Test name
Test status
Simulation time 201403243 ps
CPU time 1.36 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:15 PM PDT 24
Peak memory 201072 kb
Host smart-8a0dd2a5-bcd0-4712-87cb-aae2522c250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283033337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3283033337
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1671488002
Short name T49
Test name
Test status
Simulation time 2504173659 ps
CPU time 8.16 seconds
Started Apr 23 02:34:16 PM PDT 24
Finished Apr 23 02:34:25 PM PDT 24
Peak memory 209240 kb
Host smart-5cfe66d0-e301-4017-ae9e-543e3852d594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671488002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1671488002
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3103214611
Short name T457
Test name
Test status
Simulation time 118456777 ps
CPU time 1.46 seconds
Started Apr 23 02:34:13 PM PDT 24
Finished Apr 23 02:34:15 PM PDT 24
Peak memory 200776 kb
Host smart-1fd3092b-c3de-44b3-b4a2-5cd056f0d277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103214611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3103214611
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3329652188
Short name T340
Test name
Test status
Simulation time 77733447 ps
CPU time 0.85 seconds
Started Apr 23 02:34:14 PM PDT 24
Finished Apr 23 02:34:15 PM PDT 24
Peak memory 200812 kb
Host smart-df79e8e3-e979-437e-b471-ec3581a25246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329652188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3329652188
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.944102012
Short name T22
Test name
Test status
Simulation time 74318042 ps
CPU time 0.86 seconds
Started Apr 23 02:34:17 PM PDT 24
Finished Apr 23 02:34:19 PM PDT 24
Peak memory 200652 kb
Host smart-7fbbd4d0-c373-40a7-b19d-0c418c8edba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944102012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.944102012
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2737998383
Short name T363
Test name
Test status
Simulation time 1227585123 ps
CPU time 5.14 seconds
Started Apr 23 02:34:16 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 218056 kb
Host smart-bb3ed47f-215f-48d1-9306-09ad8b341dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737998383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2737998383
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3973903474
Short name T190
Test name
Test status
Simulation time 243414157 ps
CPU time 1.13 seconds
Started Apr 23 02:34:17 PM PDT 24
Finished Apr 23 02:34:19 PM PDT 24
Peak memory 218120 kb
Host smart-dda1852b-6d2b-43fa-9688-a480c7963172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973903474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3973903474
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3387519217
Short name T262
Test name
Test status
Simulation time 121909338 ps
CPU time 0.82 seconds
Started Apr 23 02:34:19 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 200628 kb
Host smart-f7559966-6614-4170-a8a1-340d6358b7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387519217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3387519217
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2874351355
Short name T432
Test name
Test status
Simulation time 804289327 ps
CPU time 3.9 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:26 PM PDT 24
Peak memory 201024 kb
Host smart-4a3c3446-3eb9-4438-b730-1ad687bf294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874351355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2874351355
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3969858979
Short name T338
Test name
Test status
Simulation time 149737030 ps
CPU time 1.07 seconds
Started Apr 23 02:34:17 PM PDT 24
Finished Apr 23 02:34:19 PM PDT 24
Peak memory 200748 kb
Host smart-acfd9a93-c016-464d-9745-6f6577b67fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969858979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3969858979
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3200256829
Short name T403
Test name
Test status
Simulation time 197908438 ps
CPU time 1.33 seconds
Started Apr 23 02:34:18 PM PDT 24
Finished Apr 23 02:34:20 PM PDT 24
Peak memory 201000 kb
Host smart-27fd106f-5e5a-43ce-ad06-4dddd5d4a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200256829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3200256829
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2969131184
Short name T318
Test name
Test status
Simulation time 8727398776 ps
CPU time 31.75 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 209256 kb
Host smart-a6008141-bc9d-43f0-8750-cc8c2b803280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969131184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2969131184
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.239933139
Short name T484
Test name
Test status
Simulation time 112402166 ps
CPU time 1.5 seconds
Started Apr 23 02:34:19 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 200796 kb
Host smart-be0ce55d-fbdb-4f13-8b01-0cda02b653e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239933139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.239933139
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1467300240
Short name T256
Test name
Test status
Simulation time 66622433 ps
CPU time 0.81 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:23 PM PDT 24
Peak memory 200796 kb
Host smart-63f9a3f5-5701-425b-8131-fb798826ce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467300240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1467300240
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1317839964
Short name T490
Test name
Test status
Simulation time 60321858 ps
CPU time 0.76 seconds
Started Apr 23 02:34:19 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 200624 kb
Host smart-9d193ab1-e6c8-4e41-b838-011dcce21b04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317839964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1317839964
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3463260785
Short name T390
Test name
Test status
Simulation time 1893591906 ps
CPU time 7.6 seconds
Started Apr 23 02:34:19 PM PDT 24
Finished Apr 23 02:34:27 PM PDT 24
Peak memory 218700 kb
Host smart-49da9fa0-f23a-4d55-ab1a-3b4589b9c5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463260785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3463260785
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2812178085
Short name T367
Test name
Test status
Simulation time 244372300 ps
CPU time 1.04 seconds
Started Apr 23 02:34:17 PM PDT 24
Finished Apr 23 02:34:19 PM PDT 24
Peak memory 218272 kb
Host smart-d0e573d1-696c-45b8-896e-2165b84ba51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812178085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2812178085
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1393627264
Short name T15
Test name
Test status
Simulation time 101321104 ps
CPU time 0.77 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:24 PM PDT 24
Peak memory 200660 kb
Host smart-f32eb754-3e25-435d-8040-c4f696afec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393627264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1393627264
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3247384684
Short name T257
Test name
Test status
Simulation time 1091960347 ps
CPU time 5.4 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:28 PM PDT 24
Peak memory 201036 kb
Host smart-c8cdd301-0e67-4d80-af93-9c8553c525ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247384684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3247384684
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1266367131
Short name T306
Test name
Test status
Simulation time 134872119 ps
CPU time 1.02 seconds
Started Apr 23 02:34:16 PM PDT 24
Finished Apr 23 02:34:17 PM PDT 24
Peak memory 200812 kb
Host smart-d6beaa3f-7086-4fb9-9ee5-d97bb1cf1592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266367131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1266367131
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2013805067
Short name T142
Test name
Test status
Simulation time 204237738 ps
CPU time 1.42 seconds
Started Apr 23 02:34:16 PM PDT 24
Finished Apr 23 02:34:18 PM PDT 24
Peak memory 200984 kb
Host smart-22dd70d7-aaae-49af-8bb6-d0bbad34a983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013805067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2013805067
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2832083353
Short name T325
Test name
Test status
Simulation time 3953109821 ps
CPU time 12.89 seconds
Started Apr 23 02:34:15 PM PDT 24
Finished Apr 23 02:34:29 PM PDT 24
Peak memory 201084 kb
Host smart-c01d0191-f5ff-4bba-8b8e-e88ce807e9d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832083353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2832083353
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2382650630
Short name T406
Test name
Test status
Simulation time 134523038 ps
CPU time 1.6 seconds
Started Apr 23 02:34:15 PM PDT 24
Finished Apr 23 02:34:18 PM PDT 24
Peak memory 200828 kb
Host smart-e6c686eb-fbd1-4e1d-8864-e7c04b458314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382650630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2382650630
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3863436323
Short name T159
Test name
Test status
Simulation time 171875064 ps
CPU time 1.34 seconds
Started Apr 23 02:34:18 PM PDT 24
Finished Apr 23 02:34:20 PM PDT 24
Peak memory 201008 kb
Host smart-d2d78555-944a-49f6-a470-764abbebf017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863436323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3863436323
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.487193439
Short name T525
Test name
Test status
Simulation time 69539286 ps
CPU time 0.75 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:23 PM PDT 24
Peak memory 200644 kb
Host smart-01caa430-c895-4151-95cd-54594b2321a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487193439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.487193439
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.4058528824
Short name T28
Test name
Test status
Simulation time 2357641745 ps
CPU time 7.78 seconds
Started Apr 23 02:34:17 PM PDT 24
Finished Apr 23 02:34:26 PM PDT 24
Peak memory 222656 kb
Host smart-2edf8375-ff72-47a5-bced-1de3f960d43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058528824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.4058528824
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2160035385
Short name T312
Test name
Test status
Simulation time 244448273 ps
CPU time 1.07 seconds
Started Apr 23 02:34:19 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 218128 kb
Host smart-c680c9ac-a3e3-4878-94c6-558c376e615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160035385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2160035385
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3779224269
Short name T231
Test name
Test status
Simulation time 119568847 ps
CPU time 0.8 seconds
Started Apr 23 02:34:17 PM PDT 24
Finished Apr 23 02:34:18 PM PDT 24
Peak memory 200624 kb
Host smart-78355c3c-8f1c-48ea-8a0f-256242a469b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779224269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3779224269
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.498561161
Short name T526
Test name
Test status
Simulation time 1982758213 ps
CPU time 6.86 seconds
Started Apr 23 02:34:17 PM PDT 24
Finished Apr 23 02:34:25 PM PDT 24
Peak memory 201000 kb
Host smart-e363093b-89c7-4471-872f-a7c2edb7f5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498561161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.498561161
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.931894014
Short name T486
Test name
Test status
Simulation time 143868132 ps
CPU time 1.08 seconds
Started Apr 23 02:34:23 PM PDT 24
Finished Apr 23 02:34:25 PM PDT 24
Peak memory 200812 kb
Host smart-a64cfe26-b921-40aa-b6a8-957cb8c03663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931894014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.931894014
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3052105686
Short name T277
Test name
Test status
Simulation time 259074412 ps
CPU time 1.45 seconds
Started Apr 23 02:34:19 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 200968 kb
Host smart-63f2397a-2155-453f-9c6f-43ac8931ed35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052105686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3052105686
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2025313430
Short name T238
Test name
Test status
Simulation time 2633469566 ps
CPU time 12.86 seconds
Started Apr 23 02:34:19 PM PDT 24
Finished Apr 23 02:34:33 PM PDT 24
Peak memory 201096 kb
Host smart-c4d4475a-b39c-44e0-ba48-2a0e2d508630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025313430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2025313430
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.882132647
Short name T293
Test name
Test status
Simulation time 125441466 ps
CPU time 1.52 seconds
Started Apr 23 02:34:23 PM PDT 24
Finished Apr 23 02:34:25 PM PDT 24
Peak memory 209024 kb
Host smart-59c2adc5-5ab5-4040-ad55-02e11b539734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882132647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.882132647
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.742149295
Short name T332
Test name
Test status
Simulation time 127581730 ps
CPU time 1 seconds
Started Apr 23 02:34:17 PM PDT 24
Finished Apr 23 02:34:18 PM PDT 24
Peak memory 200824 kb
Host smart-422dffe2-0eaf-45bb-9d17-48358841efb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742149295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.742149295
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3970020735
Short name T493
Test name
Test status
Simulation time 74690863 ps
CPU time 0.76 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:24 PM PDT 24
Peak memory 200572 kb
Host smart-70988dbe-0579-4f76-9724-1a590a25d8c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970020735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3970020735
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.617210845
Short name T361
Test name
Test status
Simulation time 1224381699 ps
CPU time 5.79 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:29 PM PDT 24
Peak memory 230812 kb
Host smart-ac522034-22e7-462a-9492-cf5188676ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617210845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.617210845
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1411449726
Short name T408
Test name
Test status
Simulation time 244152268 ps
CPU time 1.21 seconds
Started Apr 23 02:34:25 PM PDT 24
Finished Apr 23 02:34:27 PM PDT 24
Peak memory 218132 kb
Host smart-8ad4d41b-d865-4b46-8f31-07d0ee649258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411449726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1411449726
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2201961331
Short name T527
Test name
Test status
Simulation time 174078380 ps
CPU time 0.8 seconds
Started Apr 23 02:34:19 PM PDT 24
Finished Apr 23 02:34:20 PM PDT 24
Peak memory 200592 kb
Host smart-18312b5a-9f47-4d3b-85e7-3cc7d3ae4212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201961331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2201961331
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.496268978
Short name T442
Test name
Test status
Simulation time 1664287291 ps
CPU time 6.39 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:28 PM PDT 24
Peak memory 201024 kb
Host smart-85c0bb79-1efa-4f7a-851a-771bfdec910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496268978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.496268978
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1422972090
Short name T288
Test name
Test status
Simulation time 108612709 ps
CPU time 1 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:23 PM PDT 24
Peak memory 200812 kb
Host smart-218416af-724d-41cb-b05e-44aeae5814bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422972090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1422972090
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3271916986
Short name T424
Test name
Test status
Simulation time 232318740 ps
CPU time 1.41 seconds
Started Apr 23 02:34:20 PM PDT 24
Finished Apr 23 02:34:22 PM PDT 24
Peak memory 201060 kb
Host smart-a2b31d6d-e5fa-4219-ba13-f983a2a827e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271916986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3271916986
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1645522770
Short name T209
Test name
Test status
Simulation time 8559260956 ps
CPU time 30.9 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:54 PM PDT 24
Peak memory 201052 kb
Host smart-d6e8bad6-b66a-42b6-8858-cc17c6c286ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645522770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1645522770
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2690403778
Short name T533
Test name
Test status
Simulation time 319325732 ps
CPU time 2.13 seconds
Started Apr 23 02:34:20 PM PDT 24
Finished Apr 23 02:34:23 PM PDT 24
Peak memory 200764 kb
Host smart-982fa505-f089-43f7-8346-9cb126df0d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690403778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2690403778
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2022002233
Short name T425
Test name
Test status
Simulation time 110689711 ps
CPU time 0.99 seconds
Started Apr 23 02:34:19 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 200800 kb
Host smart-3a028914-7677-4fd0-85e0-d2f89885a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022002233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2022002233
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2905034246
Short name T100
Test name
Test status
Simulation time 66484586 ps
CPU time 0.8 seconds
Started Apr 23 02:34:27 PM PDT 24
Finished Apr 23 02:34:28 PM PDT 24
Peak memory 200648 kb
Host smart-b386c0ac-8c42-4276-8a05-3f6cca3b1896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905034246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2905034246
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.101773622
Short name T44
Test name
Test status
Simulation time 1222951953 ps
CPU time 5.66 seconds
Started Apr 23 02:34:27 PM PDT 24
Finished Apr 23 02:34:34 PM PDT 24
Peak memory 222144 kb
Host smart-8062cc66-eec2-4d76-a463-fc7e0587394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101773622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.101773622
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1189876134
Short name T451
Test name
Test status
Simulation time 244530552 ps
CPU time 0.99 seconds
Started Apr 23 02:34:25 PM PDT 24
Finished Apr 23 02:34:26 PM PDT 24
Peak memory 218196 kb
Host smart-0d098360-87da-42aa-9edc-4853b23facc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189876134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1189876134
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2606639621
Short name T439
Test name
Test status
Simulation time 215958102 ps
CPU time 0.93 seconds
Started Apr 23 02:34:27 PM PDT 24
Finished Apr 23 02:34:29 PM PDT 24
Peak memory 200644 kb
Host smart-172f5686-bb85-4633-8b2d-ec63b40b34ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606639621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2606639621
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2703090878
Short name T473
Test name
Test status
Simulation time 1374075587 ps
CPU time 4.91 seconds
Started Apr 23 02:34:27 PM PDT 24
Finished Apr 23 02:34:32 PM PDT 24
Peak memory 201024 kb
Host smart-78fa42b4-6e24-4d82-9f27-e72fc412f52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703090878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2703090878
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3467289176
Short name T517
Test name
Test status
Simulation time 147522072 ps
CPU time 1.1 seconds
Started Apr 23 02:34:25 PM PDT 24
Finished Apr 23 02:34:27 PM PDT 24
Peak memory 200832 kb
Host smart-321339c4-8e38-49f4-a16a-91849fb53594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467289176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3467289176
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4276176484
Short name T436
Test name
Test status
Simulation time 216833146 ps
CPU time 1.36 seconds
Started Apr 23 02:34:22 PM PDT 24
Finished Apr 23 02:34:24 PM PDT 24
Peak memory 201036 kb
Host smart-6c8a1ffa-9909-4732-9d77-85796094ac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276176484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4276176484
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3469660636
Short name T448
Test name
Test status
Simulation time 11276406109 ps
CPU time 38.08 seconds
Started Apr 23 02:34:25 PM PDT 24
Finished Apr 23 02:35:04 PM PDT 24
Peak memory 209976 kb
Host smart-2e835f3b-8f4c-47f8-b833-14894342a720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469660636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3469660636
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.384528578
Short name T514
Test name
Test status
Simulation time 364959757 ps
CPU time 1.98 seconds
Started Apr 23 02:34:25 PM PDT 24
Finished Apr 23 02:34:28 PM PDT 24
Peak memory 200768 kb
Host smart-3ade4e5b-c576-49ab-97a4-cb4569d67856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384528578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.384528578
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.255550312
Short name T430
Test name
Test status
Simulation time 120651455 ps
CPU time 0.94 seconds
Started Apr 23 02:34:27 PM PDT 24
Finished Apr 23 02:34:28 PM PDT 24
Peak memory 200832 kb
Host smart-4566db6f-d020-480f-9c3a-73bc4eab434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255550312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.255550312
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3373505634
Short name T399
Test name
Test status
Simulation time 69445462 ps
CPU time 0.73 seconds
Started Apr 23 02:34:31 PM PDT 24
Finished Apr 23 02:34:32 PM PDT 24
Peak memory 200668 kb
Host smart-af2c42ae-df07-4e79-a377-185dabc1ef3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373505634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3373505634
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1090306004
Short name T67
Test name
Test status
Simulation time 1222874709 ps
CPU time 5.55 seconds
Started Apr 23 02:34:32 PM PDT 24
Finished Apr 23 02:34:39 PM PDT 24
Peak memory 218644 kb
Host smart-17d5a938-51ce-41cb-bd59-d986234d51f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090306004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1090306004
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.4049421680
Short name T299
Test name
Test status
Simulation time 244526835 ps
CPU time 1.05 seconds
Started Apr 23 02:34:31 PM PDT 24
Finished Apr 23 02:34:32 PM PDT 24
Peak memory 218216 kb
Host smart-e948ede3-9dda-4d70-9be3-8a603a92fb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049421680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.4049421680
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.347517852
Short name T183
Test name
Test status
Simulation time 143693789 ps
CPU time 0.79 seconds
Started Apr 23 02:34:24 PM PDT 24
Finished Apr 23 02:34:25 PM PDT 24
Peak memory 200628 kb
Host smart-a32695d7-53ab-4a69-8de2-61bfb9f17c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347517852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.347517852
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.822278492
Short name T309
Test name
Test status
Simulation time 984324155 ps
CPU time 4.97 seconds
Started Apr 23 02:34:26 PM PDT 24
Finished Apr 23 02:34:31 PM PDT 24
Peak memory 201000 kb
Host smart-e4ee09fe-7294-4f2d-936a-6d03b323d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822278492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.822278492
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3921571623
Short name T66
Test name
Test status
Simulation time 152121027 ps
CPU time 1.08 seconds
Started Apr 23 02:34:34 PM PDT 24
Finished Apr 23 02:34:36 PM PDT 24
Peak memory 200832 kb
Host smart-56986458-d998-4a49-977d-cc93586d033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921571623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3921571623
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3723516468
Short name T186
Test name
Test status
Simulation time 248243805 ps
CPU time 1.36 seconds
Started Apr 23 02:34:26 PM PDT 24
Finished Apr 23 02:34:27 PM PDT 24
Peak memory 201012 kb
Host smart-adff4092-612d-4264-a906-709f54de9779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723516468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3723516468
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3468418367
Short name T331
Test name
Test status
Simulation time 2633310102 ps
CPU time 11.47 seconds
Started Apr 23 02:34:28 PM PDT 24
Finished Apr 23 02:34:40 PM PDT 24
Peak memory 209316 kb
Host smart-dc1e3ad1-d5ca-4cbd-be5e-ef7553b895a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468418367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3468418367
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3240148781
Short name T501
Test name
Test status
Simulation time 122358081 ps
CPU time 1.47 seconds
Started Apr 23 02:34:29 PM PDT 24
Finished Apr 23 02:34:31 PM PDT 24
Peak memory 200816 kb
Host smart-07edc656-3846-4c15-af7c-4a0617dddc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240148781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3240148781
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.4232819733
Short name T132
Test name
Test status
Simulation time 234193217 ps
CPU time 1.4 seconds
Started Apr 23 02:34:27 PM PDT 24
Finished Apr 23 02:34:29 PM PDT 24
Peak memory 200796 kb
Host smart-9ae4b29e-a183-45ca-99cb-215a25197d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232819733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4232819733
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1426976304
Short name T189
Test name
Test status
Simulation time 62854687 ps
CPU time 0.71 seconds
Started Apr 23 02:34:35 PM PDT 24
Finished Apr 23 02:34:37 PM PDT 24
Peak memory 200624 kb
Host smart-9b331374-12d9-4fa8-b574-cb53d63b53f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426976304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1426976304
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2074820022
Short name T502
Test name
Test status
Simulation time 2168015551 ps
CPU time 7.29 seconds
Started Apr 23 02:34:29 PM PDT 24
Finished Apr 23 02:34:37 PM PDT 24
Peak memory 218148 kb
Host smart-e21ab0c2-35c6-4706-b40c-df86e4c164a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074820022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2074820022
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2335695674
Short name T273
Test name
Test status
Simulation time 244276543 ps
CPU time 1.05 seconds
Started Apr 23 02:34:33 PM PDT 24
Finished Apr 23 02:34:36 PM PDT 24
Peak memory 218236 kb
Host smart-4db6efcf-5f16-4c87-a35c-41fa151a1c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335695674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2335695674
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.218367026
Short name T294
Test name
Test status
Simulation time 85739559 ps
CPU time 0.78 seconds
Started Apr 23 02:34:28 PM PDT 24
Finished Apr 23 02:34:29 PM PDT 24
Peak memory 200660 kb
Host smart-394d4586-5d9b-4a69-a7e0-7139ae212c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218367026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.218367026
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1071059994
Short name T381
Test name
Test status
Simulation time 1117625247 ps
CPU time 5.19 seconds
Started Apr 23 02:34:29 PM PDT 24
Finished Apr 23 02:34:35 PM PDT 24
Peak memory 201008 kb
Host smart-d23836d5-12e3-4b9c-b976-55fe0a97ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071059994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1071059994
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.465367377
Short name T7
Test name
Test status
Simulation time 144569666 ps
CPU time 1.09 seconds
Started Apr 23 02:34:29 PM PDT 24
Finished Apr 23 02:34:30 PM PDT 24
Peak memory 200816 kb
Host smart-db576f0e-142a-4c9d-b348-df7e37a5776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465367377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.465367377
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1413704295
Short name T149
Test name
Test status
Simulation time 109576071 ps
CPU time 1.14 seconds
Started Apr 23 02:34:34 PM PDT 24
Finished Apr 23 02:34:36 PM PDT 24
Peak memory 201012 kb
Host smart-59317bac-e970-4452-b8b2-cebc26b6d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413704295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1413704295
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2316366771
Short name T286
Test name
Test status
Simulation time 5797496296 ps
CPU time 25.39 seconds
Started Apr 23 02:34:32 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 201100 kb
Host smart-0ffa8ea6-558b-4b93-8a1c-d6716b4a1122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316366771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2316366771
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.419755030
Short name T492
Test name
Test status
Simulation time 150528876 ps
CPU time 1.84 seconds
Started Apr 23 02:34:30 PM PDT 24
Finished Apr 23 02:34:32 PM PDT 24
Peak memory 200828 kb
Host smart-aa356bc1-cdce-43b7-9962-a8efca2dab32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419755030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.419755030
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3326962265
Short name T164
Test name
Test status
Simulation time 117704149 ps
CPU time 1.02 seconds
Started Apr 23 02:34:29 PM PDT 24
Finished Apr 23 02:34:30 PM PDT 24
Peak memory 200820 kb
Host smart-31bb9dda-e631-4061-a5c3-7f7278cacbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326962265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3326962265
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2384608477
Short name T317
Test name
Test status
Simulation time 89032653 ps
CPU time 0.81 seconds
Started Apr 23 02:32:30 PM PDT 24
Finished Apr 23 02:32:31 PM PDT 24
Peak memory 200612 kb
Host smart-0da8f809-85cd-4716-875a-f9822c1a019e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384608477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2384608477
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.464016005
Short name T485
Test name
Test status
Simulation time 1217906927 ps
CPU time 5.66 seconds
Started Apr 23 02:32:25 PM PDT 24
Finished Apr 23 02:32:31 PM PDT 24
Peak memory 218608 kb
Host smart-2254579d-64ed-4d7e-beff-cc1efc72a863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464016005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.464016005
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4126530088
Short name T50
Test name
Test status
Simulation time 244282179 ps
CPU time 1.07 seconds
Started Apr 23 02:32:26 PM PDT 24
Finished Apr 23 02:32:27 PM PDT 24
Peak memory 218132 kb
Host smart-4734e36e-6826-4afd-8458-be3f6c1f0dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126530088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4126530088
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3584666662
Short name T218
Test name
Test status
Simulation time 114864070 ps
CPU time 0.74 seconds
Started Apr 23 02:32:26 PM PDT 24
Finished Apr 23 02:32:27 PM PDT 24
Peak memory 200476 kb
Host smart-62d97538-fb8e-4e4d-99f4-865a4a722960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584666662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3584666662
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3767595440
Short name T198
Test name
Test status
Simulation time 1073620647 ps
CPU time 4.73 seconds
Started Apr 23 02:32:24 PM PDT 24
Finished Apr 23 02:32:29 PM PDT 24
Peak memory 201016 kb
Host smart-78f78cbb-a2bd-4b43-955d-8ff90193c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767595440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3767595440
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1836745772
Short name T396
Test name
Test status
Simulation time 107697256 ps
CPU time 1.04 seconds
Started Apr 23 02:32:26 PM PDT 24
Finished Apr 23 02:32:28 PM PDT 24
Peak memory 200844 kb
Host smart-3032c6a8-53b6-40f0-9e14-857290822210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836745772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1836745772
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1657130406
Short name T282
Test name
Test status
Simulation time 255077274 ps
CPU time 1.45 seconds
Started Apr 23 02:32:22 PM PDT 24
Finished Apr 23 02:32:24 PM PDT 24
Peak memory 201000 kb
Host smart-a96125da-c9ab-4d40-996f-fc649c03c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657130406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1657130406
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1409584939
Short name T207
Test name
Test status
Simulation time 602196374 ps
CPU time 2.85 seconds
Started Apr 23 02:32:29 PM PDT 24
Finished Apr 23 02:32:32 PM PDT 24
Peak memory 201020 kb
Host smart-ae8c2cae-e107-40a8-b3e1-c48ce95b6b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409584939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1409584939
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.667702727
Short name T316
Test name
Test status
Simulation time 382237250 ps
CPU time 2.37 seconds
Started Apr 23 02:32:25 PM PDT 24
Finished Apr 23 02:32:28 PM PDT 24
Peak memory 200792 kb
Host smart-9d60491b-6797-45d6-88b1-ecdb26495a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667702727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.667702727
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1848152873
Short name T298
Test name
Test status
Simulation time 301869947 ps
CPU time 1.6 seconds
Started Apr 23 02:32:27 PM PDT 24
Finished Apr 23 02:32:29 PM PDT 24
Peak memory 201048 kb
Host smart-9e3acce8-00ce-4913-a1d1-da3d9da74076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848152873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1848152873
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.613196735
Short name T280
Test name
Test status
Simulation time 63066328 ps
CPU time 0.72 seconds
Started Apr 23 02:32:34 PM PDT 24
Finished Apr 23 02:32:35 PM PDT 24
Peak memory 200620 kb
Host smart-56cdd1e7-2581-43f4-a4c9-863e65241e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613196735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.613196735
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3163084783
Short name T60
Test name
Test status
Simulation time 1230257958 ps
CPU time 5.47 seconds
Started Apr 23 02:32:29 PM PDT 24
Finished Apr 23 02:32:35 PM PDT 24
Peak memory 217564 kb
Host smart-720f8b76-55b8-48c2-8d5e-5231a02d8074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163084783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3163084783
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1148081604
Short name T352
Test name
Test status
Simulation time 244417255 ps
CPU time 1.07 seconds
Started Apr 23 02:32:31 PM PDT 24
Finished Apr 23 02:32:32 PM PDT 24
Peak memory 218140 kb
Host smart-e3a6df97-fa5c-40e9-8767-6e26b623d6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148081604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1148081604
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.4031516575
Short name T431
Test name
Test status
Simulation time 205368088 ps
CPU time 0.95 seconds
Started Apr 23 02:32:30 PM PDT 24
Finished Apr 23 02:32:32 PM PDT 24
Peak memory 200648 kb
Host smart-fa5f9c8a-4bf5-4801-a529-f3812d2333ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031516575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.4031516575
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3757776166
Short name T210
Test name
Test status
Simulation time 1479131091 ps
CPU time 5.36 seconds
Started Apr 23 02:32:31 PM PDT 24
Finished Apr 23 02:32:36 PM PDT 24
Peak memory 200844 kb
Host smart-679a1e4e-3a65-4fa5-a810-7254beae2c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757776166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3757776166
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1234239202
Short name T11
Test name
Test status
Simulation time 153616533 ps
CPU time 1.2 seconds
Started Apr 23 02:32:31 PM PDT 24
Finished Apr 23 02:32:32 PM PDT 24
Peak memory 200792 kb
Host smart-64d3a519-b3e1-48bc-ac0c-d57b0d61c96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234239202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1234239202
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1243347068
Short name T144
Test name
Test status
Simulation time 206579467 ps
CPU time 1.3 seconds
Started Apr 23 02:32:28 PM PDT 24
Finished Apr 23 02:32:29 PM PDT 24
Peak memory 200984 kb
Host smart-cdfadd09-c7f9-4f7f-9f70-d224b3c7a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243347068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1243347068
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.212042398
Short name T335
Test name
Test status
Simulation time 13719927935 ps
CPU time 45.41 seconds
Started Apr 23 02:32:34 PM PDT 24
Finished Apr 23 02:33:20 PM PDT 24
Peak memory 209208 kb
Host smart-d1568aea-7c08-4524-a781-6477218b1c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212042398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.212042398
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2751533870
Short name T358
Test name
Test status
Simulation time 534614678 ps
CPU time 3 seconds
Started Apr 23 02:32:30 PM PDT 24
Finished Apr 23 02:32:34 PM PDT 24
Peak memory 200824 kb
Host smart-5680ee99-4431-4dfe-8463-e5adc0c6461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751533870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2751533870
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1829799927
Short name T185
Test name
Test status
Simulation time 153070108 ps
CPU time 1.18 seconds
Started Apr 23 02:32:28 PM PDT 24
Finished Apr 23 02:32:29 PM PDT 24
Peak memory 200992 kb
Host smart-1e1e2f72-03ce-48f4-a822-61c5c91c8077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829799927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1829799927
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2018478312
Short name T151
Test name
Test status
Simulation time 83699837 ps
CPU time 0.77 seconds
Started Apr 23 02:32:40 PM PDT 24
Finished Apr 23 02:32:41 PM PDT 24
Peak memory 200632 kb
Host smart-413f20f9-f142-41ad-9ba2-6c5f5c95bfcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018478312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2018478312
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.110844742
Short name T368
Test name
Test status
Simulation time 2354545200 ps
CPU time 7.68 seconds
Started Apr 23 02:32:35 PM PDT 24
Finished Apr 23 02:32:43 PM PDT 24
Peak memory 222740 kb
Host smart-9d63227a-9068-4098-aed0-9aecefdb8c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110844742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.110844742
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3229303096
Short name T444
Test name
Test status
Simulation time 243574445 ps
CPU time 1.14 seconds
Started Apr 23 02:32:39 PM PDT 24
Finished Apr 23 02:32:41 PM PDT 24
Peak memory 218140 kb
Host smart-b67cf437-d63f-4ecb-aba9-5ab20de27a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229303096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3229303096
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3730223715
Short name T508
Test name
Test status
Simulation time 96401028 ps
CPU time 0.72 seconds
Started Apr 23 02:32:35 PM PDT 24
Finished Apr 23 02:32:36 PM PDT 24
Peak memory 200640 kb
Host smart-f59111c2-c605-40b3-b28f-d564f7adde82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730223715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3730223715
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2436725229
Short name T97
Test name
Test status
Simulation time 1003034788 ps
CPU time 4.82 seconds
Started Apr 23 02:32:33 PM PDT 24
Finished Apr 23 02:32:38 PM PDT 24
Peak memory 201056 kb
Host smart-8255812d-4cbb-477a-945e-95f46cc55a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436725229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2436725229
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3097908995
Short name T397
Test name
Test status
Simulation time 103122186 ps
CPU time 1 seconds
Started Apr 23 02:32:35 PM PDT 24
Finished Apr 23 02:32:36 PM PDT 24
Peak memory 200864 kb
Host smart-70effb1a-3987-4dd8-a839-e874b3cd4756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097908995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3097908995
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4135477725
Short name T497
Test name
Test status
Simulation time 120734127 ps
CPU time 1.13 seconds
Started Apr 23 02:32:35 PM PDT 24
Finished Apr 23 02:32:37 PM PDT 24
Peak memory 200956 kb
Host smart-f5f7de40-5f45-445d-8e12-b77ae830722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135477725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4135477725
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.631018437
Short name T105
Test name
Test status
Simulation time 3853062791 ps
CPU time 13.1 seconds
Started Apr 23 02:32:38 PM PDT 24
Finished Apr 23 02:32:51 PM PDT 24
Peak memory 201060 kb
Host smart-7ec20566-4c41-4e84-9939-272d16630db1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631018437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.631018437
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1663537652
Short name T347
Test name
Test status
Simulation time 327571316 ps
CPU time 2.22 seconds
Started Apr 23 02:32:35 PM PDT 24
Finished Apr 23 02:32:37 PM PDT 24
Peak memory 200780 kb
Host smart-4e8cda58-f6af-45ec-be5e-1e1029ca2f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663537652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1663537652
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3192787046
Short name T178
Test name
Test status
Simulation time 110366145 ps
CPU time 0.96 seconds
Started Apr 23 02:32:33 PM PDT 24
Finished Apr 23 02:32:35 PM PDT 24
Peak memory 200820 kb
Host smart-b1c643fb-c00f-478f-a393-9e92fab4f7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192787046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3192787046
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1751434007
Short name T369
Test name
Test status
Simulation time 70357625 ps
CPU time 0.72 seconds
Started Apr 23 02:32:43 PM PDT 24
Finished Apr 23 02:32:44 PM PDT 24
Peak memory 200604 kb
Host smart-2c5facec-dd93-4b32-8c96-8baa7ef648b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751434007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1751434007
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1664601640
Short name T69
Test name
Test status
Simulation time 2358392503 ps
CPU time 7.85 seconds
Started Apr 23 02:32:40 PM PDT 24
Finished Apr 23 02:32:48 PM PDT 24
Peak memory 218632 kb
Host smart-bec9ea03-df23-40d5-b211-cce223f908b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664601640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1664601640
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3041978320
Short name T221
Test name
Test status
Simulation time 244162980 ps
CPU time 1.15 seconds
Started Apr 23 02:32:42 PM PDT 24
Finished Apr 23 02:32:43 PM PDT 24
Peak memory 218192 kb
Host smart-b70bb2d7-c733-436a-a6df-f5a6a723554b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041978320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3041978320
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3447268228
Short name T507
Test name
Test status
Simulation time 170576994 ps
CPU time 0.81 seconds
Started Apr 23 02:32:37 PM PDT 24
Finished Apr 23 02:32:38 PM PDT 24
Peak memory 200604 kb
Host smart-d88993e8-c2bf-4f28-bdbf-e85914962a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447268228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3447268228
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.870858641
Short name T392
Test name
Test status
Simulation time 817454139 ps
CPU time 4.43 seconds
Started Apr 23 02:32:39 PM PDT 24
Finished Apr 23 02:32:44 PM PDT 24
Peak memory 201004 kb
Host smart-0292d9d0-13bd-41f2-a1af-cee3820478e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870858641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.870858641
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1858540873
Short name T57
Test name
Test status
Simulation time 172454510 ps
CPU time 1.13 seconds
Started Apr 23 02:32:40 PM PDT 24
Finished Apr 23 02:32:42 PM PDT 24
Peak memory 200832 kb
Host smart-6ddf136d-7bf5-4e12-99c5-123d9c177927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858540873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1858540873
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1613460810
Short name T173
Test name
Test status
Simulation time 117777102 ps
CPU time 1.16 seconds
Started Apr 23 02:32:39 PM PDT 24
Finished Apr 23 02:32:41 PM PDT 24
Peak memory 201012 kb
Host smart-2c82f1db-036d-42ac-92fd-6c56f3de4a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613460810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1613460810
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1204754644
Short name T532
Test name
Test status
Simulation time 1435254711 ps
CPU time 6.6 seconds
Started Apr 23 02:32:40 PM PDT 24
Finished Apr 23 02:32:48 PM PDT 24
Peak memory 200948 kb
Host smart-67a68e11-e44f-4e27-b4d6-79f857d0ebfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204754644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1204754644
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.464184521
Short name T52
Test name
Test status
Simulation time 411377028 ps
CPU time 2.16 seconds
Started Apr 23 02:32:40 PM PDT 24
Finished Apr 23 02:32:43 PM PDT 24
Peak memory 209016 kb
Host smart-87ef044a-2cf6-448a-8903-4b7934fb2949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464184521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.464184521
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2838136799
Short name T197
Test name
Test status
Simulation time 151285403 ps
CPU time 1.03 seconds
Started Apr 23 02:32:36 PM PDT 24
Finished Apr 23 02:32:37 PM PDT 24
Peak memory 200848 kb
Host smart-8c659a5c-a07b-4f7b-a74e-db136903d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838136799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2838136799
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.143125562
Short name T148
Test name
Test status
Simulation time 57323779 ps
CPU time 0.77 seconds
Started Apr 23 02:32:47 PM PDT 24
Finished Apr 23 02:32:49 PM PDT 24
Peak memory 200600 kb
Host smart-2e541b6f-4842-4438-a341-4e3e900f08fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143125562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.143125562
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1033686634
Short name T45
Test name
Test status
Simulation time 2168752622 ps
CPU time 7.14 seconds
Started Apr 23 02:32:48 PM PDT 24
Finished Apr 23 02:32:55 PM PDT 24
Peak memory 222684 kb
Host smart-a41fe933-c07a-463b-be2b-09b53cab523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033686634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1033686634
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.614355202
Short name T342
Test name
Test status
Simulation time 244943991 ps
CPU time 1 seconds
Started Apr 23 02:32:46 PM PDT 24
Finished Apr 23 02:32:47 PM PDT 24
Peak memory 218200 kb
Host smart-9208a93e-35c6-4714-9838-2d1e233ad24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614355202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.614355202
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3722569125
Short name T434
Test name
Test status
Simulation time 144148558 ps
CPU time 0.78 seconds
Started Apr 23 02:32:44 PM PDT 24
Finished Apr 23 02:32:45 PM PDT 24
Peak memory 200704 kb
Host smart-f1936990-803b-4517-bac3-b9156bacc587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722569125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3722569125
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.452359497
Short name T202
Test name
Test status
Simulation time 836785663 ps
CPU time 3.89 seconds
Started Apr 23 02:32:45 PM PDT 24
Finished Apr 23 02:32:49 PM PDT 24
Peak memory 201044 kb
Host smart-5a3e433e-f37e-4bc7-950c-fcebc051ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452359497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.452359497
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1444236959
Short name T150
Test name
Test status
Simulation time 107444655 ps
CPU time 1 seconds
Started Apr 23 02:32:44 PM PDT 24
Finished Apr 23 02:32:45 PM PDT 24
Peak memory 200864 kb
Host smart-8f7e2c95-a3a4-4ac8-9aa6-1a84dc10b1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444236959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1444236959
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1644808497
Short name T395
Test name
Test status
Simulation time 197698153 ps
CPU time 1.29 seconds
Started Apr 23 02:32:45 PM PDT 24
Finished Apr 23 02:32:47 PM PDT 24
Peak memory 200848 kb
Host smart-967405d3-1cf9-43ae-b933-67eb571ff31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644808497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1644808497
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2110319984
Short name T179
Test name
Test status
Simulation time 2049339960 ps
CPU time 7.7 seconds
Started Apr 23 02:32:46 PM PDT 24
Finished Apr 23 02:32:54 PM PDT 24
Peak memory 209288 kb
Host smart-49d02d49-207b-4579-96f9-9de098381121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110319984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2110319984
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1058840554
Short name T476
Test name
Test status
Simulation time 397030503 ps
CPU time 2.07 seconds
Started Apr 23 02:32:45 PM PDT 24
Finished Apr 23 02:32:48 PM PDT 24
Peak memory 200824 kb
Host smart-b02acc62-49c9-4a4b-9a1c-7a329fdf6fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058840554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1058840554
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3726952380
Short name T64
Test name
Test status
Simulation time 63565089 ps
CPU time 0.73 seconds
Started Apr 23 02:32:44 PM PDT 24
Finished Apr 23 02:32:45 PM PDT 24
Peak memory 200860 kb
Host smart-5577d7b5-316d-479b-a007-faa194571a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726952380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3726952380
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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