Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8032

1

T2

149

T4

26

T10

99

auto[1]

11143

1

T2

153

T3

4

T4

21

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5920	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6491	1			T1	1		T2	105		T3	2
reset_info_cp[2]	2885	1			T2	53		T3	1		T4	7
reset_info_cp[4]	3941	1			T2	64		T3	1		T4	14
reset_info_cp[8]	124	1			T4	1		T8	1		T10	2
reset_info_cp[16]	116	1			T10	1		T51	1		T37	3
reset_info_cp[32]	107	1			T4	1		T11	3		T36	1
reset_info_cp[64]	99	1			T2	3		T11	1		T51	1
reset_info_cp[128]	112	1			T2	4		T40	1		T22	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3076	1			T2	40		T4	8		T10	19
reset_info_cp[1]	auto[1]	2795	1			T2	64		T3	1		T4	5
reset_info_cp[2]	auto[0]	907	1			T2	26		T4	3		T10	19
reset_info_cp[2]	auto[1]	1978	1			T2	27		T3	1		T4	4
reset_info_cp[4]	auto[0]	1376	1			T2	32		T4	7		T10	30
reset_info_cp[4]	auto[1]	2565	1			T2	32		T3	1		T4	7
reset_info_cp[8]	auto[0]	52	1			T37	1		T137	2		T73	1
reset_info_cp[8]	auto[1]	72	1			T4	1		T8	1		T10	2
reset_info_cp[16]	auto[0]	43	1			T10	1		T37	1		T78	1
reset_info_cp[16]	auto[1]	73	1			T51	1		T37	2		T23	1
reset_info_cp[32]	auto[0]	45	1			T11	3		T130	1		T81	2
reset_info_cp[32]	auto[1]	62	1			T4	1		T36	1		T133	1
reset_info_cp[64]	auto[0]	36	1			T2	2		T11	1		T81	1
reset_info_cp[64]	auto[1]	63	1			T2	1		T51	1		T40	1
reset_info_cp[128]	auto[0]	48	1			T2	2		T34	1		T81	1
reset_info_cp[128]	auto[1]	64	1			T2	2		T40	1		T22	2