Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T539 /workspace/coverage/default/19.rstmgr_reset.1808614565 Apr 25 12:57:56 PM PDT 24 Apr 25 12:58:05 PM PDT 24 1365880830 ps
T540 /workspace/coverage/default/2.rstmgr_stress_all.1054520003 Apr 25 12:57:35 PM PDT 24 Apr 25 12:57:59 PM PDT 24 5086785825 ps
T541 /workspace/coverage/default/28.rstmgr_reset.1479229659 Apr 25 12:57:57 PM PDT 24 Apr 25 12:58:05 PM PDT 24 1132701300 ps
T542 /workspace/coverage/default/25.rstmgr_stress_all.1826503894 Apr 25 12:58:05 PM PDT 24 Apr 25 12:58:41 PM PDT 24 10548454105 ps
T543 /workspace/coverage/default/38.rstmgr_por_stretcher.2396457447 Apr 25 12:58:12 PM PDT 24 Apr 25 12:58:17 PM PDT 24 219160001 ps
T55 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3849162605 Apr 25 12:50:15 PM PDT 24 Apr 25 12:50:22 PM PDT 24 872446140 ps
T56 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.367520874 Apr 25 12:50:15 PM PDT 24 Apr 25 12:50:20 PM PDT 24 60746131 ps
T57 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1192754320 Apr 25 12:50:09 PM PDT 24 Apr 25 12:50:13 PM PDT 24 144900484 ps
T61 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.814628266 Apr 25 12:50:10 PM PDT 24 Apr 25 12:50:14 PM PDT 24 95235613 ps
T60 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.278728354 Apr 25 12:50:01 PM PDT 24 Apr 25 12:50:05 PM PDT 24 202453667 ps
T58 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.940228884 Apr 25 12:50:01 PM PDT 24 Apr 25 12:50:05 PM PDT 24 191441939 ps
T105 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1722604098 Apr 25 12:50:22 PM PDT 24 Apr 25 12:50:26 PM PDT 24 81581159 ps
T59 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.652877413 Apr 25 12:50:19 PM PDT 24 Apr 25 12:50:30 PM PDT 24 479914641 ps
T544 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3785444809 Apr 25 12:50:15 PM PDT 24 Apr 25 12:50:27 PM PDT 24 1542869194 ps
T106 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3820948455 Apr 25 12:50:10 PM PDT 24 Apr 25 12:50:14 PM PDT 24 74326665 ps
T114 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4126136005 Apr 25 12:50:21 PM PDT 24 Apr 25 12:50:27 PM PDT 24 490835595 ps
T86 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.310139256 Apr 25 12:50:20 PM PDT 24 Apr 25 12:50:25 PM PDT 24 111748179 ps
T545 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3767469605 Apr 25 12:50:19 PM PDT 24 Apr 25 12:50:26 PM PDT 24 266113503 ps
T107 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1314475842 Apr 25 12:50:17 PM PDT 24 Apr 25 12:50:22 PM PDT 24 79743954 ps
T546 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.644500994 Apr 25 12:49:53 PM PDT 24 Apr 25 12:49:56 PM PDT 24 187533361 ps
T62 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.289143133 Apr 25 12:50:00 PM PDT 24 Apr 25 12:50:06 PM PDT 24 920537194 ps
T87 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2831452068 Apr 25 12:50:12 PM PDT 24 Apr 25 12:50:18 PM PDT 24 131036766 ps
T88 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2844894310 Apr 25 12:50:21 PM PDT 24 Apr 25 12:50:26 PM PDT 24 121373125 ps
T547 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3470241556 Apr 25 12:50:04 PM PDT 24 Apr 25 12:50:08 PM PDT 24 83235382 ps
T89 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.362407107 Apr 25 12:50:00 PM PDT 24 Apr 25 12:50:04 PM PDT 24 506196129 ps
T108 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.262739435 Apr 25 12:50:01 PM PDT 24 Apr 25 12:50:05 PM PDT 24 60242336 ps
T548 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3266508214 Apr 25 12:50:39 PM PDT 24 Apr 25 12:50:42 PM PDT 24 417036210 ps
T90 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4220046767 Apr 25 12:50:16 PM PDT 24 Apr 25 12:50:24 PM PDT 24 887864613 ps
T91 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.509479075 Apr 25 12:50:11 PM PDT 24 Apr 25 12:50:15 PM PDT 24 118822618 ps
T109 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1564348942 Apr 25 12:50:09 PM PDT 24 Apr 25 12:50:12 PM PDT 24 127579505 ps
T110 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3768842536 Apr 25 12:49:53 PM PDT 24 Apr 25 12:49:56 PM PDT 24 92240518 ps
T92 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1448176697 Apr 25 12:50:22 PM PDT 24 Apr 25 12:50:27 PM PDT 24 167496220 ps
T115 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3653253175 Apr 25 12:50:18 PM PDT 24 Apr 25 12:50:25 PM PDT 24 341952229 ps
T116 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4054235618 Apr 25 12:50:16 PM PDT 24 Apr 25 12:50:24 PM PDT 24 584612772 ps
T117 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3425461185 Apr 25 12:50:10 PM PDT 24 Apr 25 12:50:16 PM PDT 24 530790063 ps
T134 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3362500032 Apr 25 12:50:16 PM PDT 24 Apr 25 12:50:24 PM PDT 24 945992116 ps
T549 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3659857361 Apr 25 12:50:11 PM PDT 24 Apr 25 12:50:15 PM PDT 24 64824106 ps
T111 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.694156014 Apr 25 12:50:03 PM PDT 24 Apr 25 12:50:08 PM PDT 24 226156165 ps
T112 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1950896916 Apr 25 12:50:28 PM PDT 24 Apr 25 12:50:31 PM PDT 24 90438411 ps
T550 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1220532945 Apr 25 12:50:08 PM PDT 24 Apr 25 12:50:11 PM PDT 24 92082716 ps
T113 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1671864682 Apr 25 12:50:31 PM PDT 24 Apr 25 12:50:34 PM PDT 24 87108623 ps
T551 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3482787822 Apr 25 12:50:31 PM PDT 24 Apr 25 12:50:34 PM PDT 24 88330408 ps
T552 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.373398148 Apr 25 12:50:20 PM PDT 24 Apr 25 12:50:26 PM PDT 24 228401185 ps
T135 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.875582570 Apr 25 12:50:14 PM PDT 24 Apr 25 12:50:22 PM PDT 24 1155534144 ps
T553 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3614667338 Apr 25 12:50:26 PM PDT 24 Apr 25 12:50:30 PM PDT 24 114859719 ps
T554 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.361402492 Apr 25 12:50:11 PM PDT 24 Apr 25 12:50:16 PM PDT 24 263198664 ps
T118 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4257820490 Apr 25 12:50:22 PM PDT 24 Apr 25 12:50:27 PM PDT 24 184788868 ps
T555 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3905571708 Apr 25 12:50:21 PM PDT 24 Apr 25 12:50:25 PM PDT 24 72442097 ps
T123 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3253603907 Apr 25 12:50:14 PM PDT 24 Apr 25 12:50:22 PM PDT 24 943699050 ps
T556 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1425506819 Apr 25 12:50:14 PM PDT 24 Apr 25 12:50:21 PM PDT 24 301239032 ps
T121 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1455579224 Apr 25 12:50:09 PM PDT 24 Apr 25 12:50:15 PM PDT 24 506703826 ps
T557 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.270268537 Apr 25 12:50:04 PM PDT 24 Apr 25 12:50:08 PM PDT 24 241417292 ps
T558 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4029844156 Apr 25 12:50:01 PM PDT 24 Apr 25 12:50:05 PM PDT 24 92652448 ps
T559 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.299707536 Apr 25 12:50:01 PM PDT 24 Apr 25 12:50:04 PM PDT 24 95237488 ps
T560 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3347343825 Apr 25 12:50:20 PM PDT 24 Apr 25 12:50:25 PM PDT 24 113243169 ps
T561 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3332725678 Apr 25 12:50:31 PM PDT 24 Apr 25 12:50:35 PM PDT 24 110539062 ps
T562 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.265456324 Apr 25 12:50:16 PM PDT 24 Apr 25 12:50:22 PM PDT 24 117499312 ps
T563 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3471602868 Apr 25 12:50:13 PM PDT 24 Apr 25 12:50:19 PM PDT 24 238484790 ps
T564 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2139230852 Apr 25 12:50:12 PM PDT 24 Apr 25 12:50:19 PM PDT 24 288620433 ps
T565 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3697643600 Apr 25 12:49:59 PM PDT 24 Apr 25 12:50:03 PM PDT 24 173275241 ps
T566 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.5498503 Apr 25 12:50:05 PM PDT 24 Apr 25 12:50:09 PM PDT 24 71826647 ps
T567 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1714623455 Apr 25 12:50:33 PM PDT 24 Apr 25 12:50:37 PM PDT 24 502277852 ps
T568 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2220685865 Apr 25 12:50:06 PM PDT 24 Apr 25 12:50:10 PM PDT 24 113321463 ps
T569 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1703950286 Apr 25 12:50:09 PM PDT 24 Apr 25 12:50:12 PM PDT 24 126448842 ps
T570 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1414225305 Apr 25 12:50:00 PM PDT 24 Apr 25 12:50:03 PM PDT 24 76870279 ps
T571 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2707734677 Apr 25 12:50:20 PM PDT 24 Apr 25 12:50:25 PM PDT 24 143828408 ps
T136 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3243192610 Apr 25 12:50:26 PM PDT 24 Apr 25 12:50:33 PM PDT 24 1513077019 ps
T572 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1459038198 Apr 25 12:50:10 PM PDT 24 Apr 25 12:50:15 PM PDT 24 210608507 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4254938610 Apr 25 12:49:59 PM PDT 24 Apr 25 12:50:03 PM PDT 24 100565937 ps
T574 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1255275751 Apr 25 12:50:22 PM PDT 24 Apr 25 12:50:26 PM PDT 24 145955149 ps
T575 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1125102836 Apr 25 12:50:35 PM PDT 24 Apr 25 12:50:38 PM PDT 24 117867365 ps
T576 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3388189130 Apr 25 12:50:11 PM PDT 24 Apr 25 12:50:17 PM PDT 24 268319374 ps
T577 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1426043950 Apr 25 12:50:09 PM PDT 24 Apr 25 12:50:13 PM PDT 24 96785492 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1704574988 Apr 25 12:50:15 PM PDT 24 Apr 25 12:50:21 PM PDT 24 124415417 ps
T579 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1734875226 Apr 25 12:50:34 PM PDT 24 Apr 25 12:50:38 PM PDT 24 814823116 ps
T580 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3335468443 Apr 25 12:49:53 PM PDT 24 Apr 25 12:49:55 PM PDT 24 124497208 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1704832381 Apr 25 12:49:59 PM PDT 24 Apr 25 12:50:02 PM PDT 24 185319026 ps
T582 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1957804879 Apr 25 12:50:22 PM PDT 24 Apr 25 12:50:27 PM PDT 24 534160943 ps
T120 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.217926840 Apr 25 12:50:34 PM PDT 24 Apr 25 12:50:39 PM PDT 24 892127545 ps
T583 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1524709727 Apr 25 12:50:31 PM PDT 24 Apr 25 12:50:34 PM PDT 24 180749042 ps
T584 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1672426739 Apr 25 12:49:54 PM PDT 24 Apr 25 12:50:01 PM PDT 24 795905484 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3383278033 Apr 25 12:50:03 PM PDT 24 Apr 25 12:50:07 PM PDT 24 136748140 ps
T586 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3168733878 Apr 25 12:49:54 PM PDT 24 Apr 25 12:49:58 PM PDT 24 76705571 ps
T587 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.4155123081 Apr 25 12:50:24 PM PDT 24 Apr 25 12:50:29 PM PDT 24 114583365 ps
T588 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3592633467 Apr 25 12:50:16 PM PDT 24 Apr 25 12:50:24 PM PDT 24 423209838 ps
T589 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.27028259 Apr 25 12:50:22 PM PDT 24 Apr 25 12:50:27 PM PDT 24 275246906 ps
T590 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2726243117 Apr 25 12:50:22 PM PDT 24 Apr 25 12:50:27 PM PDT 24 65527282 ps
T591 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1316357748 Apr 25 12:50:14 PM PDT 24 Apr 25 12:50:20 PM PDT 24 107609585 ps
T592 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2386862199 Apr 25 12:50:16 PM PDT 24 Apr 25 12:50:22 PM PDT 24 134414384 ps
T593 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2272444208 Apr 25 12:50:03 PM PDT 24 Apr 25 12:50:07 PM PDT 24 72201486 ps
T594 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4156040817 Apr 25 12:50:16 PM PDT 24 Apr 25 12:50:21 PM PDT 24 56147309 ps
T595 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2825156790 Apr 25 12:50:06 PM PDT 24 Apr 25 12:50:12 PM PDT 24 202399863 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2110428481 Apr 25 12:49:59 PM PDT 24 Apr 25 12:50:02 PM PDT 24 165776864 ps
T597 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2996444780 Apr 25 12:50:08 PM PDT 24 Apr 25 12:50:14 PM PDT 24 875252782 ps
T598 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2333980241 Apr 25 12:50:14 PM PDT 24 Apr 25 12:50:20 PM PDT 24 132733855 ps
T599 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2875970320 Apr 25 12:50:00 PM PDT 24 Apr 25 12:50:10 PM PDT 24 1545791152 ps
T600 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1015578716 Apr 25 12:50:13 PM PDT 24 Apr 25 12:50:19 PM PDT 24 214374532 ps
T601 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2401343040 Apr 25 12:50:13 PM PDT 24 Apr 25 12:50:19 PM PDT 24 223416534 ps
T122 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.791748432 Apr 25 12:50:00 PM PDT 24 Apr 25 12:50:04 PM PDT 24 434958273 ps
T124 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.120921306 Apr 25 12:50:24 PM PDT 24 Apr 25 12:50:31 PM PDT 24 896446620 ps
T602 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2651603185 Apr 25 12:50:11 PM PDT 24 Apr 25 12:50:16 PM PDT 24 125358559 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.339376352 Apr 25 12:50:08 PM PDT 24 Apr 25 12:50:11 PM PDT 24 136569039 ps
T119 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.880276877 Apr 25 12:50:14 PM PDT 24 Apr 25 12:50:21 PM PDT 24 789330095 ps
T604 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1083895351 Apr 25 12:50:18 PM PDT 24 Apr 25 12:50:24 PM PDT 24 207750064 ps
T605 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1742825842 Apr 25 12:50:07 PM PDT 24 Apr 25 12:50:11 PM PDT 24 212666239 ps
T606 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3698911861 Apr 25 12:50:20 PM PDT 24 Apr 25 12:50:25 PM PDT 24 82164734 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.100972875 Apr 25 12:50:03 PM PDT 24 Apr 25 12:50:08 PM PDT 24 317733828 ps
T608 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.46693217 Apr 25 12:50:23 PM PDT 24 Apr 25 12:50:27 PM PDT 24 57955021 ps
T609 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.179869745 Apr 25 12:50:14 PM PDT 24 Apr 25 12:50:22 PM PDT 24 781914861 ps
T610 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2354990968 Apr 25 12:50:20 PM PDT 24 Apr 25 12:50:30 PM PDT 24 481124596 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1112914497 Apr 25 12:50:17 PM PDT 24 Apr 25 12:50:23 PM PDT 24 201412084 ps
T612 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.838034109 Apr 25 12:50:11 PM PDT 24 Apr 25 12:50:16 PM PDT 24 77730130 ps
T613 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2202531388 Apr 25 12:50:21 PM PDT 24 Apr 25 12:50:27 PM PDT 24 492958838 ps
T614 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.741405570 Apr 25 12:50:23 PM PDT 24 Apr 25 12:50:28 PM PDT 24 209192407 ps
T615 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1471487522 Apr 25 12:50:10 PM PDT 24 Apr 25 12:50:13 PM PDT 24 105991497 ps
T616 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.731457110 Apr 25 12:50:16 PM PDT 24 Apr 25 12:50:21 PM PDT 24 57873093 ps
T617 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2390087383 Apr 25 12:50:14 PM PDT 24 Apr 25 12:50:20 PM PDT 24 164908519 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3668091618 Apr 25 12:50:27 PM PDT 24 Apr 25 12:50:31 PM PDT 24 270107931 ps
T619 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.554296047 Apr 25 12:50:10 PM PDT 24 Apr 25 12:50:16 PM PDT 24 403328633 ps
T620 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.956263510 Apr 25 12:50:16 PM PDT 24 Apr 25 12:50:21 PM PDT 24 126869201 ps

Test location /workspace/coverage/default/17.rstmgr_stress_all.3561153632
Short name T2
Test name
Test status
Simulation time 5236611726 ps
CPU time 22.9 seconds
Started Apr 25 12:57:54 PM PDT 24
Finished Apr 25 12:58:20 PM PDT 24
Peak memory 209348 kb
Host smart-b9aa8407-d4a3-4edc-b2e5-ba53c684da44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561153632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3561153632
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2176756167
Short name T48
Test name
Test status
Simulation time 523543850 ps
CPU time 2.63 seconds
Started Apr 25 12:57:47 PM PDT 24
Finished Apr 25 12:57:52 PM PDT 24
Peak memory 200796 kb
Host smart-f8553703-9e3b-49c5-9036-6ddc5e1aa533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176756167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2176756167
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.940228884
Short name T58
Test name
Test status
Simulation time 191441939 ps
CPU time 1.8 seconds
Started Apr 25 12:50:01 PM PDT 24
Finished Apr 25 12:50:05 PM PDT 24
Peak memory 209380 kb
Host smart-44b197a9-dfe1-4df4-99a9-c824351e517a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940228884 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.940228884
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3226239673
Short name T63
Test name
Test status
Simulation time 16647457356 ps
CPU time 25.18 seconds
Started Apr 25 12:57:15 PM PDT 24
Finished Apr 25 12:57:42 PM PDT 24
Peak memory 217628 kb
Host smart-d4bd7b17-a616-4a50-b4bf-fb38d44307f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226239673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3226239673
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2040159410
Short name T23
Test name
Test status
Simulation time 1902508603 ps
CPU time 7.08 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 218092 kb
Host smart-cf188cf5-638b-4f05-8e21-c011c151bd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040159410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2040159410
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1292589941
Short name T139
Test name
Test status
Simulation time 94897504 ps
CPU time 0.86 seconds
Started Apr 25 12:57:36 PM PDT 24
Finished Apr 25 12:57:39 PM PDT 24
Peak memory 200708 kb
Host smart-f2686bc1-e52c-4202-8802-081668effc23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292589941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1292589941
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4220046767
Short name T90
Test name
Test status
Simulation time 887864613 ps
CPU time 3.2 seconds
Started Apr 25 12:50:16 PM PDT 24
Finished Apr 25 12:50:24 PM PDT 24
Peak memory 201212 kb
Host smart-8d3541c5-85fb-4190-b1b7-3a59b23ce9c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220046767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.4220046767
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.412722067
Short name T36
Test name
Test status
Simulation time 112569701 ps
CPU time 1.05 seconds
Started Apr 25 12:58:08 PM PDT 24
Finished Apr 25 12:58:11 PM PDT 24
Peak memory 200888 kb
Host smart-9c433617-6484-4df3-83a7-e4709c85a302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412722067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.412722067
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1506165685
Short name T73
Test name
Test status
Simulation time 157446650 ps
CPU time 1.14 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 200896 kb
Host smart-782d5539-66ab-4842-993e-60b962e12cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506165685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1506165685
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3131131419
Short name T41
Test name
Test status
Simulation time 1890787587 ps
CPU time 7.4 seconds
Started Apr 25 12:57:13 PM PDT 24
Finished Apr 25 12:57:23 PM PDT 24
Peak memory 217936 kb
Host smart-ebd17bf5-78bf-433a-9609-34b76b48f46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131131419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3131131419
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3425461185
Short name T117
Test name
Test status
Simulation time 530790063 ps
CPU time 3.43 seconds
Started Apr 25 12:50:10 PM PDT 24
Finished Apr 25 12:50:16 PM PDT 24
Peak memory 212908 kb
Host smart-5db5c7ed-e80e-4392-82cc-b1d8beabdedb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425461185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3425461185
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.217926840
Short name T120
Test name
Test status
Simulation time 892127545 ps
CPU time 3.23 seconds
Started Apr 25 12:50:34 PM PDT 24
Finished Apr 25 12:50:39 PM PDT 24
Peak memory 201064 kb
Host smart-1a9b79f3-db74-4d2b-936e-abb07a649960
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217926840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.217926840
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2415700754
Short name T4
Test name
Test status
Simulation time 1519243706 ps
CPU time 5.21 seconds
Started Apr 25 12:57:09 PM PDT 24
Finished Apr 25 12:57:18 PM PDT 24
Peak memory 201076 kb
Host smart-bd83b312-001c-4998-aecc-26a207cc5819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415700754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2415700754
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3849162605
Short name T55
Test name
Test status
Simulation time 872446140 ps
CPU time 3.09 seconds
Started Apr 25 12:50:15 PM PDT 24
Finished Apr 25 12:50:22 PM PDT 24
Peak memory 201132 kb
Host smart-d9cb416f-daba-4292-b7f9-b4117f27af4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849162605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3849162605
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.694156014
Short name T111
Test name
Test status
Simulation time 226156165 ps
CPU time 1.49 seconds
Started Apr 25 12:50:03 PM PDT 24
Finished Apr 25 12:50:08 PM PDT 24
Peak memory 201140 kb
Host smart-e8467a3a-9068-4d81-b124-ae1580fd102d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694156014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.694156014
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1333300231
Short name T7
Test name
Test status
Simulation time 190523638 ps
CPU time 0.88 seconds
Started Apr 25 12:57:55 PM PDT 24
Finished Apr 25 12:57:59 PM PDT 24
Peak memory 200704 kb
Host smart-d49a1839-063f-416f-8c88-e22f0c372b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333300231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1333300231
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1880844837
Short name T179
Test name
Test status
Simulation time 244525769 ps
CPU time 1.1 seconds
Started Apr 25 12:57:15 PM PDT 24
Finished Apr 25 12:57:19 PM PDT 24
Peak memory 218100 kb
Host smart-ad78b61c-cc84-4f7c-8cf5-0ac8d5632c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880844837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1880844837
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3253603907
Short name T123
Test name
Test status
Simulation time 943699050 ps
CPU time 3.03 seconds
Started Apr 25 12:50:14 PM PDT 24
Finished Apr 25 12:50:22 PM PDT 24
Peak memory 201044 kb
Host smart-875a5d32-0101-4483-b56b-7f3cc023a03c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253603907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3253603907
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.270268537
Short name T557
Test name
Test status
Simulation time 241417292 ps
CPU time 1.67 seconds
Started Apr 25 12:50:04 PM PDT 24
Finished Apr 25 12:50:08 PM PDT 24
Peak memory 201116 kb
Host smart-d52b7402-9eba-4ea9-8ef9-8d83cd8f3029
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270268537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.270268537
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3767469605
Short name T545
Test name
Test status
Simulation time 266113503 ps
CPU time 2.97 seconds
Started Apr 25 12:50:19 PM PDT 24
Finished Apr 25 12:50:26 PM PDT 24
Peak memory 200852 kb
Host smart-28a4bd6c-86a4-4de0-92f8-42b18e86c832
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767469605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
767469605
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.644500994
Short name T546
Test name
Test status
Simulation time 187533361 ps
CPU time 1 seconds
Started Apr 25 12:49:53 PM PDT 24
Finished Apr 25 12:49:56 PM PDT 24
Peak memory 200676 kb
Host smart-404b4abf-208a-4823-80ee-467e63fb5f0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644500994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.644500994
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.956263510
Short name T620
Test name
Test status
Simulation time 126869201 ps
CPU time 0.99 seconds
Started Apr 25 12:50:16 PM PDT 24
Finished Apr 25 12:50:21 PM PDT 24
Peak memory 200900 kb
Host smart-8e2c23e0-ecbf-4632-90f9-5a2d7461d1df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956263510 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.956263510
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2272444208
Short name T593
Test name
Test status
Simulation time 72201486 ps
CPU time 0.82 seconds
Started Apr 25 12:50:03 PM PDT 24
Finished Apr 25 12:50:07 PM PDT 24
Peak memory 200816 kb
Host smart-7aceea1b-01d1-4324-bd29-e25ee4c5e2ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272444208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2272444208
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1704832381
Short name T581
Test name
Test status
Simulation time 185319026 ps
CPU time 1.39 seconds
Started Apr 25 12:49:59 PM PDT 24
Finished Apr 25 12:50:02 PM PDT 24
Peak memory 201064 kb
Host smart-81ed36db-d496-4d73-884f-2d359a954ba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704832381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1704832381
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1112914497
Short name T611
Test name
Test status
Simulation time 201412084 ps
CPU time 1.46 seconds
Started Apr 25 12:50:17 PM PDT 24
Finished Apr 25 12:50:23 PM PDT 24
Peak memory 209068 kb
Host smart-751fed45-69c6-467e-8938-f69b2211656a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112914497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1112914497
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.289143133
Short name T62
Test name
Test status
Simulation time 920537194 ps
CPU time 3.24 seconds
Started Apr 25 12:50:00 PM PDT 24
Finished Apr 25 12:50:06 PM PDT 24
Peak memory 201072 kb
Host smart-1f24acbf-816a-405a-9c5e-28853f3aed5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289143133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
289143133
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.278728354
Short name T60
Test name
Test status
Simulation time 202453667 ps
CPU time 1.6 seconds
Started Apr 25 12:50:01 PM PDT 24
Finished Apr 25 12:50:05 PM PDT 24
Peak memory 209292 kb
Host smart-28293c08-6d70-4673-ad85-db1483be9fd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278728354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.278728354
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1672426739
Short name T584
Test name
Test status
Simulation time 795905484 ps
CPU time 4.48 seconds
Started Apr 25 12:49:54 PM PDT 24
Finished Apr 25 12:50:01 PM PDT 24
Peak memory 201004 kb
Host smart-fd26e565-39aa-4b06-88cf-44ab97f4f7ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672426739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
672426739
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4029844156
Short name T558
Test name
Test status
Simulation time 92652448 ps
CPU time 0.83 seconds
Started Apr 25 12:50:01 PM PDT 24
Finished Apr 25 12:50:05 PM PDT 24
Peak memory 200780 kb
Host smart-66f2be25-05a3-46b8-95b7-0220f989a75e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029844156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
029844156
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3168733878
Short name T586
Test name
Test status
Simulation time 76705571 ps
CPU time 0.76 seconds
Started Apr 25 12:49:54 PM PDT 24
Finished Apr 25 12:49:58 PM PDT 24
Peak memory 200876 kb
Host smart-60399d74-6ac8-454f-b256-443bd29dd7c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168733878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3168733878
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3383278033
Short name T585
Test name
Test status
Simulation time 136748140 ps
CPU time 1.32 seconds
Started Apr 25 12:50:03 PM PDT 24
Finished Apr 25 12:50:07 PM PDT 24
Peak memory 201008 kb
Host smart-aedfe73f-a7a6-4042-9660-6ed6da2e8d91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383278033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3383278033
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4254938610
Short name T573
Test name
Test status
Simulation time 100565937 ps
CPU time 1.43 seconds
Started Apr 25 12:49:59 PM PDT 24
Finished Apr 25 12:50:03 PM PDT 24
Peak memory 209272 kb
Host smart-0e9d86bc-b7ca-49ce-9f0e-341f878df0b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254938610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.4254938610
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2996444780
Short name T597
Test name
Test status
Simulation time 875252782 ps
CPU time 3.05 seconds
Started Apr 25 12:50:08 PM PDT 24
Finished Apr 25 12:50:14 PM PDT 24
Peak memory 200968 kb
Host smart-bd977343-35e7-4085-b1ec-0cd4d54958c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996444780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2996444780
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1524709727
Short name T583
Test name
Test status
Simulation time 180749042 ps
CPU time 1.22 seconds
Started Apr 25 12:50:31 PM PDT 24
Finished Apr 25 12:50:34 PM PDT 24
Peak memory 210540 kb
Host smart-776720e9-5c54-41a3-a86f-79d5f0e4ba59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524709727 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1524709727
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3482787822
Short name T551
Test name
Test status
Simulation time 88330408 ps
CPU time 0.89 seconds
Started Apr 25 12:50:31 PM PDT 24
Finished Apr 25 12:50:34 PM PDT 24
Peak memory 200856 kb
Host smart-c9f759bb-6603-44df-8951-f4731a792222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482787822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3482787822
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.27028259
Short name T589
Test name
Test status
Simulation time 275246906 ps
CPU time 1.64 seconds
Started Apr 25 12:50:22 PM PDT 24
Finished Apr 25 12:50:27 PM PDT 24
Peak memory 201040 kb
Host smart-b80eadb8-341a-4f3f-80aa-b20a205992c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27028259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sam
e_csr_outstanding.27028259
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.814628266
Short name T61
Test name
Test status
Simulation time 95235613 ps
CPU time 1.37 seconds
Started Apr 25 12:50:10 PM PDT 24
Finished Apr 25 12:50:14 PM PDT 24
Peak memory 209216 kb
Host smart-11530cdc-2aed-408b-85b0-9c20a7884e40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814628266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.814628266
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3362500032
Short name T134
Test name
Test status
Simulation time 945992116 ps
CPU time 3.56 seconds
Started Apr 25 12:50:16 PM PDT 24
Finished Apr 25 12:50:24 PM PDT 24
Peak memory 201128 kb
Host smart-44caf587-8fbc-46f3-8765-a719028eb0ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362500032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3362500032
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1448176697
Short name T92
Test name
Test status
Simulation time 167496220 ps
CPU time 1.1 seconds
Started Apr 25 12:50:22 PM PDT 24
Finished Apr 25 12:50:27 PM PDT 24
Peak memory 209212 kb
Host smart-a2ae5690-06c5-4b15-9ebd-325018a89421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448176697 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1448176697
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.838034109
Short name T612
Test name
Test status
Simulation time 77730130 ps
CPU time 0.87 seconds
Started Apr 25 12:50:11 PM PDT 24
Finished Apr 25 12:50:16 PM PDT 24
Peak memory 200844 kb
Host smart-334e4199-06d2-48f4-ad15-e15c94359fb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838034109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.838034109
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1125102836
Short name T575
Test name
Test status
Simulation time 117867365 ps
CPU time 1.39 seconds
Started Apr 25 12:50:35 PM PDT 24
Finished Apr 25 12:50:38 PM PDT 24
Peak memory 200984 kb
Host smart-e6fccbb0-6b58-4fde-9baf-249539bbb31c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125102836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1125102836
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3388189130
Short name T576
Test name
Test status
Simulation time 268319374 ps
CPU time 2.14 seconds
Started Apr 25 12:50:11 PM PDT 24
Finished Apr 25 12:50:17 PM PDT 24
Peak memory 209320 kb
Host smart-5acfbc30-a772-4ae7-8a5d-b94ae89d2273
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388189130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3388189130
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1714623455
Short name T567
Test name
Test status
Simulation time 502277852 ps
CPU time 2.01 seconds
Started Apr 25 12:50:33 PM PDT 24
Finished Apr 25 12:50:37 PM PDT 24
Peak memory 201008 kb
Host smart-ee3e89a9-6bcd-438d-9fea-2b0d6920e935
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714623455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1714623455
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.310139256
Short name T86
Test name
Test status
Simulation time 111748179 ps
CPU time 0.92 seconds
Started Apr 25 12:50:20 PM PDT 24
Finished Apr 25 12:50:25 PM PDT 24
Peak memory 200888 kb
Host smart-ec521066-00ad-4f1d-8f9c-5d95dc9a7ae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310139256 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.310139256
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3470241556
Short name T547
Test name
Test status
Simulation time 83235382 ps
CPU time 0.89 seconds
Started Apr 25 12:50:04 PM PDT 24
Finished Apr 25 12:50:08 PM PDT 24
Peak memory 200804 kb
Host smart-d6fde0e0-b68a-4243-b6c1-b20294d09cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470241556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3470241556
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.361402492
Short name T554
Test name
Test status
Simulation time 263198664 ps
CPU time 1.54 seconds
Started Apr 25 12:50:11 PM PDT 24
Finished Apr 25 12:50:16 PM PDT 24
Peak memory 201088 kb
Host smart-a673b0c9-73df-47a0-b208-9b723f8b0001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361402492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.361402492
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.554296047
Short name T619
Test name
Test status
Simulation time 403328633 ps
CPU time 2.8 seconds
Started Apr 25 12:50:10 PM PDT 24
Finished Apr 25 12:50:16 PM PDT 24
Peak memory 208496 kb
Host smart-d5b8adb5-c9bc-4a46-9a8a-bfe3ae0e102e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554296047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.554296047
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3243192610
Short name T136
Test name
Test status
Simulation time 1513077019 ps
CPU time 4.24 seconds
Started Apr 25 12:50:26 PM PDT 24
Finished Apr 25 12:50:33 PM PDT 24
Peak memory 201108 kb
Host smart-8c8d9364-fb95-4bb5-817a-863fbd5fcf92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243192610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3243192610
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2844894310
Short name T88
Test name
Test status
Simulation time 121373125 ps
CPU time 1.04 seconds
Started Apr 25 12:50:21 PM PDT 24
Finished Apr 25 12:50:26 PM PDT 24
Peak memory 201140 kb
Host smart-840ef18c-63c5-480c-8115-b3f3c9e78f7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844894310 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2844894310
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.46693217
Short name T608
Test name
Test status
Simulation time 57955021 ps
CPU time 0.76 seconds
Started Apr 25 12:50:23 PM PDT 24
Finished Apr 25 12:50:27 PM PDT 24
Peak memory 200804 kb
Host smart-aa202b11-36ac-47fd-b1db-1562a00014e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46693217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.46693217
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2401343040
Short name T601
Test name
Test status
Simulation time 223416534 ps
CPU time 1.51 seconds
Started Apr 25 12:50:13 PM PDT 24
Finished Apr 25 12:50:19 PM PDT 24
Peak memory 201052 kb
Host smart-665f097f-067e-48cd-b254-0b70336d92b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401343040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2401343040
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.100972875
Short name T607
Test name
Test status
Simulation time 317733828 ps
CPU time 2.2 seconds
Started Apr 25 12:50:03 PM PDT 24
Finished Apr 25 12:50:08 PM PDT 24
Peak memory 217380 kb
Host smart-bdede9fb-14d4-426b-9d9b-fdb34b32cd4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100972875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.100972875
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2831452068
Short name T87
Test name
Test status
Simulation time 131036766 ps
CPU time 1.11 seconds
Started Apr 25 12:50:12 PM PDT 24
Finished Apr 25 12:50:18 PM PDT 24
Peak memory 200952 kb
Host smart-340bf9de-e337-4934-8c69-954e067d5075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831452068 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2831452068
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4156040817
Short name T594
Test name
Test status
Simulation time 56147309 ps
CPU time 0.77 seconds
Started Apr 25 12:50:16 PM PDT 24
Finished Apr 25 12:50:21 PM PDT 24
Peak memory 200888 kb
Host smart-b2b455d7-9624-4b34-8a22-d7b7346e771b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156040817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.4156040817
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2390087383
Short name T617
Test name
Test status
Simulation time 164908519 ps
CPU time 1.17 seconds
Started Apr 25 12:50:14 PM PDT 24
Finished Apr 25 12:50:20 PM PDT 24
Peak memory 200892 kb
Host smart-2687b27a-ce64-45b5-a254-f3abc318ce5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390087383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2390087383
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3332725678
Short name T561
Test name
Test status
Simulation time 110539062 ps
CPU time 1.36 seconds
Started Apr 25 12:50:31 PM PDT 24
Finished Apr 25 12:50:35 PM PDT 24
Peak memory 201020 kb
Host smart-2abdce43-a95f-499a-abdd-d31660073182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332725678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3332725678
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2386862199
Short name T592
Test name
Test status
Simulation time 134414384 ps
CPU time 1.31 seconds
Started Apr 25 12:50:16 PM PDT 24
Finished Apr 25 12:50:22 PM PDT 24
Peak memory 209104 kb
Host smart-ccfdac79-45f0-4045-829f-adb3d5aeb74b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386862199 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2386862199
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2726243117
Short name T590
Test name
Test status
Simulation time 65527282 ps
CPU time 0.78 seconds
Started Apr 25 12:50:22 PM PDT 24
Finished Apr 25 12:50:27 PM PDT 24
Peak memory 200704 kb
Host smart-a577c9db-fa04-4d9d-b6c5-a703048cf1fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726243117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2726243117
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.373398148
Short name T552
Test name
Test status
Simulation time 228401185 ps
CPU time 1.55 seconds
Started Apr 25 12:50:20 PM PDT 24
Finished Apr 25 12:50:26 PM PDT 24
Peak memory 200988 kb
Host smart-4addeed1-7a31-4ccb-94aa-d97afa56e103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373398148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.373398148
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.179869745
Short name T609
Test name
Test status
Simulation time 781914861 ps
CPU time 2.94 seconds
Started Apr 25 12:50:14 PM PDT 24
Finished Apr 25 12:50:22 PM PDT 24
Peak memory 201192 kb
Host smart-d77775e8-c91e-49c6-a701-bfa3e6309ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179869745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.179869745
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1083895351
Short name T604
Test name
Test status
Simulation time 207750064 ps
CPU time 1.37 seconds
Started Apr 25 12:50:18 PM PDT 24
Finished Apr 25 12:50:24 PM PDT 24
Peak memory 200988 kb
Host smart-c9882dc2-46ea-46db-ac82-79a1d87760ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083895351 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1083895351
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1220532945
Short name T550
Test name
Test status
Simulation time 92082716 ps
CPU time 0.84 seconds
Started Apr 25 12:50:08 PM PDT 24
Finished Apr 25 12:50:11 PM PDT 24
Peak memory 200852 kb
Host smart-c57ed3fe-39fd-429e-8067-7e8e2fdb52c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220532945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1220532945
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2333980241
Short name T598
Test name
Test status
Simulation time 132733855 ps
CPU time 1.18 seconds
Started Apr 25 12:50:14 PM PDT 24
Finished Apr 25 12:50:20 PM PDT 24
Peak memory 201120 kb
Host smart-45b24865-1cbf-4279-960d-b143b0b983e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333980241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2333980241
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3697643600
Short name T565
Test name
Test status
Simulation time 173275241 ps
CPU time 2.5 seconds
Started Apr 25 12:49:59 PM PDT 24
Finished Apr 25 12:50:03 PM PDT 24
Peak memory 209332 kb
Host smart-83cda249-25bc-4265-8d06-d1388ec086ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697643600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3697643600
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.265456324
Short name T562
Test name
Test status
Simulation time 117499312 ps
CPU time 1.37 seconds
Started Apr 25 12:50:16 PM PDT 24
Finished Apr 25 12:50:22 PM PDT 24
Peak memory 209228 kb
Host smart-8a4ba3cb-3de7-48a9-8509-7b7c6b451598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265456324 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.265456324
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3698911861
Short name T606
Test name
Test status
Simulation time 82164734 ps
CPU time 0.84 seconds
Started Apr 25 12:50:20 PM PDT 24
Finished Apr 25 12:50:25 PM PDT 24
Peak memory 200792 kb
Host smart-e049f798-0d48-4a0e-83ea-7ee62354ab16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698911861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3698911861
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3592633467
Short name T588
Test name
Test status
Simulation time 423209838 ps
CPU time 3.1 seconds
Started Apr 25 12:50:16 PM PDT 24
Finished Apr 25 12:50:24 PM PDT 24
Peak memory 217448 kb
Host smart-88934f1a-52e6-4925-bdc9-8f76f77c4947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592633467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3592633467
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1957804879
Short name T582
Test name
Test status
Simulation time 534160943 ps
CPU time 1.92 seconds
Started Apr 25 12:50:22 PM PDT 24
Finished Apr 25 12:50:27 PM PDT 24
Peak memory 201140 kb
Host smart-1c95eb85-2f6b-4b41-83d6-10a0b2e3b654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957804879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1957804879
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2707734677
Short name T571
Test name
Test status
Simulation time 143828408 ps
CPU time 1.12 seconds
Started Apr 25 12:50:20 PM PDT 24
Finished Apr 25 12:50:25 PM PDT 24
Peak memory 209108 kb
Host smart-2ab0f632-d26e-4fb3-a512-da5ab7a379b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707734677 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2707734677
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.731457110
Short name T616
Test name
Test status
Simulation time 57873093 ps
CPU time 0.75 seconds
Started Apr 25 12:50:16 PM PDT 24
Finished Apr 25 12:50:21 PM PDT 24
Peak memory 200736 kb
Host smart-949b99f5-8424-49da-8f92-5afde7ff47b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731457110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.731457110
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.741405570
Short name T614
Test name
Test status
Simulation time 209192407 ps
CPU time 1.45 seconds
Started Apr 25 12:50:23 PM PDT 24
Finished Apr 25 12:50:28 PM PDT 24
Peak memory 201096 kb
Host smart-a551539f-00bc-47ab-8f2d-f002b4245b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741405570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.741405570
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3347343825
Short name T560
Test name
Test status
Simulation time 113243169 ps
CPU time 1.61 seconds
Started Apr 25 12:50:20 PM PDT 24
Finished Apr 25 12:50:25 PM PDT 24
Peak memory 212140 kb
Host smart-b9157ac8-6296-490f-b610-a7f870f38b26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347343825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3347343825
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1734875226
Short name T579
Test name
Test status
Simulation time 814823116 ps
CPU time 2.79 seconds
Started Apr 25 12:50:34 PM PDT 24
Finished Apr 25 12:50:38 PM PDT 24
Peak memory 201144 kb
Host smart-2fa05bd7-39c9-4564-ac97-a46882b65575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734875226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1734875226
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1426043950
Short name T577
Test name
Test status
Simulation time 96785492 ps
CPU time 0.9 seconds
Started Apr 25 12:50:09 PM PDT 24
Finished Apr 25 12:50:13 PM PDT 24
Peak memory 200940 kb
Host smart-aa07d147-044f-4c3b-8059-c1dd04665e7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426043950 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1426043950
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3905571708
Short name T555
Test name
Test status
Simulation time 72442097 ps
CPU time 0.77 seconds
Started Apr 25 12:50:21 PM PDT 24
Finished Apr 25 12:50:25 PM PDT 24
Peak memory 200844 kb
Host smart-38183787-b000-4da4-89e8-f0a6edcb00a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905571708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3905571708
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1722604098
Short name T105
Test name
Test status
Simulation time 81581159 ps
CPU time 0.97 seconds
Started Apr 25 12:50:22 PM PDT 24
Finished Apr 25 12:50:26 PM PDT 24
Peak memory 200868 kb
Host smart-47f99178-da54-421f-b0e1-bf241ae5a25f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722604098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1722604098
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4257820490
Short name T118
Test name
Test status
Simulation time 184788868 ps
CPU time 1.65 seconds
Started Apr 25 12:50:22 PM PDT 24
Finished Apr 25 12:50:27 PM PDT 24
Peak memory 216788 kb
Host smart-3479ebdd-ea1f-42f4-8535-9a7181a6dd00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257820490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4257820490
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2202531388
Short name T613
Test name
Test status
Simulation time 492958838 ps
CPU time 1.88 seconds
Started Apr 25 12:50:21 PM PDT 24
Finished Apr 25 12:50:27 PM PDT 24
Peak memory 201088 kb
Host smart-165c0817-b152-4f3d-8a5e-5412d7d1dab5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202531388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2202531388
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2110428481
Short name T596
Test name
Test status
Simulation time 165776864 ps
CPU time 1.96 seconds
Started Apr 25 12:49:59 PM PDT 24
Finished Apr 25 12:50:02 PM PDT 24
Peak memory 201032 kb
Host smart-6639c24c-4ada-473c-8237-c8fa280d2d9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110428481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
110428481
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2354990968
Short name T610
Test name
Test status
Simulation time 481124596 ps
CPU time 5.67 seconds
Started Apr 25 12:50:20 PM PDT 24
Finished Apr 25 12:50:30 PM PDT 24
Peak memory 201036 kb
Host smart-d2c9a8ed-8105-4ed0-b7c5-6208998511e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354990968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
354990968
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1316357748
Short name T591
Test name
Test status
Simulation time 107609585 ps
CPU time 0.88 seconds
Started Apr 25 12:50:14 PM PDT 24
Finished Apr 25 12:50:20 PM PDT 24
Peak memory 200808 kb
Host smart-09f1cd88-a538-406b-b944-0fad2c64c229
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316357748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
316357748
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1703950286
Short name T569
Test name
Test status
Simulation time 126448842 ps
CPU time 1.08 seconds
Started Apr 25 12:50:09 PM PDT 24
Finished Apr 25 12:50:12 PM PDT 24
Peak memory 209260 kb
Host smart-137469b9-685f-4905-b15b-38b68cef4ad4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703950286 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1703950286
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.367520874
Short name T56
Test name
Test status
Simulation time 60746131 ps
CPU time 0.83 seconds
Started Apr 25 12:50:15 PM PDT 24
Finished Apr 25 12:50:20 PM PDT 24
Peak memory 200808 kb
Host smart-ce959c74-3896-43b4-9027-813a5ab61f18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367520874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.367520874
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3768842536
Short name T110
Test name
Test status
Simulation time 92240518 ps
CPU time 1.08 seconds
Started Apr 25 12:49:53 PM PDT 24
Finished Apr 25 12:49:56 PM PDT 24
Peak memory 201020 kb
Host smart-bcc1157d-b8e1-4690-a6b3-bd4edbb5bfd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768842536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3768842536
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2825156790
Short name T595
Test name
Test status
Simulation time 202399863 ps
CPU time 2.84 seconds
Started Apr 25 12:50:06 PM PDT 24
Finished Apr 25 12:50:12 PM PDT 24
Peak memory 209300 kb
Host smart-200882b4-3b90-4f8e-9eb1-c37cd8e1c714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825156790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2825156790
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.791748432
Short name T122
Test name
Test status
Simulation time 434958273 ps
CPU time 1.78 seconds
Started Apr 25 12:50:00 PM PDT 24
Finished Apr 25 12:50:04 PM PDT 24
Peak memory 200684 kb
Host smart-3c364c36-a655-42ae-9ff0-73b15857e0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791748432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
791748432
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3266508214
Short name T548
Test name
Test status
Simulation time 417036210 ps
CPU time 2.48 seconds
Started Apr 25 12:50:39 PM PDT 24
Finished Apr 25 12:50:42 PM PDT 24
Peak memory 200996 kb
Host smart-30a8b313-23be-4013-984c-fc4ba1cfdbf9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266508214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
266508214
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2875970320
Short name T599
Test name
Test status
Simulation time 1545791152 ps
CPU time 7.65 seconds
Started Apr 25 12:50:00 PM PDT 24
Finished Apr 25 12:50:10 PM PDT 24
Peak memory 200620 kb
Host smart-8a95bfbe-2093-4266-80db-aedc82dd5963
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875970320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
875970320
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1704574988
Short name T578
Test name
Test status
Simulation time 124415417 ps
CPU time 0.92 seconds
Started Apr 25 12:50:15 PM PDT 24
Finished Apr 25 12:50:21 PM PDT 24
Peak memory 200860 kb
Host smart-96cde45e-4626-460f-9701-a070928ebe52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704574988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
704574988
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.299707536
Short name T559
Test name
Test status
Simulation time 95237488 ps
CPU time 0.87 seconds
Started Apr 25 12:50:01 PM PDT 24
Finished Apr 25 12:50:04 PM PDT 24
Peak memory 201020 kb
Host smart-d48bb9ae-71e7-4132-96a5-2fe160376f79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299707536 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.299707536
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.5498503
Short name T566
Test name
Test status
Simulation time 71826647 ps
CPU time 0.82 seconds
Started Apr 25 12:50:05 PM PDT 24
Finished Apr 25 12:50:09 PM PDT 24
Peak memory 200824 kb
Host smart-9c060b4d-a535-4867-85b7-9e86f491c249
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5498503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.5498503
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3614667338
Short name T553
Test name
Test status
Simulation time 114859719 ps
CPU time 1.25 seconds
Started Apr 25 12:50:26 PM PDT 24
Finished Apr 25 12:50:30 PM PDT 24
Peak memory 201204 kb
Host smart-5486084d-3b1c-413d-8172-49ffcf5bd7f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614667338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3614667338
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1425506819
Short name T556
Test name
Test status
Simulation time 301239032 ps
CPU time 2.21 seconds
Started Apr 25 12:50:14 PM PDT 24
Finished Apr 25 12:50:21 PM PDT 24
Peak memory 217456 kb
Host smart-243a39b9-3718-45e8-a34e-8943175f0520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425506819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1425506819
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.362407107
Short name T89
Test name
Test status
Simulation time 506196129 ps
CPU time 2.08 seconds
Started Apr 25 12:50:00 PM PDT 24
Finished Apr 25 12:50:04 PM PDT 24
Peak memory 201012 kb
Host smart-04331f84-4ec5-4ec4-87fc-27b98fcd10d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362407107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
362407107
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1459038198
Short name T572
Test name
Test status
Simulation time 210608507 ps
CPU time 1.5 seconds
Started Apr 25 12:50:10 PM PDT 24
Finished Apr 25 12:50:15 PM PDT 24
Peak memory 200944 kb
Host smart-f0ffe62e-17d8-4644-8add-b49fccd9661b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459038198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
459038198
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3785444809
Short name T544
Test name
Test status
Simulation time 1542869194 ps
CPU time 8.11 seconds
Started Apr 25 12:50:15 PM PDT 24
Finished Apr 25 12:50:27 PM PDT 24
Peak memory 217376 kb
Host smart-46d6c7e3-b619-448b-869c-3937b4a892c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785444809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
785444809
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3335468443
Short name T580
Test name
Test status
Simulation time 124497208 ps
CPU time 0.86 seconds
Started Apr 25 12:49:53 PM PDT 24
Finished Apr 25 12:49:55 PM PDT 24
Peak memory 200804 kb
Host smart-5f8a0d56-8f8c-4135-8375-eb2ab1af4647
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335468443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
335468443
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1471487522
Short name T615
Test name
Test status
Simulation time 105991497 ps
CPU time 0.89 seconds
Started Apr 25 12:50:10 PM PDT 24
Finished Apr 25 12:50:13 PM PDT 24
Peak memory 200944 kb
Host smart-3087b19f-c918-4bb6-be28-a971beed3869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471487522 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1471487522
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1414225305
Short name T570
Test name
Test status
Simulation time 76870279 ps
CPU time 0.87 seconds
Started Apr 25 12:50:00 PM PDT 24
Finished Apr 25 12:50:03 PM PDT 24
Peak memory 200888 kb
Host smart-29c07c8c-b8e8-4453-b0cd-b89168617844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414225305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1414225305
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1255275751
Short name T574
Test name
Test status
Simulation time 145955149 ps
CPU time 1.09 seconds
Started Apr 25 12:50:22 PM PDT 24
Finished Apr 25 12:50:26 PM PDT 24
Peak memory 200920 kb
Host smart-37239fd3-f360-4fc5-a7cc-4092a346b803
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255275751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1255275751
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3668091618
Short name T618
Test name
Test status
Simulation time 270107931 ps
CPU time 1.78 seconds
Started Apr 25 12:50:27 PM PDT 24
Finished Apr 25 12:50:31 PM PDT 24
Peak memory 217580 kb
Host smart-1d025695-10b5-4c8e-9df9-bb72c2f862d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668091618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3668091618
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.880276877
Short name T119
Test name
Test status
Simulation time 789330095 ps
CPU time 2.89 seconds
Started Apr 25 12:50:14 PM PDT 24
Finished Apr 25 12:50:21 PM PDT 24
Peak memory 201168 kb
Host smart-1d4db6ec-1a45-402b-986c-5957bb9574ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880276877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
880276877
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.339376352
Short name T603
Test name
Test status
Simulation time 136569039 ps
CPU time 1.37 seconds
Started Apr 25 12:50:08 PM PDT 24
Finished Apr 25 12:50:11 PM PDT 24
Peak memory 209372 kb
Host smart-11b7ed8d-05e5-46ff-988f-68ad2b2000ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339376352 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.339376352
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.262739435
Short name T108
Test name
Test status
Simulation time 60242336 ps
CPU time 0.76 seconds
Started Apr 25 12:50:01 PM PDT 24
Finished Apr 25 12:50:05 PM PDT 24
Peak memory 200740 kb
Host smart-3702b140-c4ef-4e59-b650-33b20206b648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262739435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.262739435
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2651603185
Short name T602
Test name
Test status
Simulation time 125358559 ps
CPU time 1.07 seconds
Started Apr 25 12:50:11 PM PDT 24
Finished Apr 25 12:50:16 PM PDT 24
Peak memory 200840 kb
Host smart-cebda3da-4963-4be3-82a0-0d0487d789b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651603185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2651603185
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.4155123081
Short name T587
Test name
Test status
Simulation time 114583365 ps
CPU time 1.46 seconds
Started Apr 25 12:50:24 PM PDT 24
Finished Apr 25 12:50:29 PM PDT 24
Peak memory 217396 kb
Host smart-1eeda691-1f5c-4eb0-a424-054d96055ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155123081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.4155123081
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1192754320
Short name T57
Test name
Test status
Simulation time 144900484 ps
CPU time 1.27 seconds
Started Apr 25 12:50:09 PM PDT 24
Finished Apr 25 12:50:13 PM PDT 24
Peak memory 209140 kb
Host smart-01e39cad-2955-472a-a53a-84e0777becf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192754320 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1192754320
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3659857361
Short name T549
Test name
Test status
Simulation time 64824106 ps
CPU time 0.77 seconds
Started Apr 25 12:50:11 PM PDT 24
Finished Apr 25 12:50:15 PM PDT 24
Peak memory 200884 kb
Host smart-92729744-1911-4f97-a22e-717f73dddd32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659857361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3659857361
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3471602868
Short name T563
Test name
Test status
Simulation time 238484790 ps
CPU time 1.56 seconds
Started Apr 25 12:50:13 PM PDT 24
Finished Apr 25 12:50:19 PM PDT 24
Peak memory 201088 kb
Host smart-3f46a408-9f11-48c7-91fe-f4985f05c7ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471602868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3471602868
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1455579224
Short name T121
Test name
Test status
Simulation time 506703826 ps
CPU time 3.67 seconds
Started Apr 25 12:50:09 PM PDT 24
Finished Apr 25 12:50:15 PM PDT 24
Peak memory 209372 kb
Host smart-4fbab267-147b-4041-a0e8-7723b16853c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455579224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1455579224
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.875582570
Short name T135
Test name
Test status
Simulation time 1155534144 ps
CPU time 3.48 seconds
Started Apr 25 12:50:14 PM PDT 24
Finished Apr 25 12:50:22 PM PDT 24
Peak memory 201096 kb
Host smart-cb4a6a65-ef73-4d89-8cfb-80f8a0b350bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875582570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
875582570
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1742825842
Short name T605
Test name
Test status
Simulation time 212666239 ps
CPU time 1.25 seconds
Started Apr 25 12:50:07 PM PDT 24
Finished Apr 25 12:50:11 PM PDT 24
Peak memory 209068 kb
Host smart-a21b1bad-d36d-4a29-95dc-e36e2b3456cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742825842 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1742825842
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1671864682
Short name T113
Test name
Test status
Simulation time 87108623 ps
CPU time 0.89 seconds
Started Apr 25 12:50:31 PM PDT 24
Finished Apr 25 12:50:34 PM PDT 24
Peak memory 200768 kb
Host smart-64053a85-e4f0-475f-860b-283b1c3f4cfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671864682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1671864682
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1314475842
Short name T107
Test name
Test status
Simulation time 79743954 ps
CPU time 0.95 seconds
Started Apr 25 12:50:17 PM PDT 24
Finished Apr 25 12:50:22 PM PDT 24
Peak memory 200852 kb
Host smart-401e354a-f1e9-4eae-8c5f-7904cdcc9d31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314475842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1314475842
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3653253175
Short name T115
Test name
Test status
Simulation time 341952229 ps
CPU time 2.19 seconds
Started Apr 25 12:50:18 PM PDT 24
Finished Apr 25 12:50:25 PM PDT 24
Peak memory 209224 kb
Host smart-18ba373d-1feb-44ee-8245-0f6f56b4e704
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653253175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3653253175
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.120921306
Short name T124
Test name
Test status
Simulation time 896446620 ps
CPU time 3.09 seconds
Started Apr 25 12:50:24 PM PDT 24
Finished Apr 25 12:50:31 PM PDT 24
Peak memory 201048 kb
Host smart-168344e9-cd4b-4a01-8f97-64d7cd60c2c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120921306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
120921306
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1015578716
Short name T600
Test name
Test status
Simulation time 214374532 ps
CPU time 1.46 seconds
Started Apr 25 12:50:13 PM PDT 24
Finished Apr 25 12:50:19 PM PDT 24
Peak memory 209080 kb
Host smart-aebe5e59-e446-439c-8c77-5c3ee4be3564
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015578716 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1015578716
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3820948455
Short name T106
Test name
Test status
Simulation time 74326665 ps
CPU time 0.78 seconds
Started Apr 25 12:50:10 PM PDT 24
Finished Apr 25 12:50:14 PM PDT 24
Peak memory 200804 kb
Host smart-bdc28132-5c5d-4dc2-ae01-a47b6e3c2b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820948455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3820948455
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2220685865
Short name T568
Test name
Test status
Simulation time 113321463 ps
CPU time 1.1 seconds
Started Apr 25 12:50:06 PM PDT 24
Finished Apr 25 12:50:10 PM PDT 24
Peak memory 200932 kb
Host smart-dab505a7-91d3-4771-9fcb-5b0c477ae2d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220685865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2220685865
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4054235618
Short name T116
Test name
Test status
Simulation time 584612772 ps
CPU time 3.87 seconds
Started Apr 25 12:50:16 PM PDT 24
Finished Apr 25 12:50:24 PM PDT 24
Peak memory 217376 kb
Host smart-205f4caf-727e-42d4-9768-522fe478a854
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054235618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.4054235618
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4126136005
Short name T114
Test name
Test status
Simulation time 490835595 ps
CPU time 2.04 seconds
Started Apr 25 12:50:21 PM PDT 24
Finished Apr 25 12:50:27 PM PDT 24
Peak memory 201116 kb
Host smart-ef2301ac-467b-473e-864a-92e9a5eab53c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126136005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.4126136005
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.509479075
Short name T91
Test name
Test status
Simulation time 118822618 ps
CPU time 1.16 seconds
Started Apr 25 12:50:11 PM PDT 24
Finished Apr 25 12:50:15 PM PDT 24
Peak memory 209208 kb
Host smart-1a70de9a-f42e-4a87-ab2b-1050b1fb16c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509479075 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.509479075
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1950896916
Short name T112
Test name
Test status
Simulation time 90438411 ps
CPU time 0.84 seconds
Started Apr 25 12:50:28 PM PDT 24
Finished Apr 25 12:50:31 PM PDT 24
Peak memory 200756 kb
Host smart-b0d23fb1-e650-4a5a-a16d-318abb7fc0ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950896916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1950896916
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1564348942
Short name T109
Test name
Test status
Simulation time 127579505 ps
CPU time 1.03 seconds
Started Apr 25 12:50:09 PM PDT 24
Finished Apr 25 12:50:12 PM PDT 24
Peak memory 200852 kb
Host smart-562bebc4-8677-4e03-83a8-b2c34fa03bf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564348942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1564348942
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2139230852
Short name T564
Test name
Test status
Simulation time 288620433 ps
CPU time 2.11 seconds
Started Apr 25 12:50:12 PM PDT 24
Finished Apr 25 12:50:19 PM PDT 24
Peak memory 209304 kb
Host smart-fb3b3515-8a76-4714-b483-fe0c51d5d025
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139230852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2139230852
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.652877413
Short name T59
Test name
Test status
Simulation time 479914641 ps
CPU time 1.93 seconds
Started Apr 25 12:50:19 PM PDT 24
Finished Apr 25 12:50:30 PM PDT 24
Peak memory 201088 kb
Host smart-22b00bd1-073e-4ae5-a24b-9d499494d0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652877413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
652877413
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.37804402
Short name T430
Test name
Test status
Simulation time 84076366 ps
CPU time 0.8 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:32 PM PDT 24
Peak memory 200604 kb
Host smart-3d4edd07-73b5-4303-bd96-527d2b0c30eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37804402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.37804402
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.868399369
Short name T200
Test name
Test status
Simulation time 1890832513 ps
CPU time 6.97 seconds
Started Apr 25 12:57:32 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 222612 kb
Host smart-106b4683-1da8-4cf5-9e4f-4cbf3473aed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868399369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.868399369
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4241053126
Short name T444
Test name
Test status
Simulation time 197731038 ps
CPU time 0.89 seconds
Started Apr 25 12:57:44 PM PDT 24
Finished Apr 25 12:57:47 PM PDT 24
Peak memory 200688 kb
Host smart-597f05d3-e283-4cc6-ac79-5abede10b5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241053126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4241053126
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3607782920
Short name T163
Test name
Test status
Simulation time 1276338196 ps
CPU time 5.02 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:36 PM PDT 24
Peak memory 200992 kb
Host smart-1c5d7536-397f-4927-b303-dfb596ac4706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607782920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3607782920
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4044285741
Short name T222
Test name
Test status
Simulation time 104984340 ps
CPU time 1.01 seconds
Started Apr 25 12:57:39 PM PDT 24
Finished Apr 25 12:57:42 PM PDT 24
Peak memory 200904 kb
Host smart-0b09394b-0673-43af-b059-f8b0b8282e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044285741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4044285741
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2077676496
Short name T232
Test name
Test status
Simulation time 259773278 ps
CPU time 1.51 seconds
Started Apr 25 12:57:27 PM PDT 24
Finished Apr 25 12:57:30 PM PDT 24
Peak memory 201064 kb
Host smart-4681143f-6a82-4100-9c73-851961ac95f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077676496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2077676496
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1196749248
Short name T360
Test name
Test status
Simulation time 6962545238 ps
CPU time 30.07 seconds
Started Apr 25 12:57:32 PM PDT 24
Finished Apr 25 12:58:03 PM PDT 24
Peak memory 201200 kb
Host smart-2fb5d249-ffaa-496c-a16c-6ef0f07f2915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196749248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1196749248
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1489890130
Short name T508
Test name
Test status
Simulation time 334444334 ps
CPU time 2.13 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:32 PM PDT 24
Peak memory 209164 kb
Host smart-421e3655-b499-4085-8fd8-ccca908452cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489890130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1489890130
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.4214425174
Short name T534
Test name
Test status
Simulation time 135324610 ps
CPU time 1.18 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:32 PM PDT 24
Peak memory 200796 kb
Host smart-de64bd63-a370-4a1f-af77-545070c118f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214425174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.4214425174
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1880961458
Short name T507
Test name
Test status
Simulation time 64856234 ps
CPU time 0.75 seconds
Started Apr 25 12:57:28 PM PDT 24
Finished Apr 25 12:57:30 PM PDT 24
Peak memory 200624 kb
Host smart-2a4a99d4-9c37-42ab-93c7-6733ddd2239d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880961458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1880961458
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2480576931
Short name T30
Test name
Test status
Simulation time 1881294903 ps
CPU time 7.6 seconds
Started Apr 25 12:57:16 PM PDT 24
Finished Apr 25 12:57:25 PM PDT 24
Peak memory 218560 kb
Host smart-22a14196-b471-4ff3-9385-57f4fd435021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480576931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2480576931
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.143780182
Short name T285
Test name
Test status
Simulation time 244277083 ps
CPU time 1.07 seconds
Started Apr 25 12:57:08 PM PDT 24
Finished Apr 25 12:57:13 PM PDT 24
Peak memory 218080 kb
Host smart-dda31cbe-4659-460b-8928-89717006c68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143780182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.143780182
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.902246162
Short name T244
Test name
Test status
Simulation time 91274933 ps
CPU time 0.74 seconds
Started Apr 25 12:57:20 PM PDT 24
Finished Apr 25 12:57:22 PM PDT 24
Peak memory 200616 kb
Host smart-2719c23f-1602-4106-92ac-b149f75d832f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902246162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.902246162
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1917320589
Short name T68
Test name
Test status
Simulation time 8313645406 ps
CPU time 15.49 seconds
Started Apr 25 12:57:23 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 217492 kb
Host smart-71a478ae-35d7-4cb0-880a-6315f6353ca7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917320589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1917320589
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2397252297
Short name T254
Test name
Test status
Simulation time 96991047 ps
CPU time 1.06 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 200904 kb
Host smart-54d1c26d-acbe-4fad-beb0-b39775c61087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397252297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2397252297
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.4188844775
Short name T212
Test name
Test status
Simulation time 185991146 ps
CPU time 1.41 seconds
Started Apr 25 12:57:20 PM PDT 24
Finished Apr 25 12:57:23 PM PDT 24
Peak memory 201028 kb
Host smart-1dfe74d9-d7b3-4df5-96a4-3c06499f1435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188844775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4188844775
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.4109889708
Short name T103
Test name
Test status
Simulation time 6796501219 ps
CPU time 28.23 seconds
Started Apr 25 12:57:27 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 209396 kb
Host smart-0cafd8bb-6828-4e82-bdb5-eb00c9a83d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109889708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4109889708
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.451011806
Short name T492
Test name
Test status
Simulation time 116741874 ps
CPU time 1.45 seconds
Started Apr 25 12:57:32 PM PDT 24
Finished Apr 25 12:57:35 PM PDT 24
Peak memory 200820 kb
Host smart-05bf70ac-ef61-4ccb-a557-e8803cd8e32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451011806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.451011806
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1574180779
Short name T217
Test name
Test status
Simulation time 96120112 ps
CPU time 0.94 seconds
Started Apr 25 12:57:41 PM PDT 24
Finished Apr 25 12:57:43 PM PDT 24
Peak memory 200816 kb
Host smart-6ac59adb-046e-4883-bc31-510ebec6a14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574180779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1574180779
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3329901793
Short name T386
Test name
Test status
Simulation time 70493308 ps
CPU time 0.77 seconds
Started Apr 25 12:57:27 PM PDT 24
Finished Apr 25 12:57:29 PM PDT 24
Peak memory 200692 kb
Host smart-fb2d5d69-87e2-40ee-ad73-2a0c72ca76b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329901793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3329901793
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.4031130877
Short name T383
Test name
Test status
Simulation time 2174750980 ps
CPU time 7.43 seconds
Started Apr 25 12:57:45 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 217696 kb
Host smart-4a7ce8fc-8955-41b1-bfbc-8fdeda8fe821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031130877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.4031130877
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3338854568
Short name T237
Test name
Test status
Simulation time 245288769 ps
CPU time 1.08 seconds
Started Apr 25 12:57:36 PM PDT 24
Finished Apr 25 12:57:39 PM PDT 24
Peak memory 218216 kb
Host smart-1bcf6f0c-43bc-4dc6-8947-4c1a6e443e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338854568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3338854568
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2881725978
Short name T171
Test name
Test status
Simulation time 100831965 ps
CPU time 0.84 seconds
Started Apr 25 12:57:25 PM PDT 24
Finished Apr 25 12:57:27 PM PDT 24
Peak memory 200700 kb
Host smart-2f4e271b-295c-4fda-8c3f-c08b444a3029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881725978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2881725978
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3152020085
Short name T236
Test name
Test status
Simulation time 1976844823 ps
CPU time 6.84 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:58:03 PM PDT 24
Peak memory 201048 kb
Host smart-739b66c3-25d4-4eea-94e9-5f43531de5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152020085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3152020085
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3907361193
Short name T266
Test name
Test status
Simulation time 182693278 ps
CPU time 1.24 seconds
Started Apr 25 12:57:27 PM PDT 24
Finished Apr 25 12:57:30 PM PDT 24
Peak memory 200840 kb
Host smart-acb5545d-6804-4643-b96f-0386c965a70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907361193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3907361193
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1516515182
Short name T419
Test name
Test status
Simulation time 126581975 ps
CPU time 1.18 seconds
Started Apr 25 12:57:40 PM PDT 24
Finished Apr 25 12:57:43 PM PDT 24
Peak memory 201084 kb
Host smart-e02bb895-9801-4a98-8eae-0862bf7cc2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516515182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1516515182
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1533373791
Short name T259
Test name
Test status
Simulation time 4264485476 ps
CPU time 16.16 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 201200 kb
Host smart-13f0f703-0001-4d84-a86a-631e6bd880ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533373791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1533373791
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2000066963
Short name T322
Test name
Test status
Simulation time 280915071 ps
CPU time 1.91 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 209080 kb
Host smart-aefde9c1-f09f-43ee-8526-a0d770c629a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000066963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2000066963
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1266384390
Short name T6
Test name
Test status
Simulation time 57813165 ps
CPU time 0.71 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:57:52 PM PDT 24
Peak memory 200844 kb
Host smart-0dc10e3e-a197-487a-90c8-7cea99a6e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266384390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1266384390
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1960272908
Short name T321
Test name
Test status
Simulation time 1885590306 ps
CPU time 7.2 seconds
Started Apr 25 12:57:41 PM PDT 24
Finished Apr 25 12:57:49 PM PDT 24
Peak memory 221952 kb
Host smart-50d0e78a-3dbc-4580-b03e-0bb6b2307956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960272908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1960272908
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2294175228
Short name T452
Test name
Test status
Simulation time 244320613 ps
CPU time 1.14 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 218112 kb
Host smart-6da4efee-8eb4-43e9-bcde-701e05f2a267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294175228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2294175228
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2960194152
Short name T202
Test name
Test status
Simulation time 160941817 ps
CPU time 0.81 seconds
Started Apr 25 12:57:35 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 200624 kb
Host smart-fc3be27b-7aa1-4244-8f5b-d032ee68d987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960194152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2960194152
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1048457812
Short name T245
Test name
Test status
Simulation time 1343549018 ps
CPU time 5.02 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 201068 kb
Host smart-3fee8fc5-9ea6-491b-8b1e-e17b608a0d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048457812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1048457812
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1939985034
Short name T446
Test name
Test status
Simulation time 99579602 ps
CPU time 0.99 seconds
Started Apr 25 12:57:43 PM PDT 24
Finished Apr 25 12:57:46 PM PDT 24
Peak memory 200836 kb
Host smart-eaede488-8f29-45b0-82b9-f9718ba511e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939985034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1939985034
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1459892924
Short name T228
Test name
Test status
Simulation time 114440123 ps
CPU time 1.16 seconds
Started Apr 25 12:57:33 PM PDT 24
Finished Apr 25 12:57:35 PM PDT 24
Peak memory 201084 kb
Host smart-6c2dfd3c-ff49-4c86-a89b-90e7c2e5c25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459892924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1459892924
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3088604962
Short name T423
Test name
Test status
Simulation time 5516495260 ps
CPU time 25.3 seconds
Started Apr 25 12:57:45 PM PDT 24
Finished Apr 25 12:58:12 PM PDT 24
Peak memory 209328 kb
Host smart-5f1049a6-b21c-48b5-b689-ddeb5df3b387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088604962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3088604962
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1470676955
Short name T498
Test name
Test status
Simulation time 383863230 ps
CPU time 2.33 seconds
Started Apr 25 12:57:38 PM PDT 24
Finished Apr 25 12:57:43 PM PDT 24
Peak memory 208976 kb
Host smart-3a5ee193-0835-4b5b-b6f5-641a12c76901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470676955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1470676955
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1897411325
Short name T346
Test name
Test status
Simulation time 226939438 ps
CPU time 1.29 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 200848 kb
Host smart-6d67f995-04e2-4e59-9e97-ce7afe5f099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897411325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1897411325
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4062032579
Short name T420
Test name
Test status
Simulation time 69855289 ps
CPU time 0.76 seconds
Started Apr 25 12:57:35 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 200684 kb
Host smart-cfe77a9d-279a-4e1b-aec1-be5ae7987ba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062032579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4062032579
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1700910827
Short name T392
Test name
Test status
Simulation time 2375302987 ps
CPU time 8.34 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:58:04 PM PDT 24
Peak memory 222156 kb
Host smart-ac8d851c-3395-4b18-89f2-69cedc401e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700910827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1700910827
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2079866729
Short name T482
Test name
Test status
Simulation time 244825810 ps
CPU time 1.03 seconds
Started Apr 25 12:57:34 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 218252 kb
Host smart-21058f30-4a2d-4194-96ad-4197b7242aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079866729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2079866729
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3349451391
Short name T396
Test name
Test status
Simulation time 231208090 ps
CPU time 0.92 seconds
Started Apr 25 12:57:36 PM PDT 24
Finished Apr 25 12:57:38 PM PDT 24
Peak memory 200684 kb
Host smart-dab17359-fd11-47ec-ad11-71382fc28d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349451391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3349451391
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3978442168
Short name T442
Test name
Test status
Simulation time 1492966301 ps
CPU time 5.65 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:59 PM PDT 24
Peak memory 201000 kb
Host smart-bbb3a96f-701d-4bb0-8a24-7f518bfcb12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978442168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3978442168
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3470890471
Short name T294
Test name
Test status
Simulation time 145026713 ps
CPU time 1.09 seconds
Started Apr 25 12:57:47 PM PDT 24
Finished Apr 25 12:57:51 PM PDT 24
Peak memory 200836 kb
Host smart-572f9899-dd0e-482d-94c2-aefb48e38a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470890471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3470890471
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.389583412
Short name T227
Test name
Test status
Simulation time 206569156 ps
CPU time 1.38 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 201016 kb
Host smart-7a68a7b6-033e-43b5-8f50-bc4ec4ba4421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389583412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.389583412
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1698865118
Short name T323
Test name
Test status
Simulation time 11183663985 ps
CPU time 41.21 seconds
Started Apr 25 12:57:54 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 209368 kb
Host smart-0627976b-7454-47a7-8aed-5aafd47a557f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698865118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1698865118
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.946211414
Short name T366
Test name
Test status
Simulation time 109444604 ps
CPU time 1.48 seconds
Started Apr 25 12:57:51 PM PDT 24
Finished Apr 25 12:57:55 PM PDT 24
Peak memory 200808 kb
Host smart-1937e2b4-3fbd-4fc9-aef6-64a28b193e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946211414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.946211414
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1149429785
Short name T336
Test name
Test status
Simulation time 219784705 ps
CPU time 1.35 seconds
Started Apr 25 12:57:43 PM PDT 24
Finished Apr 25 12:57:46 PM PDT 24
Peak memory 200892 kb
Host smart-ae987ad3-86dd-4f90-9461-58df9874252e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149429785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1149429785
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3019529804
Short name T363
Test name
Test status
Simulation time 77867536 ps
CPU time 0.79 seconds
Started Apr 25 12:57:41 PM PDT 24
Finished Apr 25 12:57:43 PM PDT 24
Peak memory 200684 kb
Host smart-17b8e4c1-23a8-4d09-865c-e47783fb7e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019529804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3019529804
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.795987447
Short name T524
Test name
Test status
Simulation time 2359759214 ps
CPU time 7.65 seconds
Started Apr 25 12:58:00 PM PDT 24
Finished Apr 25 12:58:10 PM PDT 24
Peak memory 222816 kb
Host smart-89d480f9-c681-4f4a-abbc-6bc87aa42ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795987447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.795987447
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.433450883
Short name T176
Test name
Test status
Simulation time 243110753 ps
CPU time 1.03 seconds
Started Apr 25 12:58:02 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 218172 kb
Host smart-7646856f-2823-425e-9222-ff645f67adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433450883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.433450883
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.4291044653
Short name T290
Test name
Test status
Simulation time 196652427 ps
CPU time 0.89 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:53 PM PDT 24
Peak memory 200692 kb
Host smart-c4f066e3-1e55-44e0-87de-04a5b05f59f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291044653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.4291044653
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.361353987
Short name T256
Test name
Test status
Simulation time 993699002 ps
CPU time 4.4 seconds
Started Apr 25 12:57:43 PM PDT 24
Finished Apr 25 12:57:49 PM PDT 24
Peak memory 201060 kb
Host smart-4fd90a6e-534c-479a-bac8-ea8bfacb749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361353987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.361353987
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3103907584
Short name T525
Test name
Test status
Simulation time 173653288 ps
CPU time 1.19 seconds
Started Apr 25 12:57:41 PM PDT 24
Finished Apr 25 12:57:43 PM PDT 24
Peak memory 200744 kb
Host smart-a9931bd8-a69c-4fe1-a0d8-5b0f0d8fce1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103907584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3103907584
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2119707290
Short name T196
Test name
Test status
Simulation time 119237851 ps
CPU time 1.15 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 201040 kb
Host smart-5fe5511d-e9da-420e-85bc-ca7962d18cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119707290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2119707290
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.826012070
Short name T262
Test name
Test status
Simulation time 939792515 ps
CPU time 4.65 seconds
Started Apr 25 12:57:51 PM PDT 24
Finished Apr 25 12:57:59 PM PDT 24
Peak memory 201056 kb
Host smart-95dc7293-1263-48e5-b367-a177a7e24689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826012070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.826012070
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3994775216
Short name T1
Test name
Test status
Simulation time 122066100 ps
CPU time 1.49 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 200896 kb
Host smart-7a94bcb5-483a-4e57-a871-a72cc380c3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994775216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3994775216
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4006708899
Short name T226
Test name
Test status
Simulation time 72946295 ps
CPU time 0.79 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:53 PM PDT 24
Peak memory 200856 kb
Host smart-2b68d85c-1f3f-493f-b27e-0c5eea305c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006708899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4006708899
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.332640949
Short name T454
Test name
Test status
Simulation time 63035969 ps
CPU time 0.76 seconds
Started Apr 25 12:57:56 PM PDT 24
Finished Apr 25 12:58:00 PM PDT 24
Peak memory 200712 kb
Host smart-588a2f14-2463-44fe-969d-fc588b721ddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332640949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.332640949
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.912934815
Short name T521
Test name
Test status
Simulation time 1224213545 ps
CPU time 5.42 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 222092 kb
Host smart-8335b40a-208b-4425-98fe-25c93ec08f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912934815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.912934815
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.984175466
Short name T282
Test name
Test status
Simulation time 243409502 ps
CPU time 1.09 seconds
Started Apr 25 12:57:46 PM PDT 24
Finished Apr 25 12:57:48 PM PDT 24
Peak memory 218100 kb
Host smart-9093eba1-821a-47ee-975c-2e7adce4c198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984175466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.984175466
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.931157240
Short name T404
Test name
Test status
Simulation time 163125169 ps
CPU time 0.89 seconds
Started Apr 25 12:57:43 PM PDT 24
Finished Apr 25 12:57:46 PM PDT 24
Peak memory 200596 kb
Host smart-8a49fc01-c314-4f5e-abaf-fa6e6cb92af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931157240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.931157240
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4164279753
Short name T342
Test name
Test status
Simulation time 835831352 ps
CPU time 3.99 seconds
Started Apr 25 12:57:48 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 201012 kb
Host smart-ca9c5215-d9f5-4834-bd1c-6d8a8098695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164279753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4164279753
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2195657967
Short name T361
Test name
Test status
Simulation time 106575871 ps
CPU time 0.96 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:15 PM PDT 24
Peak memory 200880 kb
Host smart-4f63320e-8edd-4409-a493-f2215f4e482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195657967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2195657967
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3537606227
Short name T84
Test name
Test status
Simulation time 249247244 ps
CPU time 1.53 seconds
Started Apr 25 12:57:39 PM PDT 24
Finished Apr 25 12:57:42 PM PDT 24
Peak memory 201056 kb
Host smart-679f7875-ff64-4d4d-9b25-e41bdde67270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537606227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3537606227
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2984376573
Short name T252
Test name
Test status
Simulation time 992298124 ps
CPU time 5.06 seconds
Started Apr 25 12:58:24 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 200824 kb
Host smart-3e7a5e96-5282-41da-bbbd-127c427f2cc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984376573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2984376573
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2184319450
Short name T468
Test name
Test status
Simulation time 133324626 ps
CPU time 1.56 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 209148 kb
Host smart-2cba0f93-29a5-43e0-802e-2ed38aa6bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184319450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2184319450
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1467273418
Short name T516
Test name
Test status
Simulation time 198689942 ps
CPU time 1.26 seconds
Started Apr 25 12:57:56 PM PDT 24
Finished Apr 25 12:58:00 PM PDT 24
Peak memory 200848 kb
Host smart-62e77c85-3c4e-424f-a716-43c1d3d60893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467273418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1467273418
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.682541217
Short name T313
Test name
Test status
Simulation time 98775824 ps
CPU time 0.81 seconds
Started Apr 25 12:57:48 PM PDT 24
Finished Apr 25 12:57:51 PM PDT 24
Peak memory 200716 kb
Host smart-452e68f4-bf13-47fe-8b37-e7994287b85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682541217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.682541217
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.963835188
Short name T394
Test name
Test status
Simulation time 1227121340 ps
CPU time 5.62 seconds
Started Apr 25 12:58:05 PM PDT 24
Finished Apr 25 12:58:12 PM PDT 24
Peak memory 218056 kb
Host smart-6be91a55-2d0f-4d86-9308-6a0b869cdc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963835188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.963835188
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3099713116
Short name T426
Test name
Test status
Simulation time 244040223 ps
CPU time 1.06 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 218124 kb
Host smart-0dec36f1-0f9c-4e7c-981a-1d1d5d26c8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099713116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3099713116
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1729876721
Short name T309
Test name
Test status
Simulation time 245742953 ps
CPU time 1.02 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 200672 kb
Host smart-b267b217-795a-47e0-8bd8-1b936b9ff1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729876721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1729876721
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3535678610
Short name T102
Test name
Test status
Simulation time 865494696 ps
CPU time 4.56 seconds
Started Apr 25 12:57:51 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 201076 kb
Host smart-0a00ba19-8287-4bd6-a875-53c169b8919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535678610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3535678610
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4050710827
Short name T146
Test name
Test status
Simulation time 155118276 ps
CPU time 1.16 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:57:52 PM PDT 24
Peak memory 200888 kb
Host smart-a45fd032-cf04-4253-8529-4185f07ead4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050710827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4050710827
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1208386900
Short name T9
Test name
Test status
Simulation time 249488669 ps
CPU time 1.59 seconds
Started Apr 25 12:57:54 PM PDT 24
Finished Apr 25 12:57:59 PM PDT 24
Peak memory 201048 kb
Host smart-213005c6-efeb-48c3-8ae2-b0c2ad984a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208386900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1208386900
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3026510160
Short name T445
Test name
Test status
Simulation time 12042677792 ps
CPU time 40.83 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:58:32 PM PDT 24
Peak memory 211052 kb
Host smart-f8b99016-329d-4acd-87f7-d010754bbcf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026510160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3026510160
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.918754275
Short name T190
Test name
Test status
Simulation time 477953764 ps
CPU time 2.55 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:55 PM PDT 24
Peak memory 209032 kb
Host smart-c39f57a6-2e5d-4eed-ac99-dba4fc3e4da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918754275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.918754275
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2099711285
Short name T69
Test name
Test status
Simulation time 72404907 ps
CPU time 0.85 seconds
Started Apr 25 12:58:00 PM PDT 24
Finished Apr 25 12:58:03 PM PDT 24
Peak memory 200816 kb
Host smart-73912811-6312-4516-be77-664ce72ab96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099711285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2099711285
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.370881623
Short name T384
Test name
Test status
Simulation time 74701580 ps
CPU time 0.8 seconds
Started Apr 25 12:57:51 PM PDT 24
Finished Apr 25 12:57:55 PM PDT 24
Peak memory 200568 kb
Host smart-fb192730-474a-4d3f-a60b-575f67de0efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370881623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.370881623
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.882443795
Short name T405
Test name
Test status
Simulation time 1909915463 ps
CPU time 7.34 seconds
Started Apr 25 12:57:51 PM PDT 24
Finished Apr 25 12:58:02 PM PDT 24
Peak memory 218556 kb
Host smart-74a2a9af-fc69-4db3-9783-84ff543dc94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882443795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.882443795
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3203406891
Short name T235
Test name
Test status
Simulation time 243495754 ps
CPU time 1.07 seconds
Started Apr 25 12:57:47 PM PDT 24
Finished Apr 25 12:57:50 PM PDT 24
Peak memory 218040 kb
Host smart-f36bf63c-3939-494c-9310-95ece079ee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203406891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3203406891
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2392855842
Short name T320
Test name
Test status
Simulation time 2040833130 ps
CPU time 7.54 seconds
Started Apr 25 12:57:39 PM PDT 24
Finished Apr 25 12:57:48 PM PDT 24
Peak memory 201072 kb
Host smart-8d9c805b-9171-486e-ada8-551e710911d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392855842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2392855842
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3576362541
Short name T500
Test name
Test status
Simulation time 105779634 ps
CPU time 1.02 seconds
Started Apr 25 12:57:42 PM PDT 24
Finished Apr 25 12:57:45 PM PDT 24
Peak memory 200856 kb
Host smart-c60739b2-6a3d-4491-ba81-f137ddbb39ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576362541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3576362541
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1183281815
Short name T3
Test name
Test status
Simulation time 188995910 ps
CPU time 1.38 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 201036 kb
Host smart-c5c365c3-d5a3-4fdb-8c59-1f3342ac664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183281815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1183281815
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.891698642
Short name T198
Test name
Test status
Simulation time 1301340792 ps
CPU time 6.25 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:59 PM PDT 24
Peak memory 210384 kb
Host smart-32ffaafc-5044-4498-807a-34023b17daa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891698642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.891698642
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3879427438
Short name T311
Test name
Test status
Simulation time 123867618 ps
CPU time 1.52 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 208796 kb
Host smart-500f62d3-cce3-4c45-9e7e-bc21a05f6184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879427438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3879427438
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2390524314
Short name T380
Test name
Test status
Simulation time 196107722 ps
CPU time 1.26 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 200904 kb
Host smart-2d712433-4652-4ff8-b676-bbf8e91a83cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390524314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2390524314
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3004777556
Short name T264
Test name
Test status
Simulation time 64522271 ps
CPU time 0.73 seconds
Started Apr 25 12:57:45 PM PDT 24
Finished Apr 25 12:57:48 PM PDT 24
Peak memory 200664 kb
Host smart-11519391-a728-40a2-abb4-55e25b24bc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004777556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3004777556
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3018721097
Short name T398
Test name
Test status
Simulation time 2338957186 ps
CPU time 7.77 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 218664 kb
Host smart-7071a01e-d93f-456f-823b-4074d60dd0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018721097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3018721097
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1806058070
Short name T483
Test name
Test status
Simulation time 244243092 ps
CPU time 1.06 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:57:53 PM PDT 24
Peak memory 218264 kb
Host smart-5a81bcd8-3932-4424-a053-e710f32d828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806058070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1806058070
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.49036834
Short name T510
Test name
Test status
Simulation time 160990318 ps
CPU time 0.86 seconds
Started Apr 25 12:57:42 PM PDT 24
Finished Apr 25 12:57:46 PM PDT 24
Peak memory 200652 kb
Host smart-f3f966c9-710a-4fa0-a372-dd3ce9752e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49036834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.49036834
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1676353825
Short name T213
Test name
Test status
Simulation time 1294324143 ps
CPU time 4.72 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 201028 kb
Host smart-1c5c9e4f-ba18-43c4-9f04-ee891faf2cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676353825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1676353825
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3056005016
Short name T509
Test name
Test status
Simulation time 100404723 ps
CPU time 0.97 seconds
Started Apr 25 12:58:13 PM PDT 24
Finished Apr 25 12:58:17 PM PDT 24
Peak memory 200896 kb
Host smart-b0da26f5-1a44-44b2-8fe2-6382fa402551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056005016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3056005016
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2237459531
Short name T448
Test name
Test status
Simulation time 229070856 ps
CPU time 1.47 seconds
Started Apr 25 12:57:45 PM PDT 24
Finished Apr 25 12:57:48 PM PDT 24
Peak memory 200860 kb
Host smart-46207e14-ff1c-42a9-827d-f214b6179a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237459531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2237459531
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3522439896
Short name T477
Test name
Test status
Simulation time 113563556 ps
CPU time 1.47 seconds
Started Apr 25 12:57:45 PM PDT 24
Finished Apr 25 12:57:48 PM PDT 24
Peak memory 200908 kb
Host smart-c2eed31f-03ff-4964-86c6-c5c2777b08cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522439896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3522439896
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4257920986
Short name T204
Test name
Test status
Simulation time 207450810 ps
CPU time 1.37 seconds
Started Apr 25 12:57:44 PM PDT 24
Finished Apr 25 12:57:47 PM PDT 24
Peak memory 200980 kb
Host smart-ef5705ae-29dd-4e2e-8616-6efc838febf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257920986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4257920986
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2302940077
Short name T520
Test name
Test status
Simulation time 66456211 ps
CPU time 0.74 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 200684 kb
Host smart-08e2b044-4908-42a9-9cbb-2ffff5b294a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302940077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2302940077
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3139273985
Short name T31
Test name
Test status
Simulation time 1886796262 ps
CPU time 7.07 seconds
Started Apr 25 12:58:23 PM PDT 24
Finished Apr 25 12:58:32 PM PDT 24
Peak memory 222560 kb
Host smart-a0241522-84f4-41ac-8e44-ba0b9e39c447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139273985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3139273985
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.689443630
Short name T368
Test name
Test status
Simulation time 244372299 ps
CPU time 1.04 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:16 PM PDT 24
Peak memory 218084 kb
Host smart-990ce315-1647-4bf3-b745-4deb54b00ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689443630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.689443630
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1872244077
Short name T401
Test name
Test status
Simulation time 192329442 ps
CPU time 0.86 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 200596 kb
Host smart-cebd42e6-23cd-4caf-9497-225c8e02fe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872244077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1872244077
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.300132523
Short name T184
Test name
Test status
Simulation time 956621271 ps
CPU time 4.78 seconds
Started Apr 25 12:57:48 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 200928 kb
Host smart-41941523-3803-4fd2-b31a-44e4cc0a4f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300132523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.300132523
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1896147188
Short name T49
Test name
Test status
Simulation time 105324634 ps
CPU time 0.97 seconds
Started Apr 25 12:57:45 PM PDT 24
Finished Apr 25 12:57:48 PM PDT 24
Peak memory 200692 kb
Host smart-9ffb8e95-9b21-4cdf-880e-6a5ab970d3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896147188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1896147188
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.382272692
Short name T281
Test name
Test status
Simulation time 257331555 ps
CPU time 1.56 seconds
Started Apr 25 12:57:58 PM PDT 24
Finished Apr 25 12:58:02 PM PDT 24
Peak memory 201000 kb
Host smart-2b24ebab-ae9f-47ec-8582-dc7c4ef58649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382272692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.382272692
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3864623708
Short name T301
Test name
Test status
Simulation time 4320473750 ps
CPU time 18.18 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 201208 kb
Host smart-b7161662-cb5f-4919-8c72-7d005b139b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864623708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3864623708
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1213367128
Short name T267
Test name
Test status
Simulation time 247702881 ps
CPU time 1.71 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:57:52 PM PDT 24
Peak memory 200876 kb
Host smart-083daeed-4a6a-45a8-868c-dafe7a5ce8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213367128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1213367128
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1937200644
Short name T485
Test name
Test status
Simulation time 90534845 ps
CPU time 0.87 seconds
Started Apr 25 12:57:51 PM PDT 24
Finished Apr 25 12:57:55 PM PDT 24
Peak memory 200904 kb
Host smart-10b88cd2-df26-4c48-8971-2af571b30603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937200644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1937200644
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.952918531
Short name T233
Test name
Test status
Simulation time 72157597 ps
CPU time 0.81 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 200632 kb
Host smart-f2c146cd-5405-439f-8aee-94bc54222c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952918531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.952918531
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2269827728
Short name T45
Test name
Test status
Simulation time 1241923150 ps
CPU time 5.26 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 218624 kb
Host smart-283824d2-c65b-4b55-b627-782c2bcb749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269827728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2269827728
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1179380281
Short name T535
Test name
Test status
Simulation time 244909135 ps
CPU time 1.06 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 218172 kb
Host smart-2c621882-79b9-404d-87c5-84db81d7ab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179380281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1179380281
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3804288984
Short name T424
Test name
Test status
Simulation time 189997253 ps
CPU time 0.87 seconds
Started Apr 25 12:58:06 PM PDT 24
Finished Apr 25 12:58:08 PM PDT 24
Peak memory 200548 kb
Host smart-681bc075-f284-4845-8ea0-9231c96ff8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804288984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3804288984
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1808614565
Short name T539
Test name
Test status
Simulation time 1365880830 ps
CPU time 5.55 seconds
Started Apr 25 12:57:56 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 201076 kb
Host smart-030467a0-89bd-4b55-abb8-dc35c12ccbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808614565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1808614565
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1062262201
Short name T170
Test name
Test status
Simulation time 155027789 ps
CPU time 1.17 seconds
Started Apr 25 12:58:00 PM PDT 24
Finished Apr 25 12:58:03 PM PDT 24
Peak memory 200980 kb
Host smart-6f6f7917-b63f-401f-b0e7-a35cd9711037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062262201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1062262201
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3402020355
Short name T258
Test name
Test status
Simulation time 111162333 ps
CPU time 1.18 seconds
Started Apr 25 12:58:01 PM PDT 24
Finished Apr 25 12:58:04 PM PDT 24
Peak memory 201068 kb
Host smart-5acdcf48-1868-435c-b4c0-387b466fce26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402020355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3402020355
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.48647654
Short name T153
Test name
Test status
Simulation time 130072409 ps
CPU time 1.28 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 200820 kb
Host smart-21a38b2d-ef51-4da7-a2ad-7ae1b5d3138c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48647654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.48647654
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2501037573
Short name T504
Test name
Test status
Simulation time 384168679 ps
CPU time 2.36 seconds
Started Apr 25 12:58:17 PM PDT 24
Finished Apr 25 12:58:22 PM PDT 24
Peak memory 209056 kb
Host smart-df5c270a-9cb8-4563-b773-0238c54aa0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501037573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2501037573
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2846423430
Short name T351
Test name
Test status
Simulation time 134577329 ps
CPU time 1.04 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 200980 kb
Host smart-c593c3bd-a065-4321-99c7-aab3ed9e032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846423430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2846423430
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1004033620
Short name T32
Test name
Test status
Simulation time 69905700 ps
CPU time 0.75 seconds
Started Apr 25 12:57:32 PM PDT 24
Finished Apr 25 12:57:34 PM PDT 24
Peak memory 200652 kb
Host smart-07c3a79e-2d55-4df4-adbf-57fde89bc278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004033620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1004033620
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2453441954
Short name T436
Test name
Test status
Simulation time 2346676495 ps
CPU time 8.02 seconds
Started Apr 25 12:57:12 PM PDT 24
Finished Apr 25 12:57:23 PM PDT 24
Peak memory 222744 kb
Host smart-5e7a1f9c-d756-4cc9-8123-bde56868e2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453441954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2453441954
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2176775948
Short name T522
Test name
Test status
Simulation time 245164699 ps
CPU time 1.06 seconds
Started Apr 25 12:57:24 PM PDT 24
Finished Apr 25 12:57:26 PM PDT 24
Peak memory 218260 kb
Host smart-e392f566-1261-49ce-8108-4e64d3a8d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176775948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2176775948
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1053852870
Short name T12
Test name
Test status
Simulation time 172578010 ps
CPU time 0.83 seconds
Started Apr 25 12:57:17 PM PDT 24
Finished Apr 25 12:57:20 PM PDT 24
Peak memory 200696 kb
Host smart-1417b774-60ef-49ae-9f23-5c2c31d40103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053852870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1053852870
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1612456039
Short name T501
Test name
Test status
Simulation time 973126598 ps
CPU time 4.76 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:58:00 PM PDT 24
Peak memory 201076 kb
Host smart-d4772a18-155f-4ca9-889e-fd8ff6973f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612456039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1612456039
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.737915590
Short name T67
Test name
Test status
Simulation time 8290308881 ps
CPU time 15.35 seconds
Started Apr 25 12:57:34 PM PDT 24
Finished Apr 25 12:57:50 PM PDT 24
Peak memory 217764 kb
Host smart-e666f3a9-9070-4af3-b428-bf09e450f922
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737915590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.737915590
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3450921238
Short name T229
Test name
Test status
Simulation time 155612238 ps
CPU time 1.09 seconds
Started Apr 25 12:57:26 PM PDT 24
Finished Apr 25 12:57:29 PM PDT 24
Peak memory 200816 kb
Host smart-418d1179-0591-4b0d-b43c-ade4377477fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450921238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3450921238
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3027514735
Short name T206
Test name
Test status
Simulation time 249247816 ps
CPU time 1.5 seconds
Started Apr 25 12:57:41 PM PDT 24
Finished Apr 25 12:57:45 PM PDT 24
Peak memory 201076 kb
Host smart-242e7b20-6247-42e6-9c6b-e74b41e8be27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027514735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3027514735
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1054520003
Short name T540
Test name
Test status
Simulation time 5086785825 ps
CPU time 23.12 seconds
Started Apr 25 12:57:35 PM PDT 24
Finished Apr 25 12:57:59 PM PDT 24
Peak memory 201200 kb
Host smart-406e93ce-ca20-42a6-89b4-941809d0a060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054520003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1054520003
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3536745884
Short name T82
Test name
Test status
Simulation time 489703001 ps
CPU time 2.66 seconds
Started Apr 25 12:57:36 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 200772 kb
Host smart-84d14510-ded2-490d-a3b3-ca0221c74fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536745884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3536745884
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1436131981
Short name T137
Test name
Test status
Simulation time 231607799 ps
CPU time 1.38 seconds
Started Apr 25 12:57:11 PM PDT 24
Finished Apr 25 12:57:16 PM PDT 24
Peak memory 200968 kb
Host smart-bf1c6889-8ce3-4869-b52a-552fb57ed52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436131981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1436131981
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2089197691
Short name T407
Test name
Test status
Simulation time 60206136 ps
CPU time 0.74 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 200624 kb
Host smart-e358f864-24d9-4ac9-96ef-841f4fddd9da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089197691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2089197691
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2613509834
Short name T324
Test name
Test status
Simulation time 1236330417 ps
CPU time 5.55 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 222632 kb
Host smart-d2639d6a-39a8-4f6c-828e-a68e21838f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613509834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2613509834
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.799539410
Short name T164
Test name
Test status
Simulation time 244280778 ps
CPU time 1.19 seconds
Started Apr 25 12:58:33 PM PDT 24
Finished Apr 25 12:58:37 PM PDT 24
Peak memory 218088 kb
Host smart-627d815e-0310-49c0-9227-bf6a5ef2c424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799539410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.799539410
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.4083294356
Short name T302
Test name
Test status
Simulation time 217566227 ps
CPU time 0.94 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:00 PM PDT 24
Peak memory 200636 kb
Host smart-bdeb87cd-29b3-494b-a7dc-cbea75ea60d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083294356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4083294356
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1874782622
Short name T425
Test name
Test status
Simulation time 2378473852 ps
CPU time 8.18 seconds
Started Apr 25 12:58:20 PM PDT 24
Finished Apr 25 12:58:30 PM PDT 24
Peak memory 201124 kb
Host smart-5b956106-81ae-415c-be67-b4eb733ac28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874782622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1874782622
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2806982352
Short name T432
Test name
Test status
Simulation time 195109724 ps
CPU time 1.3 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:57:56 PM PDT 24
Peak memory 200800 kb
Host smart-ca843810-1089-45b4-a32c-277fa0e1d87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806982352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2806982352
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.4259220677
Short name T188
Test name
Test status
Simulation time 118233452 ps
CPU time 1.15 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:16 PM PDT 24
Peak memory 201084 kb
Host smart-3f5ea88b-7f5d-4697-a6a7-4d3191d9528c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259220677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4259220677
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2875079023
Short name T491
Test name
Test status
Simulation time 2864472425 ps
CPU time 13.73 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 209400 kb
Host smart-67b56700-604d-4271-a995-e4453ccd4553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875079023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2875079023
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2531007790
Short name T537
Test name
Test status
Simulation time 319779275 ps
CPU time 2.35 seconds
Started Apr 25 12:57:51 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 208936 kb
Host smart-7e8994bd-e752-4b66-9f87-8b7ebd9c0ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531007790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2531007790
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.211211155
Short name T306
Test name
Test status
Simulation time 87156215 ps
CPU time 0.88 seconds
Started Apr 25 12:58:02 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 200888 kb
Host smart-bc8b7765-cdde-4ae3-83d3-c1edee6fcd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211211155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.211211155
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.4181278160
Short name T300
Test name
Test status
Simulation time 60992233 ps
CPU time 0.73 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:57:51 PM PDT 24
Peak memory 200732 kb
Host smart-6a43e00c-f292-4915-8f7b-0cdca7626ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181278160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.4181278160
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1863976825
Short name T133
Test name
Test status
Simulation time 1225162312 ps
CPU time 6.1 seconds
Started Apr 25 12:58:04 PM PDT 24
Finished Apr 25 12:58:12 PM PDT 24
Peak memory 222676 kb
Host smart-83bc4333-aa8f-4329-a731-b626009e802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863976825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1863976825
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1123908494
Short name T35
Test name
Test status
Simulation time 244481887 ps
CPU time 1.05 seconds
Started Apr 25 12:58:05 PM PDT 24
Finished Apr 25 12:58:12 PM PDT 24
Peak memory 218336 kb
Host smart-d84433b5-0964-48f2-8683-b162db6b5d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123908494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1123908494
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.391695646
Short name T215
Test name
Test status
Simulation time 215746873 ps
CPU time 0.89 seconds
Started Apr 25 12:57:51 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 200692 kb
Host smart-7601965b-91a5-42f2-8b37-80a1db8e3a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391695646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.391695646
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3596161987
Short name T295
Test name
Test status
Simulation time 1749634622 ps
CPU time 6.31 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 201108 kb
Host smart-6aafd9e1-e8f1-43b9-8632-5fd579a2e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596161987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3596161987
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2761131464
Short name T291
Test name
Test status
Simulation time 103445039 ps
CPU time 1 seconds
Started Apr 25 12:58:02 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 200840 kb
Host smart-d14e1fef-2d03-4be6-b294-147d025c638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761131464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2761131464
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1335311932
Short name T327
Test name
Test status
Simulation time 119566929 ps
CPU time 1.21 seconds
Started Apr 25 12:57:46 PM PDT 24
Finished Apr 25 12:57:48 PM PDT 24
Peak memory 201036 kb
Host smart-52353b89-def3-45fc-ba0a-c2ca76e5a837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335311932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1335311932
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2721669271
Short name T167
Test name
Test status
Simulation time 236024529 ps
CPU time 1.35 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 200900 kb
Host smart-374104d4-42cf-4918-81fa-3c7ee4ef049f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721669271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2721669271
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3347629088
Short name T382
Test name
Test status
Simulation time 105449991 ps
CPU time 0.96 seconds
Started Apr 25 12:58:03 PM PDT 24
Finished Apr 25 12:58:06 PM PDT 24
Peak memory 200884 kb
Host smart-46519476-5321-419b-95b0-e9fbc5653111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347629088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3347629088
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1740000320
Short name T178
Test name
Test status
Simulation time 68235434 ps
CPU time 0.74 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 200728 kb
Host smart-91318940-452e-489c-93c4-69584c72239d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740000320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1740000320
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1058571307
Short name T506
Test name
Test status
Simulation time 2360374157 ps
CPU time 7.92 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:26 PM PDT 24
Peak memory 222488 kb
Host smart-03a2b617-88ba-4af7-88ee-04aa17ada05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058571307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1058571307
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3300927106
Short name T72
Test name
Test status
Simulation time 245115674 ps
CPU time 1.05 seconds
Started Apr 25 12:58:01 PM PDT 24
Finished Apr 25 12:58:04 PM PDT 24
Peak memory 218072 kb
Host smart-38d6707a-2758-46b8-a759-ff1486cd5f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300927106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3300927106
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3882872018
Short name T13
Test name
Test status
Simulation time 181829509 ps
CPU time 0.86 seconds
Started Apr 25 12:58:39 PM PDT 24
Finished Apr 25 12:58:43 PM PDT 24
Peak memory 200656 kb
Host smart-533908cd-073d-4e3f-967b-9eb2a10e69b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882872018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3882872018
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2678500999
Short name T533
Test name
Test status
Simulation time 1140749752 ps
CPU time 5.26 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 201200 kb
Host smart-9a382ce0-86f6-43a0-b4cc-511fa0363dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678500999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2678500999
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3619067720
Short name T271
Test name
Test status
Simulation time 152064754 ps
CPU time 1.18 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 200840 kb
Host smart-80454eeb-918d-4d83-af8a-c2b68b24c445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619067720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3619067720
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1291880007
Short name T74
Test name
Test status
Simulation time 258276293 ps
CPU time 1.55 seconds
Started Apr 25 12:57:46 PM PDT 24
Finished Apr 25 12:57:49 PM PDT 24
Peak memory 201036 kb
Host smart-b3ca1c49-c634-4720-abfb-52a25bfb426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291880007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1291880007
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3385984686
Short name T100
Test name
Test status
Simulation time 8846770145 ps
CPU time 29.03 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:47 PM PDT 24
Peak memory 210052 kb
Host smart-b154f18c-46f0-47e3-84bc-f6a8418f3ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385984686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3385984686
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3263974397
Short name T523
Test name
Test status
Simulation time 261574570 ps
CPU time 1.73 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:17 PM PDT 24
Peak memory 200820 kb
Host smart-cebb3608-1879-4d88-8b44-5d67ee418537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263974397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3263974397
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1761343170
Short name T505
Test name
Test status
Simulation time 183996916 ps
CPU time 1.21 seconds
Started Apr 25 12:58:02 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 200936 kb
Host smart-e6820d50-8623-4621-a606-9c3814b5af7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761343170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1761343170
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.495402879
Short name T414
Test name
Test status
Simulation time 68623595 ps
CPU time 0.81 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 200700 kb
Host smart-17493d8a-ae35-4e03-bac0-329861e26343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495402879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.495402879
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3319353974
Short name T191
Test name
Test status
Simulation time 244370788 ps
CPU time 1.21 seconds
Started Apr 25 12:58:01 PM PDT 24
Finished Apr 25 12:58:04 PM PDT 24
Peak memory 218020 kb
Host smart-6383168c-530d-46f0-9524-db96adfee482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319353974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3319353974
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1392629182
Short name T371
Test name
Test status
Simulation time 139397173 ps
CPU time 0.79 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 200700 kb
Host smart-5f049d23-d16f-4a03-8a32-acfdc9d05a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392629182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1392629182
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1264533816
Short name T93
Test name
Test status
Simulation time 933613570 ps
CPU time 4.58 seconds
Started Apr 25 12:58:16 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 201056 kb
Host smart-7ea99912-4faf-4aca-8c04-356bb0403bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264533816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1264533816
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.905547137
Short name T449
Test name
Test status
Simulation time 103740128 ps
CPU time 1.02 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 200884 kb
Host smart-86689d6d-fd0d-4453-9990-0a03de4c4e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905547137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.905547137
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2736293320
Short name T408
Test name
Test status
Simulation time 223992993 ps
CPU time 1.66 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 201056 kb
Host smart-30e64453-61ef-4740-b05c-55360be83c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736293320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2736293320
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1165527249
Short name T431
Test name
Test status
Simulation time 10576027949 ps
CPU time 36.74 seconds
Started Apr 25 12:58:03 PM PDT 24
Finished Apr 25 12:58:41 PM PDT 24
Peak memory 211008 kb
Host smart-e35eea12-53ad-4a30-9ad5-8d2d531e985f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165527249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1165527249
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.950709936
Short name T279
Test name
Test status
Simulation time 128371456 ps
CPU time 1.53 seconds
Started Apr 25 12:57:56 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 200804 kb
Host smart-945146bb-b84b-4fcc-9bb0-af72e09db47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950709936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.950709936
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2609177038
Short name T459
Test name
Test status
Simulation time 133400579 ps
CPU time 1.13 seconds
Started Apr 25 12:57:55 PM PDT 24
Finished Apr 25 12:58:00 PM PDT 24
Peak memory 200852 kb
Host smart-95db511a-6b95-4544-99e8-0ad09886880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609177038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2609177038
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3677946038
Short name T526
Test name
Test status
Simulation time 62065733 ps
CPU time 0.74 seconds
Started Apr 25 12:58:02 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 200676 kb
Host smart-85fe0a9c-339d-44b4-a114-886308010ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677946038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3677946038
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2158528101
Short name T44
Test name
Test status
Simulation time 1901382326 ps
CPU time 7 seconds
Started Apr 25 12:57:58 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 217588 kb
Host smart-89cfc355-7182-4ba5-86ca-c2a7250796a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158528101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2158528101
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2340866598
Short name T381
Test name
Test status
Simulation time 244911932 ps
CPU time 1.08 seconds
Started Apr 25 12:58:17 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 218012 kb
Host smart-f6a9bb06-d61b-4de5-a585-82f82a22c7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340866598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2340866598
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1772138556
Short name T195
Test name
Test status
Simulation time 94521840 ps
CPU time 0.76 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 200664 kb
Host smart-371a3f49-a856-4a44-bb75-a4e909242bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772138556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1772138556
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3790601717
Short name T95
Test name
Test status
Simulation time 1498343421 ps
CPU time 5.82 seconds
Started Apr 25 12:57:58 PM PDT 24
Finished Apr 25 12:58:06 PM PDT 24
Peak memory 201100 kb
Host smart-1971dcbc-26f9-4bee-a335-b8786f4b33ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790601717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3790601717
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3320717289
Short name T411
Test name
Test status
Simulation time 111279049 ps
CPU time 1 seconds
Started Apr 25 12:58:25 PM PDT 24
Finished Apr 25 12:58:28 PM PDT 24
Peak memory 200908 kb
Host smart-cd004b47-2410-41b8-9621-1c26972a3cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320717289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3320717289
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2213880226
Short name T379
Test name
Test status
Simulation time 246532411 ps
CPU time 1.52 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:58:02 PM PDT 24
Peak memory 201100 kb
Host smart-201a66c8-2aa1-4997-826e-230ce5831673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213880226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2213880226
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.4006990087
Short name T427
Test name
Test status
Simulation time 206913695 ps
CPU time 1.46 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:20 PM PDT 24
Peak memory 201040 kb
Host smart-c1322087-d0f4-4a56-b9dd-c649404c19c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006990087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4006990087
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1196660892
Short name T193
Test name
Test status
Simulation time 135748820 ps
CPU time 1.59 seconds
Started Apr 25 12:58:08 PM PDT 24
Finished Apr 25 12:58:11 PM PDT 24
Peak memory 209112 kb
Host smart-f0fe3d37-2d28-487f-8aa1-f89de72660c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196660892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1196660892
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3885888389
Short name T154
Test name
Test status
Simulation time 129205689 ps
CPU time 1 seconds
Started Apr 25 12:58:16 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 200840 kb
Host smart-cc831660-9f67-42a8-9e83-f67aafeb3600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885888389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3885888389
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.4144751435
Short name T399
Test name
Test status
Simulation time 56124055 ps
CPU time 0.69 seconds
Started Apr 25 12:58:01 PM PDT 24
Finished Apr 25 12:58:04 PM PDT 24
Peak memory 200712 kb
Host smart-6ac6572f-19b1-4ec9-8227-f3173863e4f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144751435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4144751435
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3171094777
Short name T347
Test name
Test status
Simulation time 1222670183 ps
CPU time 5.53 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 218664 kb
Host smart-9301df2a-05c3-45ca-b8ba-4b60b9155a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171094777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3171094777
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3981493930
Short name T209
Test name
Test status
Simulation time 243615394 ps
CPU time 1.12 seconds
Started Apr 25 12:57:58 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 218272 kb
Host smart-3d4568d0-5142-4853-9188-3d5c09a7ae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981493930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3981493930
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2305064767
Short name T218
Test name
Test status
Simulation time 131235249 ps
CPU time 0.84 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 200620 kb
Host smart-41a1c55d-73c4-42d4-82b5-66756fd690ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305064767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2305064767
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.4275222657
Short name T418
Test name
Test status
Simulation time 1443952984 ps
CPU time 5.66 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:58:02 PM PDT 24
Peak memory 200936 kb
Host smart-48e300fd-2060-400d-aaab-eb3cc30a6b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275222657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4275222657
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3856349438
Short name T421
Test name
Test status
Simulation time 187160347 ps
CPU time 1.39 seconds
Started Apr 25 12:58:04 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 201072 kb
Host smart-24b606be-74a9-4b46-833c-e3e6e2610d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856349438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3856349438
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1826503894
Short name T542
Test name
Test status
Simulation time 10548454105 ps
CPU time 34.99 seconds
Started Apr 25 12:58:05 PM PDT 24
Finished Apr 25 12:58:41 PM PDT 24
Peak memory 209444 kb
Host smart-7d1354ca-faef-4024-bd55-c23f64b783cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826503894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1826503894
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.197320723
Short name T275
Test name
Test status
Simulation time 131028835 ps
CPU time 1.58 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:18 PM PDT 24
Peak memory 209120 kb
Host smart-6c09e1f1-aef1-49fa-b596-d76cad39a290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197320723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.197320723
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3989306640
Short name T219
Test name
Test status
Simulation time 230323542 ps
CPU time 1.32 seconds
Started Apr 25 12:57:54 PM PDT 24
Finished Apr 25 12:57:59 PM PDT 24
Peak memory 200860 kb
Host smart-b2ec0581-4c1b-4b92-9c88-04d4e22c48cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989306640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3989306640
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.405125004
Short name T512
Test name
Test status
Simulation time 62612036 ps
CPU time 0.76 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 200764 kb
Host smart-6bda7d7f-d210-4545-9c3a-998a76ba0e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405125004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.405125004
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3160380662
Short name T499
Test name
Test status
Simulation time 2163836610 ps
CPU time 8.2 seconds
Started Apr 25 12:58:34 PM PDT 24
Finished Apr 25 12:58:44 PM PDT 24
Peak memory 218768 kb
Host smart-3098649c-348a-4a1b-9bf3-b5370abf1fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160380662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3160380662
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2597506207
Short name T337
Test name
Test status
Simulation time 243698845 ps
CPU time 1.12 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 218300 kb
Host smart-3330d049-d0dd-446f-bb19-d5839543f512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597506207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2597506207
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1837006775
Short name T168
Test name
Test status
Simulation time 135449428 ps
CPU time 0.81 seconds
Started Apr 25 12:58:06 PM PDT 24
Finished Apr 25 12:58:08 PM PDT 24
Peak memory 200660 kb
Host smart-17e34fe7-9ce0-48fe-8ece-208f0fbc996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837006775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1837006775
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2446423318
Short name T276
Test name
Test status
Simulation time 1315839898 ps
CPU time 5.24 seconds
Started Apr 25 12:58:05 PM PDT 24
Finished Apr 25 12:58:12 PM PDT 24
Peak memory 201080 kb
Host smart-f540042f-509a-4c96-a2af-aaf60e2f4d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446423318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2446423318
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.49061943
Short name T241
Test name
Test status
Simulation time 96414300 ps
CPU time 1 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 200780 kb
Host smart-5ef4c59a-0b75-4cd3-b68e-7181a073eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49061943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.49061943
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3518340010
Short name T85
Test name
Test status
Simulation time 234446206 ps
CPU time 1.41 seconds
Started Apr 25 12:58:10 PM PDT 24
Finished Apr 25 12:58:13 PM PDT 24
Peak memory 201072 kb
Host smart-4d72f513-e347-46af-a72b-650c02fb4173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518340010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3518340010
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3832268445
Short name T185
Test name
Test status
Simulation time 6973549512 ps
CPU time 27.85 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:45 PM PDT 24
Peak memory 201212 kb
Host smart-1626afa3-46f3-4a22-a2b1-c5072a353bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832268445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3832268445
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.4201926558
Short name T439
Test name
Test status
Simulation time 553415034 ps
CPU time 2.74 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:02 PM PDT 24
Peak memory 200456 kb
Host smart-36c64675-8236-448b-b6a4-f7e29814293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201926558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4201926558
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3775587016
Short name T479
Test name
Test status
Simulation time 90693502 ps
CPU time 0.85 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:20 PM PDT 24
Peak memory 200848 kb
Host smart-bd0e3582-7db3-40d7-aef2-a86be81e42ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775587016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3775587016
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2430317616
Short name T248
Test name
Test status
Simulation time 80652395 ps
CPU time 0.82 seconds
Started Apr 25 12:58:07 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 200724 kb
Host smart-f8fd8c06-c63d-43f4-bcfd-420ede5f877f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430317616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2430317616
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3446702366
Short name T25
Test name
Test status
Simulation time 2375926325 ps
CPU time 8.13 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:20 PM PDT 24
Peak memory 218276 kb
Host smart-f29b6fc7-b7ff-47a9-9b8e-cb9e0b5ef9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446702366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3446702366
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3176104254
Short name T497
Test name
Test status
Simulation time 244951568 ps
CPU time 1.03 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 218032 kb
Host smart-bf588a35-96f2-49ba-a240-da253f524405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176104254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3176104254
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1645024753
Short name T417
Test name
Test status
Simulation time 151788008 ps
CPU time 0.81 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 200684 kb
Host smart-7b218396-bbae-4b0e-8e8a-f74e51c67522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645024753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1645024753
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.950565578
Short name T305
Test name
Test status
Simulation time 707831992 ps
CPU time 3.75 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:58:53 PM PDT 24
Peak memory 201128 kb
Host smart-43b0f4a5-c0a1-474c-9119-d0d737009fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950565578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.950565578
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3819958531
Short name T341
Test name
Test status
Simulation time 152121974 ps
CPU time 1.21 seconds
Started Apr 25 12:58:19 PM PDT 24
Finished Apr 25 12:58:22 PM PDT 24
Peak memory 200836 kb
Host smart-b882ef9e-99c7-4e67-8aab-2bdfe4cf5e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819958531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3819958531
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1557753281
Short name T515
Test name
Test status
Simulation time 199323152 ps
CPU time 1.33 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 201108 kb
Host smart-53f2a482-81a2-4398-b4f8-a47999a829f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557753281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1557753281
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3376120404
Short name T435
Test name
Test status
Simulation time 2147383010 ps
CPU time 8.63 seconds
Started Apr 25 12:58:13 PM PDT 24
Finished Apr 25 12:58:25 PM PDT 24
Peak memory 201084 kb
Host smart-df6eab46-0077-49c8-9d0e-36985f45031c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376120404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3376120404
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2493490080
Short name T205
Test name
Test status
Simulation time 407528818 ps
CPU time 2.28 seconds
Started Apr 25 12:57:51 PM PDT 24
Finished Apr 25 12:57:57 PM PDT 24
Peak memory 200880 kb
Host smart-3464c259-d5b6-4ca2-a1fb-211a57bb46ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493490080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2493490080
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.768767498
Short name T335
Test name
Test status
Simulation time 130416036 ps
CPU time 0.99 seconds
Started Apr 25 12:58:24 PM PDT 24
Finished Apr 25 12:58:27 PM PDT 24
Peak memory 200924 kb
Host smart-4d36dd19-9136-474b-ae64-38200366a635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768767498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.768767498
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3415738399
Short name T397
Test name
Test status
Simulation time 63863027 ps
CPU time 0.71 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:57:56 PM PDT 24
Peak memory 200712 kb
Host smart-f531773e-aeb5-4f8c-900a-19cfdd07514b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415738399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3415738399
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.210989759
Short name T255
Test name
Test status
Simulation time 1870383405 ps
CPU time 7.05 seconds
Started Apr 25 12:57:55 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 218032 kb
Host smart-4aaed756-3dce-4f31-89ea-2745bcf31e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210989759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.210989759
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.4023501883
Short name T390
Test name
Test status
Simulation time 244040205 ps
CPU time 1.23 seconds
Started Apr 25 12:58:18 PM PDT 24
Finished Apr 25 12:58:22 PM PDT 24
Peak memory 218220 kb
Host smart-f2d933e3-3b72-45de-8b79-f4db86aa5c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023501883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.4023501883
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1147913813
Short name T354
Test name
Test status
Simulation time 79746507 ps
CPU time 0.84 seconds
Started Apr 25 12:58:20 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 200700 kb
Host smart-2d6d80dd-8158-4b81-8abc-0be635a83386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147913813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1147913813
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1479229659
Short name T541
Test name
Test status
Simulation time 1132701300 ps
CPU time 5.4 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 201056 kb
Host smart-8d9c9fc4-55f3-40b1-83f9-12528c77b167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479229659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1479229659
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.4292654867
Short name T478
Test name
Test status
Simulation time 103198727 ps
CPU time 1.02 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 200820 kb
Host smart-111923ca-efc4-4a05-97d9-a160e3b54abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292654867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.4292654867
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.870179425
Short name T312
Test name
Test status
Simulation time 253290680 ps
CPU time 1.43 seconds
Started Apr 25 12:58:17 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 201076 kb
Host smart-b7227d41-a666-4eb1-abdd-24aa69adcfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870179425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.870179425
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2760366001
Short name T37
Test name
Test status
Simulation time 6097414665 ps
CPU time 20.86 seconds
Started Apr 25 12:58:04 PM PDT 24
Finished Apr 25 12:58:27 PM PDT 24
Peak memory 201124 kb
Host smart-ddb6aafb-8c57-4487-9814-7f70f81019f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760366001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2760366001
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3921701502
Short name T353
Test name
Test status
Simulation time 388317060 ps
CPU time 2.17 seconds
Started Apr 25 12:58:35 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 200892 kb
Host smart-27378c0b-8b06-435d-8d44-2bfc383837f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921701502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3921701502
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2212643346
Short name T34
Test name
Test status
Simulation time 145122490 ps
CPU time 1.07 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 200916 kb
Host smart-4fb5103d-6038-495e-9ed6-504aed50f9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212643346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2212643346
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1570271556
Short name T365
Test name
Test status
Simulation time 83857809 ps
CPU time 0.82 seconds
Started Apr 25 12:58:17 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 200636 kb
Host smart-5efa872f-ebd8-4054-8ba2-0ef535b005ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570271556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1570271556
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3615519041
Short name T26
Test name
Test status
Simulation time 1897010285 ps
CPU time 7.08 seconds
Started Apr 25 12:58:20 PM PDT 24
Finished Apr 25 12:58:29 PM PDT 24
Peak memory 218576 kb
Host smart-0c9d9950-7593-4107-80ec-6b4c0a13c722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615519041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3615519041
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2520341873
Short name T453
Test name
Test status
Simulation time 243917070 ps
CPU time 1.11 seconds
Started Apr 25 12:58:03 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 218024 kb
Host smart-acd255d6-e65b-43a0-bac1-74e30cd84759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520341873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2520341873
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2312606564
Short name T391
Test name
Test status
Simulation time 209071020 ps
CPU time 0.84 seconds
Started Apr 25 12:58:03 PM PDT 24
Finished Apr 25 12:58:06 PM PDT 24
Peak memory 200684 kb
Host smart-09f0a8f2-8b27-42ea-862f-dc48bb5a0ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312606564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2312606564
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3257234079
Short name T519
Test name
Test status
Simulation time 1591792013 ps
CPU time 5.57 seconds
Started Apr 25 12:58:28 PM PDT 24
Finished Apr 25 12:58:37 PM PDT 24
Peak memory 201072 kb
Host smart-c7089631-e146-45ac-81fd-28c3b6c06e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257234079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3257234079
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2638924077
Short name T513
Test name
Test status
Simulation time 94903489 ps
CPU time 1 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 200900 kb
Host smart-a788e58b-4c10-4fb5-97f6-ad10a384c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638924077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2638924077
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2455094577
Short name T189
Test name
Test status
Simulation time 252537531 ps
CPU time 1.45 seconds
Started Apr 25 12:58:03 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 200968 kb
Host smart-2086b0f2-e12c-4d72-9146-13bdc9316c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455094577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2455094577
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3298125595
Short name T470
Test name
Test status
Simulation time 3360058250 ps
CPU time 13.17 seconds
Started Apr 25 12:58:07 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 201176 kb
Host smart-cca5fcda-3baa-476a-b12a-674e4d04d128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298125595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3298125595
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3358021065
Short name T403
Test name
Test status
Simulation time 433411580 ps
CPU time 2.4 seconds
Started Apr 25 12:58:19 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 209092 kb
Host smart-3eb185e5-5b97-44d2-8054-6a05433bc529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358021065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3358021065
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.4109405521
Short name T389
Test name
Test status
Simulation time 205955197 ps
CPU time 1.21 seconds
Started Apr 25 12:58:17 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 200892 kb
Host smart-6742ec89-c4b3-466b-bd6d-9a194e2e444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109405521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.4109405521
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2199322515
Short name T147
Test name
Test status
Simulation time 75324218 ps
CPU time 0.75 seconds
Started Apr 25 12:57:20 PM PDT 24
Finished Apr 25 12:57:22 PM PDT 24
Peak memory 200704 kb
Host smart-935ef5c6-5dba-452e-8384-2d2ca9a827b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199322515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2199322515
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.163667897
Short name T375
Test name
Test status
Simulation time 1233001919 ps
CPU time 5.46 seconds
Started Apr 25 12:57:53 PM PDT 24
Finished Apr 25 12:58:02 PM PDT 24
Peak memory 218628 kb
Host smart-bc254384-588d-41e6-ae4c-9fd573e21db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163667897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.163667897
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.50947365
Short name T207
Test name
Test status
Simulation time 243830540 ps
CPU time 1.15 seconds
Started Apr 25 12:57:18 PM PDT 24
Finished Apr 25 12:57:20 PM PDT 24
Peak memory 218008 kb
Host smart-5e63f0e9-c58d-4a9c-b870-d628668cd08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50947365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.50947365
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3186564797
Short name T441
Test name
Test status
Simulation time 161113759 ps
CPU time 0.85 seconds
Started Apr 25 12:57:22 PM PDT 24
Finished Apr 25 12:57:24 PM PDT 24
Peak memory 200700 kb
Host smart-0285f81a-6a7f-44f4-ace6-ccfa97997829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186564797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3186564797
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1794130860
Short name T462
Test name
Test status
Simulation time 864278572 ps
CPU time 4.66 seconds
Started Apr 25 12:57:38 PM PDT 24
Finished Apr 25 12:57:44 PM PDT 24
Peak memory 201068 kb
Host smart-c0f93934-ca92-4b43-84c6-f45eb9787c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794130860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1794130860
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.4026858682
Short name T64
Test name
Test status
Simulation time 17244713941 ps
CPU time 25.35 seconds
Started Apr 25 12:57:18 PM PDT 24
Finished Apr 25 12:57:45 PM PDT 24
Peak memory 218056 kb
Host smart-503b7701-3486-4cb3-b48b-6b92950a4149
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026858682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.4026858682
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2513827312
Short name T310
Test name
Test status
Simulation time 185080122 ps
CPU time 1.21 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:32 PM PDT 24
Peak memory 200932 kb
Host smart-0b542d00-c47b-45c5-8cb4-fa324939c37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513827312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2513827312
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3870550503
Short name T261
Test name
Test status
Simulation time 123820769 ps
CPU time 1.22 seconds
Started Apr 25 12:57:41 PM PDT 24
Finished Apr 25 12:57:43 PM PDT 24
Peak memory 201056 kb
Host smart-97a7db5e-434d-43f1-9efc-c1d2cf362950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870550503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3870550503
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3313515471
Short name T367
Test name
Test status
Simulation time 4586074290 ps
CPU time 15.18 seconds
Started Apr 25 12:57:19 PM PDT 24
Finished Apr 25 12:57:35 PM PDT 24
Peak memory 201096 kb
Host smart-e9b2f523-75c1-473c-9ab9-78060b677f9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313515471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3313515471
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1365191705
Short name T80
Test name
Test status
Simulation time 130242022 ps
CPU time 1.59 seconds
Started Apr 25 12:57:20 PM PDT 24
Finished Apr 25 12:57:23 PM PDT 24
Peak memory 200892 kb
Host smart-2c2f5be8-f915-403d-9bab-34afd36c9805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365191705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1365191705
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.682599866
Short name T438
Test name
Test status
Simulation time 90624044 ps
CPU time 0.91 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:32 PM PDT 24
Peak memory 200984 kb
Host smart-30fb220b-1774-4ca7-8ba8-467fc5195c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682599866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.682599866
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.4105582659
Short name T490
Test name
Test status
Simulation time 78363284 ps
CPU time 0.78 seconds
Started Apr 25 12:57:59 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 200712 kb
Host smart-e94e97ed-d87d-454b-88d6-81ef1280f52b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105582659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.4105582659
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.480024319
Short name T369
Test name
Test status
Simulation time 2347891996 ps
CPU time 8.22 seconds
Started Apr 25 12:58:42 PM PDT 24
Finished Apr 25 12:58:52 PM PDT 24
Peak memory 222748 kb
Host smart-5479d4c1-7a6b-40bd-b64e-e695bdce3020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480024319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.480024319
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1427761315
Short name T223
Test name
Test status
Simulation time 244913823 ps
CPU time 1.07 seconds
Started Apr 25 12:58:08 PM PDT 24
Finished Apr 25 12:58:11 PM PDT 24
Peak memory 218016 kb
Host smart-779aa2e9-463c-4704-8bae-dfba2e85eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427761315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1427761315
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3640051601
Short name T287
Test name
Test status
Simulation time 99856938 ps
CPU time 0.79 seconds
Started Apr 25 12:58:06 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 200656 kb
Host smart-23e7d99b-a8a9-4771-b83c-2eff13e15d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640051601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3640051601
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1166955647
Short name T434
Test name
Test status
Simulation time 959364821 ps
CPU time 4.84 seconds
Started Apr 25 12:58:03 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 201076 kb
Host smart-4c83bbc6-db7e-4d57-9a28-5d27eeff9357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166955647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1166955647
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.747472969
Short name T210
Test name
Test status
Simulation time 185314985 ps
CPU time 1.19 seconds
Started Apr 25 12:58:06 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 200840 kb
Host smart-37b74635-c506-4219-a1b5-cfee7103551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747472969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.747472969
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3933359935
Short name T214
Test name
Test status
Simulation time 201481541 ps
CPU time 1.35 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 201080 kb
Host smart-c992e4fb-5f7b-439c-8eed-5efa4bf6ed2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933359935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3933359935
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2388250672
Short name T496
Test name
Test status
Simulation time 3936975253 ps
CPU time 17.2 seconds
Started Apr 25 12:57:55 PM PDT 24
Finished Apr 25 12:58:15 PM PDT 24
Peak memory 201236 kb
Host smart-c656da04-8abe-4caa-b681-282b1bc90227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388250672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2388250672
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3817201059
Short name T412
Test name
Test status
Simulation time 138998000 ps
CPU time 1.65 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 209044 kb
Host smart-bb1f5d85-685a-4ab6-8c3a-f756c6de0fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817201059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3817201059
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3588953219
Short name T473
Test name
Test status
Simulation time 129205741 ps
CPU time 1.06 seconds
Started Apr 25 12:58:23 PM PDT 24
Finished Apr 25 12:58:26 PM PDT 24
Peak memory 200868 kb
Host smart-7a2a69e0-c2e6-4b86-8387-509e20bc07ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588953219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3588953219
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.205261337
Short name T278
Test name
Test status
Simulation time 84741052 ps
CPU time 0.85 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 200736 kb
Host smart-26cda9ad-cd28-4923-adbf-30f883762b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205261337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.205261337
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.410146188
Short name T42
Test name
Test status
Simulation time 1889260117 ps
CPU time 7.31 seconds
Started Apr 25 12:57:59 PM PDT 24
Finished Apr 25 12:58:08 PM PDT 24
Peak memory 230500 kb
Host smart-fcf23ae7-ac0f-4690-97a9-68da58eb460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410146188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.410146188
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3200524194
Short name T339
Test name
Test status
Simulation time 243732455 ps
CPU time 1.1 seconds
Started Apr 25 12:57:54 PM PDT 24
Finished Apr 25 12:57:59 PM PDT 24
Peak memory 218076 kb
Host smart-74b79848-ec6f-4fc6-8e60-629bdf57f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200524194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3200524194
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.372606283
Short name T216
Test name
Test status
Simulation time 193615768 ps
CPU time 0.92 seconds
Started Apr 25 12:58:07 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 200616 kb
Host smart-a0dfe514-f075-4013-8808-f79e9a1ee59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372606283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.372606283
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.137163414
Short name T450
Test name
Test status
Simulation time 857826632 ps
CPU time 4.43 seconds
Started Apr 25 12:57:52 PM PDT 24
Finished Apr 25 12:58:00 PM PDT 24
Peak memory 200968 kb
Host smart-5af5c44d-cae6-48c2-9c09-89329b11c6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137163414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.137163414
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.36977150
Short name T502
Test name
Test status
Simulation time 183875254 ps
CPU time 1.22 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 200864 kb
Host smart-0763d2d2-9564-45c8-b5b3-97483a474f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36977150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.36977150
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1825191717
Short name T131
Test name
Test status
Simulation time 253190171 ps
CPU time 1.49 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 201128 kb
Host smart-0a3787c5-61da-4b98-9ae7-b39c69cc0938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825191717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1825191717
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1156177072
Short name T148
Test name
Test status
Simulation time 444075574 ps
CPU time 1.84 seconds
Started Apr 25 12:58:03 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 201060 kb
Host smart-be6957b4-223b-4344-8d03-bf56b743da7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156177072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1156177072
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2858442943
Short name T289
Test name
Test status
Simulation time 302750465 ps
CPU time 2.11 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:37 PM PDT 24
Peak memory 209056 kb
Host smart-67a1dabb-4f73-4891-a5d7-62ff12f92400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858442943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2858442943
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2666609634
Short name T173
Test name
Test status
Simulation time 150329101 ps
CPU time 1.02 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 200852 kb
Host smart-d3763f6e-be9b-41d7-a4fa-426c0aaea383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666609634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2666609634
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1119746241
Short name T47
Test name
Test status
Simulation time 55192148 ps
CPU time 0.81 seconds
Started Apr 25 12:58:18 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 200712 kb
Host smart-4db87272-3cc9-49c6-8d60-f24d721d5c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119746241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1119746241
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2622938039
Short name T51
Test name
Test status
Simulation time 1877302971 ps
CPU time 7.33 seconds
Started Apr 25 12:58:28 PM PDT 24
Finished Apr 25 12:58:38 PM PDT 24
Peak memory 218592 kb
Host smart-bddfa86b-7022-4f02-8234-043eb1fc070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622938039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2622938039
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.926418086
Short name T486
Test name
Test status
Simulation time 244875511 ps
CPU time 1.03 seconds
Started Apr 25 12:58:27 PM PDT 24
Finished Apr 25 12:58:30 PM PDT 24
Peak memory 218212 kb
Host smart-68aed5b4-5e99-48f1-a42f-e5812130cbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926418086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.926418086
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3991681377
Short name T16
Test name
Test status
Simulation time 179069325 ps
CPU time 0.89 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:18 PM PDT 24
Peak memory 200696 kb
Host smart-57cb158a-d33f-4807-8d96-824312aefaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991681377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3991681377
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1611238722
Short name T530
Test name
Test status
Simulation time 1741666675 ps
CPU time 6.42 seconds
Started Apr 25 12:58:09 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 201036 kb
Host smart-fbf528ad-83be-44b5-a4ba-031b2eb1221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611238722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1611238722
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1137292983
Short name T77
Test name
Test status
Simulation time 180622577 ps
CPU time 1.15 seconds
Started Apr 25 12:58:09 PM PDT 24
Finished Apr 25 12:58:12 PM PDT 24
Peak memory 200856 kb
Host smart-bcbb62aa-606d-4a3b-aaf0-447124723ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137292983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1137292983
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1024266479
Short name T83
Test name
Test status
Simulation time 113490237 ps
CPU time 1.17 seconds
Started Apr 25 12:58:13 PM PDT 24
Finished Apr 25 12:58:18 PM PDT 24
Peak memory 200936 kb
Host smart-104a118c-fd05-4ad9-8dfc-2af4744c78eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024266479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1024266479
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2923889218
Short name T247
Test name
Test status
Simulation time 878084754 ps
CPU time 4.46 seconds
Started Apr 25 12:58:24 PM PDT 24
Finished Apr 25 12:58:30 PM PDT 24
Peak memory 201112 kb
Host smart-429f3a46-a1f1-4276-b67e-c54b543ee58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923889218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2923889218
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1315757388
Short name T288
Test name
Test status
Simulation time 303277615 ps
CPU time 2.03 seconds
Started Apr 25 12:58:06 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 209092 kb
Host smart-52898c71-3377-450a-ab37-992d592eceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315757388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1315757388
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.864411938
Short name T303
Test name
Test status
Simulation time 118528461 ps
CPU time 0.94 seconds
Started Apr 25 12:58:21 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 200892 kb
Host smart-80792089-7436-4ee6-87ce-bc0b22767abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864411938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.864411938
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.197061301
Short name T246
Test name
Test status
Simulation time 77860558 ps
CPU time 0.77 seconds
Started Apr 25 12:58:07 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 200688 kb
Host smart-1db2b496-a083-463b-bdc6-423dbb598621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197061301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.197061301
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2064925199
Short name T466
Test name
Test status
Simulation time 1235591663 ps
CPU time 5.78 seconds
Started Apr 25 12:58:35 PM PDT 24
Finished Apr 25 12:58:42 PM PDT 24
Peak memory 222688 kb
Host smart-c8be2302-1660-4d6e-893a-b07482a8f164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064925199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2064925199
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1718839129
Short name T358
Test name
Test status
Simulation time 244440871 ps
CPU time 1.09 seconds
Started Apr 25 12:57:59 PM PDT 24
Finished Apr 25 12:58:02 PM PDT 24
Peak memory 218040 kb
Host smart-e88283cf-038b-4e74-b3f5-cfdf147565f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718839129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1718839129
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1786314227
Short name T76
Test name
Test status
Simulation time 186784671 ps
CPU time 0.87 seconds
Started Apr 25 12:57:57 PM PDT 24
Finished Apr 25 12:58:00 PM PDT 24
Peak memory 200668 kb
Host smart-4d531965-4995-4662-a432-87a19196bfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786314227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1786314227
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2380251570
Short name T126
Test name
Test status
Simulation time 1454469045 ps
CPU time 5.82 seconds
Started Apr 25 12:58:01 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 201144 kb
Host smart-65cb82d6-0cd7-4743-86f7-31f30a180792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380251570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2380251570
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.973827385
Short name T249
Test name
Test status
Simulation time 181740855 ps
CPU time 1.24 seconds
Started Apr 25 12:58:00 PM PDT 24
Finished Apr 25 12:58:03 PM PDT 24
Peak memory 200916 kb
Host smart-f409e277-bd0c-4d93-82f0-6c9bce23fc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973827385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.973827385
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1474440939
Short name T429
Test name
Test status
Simulation time 109493758 ps
CPU time 1.18 seconds
Started Apr 25 12:58:21 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 201052 kb
Host smart-dd61f7cc-4de1-4d92-b4d5-f609cfcf7bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474440939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1474440939
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1616542154
Short name T476
Test name
Test status
Simulation time 3152645217 ps
CPU time 15.21 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 201120 kb
Host smart-a8452176-0a5e-49cf-8dd9-38490433dc5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616542154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1616542154
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2967378956
Short name T70
Test name
Test status
Simulation time 541612163 ps
CPU time 2.79 seconds
Started Apr 25 12:58:02 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 200860 kb
Host smart-d72fee64-c618-4928-a215-721e5f116b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967378956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2967378956
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4230700088
Short name T165
Test name
Test status
Simulation time 77702318 ps
CPU time 0.89 seconds
Started Apr 25 12:58:18 PM PDT 24
Finished Apr 25 12:58:22 PM PDT 24
Peak memory 200896 kb
Host smart-15de9c73-0f46-4517-a8f3-8aee3f608407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230700088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4230700088
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3933278748
Short name T142
Test name
Test status
Simulation time 73203156 ps
CPU time 0.76 seconds
Started Apr 25 12:58:04 PM PDT 24
Finished Apr 25 12:58:06 PM PDT 24
Peak memory 200800 kb
Host smart-4c7e586b-e9f0-4e7c-8e86-6355c94a4d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933278748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3933278748
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.587332523
Short name T54
Test name
Test status
Simulation time 1224670800 ps
CPU time 6.01 seconds
Started Apr 25 12:58:09 PM PDT 24
Finished Apr 25 12:58:17 PM PDT 24
Peak memory 217660 kb
Host smart-44fe0d91-a886-42c9-a234-33d1215a4fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587332523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.587332523
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3453720670
Short name T325
Test name
Test status
Simulation time 244110745 ps
CPU time 1.05 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 218040 kb
Host smart-843f7273-c99f-4577-b68a-8d3b445defe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453720670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3453720670
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2654591695
Short name T162
Test name
Test status
Simulation time 83731178 ps
CPU time 0.79 seconds
Started Apr 25 12:58:01 PM PDT 24
Finished Apr 25 12:58:04 PM PDT 24
Peak memory 200652 kb
Host smart-104fd954-34f2-4d84-ac92-3a8f3038627c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654591695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2654591695
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2333962539
Short name T125
Test name
Test status
Simulation time 1469135388 ps
CPU time 5.48 seconds
Started Apr 25 12:58:08 PM PDT 24
Finished Apr 25 12:58:16 PM PDT 24
Peak memory 201052 kb
Host smart-9a091c7d-0f60-49c5-b118-e073fc02821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333962539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2333962539
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2807479400
Short name T307
Test name
Test status
Simulation time 104814026 ps
CPU time 1.01 seconds
Started Apr 25 12:58:02 PM PDT 24
Finished Apr 25 12:58:05 PM PDT 24
Peak memory 200852 kb
Host smart-c7eddc9c-0e55-4865-9df5-cb33ff69b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807479400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2807479400
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2250141520
Short name T385
Test name
Test status
Simulation time 224527993 ps
CPU time 1.45 seconds
Started Apr 25 12:57:58 PM PDT 24
Finished Apr 25 12:58:01 PM PDT 24
Peak memory 201100 kb
Host smart-b8e28b90-2db7-402d-a5b7-50f7ff6a6b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250141520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2250141520
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1014889823
Short name T370
Test name
Test status
Simulation time 1661799091 ps
CPU time 6.19 seconds
Started Apr 25 12:58:02 PM PDT 24
Finished Apr 25 12:58:10 PM PDT 24
Peak memory 201016 kb
Host smart-b013433b-fb8e-4c1f-b241-46d7e64470ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014889823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1014889823
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2582917445
Short name T350
Test name
Test status
Simulation time 358234032 ps
CPU time 1.99 seconds
Started Apr 25 12:58:06 PM PDT 24
Finished Apr 25 12:58:10 PM PDT 24
Peak memory 200796 kb
Host smart-222ec505-5607-46a8-96b9-c4221d3f326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582917445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2582917445
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1733541510
Short name T362
Test name
Test status
Simulation time 147870913 ps
CPU time 1 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:16 PM PDT 24
Peak memory 200892 kb
Host smart-8ec3300c-5caa-46a1-ba96-94620e24e97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733541510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1733541510
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.339994828
Short name T503
Test name
Test status
Simulation time 56204320 ps
CPU time 0.69 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 200712 kb
Host smart-80701506-3278-4d44-8b8f-77da4be4ff76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339994828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.339994828
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.527127944
Short name T224
Test name
Test status
Simulation time 2159338573 ps
CPU time 8.08 seconds
Started Apr 25 12:58:13 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 218780 kb
Host smart-e659ee0a-5b16-4058-a317-d7bb62759cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527127944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.527127944
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2808011402
Short name T326
Test name
Test status
Simulation time 244703518 ps
CPU time 1.04 seconds
Started Apr 25 12:57:54 PM PDT 24
Finished Apr 25 12:57:58 PM PDT 24
Peak memory 218076 kb
Host smart-cfce58ef-0a5d-4c81-9f5c-082046018019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808011402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2808011402
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1476235228
Short name T172
Test name
Test status
Simulation time 93525327 ps
CPU time 0.75 seconds
Started Apr 25 12:58:30 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 200680 kb
Host smart-a874b02d-5f94-416d-942c-728a6fe40292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476235228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1476235228
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3852996550
Short name T39
Test name
Test status
Simulation time 1840133457 ps
CPU time 6.9 seconds
Started Apr 25 12:58:05 PM PDT 24
Finished Apr 25 12:58:13 PM PDT 24
Peak memory 201076 kb
Host smart-b599764e-f02d-4583-8733-1c505f3a049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852996550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3852996550
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1218566170
Short name T528
Test name
Test status
Simulation time 175117753 ps
CPU time 1.29 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 200868 kb
Host smart-084df462-f775-4899-843b-aad71c691fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218566170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1218566170
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2509342727
Short name T180
Test name
Test status
Simulation time 118582297 ps
CPU time 1.12 seconds
Started Apr 25 12:58:03 PM PDT 24
Finished Apr 25 12:58:06 PM PDT 24
Peak memory 201072 kb
Host smart-a92893f1-b8f4-4076-a86e-07000eb4297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509342727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2509342727
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.176174317
Short name T413
Test name
Test status
Simulation time 3374966589 ps
CPU time 15.59 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 209400 kb
Host smart-c30f34de-a427-41c2-885c-efa291840d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176174317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.176174317
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.43007198
Short name T319
Test name
Test status
Simulation time 122399545 ps
CPU time 1.56 seconds
Started Apr 25 12:58:17 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 209076 kb
Host smart-176ba4f4-6613-470b-8adc-1fc2ed26967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43007198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.43007198
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2936531206
Short name T373
Test name
Test status
Simulation time 227648245 ps
CPU time 1.3 seconds
Started Apr 25 12:58:06 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 200900 kb
Host smart-c19b84af-90e5-43ca-ba52-444516f0334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936531206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2936531206
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1647547922
Short name T141
Test name
Test status
Simulation time 88704367 ps
CPU time 0.84 seconds
Started Apr 25 12:58:25 PM PDT 24
Finished Apr 25 12:58:28 PM PDT 24
Peak memory 200696 kb
Host smart-3aaa4d26-0987-4c63-93ce-89dd40447488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647547922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1647547922
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.247594756
Short name T292
Test name
Test status
Simulation time 2181372835 ps
CPU time 8.12 seconds
Started Apr 25 12:58:13 PM PDT 24
Finished Apr 25 12:58:25 PM PDT 24
Peak memory 217696 kb
Host smart-bb628ae0-796c-4b36-89cd-bf12473c32ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247594756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.247594756
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.602972839
Short name T197
Test name
Test status
Simulation time 244125255 ps
CPU time 1.1 seconds
Started Apr 25 12:58:05 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 218276 kb
Host smart-fe20de03-ac63-4a1b-a021-a1c8cfff6e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602972839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.602972839
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1527431226
Short name T166
Test name
Test status
Simulation time 155525286 ps
CPU time 0.89 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:17 PM PDT 24
Peak memory 200628 kb
Host smart-6e0665a5-4d19-45d5-b004-3fb6e6595cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527431226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1527431226
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3171914070
Short name T374
Test name
Test status
Simulation time 1668004210 ps
CPU time 5.96 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 201088 kb
Host smart-a22ec86b-922e-4445-9542-498d5a637e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171914070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3171914070
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1434782655
Short name T20
Test name
Test status
Simulation time 184325847 ps
CPU time 1.26 seconds
Started Apr 25 12:58:05 PM PDT 24
Finished Apr 25 12:58:08 PM PDT 24
Peak memory 200856 kb
Host smart-0d349c12-41c5-4cfe-9a24-ece868647eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434782655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1434782655
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4078737009
Short name T330
Test name
Test status
Simulation time 205108720 ps
CPU time 1.44 seconds
Started Apr 25 12:58:07 PM PDT 24
Finished Apr 25 12:58:10 PM PDT 24
Peak memory 201116 kb
Host smart-149a722c-1eda-411d-b54a-aacf6b962deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078737009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4078737009
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2839291351
Short name T273
Test name
Test status
Simulation time 4372974816 ps
CPU time 14.43 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:49 PM PDT 24
Peak memory 210084 kb
Host smart-0abb621d-1afe-4365-b6a3-2447827b066b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839291351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2839291351
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3701458736
Short name T517
Test name
Test status
Simulation time 151571816 ps
CPU time 1.95 seconds
Started Apr 25 12:58:19 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 200880 kb
Host smart-ea41d583-c6a7-43b3-9130-b1c030180b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701458736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3701458736
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2444648263
Short name T130
Test name
Test status
Simulation time 274288240 ps
CPU time 1.46 seconds
Started Apr 25 12:58:27 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 200892 kb
Host smart-65b0cf98-c3d0-4c08-94c7-562b77eba764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444648263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2444648263
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3462690757
Short name T169
Test name
Test status
Simulation time 59702649 ps
CPU time 0.74 seconds
Started Apr 25 12:58:24 PM PDT 24
Finished Apr 25 12:58:27 PM PDT 24
Peak memory 200428 kb
Host smart-89bf7f84-5fd4-4a02-9ce4-559d062afe96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462690757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3462690757
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3780119034
Short name T355
Test name
Test status
Simulation time 2353962373 ps
CPU time 8.33 seconds
Started Apr 25 12:58:33 PM PDT 24
Finished Apr 25 12:58:44 PM PDT 24
Peak memory 222644 kb
Host smart-b1809ccd-8c8a-4db0-8605-0e79002fa3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780119034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3780119034
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2474317597
Short name T33
Test name
Test status
Simulation time 249906272 ps
CPU time 1.05 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 218092 kb
Host smart-5edd4a8d-87c8-439a-b76b-4f5c637330da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474317597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2474317597
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.931126542
Short name T5
Test name
Test status
Simulation time 200748621 ps
CPU time 0.98 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 200708 kb
Host smart-178e45e6-1df0-4b0b-9e25-dffe7fdfc77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931126542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.931126542
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.278160586
Short name T348
Test name
Test status
Simulation time 1197448133 ps
CPU time 4.54 seconds
Started Apr 25 12:58:19 PM PDT 24
Finished Apr 25 12:58:26 PM PDT 24
Peak memory 201076 kb
Host smart-800f4839-b115-4750-a5d8-94b6d0a90a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278160586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.278160586
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3401744476
Short name T527
Test name
Test status
Simulation time 101532505 ps
CPU time 1.02 seconds
Started Apr 25 12:58:19 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 200864 kb
Host smart-9cb5641d-869c-4a97-94da-253de8101ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401744476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3401744476
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.4130613541
Short name T208
Test name
Test status
Simulation time 264982543 ps
CPU time 1.47 seconds
Started Apr 25 12:58:20 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 201104 kb
Host smart-a5a9e25a-4c44-4138-82b2-63c6a431e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130613541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4130613541
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2571559759
Short name T357
Test name
Test status
Simulation time 5924415897 ps
CPU time 20.12 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:55 PM PDT 24
Peak memory 201204 kb
Host smart-4c8573df-e72e-48d7-9e71-e82eb1d32cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571559759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2571559759
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.4253150222
Short name T455
Test name
Test status
Simulation time 507710209 ps
CPU time 2.53 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:16 PM PDT 24
Peak memory 200876 kb
Host smart-ead07e32-bc40-46d5-b0fe-1bd846b7c0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253150222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.4253150222
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2070938461
Short name T175
Test name
Test status
Simulation time 223995577 ps
CPU time 1.38 seconds
Started Apr 25 12:58:19 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 200980 kb
Host smart-9140a41f-979b-494b-9ca3-a69ef13b0784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070938461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2070938461
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.4273342054
Short name T194
Test name
Test status
Simulation time 77328890 ps
CPU time 0.8 seconds
Started Apr 25 12:58:23 PM PDT 24
Finished Apr 25 12:58:26 PM PDT 24
Peak memory 200708 kb
Host smart-c5d8e95e-3624-4707-89b1-9013d8b74f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273342054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.4273342054
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2781928408
Short name T43
Test name
Test status
Simulation time 1216327081 ps
CPU time 5.69 seconds
Started Apr 25 12:58:13 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 217800 kb
Host smart-d9a90f12-a73f-4cc9-8cd7-27dd45046320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781928408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2781928408
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.801961472
Short name T143
Test name
Test status
Simulation time 245700495 ps
CPU time 1.09 seconds
Started Apr 25 12:58:25 PM PDT 24
Finished Apr 25 12:58:27 PM PDT 24
Peak memory 218164 kb
Host smart-36af94ac-f5d1-4460-8d3c-8f330594ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801961472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.801961472
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2396457447
Short name T543
Test name
Test status
Simulation time 219160001 ps
CPU time 0.9 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:17 PM PDT 24
Peak memory 200700 kb
Host smart-44555ce5-eac1-44f8-9c14-4825c31774ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396457447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2396457447
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1869759264
Short name T489
Test name
Test status
Simulation time 1088840899 ps
CPU time 5.45 seconds
Started Apr 25 12:58:33 PM PDT 24
Finished Apr 25 12:58:41 PM PDT 24
Peak memory 201084 kb
Host smart-a16ef4fb-7d14-46ec-b01f-b5a1d56dbc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869759264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1869759264
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.136216999
Short name T318
Test name
Test status
Simulation time 153285017 ps
CPU time 1.09 seconds
Started Apr 25 12:58:26 PM PDT 24
Finished Apr 25 12:58:28 PM PDT 24
Peak memory 200864 kb
Host smart-8449c170-b4cc-4ed8-a952-83b5f700c573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136216999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.136216999
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4241415417
Short name T447
Test name
Test status
Simulation time 210403455 ps
CPU time 1.42 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:13 PM PDT 24
Peak memory 201072 kb
Host smart-5cfec299-c913-4f9b-a35c-b1200488de4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241415417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4241415417
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3092879215
Short name T332
Test name
Test status
Simulation time 16233832498 ps
CPU time 53.74 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:59:09 PM PDT 24
Peak memory 209392 kb
Host smart-a0c80d6a-ef95-43ff-9c47-e68ea73193bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092879215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3092879215
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1581033287
Short name T331
Test name
Test status
Simulation time 481705358 ps
CPU time 2.57 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 200912 kb
Host smart-71763929-8b04-4560-877a-5760ea54b832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581033287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1581033287
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2021277373
Short name T372
Test name
Test status
Simulation time 112574573 ps
CPU time 0.94 seconds
Started Apr 25 12:58:33 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 200900 kb
Host smart-faa9e36e-fe51-4435-9e15-c0f378198a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021277373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2021277373
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1503535076
Short name T181
Test name
Test status
Simulation time 90873080 ps
CPU time 0.82 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:35 PM PDT 24
Peak memory 200664 kb
Host smart-1ea41f1d-7fa7-420c-a734-6024476b4704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503535076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1503535076
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4182480295
Short name T514
Test name
Test status
Simulation time 2183171352 ps
CPU time 8.62 seconds
Started Apr 25 12:58:20 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 218688 kb
Host smart-5ea4bb10-84d9-4ed7-b920-9e366d984cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182480295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4182480295
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2391110228
Short name T240
Test name
Test status
Simulation time 247282667 ps
CPU time 1.04 seconds
Started Apr 25 12:58:27 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 218340 kb
Host smart-73591016-12b6-4dab-bed8-e0f0eb7feced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391110228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2391110228
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1174170691
Short name T17
Test name
Test status
Simulation time 157791940 ps
CPU time 0.85 seconds
Started Apr 25 12:58:21 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 200684 kb
Host smart-32d23e39-48f9-4103-b3d9-ba02e9f324b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174170691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1174170691
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2199098002
Short name T155
Test name
Test status
Simulation time 1647285952 ps
CPU time 6.38 seconds
Started Apr 25 12:58:28 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 201084 kb
Host smart-261de126-9a0e-40fb-91dd-bee648134b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199098002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2199098002
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2235283948
Short name T416
Test name
Test status
Simulation time 105277029 ps
CPU time 1.04 seconds
Started Apr 25 12:58:28 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 200868 kb
Host smart-60a6e504-a3da-4d97-9a19-c8c878c83553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235283948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2235283948
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2822401300
Short name T242
Test name
Test status
Simulation time 190859314 ps
CPU time 1.34 seconds
Started Apr 25 12:58:06 PM PDT 24
Finished Apr 25 12:58:09 PM PDT 24
Peak memory 201108 kb
Host smart-04aecd4a-e18f-43f6-ac80-613db137651e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822401300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2822401300
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.739555371
Short name T317
Test name
Test status
Simulation time 9472652068 ps
CPU time 32.45 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:47 PM PDT 24
Peak memory 201292 kb
Host smart-3a523cee-a058-4885-bca5-78053b9b48fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739555371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.739555371
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1854550935
Short name T79
Test name
Test status
Simulation time 150190372 ps
CPU time 1.71 seconds
Started Apr 25 12:58:20 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 200896 kb
Host smart-280074e0-51c8-4878-8aa8-1548e3be5b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854550935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1854550935
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.435197162
Short name T469
Test name
Test status
Simulation time 170780532 ps
CPU time 1.07 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 200876 kb
Host smart-e9b94e13-d6e9-4d4d-9b00-142142ceb29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435197162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.435197162
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2972007838
Short name T333
Test name
Test status
Simulation time 70700689 ps
CPU time 0.73 seconds
Started Apr 25 12:57:48 PM PDT 24
Finished Apr 25 12:57:51 PM PDT 24
Peak memory 200692 kb
Host smart-ddc2f59d-da0c-4504-83bd-058308147af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972007838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2972007838
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1625657202
Short name T465
Test name
Test status
Simulation time 244494290 ps
CPU time 1.03 seconds
Started Apr 25 12:57:31 PM PDT 24
Finished Apr 25 12:57:33 PM PDT 24
Peak memory 217996 kb
Host smart-8138f8c2-c101-4599-b003-50eb6f80dc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625657202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1625657202
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1257031249
Short name T493
Test name
Test status
Simulation time 169063901 ps
CPU time 0.88 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 200640 kb
Host smart-1bc65aa5-53b5-418e-b68f-95f9e6bca300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257031249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1257031249
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2641299576
Short name T395
Test name
Test status
Simulation time 801171774 ps
CPU time 4.59 seconds
Started Apr 25 12:57:31 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 201040 kb
Host smart-81dfd928-5e21-43d0-bb3d-a8f5c523216b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641299576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2641299576
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1310381843
Short name T65
Test name
Test status
Simulation time 16506334207 ps
CPU time 32.78 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:58:03 PM PDT 24
Peak memory 218748 kb
Host smart-6bd2eae7-72c7-4558-939f-a8f2962b40de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310381843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1310381843
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3220126726
Short name T159
Test name
Test status
Simulation time 142692754 ps
CPU time 1.04 seconds
Started Apr 25 12:57:27 PM PDT 24
Finished Apr 25 12:57:29 PM PDT 24
Peak memory 200884 kb
Host smart-3b851820-a580-451e-8515-fe3c8225ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220126726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3220126726
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.4054188161
Short name T410
Test name
Test status
Simulation time 111653129 ps
CPU time 1.29 seconds
Started Apr 25 12:57:25 PM PDT 24
Finished Apr 25 12:57:27 PM PDT 24
Peak memory 200996 kb
Host smart-0999ba67-52df-4eb1-9742-18f3a0e203c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054188161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.4054188161
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1768863736
Short name T531
Test name
Test status
Simulation time 11059695917 ps
CPU time 38.68 seconds
Started Apr 25 12:57:27 PM PDT 24
Finished Apr 25 12:58:07 PM PDT 24
Peak memory 209420 kb
Host smart-fe11cdcd-41d0-4b42-9f01-e995c2ba23fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768863736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1768863736
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1308704812
Short name T75
Test name
Test status
Simulation time 140151814 ps
CPU time 1.75 seconds
Started Apr 25 12:57:39 PM PDT 24
Finished Apr 25 12:57:43 PM PDT 24
Peak memory 200736 kb
Host smart-35190013-9738-442b-95fd-bf079ffb2e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308704812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1308704812
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3124194043
Short name T456
Test name
Test status
Simulation time 72820575 ps
CPU time 0.78 seconds
Started Apr 25 12:57:23 PM PDT 24
Finished Apr 25 12:57:24 PM PDT 24
Peak memory 200880 kb
Host smart-7f217341-5ea8-42ed-95f9-e1caba094faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124194043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3124194043
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.493912907
Short name T253
Test name
Test status
Simulation time 69952146 ps
CPU time 0.75 seconds
Started Apr 25 12:58:08 PM PDT 24
Finished Apr 25 12:58:10 PM PDT 24
Peak memory 200708 kb
Host smart-56324e1d-7e39-4a10-a164-e9c8e009741f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493912907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.493912907
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1655791578
Short name T40
Test name
Test status
Simulation time 1230871308 ps
CPU time 5.76 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 218492 kb
Host smart-342786cc-49f9-4b4b-892c-7765f1be0675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655791578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1655791578
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3869542643
Short name T359
Test name
Test status
Simulation time 243821427 ps
CPU time 1.1 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 218224 kb
Host smart-4e513137-ac1b-4fac-a454-d5fd87245f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869542643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3869542643
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.71888672
Short name T201
Test name
Test status
Simulation time 101689859 ps
CPU time 0.79 seconds
Started Apr 25 12:58:37 PM PDT 24
Finished Apr 25 12:58:40 PM PDT 24
Peak memory 200688 kb
Host smart-41a8be25-d0e1-403b-9c41-f79c982d9f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71888672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.71888672
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.946346475
Short name T304
Test name
Test status
Simulation time 902586100 ps
CPU time 4.41 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 200936 kb
Host smart-2886b167-cae7-40ca-b540-afd59d599efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946346475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.946346475
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3144784291
Short name T364
Test name
Test status
Simulation time 185987776 ps
CPU time 1.24 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 200868 kb
Host smart-6b156f3e-5dc8-45f9-9f25-5d34f4f06ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144784291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3144784291
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.64398685
Short name T538
Test name
Test status
Simulation time 121076952 ps
CPU time 1.19 seconds
Started Apr 25 12:58:20 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 201084 kb
Host smart-ec3aa278-6b67-417d-9d0c-7bf2a87819d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64398685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.64398685
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.69671884
Short name T81
Test name
Test status
Simulation time 6328113279 ps
CPU time 23.08 seconds
Started Apr 25 12:58:09 PM PDT 24
Finished Apr 25 12:58:34 PM PDT 24
Peak memory 210148 kb
Host smart-801082f9-be42-4bb5-a6a2-3055c88643b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69671884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.69671884
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.4184749345
Short name T160
Test name
Test status
Simulation time 402001629 ps
CPU time 2.24 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:16 PM PDT 24
Peak memory 200916 kb
Host smart-8e86d35c-0da0-46d5-994f-550b3dbf1eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184749345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4184749345
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.731381150
Short name T257
Test name
Test status
Simulation time 256291017 ps
CPU time 1.4 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:15 PM PDT 24
Peak memory 200888 kb
Host smart-fead271f-a597-434f-8bd0-00c650f41b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731381150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.731381150
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3759989173
Short name T472
Test name
Test status
Simulation time 77565875 ps
CPU time 0.82 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:58:38 PM PDT 24
Peak memory 200716 kb
Host smart-8f77641b-d5a7-49e5-8186-49b0da7cf606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759989173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3759989173
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.997365292
Short name T29
Test name
Test status
Simulation time 1897745038 ps
CPU time 6.81 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:58:50 PM PDT 24
Peak memory 218680 kb
Host smart-987e2211-ce52-4e99-9f22-6ebb3801df9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997365292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.997365292
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.937136988
Short name T52
Test name
Test status
Simulation time 244533548 ps
CPU time 1.1 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 218108 kb
Host smart-06a03e0a-cb6d-4c6a-a554-cc5088a65fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937136988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.937136988
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3788315206
Short name T260
Test name
Test status
Simulation time 147070517 ps
CPU time 0.81 seconds
Started Apr 25 12:58:28 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 200700 kb
Host smart-a484e2a8-64f7-47e8-8ac6-e4a882eb41a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788315206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3788315206
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.549105247
Short name T428
Test name
Test status
Simulation time 713410396 ps
CPU time 3.8 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:22 PM PDT 24
Peak memory 201056 kb
Host smart-16303713-b2ab-4d53-8d96-574403819adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549105247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.549105247
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3267943067
Short name T334
Test name
Test status
Simulation time 109239948 ps
CPU time 1 seconds
Started Apr 25 12:58:33 PM PDT 24
Finished Apr 25 12:58:37 PM PDT 24
Peak memory 200836 kb
Host smart-6fb9a9fa-fea5-4711-974a-5d29f8dc2949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267943067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3267943067
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3916524474
Short name T238
Test name
Test status
Simulation time 125274628 ps
CPU time 1.17 seconds
Started Apr 25 12:58:16 PM PDT 24
Finished Apr 25 12:58:20 PM PDT 24
Peak memory 201080 kb
Host smart-1a4f969d-3f00-475d-939a-839cdc1c659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916524474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3916524474
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4180665412
Short name T376
Test name
Test status
Simulation time 4768518093 ps
CPU time 16.95 seconds
Started Apr 25 12:58:23 PM PDT 24
Finished Apr 25 12:58:42 PM PDT 24
Peak memory 201200 kb
Host smart-44d118b2-1de2-4624-a26f-3e27136ea57d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180665412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4180665412
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2429135559
Short name T315
Test name
Test status
Simulation time 120193196 ps
CPU time 1.44 seconds
Started Apr 25 12:58:20 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 200812 kb
Host smart-1e40f796-e810-44fe-bced-b7036e35ff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429135559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2429135559
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.4043571999
Short name T511
Test name
Test status
Simulation time 166319952 ps
CPU time 1.21 seconds
Started Apr 25 12:58:28 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 200840 kb
Host smart-696c093c-f1a0-4bfb-bd60-16153df84d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043571999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.4043571999
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.4245170030
Short name T158
Test name
Test status
Simulation time 70825490 ps
CPU time 0.76 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:17 PM PDT 24
Peak memory 200744 kb
Host smart-d02436d4-66e8-4d1d-b328-1325b51e21d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245170030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.4245170030
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1520665955
Short name T22
Test name
Test status
Simulation time 2183591220 ps
CPU time 8.42 seconds
Started Apr 25 12:58:26 PM PDT 24
Finished Apr 25 12:58:42 PM PDT 24
Peak memory 218784 kb
Host smart-3f0b52ad-7dc8-43a8-a183-cca52733eeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520665955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1520665955
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.916655796
Short name T183
Test name
Test status
Simulation time 243523661 ps
CPU time 1.09 seconds
Started Apr 25 12:58:18 PM PDT 24
Finished Apr 25 12:58:22 PM PDT 24
Peak memory 218280 kb
Host smart-50ef18f3-e492-4d4f-a4b0-e9c93ec8f116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916655796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.916655796
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.990353117
Short name T329
Test name
Test status
Simulation time 190199572 ps
CPU time 0.91 seconds
Started Apr 25 12:58:33 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 200700 kb
Host smart-14a5ab8e-8908-4067-bdb5-65aa83fb04c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990353117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.990353117
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1572632573
Short name T518
Test name
Test status
Simulation time 815621253 ps
CPU time 4.1 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 201060 kb
Host smart-fe7eb014-e65b-4617-a63c-076129bec70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572632573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1572632573
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.560450583
Short name T145
Test name
Test status
Simulation time 145866075 ps
CPU time 1.08 seconds
Started Apr 25 12:58:30 PM PDT 24
Finished Apr 25 12:58:34 PM PDT 24
Peak memory 200868 kb
Host smart-27ff4c69-42a1-4f87-ad59-ac0113491e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560450583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.560450583
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.4021376418
Short name T286
Test name
Test status
Simulation time 190244590 ps
CPU time 1.41 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 200712 kb
Host smart-43473a5b-403a-4ae8-9bff-96111703096f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021376418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4021376418
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1859067895
Short name T277
Test name
Test status
Simulation time 4161563560 ps
CPU time 15.34 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 201196 kb
Host smart-18769629-5e5c-4729-9204-d8b72daaa093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859067895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1859067895
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1696895063
Short name T192
Test name
Test status
Simulation time 361443778 ps
CPU time 2.3 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:58:45 PM PDT 24
Peak memory 200908 kb
Host smart-36fe73f7-bade-4634-bb12-24fad354c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696895063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1696895063
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.576993612
Short name T11
Test name
Test status
Simulation time 205157115 ps
CPU time 1.28 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:19 PM PDT 24
Peak memory 200608 kb
Host smart-04341c06-47e4-4618-b5d8-db7b2891d14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576993612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.576993612
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.39479723
Short name T230
Test name
Test status
Simulation time 72445486 ps
CPU time 0.76 seconds
Started Apr 25 12:58:27 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 200660 kb
Host smart-1fd80cdd-1108-4525-9c4e-d0459e115e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39479723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.39479723
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.4137287751
Short name T352
Test name
Test status
Simulation time 2160262916 ps
CPU time 8.2 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:40 PM PDT 24
Peak memory 218212 kb
Host smart-4084ed30-9f75-4e40-ba37-c3224ee3357a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137287751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4137287751
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2130374006
Short name T50
Test name
Test status
Simulation time 244698743 ps
CPU time 1.16 seconds
Started Apr 25 12:58:18 PM PDT 24
Finished Apr 25 12:58:22 PM PDT 24
Peak memory 217952 kb
Host smart-3a2bf3c1-44c0-4ed2-a211-bf054dca9ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130374006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2130374006
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3292313786
Short name T14
Test name
Test status
Simulation time 111190826 ps
CPU time 0.8 seconds
Started Apr 25 12:58:45 PM PDT 24
Finished Apr 25 12:58:48 PM PDT 24
Peak memory 200652 kb
Host smart-8a9ca4ba-5b87-4386-993e-4403a3407117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292313786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3292313786
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3757225061
Short name T104
Test name
Test status
Simulation time 1021656964 ps
CPU time 5.05 seconds
Started Apr 25 12:58:23 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 201024 kb
Host smart-4b559a53-de15-4362-b491-6460ecd2a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757225061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3757225061
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2515999829
Short name T388
Test name
Test status
Simulation time 180610074 ps
CPU time 1.13 seconds
Started Apr 25 12:58:30 PM PDT 24
Finished Apr 25 12:58:34 PM PDT 24
Peak memory 200868 kb
Host smart-ead09210-f5a6-4351-a6f4-97af0e6d38db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515999829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2515999829
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1503961854
Short name T495
Test name
Test status
Simulation time 122487722 ps
CPU time 1.2 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 12:58:47 PM PDT 24
Peak memory 201080 kb
Host smart-2e63030c-66ef-45c4-b91b-e7404860f9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503961854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1503961854
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2128184578
Short name T101
Test name
Test status
Simulation time 8406351877 ps
CPU time 37.86 seconds
Started Apr 25 12:58:14 PM PDT 24
Finished Apr 25 12:58:55 PM PDT 24
Peak memory 209292 kb
Host smart-8f5902ba-179c-4c88-90bc-b50f2d835240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128184578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2128184578
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4176825471
Short name T440
Test name
Test status
Simulation time 447197056 ps
CPU time 2.58 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 200840 kb
Host smart-5f0da34e-084e-46ca-922e-c01528056e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176825471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4176825471
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3298579968
Short name T144
Test name
Test status
Simulation time 194077886 ps
CPU time 1.16 seconds
Started Apr 25 12:58:27 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 200892 kb
Host smart-d7d3db06-f248-4ca7-98fc-868d001946fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298579968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3298579968
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2823530974
Short name T280
Test name
Test status
Simulation time 78624496 ps
CPU time 0.8 seconds
Started Apr 25 12:58:18 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 200768 kb
Host smart-d5cfd8a9-06f2-4fe9-8abf-80517cc232e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823530974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2823530974
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2704430028
Short name T46
Test name
Test status
Simulation time 2337469998 ps
CPU time 8.15 seconds
Started Apr 25 12:58:13 PM PDT 24
Finished Apr 25 12:58:25 PM PDT 24
Peak memory 218756 kb
Host smart-3e7f15fc-6ad9-4945-b6ee-576132b9639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704430028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2704430028
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.972898233
Short name T458
Test name
Test status
Simulation time 244490818 ps
CPU time 1.18 seconds
Started Apr 25 12:58:21 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 218028 kb
Host smart-167fcc77-5ae5-4750-8c34-5fc45be7b75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972898233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.972898233
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2823048132
Short name T174
Test name
Test status
Simulation time 166706999 ps
CPU time 0.88 seconds
Started Apr 25 12:58:24 PM PDT 24
Finished Apr 25 12:58:27 PM PDT 24
Peak memory 200700 kb
Host smart-788544ee-2093-4963-945d-f223f6c6542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823048132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2823048132
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2782909353
Short name T471
Test name
Test status
Simulation time 1557841083 ps
CPU time 5.91 seconds
Started Apr 25 12:58:11 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 201012 kb
Host smart-c021bcc6-5b6d-4764-afdd-a0a7482ce01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782909353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2782909353
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.852145306
Short name T328
Test name
Test status
Simulation time 109112135 ps
CPU time 1.01 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 200912 kb
Host smart-3394da78-42d7-47d2-bfd2-10618ae44d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852145306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.852145306
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1438295112
Short name T21
Test name
Test status
Simulation time 201036701 ps
CPU time 1.37 seconds
Started Apr 25 12:58:35 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 201116 kb
Host smart-79e7fb8f-7cde-4317-bbc2-dd683e0cd627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438295112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1438295112
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2220967250
Short name T211
Test name
Test status
Simulation time 1357673408 ps
CPU time 6.12 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:38 PM PDT 24
Peak memory 209296 kb
Host smart-837a0343-a742-442b-a1df-f6a8557959b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220967250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2220967250
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3007222889
Short name T152
Test name
Test status
Simulation time 157403976 ps
CPU time 1.89 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:18 PM PDT 24
Peak memory 200804 kb
Host smart-55875ce8-4cfb-4c82-8a62-f3d845de9992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007222889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3007222889
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1646220104
Short name T433
Test name
Test status
Simulation time 203488821 ps
CPU time 1.21 seconds
Started Apr 25 12:58:31 PM PDT 24
Finished Apr 25 12:58:34 PM PDT 24
Peak memory 200884 kb
Host smart-9753928d-7ace-402c-bf4a-bde571daa79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646220104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1646220104
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.638434817
Short name T296
Test name
Test status
Simulation time 84659311 ps
CPU time 0.81 seconds
Started Apr 25 12:58:50 PM PDT 24
Finished Apr 25 12:58:53 PM PDT 24
Peak memory 200628 kb
Host smart-e75cde64-87f2-49b3-b7e5-79c99557104a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638434817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.638434817
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.4010285339
Short name T27
Test name
Test status
Simulation time 2158926935 ps
CPU time 8.24 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:40 PM PDT 24
Peak memory 222684 kb
Host smart-3b2d9dd6-1a6b-4f2c-ad18-6b13f94e8841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010285339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.4010285339
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2102192008
Short name T186
Test name
Test status
Simulation time 245407847 ps
CPU time 1.02 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 218076 kb
Host smart-a0ff9ae3-cf0b-470e-ad57-3709a412d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102192008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2102192008
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.664938507
Short name T298
Test name
Test status
Simulation time 158111780 ps
CPU time 0.83 seconds
Started Apr 25 12:58:37 PM PDT 24
Finished Apr 25 12:58:40 PM PDT 24
Peak memory 200688 kb
Host smart-019bf1ba-94da-4a19-9c4b-28f0f81055e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664938507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.664938507
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2011614611
Short name T128
Test name
Test status
Simulation time 1264668192 ps
CPU time 4.99 seconds
Started Apr 25 12:58:34 PM PDT 24
Finished Apr 25 12:58:41 PM PDT 24
Peak memory 200972 kb
Host smart-90f374b3-0b00-415a-9901-987ede7115ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011614611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2011614611
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2981851206
Short name T138
Test name
Test status
Simulation time 175317462 ps
CPU time 1.27 seconds
Started Apr 25 12:58:19 PM PDT 24
Finished Apr 25 12:58:23 PM PDT 24
Peak memory 200868 kb
Host smart-5f965c33-2fcf-4647-a67f-f0ee5f30a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981851206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2981851206
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.914528125
Short name T464
Test name
Test status
Simulation time 227606719 ps
CPU time 1.43 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 201060 kb
Host smart-ed473ad7-b3e8-41f8-8cb2-7acbfc843494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914528125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.914528125
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1526344515
Short name T99
Test name
Test status
Simulation time 13699395211 ps
CPU time 46.1 seconds
Started Apr 25 12:58:25 PM PDT 24
Finished Apr 25 12:59:13 PM PDT 24
Peak memory 201156 kb
Host smart-51e26306-938c-4cda-9390-013eb7830af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526344515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1526344515
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1717065643
Short name T349
Test name
Test status
Simulation time 434400825 ps
CPU time 2.23 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 209116 kb
Host smart-fa336795-8220-4027-9b69-4a9693b9c558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717065643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1717065643
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2083811071
Short name T488
Test name
Test status
Simulation time 77563848 ps
CPU time 0.85 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 200884 kb
Host smart-7991a661-3ea5-47ce-bf40-dce453125a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083811071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2083811071
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2142229082
Short name T161
Test name
Test status
Simulation time 83321891 ps
CPU time 0.79 seconds
Started Apr 25 12:58:26 PM PDT 24
Finished Apr 25 12:58:30 PM PDT 24
Peak memory 200680 kb
Host smart-f90fa43d-59e2-403c-884b-270b1260e8c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142229082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2142229082
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.22390410
Short name T314
Test name
Test status
Simulation time 1898005937 ps
CPU time 7.12 seconds
Started Apr 25 12:58:15 PM PDT 24
Finished Apr 25 12:58:26 PM PDT 24
Peak memory 222692 kb
Host smart-417fc827-a66b-40b1-8b0e-33c8171bbd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22390410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.22390410
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1196258208
Short name T140
Test name
Test status
Simulation time 243993987 ps
CPU time 1.1 seconds
Started Apr 25 12:58:28 PM PDT 24
Finished Apr 25 12:58:32 PM PDT 24
Peak memory 218316 kb
Host smart-a69e4c6e-940f-4e32-acf3-eed7263895dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196258208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1196258208
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1141203651
Short name T19
Test name
Test status
Simulation time 166864784 ps
CPU time 0.93 seconds
Started Apr 25 12:58:31 PM PDT 24
Finished Apr 25 12:58:35 PM PDT 24
Peak memory 200676 kb
Host smart-92877c4a-fa36-465b-b44e-fdc5c025a0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141203651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1141203651
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.499173623
Short name T239
Test name
Test status
Simulation time 1402079765 ps
CPU time 5.51 seconds
Started Apr 25 12:58:12 PM PDT 24
Finished Apr 25 12:58:21 PM PDT 24
Peak memory 201076 kb
Host smart-a09fc49b-10d8-4e85-9295-3918bac4440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499173623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.499173623
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.389077960
Short name T234
Test name
Test status
Simulation time 111776326 ps
CPU time 1.02 seconds
Started Apr 25 12:58:21 PM PDT 24
Finished Apr 25 12:58:24 PM PDT 24
Peak memory 200864 kb
Host smart-4bafcecf-11fd-413d-97de-857b4d1c5876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389077960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.389077960
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1162342744
Short name T293
Test name
Test status
Simulation time 196742511 ps
CPU time 1.3 seconds
Started Apr 25 12:58:24 PM PDT 24
Finished Apr 25 12:58:27 PM PDT 24
Peak memory 201088 kb
Host smart-e9e2c40e-babc-4bb8-a759-b21c8d64ec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162342744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1162342744
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1580464131
Short name T10
Test name
Test status
Simulation time 2607557864 ps
CPU time 12.24 seconds
Started Apr 25 12:58:31 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 201148 kb
Host smart-2231f87e-cab9-4864-b9db-e35016643d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580464131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1580464131
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.4095984134
Short name T377
Test name
Test status
Simulation time 144038161 ps
CPU time 1.76 seconds
Started Apr 25 12:58:28 PM PDT 24
Finished Apr 25 12:58:32 PM PDT 24
Peak memory 200808 kb
Host smart-57317e40-873c-4f40-80c0-84cf8eb04542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095984134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.4095984134
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2382660504
Short name T251
Test name
Test status
Simulation time 89193982 ps
CPU time 0.86 seconds
Started Apr 25 12:58:39 PM PDT 24
Finished Apr 25 12:58:41 PM PDT 24
Peak memory 200864 kb
Host smart-09810f72-2174-40e1-a934-518cfcb7f594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382660504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2382660504
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1113733754
Short name T457
Test name
Test status
Simulation time 63535168 ps
CPU time 0.75 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 12:58:44 PM PDT 24
Peak memory 200800 kb
Host smart-5eb8a68e-be6a-46c3-8ee7-194ad863ce05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113733754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1113733754
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2890439252
Short name T243
Test name
Test status
Simulation time 1869596150 ps
CPU time 7.24 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 12:58:52 PM PDT 24
Peak memory 222616 kb
Host smart-d9d488ff-e0e3-4fb2-a924-ede6d213b1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890439252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2890439252
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3598785546
Short name T151
Test name
Test status
Simulation time 244317316 ps
CPU time 1.05 seconds
Started Apr 25 12:58:51 PM PDT 24
Finished Apr 25 12:58:55 PM PDT 24
Peak memory 218108 kb
Host smart-81410b8f-1d7a-4b3a-97bc-c3f1a5f2c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598785546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3598785546
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3083576854
Short name T269
Test name
Test status
Simulation time 87821943 ps
CPU time 0.76 seconds
Started Apr 25 12:58:35 PM PDT 24
Finished Apr 25 12:58:38 PM PDT 24
Peak memory 200532 kb
Host smart-89a48d3f-09ff-456e-adfb-f541e5b13b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083576854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3083576854
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2960638843
Short name T461
Test name
Test status
Simulation time 1933917959 ps
CPU time 6.67 seconds
Started Apr 25 12:58:35 PM PDT 24
Finished Apr 25 12:58:44 PM PDT 24
Peak memory 201108 kb
Host smart-84ff0099-1002-476b-a65c-55ad6fb8243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960638843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2960638843
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.332542412
Short name T53
Test name
Test status
Simulation time 168491400 ps
CPU time 1.11 seconds
Started Apr 25 12:58:50 PM PDT 24
Finished Apr 25 12:58:53 PM PDT 24
Peak memory 200912 kb
Host smart-4655d5ad-dcc7-41b4-a651-b410d8f47c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332542412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.332542412
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2604287158
Short name T199
Test name
Test status
Simulation time 254827114 ps
CPU time 1.49 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:58:40 PM PDT 24
Peak memory 201088 kb
Host smart-e91223b5-82fa-4581-b484-7783d2944e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604287158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2604287158
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3458182197
Short name T127
Test name
Test status
Simulation time 9637681653 ps
CPU time 35.77 seconds
Started Apr 25 12:58:42 PM PDT 24
Finished Apr 25 12:59:20 PM PDT 24
Peak memory 201232 kb
Host smart-ab2b0a32-24dc-40e4-b706-89ed29ad17ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458182197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3458182197
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2359019679
Short name T481
Test name
Test status
Simulation time 394458245 ps
CPU time 2.21 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 12:58:47 PM PDT 24
Peak memory 200904 kb
Host smart-413f6109-42ae-47b1-90ff-d93342f5e616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359019679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2359019679
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4265378905
Short name T338
Test name
Test status
Simulation time 75748646 ps
CPU time 0.86 seconds
Started Apr 25 12:58:39 PM PDT 24
Finished Apr 25 12:58:42 PM PDT 24
Peak memory 200892 kb
Host smart-dcef094c-8032-4f08-ae43-770dd575e58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265378905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4265378905
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1732992190
Short name T529
Test name
Test status
Simulation time 63606976 ps
CPU time 0.78 seconds
Started Apr 25 12:58:50 PM PDT 24
Finished Apr 25 12:58:53 PM PDT 24
Peak memory 200708 kb
Host smart-088ff072-35f5-40ba-8d6b-edf8b7926745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732992190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1732992190
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.583581650
Short name T24
Test name
Test status
Simulation time 1224163385 ps
CPU time 5.36 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:58:48 PM PDT 24
Peak memory 218496 kb
Host smart-16763869-6c81-4db4-acb4-9b78c8eab4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583581650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.583581650
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3784877153
Short name T265
Test name
Test status
Simulation time 244118348 ps
CPU time 1.05 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 12:58:45 PM PDT 24
Peak memory 218200 kb
Host smart-65846ac5-0aa9-4e61-98c4-e4c7fb441250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784877153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3784877153
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2919199502
Short name T443
Test name
Test status
Simulation time 101413279 ps
CPU time 0.81 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:58:39 PM PDT 24
Peak memory 200676 kb
Host smart-78c390c8-2906-4de7-b705-3bcf54d472b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919199502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2919199502
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1870671624
Short name T475
Test name
Test status
Simulation time 1121288995 ps
CPU time 5.08 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:37 PM PDT 24
Peak memory 201040 kb
Host smart-aedb7530-9f5f-413f-be6f-334e49f7b619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870671624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1870671624
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.765357792
Short name T409
Test name
Test status
Simulation time 185031145 ps
CPU time 1.27 seconds
Started Apr 25 12:58:45 PM PDT 24
Finished Apr 25 12:58:49 PM PDT 24
Peak memory 200900 kb
Host smart-9937c47f-7ae6-4868-b7c0-a532711c669a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765357792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.765357792
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1095915570
Short name T536
Test name
Test status
Simulation time 198621613 ps
CPU time 1.36 seconds
Started Apr 25 12:58:29 PM PDT 24
Finished Apr 25 12:58:33 PM PDT 24
Peak memory 201128 kb
Host smart-57ba4bbf-5ca7-4038-bd33-8bfc76d93f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095915570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1095915570
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1452105559
Short name T532
Test name
Test status
Simulation time 8551884815 ps
CPU time 30.41 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:59:08 PM PDT 24
Peak memory 201180 kb
Host smart-72e319cf-184d-431a-b453-f701c38b3c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452105559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1452105559
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2275801406
Short name T467
Test name
Test status
Simulation time 376941579 ps
CPU time 2.37 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:04 PM PDT 24
Peak memory 200844 kb
Host smart-98299eae-1576-4f14-9827-5801ae8eb4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275801406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2275801406
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1337763971
Short name T272
Test name
Test status
Simulation time 77290134 ps
CPU time 0.8 seconds
Started Apr 25 12:58:33 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 200936 kb
Host smart-093e04e9-0d88-40a8-bedf-99b7217a9850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337763971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1337763971
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.99256346
Short name T437
Test name
Test status
Simulation time 75482519 ps
CPU time 0.8 seconds
Started Apr 25 12:58:25 PM PDT 24
Finished Apr 25 12:58:27 PM PDT 24
Peak memory 200708 kb
Host smart-096dd5c6-f0c3-4f27-9a5f-2d5dd58ab399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99256346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.99256346
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3762152100
Short name T387
Test name
Test status
Simulation time 1890381513 ps
CPU time 7.7 seconds
Started Apr 25 12:58:37 PM PDT 24
Finished Apr 25 12:58:47 PM PDT 24
Peak memory 222616 kb
Host smart-5307c7de-f73c-4e60-92c6-c8acdab06b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762152100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3762152100
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3665684664
Short name T402
Test name
Test status
Simulation time 246239619 ps
CPU time 1.02 seconds
Started Apr 25 12:58:37 PM PDT 24
Finished Apr 25 12:58:40 PM PDT 24
Peak memory 218008 kb
Host smart-156e32d7-8e54-45c2-a136-a2721470ea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665684664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3665684664
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1938884874
Short name T250
Test name
Test status
Simulation time 172987687 ps
CPU time 0.87 seconds
Started Apr 25 12:58:45 PM PDT 24
Finished Apr 25 12:58:48 PM PDT 24
Peak memory 200688 kb
Host smart-bb217788-b52e-4598-8127-00e30918d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938884874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1938884874
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.102572118
Short name T487
Test name
Test status
Simulation time 1195164639 ps
CPU time 5.24 seconds
Started Apr 25 12:58:34 PM PDT 24
Finished Apr 25 12:58:41 PM PDT 24
Peak memory 201052 kb
Host smart-5380c2e9-8fb0-45a0-a742-e41619232d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102572118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.102572118
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2629887709
Short name T187
Test name
Test status
Simulation time 156067697 ps
CPU time 1.15 seconds
Started Apr 25 12:58:35 PM PDT 24
Finished Apr 25 12:58:38 PM PDT 24
Peak memory 200728 kb
Host smart-0c8ffd46-395b-4cfa-b037-56b9c8a4792a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629887709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2629887709
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.500593370
Short name T177
Test name
Test status
Simulation time 252040283 ps
CPU time 1.63 seconds
Started Apr 25 12:58:51 PM PDT 24
Finished Apr 25 12:58:55 PM PDT 24
Peak memory 201088 kb
Host smart-bc33e631-566a-4a9e-b748-df212c509a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500593370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.500593370
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.568416433
Short name T94
Test name
Test status
Simulation time 1270256711 ps
CPU time 6.23 seconds
Started Apr 25 12:58:28 PM PDT 24
Finished Apr 25 12:58:37 PM PDT 24
Peak memory 201104 kb
Host smart-4df6d779-ce8d-49b7-887b-2daee7629bb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568416433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.568416433
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1006916473
Short name T220
Test name
Test status
Simulation time 505958445 ps
CPU time 2.53 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 200932 kb
Host smart-dd48622d-f23a-4316-886a-ece0f3fdd939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006916473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1006916473
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3258420296
Short name T451
Test name
Test status
Simulation time 151910044 ps
CPU time 1.17 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 200896 kb
Host smart-be89a2b9-cb39-4349-aae3-4b2b939715e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258420296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3258420296
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.331866220
Short name T66
Test name
Test status
Simulation time 96443727 ps
CPU time 0.86 seconds
Started Apr 25 12:57:50 PM PDT 24
Finished Apr 25 12:57:54 PM PDT 24
Peak memory 200740 kb
Host smart-9eb8c7c2-13f5-48d0-b95d-346ce94d50d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331866220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.331866220
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3688327685
Short name T340
Test name
Test status
Simulation time 2343888102 ps
CPU time 8 seconds
Started Apr 25 12:57:14 PM PDT 24
Finished Apr 25 12:57:24 PM PDT 24
Peak memory 218720 kb
Host smart-207ce981-0a3e-494e-9cc3-3c9aa4c2bdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688327685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3688327685
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3751852491
Short name T274
Test name
Test status
Simulation time 246250100 ps
CPU time 1.07 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 218288 kb
Host smart-d70af89f-9533-43aa-af23-50f43312fc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751852491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3751852491
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1843378714
Short name T18
Test name
Test status
Simulation time 147701983 ps
CPU time 0.84 seconds
Started Apr 25 12:57:26 PM PDT 24
Finished Apr 25 12:57:28 PM PDT 24
Peak memory 200696 kb
Host smart-1273b221-596c-42fd-b7a1-2c3073f3054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843378714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1843378714
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2486202466
Short name T129
Test name
Test status
Simulation time 1826846938 ps
CPU time 6.92 seconds
Started Apr 25 12:57:32 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 201132 kb
Host smart-71424323-3753-4ac6-8cdd-61fdfdf23c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486202466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2486202466
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2888023485
Short name T356
Test name
Test status
Simulation time 109901723 ps
CPU time 0.99 seconds
Started Apr 25 12:57:36 PM PDT 24
Finished Apr 25 12:57:39 PM PDT 24
Peak memory 200980 kb
Host smart-3d5491dc-fbe7-455a-a7b7-95cfc27e5e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888023485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2888023485
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2951796824
Short name T203
Test name
Test status
Simulation time 194695112 ps
CPU time 1.38 seconds
Started Apr 25 12:57:34 PM PDT 24
Finished Apr 25 12:57:43 PM PDT 24
Peak memory 201072 kb
Host smart-d565aa6e-53b7-464d-869f-dadfbc2e9fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951796824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2951796824
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3148618981
Short name T98
Test name
Test status
Simulation time 9815896660 ps
CPU time 33.7 seconds
Started Apr 25 12:57:39 PM PDT 24
Finished Apr 25 12:58:14 PM PDT 24
Peak memory 201144 kb
Host smart-ff20de24-2078-4a4c-952e-cc07187e2c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148618981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3148618981
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.933459565
Short name T38
Test name
Test status
Simulation time 405497892 ps
CPU time 2.13 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:32 PM PDT 24
Peak memory 200804 kb
Host smart-d3725f80-fe9a-40c1-8558-a6dc34bfa551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933459565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.933459565
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3917482762
Short name T78
Test name
Test status
Simulation time 118115002 ps
CPU time 1.03 seconds
Started Apr 25 12:57:16 PM PDT 24
Finished Apr 25 12:57:19 PM PDT 24
Peak memory 200756 kb
Host smart-7786dda9-6de1-4c25-a23f-626e43b5e30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917482762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3917482762
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2085800579
Short name T156
Test name
Test status
Simulation time 53901607 ps
CPU time 0.79 seconds
Started Apr 25 12:57:47 PM PDT 24
Finished Apr 25 12:57:50 PM PDT 24
Peak memory 200648 kb
Host smart-b7633d92-0706-4d62-9b01-3ce72adc163c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085800579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2085800579
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1924773785
Short name T480
Test name
Test status
Simulation time 1902171275 ps
CPU time 7.12 seconds
Started Apr 25 12:57:19 PM PDT 24
Finished Apr 25 12:57:28 PM PDT 24
Peak memory 217964 kb
Host smart-2a06eb78-b418-41b1-b619-ef5c558109eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924773785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1924773785
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4100499778
Short name T71
Test name
Test status
Simulation time 245746346 ps
CPU time 1.11 seconds
Started Apr 25 12:57:44 PM PDT 24
Finished Apr 25 12:57:46 PM PDT 24
Peak memory 218028 kb
Host smart-acc1371f-48ce-48b1-ba3e-b219a0e0ef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100499778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.4100499778
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3062185977
Short name T231
Test name
Test status
Simulation time 182660522 ps
CPU time 0.86 seconds
Started Apr 25 12:57:19 PM PDT 24
Finished Apr 25 12:57:21 PM PDT 24
Peak memory 200696 kb
Host smart-4ba752ba-2675-45cb-8580-5f8557b21fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062185977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3062185977
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.4116144083
Short name T96
Test name
Test status
Simulation time 839906063 ps
CPU time 4.24 seconds
Started Apr 25 12:57:42 PM PDT 24
Finished Apr 25 12:57:48 PM PDT 24
Peak memory 201032 kb
Host smart-d52598fe-5a1b-4668-86d8-41355ef12cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116144083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4116144083
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2019810117
Short name T343
Test name
Test status
Simulation time 96362421 ps
CPU time 0.98 seconds
Started Apr 25 12:57:11 PM PDT 24
Finished Apr 25 12:57:16 PM PDT 24
Peak memory 200800 kb
Host smart-80376f97-a2c7-4e25-b80b-171a1b044565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019810117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2019810117
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4259648701
Short name T308
Test name
Test status
Simulation time 118939130 ps
CPU time 1.17 seconds
Started Apr 25 12:57:34 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 201012 kb
Host smart-78e2e6dd-1a95-4b3b-8eff-9940f8b8038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259648701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4259648701
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1495734240
Short name T284
Test name
Test status
Simulation time 2327760344 ps
CPU time 8.45 seconds
Started Apr 25 12:57:21 PM PDT 24
Finished Apr 25 12:57:31 PM PDT 24
Peak memory 210524 kb
Host smart-7b64ad4c-3c12-418c-af89-76d27ec85a66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495734240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1495734240
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.60542532
Short name T463
Test name
Test status
Simulation time 273076077 ps
CPU time 1.94 seconds
Started Apr 25 12:57:31 PM PDT 24
Finished Apr 25 12:57:34 PM PDT 24
Peak memory 200744 kb
Host smart-251b7bce-edc8-4ae2-92b9-61a636f13c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60542532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.60542532
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.704813966
Short name T270
Test name
Test status
Simulation time 275203494 ps
CPU time 1.55 seconds
Started Apr 25 12:57:32 PM PDT 24
Finished Apr 25 12:57:35 PM PDT 24
Peak memory 201100 kb
Host smart-2a13a141-dc60-4b1c-879c-f322b610157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704813966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.704813966
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2116683974
Short name T406
Test name
Test status
Simulation time 67438354 ps
CPU time 0.77 seconds
Started Apr 25 12:57:34 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 200716 kb
Host smart-48cd8351-d296-4b36-8807-9bbb0d5701a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116683974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2116683974
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.4055503612
Short name T494
Test name
Test status
Simulation time 1220127238 ps
CPU time 5.72 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:45 PM PDT 24
Peak memory 218080 kb
Host smart-93b09c28-d942-4069-afdc-af49889cfee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055503612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.4055503612
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1837319206
Short name T378
Test name
Test status
Simulation time 244151390 ps
CPU time 1.1 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:57:52 PM PDT 24
Peak memory 218236 kb
Host smart-56a087cd-35bd-43c6-b77a-272d80f47538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837319206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1837319206
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.107055002
Short name T393
Test name
Test status
Simulation time 95241063 ps
CPU time 0.86 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:57:52 PM PDT 24
Peak memory 200708 kb
Host smart-a29bc563-7ed6-46a3-9659-b841851e6169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107055002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.107055002
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.355207014
Short name T263
Test name
Test status
Simulation time 1526841423 ps
CPU time 5.54 seconds
Started Apr 25 12:57:36 PM PDT 24
Finished Apr 25 12:57:44 PM PDT 24
Peak memory 201076 kb
Host smart-f0209120-f3bd-4049-8ca0-82368a60e042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355207014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.355207014
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1697978119
Short name T316
Test name
Test status
Simulation time 171579972 ps
CPU time 1.23 seconds
Started Apr 25 12:57:46 PM PDT 24
Finished Apr 25 12:57:48 PM PDT 24
Peak memory 200904 kb
Host smart-010d03cd-5c6b-450c-bb52-7020be049be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697978119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1697978119
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3340338118
Short name T474
Test name
Test status
Simulation time 250708085 ps
CPU time 1.59 seconds
Started Apr 25 12:57:49 PM PDT 24
Finished Apr 25 12:57:53 PM PDT 24
Peak memory 201068 kb
Host smart-1b3d752e-4688-4317-bd9e-6a07c8358630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340338118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3340338118
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.91696659
Short name T422
Test name
Test status
Simulation time 9671236315 ps
CPU time 34.47 seconds
Started Apr 25 12:58:06 PM PDT 24
Finished Apr 25 12:58:42 PM PDT 24
Peak memory 209416 kb
Host smart-bd8b684f-3fb1-49d5-814d-673565d6da5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91696659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.91696659
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1601105937
Short name T344
Test name
Test status
Simulation time 255945750 ps
CPU time 1.79 seconds
Started Apr 25 12:57:47 PM PDT 24
Finished Apr 25 12:57:50 PM PDT 24
Peak memory 200848 kb
Host smart-3c693ad1-a03d-456d-9bbc-68bd91dfe797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601105937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1601105937
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.635984111
Short name T297
Test name
Test status
Simulation time 138873419 ps
CPU time 1.16 seconds
Started Apr 25 12:57:32 PM PDT 24
Finished Apr 25 12:57:34 PM PDT 24
Peak memory 200824 kb
Host smart-19959298-d0e2-4f08-92c6-6fc4645374c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635984111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.635984111
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1659038323
Short name T460
Test name
Test status
Simulation time 68530122 ps
CPU time 0.76 seconds
Started Apr 25 12:57:43 PM PDT 24
Finished Apr 25 12:57:46 PM PDT 24
Peak memory 200680 kb
Host smart-7ef70264-69a3-4f64-9c5f-9c103c3731d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659038323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1659038323
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1676814287
Short name T28
Test name
Test status
Simulation time 1226787068 ps
CPU time 5.91 seconds
Started Apr 25 12:57:45 PM PDT 24
Finished Apr 25 12:57:52 PM PDT 24
Peak memory 217524 kb
Host smart-ab8ab155-db25-4f66-ab07-bb5b776ce974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676814287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1676814287
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3889048339
Short name T150
Test name
Test status
Simulation time 244945926 ps
CPU time 1.06 seconds
Started Apr 25 12:57:38 PM PDT 24
Finished Apr 25 12:57:41 PM PDT 24
Peak memory 218136 kb
Host smart-81c7b8f9-e3ef-4fa5-87d2-5bb728759330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889048339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3889048339
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.669064055
Short name T15
Test name
Test status
Simulation time 156955085 ps
CPU time 0.81 seconds
Started Apr 25 12:57:43 PM PDT 24
Finished Apr 25 12:57:46 PM PDT 24
Peak memory 200672 kb
Host smart-24bc3748-47bb-4eda-bec7-2e3f07dbd132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669064055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.669064055
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3087448457
Short name T97
Test name
Test status
Simulation time 753414573 ps
CPU time 4.04 seconds
Started Apr 25 12:57:42 PM PDT 24
Finished Apr 25 12:57:53 PM PDT 24
Peak memory 201104 kb
Host smart-bfe230a2-b943-4023-a5e0-015d51162c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087448457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3087448457
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2510630970
Short name T182
Test name
Test status
Simulation time 174454980 ps
CPU time 1.15 seconds
Started Apr 25 12:57:36 PM PDT 24
Finished Apr 25 12:57:38 PM PDT 24
Peak memory 200848 kb
Host smart-b4381c7c-3b2b-49f5-af22-19e0aeed8941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510630970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2510630970
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.525797189
Short name T400
Test name
Test status
Simulation time 235620671 ps
CPU time 1.44 seconds
Started Apr 25 12:57:24 PM PDT 24
Finished Apr 25 12:57:26 PM PDT 24
Peak memory 201032 kb
Host smart-de290535-2b39-49cc-b3e8-48583cd5386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525797189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.525797189
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2991327586
Short name T225
Test name
Test status
Simulation time 5935113431 ps
CPU time 21.05 seconds
Started Apr 25 12:57:29 PM PDT 24
Finished Apr 25 12:57:51 PM PDT 24
Peak memory 209400 kb
Host smart-8a4c2c57-3e4f-4484-82cc-02a0c3e5696b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991327586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2991327586
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.512301729
Short name T299
Test name
Test status
Simulation time 152691643 ps
CPU time 1.84 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:41 PM PDT 24
Peak memory 200880 kb
Host smart-da5ea0df-17be-432e-94c5-b0fd5524b39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512301729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.512301729
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.847834770
Short name T415
Test name
Test status
Simulation time 84658321 ps
CPU time 0.83 seconds
Started Apr 25 12:57:55 PM PDT 24
Finished Apr 25 12:57:59 PM PDT 24
Peak memory 200708 kb
Host smart-1dfe51fb-30bc-4953-94c6-08209699e6e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847834770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.847834770
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.893822491
Short name T345
Test name
Test status
Simulation time 2336339683 ps
CPU time 7.88 seconds
Started Apr 25 12:57:34 PM PDT 24
Finished Apr 25 12:57:43 PM PDT 24
Peak memory 218672 kb
Host smart-487012ad-ae0d-445c-be3e-c734392506cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893822491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.893822491
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3849692766
Short name T221
Test name
Test status
Simulation time 243866500 ps
CPU time 1.07 seconds
Started Apr 25 12:57:47 PM PDT 24
Finished Apr 25 12:57:50 PM PDT 24
Peak memory 218180 kb
Host smart-e709d38b-8041-45ba-9811-c68f7cb4d536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849692766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3849692766
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1429216495
Short name T484
Test name
Test status
Simulation time 161289143 ps
CPU time 0.91 seconds
Started Apr 25 12:57:38 PM PDT 24
Finished Apr 25 12:57:45 PM PDT 24
Peak memory 200700 kb
Host smart-530781ab-224a-40e6-b992-1b3154e63b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429216495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1429216495
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3892022648
Short name T283
Test name
Test status
Simulation time 943870803 ps
CPU time 4.63 seconds
Started Apr 25 12:57:32 PM PDT 24
Finished Apr 25 12:57:38 PM PDT 24
Peak memory 201040 kb
Host smart-80151c77-09e0-419f-bc28-f21a46790d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892022648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3892022648
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1587900471
Short name T149
Test name
Test status
Simulation time 92980788 ps
CPU time 0.97 seconds
Started Apr 25 12:57:35 PM PDT 24
Finished Apr 25 12:57:38 PM PDT 24
Peak memory 200808 kb
Host smart-b482fad2-3ce6-4976-9238-b9ba050dfb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587900471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1587900471
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3016538274
Short name T132
Test name
Test status
Simulation time 254535046 ps
CPU time 1.68 seconds
Started Apr 25 12:57:37 PM PDT 24
Finished Apr 25 12:57:40 PM PDT 24
Peak memory 200992 kb
Host smart-6adf1d6f-8053-4a33-ac66-3ba58caeda31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016538274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3016538274
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.48292480
Short name T268
Test name
Test status
Simulation time 1214004302 ps
CPU time 5.87 seconds
Started Apr 25 12:57:42 PM PDT 24
Finished Apr 25 12:57:50 PM PDT 24
Peak memory 210420 kb
Host smart-743551b3-43c5-4230-bf4a-149c1611e0fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48292480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.48292480
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1081057061
Short name T157
Test name
Test status
Simulation time 265620582 ps
CPU time 1.83 seconds
Started Apr 25 12:57:46 PM PDT 24
Finished Apr 25 12:57:49 PM PDT 24
Peak memory 200880 kb
Host smart-88c5cac9-9376-4e4f-aaea-1c46fa4b3ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081057061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1081057061
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2662295503
Short name T8
Test name
Test status
Simulation time 69071041 ps
CPU time 0.78 seconds
Started Apr 25 12:57:35 PM PDT 24
Finished Apr 25 12:57:37 PM PDT 24
Peak memory 200892 kb
Host smart-3e8c3673-b572-45c7-9e89-74b7f134c551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662295503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2662295503
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%