Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9161

1

T4

229

T5

15

T6

12

auto[1]

11848

1

T2

4

T4

214

T5

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6584	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6966	1			T1	1		T2	2		T3	1
reset_info_cp[2]	3249	1			T2	1		T4	70		T8	1
reset_info_cp[4]	4263	1			T2	1		T4	107		T8	1
reset_info_cp[8]	101	1			T44	1		T45	1		T76	1
reset_info_cp[16]	109	1			T4	4		T6	1		T11	1
reset_info_cp[32]	127	1			T5	1		T36	1		T43	2
reset_info_cp[64]	122	1			T4	2		T5	2		T13	1
reset_info_cp[128]	108	1			T4	4		T5	2		T6	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3416	1			T4	56		T11	8		T13	16
reset_info_cp[1]	auto[1]	2930	1			T2	1		T4	70		T8	1
reset_info_cp[2]	auto[0]	1044	1			T4	27		T11	7		T43	20
reset_info_cp[2]	auto[1]	2205	1			T2	1		T4	43		T8	1
reset_info_cp[4]	auto[0]	1576	1			T4	63		T11	7		T43	36
reset_info_cp[4]	auto[1]	2687	1			T2	1		T4	44		T8	1
reset_info_cp[8]	auto[0]	51	1			T44	1		T76	1		T121	1
reset_info_cp[8]	auto[1]	50	1			T45	1		T79	1		T39	2
reset_info_cp[16]	auto[0]	49	1			T4	1		T6	1		T43	1
reset_info_cp[16]	auto[1]	60	1			T4	3		T11	1		T79	1
reset_info_cp[32]	auto[0]	59	1			T5	1		T43	2		T121	1
reset_info_cp[32]	auto[1]	68	1			T36	1		T90	1		T79	1
reset_info_cp[64]	auto[0]	55	1			T4	1		T5	2		T76	1
reset_info_cp[64]	auto[1]	67	1			T4	1		T13	1		T23	1
reset_info_cp[128]	auto[0]	48	1			T4	2		T5	2		T6	1
reset_info_cp[128]	auto[1]	60	1			T4	2		T23	1		T79	2