Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1457669451 Apr 28 02:08:48 PM PDT 24 Apr 28 02:08:50 PM PDT 24 99076562 ps
T539 /workspace/coverage/default/4.rstmgr_alert_test.2176777093 Apr 28 02:08:51 PM PDT 24 Apr 28 02:08:52 PM PDT 24 63070335 ps
T540 /workspace/coverage/default/33.rstmgr_por_stretcher.2759703941 Apr 28 02:10:11 PM PDT 24 Apr 28 02:10:12 PM PDT 24 95199612 ps
T541 /workspace/coverage/default/20.rstmgr_smoke.2302770252 Apr 28 02:09:36 PM PDT 24 Apr 28 02:09:38 PM PDT 24 221290239 ps
T542 /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2296514923 Apr 28 02:09:52 PM PDT 24 Apr 28 02:09:53 PM PDT 24 132027014 ps
T55 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1255601361 Apr 28 03:18:53 PM PDT 24 Apr 28 03:18:56 PM PDT 24 433202531 ps
T56 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3146953713 Apr 28 03:19:13 PM PDT 24 Apr 28 03:19:16 PM PDT 24 194832832 ps
T57 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3998589923 Apr 28 03:19:13 PM PDT 24 Apr 28 03:19:15 PM PDT 24 193498586 ps
T58 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.935873315 Apr 28 03:18:59 PM PDT 24 Apr 28 03:19:01 PM PDT 24 141740378 ps
T96 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.234319239 Apr 28 03:19:07 PM PDT 24 Apr 28 03:19:10 PM PDT 24 113188996 ps
T97 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1088680638 Apr 28 03:19:14 PM PDT 24 Apr 28 03:19:16 PM PDT 24 139023271 ps
T61 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3268885379 Apr 28 03:19:02 PM PDT 24 Apr 28 03:19:04 PM PDT 24 118535065 ps
T129 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2631407667 Apr 28 03:18:56 PM PDT 24 Apr 28 03:19:05 PM PDT 24 1562999008 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2965537465 Apr 28 03:18:51 PM PDT 24 Apr 28 03:18:53 PM PDT 24 100623275 ps
T59 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4198585186 Apr 28 03:19:13 PM PDT 24 Apr 28 03:19:16 PM PDT 24 484861211 ps
T98 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2983171395 Apr 28 03:18:59 PM PDT 24 Apr 28 03:19:00 PM PDT 24 85994349 ps
T99 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2259966445 Apr 28 03:19:03 PM PDT 24 Apr 28 03:19:04 PM PDT 24 59981628 ps
T60 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2853086237 Apr 28 03:18:48 PM PDT 24 Apr 28 03:18:51 PM PDT 24 909114364 ps
T83 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3924069712 Apr 28 03:19:07 PM PDT 24 Apr 28 03:19:11 PM PDT 24 771206622 ps
T84 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1251729488 Apr 28 03:18:57 PM PDT 24 Apr 28 03:19:01 PM PDT 24 178821610 ps
T85 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4165715360 Apr 28 03:19:07 PM PDT 24 Apr 28 03:19:13 PM PDT 24 639831819 ps
T100 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3664430216 Apr 28 03:19:00 PM PDT 24 Apr 28 03:19:02 PM PDT 24 244991215 ps
T86 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1049020029 Apr 28 03:19:07 PM PDT 24 Apr 28 03:19:11 PM PDT 24 465083850 ps
T101 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2968282147 Apr 28 03:19:10 PM PDT 24 Apr 28 03:19:12 PM PDT 24 64485041 ps
T107 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3905474525 Apr 28 03:19:03 PM PDT 24 Apr 28 03:19:06 PM PDT 24 455608401 ps
T87 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.182194587 Apr 28 03:18:54 PM PDT 24 Apr 28 03:18:57 PM PDT 24 979661617 ps
T544 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2209918444 Apr 28 03:19:11 PM PDT 24 Apr 28 03:19:13 PM PDT 24 86745891 ps
T102 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2137897072 Apr 28 03:19:13 PM PDT 24 Apr 28 03:19:15 PM PDT 24 78371731 ps
T88 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3063089481 Apr 28 03:19:08 PM PDT 24 Apr 28 03:19:11 PM PDT 24 181075969 ps
T545 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1605480469 Apr 28 03:18:52 PM PDT 24 Apr 28 03:18:56 PM PDT 24 271946632 ps
T89 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.825198483 Apr 28 03:19:04 PM PDT 24 Apr 28 03:19:07 PM PDT 24 189866759 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2931530614 Apr 28 03:18:57 PM PDT 24 Apr 28 03:19:00 PM PDT 24 148531589 ps
T103 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4199449551 Apr 28 03:19:10 PM PDT 24 Apr 28 03:19:12 PM PDT 24 65664137 ps
T547 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.990635187 Apr 28 03:19:06 PM PDT 24 Apr 28 03:19:08 PM PDT 24 137823270 ps
T548 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1194969489 Apr 28 03:19:06 PM PDT 24 Apr 28 03:19:07 PM PDT 24 110870447 ps
T549 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1012980038 Apr 28 03:18:57 PM PDT 24 Apr 28 03:18:59 PM PDT 24 68114493 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2165322963 Apr 28 03:18:58 PM PDT 24 Apr 28 03:19:00 PM PDT 24 152983335 ps
T106 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2486957050 Apr 28 03:19:14 PM PDT 24 Apr 28 03:19:17 PM PDT 24 499377917 ps
T551 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1777122635 Apr 28 03:18:51 PM PDT 24 Apr 28 03:18:53 PM PDT 24 87115882 ps
T104 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3606032480 Apr 28 03:19:00 PM PDT 24 Apr 28 03:19:02 PM PDT 24 127333350 ps
T105 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.279884856 Apr 28 03:19:06 PM PDT 24 Apr 28 03:19:08 PM PDT 24 64577789 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2577073854 Apr 28 03:18:51 PM PDT 24 Apr 28 03:18:53 PM PDT 24 116196401 ps
T553 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1663275146 Apr 28 03:19:15 PM PDT 24 Apr 28 03:19:17 PM PDT 24 149649973 ps
T113 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3416160679 Apr 28 03:19:15 PM PDT 24 Apr 28 03:19:19 PM PDT 24 175664929 ps
T114 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1704191068 Apr 28 03:19:08 PM PDT 24 Apr 28 03:19:12 PM PDT 24 172540818 ps
T554 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.327389178 Apr 28 03:19:02 PM PDT 24 Apr 28 03:19:04 PM PDT 24 60814543 ps
T555 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2533540729 Apr 28 03:19:09 PM PDT 24 Apr 28 03:19:11 PM PDT 24 215741190 ps
T115 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3594119554 Apr 28 03:19:05 PM PDT 24 Apr 28 03:19:08 PM PDT 24 454706191 ps
T556 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1935626282 Apr 28 03:19:16 PM PDT 24 Apr 28 03:19:19 PM PDT 24 426294160 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1743832478 Apr 28 03:18:59 PM PDT 24 Apr 28 03:19:01 PM PDT 24 83439302 ps
T558 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3267526507 Apr 28 03:18:58 PM PDT 24 Apr 28 03:18:59 PM PDT 24 124493398 ps
T559 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1996024371 Apr 28 03:19:09 PM PDT 24 Apr 28 03:19:12 PM PDT 24 441317741 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2613665433 Apr 28 03:18:51 PM PDT 24 Apr 28 03:18:58 PM PDT 24 1188167852 ps
T561 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4080704058 Apr 28 03:19:01 PM PDT 24 Apr 28 03:19:03 PM PDT 24 175981011 ps
T562 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2672302934 Apr 28 03:19:08 PM PDT 24 Apr 28 03:19:10 PM PDT 24 66188515 ps
T563 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.107772170 Apr 28 03:18:57 PM PDT 24 Apr 28 03:19:01 PM PDT 24 318542645 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1601808277 Apr 28 03:18:53 PM PDT 24 Apr 28 03:18:57 PM PDT 24 237570050 ps
T565 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1630292008 Apr 28 03:18:56 PM PDT 24 Apr 28 03:18:57 PM PDT 24 53817136 ps
T112 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3250567363 Apr 28 03:19:04 PM PDT 24 Apr 28 03:19:08 PM PDT 24 775205555 ps
T566 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1284175431 Apr 28 03:19:02 PM PDT 24 Apr 28 03:19:05 PM PDT 24 134319030 ps
T567 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.716017448 Apr 28 03:19:07 PM PDT 24 Apr 28 03:19:10 PM PDT 24 138826188 ps
T568 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2561953716 Apr 28 03:19:02 PM PDT 24 Apr 28 03:19:04 PM PDT 24 164283991 ps
T569 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.421783915 Apr 28 03:18:52 PM PDT 24 Apr 28 03:18:55 PM PDT 24 249121295 ps
T570 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3967284146 Apr 28 03:19:01 PM PDT 24 Apr 28 03:19:03 PM PDT 24 218789105 ps
T571 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4006741617 Apr 28 03:19:08 PM PDT 24 Apr 28 03:19:10 PM PDT 24 157912176 ps
T572 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.7899764 Apr 28 03:19:11 PM PDT 24 Apr 28 03:19:13 PM PDT 24 86703314 ps
T573 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3038246323 Apr 28 03:19:15 PM PDT 24 Apr 28 03:19:17 PM PDT 24 142647128 ps
T574 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1564893936 Apr 28 03:19:05 PM PDT 24 Apr 28 03:19:07 PM PDT 24 179832379 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3995502993 Apr 28 03:18:56 PM PDT 24 Apr 28 03:18:59 PM PDT 24 149535098 ps
T576 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.902433629 Apr 28 03:18:56 PM PDT 24 Apr 28 03:19:00 PM PDT 24 222984266 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3907934707 Apr 28 03:18:57 PM PDT 24 Apr 28 03:19:00 PM PDT 24 504989537 ps
T578 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2113014510 Apr 28 03:18:51 PM PDT 24 Apr 28 03:18:54 PM PDT 24 405774216 ps
T579 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2524113723 Apr 28 03:19:13 PM PDT 24 Apr 28 03:19:16 PM PDT 24 366745708 ps
T580 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.214943433 Apr 28 03:18:51 PM PDT 24 Apr 28 03:18:53 PM PDT 24 73952603 ps
T581 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3530523284 Apr 28 03:19:06 PM PDT 24 Apr 28 03:19:10 PM PDT 24 195450343 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3113360412 Apr 28 03:18:56 PM PDT 24 Apr 28 03:18:57 PM PDT 24 72953113 ps
T583 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1267972641 Apr 28 03:18:56 PM PDT 24 Apr 28 03:18:58 PM PDT 24 102665646 ps
T584 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3573939359 Apr 28 03:19:09 PM PDT 24 Apr 28 03:19:11 PM PDT 24 58249470 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3845098996 Apr 28 03:18:51 PM PDT 24 Apr 28 03:18:53 PM PDT 24 149694753 ps
T586 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1669308758 Apr 28 03:18:54 PM PDT 24 Apr 28 03:19:06 PM PDT 24 2303917704 ps
T587 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1262807317 Apr 28 03:19:07 PM PDT 24 Apr 28 03:19:09 PM PDT 24 107819774 ps
T588 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3293009692 Apr 28 03:19:10 PM PDT 24 Apr 28 03:19:14 PM PDT 24 411149827 ps
T589 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2079332289 Apr 28 03:19:01 PM PDT 24 Apr 28 03:19:03 PM PDT 24 95208130 ps
T590 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3027521417 Apr 28 03:19:13 PM PDT 24 Apr 28 03:19:18 PM PDT 24 535282320 ps
T591 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4252396995 Apr 28 03:19:07 PM PDT 24 Apr 28 03:19:11 PM PDT 24 463951287 ps
T592 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3123634861 Apr 28 03:19:03 PM PDT 24 Apr 28 03:19:07 PM PDT 24 441781725 ps
T593 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3406822811 Apr 28 03:19:12 PM PDT 24 Apr 28 03:19:15 PM PDT 24 143328954 ps
T594 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.710796217 Apr 28 03:19:07 PM PDT 24 Apr 28 03:19:10 PM PDT 24 122149379 ps
T595 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1642736361 Apr 28 03:18:51 PM PDT 24 Apr 28 03:18:54 PM PDT 24 185865500 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3368688171 Apr 28 03:18:52 PM PDT 24 Apr 28 03:18:55 PM PDT 24 369827939 ps
T108 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4270720972 Apr 28 03:19:03 PM PDT 24 Apr 28 03:19:05 PM PDT 24 433110901 ps
T597 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1819231514 Apr 28 03:19:08 PM PDT 24 Apr 28 03:19:11 PM PDT 24 115941663 ps
T598 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3180446463 Apr 28 03:19:07 PM PDT 24 Apr 28 03:19:09 PM PDT 24 128833039 ps
T110 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1939635245 Apr 28 03:19:08 PM PDT 24 Apr 28 03:19:12 PM PDT 24 806210729 ps
T599 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.629396292 Apr 28 03:19:02 PM PDT 24 Apr 28 03:19:04 PM PDT 24 76730624 ps
T600 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2377303988 Apr 28 03:18:51 PM PDT 24 Apr 28 03:18:54 PM PDT 24 188657468 ps
T601 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1730124023 Apr 28 03:18:52 PM PDT 24 Apr 28 03:18:54 PM PDT 24 92986446 ps
T602 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2406502155 Apr 28 03:19:15 PM PDT 24 Apr 28 03:19:17 PM PDT 24 76704774 ps
T109 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1372740173 Apr 28 03:19:04 PM PDT 24 Apr 28 03:19:06 PM PDT 24 495919425 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3412028302 Apr 28 03:19:01 PM PDT 24 Apr 28 03:19:05 PM PDT 24 490318492 ps
T604 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3115247874 Apr 28 03:19:02 PM PDT 24 Apr 28 03:19:04 PM PDT 24 172039341 ps
T605 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4249087336 Apr 28 03:19:14 PM PDT 24 Apr 28 03:19:16 PM PDT 24 86991145 ps
T127 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3119190768 Apr 28 03:19:12 PM PDT 24 Apr 28 03:19:16 PM PDT 24 889330246 ps
T128 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4084593286 Apr 28 03:18:57 PM PDT 24 Apr 28 03:19:00 PM PDT 24 463317170 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3255856907 Apr 28 03:18:53 PM PDT 24 Apr 28 03:18:55 PM PDT 24 72371828 ps
T607 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1337165645 Apr 28 03:19:02 PM PDT 24 Apr 28 03:19:03 PM PDT 24 59230444 ps
T608 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1090148999 Apr 28 03:19:12 PM PDT 24 Apr 28 03:19:14 PM PDT 24 175527820 ps
T609 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.150154901 Apr 28 03:18:54 PM PDT 24 Apr 28 03:18:57 PM PDT 24 271441485 ps
T610 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1327042531 Apr 28 03:19:06 PM PDT 24 Apr 28 03:19:10 PM PDT 24 524568288 ps
T611 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.4066581835 Apr 28 03:19:12 PM PDT 24 Apr 28 03:19:14 PM PDT 24 139116237 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3975009469 Apr 28 03:18:52 PM PDT 24 Apr 28 03:18:54 PM PDT 24 123744180 ps
T613 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3519532200 Apr 28 03:19:12 PM PDT 24 Apr 28 03:19:13 PM PDT 24 94781965 ps
T614 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2859182058 Apr 28 03:18:58 PM PDT 24 Apr 28 03:19:04 PM PDT 24 797823000 ps
T615 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1667300210 Apr 28 03:19:08 PM PDT 24 Apr 28 03:19:12 PM PDT 24 760996544 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1377869585 Apr 28 03:18:57 PM PDT 24 Apr 28 03:18:59 PM PDT 24 99486874 ps
T617 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4016063434 Apr 28 03:19:02 PM PDT 24 Apr 28 03:19:04 PM PDT 24 225693935 ps
T618 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.282297892 Apr 28 03:19:11 PM PDT 24 Apr 28 03:19:13 PM PDT 24 75914948 ps
T619 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.313779097 Apr 28 03:19:12 PM PDT 24 Apr 28 03:19:15 PM PDT 24 165582059 ps
T620 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2951407156 Apr 28 03:19:00 PM PDT 24 Apr 28 03:19:05 PM PDT 24 934963714 ps
T111 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3530707771 Apr 28 03:18:56 PM PDT 24 Apr 28 03:19:00 PM PDT 24 891254287 ps

Test location /workspace/coverage/default/15.rstmgr_stress_all.1165574832
Short name T4
Test name
Test status
Simulation time 6705578700 ps
CPU time 32.77 seconds
Started Apr 28 02:09:23 PM PDT 24
Finished Apr 28 02:09:57 PM PDT 24
Peak memory 210244 kb
Host smart-70657cef-1db4-44a4-9a75-471a2277ef50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165574832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1165574832
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.529732878
Short name T77
Test name
Test status
Simulation time 291274852 ps
CPU time 2.03 seconds
Started Apr 28 02:10:36 PM PDT 24
Finished Apr 28 02:10:38 PM PDT 24
Peak memory 200904 kb
Host smart-2194ee02-a3ba-4429-a737-64aebc4237b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529732878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.529732878
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.880461210
Short name T13
Test name
Test status
Simulation time 1880846917 ps
CPU time 7.42 seconds
Started Apr 28 02:09:01 PM PDT 24
Finished Apr 28 02:09:09 PM PDT 24
Peak memory 222616 kb
Host smart-b31cddbe-c189-4dbe-8163-3c426ef062c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880461210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.880461210
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.935873315
Short name T58
Test name
Test status
Simulation time 141740378 ps
CPU time 1.48 seconds
Started Apr 28 03:18:59 PM PDT 24
Finished Apr 28 03:19:01 PM PDT 24
Peak memory 209444 kb
Host smart-e1cbf850-7346-4df2-8355-ebce7beb79d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935873315 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.935873315
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1585817093
Short name T62
Test name
Test status
Simulation time 16752364604 ps
CPU time 24.26 seconds
Started Apr 28 02:08:42 PM PDT 24
Finished Apr 28 02:09:07 PM PDT 24
Peak memory 218316 kb
Host smart-b448cc4a-12fd-4085-b4a2-963f67fae210
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585817093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1585817093
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3686804397
Short name T79
Test name
Test status
Simulation time 9226110071 ps
CPU time 31.85 seconds
Started Apr 28 02:10:32 PM PDT 24
Finished Apr 28 02:11:04 PM PDT 24
Peak memory 201172 kb
Host smart-3524e6f7-9551-486d-9871-2956cb6fd8a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686804397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3686804397
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3924069712
Short name T83
Test name
Test status
Simulation time 771206622 ps
CPU time 2.83 seconds
Started Apr 28 03:19:07 PM PDT 24
Finished Apr 28 03:19:11 PM PDT 24
Peak memory 201088 kb
Host smart-14243816-b607-4f5e-997f-6f77d81c88f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924069712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3924069712
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3874489265
Short name T2
Test name
Test status
Simulation time 144743125 ps
CPU time 1.08 seconds
Started Apr 28 02:09:12 PM PDT 24
Finished Apr 28 02:09:14 PM PDT 24
Peak memory 200800 kb
Host smart-cb0ededd-5290-4059-8f67-b0d7ddb87a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874489265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3874489265
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3841776255
Short name T30
Test name
Test status
Simulation time 1879212241 ps
CPU time 7.2 seconds
Started Apr 28 02:09:44 PM PDT 24
Finished Apr 28 02:09:51 PM PDT 24
Peak memory 218052 kb
Host smart-f9c8fca8-b8bf-48c0-a8de-d8100242fc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841776255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3841776255
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3594119554
Short name T115
Test name
Test status
Simulation time 454706191 ps
CPU time 3.43 seconds
Started Apr 28 03:19:05 PM PDT 24
Finished Apr 28 03:19:08 PM PDT 24
Peak memory 213228 kb
Host smart-e0702812-be39-40de-bd7e-d47d583b9c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594119554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3594119554
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3110810321
Short name T160
Test name
Test status
Simulation time 76123208 ps
CPU time 0.8 seconds
Started Apr 28 02:08:45 PM PDT 24
Finished Apr 28 02:08:46 PM PDT 24
Peak memory 200688 kb
Host smart-ca06e01a-1bbe-4d16-b819-37ab049da404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110810321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3110810321
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3250567363
Short name T112
Test name
Test status
Simulation time 775205555 ps
CPU time 3.14 seconds
Started Apr 28 03:19:04 PM PDT 24
Finished Apr 28 03:19:08 PM PDT 24
Peak memory 201124 kb
Host smart-63a6986a-573d-42fc-8549-2feae77ad98b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250567363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3250567363
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3902614997
Short name T131
Test name
Test status
Simulation time 137691280 ps
CPU time 0.99 seconds
Started Apr 28 02:08:32 PM PDT 24
Finished Apr 28 02:08:33 PM PDT 24
Peak memory 200832 kb
Host smart-5cd58be3-86ac-420c-b8dd-9ecac6b570f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902614997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3902614997
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.234319239
Short name T96
Test name
Test status
Simulation time 113188996 ps
CPU time 1.34 seconds
Started Apr 28 03:19:07 PM PDT 24
Finished Apr 28 03:19:10 PM PDT 24
Peak memory 201120 kb
Host smart-06a6fb53-7061-47fb-86b0-e1187fdc99e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234319239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.234319239
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1165291777
Short name T15
Test name
Test status
Simulation time 197492070 ps
CPU time 0.87 seconds
Started Apr 28 02:08:34 PM PDT 24
Finished Apr 28 02:08:35 PM PDT 24
Peak memory 200716 kb
Host smart-5bfe75be-3934-4918-87ff-594a01479c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165291777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1165291777
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4270720972
Short name T108
Test name
Test status
Simulation time 433110901 ps
CPU time 1.79 seconds
Started Apr 28 03:19:03 PM PDT 24
Finished Apr 28 03:19:05 PM PDT 24
Peak memory 201176 kb
Host smart-60d49f7b-3c03-4361-996c-8f2f07df0730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270720972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.4270720972
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3580872871
Short name T51
Test name
Test status
Simulation time 1227882477 ps
CPU time 6.41 seconds
Started Apr 28 02:08:38 PM PDT 24
Finished Apr 28 02:08:45 PM PDT 24
Peak memory 217596 kb
Host smart-3f70566a-e1dd-438f-84c9-6a9b2f26d785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580872871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3580872871
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2248613410
Short name T7
Test name
Test status
Simulation time 153615654 ps
CPU time 1.87 seconds
Started Apr 28 02:08:47 PM PDT 24
Finished Apr 28 02:08:49 PM PDT 24
Peak memory 200876 kb
Host smart-d406b229-c5f4-4385-b1d3-7b0a5941bebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248613410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2248613410
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.150154901
Short name T609
Test name
Test status
Simulation time 271441485 ps
CPU time 1.71 seconds
Started Apr 28 03:18:54 PM PDT 24
Finished Apr 28 03:18:57 PM PDT 24
Peak memory 201036 kb
Host smart-fa7b4d64-017b-4542-ae08-5d367301bbf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150154901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.150154901
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1605480469
Short name T545
Test name
Test status
Simulation time 271946632 ps
CPU time 3.28 seconds
Started Apr 28 03:18:52 PM PDT 24
Finished Apr 28 03:18:56 PM PDT 24
Peak memory 201048 kb
Host smart-35523504-3bcd-4616-b3bc-c74a692a7d62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605480469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
605480469
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1730124023
Short name T601
Test name
Test status
Simulation time 92986446 ps
CPU time 0.83 seconds
Started Apr 28 03:18:52 PM PDT 24
Finished Apr 28 03:18:54 PM PDT 24
Peak memory 200788 kb
Host smart-72b3e57c-eee2-4f17-8557-61a5ee202289
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730124023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
730124023
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2377303988
Short name T600
Test name
Test status
Simulation time 188657468 ps
CPU time 1.81 seconds
Started Apr 28 03:18:51 PM PDT 24
Finished Apr 28 03:18:54 PM PDT 24
Peak memory 209368 kb
Host smart-68373214-084b-4cb7-b7e3-380d99d4775d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377303988 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2377303988
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1777122635
Short name T551
Test name
Test status
Simulation time 87115882 ps
CPU time 0.84 seconds
Started Apr 28 03:18:51 PM PDT 24
Finished Apr 28 03:18:53 PM PDT 24
Peak memory 200876 kb
Host smart-dee3bbd0-61fd-4d4f-9656-dc8de0ff6fa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777122635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1777122635
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3995502993
Short name T575
Test name
Test status
Simulation time 149535098 ps
CPU time 1.25 seconds
Started Apr 28 03:18:56 PM PDT 24
Finished Apr 28 03:18:59 PM PDT 24
Peak memory 200948 kb
Host smart-b7cb1a68-ba08-41cb-9503-80eabfc6f11c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995502993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3995502993
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2113014510
Short name T578
Test name
Test status
Simulation time 405774216 ps
CPU time 3.11 seconds
Started Apr 28 03:18:51 PM PDT 24
Finished Apr 28 03:18:54 PM PDT 24
Peak memory 212288 kb
Host smart-2b65b041-52c1-41d6-9a6f-2f254ea68cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113014510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2113014510
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2853086237
Short name T60
Test name
Test status
Simulation time 909114364 ps
CPU time 2.95 seconds
Started Apr 28 03:18:48 PM PDT 24
Finished Apr 28 03:18:51 PM PDT 24
Peak memory 201132 kb
Host smart-e354e1da-62a7-4ee9-895d-7227d8b64870
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853086237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2853086237
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1255601361
Short name T55
Test name
Test status
Simulation time 433202531 ps
CPU time 2.66 seconds
Started Apr 28 03:18:53 PM PDT 24
Finished Apr 28 03:18:56 PM PDT 24
Peak memory 201060 kb
Host smart-eb5a0e70-add6-46f5-95f1-4a9acaf3dc78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255601361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
255601361
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2613665433
Short name T560
Test name
Test status
Simulation time 1188167852 ps
CPU time 5.58 seconds
Started Apr 28 03:18:51 PM PDT 24
Finished Apr 28 03:18:58 PM PDT 24
Peak memory 201068 kb
Host smart-05a8f65c-8b72-4505-b171-a16592439d6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613665433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
613665433
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2965537465
Short name T543
Test name
Test status
Simulation time 100623275 ps
CPU time 0.84 seconds
Started Apr 28 03:18:51 PM PDT 24
Finished Apr 28 03:18:53 PM PDT 24
Peak memory 200912 kb
Host smart-f8d5e16e-c3e5-4428-b92f-4bab8082988c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965537465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
965537465
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3975009469
Short name T612
Test name
Test status
Simulation time 123744180 ps
CPU time 1.04 seconds
Started Apr 28 03:18:52 PM PDT 24
Finished Apr 28 03:18:54 PM PDT 24
Peak memory 201040 kb
Host smart-5b81ef54-23a5-451c-ac10-f5ce70ff370e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975009469 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3975009469
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.214943433
Short name T580
Test name
Test status
Simulation time 73952603 ps
CPU time 0.81 seconds
Started Apr 28 03:18:51 PM PDT 24
Finished Apr 28 03:18:53 PM PDT 24
Peak memory 200880 kb
Host smart-f65b6780-7ac8-48a8-a047-720d43260034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214943433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.214943433
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3845098996
Short name T585
Test name
Test status
Simulation time 149694753 ps
CPU time 1.18 seconds
Started Apr 28 03:18:51 PM PDT 24
Finished Apr 28 03:18:53 PM PDT 24
Peak memory 200940 kb
Host smart-1ebb46b1-598f-4886-a467-b5596d9d0a9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845098996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3845098996
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.421783915
Short name T569
Test name
Test status
Simulation time 249121295 ps
CPU time 2.01 seconds
Started Apr 28 03:18:52 PM PDT 24
Finished Apr 28 03:18:55 PM PDT 24
Peak memory 209364 kb
Host smart-36650c06-e5a7-4cfd-b9f9-d1f7e74d0c21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421783915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.421783915
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.182194587
Short name T87
Test name
Test status
Simulation time 979661617 ps
CPU time 2.99 seconds
Started Apr 28 03:18:54 PM PDT 24
Finished Apr 28 03:18:57 PM PDT 24
Peak memory 201112 kb
Host smart-9e3e3945-9934-4ae9-bfc2-4eebc41b7b04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182194587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
182194587
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1194969489
Short name T548
Test name
Test status
Simulation time 110870447 ps
CPU time 1.06 seconds
Started Apr 28 03:19:06 PM PDT 24
Finished Apr 28 03:19:07 PM PDT 24
Peak memory 201028 kb
Host smart-cdf0fed6-d1e2-4686-b2ed-d3496c8f113d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194969489 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1194969489
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4199449551
Short name T103
Test name
Test status
Simulation time 65664137 ps
CPU time 0.79 seconds
Started Apr 28 03:19:10 PM PDT 24
Finished Apr 28 03:19:12 PM PDT 24
Peak memory 200800 kb
Host smart-e1705f47-4a62-43fd-b8a7-84fe725bfa60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199449551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4199449551
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2533540729
Short name T555
Test name
Test status
Simulation time 215741190 ps
CPU time 1.54 seconds
Started Apr 28 03:19:09 PM PDT 24
Finished Apr 28 03:19:11 PM PDT 24
Peak memory 201164 kb
Host smart-ae3200d3-d0e8-438d-9c22-bb23fadabb50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533540729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2533540729
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4165715360
Short name T85
Test name
Test status
Simulation time 639831819 ps
CPU time 3.99 seconds
Started Apr 28 03:19:07 PM PDT 24
Finished Apr 28 03:19:13 PM PDT 24
Peak memory 209396 kb
Host smart-e6f75581-7643-4902-831f-72538a5edaf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165715360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.4165715360
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.990635187
Short name T547
Test name
Test status
Simulation time 137823270 ps
CPU time 1.09 seconds
Started Apr 28 03:19:06 PM PDT 24
Finished Apr 28 03:19:08 PM PDT 24
Peak memory 209276 kb
Host smart-407d5a47-482d-42c7-82da-eb6018a970f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990635187 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.990635187
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2672302934
Short name T562
Test name
Test status
Simulation time 66188515 ps
CPU time 0.77 seconds
Started Apr 28 03:19:08 PM PDT 24
Finished Apr 28 03:19:10 PM PDT 24
Peak memory 200896 kb
Host smart-95b95e16-8256-4631-ac1d-2a0bb1cdc8f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672302934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2672302934
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1704191068
Short name T114
Test name
Test status
Simulation time 172540818 ps
CPU time 2.65 seconds
Started Apr 28 03:19:08 PM PDT 24
Finished Apr 28 03:19:12 PM PDT 24
Peak memory 209328 kb
Host smart-676e17c2-58ab-416c-805a-3f092311da92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704191068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1704191068
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4252396995
Short name T591
Test name
Test status
Simulation time 463951287 ps
CPU time 1.89 seconds
Started Apr 28 03:19:07 PM PDT 24
Finished Apr 28 03:19:11 PM PDT 24
Peak memory 201152 kb
Host smart-8ace4e37-9e70-461a-86f6-a9d5d39ad873
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252396995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4252396995
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3063089481
Short name T88
Test name
Test status
Simulation time 181075969 ps
CPU time 1.29 seconds
Started Apr 28 03:19:08 PM PDT 24
Finished Apr 28 03:19:11 PM PDT 24
Peak memory 201044 kb
Host smart-3247edd4-f223-4a37-8690-ec7945e3f186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063089481 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3063089481
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3573939359
Short name T584
Test name
Test status
Simulation time 58249470 ps
CPU time 0.72 seconds
Started Apr 28 03:19:09 PM PDT 24
Finished Apr 28 03:19:11 PM PDT 24
Peak memory 200892 kb
Host smart-a54ac617-a9fb-4968-a642-a4f2495aa4cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573939359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3573939359
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4006741617
Short name T571
Test name
Test status
Simulation time 157912176 ps
CPU time 1.15 seconds
Started Apr 28 03:19:08 PM PDT 24
Finished Apr 28 03:19:10 PM PDT 24
Peak memory 200964 kb
Host smart-b556de82-904a-4546-883c-c6e83348e4d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006741617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4006741617
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1819231514
Short name T597
Test name
Test status
Simulation time 115941663 ps
CPU time 1.6 seconds
Started Apr 28 03:19:08 PM PDT 24
Finished Apr 28 03:19:11 PM PDT 24
Peak memory 209328 kb
Host smart-8ba3f34a-06a6-4630-aa79-6d6148a472e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819231514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1819231514
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1667300210
Short name T615
Test name
Test status
Simulation time 760996544 ps
CPU time 2.91 seconds
Started Apr 28 03:19:08 PM PDT 24
Finished Apr 28 03:19:12 PM PDT 24
Peak memory 201192 kb
Host smart-9205aed8-6332-4a55-a947-c2f8ff6d2649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667300210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1667300210
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.716017448
Short name T567
Test name
Test status
Simulation time 138826188 ps
CPU time 1.15 seconds
Started Apr 28 03:19:07 PM PDT 24
Finished Apr 28 03:19:10 PM PDT 24
Peak memory 200940 kb
Host smart-7b4b2b49-2b71-4b7e-b704-fa9b9348ce99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716017448 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.716017448
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.279884856
Short name T105
Test name
Test status
Simulation time 64577789 ps
CPU time 0.78 seconds
Started Apr 28 03:19:06 PM PDT 24
Finished Apr 28 03:19:08 PM PDT 24
Peak memory 200896 kb
Host smart-2715ab2a-f3f1-4ad2-a527-f062e462079a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279884856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.279884856
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3180446463
Short name T598
Test name
Test status
Simulation time 128833039 ps
CPU time 1.15 seconds
Started Apr 28 03:19:07 PM PDT 24
Finished Apr 28 03:19:09 PM PDT 24
Peak memory 200940 kb
Host smart-a5bcb419-d546-420f-8fec-24fec50467ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180446463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3180446463
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1327042531
Short name T610
Test name
Test status
Simulation time 524568288 ps
CPU time 3.93 seconds
Started Apr 28 03:19:06 PM PDT 24
Finished Apr 28 03:19:10 PM PDT 24
Peak memory 209368 kb
Host smart-0118d865-17cf-46ce-aeda-49862791c689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327042531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1327042531
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1049020029
Short name T86
Test name
Test status
Simulation time 465083850 ps
CPU time 1.93 seconds
Started Apr 28 03:19:07 PM PDT 24
Finished Apr 28 03:19:11 PM PDT 24
Peak memory 201116 kb
Host smart-7c177926-46ae-4ad0-b962-eb6ab6c0a61a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049020029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1049020029
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.710796217
Short name T594
Test name
Test status
Simulation time 122149379 ps
CPU time 1.02 seconds
Started Apr 28 03:19:07 PM PDT 24
Finished Apr 28 03:19:10 PM PDT 24
Peak memory 200964 kb
Host smart-d93c9d01-7dd7-4d9c-a732-5f1f42381db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710796217 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.710796217
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2968282147
Short name T101
Test name
Test status
Simulation time 64485041 ps
CPU time 0.79 seconds
Started Apr 28 03:19:10 PM PDT 24
Finished Apr 28 03:19:12 PM PDT 24
Peak memory 200868 kb
Host smart-bd1e080c-6764-49d0-abe7-ce059407c26c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968282147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2968282147
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1262807317
Short name T587
Test name
Test status
Simulation time 107819774 ps
CPU time 1.24 seconds
Started Apr 28 03:19:07 PM PDT 24
Finished Apr 28 03:19:09 PM PDT 24
Peak memory 201112 kb
Host smart-9c83c378-82fd-494f-ba5a-ab8b930ac244
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262807317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1262807317
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3293009692
Short name T588
Test name
Test status
Simulation time 411149827 ps
CPU time 3.01 seconds
Started Apr 28 03:19:10 PM PDT 24
Finished Apr 28 03:19:14 PM PDT 24
Peak memory 209268 kb
Host smart-e5aaf06b-34be-4c63-a767-ab48617876bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293009692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3293009692
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1939635245
Short name T110
Test name
Test status
Simulation time 806210729 ps
CPU time 2.74 seconds
Started Apr 28 03:19:08 PM PDT 24
Finished Apr 28 03:19:12 PM PDT 24
Peak memory 201116 kb
Host smart-b22bf40b-f307-423c-ae7b-a8106d28e84c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939635245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1939635245
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.313779097
Short name T619
Test name
Test status
Simulation time 165582059 ps
CPU time 1.53 seconds
Started Apr 28 03:19:12 PM PDT 24
Finished Apr 28 03:19:15 PM PDT 24
Peak memory 214240 kb
Host smart-709d38d4-fe94-4419-9136-ebe4e497ef15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313779097 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.313779097
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.7899764
Short name T572
Test name
Test status
Simulation time 86703314 ps
CPU time 0.86 seconds
Started Apr 28 03:19:11 PM PDT 24
Finished Apr 28 03:19:13 PM PDT 24
Peak memory 200900 kb
Host smart-ee3b1e91-4433-4caa-879d-6496458349a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7899764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.7899764
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.282297892
Short name T618
Test name
Test status
Simulation time 75914948 ps
CPU time 0.93 seconds
Started Apr 28 03:19:11 PM PDT 24
Finished Apr 28 03:19:13 PM PDT 24
Peak memory 200988 kb
Host smart-583bbf8c-7ae7-4282-81f8-a6b2aa5ffeda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282297892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.282297892
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3530523284
Short name T581
Test name
Test status
Simulation time 195450343 ps
CPU time 3.05 seconds
Started Apr 28 03:19:06 PM PDT 24
Finished Apr 28 03:19:10 PM PDT 24
Peak memory 209308 kb
Host smart-8d443f7e-cf62-43ab-b5d2-63dd78cd7e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530523284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3530523284
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1996024371
Short name T559
Test name
Test status
Simulation time 441317741 ps
CPU time 1.7 seconds
Started Apr 28 03:19:09 PM PDT 24
Finished Apr 28 03:19:12 PM PDT 24
Peak memory 201108 kb
Host smart-017597a7-93ef-4b27-83de-41a22c4bb9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996024371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1996024371
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3519532200
Short name T613
Test name
Test status
Simulation time 94781965 ps
CPU time 0.97 seconds
Started Apr 28 03:19:12 PM PDT 24
Finished Apr 28 03:19:13 PM PDT 24
Peak memory 201008 kb
Host smart-b1150c56-b9d9-4a7e-96d9-8ce2bfa51d3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519532200 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3519532200
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2137897072
Short name T102
Test name
Test status
Simulation time 78371731 ps
CPU time 0.78 seconds
Started Apr 28 03:19:13 PM PDT 24
Finished Apr 28 03:19:15 PM PDT 24
Peak memory 200808 kb
Host smart-0b1f50f1-5b30-4cff-b92a-568f40d2f36b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137897072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2137897072
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3038246323
Short name T573
Test name
Test status
Simulation time 142647128 ps
CPU time 1.1 seconds
Started Apr 28 03:19:15 PM PDT 24
Finished Apr 28 03:19:17 PM PDT 24
Peak memory 200952 kb
Host smart-d66fee55-6acf-485c-abfb-dfc032fdfad4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038246323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3038246323
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3416160679
Short name T113
Test name
Test status
Simulation time 175664929 ps
CPU time 2.43 seconds
Started Apr 28 03:19:15 PM PDT 24
Finished Apr 28 03:19:19 PM PDT 24
Peak memory 209380 kb
Host smart-baf4e20b-322c-4ee6-962c-f1d1ba592e72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416160679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3416160679
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1935626282
Short name T556
Test name
Test status
Simulation time 426294160 ps
CPU time 1.82 seconds
Started Apr 28 03:19:16 PM PDT 24
Finished Apr 28 03:19:19 PM PDT 24
Peak memory 201140 kb
Host smart-9f581f1e-57ec-4844-840c-4f0d71547890
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935626282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1935626282
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3998589923
Short name T57
Test name
Test status
Simulation time 193498586 ps
CPU time 1.18 seconds
Started Apr 28 03:19:13 PM PDT 24
Finished Apr 28 03:19:15 PM PDT 24
Peak memory 209224 kb
Host smart-efb0484a-1e04-4b91-887f-3861d1fcaabc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998589923 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3998589923
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2406502155
Short name T602
Test name
Test status
Simulation time 76704774 ps
CPU time 0.8 seconds
Started Apr 28 03:19:15 PM PDT 24
Finished Apr 28 03:19:17 PM PDT 24
Peak memory 200816 kb
Host smart-27c485c6-3588-4fd9-814e-b43ed5708787
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406502155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2406502155
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.4066581835
Short name T611
Test name
Test status
Simulation time 139116237 ps
CPU time 1.12 seconds
Started Apr 28 03:19:12 PM PDT 24
Finished Apr 28 03:19:14 PM PDT 24
Peak memory 200812 kb
Host smart-9df7f6cf-8b8b-4b01-bcda-20669a04dd15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066581835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.4066581835
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2524113723
Short name T579
Test name
Test status
Simulation time 366745708 ps
CPU time 2.39 seconds
Started Apr 28 03:19:13 PM PDT 24
Finished Apr 28 03:19:16 PM PDT 24
Peak memory 201096 kb
Host smart-b4419e93-5f53-4349-a52d-1af9883fb42b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524113723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2524113723
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2486957050
Short name T106
Test name
Test status
Simulation time 499377917 ps
CPU time 1.95 seconds
Started Apr 28 03:19:14 PM PDT 24
Finished Apr 28 03:19:17 PM PDT 24
Peak memory 201192 kb
Host smart-b8c4848c-6247-4277-9043-a06018be2c17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486957050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2486957050
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3146953713
Short name T56
Test name
Test status
Simulation time 194832832 ps
CPU time 1.28 seconds
Started Apr 28 03:19:13 PM PDT 24
Finished Apr 28 03:19:16 PM PDT 24
Peak memory 209240 kb
Host smart-f3bd3269-8b4e-44a1-85b2-7ce2f878bd8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146953713 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3146953713
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2209918444
Short name T544
Test name
Test status
Simulation time 86745891 ps
CPU time 0.89 seconds
Started Apr 28 03:19:11 PM PDT 24
Finished Apr 28 03:19:13 PM PDT 24
Peak memory 200908 kb
Host smart-faf48af6-c522-4351-9e06-9c557548aa73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209918444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2209918444
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1088680638
Short name T97
Test name
Test status
Simulation time 139023271 ps
CPU time 1.31 seconds
Started Apr 28 03:19:14 PM PDT 24
Finished Apr 28 03:19:16 PM PDT 24
Peak memory 201188 kb
Host smart-270be9cc-9a79-47e9-9ba4-68e1dfc2359c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088680638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1088680638
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3406822811
Short name T593
Test name
Test status
Simulation time 143328954 ps
CPU time 1.88 seconds
Started Apr 28 03:19:12 PM PDT 24
Finished Apr 28 03:19:15 PM PDT 24
Peak memory 217212 kb
Host smart-a1bd3d27-7ee7-40ae-a948-d013d11d0948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406822811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3406822811
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4198585186
Short name T59
Test name
Test status
Simulation time 484861211 ps
CPU time 1.87 seconds
Started Apr 28 03:19:13 PM PDT 24
Finished Apr 28 03:19:16 PM PDT 24
Peak memory 201116 kb
Host smart-ec2ca87f-c0dc-4a70-9256-cd0e402178c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198585186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.4198585186
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1663275146
Short name T553
Test name
Test status
Simulation time 149649973 ps
CPU time 1.15 seconds
Started Apr 28 03:19:15 PM PDT 24
Finished Apr 28 03:19:17 PM PDT 24
Peak memory 209144 kb
Host smart-d27c9180-2e61-408d-97ec-ad51fc305979
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663275146 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1663275146
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4249087336
Short name T605
Test name
Test status
Simulation time 86991145 ps
CPU time 0.88 seconds
Started Apr 28 03:19:14 PM PDT 24
Finished Apr 28 03:19:16 PM PDT 24
Peak memory 200904 kb
Host smart-a138ef40-dbc1-447c-92ba-0ed07b295a1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249087336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.4249087336
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1090148999
Short name T608
Test name
Test status
Simulation time 175527820 ps
CPU time 1.38 seconds
Started Apr 28 03:19:12 PM PDT 24
Finished Apr 28 03:19:14 PM PDT 24
Peak memory 201140 kb
Host smart-b053bb30-f41c-4541-8168-1c2d479a94d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090148999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1090148999
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3027521417
Short name T590
Test name
Test status
Simulation time 535282320 ps
CPU time 3.47 seconds
Started Apr 28 03:19:13 PM PDT 24
Finished Apr 28 03:19:18 PM PDT 24
Peak memory 217508 kb
Host smart-7f825d2f-241d-4163-b6c3-5e3e249da728
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027521417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3027521417
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3119190768
Short name T127
Test name
Test status
Simulation time 889330246 ps
CPU time 3.12 seconds
Started Apr 28 03:19:12 PM PDT 24
Finished Apr 28 03:19:16 PM PDT 24
Peak memory 201092 kb
Host smart-9442f4e9-d6db-45ad-9aa0-efd7d353d5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119190768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3119190768
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3368688171
Short name T596
Test name
Test status
Simulation time 369827939 ps
CPU time 2.43 seconds
Started Apr 28 03:18:52 PM PDT 24
Finished Apr 28 03:18:55 PM PDT 24
Peak memory 201116 kb
Host smart-4ce243cf-3900-49fa-958f-2dd8b0781833
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368688171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
368688171
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1669308758
Short name T586
Test name
Test status
Simulation time 2303917704 ps
CPU time 10.94 seconds
Started Apr 28 03:18:54 PM PDT 24
Finished Apr 28 03:19:06 PM PDT 24
Peak memory 201180 kb
Host smart-f85d841b-25b0-467e-97b3-36118c6271fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669308758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
669308758
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2577073854
Short name T552
Test name
Test status
Simulation time 116196401 ps
CPU time 0.88 seconds
Started Apr 28 03:18:51 PM PDT 24
Finished Apr 28 03:18:53 PM PDT 24
Peak memory 200860 kb
Host smart-c3bd9e1c-ee82-4745-9948-e50ff7875fa2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577073854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
577073854
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1642736361
Short name T595
Test name
Test status
Simulation time 185865500 ps
CPU time 1.74 seconds
Started Apr 28 03:18:51 PM PDT 24
Finished Apr 28 03:18:54 PM PDT 24
Peak memory 209368 kb
Host smart-bc74be0c-79f5-4bba-b81d-512ac92a4587
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642736361 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1642736361
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3113360412
Short name T582
Test name
Test status
Simulation time 72953113 ps
CPU time 0.79 seconds
Started Apr 28 03:18:56 PM PDT 24
Finished Apr 28 03:18:57 PM PDT 24
Peak memory 200888 kb
Host smart-80b390a5-c0ce-44d2-bbd3-2326a2721949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113360412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3113360412
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3255856907
Short name T606
Test name
Test status
Simulation time 72371828 ps
CPU time 0.93 seconds
Started Apr 28 03:18:53 PM PDT 24
Finished Apr 28 03:18:55 PM PDT 24
Peak memory 200868 kb
Host smart-6283cf84-bc53-4f8d-84b4-303cc8a8d650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255856907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3255856907
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1601808277
Short name T564
Test name
Test status
Simulation time 237570050 ps
CPU time 3.53 seconds
Started Apr 28 03:18:53 PM PDT 24
Finished Apr 28 03:18:57 PM PDT 24
Peak memory 201148 kb
Host smart-364e405f-e319-4a9d-9277-61da365ff777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601808277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1601808277
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3530707771
Short name T111
Test name
Test status
Simulation time 891254287 ps
CPU time 3.1 seconds
Started Apr 28 03:18:56 PM PDT 24
Finished Apr 28 03:19:00 PM PDT 24
Peak memory 201132 kb
Host smart-4493e569-dfcd-4581-8eb0-7a349fd5c28b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530707771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3530707771
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2931530614
Short name T546
Test name
Test status
Simulation time 148531589 ps
CPU time 1.93 seconds
Started Apr 28 03:18:57 PM PDT 24
Finished Apr 28 03:19:00 PM PDT 24
Peak memory 209288 kb
Host smart-dc483498-2fa3-4c43-99ee-6f5b136c935f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931530614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
931530614
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2859182058
Short name T614
Test name
Test status
Simulation time 797823000 ps
CPU time 5.05 seconds
Started Apr 28 03:18:58 PM PDT 24
Finished Apr 28 03:19:04 PM PDT 24
Peak memory 201044 kb
Host smart-15b0e7e1-0986-44fd-a31f-15f7fb78d270
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859182058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
859182058
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1377869585
Short name T616
Test name
Test status
Simulation time 99486874 ps
CPU time 0.93 seconds
Started Apr 28 03:18:57 PM PDT 24
Finished Apr 28 03:18:59 PM PDT 24
Peak memory 200884 kb
Host smart-2533da70-75b0-4e7a-9ca9-3f49f33a8365
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377869585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
377869585
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3267526507
Short name T558
Test name
Test status
Simulation time 124493398 ps
CPU time 1.02 seconds
Started Apr 28 03:18:58 PM PDT 24
Finished Apr 28 03:18:59 PM PDT 24
Peak memory 201292 kb
Host smart-efc32b62-116e-427e-9d2f-377890a9f03a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267526507 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3267526507
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1012980038
Short name T549
Test name
Test status
Simulation time 68114493 ps
CPU time 0.77 seconds
Started Apr 28 03:18:57 PM PDT 24
Finished Apr 28 03:18:59 PM PDT 24
Peak memory 200836 kb
Host smart-866e64f2-d8b5-4c94-90ef-ed9e2a214753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012980038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1012980038
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1743832478
Short name T557
Test name
Test status
Simulation time 83439302 ps
CPU time 0.98 seconds
Started Apr 28 03:18:59 PM PDT 24
Finished Apr 28 03:19:01 PM PDT 24
Peak memory 200936 kb
Host smart-7ac3e053-bb47-4650-b4ce-9ac29adb36c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743832478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1743832478
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.107772170
Short name T563
Test name
Test status
Simulation time 318542645 ps
CPU time 2.52 seconds
Started Apr 28 03:18:57 PM PDT 24
Finished Apr 28 03:19:01 PM PDT 24
Peak memory 209348 kb
Host smart-31bc88d5-089b-40c8-943b-841ab68ca975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107772170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.107772170
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2951407156
Short name T620
Test name
Test status
Simulation time 934963714 ps
CPU time 3.29 seconds
Started Apr 28 03:19:00 PM PDT 24
Finished Apr 28 03:19:05 PM PDT 24
Peak memory 201136 kb
Host smart-3676f333-b885-4138-a061-adbb231de53e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951407156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2951407156
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2165322963
Short name T550
Test name
Test status
Simulation time 152983335 ps
CPU time 1.94 seconds
Started Apr 28 03:18:58 PM PDT 24
Finished Apr 28 03:19:00 PM PDT 24
Peak memory 201080 kb
Host smart-86c929d2-a165-413c-b380-aa4771eb8a60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165322963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
165322963
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2631407667
Short name T129
Test name
Test status
Simulation time 1562999008 ps
CPU time 8.09 seconds
Started Apr 28 03:18:56 PM PDT 24
Finished Apr 28 03:19:05 PM PDT 24
Peak memory 201116 kb
Host smart-55d6cc19-f4d1-45d8-822e-4b0bf1dd7790
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631407667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
631407667
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1267972641
Short name T583
Test name
Test status
Simulation time 102665646 ps
CPU time 0.81 seconds
Started Apr 28 03:18:56 PM PDT 24
Finished Apr 28 03:18:58 PM PDT 24
Peak memory 200884 kb
Host smart-e63ecb74-2fd5-4aff-b1d1-286009f8f670
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267972641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
267972641
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2983171395
Short name T98
Test name
Test status
Simulation time 85994349 ps
CPU time 0.86 seconds
Started Apr 28 03:18:59 PM PDT 24
Finished Apr 28 03:19:00 PM PDT 24
Peak memory 200880 kb
Host smart-b87592bc-3193-4fca-a539-353fc4dbf973
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983171395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2983171395
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3664430216
Short name T100
Test name
Test status
Simulation time 244991215 ps
CPU time 1.56 seconds
Started Apr 28 03:19:00 PM PDT 24
Finished Apr 28 03:19:02 PM PDT 24
Peak memory 201120 kb
Host smart-2d855446-dcb7-41c5-94f1-d5d135255d90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664430216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3664430216
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1251729488
Short name T84
Test name
Test status
Simulation time 178821610 ps
CPU time 2.55 seconds
Started Apr 28 03:18:57 PM PDT 24
Finished Apr 28 03:19:01 PM PDT 24
Peak memory 209316 kb
Host smart-0a7f61ba-ab2b-4b71-b3e0-be5ee94ee5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251729488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1251729488
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3907934707
Short name T577
Test name
Test status
Simulation time 504989537 ps
CPU time 1.96 seconds
Started Apr 28 03:18:57 PM PDT 24
Finished Apr 28 03:19:00 PM PDT 24
Peak memory 201144 kb
Host smart-06d7fb94-5c31-49e6-8ba4-8b2c553b8b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907934707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3907934707
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4080704058
Short name T561
Test name
Test status
Simulation time 175981011 ps
CPU time 1.15 seconds
Started Apr 28 03:19:01 PM PDT 24
Finished Apr 28 03:19:03 PM PDT 24
Peak memory 201012 kb
Host smart-2df136d0-0e13-4492-b5e2-ad0ae3395655
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080704058 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4080704058
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1630292008
Short name T565
Test name
Test status
Simulation time 53817136 ps
CPU time 0.75 seconds
Started Apr 28 03:18:56 PM PDT 24
Finished Apr 28 03:18:57 PM PDT 24
Peak memory 200808 kb
Host smart-ec4b0c4c-c122-42b3-81e9-84ca196f24ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630292008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1630292008
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.902433629
Short name T576
Test name
Test status
Simulation time 222984266 ps
CPU time 1.58 seconds
Started Apr 28 03:18:56 PM PDT 24
Finished Apr 28 03:19:00 PM PDT 24
Peak memory 201144 kb
Host smart-d9fda35f-7a27-448a-8b7d-314d0edc506f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902433629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.902433629
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3412028302
Short name T603
Test name
Test status
Simulation time 490318492 ps
CPU time 3.3 seconds
Started Apr 28 03:19:01 PM PDT 24
Finished Apr 28 03:19:05 PM PDT 24
Peak memory 209316 kb
Host smart-2d2a3912-0144-4bca-9700-7c8bcc716b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412028302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3412028302
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4084593286
Short name T128
Test name
Test status
Simulation time 463317170 ps
CPU time 2.01 seconds
Started Apr 28 03:18:57 PM PDT 24
Finished Apr 28 03:19:00 PM PDT 24
Peak memory 201148 kb
Host smart-5c9647f8-1f7d-4d5f-ac28-5bd32ec542db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084593286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.4084593286
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3115247874
Short name T604
Test name
Test status
Simulation time 172039341 ps
CPU time 1.59 seconds
Started Apr 28 03:19:02 PM PDT 24
Finished Apr 28 03:19:04 PM PDT 24
Peak memory 209440 kb
Host smart-6a2e1986-628b-4ee9-9f78-517bbe405566
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115247874 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3115247874
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.327389178
Short name T554
Test name
Test status
Simulation time 60814543 ps
CPU time 0.79 seconds
Started Apr 28 03:19:02 PM PDT 24
Finished Apr 28 03:19:04 PM PDT 24
Peak memory 200892 kb
Host smart-ce95a37b-40a1-4812-a0d1-93829400a582
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327389178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.327389178
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3967284146
Short name T570
Test name
Test status
Simulation time 218789105 ps
CPU time 1.53 seconds
Started Apr 28 03:19:01 PM PDT 24
Finished Apr 28 03:19:03 PM PDT 24
Peak memory 201176 kb
Host smart-4fdd78a0-0528-460f-8ce0-51f111f4c997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967284146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3967284146
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3123634861
Short name T592
Test name
Test status
Simulation time 441781725 ps
CPU time 3.73 seconds
Started Apr 28 03:19:03 PM PDT 24
Finished Apr 28 03:19:07 PM PDT 24
Peak memory 209296 kb
Host smart-79118376-de77-4ccb-95c8-ea1e96bed52c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123634861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3123634861
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2561953716
Short name T568
Test name
Test status
Simulation time 164283991 ps
CPU time 1.58 seconds
Started Apr 28 03:19:02 PM PDT 24
Finished Apr 28 03:19:04 PM PDT 24
Peak memory 209388 kb
Host smart-baf2c1ef-639b-447b-be14-d050f077ae79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561953716 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2561953716
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.629396292
Short name T599
Test name
Test status
Simulation time 76730624 ps
CPU time 0.82 seconds
Started Apr 28 03:19:02 PM PDT 24
Finished Apr 28 03:19:04 PM PDT 24
Peak memory 200784 kb
Host smart-52148832-0c48-49a3-890b-2b10e879ae18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629396292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.629396292
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3606032480
Short name T104
Test name
Test status
Simulation time 127333350 ps
CPU time 1.1 seconds
Started Apr 28 03:19:00 PM PDT 24
Finished Apr 28 03:19:02 PM PDT 24
Peak memory 200980 kb
Host smart-064af554-066a-4063-99da-59926eec6739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606032480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3606032480
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1564893936
Short name T574
Test name
Test status
Simulation time 179832379 ps
CPU time 1.78 seconds
Started Apr 28 03:19:05 PM PDT 24
Finished Apr 28 03:19:07 PM PDT 24
Peak memory 209516 kb
Host smart-7841d775-49c4-49cb-b6b2-7a310c31868e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564893936 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1564893936
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1337165645
Short name T607
Test name
Test status
Simulation time 59230444 ps
CPU time 0.89 seconds
Started Apr 28 03:19:02 PM PDT 24
Finished Apr 28 03:19:03 PM PDT 24
Peak memory 200856 kb
Host smart-fc224c1f-cdfd-4f2f-83b8-f31b1e94eca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337165645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1337165645
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4016063434
Short name T617
Test name
Test status
Simulation time 225693935 ps
CPU time 1.66 seconds
Started Apr 28 03:19:02 PM PDT 24
Finished Apr 28 03:19:04 PM PDT 24
Peak memory 201160 kb
Host smart-507bb9b6-7ea0-4c8a-b994-c18a3b0669fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016063434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4016063434
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.825198483
Short name T89
Test name
Test status
Simulation time 189866759 ps
CPU time 2.61 seconds
Started Apr 28 03:19:04 PM PDT 24
Finished Apr 28 03:19:07 PM PDT 24
Peak memory 209332 kb
Host smart-d6f9ee90-00f3-437e-8730-be1fadb12639
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825198483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.825198483
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1372740173
Short name T109
Test name
Test status
Simulation time 495919425 ps
CPU time 1.85 seconds
Started Apr 28 03:19:04 PM PDT 24
Finished Apr 28 03:19:06 PM PDT 24
Peak memory 201148 kb
Host smart-b9a88368-b921-40b8-967e-380fdd5214e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372740173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1372740173
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3268885379
Short name T61
Test name
Test status
Simulation time 118535065 ps
CPU time 0.93 seconds
Started Apr 28 03:19:02 PM PDT 24
Finished Apr 28 03:19:04 PM PDT 24
Peak memory 200960 kb
Host smart-9df75d12-a1a2-4f74-a681-b6df4c81570c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268885379 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3268885379
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2259966445
Short name T99
Test name
Test status
Simulation time 59981628 ps
CPU time 0.85 seconds
Started Apr 28 03:19:03 PM PDT 24
Finished Apr 28 03:19:04 PM PDT 24
Peak memory 200848 kb
Host smart-930ba94b-b03a-46bf-a909-ba88d98ef964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259966445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2259966445
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2079332289
Short name T589
Test name
Test status
Simulation time 95208130 ps
CPU time 1.25 seconds
Started Apr 28 03:19:01 PM PDT 24
Finished Apr 28 03:19:03 PM PDT 24
Peak memory 201188 kb
Host smart-a21f787d-b0a9-440a-a16f-6a8237a0effd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079332289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2079332289
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1284175431
Short name T566
Test name
Test status
Simulation time 134319030 ps
CPU time 1.92 seconds
Started Apr 28 03:19:02 PM PDT 24
Finished Apr 28 03:19:05 PM PDT 24
Peak memory 211816 kb
Host smart-a993a248-2bbe-49b3-a6c2-3e7de96f9781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284175431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1284175431
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3905474525
Short name T107
Test name
Test status
Simulation time 455608401 ps
CPU time 1.91 seconds
Started Apr 28 03:19:03 PM PDT 24
Finished Apr 28 03:19:06 PM PDT 24
Peak memory 201104 kb
Host smart-40d0a2a2-21da-42fe-875a-3b9321f46adf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905474525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3905474525
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2818742638
Short name T210
Test name
Test status
Simulation time 245654242 ps
CPU time 1.04 seconds
Started Apr 28 02:08:39 PM PDT 24
Finished Apr 28 02:08:40 PM PDT 24
Peak memory 218308 kb
Host smart-7e2cca35-4344-412f-aa45-e502882a5ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818742638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2818742638
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3342335838
Short name T445
Test name
Test status
Simulation time 1246667896 ps
CPU time 4.88 seconds
Started Apr 28 02:08:32 PM PDT 24
Finished Apr 28 02:08:37 PM PDT 24
Peak memory 201040 kb
Host smart-0203f954-6ba6-49e2-8285-a5d31c88ccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342335838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3342335838
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2439314280
Short name T63
Test name
Test status
Simulation time 16755166197 ps
CPU time 25 seconds
Started Apr 28 02:08:47 PM PDT 24
Finished Apr 28 02:09:13 PM PDT 24
Peak memory 217792 kb
Host smart-58525d15-edef-4afb-8b5b-bdf2b952c1e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439314280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2439314280
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3296974741
Short name T290
Test name
Test status
Simulation time 176282837 ps
CPU time 1.12 seconds
Started Apr 28 02:08:38 PM PDT 24
Finished Apr 28 02:08:39 PM PDT 24
Peak memory 200900 kb
Host smart-54f03ea8-0ae3-45cc-a304-be797a72b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296974741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3296974741
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.572128788
Short name T535
Test name
Test status
Simulation time 117821067 ps
CPU time 1.21 seconds
Started Apr 28 02:08:32 PM PDT 24
Finished Apr 28 02:08:34 PM PDT 24
Peak memory 201016 kb
Host smart-c94b617f-b1d6-4290-8ca5-ed3b9593081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572128788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.572128788
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.378142332
Short name T389
Test name
Test status
Simulation time 7534391002 ps
CPU time 30.74 seconds
Started Apr 28 02:08:45 PM PDT 24
Finished Apr 28 02:09:16 PM PDT 24
Peak memory 201200 kb
Host smart-89fa50a0-f1a1-4667-ac5e-d035b87129b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378142332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.378142332
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3072928875
Short name T176
Test name
Test status
Simulation time 432275279 ps
CPU time 2.32 seconds
Started Apr 28 02:08:38 PM PDT 24
Finished Apr 28 02:08:41 PM PDT 24
Peak memory 209032 kb
Host smart-aa411f22-6072-4419-afa0-e7f146f5deb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072928875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3072928875
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.885716536
Short name T411
Test name
Test status
Simulation time 68699387 ps
CPU time 0.74 seconds
Started Apr 28 02:08:43 PM PDT 24
Finished Apr 28 02:08:44 PM PDT 24
Peak memory 200580 kb
Host smart-bd58ba49-bd01-4ae4-9d99-a4758a4c4be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885716536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.885716536
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3414007195
Short name T50
Test name
Test status
Simulation time 1886420135 ps
CPU time 7.05 seconds
Started Apr 28 02:08:45 PM PDT 24
Finished Apr 28 02:08:53 PM PDT 24
Peak memory 218624 kb
Host smart-b42c8d0d-5b01-4e95-b60b-c252a0af63f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414007195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3414007195
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3761986679
Short name T478
Test name
Test status
Simulation time 245069777 ps
CPU time 1.06 seconds
Started Apr 28 02:08:43 PM PDT 24
Finished Apr 28 02:08:45 PM PDT 24
Peak memory 218072 kb
Host smart-d6209ec9-d0a8-4bbb-9caf-21b853f93d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761986679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3761986679
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2337650134
Short name T209
Test name
Test status
Simulation time 99659037 ps
CPU time 0.82 seconds
Started Apr 28 02:08:47 PM PDT 24
Finished Apr 28 02:08:48 PM PDT 24
Peak memory 200692 kb
Host smart-ce4c150a-d645-4392-951e-44bee4af58dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337650134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2337650134
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1553174611
Short name T45
Test name
Test status
Simulation time 1062113336 ps
CPU time 4.84 seconds
Started Apr 28 02:08:46 PM PDT 24
Finished Apr 28 02:08:52 PM PDT 24
Peak memory 200980 kb
Host smart-4df6abb8-751a-42af-afb4-817cf2b7b9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553174611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1553174611
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4071834571
Short name T64
Test name
Test status
Simulation time 8347106467 ps
CPU time 12.71 seconds
Started Apr 28 02:08:47 PM PDT 24
Finished Apr 28 02:09:00 PM PDT 24
Peak memory 217744 kb
Host smart-fd8c132e-0aca-48c7-8dc0-dbfedb4f95cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071834571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4071834571
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2914691119
Short name T415
Test name
Test status
Simulation time 142702780 ps
CPU time 1.16 seconds
Started Apr 28 02:08:44 PM PDT 24
Finished Apr 28 02:08:45 PM PDT 24
Peak memory 200816 kb
Host smart-1dc84134-1f01-4262-b805-4620b47a2fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914691119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2914691119
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1760415811
Short name T249
Test name
Test status
Simulation time 192274404 ps
CPU time 1.32 seconds
Started Apr 28 02:08:45 PM PDT 24
Finished Apr 28 02:08:47 PM PDT 24
Peak memory 200980 kb
Host smart-b240634a-ccc4-4f2f-9e3f-85c380121546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760415811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1760415811
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2350416617
Short name T294
Test name
Test status
Simulation time 8300355659 ps
CPU time 28.51 seconds
Started Apr 28 02:08:44 PM PDT 24
Finished Apr 28 02:09:13 PM PDT 24
Peak memory 201216 kb
Host smart-435c381f-4236-4755-8224-b14f89e63521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350416617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2350416617
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2552175367
Short name T391
Test name
Test status
Simulation time 99537380 ps
CPU time 0.94 seconds
Started Apr 28 02:08:42 PM PDT 24
Finished Apr 28 02:08:44 PM PDT 24
Peak memory 200816 kb
Host smart-eab098d8-e85a-4d6c-a02e-e5aa8c8ff8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552175367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2552175367
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3449867626
Short name T534
Test name
Test status
Simulation time 129994104 ps
CPU time 0.88 seconds
Started Apr 28 02:09:09 PM PDT 24
Finished Apr 28 02:09:11 PM PDT 24
Peak memory 200728 kb
Host smart-dfed20d8-6c12-4e3f-a81c-5be7e8166cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449867626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3449867626
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2897048627
Short name T314
Test name
Test status
Simulation time 1239493853 ps
CPU time 5.25 seconds
Started Apr 28 02:09:04 PM PDT 24
Finished Apr 28 02:09:09 PM PDT 24
Peak memory 217696 kb
Host smart-e747fa91-a7b6-44a4-813d-ba369a09d681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897048627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2897048627
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4001246956
Short name T227
Test name
Test status
Simulation time 245775368 ps
CPU time 1.01 seconds
Started Apr 28 02:09:05 PM PDT 24
Finished Apr 28 02:09:06 PM PDT 24
Peak memory 218228 kb
Host smart-a2e98822-5515-474a-9859-eef9b9137f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001246956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.4001246956
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2125064286
Short name T166
Test name
Test status
Simulation time 99412422 ps
CPU time 0.73 seconds
Started Apr 28 02:09:04 PM PDT 24
Finished Apr 28 02:09:05 PM PDT 24
Peak memory 200644 kb
Host smart-66b2941e-93f9-4400-a7f9-ffc49db12b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125064286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2125064286
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2341020261
Short name T90
Test name
Test status
Simulation time 977125202 ps
CPU time 4.67 seconds
Started Apr 28 02:09:05 PM PDT 24
Finished Apr 28 02:09:10 PM PDT 24
Peak memory 200992 kb
Host smart-b1e1a90c-7a23-4cd1-b85d-43c9d7d43b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341020261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2341020261
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.678764200
Short name T304
Test name
Test status
Simulation time 190023838 ps
CPU time 1.28 seconds
Started Apr 28 02:09:08 PM PDT 24
Finished Apr 28 02:09:10 PM PDT 24
Peak memory 200824 kb
Host smart-003f7f74-dd9e-4d8d-ae76-dd480d9513e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678764200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.678764200
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.584072659
Short name T193
Test name
Test status
Simulation time 117529636 ps
CPU time 1.12 seconds
Started Apr 28 02:09:05 PM PDT 24
Finished Apr 28 02:09:06 PM PDT 24
Peak memory 200976 kb
Host smart-e03a2361-1f98-495e-b8e8-834f17091538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584072659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.584072659
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3815286655
Short name T494
Test name
Test status
Simulation time 170695575 ps
CPU time 1.15 seconds
Started Apr 28 02:09:09 PM PDT 24
Finished Apr 28 02:09:11 PM PDT 24
Peak memory 200776 kb
Host smart-490e31bc-2422-451c-bb59-b945b96f6f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815286655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3815286655
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2651756273
Short name T222
Test name
Test status
Simulation time 257947071 ps
CPU time 1.83 seconds
Started Apr 28 02:09:10 PM PDT 24
Finished Apr 28 02:09:12 PM PDT 24
Peak memory 200776 kb
Host smart-93f04df1-21cd-4b55-bceb-bfeb8109c4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651756273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2651756273
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.866185925
Short name T479
Test name
Test status
Simulation time 158241468 ps
CPU time 1.11 seconds
Started Apr 28 02:09:10 PM PDT 24
Finished Apr 28 02:09:12 PM PDT 24
Peak memory 200792 kb
Host smart-1ba4bc76-d9ea-4e5c-95cd-d5698dbbf26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866185925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.866185925
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.246160257
Short name T241
Test name
Test status
Simulation time 70579748 ps
CPU time 0.77 seconds
Started Apr 28 02:09:12 PM PDT 24
Finished Apr 28 02:09:14 PM PDT 24
Peak memory 200676 kb
Host smart-2dd5cf4e-4995-401a-a14d-3326c172c18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246160257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.246160257
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1229238218
Short name T48
Test name
Test status
Simulation time 1229168608 ps
CPU time 5.7 seconds
Started Apr 28 02:09:10 PM PDT 24
Finished Apr 28 02:09:17 PM PDT 24
Peak memory 218600 kb
Host smart-00605f8c-a144-45a3-8a92-83223ee8bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229238218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1229238218
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.247774577
Short name T134
Test name
Test status
Simulation time 247073090 ps
CPU time 1.05 seconds
Started Apr 28 02:09:10 PM PDT 24
Finished Apr 28 02:09:12 PM PDT 24
Peak memory 218268 kb
Host smart-9cbd54ef-15a9-4bd4-ae15-a5d8342fc579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247774577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.247774577
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.271051942
Short name T268
Test name
Test status
Simulation time 121619110 ps
CPU time 0.78 seconds
Started Apr 28 02:09:09 PM PDT 24
Finished Apr 28 02:09:10 PM PDT 24
Peak memory 200644 kb
Host smart-26e446ac-430e-4c8e-93e0-9d5685551776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271051942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.271051942
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.56683171
Short name T70
Test name
Test status
Simulation time 1811261166 ps
CPU time 6.48 seconds
Started Apr 28 02:09:08 PM PDT 24
Finished Apr 28 02:09:15 PM PDT 24
Peak memory 201064 kb
Host smart-5beb2ca7-0216-4876-ac70-31f11b1f6e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56683171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.56683171
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.869350351
Short name T215
Test name
Test status
Simulation time 195486664 ps
CPU time 1.3 seconds
Started Apr 28 02:09:10 PM PDT 24
Finished Apr 28 02:09:12 PM PDT 24
Peak memory 201104 kb
Host smart-d41baa24-f087-4075-a280-93bfa4427ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869350351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.869350351
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1709496661
Short name T173
Test name
Test status
Simulation time 123034027 ps
CPU time 1.16 seconds
Started Apr 28 02:09:13 PM PDT 24
Finished Apr 28 02:09:15 PM PDT 24
Peak memory 200688 kb
Host smart-ae33b6a1-b2a3-4409-8127-2625675ee7d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709496661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1709496661
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1424634267
Short name T430
Test name
Test status
Simulation time 388198673 ps
CPU time 2.48 seconds
Started Apr 28 02:09:13 PM PDT 24
Finished Apr 28 02:09:16 PM PDT 24
Peak memory 200856 kb
Host smart-d8a23b41-78c8-4413-b483-8f66960fce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424634267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1424634267
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3093316617
Short name T396
Test name
Test status
Simulation time 254782496 ps
CPU time 1.5 seconds
Started Apr 28 02:09:08 PM PDT 24
Finished Apr 28 02:09:10 PM PDT 24
Peak memory 201088 kb
Host smart-41b295d6-de62-485e-9545-0d44729fd245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093316617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3093316617
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3858489756
Short name T177
Test name
Test status
Simulation time 74194797 ps
CPU time 0.83 seconds
Started Apr 28 02:09:09 PM PDT 24
Finished Apr 28 02:09:11 PM PDT 24
Peak memory 200732 kb
Host smart-a0db6d04-75b6-4700-89c0-33ac816ab132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858489756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3858489756
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3941430958
Short name T46
Test name
Test status
Simulation time 1894011378 ps
CPU time 7.19 seconds
Started Apr 28 02:09:09 PM PDT 24
Finished Apr 28 02:09:17 PM PDT 24
Peak memory 222700 kb
Host smart-b6ff26bf-f768-4892-9a64-958d1bfb0924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941430958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3941430958
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1805898713
Short name T465
Test name
Test status
Simulation time 244114082 ps
CPU time 1.13 seconds
Started Apr 28 02:09:08 PM PDT 24
Finished Apr 28 02:09:10 PM PDT 24
Peak memory 218304 kb
Host smart-8dec6a07-bd10-4dff-8b7f-8db0d973ac7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805898713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1805898713
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3810048149
Short name T370
Test name
Test status
Simulation time 140485928 ps
CPU time 0.84 seconds
Started Apr 28 02:09:13 PM PDT 24
Finished Apr 28 02:09:14 PM PDT 24
Peak memory 200708 kb
Host smart-907b0d27-6e36-4464-b51f-5333e7ac67da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810048149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3810048149
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.369805073
Short name T116
Test name
Test status
Simulation time 1501672545 ps
CPU time 5.45 seconds
Started Apr 28 02:09:11 PM PDT 24
Finished Apr 28 02:09:17 PM PDT 24
Peak memory 201096 kb
Host smart-4b622b91-9ed6-490b-8404-195a62828663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369805073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.369805073
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1053173896
Short name T126
Test name
Test status
Simulation time 110491584 ps
CPU time 1.01 seconds
Started Apr 28 02:09:09 PM PDT 24
Finished Apr 28 02:09:11 PM PDT 24
Peak memory 200824 kb
Host smart-0b29cb11-f9e7-4ece-a01b-b6ef3747d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053173896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1053173896
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1778941786
Short name T372
Test name
Test status
Simulation time 122405555 ps
CPU time 1.18 seconds
Started Apr 28 02:09:13 PM PDT 24
Finished Apr 28 02:09:14 PM PDT 24
Peak memory 201084 kb
Host smart-444ff3cf-3ca8-4f02-be30-a46811261788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778941786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1778941786
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3916569901
Short name T327
Test name
Test status
Simulation time 2939590559 ps
CPU time 12.38 seconds
Started Apr 28 02:09:09 PM PDT 24
Finished Apr 28 02:09:22 PM PDT 24
Peak memory 201228 kb
Host smart-3b1604af-ecfa-4c2b-ba8a-776bf96f3f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916569901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3916569901
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3719585
Short name T214
Test name
Test status
Simulation time 534860086 ps
CPU time 2.98 seconds
Started Apr 28 02:09:12 PM PDT 24
Finished Apr 28 02:09:16 PM PDT 24
Peak memory 200836 kb
Host smart-1728d01f-b068-4486-8b74-4c4aaabdb8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3719585
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.976974584
Short name T274
Test name
Test status
Simulation time 107491831 ps
CPU time 1.02 seconds
Started Apr 28 02:09:12 PM PDT 24
Finished Apr 28 02:09:14 PM PDT 24
Peak memory 200868 kb
Host smart-8b95c6f8-06b7-459d-95a7-dbd9d173a62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976974584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.976974584
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.23766229
Short name T242
Test name
Test status
Simulation time 84650467 ps
CPU time 0.83 seconds
Started Apr 28 02:09:21 PM PDT 24
Finished Apr 28 02:09:22 PM PDT 24
Peak memory 200712 kb
Host smart-3624c15f-32aa-4da5-b972-f13f96637e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23766229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.23766229
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1338793678
Short name T29
Test name
Test status
Simulation time 1235494500 ps
CPU time 5.48 seconds
Started Apr 28 02:09:24 PM PDT 24
Finished Apr 28 02:09:30 PM PDT 24
Peak memory 218672 kb
Host smart-d9bef19a-c387-4feb-ab84-b1ad22534bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338793678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1338793678
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2327130252
Short name T330
Test name
Test status
Simulation time 244118992 ps
CPU time 1.05 seconds
Started Apr 28 02:09:23 PM PDT 24
Finished Apr 28 02:09:25 PM PDT 24
Peak memory 218208 kb
Host smart-ac167d4e-6620-497d-9ebd-461f67ade38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327130252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2327130252
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2887255924
Short name T185
Test name
Test status
Simulation time 178574250 ps
CPU time 0.85 seconds
Started Apr 28 02:09:16 PM PDT 24
Finished Apr 28 02:09:17 PM PDT 24
Peak memory 200616 kb
Host smart-a93884ad-40fc-4c3b-87dd-f04d62916287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887255924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2887255924
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1770220740
Short name T145
Test name
Test status
Simulation time 1738755032 ps
CPU time 7.03 seconds
Started Apr 28 02:09:14 PM PDT 24
Finished Apr 28 02:09:21 PM PDT 24
Peak memory 201060 kb
Host smart-fed5f2be-a956-4378-8ff3-5ac06c23452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770220740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1770220740
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3199148609
Short name T133
Test name
Test status
Simulation time 107356851 ps
CPU time 1.05 seconds
Started Apr 28 02:09:20 PM PDT 24
Finished Apr 28 02:09:21 PM PDT 24
Peak memory 200884 kb
Host smart-d498f012-c2b7-48f3-ab90-23257d2bc524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199148609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3199148609
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.387722531
Short name T469
Test name
Test status
Simulation time 122286222 ps
CPU time 1.12 seconds
Started Apr 28 02:09:09 PM PDT 24
Finished Apr 28 02:09:10 PM PDT 24
Peak memory 201072 kb
Host smart-2165e2d7-99c8-44df-8d00-a06c2e84ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387722531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.387722531
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1665096394
Short name T233
Test name
Test status
Simulation time 4577769364 ps
CPU time 17.7 seconds
Started Apr 28 02:09:20 PM PDT 24
Finished Apr 28 02:09:38 PM PDT 24
Peak memory 201176 kb
Host smart-bb28e2c4-1add-483e-b13d-4eaa8feb016c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665096394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1665096394
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.470403658
Short name T459
Test name
Test status
Simulation time 263241022 ps
CPU time 1.86 seconds
Started Apr 28 02:09:14 PM PDT 24
Finished Apr 28 02:09:17 PM PDT 24
Peak memory 200884 kb
Host smart-c25f5af7-b996-4457-8e35-a06b81a4a904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470403658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.470403658
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1450749470
Short name T492
Test name
Test status
Simulation time 214375412 ps
CPU time 1.26 seconds
Started Apr 28 02:09:14 PM PDT 24
Finished Apr 28 02:09:16 PM PDT 24
Peak memory 200860 kb
Host smart-b75ad81a-cf25-46b7-8f91-6286a033089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450749470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1450749470
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3102780992
Short name T244
Test name
Test status
Simulation time 60192250 ps
CPU time 0.72 seconds
Started Apr 28 02:09:22 PM PDT 24
Finished Apr 28 02:09:23 PM PDT 24
Peak memory 200588 kb
Host smart-2d80b9a3-689a-4c52-85f5-6d43d518c882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102780992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3102780992
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.764213334
Short name T439
Test name
Test status
Simulation time 2353802241 ps
CPU time 7.96 seconds
Started Apr 28 02:09:25 PM PDT 24
Finished Apr 28 02:09:34 PM PDT 24
Peak memory 218436 kb
Host smart-4eb627b6-e964-43f1-b4d6-725c3c93bbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764213334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.764213334
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.4203676456
Short name T405
Test name
Test status
Simulation time 244450367 ps
CPU time 1.18 seconds
Started Apr 28 02:09:23 PM PDT 24
Finished Apr 28 02:09:25 PM PDT 24
Peak memory 218224 kb
Host smart-c0886d07-0014-4e90-9303-13ab96bed815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203676456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.4203676456
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2640244271
Short name T404
Test name
Test status
Simulation time 197240862 ps
CPU time 0.92 seconds
Started Apr 28 02:09:20 PM PDT 24
Finished Apr 28 02:09:21 PM PDT 24
Peak memory 200720 kb
Host smart-85bfb8fe-bf63-490d-a86e-ea72973e41cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640244271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2640244271
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.45571103
Short name T521
Test name
Test status
Simulation time 1757704704 ps
CPU time 6.72 seconds
Started Apr 28 02:09:20 PM PDT 24
Finished Apr 28 02:09:27 PM PDT 24
Peak memory 201092 kb
Host smart-ec895adc-1154-40be-aa12-89851cbc9ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45571103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.45571103
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3524896176
Short name T135
Test name
Test status
Simulation time 175281271 ps
CPU time 1.25 seconds
Started Apr 28 02:09:19 PM PDT 24
Finished Apr 28 02:09:20 PM PDT 24
Peak memory 200816 kb
Host smart-9d69105d-611a-4f55-94f9-8719d3d3e467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524896176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3524896176
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3691159310
Short name T187
Test name
Test status
Simulation time 262999020 ps
CPU time 1.62 seconds
Started Apr 28 02:09:18 PM PDT 24
Finished Apr 28 02:09:20 PM PDT 24
Peak memory 200984 kb
Host smart-e3d21e18-7cf2-4263-ac9c-1eea30a684f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691159310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3691159310
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3957642775
Short name T117
Test name
Test status
Simulation time 14214858678 ps
CPU time 52.15 seconds
Started Apr 28 02:09:23 PM PDT 24
Finished Apr 28 02:10:16 PM PDT 24
Peak memory 201212 kb
Host smart-d4f5da9b-71d0-4f6c-ac3d-6a6c39a0fbb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957642775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3957642775
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1877538054
Short name T348
Test name
Test status
Simulation time 351001403 ps
CPU time 2.2 seconds
Started Apr 28 02:09:23 PM PDT 24
Finished Apr 28 02:09:26 PM PDT 24
Peak memory 200820 kb
Host smart-60d84aa7-a46d-434d-947a-8a64554d99ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877538054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1877538054
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3606670891
Short name T474
Test name
Test status
Simulation time 271951350 ps
CPU time 1.39 seconds
Started Apr 28 02:09:24 PM PDT 24
Finished Apr 28 02:09:26 PM PDT 24
Peak memory 200796 kb
Host smart-c500e5db-f6c8-45e0-9213-363c78340b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606670891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3606670891
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3893259022
Short name T207
Test name
Test status
Simulation time 72523585 ps
CPU time 0.84 seconds
Started Apr 28 02:09:25 PM PDT 24
Finished Apr 28 02:09:27 PM PDT 24
Peak memory 200624 kb
Host smart-a63ce1d6-8d4f-46bd-98ea-d7568c6c0920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893259022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3893259022
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3799789577
Short name T31
Test name
Test status
Simulation time 2356298235 ps
CPU time 8.12 seconds
Started Apr 28 02:09:26 PM PDT 24
Finished Apr 28 02:09:35 PM PDT 24
Peak memory 218732 kb
Host smart-a599e7f4-2d47-4bfa-9c23-c626e2949604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799789577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3799789577
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2825634595
Short name T165
Test name
Test status
Simulation time 244323205 ps
CPU time 1.14 seconds
Started Apr 28 02:09:25 PM PDT 24
Finished Apr 28 02:09:27 PM PDT 24
Peak memory 218144 kb
Host smart-81c704f2-8768-49a1-8293-e7f66bdc93ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825634595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2825634595
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2001041195
Short name T18
Test name
Test status
Simulation time 148117841 ps
CPU time 0.87 seconds
Started Apr 28 02:09:19 PM PDT 24
Finished Apr 28 02:09:21 PM PDT 24
Peak memory 200672 kb
Host smart-37fb0375-54f3-4f9e-a7b9-6d0251de1933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001041195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2001041195
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.119578731
Short name T515
Test name
Test status
Simulation time 2086167552 ps
CPU time 8.15 seconds
Started Apr 28 02:09:19 PM PDT 24
Finished Apr 28 02:09:28 PM PDT 24
Peak memory 200968 kb
Host smart-6898181b-6d64-4f92-bb9d-a22c4d37c78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119578731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.119578731
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1212636111
Short name T272
Test name
Test status
Simulation time 151665632 ps
CPU time 1.09 seconds
Started Apr 28 02:09:25 PM PDT 24
Finished Apr 28 02:09:27 PM PDT 24
Peak memory 200856 kb
Host smart-3b07a8fd-9c6d-4906-9877-349bb07569f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212636111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1212636111
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1152174513
Short name T374
Test name
Test status
Simulation time 110358500 ps
CPU time 1.23 seconds
Started Apr 28 02:09:24 PM PDT 24
Finished Apr 28 02:09:26 PM PDT 24
Peak memory 201096 kb
Host smart-9e823cf0-42a2-4ea7-84d6-57ddb51a7b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152174513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1152174513
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2936845088
Short name T189
Test name
Test status
Simulation time 129613908 ps
CPU time 1.59 seconds
Started Apr 28 02:09:20 PM PDT 24
Finished Apr 28 02:09:22 PM PDT 24
Peak memory 200892 kb
Host smart-5ac19dd1-d27a-4e4b-8770-188adda3bc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936845088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2936845088
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.4073409552
Short name T123
Test name
Test status
Simulation time 196320422 ps
CPU time 1.2 seconds
Started Apr 28 02:09:25 PM PDT 24
Finished Apr 28 02:09:27 PM PDT 24
Peak memory 200796 kb
Host smart-803a01da-fc47-48ca-a0ac-68e1296aa247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073409552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.4073409552
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1351386381
Short name T312
Test name
Test status
Simulation time 93120262 ps
CPU time 0.82 seconds
Started Apr 28 02:09:23 PM PDT 24
Finished Apr 28 02:09:25 PM PDT 24
Peak memory 200676 kb
Host smart-9e5c4652-43ea-4b1d-bc34-e358f380e448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351386381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1351386381
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1318761266
Short name T49
Test name
Test status
Simulation time 1227831716 ps
CPU time 5.78 seconds
Started Apr 28 02:09:24 PM PDT 24
Finished Apr 28 02:09:31 PM PDT 24
Peak memory 222664 kb
Host smart-5a7c7e8e-3ee9-40ef-a01c-46672bb75854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318761266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1318761266
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.561274081
Short name T142
Test name
Test status
Simulation time 244823936 ps
CPU time 1.07 seconds
Started Apr 28 02:09:24 PM PDT 24
Finished Apr 28 02:09:26 PM PDT 24
Peak memory 218264 kb
Host smart-5303d6d7-4080-43f8-8f76-d5f90ae46ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561274081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.561274081
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3184893017
Short name T421
Test name
Test status
Simulation time 118734662 ps
CPU time 0.79 seconds
Started Apr 28 02:09:24 PM PDT 24
Finished Apr 28 02:09:26 PM PDT 24
Peak memory 200600 kb
Host smart-77f23b36-b57e-47c8-82c6-b6a370600b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184893017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3184893017
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1872902219
Short name T529
Test name
Test status
Simulation time 919698605 ps
CPU time 4.58 seconds
Started Apr 28 02:09:26 PM PDT 24
Finished Apr 28 02:09:31 PM PDT 24
Peak memory 201016 kb
Host smart-aa5fab75-2338-4cc9-93c0-618f1fed4e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872902219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1872902219
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2144136971
Short name T425
Test name
Test status
Simulation time 185574092 ps
CPU time 1.21 seconds
Started Apr 28 02:09:24 PM PDT 24
Finished Apr 28 02:09:27 PM PDT 24
Peak memory 200764 kb
Host smart-21affbcb-6714-4e6c-90f6-9857a8fa5f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144136971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2144136971
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1876828690
Short name T377
Test name
Test status
Simulation time 253858691 ps
CPU time 1.51 seconds
Started Apr 28 02:09:24 PM PDT 24
Finished Apr 28 02:09:27 PM PDT 24
Peak memory 201068 kb
Host smart-93950cad-f132-46b1-86e2-647d45cabcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876828690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1876828690
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.552495075
Short name T208
Test name
Test status
Simulation time 10461622923 ps
CPU time 36.21 seconds
Started Apr 28 02:09:29 PM PDT 24
Finished Apr 28 02:10:06 PM PDT 24
Peak memory 201176 kb
Host smart-3ccadadf-1e22-44bf-98cd-27bcf97bc206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552495075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.552495075
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2505632390
Short name T419
Test name
Test status
Simulation time 143938663 ps
CPU time 1.92 seconds
Started Apr 28 02:09:28 PM PDT 24
Finished Apr 28 02:09:30 PM PDT 24
Peak memory 200948 kb
Host smart-208b8d17-ff22-4d52-9bc1-d8bf3322e966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505632390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2505632390
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1595441095
Short name T121
Test name
Test status
Simulation time 287234005 ps
CPU time 1.59 seconds
Started Apr 28 02:09:29 PM PDT 24
Finished Apr 28 02:09:31 PM PDT 24
Peak memory 201056 kb
Host smart-461f11b7-2697-460e-a3b4-c50dc71be496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595441095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1595441095
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2733530211
Short name T232
Test name
Test status
Simulation time 60363244 ps
CPU time 0.75 seconds
Started Apr 28 02:09:29 PM PDT 24
Finished Apr 28 02:09:31 PM PDT 24
Peak memory 200708 kb
Host smart-e6c248bb-d930-40d1-84ac-038385bf0d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733530211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2733530211
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1293267551
Short name T486
Test name
Test status
Simulation time 1885592890 ps
CPU time 7.75 seconds
Started Apr 28 02:09:30 PM PDT 24
Finished Apr 28 02:09:39 PM PDT 24
Peak memory 218608 kb
Host smart-28dfe032-87cb-4d66-b851-8b1587ead905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293267551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1293267551
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2316531622
Short name T335
Test name
Test status
Simulation time 244205822 ps
CPU time 1.08 seconds
Started Apr 28 02:09:28 PM PDT 24
Finished Apr 28 02:09:30 PM PDT 24
Peak memory 218284 kb
Host smart-bc3926b7-7a1f-41b5-a9c8-6b539886afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316531622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2316531622
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1553962380
Short name T440
Test name
Test status
Simulation time 173107990 ps
CPU time 0.87 seconds
Started Apr 28 02:09:25 PM PDT 24
Finished Apr 28 02:09:27 PM PDT 24
Peak memory 200588 kb
Host smart-c9ca8cc1-b848-420c-b1b7-fdf78fee27e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553962380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1553962380
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3141074466
Short name T255
Test name
Test status
Simulation time 941909124 ps
CPU time 4.12 seconds
Started Apr 28 02:09:29 PM PDT 24
Finished Apr 28 02:09:33 PM PDT 24
Peak memory 201048 kb
Host smart-82440ff8-bff0-403c-a57d-6fef4846f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141074466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3141074466
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.292420177
Short name T9
Test name
Test status
Simulation time 143858257 ps
CPU time 1.27 seconds
Started Apr 28 02:09:25 PM PDT 24
Finished Apr 28 02:09:28 PM PDT 24
Peak memory 200900 kb
Host smart-ce0c69a3-30ba-4ba0-b025-0b1ae6d736d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292420177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.292420177
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2840867960
Short name T424
Test name
Test status
Simulation time 192364209 ps
CPU time 1.36 seconds
Started Apr 28 02:09:26 PM PDT 24
Finished Apr 28 02:09:29 PM PDT 24
Peak memory 201052 kb
Host smart-c7057962-7783-481d-8b34-446d90772099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840867960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2840867960
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.479914120
Short name T487
Test name
Test status
Simulation time 8606352819 ps
CPU time 30.63 seconds
Started Apr 28 02:09:30 PM PDT 24
Finished Apr 28 02:10:01 PM PDT 24
Peak memory 217492 kb
Host smart-e84ccb3e-9f29-4077-89dc-ed64ae7896c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479914120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.479914120
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3824753458
Short name T202
Test name
Test status
Simulation time 143865180 ps
CPU time 1.83 seconds
Started Apr 28 02:09:26 PM PDT 24
Finished Apr 28 02:09:28 PM PDT 24
Peak memory 200932 kb
Host smart-5dff119c-e489-4bcd-a02f-8c126b49b9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824753458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3824753458
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4102266925
Short name T446
Test name
Test status
Simulation time 96900482 ps
CPU time 0.92 seconds
Started Apr 28 02:09:25 PM PDT 24
Finished Apr 28 02:09:27 PM PDT 24
Peak memory 200904 kb
Host smart-c950f8ae-4f0e-4f37-b196-4d8e5eaf4d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102266925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4102266925
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.845221428
Short name T67
Test name
Test status
Simulation time 82153316 ps
CPU time 0.81 seconds
Started Apr 28 02:09:28 PM PDT 24
Finished Apr 28 02:09:30 PM PDT 24
Peak memory 200720 kb
Host smart-0664fecf-743e-4479-a6eb-096e9791e0fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845221428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.845221428
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2118678293
Short name T125
Test name
Test status
Simulation time 2378716473 ps
CPU time 8.13 seconds
Started Apr 28 02:09:28 PM PDT 24
Finished Apr 28 02:09:37 PM PDT 24
Peak memory 222068 kb
Host smart-f75d0fc4-9ccf-468b-a2a5-b942015f6c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118678293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2118678293
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3684883951
Short name T138
Test name
Test status
Simulation time 244161067 ps
CPU time 1.09 seconds
Started Apr 28 02:09:29 PM PDT 24
Finished Apr 28 02:09:30 PM PDT 24
Peak memory 218052 kb
Host smart-d10d471e-c3e2-4174-a851-4a15a02e00f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684883951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3684883951
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.198033458
Short name T473
Test name
Test status
Simulation time 98739192 ps
CPU time 0.78 seconds
Started Apr 28 02:09:30 PM PDT 24
Finished Apr 28 02:09:31 PM PDT 24
Peak memory 200700 kb
Host smart-8acd78fb-3b55-4125-afdb-11f08ed06b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198033458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.198033458
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3856260620
Short name T457
Test name
Test status
Simulation time 2055591493 ps
CPU time 7.17 seconds
Started Apr 28 02:09:29 PM PDT 24
Finished Apr 28 02:09:36 PM PDT 24
Peak memory 201084 kb
Host smart-b73bbc99-44cb-421f-a502-059a394a19fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856260620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3856260620
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1216118341
Short name T258
Test name
Test status
Simulation time 112203489 ps
CPU time 1.02 seconds
Started Apr 28 02:09:31 PM PDT 24
Finished Apr 28 02:09:32 PM PDT 24
Peak memory 200884 kb
Host smart-94495d4d-bb67-4799-b143-fe32fb491142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216118341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1216118341
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3490973174
Short name T477
Test name
Test status
Simulation time 125775353 ps
CPU time 1.13 seconds
Started Apr 28 02:09:28 PM PDT 24
Finished Apr 28 02:09:30 PM PDT 24
Peak memory 200956 kb
Host smart-8427913b-de3a-4947-9079-82ee5b82b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490973174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3490973174
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.4291146545
Short name T520
Test name
Test status
Simulation time 5667494620 ps
CPU time 25.8 seconds
Started Apr 28 02:09:29 PM PDT 24
Finished Apr 28 02:09:55 PM PDT 24
Peak memory 209404 kb
Host smart-1f6e7544-3ab7-42cc-bfa5-9781096d4c48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291146545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4291146545
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2239776528
Short name T198
Test name
Test status
Simulation time 531620190 ps
CPU time 2.9 seconds
Started Apr 28 02:09:30 PM PDT 24
Finished Apr 28 02:09:33 PM PDT 24
Peak memory 200912 kb
Host smart-36b2b812-ab48-436c-871f-6a36d3a2f3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239776528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2239776528
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2596570798
Short name T382
Test name
Test status
Simulation time 117565162 ps
CPU time 0.97 seconds
Started Apr 28 02:09:29 PM PDT 24
Finished Apr 28 02:09:31 PM PDT 24
Peak memory 200904 kb
Host smart-7ed6cfb4-097c-4eb5-b665-8d155e1a7830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596570798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2596570798
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4004717326
Short name T168
Test name
Test status
Simulation time 56740538 ps
CPU time 0.74 seconds
Started Apr 28 02:09:32 PM PDT 24
Finished Apr 28 02:09:33 PM PDT 24
Peak memory 200712 kb
Host smart-27b112df-9a60-41f1-8646-68e7e43d5d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004717326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4004717326
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2674285536
Short name T437
Test name
Test status
Simulation time 1901956626 ps
CPU time 6.89 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:46 PM PDT 24
Peak memory 218120 kb
Host smart-d9162dc1-77f4-453e-bd30-9f0598cd002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674285536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2674285536
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2660718861
Short name T157
Test name
Test status
Simulation time 244400663 ps
CPU time 1.05 seconds
Started Apr 28 02:09:35 PM PDT 24
Finished Apr 28 02:09:37 PM PDT 24
Peak memory 218012 kb
Host smart-390848ca-da93-45c2-bed6-c5595e8a444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660718861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2660718861
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3755022026
Short name T206
Test name
Test status
Simulation time 137239080 ps
CPU time 0.8 seconds
Started Apr 28 02:09:41 PM PDT 24
Finished Apr 28 02:09:42 PM PDT 24
Peak memory 200672 kb
Host smart-beccaf55-6079-4f7d-b04a-f91479c7a005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755022026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3755022026
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.823029669
Short name T385
Test name
Test status
Simulation time 1674161617 ps
CPU time 6.76 seconds
Started Apr 28 02:09:39 PM PDT 24
Finished Apr 28 02:09:47 PM PDT 24
Peak memory 200980 kb
Host smart-9b80d384-7b28-47ef-af80-9dc87b3b1307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823029669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.823029669
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.530171947
Short name T470
Test name
Test status
Simulation time 178700141 ps
CPU time 1.2 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:41 PM PDT 24
Peak memory 200788 kb
Host smart-e591eda1-0482-4ee6-8bf9-71f79dc1b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530171947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.530171947
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3807243751
Short name T139
Test name
Test status
Simulation time 132772938 ps
CPU time 1.2 seconds
Started Apr 28 02:09:30 PM PDT 24
Finished Apr 28 02:09:31 PM PDT 24
Peak memory 201012 kb
Host smart-9e85dfb3-b58a-4049-89d5-72fce4160e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807243751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3807243751
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.320463595
Short name T414
Test name
Test status
Simulation time 3810150868 ps
CPU time 12.62 seconds
Started Apr 28 02:09:36 PM PDT 24
Finished Apr 28 02:09:49 PM PDT 24
Peak memory 209440 kb
Host smart-3218bfbb-26a4-4c86-8b0b-6973d23d3752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320463595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.320463595
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1433779870
Short name T80
Test name
Test status
Simulation time 324739138 ps
CPU time 2.15 seconds
Started Apr 28 02:09:41 PM PDT 24
Finished Apr 28 02:09:44 PM PDT 24
Peak memory 200872 kb
Host smart-bf561298-f7e8-40a7-9b7b-eefdf8714370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433779870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1433779870
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1390214857
Short name T287
Test name
Test status
Simulation time 100198108 ps
CPU time 0.9 seconds
Started Apr 28 02:09:35 PM PDT 24
Finished Apr 28 02:09:36 PM PDT 24
Peak memory 200880 kb
Host smart-383be0da-80df-4b22-be6d-ecb666bb1e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390214857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1390214857
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2565349415
Short name T518
Test name
Test status
Simulation time 62689387 ps
CPU time 0.74 seconds
Started Apr 28 02:08:42 PM PDT 24
Finished Apr 28 02:08:43 PM PDT 24
Peak memory 200688 kb
Host smart-88ab6883-cfc3-4a00-bc8b-d38b0f6e64a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565349415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2565349415
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2552370208
Short name T40
Test name
Test status
Simulation time 1225794116 ps
CPU time 5.64 seconds
Started Apr 28 02:08:44 PM PDT 24
Finished Apr 28 02:08:50 PM PDT 24
Peak memory 222592 kb
Host smart-0e0fa303-dfd9-42a4-9d35-3e559b04e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552370208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2552370208
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2117876936
Short name T358
Test name
Test status
Simulation time 244939973 ps
CPU time 1.12 seconds
Started Apr 28 02:08:43 PM PDT 24
Finished Apr 28 02:08:45 PM PDT 24
Peak memory 218132 kb
Host smart-3c336a0e-5587-4f89-89a9-b86bbd7c584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117876936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2117876936
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2292696146
Short name T338
Test name
Test status
Simulation time 119319410 ps
CPU time 0.8 seconds
Started Apr 28 02:08:47 PM PDT 24
Finished Apr 28 02:08:48 PM PDT 24
Peak memory 200688 kb
Host smart-0fa05c46-e684-4c45-8c2d-d65294fd1e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292696146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2292696146
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2975760192
Short name T44
Test name
Test status
Simulation time 1942588379 ps
CPU time 7.75 seconds
Started Apr 28 02:08:46 PM PDT 24
Finished Apr 28 02:08:54 PM PDT 24
Peak memory 200980 kb
Host smart-74ca8dfc-e0b8-4d7d-98f5-69dc3f889e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975760192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2975760192
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1903080882
Short name T296
Test name
Test status
Simulation time 107068082 ps
CPU time 1 seconds
Started Apr 28 02:08:44 PM PDT 24
Finished Apr 28 02:08:45 PM PDT 24
Peak memory 200772 kb
Host smart-8d93d5fb-59c9-45ef-ae0d-8211fbe8b5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903080882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1903080882
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3536388261
Short name T256
Test name
Test status
Simulation time 111403553 ps
CPU time 1.15 seconds
Started Apr 28 02:08:43 PM PDT 24
Finished Apr 28 02:08:44 PM PDT 24
Peak memory 201092 kb
Host smart-5ba49b46-5ebe-4052-a88b-1262bd39b35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536388261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3536388261
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1551786681
Short name T167
Test name
Test status
Simulation time 4637603597 ps
CPU time 16.46 seconds
Started Apr 28 02:08:43 PM PDT 24
Finished Apr 28 02:08:59 PM PDT 24
Peak memory 201240 kb
Host smart-a45c173d-86f6-42fe-8bfa-78e52219db7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551786681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1551786681
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.913426115
Short name T211
Test name
Test status
Simulation time 481567701 ps
CPU time 2.46 seconds
Started Apr 28 02:08:44 PM PDT 24
Finished Apr 28 02:08:47 PM PDT 24
Peak memory 200828 kb
Host smart-a9479cb8-dad9-4388-8270-72e6703e0fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913426115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.913426115
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.4179916127
Short name T346
Test name
Test status
Simulation time 174082026 ps
CPU time 1.21 seconds
Started Apr 28 02:08:44 PM PDT 24
Finished Apr 28 02:08:46 PM PDT 24
Peak memory 200892 kb
Host smart-89864d4c-e982-4130-8280-64896b116b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179916127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4179916127
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1221158364
Short name T220
Test name
Test status
Simulation time 68648207 ps
CPU time 0.79 seconds
Started Apr 28 02:09:36 PM PDT 24
Finished Apr 28 02:09:37 PM PDT 24
Peak memory 200708 kb
Host smart-74f5df63-a6a8-40f2-a5bd-f18c06ee2261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221158364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1221158364
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2952681014
Short name T302
Test name
Test status
Simulation time 2355294544 ps
CPU time 7.81 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:47 PM PDT 24
Peak memory 218756 kb
Host smart-70fec06c-ecb8-4302-a2b8-d3e819ef9caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952681014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2952681014
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2884698391
Short name T140
Test name
Test status
Simulation time 245287364 ps
CPU time 1.07 seconds
Started Apr 28 02:09:36 PM PDT 24
Finished Apr 28 02:09:38 PM PDT 24
Peak memory 218228 kb
Host smart-a334e246-75d2-4604-9a14-103f7f2a54e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884698391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2884698391
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.994820900
Short name T460
Test name
Test status
Simulation time 171655515 ps
CPU time 0.85 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:40 PM PDT 24
Peak memory 200700 kb
Host smart-b453db07-6d8c-4900-a6d4-3c5900466a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994820900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.994820900
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2185408850
Short name T418
Test name
Test status
Simulation time 1514498429 ps
CPU time 5.71 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:45 PM PDT 24
Peak memory 201100 kb
Host smart-3cf8ab51-18d4-4378-94fd-70a2b04ff426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185408850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2185408850
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.648528370
Short name T259
Test name
Test status
Simulation time 114452074 ps
CPU time 1.01 seconds
Started Apr 28 02:09:37 PM PDT 24
Finished Apr 28 02:09:39 PM PDT 24
Peak memory 200912 kb
Host smart-61185dbe-8152-409c-8bc5-707397652012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648528370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.648528370
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2302770252
Short name T541
Test name
Test status
Simulation time 221290239 ps
CPU time 1.44 seconds
Started Apr 28 02:09:36 PM PDT 24
Finished Apr 28 02:09:38 PM PDT 24
Peak memory 201080 kb
Host smart-33922708-e0a5-4519-b5fc-d6b8a32ade5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302770252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2302770252
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3913627800
Short name T94
Test name
Test status
Simulation time 16320656324 ps
CPU time 51.71 seconds
Started Apr 28 02:09:39 PM PDT 24
Finished Apr 28 02:10:32 PM PDT 24
Peak memory 209376 kb
Host smart-4874c931-10f5-470d-a426-0cdd9ddeaa0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913627800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3913627800
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2204612853
Short name T213
Test name
Test status
Simulation time 368036725 ps
CPU time 2.26 seconds
Started Apr 28 02:09:36 PM PDT 24
Finished Apr 28 02:09:39 PM PDT 24
Peak memory 200900 kb
Host smart-b1e6761d-b488-4bdc-aaba-3528ec467e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204612853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2204612853
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2918814685
Short name T6
Test name
Test status
Simulation time 213073786 ps
CPU time 1.27 seconds
Started Apr 28 02:09:35 PM PDT 24
Finished Apr 28 02:09:37 PM PDT 24
Peak memory 200880 kb
Host smart-18c70cca-68df-4f19-b624-6473fd9da0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918814685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2918814685
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3008011461
Short name T221
Test name
Test status
Simulation time 68409469 ps
CPU time 0.83 seconds
Started Apr 28 02:09:40 PM PDT 24
Finished Apr 28 02:09:42 PM PDT 24
Peak memory 200692 kb
Host smart-c94cd38e-6142-4d25-b7a7-207c2c0a8d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008011461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3008011461
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2326138174
Short name T409
Test name
Test status
Simulation time 1218003268 ps
CPU time 5.52 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:45 PM PDT 24
Peak memory 218652 kb
Host smart-e7ed2f95-8612-4087-bfc5-1b09ae373359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326138174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2326138174
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2604584076
Short name T500
Test name
Test status
Simulation time 244208845 ps
CPU time 1.11 seconds
Started Apr 28 02:09:42 PM PDT 24
Finished Apr 28 02:09:43 PM PDT 24
Peak memory 218272 kb
Host smart-4251dae6-46eb-48ab-8246-b2484cb3bbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604584076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2604584076
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.4082897699
Short name T205
Test name
Test status
Simulation time 221412001 ps
CPU time 0.97 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:40 PM PDT 24
Peak memory 200700 kb
Host smart-76d226a8-9a41-440d-af78-382a46afe592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082897699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.4082897699
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2107743253
Short name T243
Test name
Test status
Simulation time 1827834858 ps
CPU time 6.24 seconds
Started Apr 28 02:09:35 PM PDT 24
Finished Apr 28 02:09:42 PM PDT 24
Peak memory 201028 kb
Host smart-0097528e-21eb-4bda-8b6b-81054d7d619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107743253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2107743253
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.419130562
Short name T183
Test name
Test status
Simulation time 172565612 ps
CPU time 1.27 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:40 PM PDT 24
Peak memory 200864 kb
Host smart-b2f5a678-3411-4aeb-bb92-2cee9f6c8280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419130562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.419130562
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3766998857
Short name T476
Test name
Test status
Simulation time 118983770 ps
CPU time 1.13 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:40 PM PDT 24
Peak memory 201096 kb
Host smart-57b50b3e-4432-4730-8af0-19d12579beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766998857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3766998857
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1588239314
Short name T282
Test name
Test status
Simulation time 17321623855 ps
CPU time 60.34 seconds
Started Apr 28 02:09:40 PM PDT 24
Finished Apr 28 02:10:41 PM PDT 24
Peak memory 209284 kb
Host smart-d5a5f20c-3ce9-45e3-af16-d337284584e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588239314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1588239314
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.648551602
Short name T72
Test name
Test status
Simulation time 298373962 ps
CPU time 1.97 seconds
Started Apr 28 02:09:37 PM PDT 24
Finished Apr 28 02:09:40 PM PDT 24
Peak memory 209284 kb
Host smart-f5d3dea7-bb7d-4011-b54e-685e6b54730f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648551602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.648551602
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1943254785
Short name T380
Test name
Test status
Simulation time 137191813 ps
CPU time 1.2 seconds
Started Apr 28 02:09:36 PM PDT 24
Finished Apr 28 02:09:38 PM PDT 24
Peak memory 200872 kb
Host smart-051c899f-30a0-4d93-99d2-ca4691310d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943254785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1943254785
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1812874836
Short name T284
Test name
Test status
Simulation time 53730274 ps
CPU time 0.72 seconds
Started Apr 28 02:09:41 PM PDT 24
Finished Apr 28 02:09:43 PM PDT 24
Peak memory 200712 kb
Host smart-100ae4a0-6bb2-4730-8b77-9d8f156cb797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812874836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1812874836
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1155050780
Short name T28
Test name
Test status
Simulation time 1229341549 ps
CPU time 5.55 seconds
Started Apr 28 02:09:41 PM PDT 24
Finished Apr 28 02:09:48 PM PDT 24
Peak memory 222676 kb
Host smart-54810723-8590-448c-8de7-9ae550219e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155050780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1155050780
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.474325869
Short name T226
Test name
Test status
Simulation time 243700915 ps
CPU time 1.12 seconds
Started Apr 28 02:09:41 PM PDT 24
Finished Apr 28 02:09:42 PM PDT 24
Peak memory 218008 kb
Host smart-6e520a77-229f-41e4-adf6-768f7d423a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474325869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.474325869
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1100451332
Short name T288
Test name
Test status
Simulation time 87989343 ps
CPU time 0.73 seconds
Started Apr 28 02:09:37 PM PDT 24
Finished Apr 28 02:09:38 PM PDT 24
Peak memory 200716 kb
Host smart-a6aa144b-06af-44fd-bd57-e8436af4f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100451332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1100451332
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.507279623
Short name T158
Test name
Test status
Simulation time 691499330 ps
CPU time 3.44 seconds
Started Apr 28 02:09:41 PM PDT 24
Finished Apr 28 02:09:46 PM PDT 24
Peak memory 201096 kb
Host smart-3003507b-f679-456a-9b28-7d1b65aa7111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507279623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.507279623
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4125050740
Short name T163
Test name
Test status
Simulation time 102359719 ps
CPU time 0.95 seconds
Started Apr 28 02:09:41 PM PDT 24
Finished Apr 28 02:09:42 PM PDT 24
Peak memory 200888 kb
Host smart-43c8c33c-6e9d-444f-98d9-bdb9516ab14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125050740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4125050740
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1975955365
Short name T499
Test name
Test status
Simulation time 249956552 ps
CPU time 1.49 seconds
Started Apr 28 02:09:39 PM PDT 24
Finished Apr 28 02:09:41 PM PDT 24
Peak memory 201072 kb
Host smart-b3188746-4e54-48d1-99ba-da48c5898f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975955365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1975955365
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1455336292
Short name T161
Test name
Test status
Simulation time 5190913470 ps
CPU time 18.73 seconds
Started Apr 28 02:09:43 PM PDT 24
Finished Apr 28 02:10:02 PM PDT 24
Peak memory 209400 kb
Host smart-5468efe4-2fdb-4885-bdf7-a8e2c2848733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455336292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1455336292
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.570206125
Short name T516
Test name
Test status
Simulation time 333957613 ps
CPU time 2.21 seconds
Started Apr 28 02:09:40 PM PDT 24
Finished Apr 28 02:09:43 PM PDT 24
Peak memory 200860 kb
Host smart-c1eaa675-662c-425a-aab4-3fd6b1ae97d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570206125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.570206125
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1837898964
Short name T248
Test name
Test status
Simulation time 113956377 ps
CPU time 1 seconds
Started Apr 28 02:09:42 PM PDT 24
Finished Apr 28 02:09:43 PM PDT 24
Peak memory 200876 kb
Host smart-42628560-b257-4666-ab48-43ce5a9bec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837898964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1837898964
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1306708440
Short name T66
Test name
Test status
Simulation time 79274478 ps
CPU time 0.82 seconds
Started Apr 28 02:09:49 PM PDT 24
Finished Apr 28 02:09:50 PM PDT 24
Peak memory 200712 kb
Host smart-eaefa71e-ec64-4f71-bdd4-c4ab3e36cedb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306708440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1306708440
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2362936620
Short name T42
Test name
Test status
Simulation time 2359546584 ps
CPU time 7.78 seconds
Started Apr 28 02:09:43 PM PDT 24
Finished Apr 28 02:09:51 PM PDT 24
Peak memory 218656 kb
Host smart-9107065f-45d4-4885-ba3e-04f6f95a2de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362936620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2362936620
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1030397081
Short name T54
Test name
Test status
Simulation time 244414683 ps
CPU time 1.03 seconds
Started Apr 28 02:09:48 PM PDT 24
Finished Apr 28 02:09:50 PM PDT 24
Peak memory 218284 kb
Host smart-700d2660-a650-41ec-9762-cda24703bcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030397081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1030397081
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2934593679
Short name T490
Test name
Test status
Simulation time 109163519 ps
CPU time 0.79 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:41 PM PDT 24
Peak memory 200644 kb
Host smart-5777b798-89cf-40d5-a4fa-5971e804f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934593679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2934593679
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3406234449
Short name T413
Test name
Test status
Simulation time 1430536794 ps
CPU time 5.07 seconds
Started Apr 28 02:09:38 PM PDT 24
Finished Apr 28 02:09:45 PM PDT 24
Peak memory 201104 kb
Host smart-94399813-9938-4c0e-990d-3b34808de116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406234449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3406234449
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.4180144757
Short name T299
Test name
Test status
Simulation time 111574232 ps
CPU time 1 seconds
Started Apr 28 02:09:46 PM PDT 24
Finished Apr 28 02:09:48 PM PDT 24
Peak memory 200856 kb
Host smart-2cc2120c-17ba-4fd5-919d-43f521e45ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180144757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.4180144757
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2730142075
Short name T387
Test name
Test status
Simulation time 129690137 ps
CPU time 1.21 seconds
Started Apr 28 02:09:42 PM PDT 24
Finished Apr 28 02:09:44 PM PDT 24
Peak memory 201072 kb
Host smart-4346f649-eefb-44c4-9cc7-8fadc53ec117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730142075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2730142075
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3380659100
Short name T307
Test name
Test status
Simulation time 9777781780 ps
CPU time 34.78 seconds
Started Apr 28 02:09:42 PM PDT 24
Finished Apr 28 02:10:18 PM PDT 24
Peak memory 209924 kb
Host smart-80f18ad6-8aaf-4706-8de6-a09dd50ec860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380659100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3380659100
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3515523855
Short name T407
Test name
Test status
Simulation time 125246026 ps
CPU time 1.51 seconds
Started Apr 28 02:09:48 PM PDT 24
Finished Apr 28 02:09:50 PM PDT 24
Peak memory 200876 kb
Host smart-267abe51-f140-4ccd-befc-6ede5e8d0beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515523855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3515523855
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.287172690
Short name T378
Test name
Test status
Simulation time 139907258 ps
CPU time 1.11 seconds
Started Apr 28 02:09:39 PM PDT 24
Finished Apr 28 02:09:41 PM PDT 24
Peak memory 200908 kb
Host smart-d939ad22-b5e9-4865-b376-a941ba5bfe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287172690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.287172690
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2333814517
Short name T334
Test name
Test status
Simulation time 79402803 ps
CPU time 0.82 seconds
Started Apr 28 02:09:45 PM PDT 24
Finished Apr 28 02:09:46 PM PDT 24
Peak memory 200704 kb
Host smart-2259bb38-2d19-476a-bf0d-8889a58cdc40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333814517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2333814517
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.569487486
Short name T27
Test name
Test status
Simulation time 245039538 ps
CPU time 1.01 seconds
Started Apr 28 02:09:45 PM PDT 24
Finished Apr 28 02:09:46 PM PDT 24
Peak memory 218136 kb
Host smart-af9a0d02-25e5-449a-96ac-99b457db75fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569487486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.569487486
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2484336602
Short name T184
Test name
Test status
Simulation time 196622884 ps
CPU time 0.94 seconds
Started Apr 28 02:09:44 PM PDT 24
Finished Apr 28 02:09:45 PM PDT 24
Peak memory 200700 kb
Host smart-9f301139-3a03-48d2-b705-f4d50338121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484336602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2484336602
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.143971510
Short name T361
Test name
Test status
Simulation time 1201039080 ps
CPU time 4.83 seconds
Started Apr 28 02:09:43 PM PDT 24
Finished Apr 28 02:09:48 PM PDT 24
Peak memory 200984 kb
Host smart-6a72fef9-5794-485a-a693-817d6fd6bf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143971510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.143971510
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1120731972
Short name T524
Test name
Test status
Simulation time 106284398 ps
CPU time 1 seconds
Started Apr 28 02:09:44 PM PDT 24
Finished Apr 28 02:09:45 PM PDT 24
Peak memory 200876 kb
Host smart-7e12a988-4534-4bf0-9918-738b6cf37e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120731972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1120731972
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2865220895
Short name T464
Test name
Test status
Simulation time 252123674 ps
CPU time 1.57 seconds
Started Apr 28 02:09:48 PM PDT 24
Finished Apr 28 02:09:50 PM PDT 24
Peak memory 201088 kb
Host smart-a3ab8b03-d0e5-4d2e-9ff8-e49bc0522b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865220895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2865220895
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.4029514582
Short name T190
Test name
Test status
Simulation time 7568374209 ps
CPU time 24.59 seconds
Started Apr 28 02:09:45 PM PDT 24
Finished Apr 28 02:10:10 PM PDT 24
Peak memory 201204 kb
Host smart-fe7a44b9-e63c-4cfb-bb31-2b6e78e8c407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029514582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4029514582
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1736554972
Short name T390
Test name
Test status
Simulation time 419626702 ps
CPU time 2.47 seconds
Started Apr 28 02:09:47 PM PDT 24
Finished Apr 28 02:09:50 PM PDT 24
Peak memory 209028 kb
Host smart-3a54b09e-966a-4b13-96cd-8d93bd4feae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736554972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1736554972
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1532629761
Short name T333
Test name
Test status
Simulation time 251406127 ps
CPU time 1.34 seconds
Started Apr 28 02:09:45 PM PDT 24
Finished Apr 28 02:09:46 PM PDT 24
Peak memory 200828 kb
Host smart-8b2b6938-d7d3-4acb-bdb3-f182a3213424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532629761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1532629761
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.485273460
Short name T528
Test name
Test status
Simulation time 75775358 ps
CPU time 0.79 seconds
Started Apr 28 02:09:49 PM PDT 24
Finished Apr 28 02:09:51 PM PDT 24
Peak memory 200736 kb
Host smart-7fce0da7-632c-4c0d-9a9f-87c62ff5771a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485273460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.485273460
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3020289391
Short name T39
Test name
Test status
Simulation time 2353626900 ps
CPU time 7.98 seconds
Started Apr 28 02:09:55 PM PDT 24
Finished Apr 28 02:10:03 PM PDT 24
Peak memory 217940 kb
Host smart-f3ae4344-92cb-4119-bfc9-f7f901de480a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020289391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3020289391
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4104055801
Short name T332
Test name
Test status
Simulation time 244000316 ps
CPU time 1.07 seconds
Started Apr 28 02:09:52 PM PDT 24
Finished Apr 28 02:09:53 PM PDT 24
Peak memory 218096 kb
Host smart-47b7b5b2-9690-45b2-941a-272dcea932fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104055801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4104055801
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.4155848303
Short name T326
Test name
Test status
Simulation time 232448833 ps
CPU time 0.96 seconds
Started Apr 28 02:09:46 PM PDT 24
Finished Apr 28 02:09:47 PM PDT 24
Peak memory 200708 kb
Host smart-ba29ec13-afca-4169-826e-ce2d88c8b540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155848303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.4155848303
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3632858272
Short name T532
Test name
Test status
Simulation time 919506106 ps
CPU time 4.24 seconds
Started Apr 28 02:09:44 PM PDT 24
Finished Apr 28 02:09:48 PM PDT 24
Peak memory 201100 kb
Host smart-5f262345-fec0-432f-9a90-6395d3d7c9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632858272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3632858272
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3915267900
Short name T132
Test name
Test status
Simulation time 173943688 ps
CPU time 1.18 seconds
Started Apr 28 02:09:48 PM PDT 24
Finished Apr 28 02:09:50 PM PDT 24
Peak memory 200904 kb
Host smart-6f5447ad-6a27-4020-9719-68566438038f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915267900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3915267900
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3163214336
Short name T480
Test name
Test status
Simulation time 114697073 ps
CPU time 1.22 seconds
Started Apr 28 02:09:45 PM PDT 24
Finished Apr 28 02:09:46 PM PDT 24
Peak memory 201056 kb
Host smart-befc27e9-8329-4ed1-8f68-9defd4c42dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163214336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3163214336
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1653953870
Short name T510
Test name
Test status
Simulation time 5364368670 ps
CPU time 23.35 seconds
Started Apr 28 02:09:49 PM PDT 24
Finished Apr 28 02:10:13 PM PDT 24
Peak memory 209428 kb
Host smart-d1aac304-5274-4197-b5f4-0bfcd46229d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653953870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1653953870
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3255025892
Short name T466
Test name
Test status
Simulation time 525321426 ps
CPU time 2.77 seconds
Started Apr 28 02:09:47 PM PDT 24
Finished Apr 28 02:09:50 PM PDT 24
Peak memory 200832 kb
Host smart-4d084d70-ca7a-4fe7-aa24-6be0f92d4e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255025892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3255025892
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3510544859
Short name T513
Test name
Test status
Simulation time 106153613 ps
CPU time 0.95 seconds
Started Apr 28 02:09:48 PM PDT 24
Finished Apr 28 02:09:49 PM PDT 24
Peak memory 200868 kb
Host smart-90ddfe4b-3d5d-4723-aa8f-32911ce227fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510544859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3510544859
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.827196189
Short name T265
Test name
Test status
Simulation time 80121743 ps
CPU time 0.77 seconds
Started Apr 28 02:09:50 PM PDT 24
Finished Apr 28 02:09:51 PM PDT 24
Peak memory 200584 kb
Host smart-16bc1caa-bc46-4fc9-afde-55482d3e8a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827196189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.827196189
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.491555447
Short name T420
Test name
Test status
Simulation time 1224002297 ps
CPU time 5.81 seconds
Started Apr 28 02:09:49 PM PDT 24
Finished Apr 28 02:09:56 PM PDT 24
Peak memory 218096 kb
Host smart-f5b8b25a-fc47-40e3-b546-07ebba71264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491555447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.491555447
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.699447204
Short name T403
Test name
Test status
Simulation time 244289894 ps
CPU time 1.05 seconds
Started Apr 28 02:09:49 PM PDT 24
Finished Apr 28 02:09:51 PM PDT 24
Peak memory 218092 kb
Host smart-e7d47a51-9ffc-47af-a3e8-c26cbfde4611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699447204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.699447204
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1635720092
Short name T16
Test name
Test status
Simulation time 127112304 ps
CPU time 0.78 seconds
Started Apr 28 02:09:48 PM PDT 24
Finished Apr 28 02:09:49 PM PDT 24
Peak memory 200672 kb
Host smart-15f8aa13-7bd5-49b8-bafb-370ec170133f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635720092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1635720092
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3247583561
Short name T146
Test name
Test status
Simulation time 1094044213 ps
CPU time 4.56 seconds
Started Apr 28 02:09:51 PM PDT 24
Finished Apr 28 02:09:56 PM PDT 24
Peak memory 201032 kb
Host smart-c68f67b2-fcd6-477a-99b2-36c58c497bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247583561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3247583561
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1438373291
Short name T309
Test name
Test status
Simulation time 176285347 ps
CPU time 1.3 seconds
Started Apr 28 02:09:48 PM PDT 24
Finished Apr 28 02:09:50 PM PDT 24
Peak memory 200880 kb
Host smart-24c64503-63a3-4411-9c39-dc6de556a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438373291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1438373291
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3568471242
Short name T253
Test name
Test status
Simulation time 190491192 ps
CPU time 1.26 seconds
Started Apr 28 02:09:48 PM PDT 24
Finished Apr 28 02:09:50 PM PDT 24
Peak memory 200976 kb
Host smart-e5a259a0-1002-4c18-a089-b12dfa725155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568471242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3568471242
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2277824162
Short name T216
Test name
Test status
Simulation time 2645833690 ps
CPU time 12.92 seconds
Started Apr 28 02:09:48 PM PDT 24
Finished Apr 28 02:10:01 PM PDT 24
Peak memory 210904 kb
Host smart-c599d97c-4724-46b8-ab77-1563150e4947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277824162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2277824162
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2431972436
Short name T257
Test name
Test status
Simulation time 515493538 ps
CPU time 2.56 seconds
Started Apr 28 02:09:49 PM PDT 24
Finished Apr 28 02:09:52 PM PDT 24
Peak memory 200880 kb
Host smart-7d10007a-353d-435c-898b-159324054068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431972436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2431972436
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2296514923
Short name T542
Test name
Test status
Simulation time 132027014 ps
CPU time 1.08 seconds
Started Apr 28 02:09:52 PM PDT 24
Finished Apr 28 02:09:53 PM PDT 24
Peak memory 200732 kb
Host smart-9e643160-b22c-41de-82bf-43bf4e64cf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296514923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2296514923
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1783904727
Short name T329
Test name
Test status
Simulation time 85165514 ps
CPU time 0.79 seconds
Started Apr 28 02:09:56 PM PDT 24
Finished Apr 28 02:09:58 PM PDT 24
Peak memory 200676 kb
Host smart-c9d98e86-bfc6-4722-87bd-ea9159accc5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783904727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1783904727
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1278573014
Short name T273
Test name
Test status
Simulation time 1883836465 ps
CPU time 7.72 seconds
Started Apr 28 02:09:57 PM PDT 24
Finished Apr 28 02:10:05 PM PDT 24
Peak memory 230024 kb
Host smart-196472f5-c5ff-4c5e-8fe9-59875d385d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278573014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1278573014
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3849699143
Short name T352
Test name
Test status
Simulation time 243733902 ps
CPU time 1.01 seconds
Started Apr 28 02:09:53 PM PDT 24
Finished Apr 28 02:09:55 PM PDT 24
Peak memory 218112 kb
Host smart-1cffd29e-42b7-459f-b33b-b072c445f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849699143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3849699143
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2397907829
Short name T523
Test name
Test status
Simulation time 157537253 ps
CPU time 0.89 seconds
Started Apr 28 02:09:50 PM PDT 24
Finished Apr 28 02:09:51 PM PDT 24
Peak memory 200616 kb
Host smart-3e0ac423-f58a-42c0-a0ad-a8ddd0a8e522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397907829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2397907829
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2838852645
Short name T365
Test name
Test status
Simulation time 1735467437 ps
CPU time 6.27 seconds
Started Apr 28 02:09:54 PM PDT 24
Finished Apr 28 02:10:00 PM PDT 24
Peak memory 201020 kb
Host smart-30745026-a827-426e-8f0f-13eb4aea2e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838852645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2838852645
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2470293719
Short name T398
Test name
Test status
Simulation time 145401438 ps
CPU time 1.16 seconds
Started Apr 28 02:09:53 PM PDT 24
Finished Apr 28 02:09:54 PM PDT 24
Peak memory 200892 kb
Host smart-cf10e31c-a98a-4a75-85e9-ba88597cb654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470293719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2470293719
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3295744383
Short name T182
Test name
Test status
Simulation time 214697853 ps
CPU time 1.38 seconds
Started Apr 28 02:09:49 PM PDT 24
Finished Apr 28 02:09:51 PM PDT 24
Peak memory 201088 kb
Host smart-ea58a05e-4c1e-469f-a97e-fb530a189e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295744383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3295744383
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1189057095
Short name T506
Test name
Test status
Simulation time 135814521 ps
CPU time 0.93 seconds
Started Apr 28 02:09:53 PM PDT 24
Finished Apr 28 02:09:54 PM PDT 24
Peak memory 200676 kb
Host smart-a974b528-83be-49e5-a090-9498a0e08596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189057095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1189057095
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3102575317
Short name T356
Test name
Test status
Simulation time 446406677 ps
CPU time 2.37 seconds
Started Apr 28 02:09:54 PM PDT 24
Finished Apr 28 02:09:57 PM PDT 24
Peak memory 200888 kb
Host smart-a07e76e2-f424-4e11-9d2e-c8763b2ebc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102575317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3102575317
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2680396174
Short name T275
Test name
Test status
Simulation time 286990674 ps
CPU time 1.52 seconds
Started Apr 28 02:09:55 PM PDT 24
Finished Apr 28 02:09:57 PM PDT 24
Peak memory 200876 kb
Host smart-466c8a22-838b-4829-82f6-1241998e3c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680396174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2680396174
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4292881502
Short name T169
Test name
Test status
Simulation time 72064796 ps
CPU time 0.79 seconds
Started Apr 28 02:09:59 PM PDT 24
Finished Apr 28 02:10:01 PM PDT 24
Peak memory 200632 kb
Host smart-e8a2ebc1-b41b-4c86-bcab-50fdd598435c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292881502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4292881502
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3070088243
Short name T32
Test name
Test status
Simulation time 1226880660 ps
CPU time 5.76 seconds
Started Apr 28 02:10:02 PM PDT 24
Finished Apr 28 02:10:08 PM PDT 24
Peak memory 222576 kb
Host smart-43576b08-aed0-41a6-a98f-86d1f7bbe1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070088243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3070088243
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3306662085
Short name T488
Test name
Test status
Simulation time 243239864 ps
CPU time 1.08 seconds
Started Apr 28 02:10:01 PM PDT 24
Finished Apr 28 02:10:02 PM PDT 24
Peak memory 218036 kb
Host smart-55f93515-2387-4d51-bf70-b311674a0b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306662085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3306662085
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3651951126
Short name T383
Test name
Test status
Simulation time 87581415 ps
CPU time 0.73 seconds
Started Apr 28 02:09:53 PM PDT 24
Finished Apr 28 02:09:54 PM PDT 24
Peak memory 200576 kb
Host smart-42bb4484-05e3-42d1-bb1b-c5ba766d7f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651951126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3651951126
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3494335842
Short name T428
Test name
Test status
Simulation time 717996546 ps
CPU time 3.56 seconds
Started Apr 28 02:09:53 PM PDT 24
Finished Apr 28 02:09:58 PM PDT 24
Peak memory 200988 kb
Host smart-0a91e80c-a82a-4f6f-ace9-bcfb745703ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494335842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3494335842
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.422872535
Short name T71
Test name
Test status
Simulation time 187855925 ps
CPU time 1.19 seconds
Started Apr 28 02:09:59 PM PDT 24
Finished Apr 28 02:10:01 PM PDT 24
Peak memory 200872 kb
Host smart-392bb9a7-84ea-4504-a422-c2f2eab4e684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422872535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.422872535
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.151254894
Short name T179
Test name
Test status
Simulation time 263612713 ps
CPU time 1.45 seconds
Started Apr 28 02:09:56 PM PDT 24
Finished Apr 28 02:09:58 PM PDT 24
Peak memory 201088 kb
Host smart-c267fecf-18fa-45b2-ae09-d31327c454a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151254894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.151254894
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1163874762
Short name T286
Test name
Test status
Simulation time 106569238 ps
CPU time 1.07 seconds
Started Apr 28 02:10:00 PM PDT 24
Finished Apr 28 02:10:02 PM PDT 24
Peak memory 200704 kb
Host smart-9bdab3d3-f39f-4ba2-b399-46c8afafb37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163874762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1163874762
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1369460936
Short name T26
Test name
Test status
Simulation time 122159166 ps
CPU time 1.44 seconds
Started Apr 28 02:09:59 PM PDT 24
Finished Apr 28 02:10:00 PM PDT 24
Peak memory 200848 kb
Host smart-1dce5d37-6261-4fa1-9b6f-b634835b8577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369460936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1369460936
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1580844206
Short name T514
Test name
Test status
Simulation time 141655759 ps
CPU time 1.11 seconds
Started Apr 28 02:09:56 PM PDT 24
Finished Apr 28 02:09:57 PM PDT 24
Peak memory 200860 kb
Host smart-133de42f-312c-47d2-867b-7d7c925ed871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580844206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1580844206
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1294143109
Short name T283
Test name
Test status
Simulation time 57575283 ps
CPU time 0.75 seconds
Started Apr 28 02:10:00 PM PDT 24
Finished Apr 28 02:10:01 PM PDT 24
Peak memory 200656 kb
Host smart-465041d3-39b5-4507-82f4-428225cf7d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294143109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1294143109
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.601428518
Short name T341
Test name
Test status
Simulation time 1896591571 ps
CPU time 7.19 seconds
Started Apr 28 02:10:00 PM PDT 24
Finished Apr 28 02:10:08 PM PDT 24
Peak memory 218604 kb
Host smart-f3b4bf8b-844c-4012-bdef-8bfcfbc6aa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601428518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.601428518
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3657658040
Short name T3
Test name
Test status
Simulation time 244283178 ps
CPU time 1.09 seconds
Started Apr 28 02:10:01 PM PDT 24
Finished Apr 28 02:10:03 PM PDT 24
Peak memory 218220 kb
Host smart-b7a6f5b7-c7e0-489e-9133-af99b6399e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657658040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3657658040
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.726456332
Short name T434
Test name
Test status
Simulation time 218156966 ps
CPU time 0.94 seconds
Started Apr 28 02:09:58 PM PDT 24
Finished Apr 28 02:10:00 PM PDT 24
Peak memory 200648 kb
Host smart-061244fe-91c5-44ad-8088-76abed9f6a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726456332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.726456332
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.210136347
Short name T308
Test name
Test status
Simulation time 1534466202 ps
CPU time 5.55 seconds
Started Apr 28 02:10:01 PM PDT 24
Finished Apr 28 02:10:07 PM PDT 24
Peak memory 200956 kb
Host smart-3652f4ce-79f2-4b3b-82c2-1e84fcf8acae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210136347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.210136347
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3909248562
Short name T342
Test name
Test status
Simulation time 100539117 ps
CPU time 0.97 seconds
Started Apr 28 02:09:59 PM PDT 24
Finished Apr 28 02:10:00 PM PDT 24
Peak memory 200860 kb
Host smart-e4766c19-3ef1-4a1e-a297-90885d7072e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909248562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3909248562
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1514176683
Short name T270
Test name
Test status
Simulation time 246373912 ps
CPU time 1.54 seconds
Started Apr 28 02:10:01 PM PDT 24
Finished Apr 28 02:10:03 PM PDT 24
Peak memory 201084 kb
Host smart-ae50fbc6-f29d-4b1f-b4b0-16437ae7ddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514176683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1514176683
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.879980624
Short name T345
Test name
Test status
Simulation time 6264042214 ps
CPU time 21.33 seconds
Started Apr 28 02:10:01 PM PDT 24
Finished Apr 28 02:10:23 PM PDT 24
Peak memory 201188 kb
Host smart-5bc8b2c3-819e-4df3-a2b7-0ca498e71ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879980624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.879980624
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1358492234
Short name T236
Test name
Test status
Simulation time 136276379 ps
CPU time 1.76 seconds
Started Apr 28 02:10:00 PM PDT 24
Finished Apr 28 02:10:02 PM PDT 24
Peak memory 200880 kb
Host smart-abd15079-9c79-466a-bf14-ce7c5c4f971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358492234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1358492234
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2611166019
Short name T343
Test name
Test status
Simulation time 104445226 ps
CPU time 0.98 seconds
Started Apr 28 02:10:01 PM PDT 24
Finished Apr 28 02:10:03 PM PDT 24
Peak memory 200864 kb
Host smart-037da71c-9e64-4144-8575-b78af8b38e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611166019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2611166019
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2474151940
Short name T281
Test name
Test status
Simulation time 80688740 ps
CPU time 0.81 seconds
Started Apr 28 02:08:50 PM PDT 24
Finished Apr 28 02:08:51 PM PDT 24
Peak memory 200700 kb
Host smart-866bfdc0-8def-4959-9b67-e2d16cb91f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474151940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2474151940
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1915897393
Short name T443
Test name
Test status
Simulation time 1900536016 ps
CPU time 7.62 seconds
Started Apr 28 02:08:57 PM PDT 24
Finished Apr 28 02:09:05 PM PDT 24
Peak memory 217592 kb
Host smart-f164dce8-3b93-4cf5-aacd-33635026e812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915897393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1915897393
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3913241416
Short name T462
Test name
Test status
Simulation time 244032858 ps
CPU time 1.15 seconds
Started Apr 28 02:08:50 PM PDT 24
Finished Apr 28 02:08:51 PM PDT 24
Peak memory 218004 kb
Host smart-4db635b1-610f-41f7-8508-1db8b9a3ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913241416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3913241416
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3616745641
Short name T291
Test name
Test status
Simulation time 139949595 ps
CPU time 0.82 seconds
Started Apr 28 02:08:47 PM PDT 24
Finished Apr 28 02:08:48 PM PDT 24
Peak memory 200600 kb
Host smart-a83d60bf-e8ac-4459-b438-57bc076edc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616745641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3616745641
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.513243824
Short name T454
Test name
Test status
Simulation time 1507871092 ps
CPU time 5.57 seconds
Started Apr 28 02:08:46 PM PDT 24
Finished Apr 28 02:08:52 PM PDT 24
Peak memory 201096 kb
Host smart-ac664c51-5651-4dba-81d7-b9130f990275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513243824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.513243824
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.443589669
Short name T69
Test name
Test status
Simulation time 8401590102 ps
CPU time 12.52 seconds
Started Apr 28 02:08:48 PM PDT 24
Finished Apr 28 02:09:01 PM PDT 24
Peak memory 217800 kb
Host smart-3ce3d8b4-dbeb-40f9-a863-9e9e3f30fe4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443589669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.443589669
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3775470370
Short name T353
Test name
Test status
Simulation time 98745132 ps
CPU time 1.02 seconds
Started Apr 28 02:08:48 PM PDT 24
Finished Apr 28 02:08:50 PM PDT 24
Peak memory 200908 kb
Host smart-bb06f566-caf7-4d32-9afc-fb6af9c1bd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775470370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3775470370
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3646131204
Short name T497
Test name
Test status
Simulation time 118826514 ps
CPU time 1.22 seconds
Started Apr 28 02:08:44 PM PDT 24
Finished Apr 28 02:08:46 PM PDT 24
Peak memory 200948 kb
Host smart-7e68e5cb-077b-4035-861b-82d1c3af1d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646131204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3646131204
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1324564882
Short name T351
Test name
Test status
Simulation time 307944873 ps
CPU time 1.69 seconds
Started Apr 28 02:08:49 PM PDT 24
Finished Apr 28 02:08:51 PM PDT 24
Peak memory 200884 kb
Host smart-30b6f6df-62b7-49e9-ab29-2616485a648c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324564882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1324564882
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1823027407
Short name T269
Test name
Test status
Simulation time 405274705 ps
CPU time 2.1 seconds
Started Apr 28 02:08:48 PM PDT 24
Finished Apr 28 02:08:51 PM PDT 24
Peak memory 209112 kb
Host smart-0ce6df10-a27a-4e3e-b84c-a694a51bde3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823027407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1823027407
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2358211827
Short name T162
Test name
Test status
Simulation time 160203132 ps
CPU time 1.26 seconds
Started Apr 28 02:08:43 PM PDT 24
Finished Apr 28 02:08:45 PM PDT 24
Peak memory 200988 kb
Host smart-3545bc82-310d-41fb-9b9e-d543273b0a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358211827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2358211827
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.994282650
Short name T240
Test name
Test status
Simulation time 73982717 ps
CPU time 0.82 seconds
Started Apr 28 02:10:02 PM PDT 24
Finished Apr 28 02:10:04 PM PDT 24
Peak memory 200720 kb
Host smart-46737bda-e62a-48b1-b1be-2a940ced386f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994282650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.994282650
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.387607635
Short name T373
Test name
Test status
Simulation time 2163887094 ps
CPU time 8.38 seconds
Started Apr 28 02:10:05 PM PDT 24
Finished Apr 28 02:10:14 PM PDT 24
Peak memory 218184 kb
Host smart-0848f30d-fef2-4d74-a4fe-d48675df9b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387607635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.387607635
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.445186039
Short name T502
Test name
Test status
Simulation time 245414931 ps
CPU time 1.02 seconds
Started Apr 28 02:10:05 PM PDT 24
Finished Apr 28 02:10:06 PM PDT 24
Peak memory 218160 kb
Host smart-6b99cab7-c9f7-4880-9869-3466ceef6ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445186039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.445186039
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2726813800
Short name T297
Test name
Test status
Simulation time 101371537 ps
CPU time 0.76 seconds
Started Apr 28 02:09:59 PM PDT 24
Finished Apr 28 02:10:00 PM PDT 24
Peak memory 200724 kb
Host smart-52e95b09-b751-49d2-9c25-7676c6f631d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726813800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2726813800
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3160006455
Short name T11
Test name
Test status
Simulation time 961455787 ps
CPU time 4.99 seconds
Started Apr 28 02:09:59 PM PDT 24
Finished Apr 28 02:10:04 PM PDT 24
Peak memory 201068 kb
Host smart-868969a8-8168-409f-841b-21f6b7368be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160006455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3160006455
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3127504711
Short name T122
Test name
Test status
Simulation time 103939151 ps
CPU time 1.04 seconds
Started Apr 28 02:10:04 PM PDT 24
Finished Apr 28 02:10:06 PM PDT 24
Peak memory 200860 kb
Host smart-e03d459f-7e2e-49db-ad77-41e195bbbabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127504711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3127504711
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2818387143
Short name T362
Test name
Test status
Simulation time 126874872 ps
CPU time 1.2 seconds
Started Apr 28 02:10:03 PM PDT 24
Finished Apr 28 02:10:04 PM PDT 24
Peak memory 201076 kb
Host smart-529e2958-86fc-4b8c-acb2-62e331a8f0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818387143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2818387143
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.114732003
Short name T119
Test name
Test status
Simulation time 10501196991 ps
CPU time 36.07 seconds
Started Apr 28 02:10:04 PM PDT 24
Finished Apr 28 02:10:40 PM PDT 24
Peak memory 209376 kb
Host smart-c5545dde-83d3-4938-930d-bac2e5ba2353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114732003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.114732003
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.462462854
Short name T124
Test name
Test status
Simulation time 485537423 ps
CPU time 2.57 seconds
Started Apr 28 02:10:01 PM PDT 24
Finished Apr 28 02:10:04 PM PDT 24
Peak memory 200856 kb
Host smart-c8c516cc-578f-45fd-b65f-a95d710e4cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462462854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.462462854
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1851621424
Short name T78
Test name
Test status
Simulation time 119649977 ps
CPU time 1.02 seconds
Started Apr 28 02:09:59 PM PDT 24
Finished Apr 28 02:10:00 PM PDT 24
Peak memory 200928 kb
Host smart-e817ec34-7b6c-4cb7-af2d-70efcb84b669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851621424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1851621424
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2074550035
Short name T191
Test name
Test status
Simulation time 86064520 ps
CPU time 0.79 seconds
Started Apr 28 02:10:04 PM PDT 24
Finished Apr 28 02:10:05 PM PDT 24
Peak memory 200732 kb
Host smart-ef2274fa-537d-45e4-8de5-2b8832633b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074550035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2074550035
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3246864807
Short name T450
Test name
Test status
Simulation time 1225206661 ps
CPU time 5.9 seconds
Started Apr 28 02:10:02 PM PDT 24
Finished Apr 28 02:10:09 PM PDT 24
Peak memory 222664 kb
Host smart-a7be1fcd-deec-4f63-8ca6-78f17ed00134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246864807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3246864807
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1242733322
Short name T412
Test name
Test status
Simulation time 243607816 ps
CPU time 1.05 seconds
Started Apr 28 02:10:03 PM PDT 24
Finished Apr 28 02:10:05 PM PDT 24
Peak memory 218256 kb
Host smart-df23fffb-c83b-4026-bdbd-aa04ebe97a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242733322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1242733322
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3674213382
Short name T164
Test name
Test status
Simulation time 171357534 ps
CPU time 0.86 seconds
Started Apr 28 02:10:04 PM PDT 24
Finished Apr 28 02:10:05 PM PDT 24
Peak memory 200716 kb
Host smart-835445e3-f2a1-4aee-8a97-8415fa2fa26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674213382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3674213382
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.982277750
Short name T118
Test name
Test status
Simulation time 1425163648 ps
CPU time 5.63 seconds
Started Apr 28 02:10:04 PM PDT 24
Finished Apr 28 02:10:10 PM PDT 24
Peak memory 201012 kb
Host smart-f5b0c4c9-ce6f-4e44-ad56-3ea26d4ee421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982277750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.982277750
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1040997613
Short name T223
Test name
Test status
Simulation time 97573655 ps
CPU time 0.94 seconds
Started Apr 28 02:10:03 PM PDT 24
Finished Apr 28 02:10:04 PM PDT 24
Peak memory 200800 kb
Host smart-dd05de06-6a40-4978-8026-4e6bcfcdc4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040997613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1040997613
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.747528977
Short name T154
Test name
Test status
Simulation time 197819511 ps
CPU time 1.47 seconds
Started Apr 28 02:10:04 PM PDT 24
Finished Apr 28 02:10:06 PM PDT 24
Peak memory 200948 kb
Host smart-80a61db5-4a71-4a77-8e18-a205bd626c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747528977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.747528977
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.4007623521
Short name T186
Test name
Test status
Simulation time 6336748001 ps
CPU time 20.28 seconds
Started Apr 28 02:10:04 PM PDT 24
Finished Apr 28 02:10:25 PM PDT 24
Peak memory 209432 kb
Host smart-b4c7b341-845a-4567-b22b-6e0115324bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007623521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4007623521
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1865375952
Short name T196
Test name
Test status
Simulation time 311149273 ps
CPU time 2.12 seconds
Started Apr 28 02:10:03 PM PDT 24
Finished Apr 28 02:10:06 PM PDT 24
Peak memory 200828 kb
Host smart-9ea2ecea-70ab-4dbc-bdd8-dd9fe0e4dec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865375952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1865375952
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.138540085
Short name T76
Test name
Test status
Simulation time 140942442 ps
CPU time 1.21 seconds
Started Apr 28 02:10:05 PM PDT 24
Finished Apr 28 02:10:07 PM PDT 24
Peak memory 200876 kb
Host smart-8c80b9e1-361b-4b56-af71-8f4d98f0e434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138540085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.138540085
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3366081226
Short name T147
Test name
Test status
Simulation time 69534581 ps
CPU time 0.79 seconds
Started Apr 28 02:10:10 PM PDT 24
Finished Apr 28 02:10:11 PM PDT 24
Peak memory 200692 kb
Host smart-9d477714-a0ac-4fd4-933d-ca8f28218d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366081226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3366081226
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.368018625
Short name T23
Test name
Test status
Simulation time 1230244761 ps
CPU time 5.97 seconds
Started Apr 28 02:10:10 PM PDT 24
Finished Apr 28 02:10:17 PM PDT 24
Peak memory 222624 kb
Host smart-8acdc44b-49b3-4595-a854-262cfc64e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368018625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.368018625
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1949110623
Short name T1
Test name
Test status
Simulation time 244197548 ps
CPU time 1.09 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:10:15 PM PDT 24
Peak memory 217992 kb
Host smart-142bf787-de92-46cb-b0a0-4c81c6a024b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949110623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1949110623
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.292560722
Short name T22
Test name
Test status
Simulation time 163785304 ps
CPU time 0.86 seconds
Started Apr 28 02:10:04 PM PDT 24
Finished Apr 28 02:10:06 PM PDT 24
Peak memory 200708 kb
Host smart-dd60f3d4-edc3-4beb-88ba-5018bdc3d50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292560722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.292560722
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.17120014
Short name T527
Test name
Test status
Simulation time 818281276 ps
CPU time 3.89 seconds
Started Apr 28 02:10:04 PM PDT 24
Finished Apr 28 02:10:08 PM PDT 24
Peak memory 201072 kb
Host smart-6a89328c-6be2-46c3-a01f-14c9feedcd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17120014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.17120014
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3800717528
Short name T217
Test name
Test status
Simulation time 168081819 ps
CPU time 1.15 seconds
Started Apr 28 02:10:12 PM PDT 24
Finished Apr 28 02:10:13 PM PDT 24
Peak memory 200884 kb
Host smart-0d1c5782-3d30-455f-aec6-0329812983c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800717528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3800717528
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2047196711
Short name T12
Test name
Test status
Simulation time 125164541 ps
CPU time 1.17 seconds
Started Apr 28 02:10:03 PM PDT 24
Finished Apr 28 02:10:05 PM PDT 24
Peak memory 200940 kb
Host smart-7b0b5bac-7a89-4eab-b484-ce69e01b919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047196711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2047196711
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.998162344
Short name T188
Test name
Test status
Simulation time 10378203929 ps
CPU time 34.05 seconds
Started Apr 28 02:10:11 PM PDT 24
Finished Apr 28 02:10:45 PM PDT 24
Peak memory 201228 kb
Host smart-42614f21-d60e-403c-9dc7-ae8ec67e7627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998162344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.998162344
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.207864060
Short name T508
Test name
Test status
Simulation time 267955866 ps
CPU time 1.92 seconds
Started Apr 28 02:10:12 PM PDT 24
Finished Apr 28 02:10:15 PM PDT 24
Peak memory 200876 kb
Host smart-324fb462-65d0-428a-86bb-362111dc09f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207864060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.207864060
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2023272209
Short name T533
Test name
Test status
Simulation time 79787378 ps
CPU time 0.83 seconds
Started Apr 28 02:10:09 PM PDT 24
Finished Apr 28 02:10:11 PM PDT 24
Peak memory 200904 kb
Host smart-87cd418f-8eb9-455b-bade-c277863a2a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023272209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2023272209
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1253409655
Short name T199
Test name
Test status
Simulation time 78772944 ps
CPU time 0.74 seconds
Started Apr 28 02:10:12 PM PDT 24
Finished Apr 28 02:10:14 PM PDT 24
Peak memory 200740 kb
Host smart-2b903d89-fd87-4dfe-b979-4b11ab867712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253409655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1253409655
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1661039355
Short name T35
Test name
Test status
Simulation time 1222995251 ps
CPU time 5.87 seconds
Started Apr 28 02:10:11 PM PDT 24
Finished Apr 28 02:10:18 PM PDT 24
Peak memory 218508 kb
Host smart-8047b553-3897-481d-8d9a-8a8738f43bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661039355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1661039355
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2364642213
Short name T267
Test name
Test status
Simulation time 243695609 ps
CPU time 1.09 seconds
Started Apr 28 02:10:11 PM PDT 24
Finished Apr 28 02:10:13 PM PDT 24
Peak memory 218284 kb
Host smart-69a8c159-41da-4245-8ffa-03d49dd36256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364642213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2364642213
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2759703941
Short name T540
Test name
Test status
Simulation time 95199612 ps
CPU time 0.81 seconds
Started Apr 28 02:10:11 PM PDT 24
Finished Apr 28 02:10:12 PM PDT 24
Peak memory 200604 kb
Host smart-430fe5a7-af40-419a-96c4-3e978fd8d949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759703941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2759703941
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1346919038
Short name T423
Test name
Test status
Simulation time 896030457 ps
CPU time 4.59 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:10:19 PM PDT 24
Peak memory 200968 kb
Host smart-40b1ad30-ba22-4040-830b-bdb3a7711a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346919038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1346919038
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2250822999
Short name T234
Test name
Test status
Simulation time 186941892 ps
CPU time 1.21 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:10:14 PM PDT 24
Peak memory 200896 kb
Host smart-94bf0062-968a-442b-86a2-23656aac9dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250822999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2250822999
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2193216117
Short name T174
Test name
Test status
Simulation time 205451281 ps
CPU time 1.43 seconds
Started Apr 28 02:10:11 PM PDT 24
Finished Apr 28 02:10:13 PM PDT 24
Peak memory 201000 kb
Host smart-1817a02e-5b00-4e92-9957-17a016bfbe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193216117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2193216117
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.4054548582
Short name T429
Test name
Test status
Simulation time 2249624351 ps
CPU time 8 seconds
Started Apr 28 02:10:12 PM PDT 24
Finished Apr 28 02:10:21 PM PDT 24
Peak memory 201232 kb
Host smart-fffce077-3089-4f0e-a1f9-ca2447131e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054548582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.4054548582
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1528076430
Short name T292
Test name
Test status
Simulation time 254939739 ps
CPU time 1.7 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:10:15 PM PDT 24
Peak memory 200908 kb
Host smart-17ede3ff-644b-4acf-b4aa-b198e0f821f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528076430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1528076430
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2323049587
Short name T218
Test name
Test status
Simulation time 61535273 ps
CPU time 0.74 seconds
Started Apr 28 02:10:12 PM PDT 24
Finished Apr 28 02:10:13 PM PDT 24
Peak memory 200864 kb
Host smart-06a0a8bf-d189-4ec4-8cda-60bf5a2af21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323049587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2323049587
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2136254402
Short name T501
Test name
Test status
Simulation time 64403665 ps
CPU time 0.74 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:10:14 PM PDT 24
Peak memory 200724 kb
Host smart-98c8e80a-0826-4383-8e39-e88ba6c4d458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136254402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2136254402
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1970811984
Short name T36
Test name
Test status
Simulation time 2357292624 ps
CPU time 8.08 seconds
Started Apr 28 02:10:16 PM PDT 24
Finished Apr 28 02:10:25 PM PDT 24
Peak memory 218720 kb
Host smart-11536384-07a2-4544-96e3-c2871c45d98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970811984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1970811984
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1051625684
Short name T448
Test name
Test status
Simulation time 244485002 ps
CPU time 1.02 seconds
Started Apr 28 02:10:14 PM PDT 24
Finished Apr 28 02:10:16 PM PDT 24
Peak memory 218156 kb
Host smart-26090ee1-dc0b-4104-8f5d-b408822645f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051625684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1051625684
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2925075176
Short name T19
Test name
Test status
Simulation time 214240693 ps
CPU time 0.84 seconds
Started Apr 28 02:10:25 PM PDT 24
Finished Apr 28 02:10:27 PM PDT 24
Peak memory 200696 kb
Host smart-5ad6b21f-7393-4dcd-ae1f-d9208d20a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925075176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2925075176
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2680740598
Short name T197
Test name
Test status
Simulation time 943623749 ps
CPU time 4.55 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:10:18 PM PDT 24
Peak memory 201076 kb
Host smart-b85c97df-ca0b-4bb8-8d2c-9108d4a59093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680740598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2680740598
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.4202710550
Short name T416
Test name
Test status
Simulation time 111616644 ps
CPU time 1.01 seconds
Started Apr 28 02:10:14 PM PDT 24
Finished Apr 28 02:10:15 PM PDT 24
Peak memory 200872 kb
Host smart-c40de559-a63b-4d15-a3ee-a05a54d0079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202710550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.4202710550
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2756554137
Short name T455
Test name
Test status
Simulation time 198080295 ps
CPU time 1.41 seconds
Started Apr 28 02:10:11 PM PDT 24
Finished Apr 28 02:10:13 PM PDT 24
Peak memory 201048 kb
Host smart-6204d14e-3a34-4647-b012-d96fd7048879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756554137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2756554137
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1910229713
Short name T277
Test name
Test status
Simulation time 11932422299 ps
CPU time 39.56 seconds
Started Apr 28 02:10:16 PM PDT 24
Finished Apr 28 02:10:55 PM PDT 24
Peak memory 209404 kb
Host smart-e156797b-3674-464a-be3a-3d2fba6c8f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910229713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1910229713
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3202113146
Short name T472
Test name
Test status
Simulation time 540657497 ps
CPU time 2.65 seconds
Started Apr 28 02:10:16 PM PDT 24
Finished Apr 28 02:10:19 PM PDT 24
Peak memory 200880 kb
Host smart-4d7a51cb-3d6f-4b9d-8661-3757398540a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202113146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3202113146
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2543807580
Short name T392
Test name
Test status
Simulation time 218036422 ps
CPU time 1.25 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:10:15 PM PDT 24
Peak memory 200880 kb
Host smart-47a7976b-4b6b-43f8-98c2-7a74514abf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543807580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2543807580
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.719419213
Short name T65
Test name
Test status
Simulation time 77491576 ps
CPU time 0.77 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:10:15 PM PDT 24
Peak memory 200736 kb
Host smart-5919d1ac-f91d-4ff9-8377-c2dd7f504162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719419213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.719419213
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.4115946835
Short name T316
Test name
Test status
Simulation time 2373765122 ps
CPU time 9.08 seconds
Started Apr 28 02:10:14 PM PDT 24
Finished Apr 28 02:10:24 PM PDT 24
Peak memory 230788 kb
Host smart-f2382cbf-aa30-46f0-b865-f4bb9e30cd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115946835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.4115946835
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.644643268
Short name T349
Test name
Test status
Simulation time 244075099 ps
CPU time 1.04 seconds
Started Apr 28 02:10:15 PM PDT 24
Finished Apr 28 02:10:16 PM PDT 24
Peak memory 218104 kb
Host smart-fa2181b4-f731-4925-8059-80cb79c5fcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644643268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.644643268
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.743676955
Short name T149
Test name
Test status
Simulation time 192199278 ps
CPU time 0.94 seconds
Started Apr 28 02:10:14 PM PDT 24
Finished Apr 28 02:10:16 PM PDT 24
Peak memory 200672 kb
Host smart-9c97df5c-65ef-4e6e-8c67-a4c02d656fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743676955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.743676955
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3045266928
Short name T451
Test name
Test status
Simulation time 798739365 ps
CPU time 3.86 seconds
Started Apr 28 02:10:14 PM PDT 24
Finished Apr 28 02:10:18 PM PDT 24
Peak memory 201060 kb
Host smart-1e15b1ec-ddbe-4717-9f2c-14abbd26e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045266928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3045266928
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.929322072
Short name T536
Test name
Test status
Simulation time 183447401 ps
CPU time 1.26 seconds
Started Apr 28 02:10:16 PM PDT 24
Finished Apr 28 02:10:18 PM PDT 24
Peak memory 200820 kb
Host smart-de52b030-2c60-4066-93ed-5941db8f9f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929322072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.929322072
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1228089023
Short name T203
Test name
Test status
Simulation time 116355769 ps
CPU time 1.24 seconds
Started Apr 28 02:10:15 PM PDT 24
Finished Apr 28 02:10:17 PM PDT 24
Peak memory 200980 kb
Host smart-cd9a6c97-0eaf-4d4f-b25d-45c56933a956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228089023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1228089023
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3551313035
Short name T509
Test name
Test status
Simulation time 15108643075 ps
CPU time 50.58 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:11:05 PM PDT 24
Peak memory 209436 kb
Host smart-7b64d7ed-5cff-46ff-8617-280ebfbf09cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551313035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3551313035
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1241614963
Short name T252
Test name
Test status
Simulation time 366983811 ps
CPU time 2.07 seconds
Started Apr 28 02:10:15 PM PDT 24
Finished Apr 28 02:10:17 PM PDT 24
Peak memory 200880 kb
Host smart-b8a569ac-19fa-463b-abe5-9a1d8815fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241614963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1241614963
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2884637241
Short name T172
Test name
Test status
Simulation time 142540236 ps
CPU time 1.11 seconds
Started Apr 28 02:10:16 PM PDT 24
Finished Apr 28 02:10:17 PM PDT 24
Peak memory 200872 kb
Host smart-31900e3c-fd19-45a1-89f2-f58a87599bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884637241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2884637241
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.376920971
Short name T347
Test name
Test status
Simulation time 67575007 ps
CPU time 0.76 seconds
Started Apr 28 02:10:21 PM PDT 24
Finished Apr 28 02:10:22 PM PDT 24
Peak memory 200688 kb
Host smart-9d2cfc37-6b35-4cee-9214-b4f1c06da86f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376920971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.376920971
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2609246323
Short name T33
Test name
Test status
Simulation time 1221447776 ps
CPU time 5.75 seconds
Started Apr 28 02:10:22 PM PDT 24
Finished Apr 28 02:10:28 PM PDT 24
Peak memory 217592 kb
Host smart-1af2f75a-a71a-45f1-8c57-ee00660ef376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609246323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2609246323
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.518118009
Short name T530
Test name
Test status
Simulation time 244541126 ps
CPU time 1.02 seconds
Started Apr 28 02:10:20 PM PDT 24
Finished Apr 28 02:10:22 PM PDT 24
Peak memory 218400 kb
Host smart-ba5a29f3-5568-49e5-8d32-39cb458797f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518118009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.518118009
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3493546284
Short name T276
Test name
Test status
Simulation time 223742482 ps
CPU time 1 seconds
Started Apr 28 02:10:16 PM PDT 24
Finished Apr 28 02:10:17 PM PDT 24
Peak memory 200680 kb
Host smart-8d1a8e6f-8d68-4ba4-82b5-f01fa4f48814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493546284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3493546284
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3520688617
Short name T73
Test name
Test status
Simulation time 906871870 ps
CPU time 4.44 seconds
Started Apr 28 02:10:16 PM PDT 24
Finished Apr 28 02:10:21 PM PDT 24
Peak memory 201076 kb
Host smart-553e92e1-f70a-46c6-8ffa-28183f2ff1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520688617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3520688617
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4253033401
Short name T250
Test name
Test status
Simulation time 96318454 ps
CPU time 0.98 seconds
Started Apr 28 02:10:23 PM PDT 24
Finished Apr 28 02:10:24 PM PDT 24
Peak memory 200912 kb
Host smart-fcd8f709-c3df-4762-9a46-18b3b5407c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253033401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4253033401
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.651120094
Short name T238
Test name
Test status
Simulation time 122569288 ps
CPU time 1.15 seconds
Started Apr 28 02:10:13 PM PDT 24
Finished Apr 28 02:10:15 PM PDT 24
Peak memory 201064 kb
Host smart-346837d4-7af2-44f8-bfd3-d3a4f1677a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651120094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.651120094
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.4148979525
Short name T379
Test name
Test status
Simulation time 4965107411 ps
CPU time 23.37 seconds
Started Apr 28 02:10:19 PM PDT 24
Finished Apr 28 02:10:43 PM PDT 24
Peak memory 201184 kb
Host smart-0420f312-ef80-4a05-bf57-1d09d93f15f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148979525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.4148979525
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3023102480
Short name T328
Test name
Test status
Simulation time 139578526 ps
CPU time 1.73 seconds
Started Apr 28 02:10:21 PM PDT 24
Finished Apr 28 02:10:24 PM PDT 24
Peak memory 200928 kb
Host smart-b42ea614-17d7-4f70-9a16-9185720630ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023102480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3023102480
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1258227527
Short name T171
Test name
Test status
Simulation time 142735407 ps
CPU time 1.12 seconds
Started Apr 28 02:10:21 PM PDT 24
Finished Apr 28 02:10:23 PM PDT 24
Peak memory 200924 kb
Host smart-1d83c56c-4fa6-4881-824c-cad2c79d0822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258227527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1258227527
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2947199411
Short name T504
Test name
Test status
Simulation time 72902147 ps
CPU time 0.78 seconds
Started Apr 28 02:10:21 PM PDT 24
Finished Apr 28 02:10:22 PM PDT 24
Peak memory 200696 kb
Host smart-25a9aa52-216b-45d7-866d-e7198eb299b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947199411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2947199411
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.355924448
Short name T315
Test name
Test status
Simulation time 2170293033 ps
CPU time 7.64 seconds
Started Apr 28 02:10:24 PM PDT 24
Finished Apr 28 02:10:32 PM PDT 24
Peak memory 222728 kb
Host smart-7bb53e3d-beca-4518-be26-d504a0bd01b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355924448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.355924448
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.557764439
Short name T130
Test name
Test status
Simulation time 244701667 ps
CPU time 1.17 seconds
Started Apr 28 02:10:19 PM PDT 24
Finished Apr 28 02:10:21 PM PDT 24
Peak memory 218244 kb
Host smart-c8ea70ab-3e77-4133-96fe-77f725f84cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557764439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.557764439
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.607250485
Short name T453
Test name
Test status
Simulation time 136365661 ps
CPU time 0.81 seconds
Started Apr 28 02:10:23 PM PDT 24
Finished Apr 28 02:10:24 PM PDT 24
Peak memory 200720 kb
Host smart-cf5596a4-b8c7-4440-936b-efe37b861275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607250485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.607250485
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3676396171
Short name T363
Test name
Test status
Simulation time 1814414539 ps
CPU time 6.73 seconds
Started Apr 28 02:10:21 PM PDT 24
Finished Apr 28 02:10:28 PM PDT 24
Peak memory 201076 kb
Host smart-037bfa86-7555-4f1f-a5f5-eb2aff4f1d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676396171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3676396171
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.4230037892
Short name T204
Test name
Test status
Simulation time 147000139 ps
CPU time 1.09 seconds
Started Apr 28 02:10:19 PM PDT 24
Finished Apr 28 02:10:20 PM PDT 24
Peak memory 200876 kb
Host smart-572eb419-8ecc-4371-be53-baf4ec9f881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230037892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.4230037892
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.583426294
Short name T399
Test name
Test status
Simulation time 118990653 ps
CPU time 1.24 seconds
Started Apr 28 02:10:20 PM PDT 24
Finished Apr 28 02:10:22 PM PDT 24
Peak memory 201036 kb
Host smart-78f615c2-3938-4515-a31d-40fb6067acf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583426294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.583426294
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2565112374
Short name T43
Test name
Test status
Simulation time 5342616596 ps
CPU time 22.54 seconds
Started Apr 28 02:10:23 PM PDT 24
Finished Apr 28 02:10:46 PM PDT 24
Peak memory 209464 kb
Host smart-ede7baeb-68a8-4b89-9768-9e5a8adfdf10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565112374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2565112374
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3480791532
Short name T360
Test name
Test status
Simulation time 347150243 ps
CPU time 2.51 seconds
Started Apr 28 02:10:18 PM PDT 24
Finished Apr 28 02:10:21 PM PDT 24
Peak memory 200852 kb
Host smart-df50c213-1a0f-48a0-b1fd-8169ac8d7727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480791532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3480791532
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.486051624
Short name T426
Test name
Test status
Simulation time 99748770 ps
CPU time 0.82 seconds
Started Apr 28 02:10:21 PM PDT 24
Finished Apr 28 02:10:22 PM PDT 24
Peak memory 200924 kb
Host smart-581f4568-208d-41f2-86c5-b5694587d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486051624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.486051624
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2299642882
Short name T427
Test name
Test status
Simulation time 68939558 ps
CPU time 0.77 seconds
Started Apr 28 02:10:27 PM PDT 24
Finished Apr 28 02:10:28 PM PDT 24
Peak memory 200724 kb
Host smart-a388abc9-4a44-40ed-a7c0-1bc7add544c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299642882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2299642882
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1894518810
Short name T359
Test name
Test status
Simulation time 1881084685 ps
CPU time 6.88 seconds
Started Apr 28 02:10:25 PM PDT 24
Finished Apr 28 02:10:32 PM PDT 24
Peak memory 218616 kb
Host smart-ef1dff94-3f9b-4010-a56c-c6a7ea5d0b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894518810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1894518810
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2269064128
Short name T285
Test name
Test status
Simulation time 244410421 ps
CPU time 1.03 seconds
Started Apr 28 02:10:25 PM PDT 24
Finished Apr 28 02:10:26 PM PDT 24
Peak memory 218320 kb
Host smart-86601011-b451-4782-b4b7-e43ff9c0991b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269064128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2269064128
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2758276976
Short name T319
Test name
Test status
Simulation time 140915866 ps
CPU time 0.86 seconds
Started Apr 28 02:10:20 PM PDT 24
Finished Apr 28 02:10:21 PM PDT 24
Peak memory 200652 kb
Host smart-5e9117ef-5dc2-469b-ad2d-640d422b4c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758276976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2758276976
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.56719144
Short name T336
Test name
Test status
Simulation time 944655925 ps
CPU time 4.6 seconds
Started Apr 28 02:10:26 PM PDT 24
Finished Apr 28 02:10:31 PM PDT 24
Peak memory 201088 kb
Host smart-0c8a4a97-b414-427a-918c-48773723b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56719144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.56719144
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3955100046
Short name T137
Test name
Test status
Simulation time 93409125 ps
CPU time 0.98 seconds
Started Apr 28 02:10:27 PM PDT 24
Finished Apr 28 02:10:29 PM PDT 24
Peak memory 200860 kb
Host smart-efdb5f94-ed63-4303-8fce-cef44530e923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955100046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3955100046
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3581004582
Short name T386
Test name
Test status
Simulation time 106327030 ps
CPU time 1.21 seconds
Started Apr 28 02:10:21 PM PDT 24
Finished Apr 28 02:10:23 PM PDT 24
Peak memory 201088 kb
Host smart-a5205822-57d5-4638-af0b-978abc08a2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581004582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3581004582
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.777802924
Short name T245
Test name
Test status
Simulation time 13736270534 ps
CPU time 48.41 seconds
Started Apr 28 02:10:25 PM PDT 24
Finished Apr 28 02:11:14 PM PDT 24
Peak memory 209444 kb
Host smart-c14bdc7c-7281-42f5-aeb8-18d88c8841ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777802924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.777802924
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1078269302
Short name T170
Test name
Test status
Simulation time 128483979 ps
CPU time 1.69 seconds
Started Apr 28 02:10:28 PM PDT 24
Finished Apr 28 02:10:30 PM PDT 24
Peak memory 200924 kb
Host smart-c5dba066-242a-47da-933a-b58cf02517bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078269302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1078269302
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.453096851
Short name T519
Test name
Test status
Simulation time 96202164 ps
CPU time 0.85 seconds
Started Apr 28 02:10:24 PM PDT 24
Finished Apr 28 02:10:26 PM PDT 24
Peak memory 200912 kb
Host smart-b1cddf8d-72f8-476f-973c-1011327a7bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453096851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.453096851
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.446216473
Short name T522
Test name
Test status
Simulation time 63364782 ps
CPU time 0.77 seconds
Started Apr 28 02:10:26 PM PDT 24
Finished Apr 28 02:10:27 PM PDT 24
Peak memory 200612 kb
Host smart-1b084c7e-d241-43cd-932a-dc698eb19c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446216473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.446216473
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4183647414
Short name T295
Test name
Test status
Simulation time 2381045097 ps
CPU time 8.55 seconds
Started Apr 28 02:10:25 PM PDT 24
Finished Apr 28 02:10:34 PM PDT 24
Peak memory 230764 kb
Host smart-a31b3a08-8a44-47b7-a6a3-dcea515dedba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183647414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4183647414
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3602569275
Short name T436
Test name
Test status
Simulation time 243945742 ps
CPU time 1.12 seconds
Started Apr 28 02:10:24 PM PDT 24
Finished Apr 28 02:10:26 PM PDT 24
Peak memory 218292 kb
Host smart-ef4dad31-1b55-4851-a83e-818b51e4c2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602569275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3602569275
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2338674692
Short name T369
Test name
Test status
Simulation time 109531145 ps
CPU time 0.75 seconds
Started Apr 28 02:10:25 PM PDT 24
Finished Apr 28 02:10:27 PM PDT 24
Peak memory 200692 kb
Host smart-eed22b41-78a2-4c09-8803-f33ab52347a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338674692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2338674692
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2078627249
Short name T491
Test name
Test status
Simulation time 985994301 ps
CPU time 4.92 seconds
Started Apr 28 02:10:25 PM PDT 24
Finished Apr 28 02:10:31 PM PDT 24
Peak memory 201080 kb
Host smart-25bcfa36-c2de-47d7-b97c-28b88a24b708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078627249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2078627249
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1052620161
Short name T393
Test name
Test status
Simulation time 142207592 ps
CPU time 1.05 seconds
Started Apr 28 02:10:27 PM PDT 24
Finished Apr 28 02:10:29 PM PDT 24
Peak memory 200860 kb
Host smart-b70e007e-945b-4d4a-806b-f268bb3211b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052620161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1052620161
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3268720274
Short name T467
Test name
Test status
Simulation time 233875824 ps
CPU time 1.44 seconds
Started Apr 28 02:10:24 PM PDT 24
Finished Apr 28 02:10:27 PM PDT 24
Peak memory 200976 kb
Host smart-7073eca6-ecef-4120-b003-87e2dc481c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268720274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3268720274
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.906182129
Short name T366
Test name
Test status
Simulation time 4975319842 ps
CPU time 21.53 seconds
Started Apr 28 02:10:25 PM PDT 24
Finished Apr 28 02:10:48 PM PDT 24
Peak memory 209344 kb
Host smart-cc870a8a-81cb-4d55-855f-ce49d795755a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906182129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.906182129
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4251158255
Short name T317
Test name
Test status
Simulation time 355155842 ps
CPU time 2.32 seconds
Started Apr 28 02:10:24 PM PDT 24
Finished Apr 28 02:10:27 PM PDT 24
Peak memory 200928 kb
Host smart-d4677709-5ca4-4634-9f7b-c2307507177b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251158255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4251158255
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3883925938
Short name T136
Test name
Test status
Simulation time 125689593 ps
CPU time 1 seconds
Started Apr 28 02:10:24 PM PDT 24
Finished Apr 28 02:10:25 PM PDT 24
Peak memory 200904 kb
Host smart-76ef18c5-b5ef-4784-955c-8b4e5294622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883925938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3883925938
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2176777093
Short name T539
Test name
Test status
Simulation time 63070335 ps
CPU time 0.74 seconds
Started Apr 28 02:08:51 PM PDT 24
Finished Apr 28 02:08:52 PM PDT 24
Peak memory 200608 kb
Host smart-83f48778-19f5-4f7b-bfc5-c4237a3ee73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176777093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2176777093
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2649311243
Short name T507
Test name
Test status
Simulation time 1235043994 ps
CPU time 5.52 seconds
Started Apr 28 02:08:51 PM PDT 24
Finished Apr 28 02:08:57 PM PDT 24
Peak memory 218616 kb
Host smart-377502ad-0050-433f-832a-3d15a2302676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649311243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2649311243
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2415440675
Short name T417
Test name
Test status
Simulation time 244194540 ps
CPU time 1.06 seconds
Started Apr 28 02:08:49 PM PDT 24
Finished Apr 28 02:08:51 PM PDT 24
Peak memory 218304 kb
Host smart-a4de3d30-f186-45a6-a59d-73442b1dd742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415440675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2415440675
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3164786407
Short name T20
Test name
Test status
Simulation time 90535496 ps
CPU time 0.79 seconds
Started Apr 28 02:08:48 PM PDT 24
Finished Apr 28 02:08:50 PM PDT 24
Peak memory 200676 kb
Host smart-abcc6fae-5dcb-49c5-8f16-295c82096910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164786407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3164786407
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.372801329
Short name T92
Test name
Test status
Simulation time 758779558 ps
CPU time 3.72 seconds
Started Apr 28 02:08:48 PM PDT 24
Finished Apr 28 02:08:53 PM PDT 24
Peak memory 200992 kb
Host smart-bdb0b3d6-5829-4398-b3b4-55549ce0ccc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372801329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.372801329
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.337773704
Short name T68
Test name
Test status
Simulation time 16525339213 ps
CPU time 30.35 seconds
Started Apr 28 02:08:51 PM PDT 24
Finished Apr 28 02:09:22 PM PDT 24
Peak memory 218328 kb
Host smart-c84fcb96-fc23-4717-b361-796e8adde3ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337773704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.337773704
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1457669451
Short name T538
Test name
Test status
Simulation time 99076562 ps
CPU time 1 seconds
Started Apr 28 02:08:48 PM PDT 24
Finished Apr 28 02:08:50 PM PDT 24
Peak memory 200852 kb
Host smart-943485b5-cad6-4f8d-b59b-6abbf4e2bdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457669451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1457669451
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3449718306
Short name T447
Test name
Test status
Simulation time 109231619 ps
CPU time 1.21 seconds
Started Apr 28 02:08:49 PM PDT 24
Finished Apr 28 02:08:51 PM PDT 24
Peak memory 201016 kb
Host smart-2b06a715-6b70-4ecd-b9d1-ccaa8a38b15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449718306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3449718306
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1955690219
Short name T498
Test name
Test status
Simulation time 12439721207 ps
CPU time 43.8 seconds
Started Apr 28 02:08:48 PM PDT 24
Finished Apr 28 02:09:33 PM PDT 24
Peak memory 209308 kb
Host smart-519abe7a-5f3f-4fbc-afc9-22dd25bff770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955690219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1955690219
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1653450945
Short name T38
Test name
Test status
Simulation time 314197126 ps
CPU time 2.09 seconds
Started Apr 28 02:08:49 PM PDT 24
Finished Apr 28 02:08:51 PM PDT 24
Peak memory 209132 kb
Host smart-be431d78-1ab7-425a-bebf-388b9503e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653450945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1653450945
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.802776003
Short name T219
Test name
Test status
Simulation time 116742168 ps
CPU time 0.99 seconds
Started Apr 28 02:08:50 PM PDT 24
Finished Apr 28 02:08:51 PM PDT 24
Peak memory 200800 kb
Host smart-c74c783f-bf11-4f6a-ba1e-0c6e29cf25e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802776003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.802776003
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3446425262
Short name T254
Test name
Test status
Simulation time 75160492 ps
CPU time 0.77 seconds
Started Apr 28 02:10:32 PM PDT 24
Finished Apr 28 02:10:33 PM PDT 24
Peak memory 200632 kb
Host smart-4a8ec50f-fda9-4e39-b18e-013bfec4e624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446425262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3446425262
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.473817377
Short name T34
Test name
Test status
Simulation time 1227285683 ps
CPU time 5.41 seconds
Started Apr 28 02:10:32 PM PDT 24
Finished Apr 28 02:10:38 PM PDT 24
Peak memory 218620 kb
Host smart-26f52121-0d2d-471d-a003-ed3858675bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473817377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.473817377
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3978776552
Short name T141
Test name
Test status
Simulation time 244249788 ps
CPU time 1.08 seconds
Started Apr 28 02:10:32 PM PDT 24
Finished Apr 28 02:10:34 PM PDT 24
Peak memory 218304 kb
Host smart-0759699e-d721-4705-8ddf-fb753a34f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978776552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3978776552
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3585497037
Short name T262
Test name
Test status
Simulation time 97665098 ps
CPU time 0.73 seconds
Started Apr 28 02:10:27 PM PDT 24
Finished Apr 28 02:10:28 PM PDT 24
Peak memory 200676 kb
Host smart-b60978e9-1900-404f-b636-b6d2035fc0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585497037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3585497037
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3889335604
Short name T463
Test name
Test status
Simulation time 1059712896 ps
CPU time 5.16 seconds
Started Apr 28 02:10:28 PM PDT 24
Finished Apr 28 02:10:33 PM PDT 24
Peak memory 201068 kb
Host smart-197bbb01-e1e8-4dcd-a765-15d1fe5cdf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889335604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3889335604
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2152915836
Short name T8
Test name
Test status
Simulation time 98439320 ps
CPU time 0.99 seconds
Started Apr 28 02:10:31 PM PDT 24
Finished Apr 28 02:10:33 PM PDT 24
Peak memory 200760 kb
Host smart-5004075c-a252-4667-b915-d857673de46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152915836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2152915836
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2575700371
Short name T517
Test name
Test status
Simulation time 122192926 ps
CPU time 1.24 seconds
Started Apr 28 02:10:24 PM PDT 24
Finished Apr 28 02:10:26 PM PDT 24
Peak memory 201068 kb
Host smart-0c813acd-00d8-49c6-9b6c-7af6a6395db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575700371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2575700371
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.971199244
Short name T235
Test name
Test status
Simulation time 1467255244 ps
CPU time 5.54 seconds
Started Apr 28 02:10:31 PM PDT 24
Finished Apr 28 02:10:37 PM PDT 24
Peak memory 200992 kb
Host smart-ce8a0358-5a06-44a1-9fd9-3b788f24d0cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971199244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.971199244
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3825327953
Short name T311
Test name
Test status
Simulation time 312287036 ps
CPU time 1.98 seconds
Started Apr 28 02:10:27 PM PDT 24
Finished Apr 28 02:10:30 PM PDT 24
Peak memory 200852 kb
Host smart-3fe56dee-801b-4b9c-85e2-ae967ac12ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825327953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3825327953
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3705119288
Short name T485
Test name
Test status
Simulation time 111697349 ps
CPU time 0.9 seconds
Started Apr 28 02:10:25 PM PDT 24
Finished Apr 28 02:10:27 PM PDT 24
Peak memory 200864 kb
Host smart-ed127d8f-2ed2-42c8-b460-5c7fe9a1ea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705119288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3705119288
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3727048062
Short name T489
Test name
Test status
Simulation time 71661599 ps
CPU time 0.75 seconds
Started Apr 28 02:10:35 PM PDT 24
Finished Apr 28 02:10:36 PM PDT 24
Peak memory 200632 kb
Host smart-5bdfb8be-8fcf-43ef-b309-d404cc0f7d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727048062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3727048062
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3476922819
Short name T47
Test name
Test status
Simulation time 1229583684 ps
CPU time 5.7 seconds
Started Apr 28 02:10:30 PM PDT 24
Finished Apr 28 02:10:36 PM PDT 24
Peak memory 218108 kb
Host smart-13e8b51b-62ef-4a89-8238-53b5f4c20793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476922819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3476922819
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.624722075
Short name T484
Test name
Test status
Simulation time 244488714 ps
CPU time 1.01 seconds
Started Apr 28 02:10:31 PM PDT 24
Finished Apr 28 02:10:33 PM PDT 24
Peak memory 218048 kb
Host smart-cf85a129-71f2-4740-a83a-faa0f162dcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624722075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.624722075
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3920698352
Short name T402
Test name
Test status
Simulation time 162607744 ps
CPU time 0.78 seconds
Started Apr 28 02:10:29 PM PDT 24
Finished Apr 28 02:10:30 PM PDT 24
Peak memory 200672 kb
Host smart-95565a70-f301-4ece-9930-548e6c27f27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920698352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3920698352
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.283636199
Short name T483
Test name
Test status
Simulation time 1824301811 ps
CPU time 6.3 seconds
Started Apr 28 02:10:30 PM PDT 24
Finished Apr 28 02:10:36 PM PDT 24
Peak memory 201088 kb
Host smart-6f696af2-87b4-4127-8527-2ff1dce90cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283636199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.283636199
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2816039052
Short name T384
Test name
Test status
Simulation time 149206240 ps
CPU time 1.19 seconds
Started Apr 28 02:10:31 PM PDT 24
Finished Apr 28 02:10:33 PM PDT 24
Peak memory 200880 kb
Host smart-10016760-23c9-4c35-8a04-13911e070318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816039052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2816039052
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3092079906
Short name T280
Test name
Test status
Simulation time 125397267 ps
CPU time 1.17 seconds
Started Apr 28 02:10:30 PM PDT 24
Finished Apr 28 02:10:32 PM PDT 24
Peak memory 201068 kb
Host smart-46898cb6-f416-41c9-ab37-78279299498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092079906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3092079906
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2940236541
Short name T239
Test name
Test status
Simulation time 259112795 ps
CPU time 1.77 seconds
Started Apr 28 02:10:31 PM PDT 24
Finished Apr 28 02:10:33 PM PDT 24
Peak memory 200896 kb
Host smart-ec0bc891-9516-4e81-bdd0-0c92414d61f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940236541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2940236541
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1184917056
Short name T229
Test name
Test status
Simulation time 157653655 ps
CPU time 1.2 seconds
Started Apr 28 02:10:30 PM PDT 24
Finished Apr 28 02:10:31 PM PDT 24
Peak memory 201104 kb
Host smart-a22311af-586f-4e7b-a983-473f2850c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184917056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1184917056
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1008949648
Short name T322
Test name
Test status
Simulation time 66993745 ps
CPU time 0.75 seconds
Started Apr 28 02:10:34 PM PDT 24
Finished Apr 28 02:10:35 PM PDT 24
Peak memory 200688 kb
Host smart-925dbc86-32c5-4c20-a42b-0393d127975f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008949648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1008949648
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1111742101
Short name T452
Test name
Test status
Simulation time 1226447797 ps
CPU time 5.71 seconds
Started Apr 28 02:10:34 PM PDT 24
Finished Apr 28 02:10:40 PM PDT 24
Peak memory 218580 kb
Host smart-c6db2838-7ea2-41fa-8140-d6fce27c93e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111742101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1111742101
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.81870717
Short name T155
Test name
Test status
Simulation time 244249867 ps
CPU time 1.09 seconds
Started Apr 28 02:10:39 PM PDT 24
Finished Apr 28 02:10:41 PM PDT 24
Peak memory 218108 kb
Host smart-633c3358-c61d-46b7-80fa-c91a300c0b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81870717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.81870717
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1852071083
Short name T323
Test name
Test status
Simulation time 234657041 ps
CPU time 1.02 seconds
Started Apr 28 02:10:34 PM PDT 24
Finished Apr 28 02:10:35 PM PDT 24
Peak memory 200652 kb
Host smart-2bb6e5f5-5172-4287-884d-28cc2e8787fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852071083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1852071083
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.233141249
Short name T357
Test name
Test status
Simulation time 1977468052 ps
CPU time 7.18 seconds
Started Apr 28 02:10:40 PM PDT 24
Finished Apr 28 02:10:48 PM PDT 24
Peak memory 201016 kb
Host smart-69a0f41e-e945-487b-a889-366473c381e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233141249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.233141249
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.4270511633
Short name T159
Test name
Test status
Simulation time 181624611 ps
CPU time 1.2 seconds
Started Apr 28 02:10:34 PM PDT 24
Finished Apr 28 02:10:36 PM PDT 24
Peak memory 200868 kb
Host smart-b2a1da8b-28bf-4f5d-8c2f-663d40d0a14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270511633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.4270511633
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1303383288
Short name T367
Test name
Test status
Simulation time 193159058 ps
CPU time 1.39 seconds
Started Apr 28 02:10:35 PM PDT 24
Finished Apr 28 02:10:37 PM PDT 24
Peak memory 201040 kb
Host smart-56b731ca-c049-4026-b01f-44640099ee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303383288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1303383288
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1434151660
Short name T537
Test name
Test status
Simulation time 3498482591 ps
CPU time 16.78 seconds
Started Apr 28 02:10:39 PM PDT 24
Finished Apr 28 02:10:56 PM PDT 24
Peak memory 201204 kb
Host smart-9f964c27-dcb9-4a2c-be6e-b91f10b738f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434151660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1434151660
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3122746564
Short name T5
Test name
Test status
Simulation time 211160023 ps
CPU time 1.3 seconds
Started Apr 28 02:10:35 PM PDT 24
Finished Apr 28 02:10:37 PM PDT 24
Peak memory 200916 kb
Host smart-97ba156f-b174-45d6-8b0d-1b1005ef32d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122746564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3122746564
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3550831811
Short name T300
Test name
Test status
Simulation time 73021387 ps
CPU time 0.77 seconds
Started Apr 28 02:10:41 PM PDT 24
Finished Apr 28 02:10:42 PM PDT 24
Peak memory 200616 kb
Host smart-710ced24-201e-4cd2-ae05-7d0d109d8030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550831811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3550831811
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2181773027
Short name T435
Test name
Test status
Simulation time 1220450317 ps
CPU time 5.61 seconds
Started Apr 28 02:10:39 PM PDT 24
Finished Apr 28 02:10:45 PM PDT 24
Peak memory 218608 kb
Host smart-1ddef0a7-91a8-4a2d-ab18-f3e0884833c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181773027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2181773027
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1501635045
Short name T151
Test name
Test status
Simulation time 244077614 ps
CPU time 1.03 seconds
Started Apr 28 02:10:35 PM PDT 24
Finished Apr 28 02:10:36 PM PDT 24
Peak memory 218164 kb
Host smart-b3f20847-2c4e-44f5-8f13-da486bb57e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501635045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1501635045
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.4107683589
Short name T303
Test name
Test status
Simulation time 111907516 ps
CPU time 0.83 seconds
Started Apr 28 02:10:37 PM PDT 24
Finished Apr 28 02:10:38 PM PDT 24
Peak memory 200700 kb
Host smart-fcdd9e6b-a43c-4a0c-9361-7050bbd89413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107683589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.4107683589
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.4097150820
Short name T340
Test name
Test status
Simulation time 1864505536 ps
CPU time 7.08 seconds
Started Apr 28 02:10:41 PM PDT 24
Finished Apr 28 02:10:49 PM PDT 24
Peak memory 200984 kb
Host smart-d2e401dc-4a32-4655-ae26-5abc689c5014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097150820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.4097150820
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.583842697
Short name T200
Test name
Test status
Simulation time 181416922 ps
CPU time 1.17 seconds
Started Apr 28 02:10:36 PM PDT 24
Finished Apr 28 02:10:37 PM PDT 24
Peak memory 200884 kb
Host smart-2df456b5-cef0-4c1a-895d-1bf3f6a64f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583842697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.583842697
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3999160466
Short name T81
Test name
Test status
Simulation time 199662474 ps
CPU time 1.42 seconds
Started Apr 28 02:10:39 PM PDT 24
Finished Apr 28 02:10:41 PM PDT 24
Peak memory 201060 kb
Host smart-29a528ba-73fa-4aaf-975a-562155868482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999160466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3999160466
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.476374250
Short name T75
Test name
Test status
Simulation time 4483142510 ps
CPU time 16.4 seconds
Started Apr 28 02:10:37 PM PDT 24
Finished Apr 28 02:10:54 PM PDT 24
Peak memory 201232 kb
Host smart-ce86283b-0d20-4482-b35b-adeae232db71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476374250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.476374250
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1673407755
Short name T175
Test name
Test status
Simulation time 365784732 ps
CPU time 2.23 seconds
Started Apr 28 02:10:38 PM PDT 24
Finished Apr 28 02:10:40 PM PDT 24
Peak memory 200864 kb
Host smart-64618e74-0c3c-4039-bf72-b3b08a5b7180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673407755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1673407755
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3127516729
Short name T266
Test name
Test status
Simulation time 80661611 ps
CPU time 0.8 seconds
Started Apr 28 02:10:35 PM PDT 24
Finished Apr 28 02:10:37 PM PDT 24
Peak memory 200880 kb
Host smart-f6d19043-cfcc-413d-80ea-0927a845b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127516729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3127516729
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1721830455
Short name T320
Test name
Test status
Simulation time 65659727 ps
CPU time 0.71 seconds
Started Apr 28 02:10:38 PM PDT 24
Finished Apr 28 02:10:39 PM PDT 24
Peak memory 200604 kb
Host smart-ac1fffa6-cabd-471b-b627-80581f0e5241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721830455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1721830455
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2671687479
Short name T278
Test name
Test status
Simulation time 2182842254 ps
CPU time 7.77 seconds
Started Apr 28 02:10:41 PM PDT 24
Finished Apr 28 02:10:49 PM PDT 24
Peak memory 218720 kb
Host smart-4867eec5-76bb-4807-b8fe-d304b1ef326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671687479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2671687479
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2782794915
Short name T144
Test name
Test status
Simulation time 245583896 ps
CPU time 1.05 seconds
Started Apr 28 02:10:40 PM PDT 24
Finished Apr 28 02:10:42 PM PDT 24
Peak memory 218124 kb
Host smart-3f53beed-6cdf-4020-96ff-476cd561f91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782794915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2782794915
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.997190089
Short name T350
Test name
Test status
Simulation time 183330359 ps
CPU time 0.85 seconds
Started Apr 28 02:10:34 PM PDT 24
Finished Apr 28 02:10:35 PM PDT 24
Peak memory 200728 kb
Host smart-4f069fc7-f997-46c2-991e-5363873f0722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997190089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.997190089
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3024560044
Short name T95
Test name
Test status
Simulation time 1614209469 ps
CPU time 6.22 seconds
Started Apr 28 02:10:37 PM PDT 24
Finished Apr 28 02:10:43 PM PDT 24
Peak memory 201100 kb
Host smart-6a17090b-4847-416a-a1a2-54c3cfffbcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024560044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3024560044
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1821490260
Short name T143
Test name
Test status
Simulation time 141231143 ps
CPU time 1.08 seconds
Started Apr 28 02:10:40 PM PDT 24
Finished Apr 28 02:10:42 PM PDT 24
Peak memory 200880 kb
Host smart-f6e76a7c-c1e9-415d-9bc5-274757b1e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821490260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1821490260
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1108847486
Short name T231
Test name
Test status
Simulation time 199404061 ps
CPU time 1.48 seconds
Started Apr 28 02:10:39 PM PDT 24
Finished Apr 28 02:10:41 PM PDT 24
Peak memory 201072 kb
Host smart-9de49767-f079-4a40-8dd7-3de974627aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108847486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1108847486
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1980922173
Short name T225
Test name
Test status
Simulation time 5633525031 ps
CPU time 25.02 seconds
Started Apr 28 02:10:38 PM PDT 24
Finished Apr 28 02:11:04 PM PDT 24
Peak memory 201252 kb
Host smart-31ea2383-f774-4f26-ac3e-157433ed7fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980922173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1980922173
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1494199980
Short name T150
Test name
Test status
Simulation time 122125076 ps
CPU time 1.68 seconds
Started Apr 28 02:10:42 PM PDT 24
Finished Apr 28 02:10:44 PM PDT 24
Peak memory 200848 kb
Host smart-7caa9e47-4070-45ef-b5ba-bb4e72ea2ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494199980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1494199980
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2374400828
Short name T406
Test name
Test status
Simulation time 167447164 ps
CPU time 1.26 seconds
Started Apr 28 02:10:39 PM PDT 24
Finished Apr 28 02:10:41 PM PDT 24
Peak memory 200984 kb
Host smart-ce47006c-6a03-4554-becd-1898ddd60334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374400828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2374400828
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3241302174
Short name T468
Test name
Test status
Simulation time 65980847 ps
CPU time 0.76 seconds
Started Apr 28 02:10:40 PM PDT 24
Finished Apr 28 02:10:41 PM PDT 24
Peak memory 200656 kb
Host smart-58d5a9c6-06aa-4286-acc1-c7a2525135b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241302174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3241302174
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1124657250
Short name T531
Test name
Test status
Simulation time 1218506619 ps
CPU time 5.91 seconds
Started Apr 28 02:10:42 PM PDT 24
Finished Apr 28 02:10:48 PM PDT 24
Peak memory 218076 kb
Host smart-2ede9adb-d3e5-4ec7-8c91-c193b9d59c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124657250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1124657250
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2305526059
Short name T321
Test name
Test status
Simulation time 243497249 ps
CPU time 1.15 seconds
Started Apr 28 02:10:42 PM PDT 24
Finished Apr 28 02:10:44 PM PDT 24
Peak memory 218084 kb
Host smart-b5a7eb6b-599d-401a-9b6d-2c9c9296c206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305526059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2305526059
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2048445126
Short name T260
Test name
Test status
Simulation time 150998546 ps
CPU time 0.8 seconds
Started Apr 28 02:10:42 PM PDT 24
Finished Apr 28 02:10:43 PM PDT 24
Peak memory 200604 kb
Host smart-b189401c-0001-42d0-bcc7-dab778e61be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048445126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2048445126
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1232062666
Short name T194
Test name
Test status
Simulation time 1649082757 ps
CPU time 6.34 seconds
Started Apr 28 02:10:42 PM PDT 24
Finished Apr 28 02:10:49 PM PDT 24
Peak memory 201108 kb
Host smart-55b83e3a-0ed2-4ac7-b527-39e054224969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232062666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1232062666
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.4226064787
Short name T52
Test name
Test status
Simulation time 141612168 ps
CPU time 1.12 seconds
Started Apr 28 02:10:40 PM PDT 24
Finished Apr 28 02:10:42 PM PDT 24
Peak memory 200860 kb
Host smart-938d5724-a16b-4772-ac53-5a62165fdc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226064787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.4226064787
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3363502699
Short name T475
Test name
Test status
Simulation time 115903077 ps
CPU time 1.27 seconds
Started Apr 28 02:10:39 PM PDT 24
Finished Apr 28 02:10:41 PM PDT 24
Peak memory 201092 kb
Host smart-2268501b-605c-4784-83af-8ae6951ebf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363502699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3363502699
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3264534157
Short name T251
Test name
Test status
Simulation time 10363996480 ps
CPU time 34.73 seconds
Started Apr 28 02:10:41 PM PDT 24
Finished Apr 28 02:11:17 PM PDT 24
Peak memory 201152 kb
Host smart-2bcadc5c-798b-4874-a131-58408b0d5347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264534157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3264534157
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1044279862
Short name T24
Test name
Test status
Simulation time 341199069 ps
CPU time 2.15 seconds
Started Apr 28 02:10:42 PM PDT 24
Finished Apr 28 02:10:44 PM PDT 24
Peak memory 200864 kb
Host smart-b77bb783-d667-434a-a860-fa443f6583e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044279862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1044279862
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3238962556
Short name T310
Test name
Test status
Simulation time 190862182 ps
CPU time 1.21 seconds
Started Apr 28 02:10:39 PM PDT 24
Finished Apr 28 02:10:41 PM PDT 24
Peak memory 200912 kb
Host smart-3723add8-49de-4ef3-b920-0e28ce69c12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238962556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3238962556
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.841237340
Short name T438
Test name
Test status
Simulation time 77874704 ps
CPU time 0.87 seconds
Started Apr 28 02:10:45 PM PDT 24
Finished Apr 28 02:10:46 PM PDT 24
Peak memory 200732 kb
Host smart-cf1c0229-71b9-47db-bd92-f8eab73bbd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841237340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.841237340
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3913062725
Short name T395
Test name
Test status
Simulation time 1235502060 ps
CPU time 5.31 seconds
Started Apr 28 02:10:48 PM PDT 24
Finished Apr 28 02:10:54 PM PDT 24
Peak memory 218068 kb
Host smart-097b9418-8e7f-4b8a-a32b-57ec44aea2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913062725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3913062725
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.998172059
Short name T432
Test name
Test status
Simulation time 243663828 ps
CPU time 1.1 seconds
Started Apr 28 02:10:44 PM PDT 24
Finished Apr 28 02:10:45 PM PDT 24
Peak memory 218092 kb
Host smart-31008109-3f0f-4f4f-b2f6-b90312a365ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998172059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.998172059
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1865016641
Short name T14
Test name
Test status
Simulation time 174366636 ps
CPU time 0.85 seconds
Started Apr 28 02:10:41 PM PDT 24
Finished Apr 28 02:10:42 PM PDT 24
Peak memory 200664 kb
Host smart-3ca457d7-93de-434f-b147-ef664a8ed3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865016641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1865016641
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3294626538
Short name T91
Test name
Test status
Simulation time 1054424155 ps
CPU time 5.5 seconds
Started Apr 28 02:10:39 PM PDT 24
Finished Apr 28 02:10:46 PM PDT 24
Peak memory 201076 kb
Host smart-ff2d6580-3612-4349-a8d9-abbd55c15729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294626538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3294626538
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1931579528
Short name T449
Test name
Test status
Simulation time 176749470 ps
CPU time 1.19 seconds
Started Apr 28 02:10:45 PM PDT 24
Finished Apr 28 02:10:47 PM PDT 24
Peak memory 200868 kb
Host smart-ca175041-ce72-453e-ac3d-641cb3a0b03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931579528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1931579528
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3676251218
Short name T354
Test name
Test status
Simulation time 109823108 ps
CPU time 1.21 seconds
Started Apr 28 02:10:43 PM PDT 24
Finished Apr 28 02:10:44 PM PDT 24
Peak memory 201104 kb
Host smart-1454b68d-eee4-4678-bd66-a9e4132d7da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676251218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3676251218
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3323548186
Short name T148
Test name
Test status
Simulation time 9611240497 ps
CPU time 34.51 seconds
Started Apr 28 02:10:44 PM PDT 24
Finished Apr 28 02:11:20 PM PDT 24
Peak memory 201176 kb
Host smart-54286614-91d4-4bc4-bbad-22ac1471f71b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323548186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3323548186
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.586263408
Short name T458
Test name
Test status
Simulation time 376987465 ps
CPU time 2.06 seconds
Started Apr 28 02:10:47 PM PDT 24
Finished Apr 28 02:10:49 PM PDT 24
Peak memory 200880 kb
Host smart-84d6dbb8-c60a-4ef4-906b-da1038d2e5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586263408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.586263408
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2921294724
Short name T324
Test name
Test status
Simulation time 69950621 ps
CPU time 0.73 seconds
Started Apr 28 02:10:41 PM PDT 24
Finished Apr 28 02:10:43 PM PDT 24
Peak memory 200928 kb
Host smart-97ed6b71-f200-4dbc-9d21-b0faa08c6b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921294724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2921294724
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2223310474
Short name T212
Test name
Test status
Simulation time 67271634 ps
CPU time 0.77 seconds
Started Apr 28 02:10:51 PM PDT 24
Finished Apr 28 02:10:52 PM PDT 24
Peak memory 200616 kb
Host smart-9ace4804-5e85-4544-9d1d-51fc7aeca446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223310474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2223310474
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3561934145
Short name T289
Test name
Test status
Simulation time 1870761139 ps
CPU time 7.14 seconds
Started Apr 28 02:10:48 PM PDT 24
Finished Apr 28 02:10:55 PM PDT 24
Peak memory 222696 kb
Host smart-e66ff7e2-47aa-44e3-ae09-1d1e6086cbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561934145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3561934145
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3515137550
Short name T431
Test name
Test status
Simulation time 244522968 ps
CPU time 1.16 seconds
Started Apr 28 02:10:44 PM PDT 24
Finished Apr 28 02:10:46 PM PDT 24
Peak memory 218096 kb
Host smart-23923b40-58ee-4c86-9949-fb9b6e55dd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515137550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3515137550
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2390330061
Short name T247
Test name
Test status
Simulation time 143481386 ps
CPU time 0.85 seconds
Started Apr 28 02:10:45 PM PDT 24
Finished Apr 28 02:10:46 PM PDT 24
Peak memory 200668 kb
Host smart-be93a655-a345-4971-9819-673719340622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390330061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2390330061
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1323237355
Short name T331
Test name
Test status
Simulation time 969285965 ps
CPU time 4.99 seconds
Started Apr 28 02:10:48 PM PDT 24
Finished Apr 28 02:10:53 PM PDT 24
Peak memory 201108 kb
Host smart-ccf7a7b7-5509-4f50-a319-87d4cfaca642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323237355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1323237355
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3441450699
Short name T400
Test name
Test status
Simulation time 106189124 ps
CPU time 1.08 seconds
Started Apr 28 02:10:46 PM PDT 24
Finished Apr 28 02:10:47 PM PDT 24
Peak memory 200764 kb
Host smart-46bf2edf-82b5-4215-b904-b424a5a8d758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441450699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3441450699
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3618828593
Short name T263
Test name
Test status
Simulation time 194569221 ps
CPU time 1.27 seconds
Started Apr 28 02:10:44 PM PDT 24
Finished Apr 28 02:10:46 PM PDT 24
Peak memory 201112 kb
Host smart-70307029-3a2f-4287-8318-fcefc3c5e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618828593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3618828593
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.906391254
Short name T246
Test name
Test status
Simulation time 234290420 ps
CPU time 1.27 seconds
Started Apr 28 02:10:51 PM PDT 24
Finished Apr 28 02:10:53 PM PDT 24
Peak memory 200912 kb
Host smart-11fb6c92-f695-4f87-ab8b-38f491da3103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906391254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.906391254
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3025372659
Short name T337
Test name
Test status
Simulation time 128897368 ps
CPU time 1.61 seconds
Started Apr 28 02:10:44 PM PDT 24
Finished Apr 28 02:10:46 PM PDT 24
Peak memory 209116 kb
Host smart-9415951e-6a8a-466d-a979-71e9f97d65b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025372659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3025372659
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3303405346
Short name T344
Test name
Test status
Simulation time 104860704 ps
CPU time 1.05 seconds
Started Apr 28 02:10:46 PM PDT 24
Finished Apr 28 02:10:47 PM PDT 24
Peak memory 200772 kb
Host smart-de45de69-4a3a-41a2-ba78-be7a0e2c293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303405346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3303405346
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1630106109
Short name T325
Test name
Test status
Simulation time 57698117 ps
CPU time 0.8 seconds
Started Apr 28 02:10:50 PM PDT 24
Finished Apr 28 02:10:52 PM PDT 24
Peak memory 200684 kb
Host smart-03f1cd2b-6232-4579-8be4-f35dcb598e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630106109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1630106109
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.692284394
Short name T41
Test name
Test status
Simulation time 1894509989 ps
CPU time 8.46 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:11:05 PM PDT 24
Peak memory 222648 kb
Host smart-1768d41a-7f00-4e5e-8936-078452b060b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692284394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.692284394
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1435711176
Short name T192
Test name
Test status
Simulation time 244697587 ps
CPU time 1.08 seconds
Started Apr 28 02:10:50 PM PDT 24
Finished Apr 28 02:10:52 PM PDT 24
Peak memory 218276 kb
Host smart-b51a9000-d3df-4f98-95d1-da8806d9f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435711176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1435711176
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2186257672
Short name T503
Test name
Test status
Simulation time 126705429 ps
CPU time 0.79 seconds
Started Apr 28 02:10:52 PM PDT 24
Finished Apr 28 02:10:53 PM PDT 24
Peak memory 200648 kb
Host smart-8e9df10d-f075-4646-a42d-ce28a50f3407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186257672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2186257672
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1201863454
Short name T441
Test name
Test status
Simulation time 689531545 ps
CPU time 4.11 seconds
Started Apr 28 02:10:50 PM PDT 24
Finished Apr 28 02:10:55 PM PDT 24
Peak memory 201100 kb
Host smart-37534faf-1be3-4b37-b8cc-beddc7ef0a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201863454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1201863454
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1306925750
Short name T228
Test name
Test status
Simulation time 99529152 ps
CPU time 0.93 seconds
Started Apr 28 02:10:49 PM PDT 24
Finished Apr 28 02:10:50 PM PDT 24
Peak memory 200904 kb
Host smart-a35a9093-56a8-4b1f-ad63-96ce770f5dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306925750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1306925750
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2819946322
Short name T181
Test name
Test status
Simulation time 188611503 ps
CPU time 1.35 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:10:57 PM PDT 24
Peak memory 201108 kb
Host smart-83615170-cfa1-4d19-9976-e21ea43bb385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819946322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2819946322
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1803480223
Short name T152
Test name
Test status
Simulation time 817154193 ps
CPU time 4.88 seconds
Started Apr 28 02:10:55 PM PDT 24
Finished Apr 28 02:11:01 PM PDT 24
Peak memory 201080 kb
Host smart-4e1ad977-acf2-41d7-abd8-0683262239ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803480223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1803480223
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3229538916
Short name T505
Test name
Test status
Simulation time 113488402 ps
CPU time 1.41 seconds
Started Apr 28 02:10:53 PM PDT 24
Finished Apr 28 02:10:55 PM PDT 24
Peak memory 200876 kb
Host smart-cd5f9be7-9672-4021-af3d-49abd37e5c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229538916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3229538916
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.4008007423
Short name T261
Test name
Test status
Simulation time 126151859 ps
CPU time 0.93 seconds
Started Apr 28 02:10:50 PM PDT 24
Finished Apr 28 02:10:52 PM PDT 24
Peak memory 200812 kb
Host smart-8d0d5957-7e28-4eaa-bf41-ac62a139a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008007423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4008007423
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3508479169
Short name T512
Test name
Test status
Simulation time 76109830 ps
CPU time 0.78 seconds
Started Apr 28 02:10:50 PM PDT 24
Finished Apr 28 02:10:52 PM PDT 24
Peak memory 200704 kb
Host smart-30d8ff66-343d-465d-8350-e324aa5761ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508479169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3508479169
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3894271749
Short name T456
Test name
Test status
Simulation time 1226253830 ps
CPU time 5.71 seconds
Started Apr 28 02:10:49 PM PDT 24
Finished Apr 28 02:10:55 PM PDT 24
Peak memory 218052 kb
Host smart-c8c5a60a-61b8-4841-968d-e0467ee7fe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894271749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3894271749
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.731933679
Short name T355
Test name
Test status
Simulation time 245361106 ps
CPU time 1.12 seconds
Started Apr 28 02:10:52 PM PDT 24
Finished Apr 28 02:10:54 PM PDT 24
Peak memory 217928 kb
Host smart-3775fc36-4986-49b6-a561-87be260e4903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731933679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.731933679
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1243709581
Short name T21
Test name
Test status
Simulation time 150273956 ps
CPU time 0.83 seconds
Started Apr 28 02:10:56 PM PDT 24
Finished Apr 28 02:10:58 PM PDT 24
Peak memory 200604 kb
Host smart-ef99be29-5dad-4326-89c7-b4c71c87a27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243709581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1243709581
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1736320310
Short name T368
Test name
Test status
Simulation time 816207677 ps
CPU time 4.07 seconds
Started Apr 28 02:10:51 PM PDT 24
Finished Apr 28 02:10:56 PM PDT 24
Peak memory 201104 kb
Host smart-067a231e-7ecd-4b26-a02a-e565a4f9e51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736320310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1736320310
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.788586481
Short name T388
Test name
Test status
Simulation time 112036695 ps
CPU time 0.97 seconds
Started Apr 28 02:10:50 PM PDT 24
Finished Apr 28 02:10:52 PM PDT 24
Peak memory 200896 kb
Host smart-b11cfca7-3d5f-4416-b5a3-8ee048c08a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788586481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.788586481
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1798889506
Short name T224
Test name
Test status
Simulation time 122116251 ps
CPU time 1.24 seconds
Started Apr 28 02:10:52 PM PDT 24
Finished Apr 28 02:10:54 PM PDT 24
Peak memory 201020 kb
Host smart-52573edc-e07a-40ff-ae2e-19dac4cff466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798889506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1798889506
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1933306507
Short name T495
Test name
Test status
Simulation time 4558775678 ps
CPU time 19.71 seconds
Started Apr 28 02:10:52 PM PDT 24
Finished Apr 28 02:11:12 PM PDT 24
Peak memory 209052 kb
Host smart-25586e99-44bd-42be-93ae-e971edacd9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933306507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1933306507
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3239505509
Short name T301
Test name
Test status
Simulation time 512902407 ps
CPU time 2.64 seconds
Started Apr 28 02:10:53 PM PDT 24
Finished Apr 28 02:10:56 PM PDT 24
Peak memory 200880 kb
Host smart-e2b8f757-d10e-4e68-a550-591896695193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239505509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3239505509
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.4229406872
Short name T271
Test name
Test status
Simulation time 164732533 ps
CPU time 1.28 seconds
Started Apr 28 02:10:49 PM PDT 24
Finished Apr 28 02:10:50 PM PDT 24
Peak memory 201096 kb
Host smart-dec64aef-a4f7-4947-9129-7cebd5f55677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229406872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.4229406872
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.431743229
Short name T408
Test name
Test status
Simulation time 66443773 ps
CPU time 0.77 seconds
Started Apr 28 02:08:53 PM PDT 24
Finished Apr 28 02:08:55 PM PDT 24
Peak memory 200708 kb
Host smart-7280e1e8-2493-4078-89fd-2eb35fe3b33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431743229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.431743229
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2424304771
Short name T364
Test name
Test status
Simulation time 1889005440 ps
CPU time 6.88 seconds
Started Apr 28 02:08:58 PM PDT 24
Finished Apr 28 02:09:06 PM PDT 24
Peak memory 218588 kb
Host smart-1596cf54-c782-45e0-ab0c-06f08bf333e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424304771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2424304771
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1799155418
Short name T305
Test name
Test status
Simulation time 244488622 ps
CPU time 1.12 seconds
Started Apr 28 02:08:55 PM PDT 24
Finished Apr 28 02:08:56 PM PDT 24
Peak memory 218196 kb
Host smart-fe57f817-ec87-4e2b-8586-a8b99311970d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799155418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1799155418
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1589060978
Short name T10
Test name
Test status
Simulation time 171200115 ps
CPU time 0.81 seconds
Started Apr 28 02:08:53 PM PDT 24
Finished Apr 28 02:08:55 PM PDT 24
Peak memory 200696 kb
Host smart-9944c7d6-9cc1-4629-b9f9-bbd7c2d6ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589060978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1589060978
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1040019015
Short name T371
Test name
Test status
Simulation time 957040865 ps
CPU time 4.46 seconds
Started Apr 28 02:08:54 PM PDT 24
Finished Apr 28 02:08:59 PM PDT 24
Peak memory 201100 kb
Host smart-0c735314-d94b-4143-9ee8-e780e2cf8d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040019015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1040019015
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.958409005
Short name T442
Test name
Test status
Simulation time 110073099 ps
CPU time 1.06 seconds
Started Apr 28 02:08:58 PM PDT 24
Finished Apr 28 02:09:01 PM PDT 24
Peak memory 200892 kb
Host smart-cec979d1-4865-44c2-851b-38aa5809805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958409005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.958409005
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3546270853
Short name T313
Test name
Test status
Simulation time 256531217 ps
CPU time 1.48 seconds
Started Apr 28 02:08:56 PM PDT 24
Finished Apr 28 02:08:58 PM PDT 24
Peak memory 201088 kb
Host smart-95bec6fa-8d54-4b12-bef0-0d798b69bd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546270853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3546270853
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.4183965165
Short name T279
Test name
Test status
Simulation time 3798266690 ps
CPU time 18.5 seconds
Started Apr 28 02:08:53 PM PDT 24
Finished Apr 28 02:09:11 PM PDT 24
Peak memory 201224 kb
Host smart-12dd1bd7-d17c-488e-b7a5-df22642acaeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183965165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.4183965165
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2388140302
Short name T82
Test name
Test status
Simulation time 121576231 ps
CPU time 1.55 seconds
Started Apr 28 02:08:55 PM PDT 24
Finished Apr 28 02:08:57 PM PDT 24
Peak memory 209040 kb
Host smart-60d4f85e-c7bc-40a1-a696-52c4a3f0f699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388140302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2388140302
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2683390328
Short name T153
Test name
Test status
Simulation time 157815379 ps
CPU time 1.07 seconds
Started Apr 28 02:08:56 PM PDT 24
Finished Apr 28 02:08:58 PM PDT 24
Peak memory 200920 kb
Host smart-89451d42-e98b-485b-b65a-989a83767d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683390328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2683390328
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3455202772
Short name T511
Test name
Test status
Simulation time 84539983 ps
CPU time 0.83 seconds
Started Apr 28 02:08:52 PM PDT 24
Finished Apr 28 02:08:54 PM PDT 24
Peak memory 200712 kb
Host smart-0c751f02-dc06-4eb1-b690-316d1f2c4932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455202772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3455202772
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1918304913
Short name T525
Test name
Test status
Simulation time 1887287805 ps
CPU time 7.59 seconds
Started Apr 28 02:08:57 PM PDT 24
Finished Apr 28 02:09:06 PM PDT 24
Peak memory 218604 kb
Host smart-34214674-3773-473d-a6b3-9107478dc3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918304913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1918304913
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2649665356
Short name T394
Test name
Test status
Simulation time 244499500 ps
CPU time 1.04 seconds
Started Apr 28 02:08:57 PM PDT 24
Finished Apr 28 02:08:59 PM PDT 24
Peak memory 218108 kb
Host smart-72ddf310-4ec8-4459-b431-70136c04168d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649665356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2649665356
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1370608715
Short name T461
Test name
Test status
Simulation time 96114199 ps
CPU time 0.76 seconds
Started Apr 28 02:08:58 PM PDT 24
Finished Apr 28 02:09:00 PM PDT 24
Peak memory 200684 kb
Host smart-8f4b71e9-4fea-40c5-8cd6-74227f73e0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370608715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1370608715
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.308381225
Short name T381
Test name
Test status
Simulation time 1391924963 ps
CPU time 5.27 seconds
Started Apr 28 02:08:54 PM PDT 24
Finished Apr 28 02:08:59 PM PDT 24
Peak memory 201056 kb
Host smart-216536d6-4399-4f49-814d-240242fa99fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308381225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.308381225
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.199842116
Short name T482
Test name
Test status
Simulation time 177734040 ps
CPU time 1.2 seconds
Started Apr 28 02:08:53 PM PDT 24
Finished Apr 28 02:08:54 PM PDT 24
Peak memory 200904 kb
Host smart-f52541dc-4a79-4aa3-a43e-35b6cdd28c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199842116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.199842116
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3428168101
Short name T230
Test name
Test status
Simulation time 197153711 ps
CPU time 1.4 seconds
Started Apr 28 02:08:57 PM PDT 24
Finished Apr 28 02:08:59 PM PDT 24
Peak memory 201104 kb
Host smart-279e2cee-a6bf-450e-a125-ee843ccf82f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428168101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3428168101
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2073377883
Short name T306
Test name
Test status
Simulation time 1906374746 ps
CPU time 7.61 seconds
Started Apr 28 02:08:57 PM PDT 24
Finished Apr 28 02:09:06 PM PDT 24
Peak memory 209064 kb
Host smart-e09f0b6a-a387-42ec-a0e7-1cf9a9f9b034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073377883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2073377883
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1690106472
Short name T25
Test name
Test status
Simulation time 320660924 ps
CPU time 2.2 seconds
Started Apr 28 02:08:54 PM PDT 24
Finished Apr 28 02:08:56 PM PDT 24
Peak memory 200824 kb
Host smart-c7f7f17b-9f3f-4ec1-8b38-1988ef8f5fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690106472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1690106472
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3830152100
Short name T526
Test name
Test status
Simulation time 122413042 ps
CPU time 1.04 seconds
Started Apr 28 02:08:52 PM PDT 24
Finished Apr 28 02:08:54 PM PDT 24
Peak memory 200896 kb
Host smart-517dbc7c-f6bd-4c3d-9ae5-d9827bac5c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830152100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3830152100
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1283846773
Short name T293
Test name
Test status
Simulation time 80455696 ps
CPU time 0.77 seconds
Started Apr 28 02:09:01 PM PDT 24
Finished Apr 28 02:09:02 PM PDT 24
Peak memory 200700 kb
Host smart-e2a79e6b-bd97-47b4-8b6a-905c9a7283c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283846773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1283846773
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2942934705
Short name T444
Test name
Test status
Simulation time 1890500493 ps
CPU time 7.34 seconds
Started Apr 28 02:08:59 PM PDT 24
Finished Apr 28 02:09:07 PM PDT 24
Peak memory 222624 kb
Host smart-255c913c-1f3f-4d58-8af4-0096cdeb6a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942934705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2942934705
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2301515921
Short name T37
Test name
Test status
Simulation time 244985000 ps
CPU time 1.12 seconds
Started Apr 28 02:08:58 PM PDT 24
Finished Apr 28 02:09:00 PM PDT 24
Peak memory 218132 kb
Host smart-c2fc1387-85e4-4eb4-a1b5-4c6b6d7bf317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301515921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2301515921
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.4005249363
Short name T264
Test name
Test status
Simulation time 219315172 ps
CPU time 1.06 seconds
Started Apr 28 02:08:57 PM PDT 24
Finished Apr 28 02:08:59 PM PDT 24
Peak memory 200484 kb
Host smart-0a18a7bb-7a83-4909-858a-0b279a48c0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005249363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.4005249363
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.660880449
Short name T93
Test name
Test status
Simulation time 1621591296 ps
CPU time 5.99 seconds
Started Apr 28 02:09:00 PM PDT 24
Finished Apr 28 02:09:07 PM PDT 24
Peak memory 201084 kb
Host smart-8207e744-085d-4fa6-88ee-cfce78dd267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660880449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.660880449
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.767247546
Short name T376
Test name
Test status
Simulation time 150247811 ps
CPU time 1.12 seconds
Started Apr 28 02:08:59 PM PDT 24
Finished Apr 28 02:09:01 PM PDT 24
Peak memory 200884 kb
Host smart-ec3e09f8-3c9b-4c23-a413-4f3b3612631d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767247546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.767247546
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4288816927
Short name T201
Test name
Test status
Simulation time 120414355 ps
CPU time 1.15 seconds
Started Apr 28 02:08:53 PM PDT 24
Finished Apr 28 02:08:55 PM PDT 24
Peak memory 201020 kb
Host smart-b7291917-e404-4495-9000-b6a5e6fdc890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288816927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4288816927
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.389261331
Short name T422
Test name
Test status
Simulation time 4781531008 ps
CPU time 21.31 seconds
Started Apr 28 02:09:01 PM PDT 24
Finished Apr 28 02:09:23 PM PDT 24
Peak memory 201136 kb
Host smart-005d5f16-1b33-4bf3-bbcb-383e61111d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389261331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.389261331
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1210332429
Short name T180
Test name
Test status
Simulation time 340235278 ps
CPU time 2.2 seconds
Started Apr 28 02:08:57 PM PDT 24
Finished Apr 28 02:09:00 PM PDT 24
Peak memory 200904 kb
Host smart-80124b4d-bc45-423c-88e7-7d23581b7a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210332429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1210332429
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.4131383338
Short name T401
Test name
Test status
Simulation time 82164261 ps
CPU time 0.83 seconds
Started Apr 28 02:08:59 PM PDT 24
Finished Apr 28 02:09:01 PM PDT 24
Peak memory 200876 kb
Host smart-67478fbf-3a11-48da-89eb-58ca21333aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131383338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.4131383338
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.970459481
Short name T375
Test name
Test status
Simulation time 68782115 ps
CPU time 0.75 seconds
Started Apr 28 02:09:00 PM PDT 24
Finished Apr 28 02:09:02 PM PDT 24
Peak memory 200724 kb
Host smart-db3e7810-e320-427a-9183-6444f13aef30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970459481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.970459481
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.559989106
Short name T481
Test name
Test status
Simulation time 243747775 ps
CPU time 1.11 seconds
Started Apr 28 02:09:02 PM PDT 24
Finished Apr 28 02:09:03 PM PDT 24
Peak memory 218112 kb
Host smart-b32a4ae8-c6da-4fac-876b-71bf2fe374d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559989106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.559989106
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1799502217
Short name T17
Test name
Test status
Simulation time 201994250 ps
CPU time 0.95 seconds
Started Apr 28 02:09:01 PM PDT 24
Finished Apr 28 02:09:03 PM PDT 24
Peak memory 200584 kb
Host smart-405a99a4-df58-4ecc-ae82-869372f59642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799502217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1799502217
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3797889805
Short name T471
Test name
Test status
Simulation time 790546234 ps
CPU time 3.97 seconds
Started Apr 28 02:08:57 PM PDT 24
Finished Apr 28 02:09:02 PM PDT 24
Peak memory 201104 kb
Host smart-e29b0a01-bd90-4e22-8aa2-f3b0b8812eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797889805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3797889805
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2439380105
Short name T178
Test name
Test status
Simulation time 99066290 ps
CPU time 1 seconds
Started Apr 28 02:09:01 PM PDT 24
Finished Apr 28 02:09:03 PM PDT 24
Peak memory 200772 kb
Host smart-eaf23384-455d-4b43-be74-9ce0be6ffe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439380105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2439380105
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.138238846
Short name T53
Test name
Test status
Simulation time 188105873 ps
CPU time 1.26 seconds
Started Apr 28 02:08:59 PM PDT 24
Finished Apr 28 02:09:01 PM PDT 24
Peak memory 201048 kb
Host smart-1c68eba1-5b56-4c72-b125-2b8fd68183fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138238846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.138238846
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3630881926
Short name T156
Test name
Test status
Simulation time 5693736256 ps
CPU time 24.84 seconds
Started Apr 28 02:08:59 PM PDT 24
Finished Apr 28 02:09:25 PM PDT 24
Peak memory 209352 kb
Host smart-1fc17d70-5b48-44bf-9fa8-77e69a8dafcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630881926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3630881926
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3476983831
Short name T433
Test name
Test status
Simulation time 343527245 ps
CPU time 2.12 seconds
Started Apr 28 02:09:00 PM PDT 24
Finished Apr 28 02:09:03 PM PDT 24
Peak memory 200912 kb
Host smart-271b7f2c-40f6-4ebf-8c71-66fe87ee2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476983831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3476983831
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2423132124
Short name T496
Test name
Test status
Simulation time 203695105 ps
CPU time 1.4 seconds
Started Apr 28 02:09:00 PM PDT 24
Finished Apr 28 02:09:02 PM PDT 24
Peak memory 200876 kb
Host smart-ff445b7c-1694-45b8-9a5f-cc49a02271a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423132124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2423132124
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2769098171
Short name T298
Test name
Test status
Simulation time 61200237 ps
CPU time 0.77 seconds
Started Apr 28 02:09:06 PM PDT 24
Finished Apr 28 02:09:07 PM PDT 24
Peak memory 200704 kb
Host smart-a2e262d7-754e-49d7-b3b0-fa53914830b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769098171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2769098171
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1595832382
Short name T339
Test name
Test status
Simulation time 1232923090 ps
CPU time 5.67 seconds
Started Apr 28 02:09:10 PM PDT 24
Finished Apr 28 02:09:16 PM PDT 24
Peak memory 218000 kb
Host smart-626364ef-9b52-496f-b3f4-b80e89b7d6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595832382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1595832382
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1797312174
Short name T120
Test name
Test status
Simulation time 245577865 ps
CPU time 1.03 seconds
Started Apr 28 02:09:03 PM PDT 24
Finished Apr 28 02:09:05 PM PDT 24
Peak memory 218268 kb
Host smart-ce2a9df4-0239-4371-a450-2c51ae57bb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797312174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1797312174
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1925752819
Short name T237
Test name
Test status
Simulation time 199901636 ps
CPU time 0.89 seconds
Started Apr 28 02:09:00 PM PDT 24
Finished Apr 28 02:09:01 PM PDT 24
Peak memory 200656 kb
Host smart-21535986-1a1d-4f1f-8529-e90c844f73d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925752819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1925752819
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1398478031
Short name T493
Test name
Test status
Simulation time 1381546126 ps
CPU time 5.06 seconds
Started Apr 28 02:08:58 PM PDT 24
Finished Apr 28 02:09:04 PM PDT 24
Peak memory 201100 kb
Host smart-0bbbb4f4-be5e-4176-a42e-18996846744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398478031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1398478031
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1972755249
Short name T397
Test name
Test status
Simulation time 111029855 ps
CPU time 1.06 seconds
Started Apr 28 02:09:06 PM PDT 24
Finished Apr 28 02:09:07 PM PDT 24
Peak memory 200848 kb
Host smart-1f13bdca-0be0-4ee4-9d4c-783c6c46da23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972755249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1972755249
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3512112464
Short name T195
Test name
Test status
Simulation time 115165683 ps
CPU time 1.15 seconds
Started Apr 28 02:08:59 PM PDT 24
Finished Apr 28 02:09:01 PM PDT 24
Peak memory 200980 kb
Host smart-e7e2022d-c921-452e-a7fb-4ccdc63ff91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512112464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3512112464
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2275207567
Short name T410
Test name
Test status
Simulation time 1708127622 ps
CPU time 6.88 seconds
Started Apr 28 02:09:03 PM PDT 24
Finished Apr 28 02:09:10 PM PDT 24
Peak memory 201116 kb
Host smart-3b61bbab-c39f-436d-827a-9a4ab9ab93b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275207567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2275207567
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2898221314
Short name T318
Test name
Test status
Simulation time 154125028 ps
CPU time 1.78 seconds
Started Apr 28 02:09:03 PM PDT 24
Finished Apr 28 02:09:06 PM PDT 24
Peak memory 200804 kb
Host smart-46ab3b23-414f-40e9-a07c-321ccc45bfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898221314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2898221314
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3961497038
Short name T74
Test name
Test status
Simulation time 83191173 ps
CPU time 0.85 seconds
Started Apr 28 02:09:06 PM PDT 24
Finished Apr 28 02:09:08 PM PDT 24
Peak memory 200876 kb
Host smart-fa612eb9-8137-49a8-ae88-65c7bcb180ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961497038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3961497038
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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