Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7980

1

T5

74

T7

6

T11

14

auto[1]

10990

1

T2

4

T3

4

T5

58

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5887	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6454	1			T1	1		T2	2		T3	2
reset_info_cp[2]	2892	1			T2	1		T3	1		T5	18
reset_info_cp[4]	3809	1			T2	1		T3	1		T5	32
reset_info_cp[8]	102	1			T5	1		T7	2		T11	1
reset_info_cp[16]	113	1			T5	1		T13	2		T15	1
reset_info_cp[32]	103	1			T3	1		T5	1		T11	3
reset_info_cp[64]	135	1			T5	2		T7	1		T11	1
reset_info_cp[128]	95	1			T15	1		T44	1		T46	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3095	1			T5	26		T11	14		T12	8
reset_info_cp[1]	auto[1]	2739	1			T2	1		T3	1		T5	12
reset_info_cp[2]	auto[0]	864	1			T5	7		T12	3		T13	19
reset_info_cp[2]	auto[1]	2028	1			T2	1		T3	1		T5	11
reset_info_cp[4]	auto[0]	1331	1			T5	14		T12	5		T13	19
reset_info_cp[4]	auto[1]	2478	1			T2	1		T3	1		T5	18
reset_info_cp[8]	auto[0]	49	1			T7	2		T52	1		T136	1
reset_info_cp[8]	auto[1]	53	1			T5	1		T11	1		T15	1
reset_info_cp[16]	auto[0]	46	1			T13	1		T88	1		T106	1
reset_info_cp[16]	auto[1]	67	1			T5	1		T13	1		T15	1
reset_info_cp[32]	auto[0]	43	1			T5	1		T64	1		T53	1
reset_info_cp[32]	auto[1]	60	1			T3	1		T11	3		T52	1
reset_info_cp[64]	auto[0]	52	1			T5	1		T7	1		T52	1
reset_info_cp[64]	auto[1]	83	1			T5	1		T11	1		T13	1
reset_info_cp[128]	auto[0]	42	1			T46	1		T27	1		T109	1
reset_info_cp[128]	auto[1]	53	1			T15	1		T44	1		T52	1