Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2197832477 Apr 30 01:05:36 PM PDT 24 Apr 30 01:05:38 PM PDT 24 247444518 ps
T541 /workspace/coverage/default/49.rstmgr_sw_rst.743232545 Apr 30 01:11:01 PM PDT 24 Apr 30 01:11:03 PM PDT 24 146313904 ps
T542 /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2464837819 Apr 30 01:10:16 PM PDT 24 Apr 30 01:10:18 PM PDT 24 143955751 ps
T543 /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2061773341 Apr 30 01:09:17 PM PDT 24 Apr 30 01:09:18 PM PDT 24 243999682 ps
T544 /workspace/coverage/default/46.rstmgr_por_stretcher.2914244071 Apr 30 01:10:39 PM PDT 24 Apr 30 01:10:40 PM PDT 24 187399438 ps
T68 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4174170881 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:47 PM PDT 24 896653626 ps
T69 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.214063345 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:46 PM PDT 24 77652910 ps
T70 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.396811744 Apr 30 02:08:51 PM PDT 24 Apr 30 02:08:54 PM PDT 24 768462165 ps
T112 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4164946816 Apr 30 02:08:47 PM PDT 24 Apr 30 02:08:48 PM PDT 24 85207510 ps
T71 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.451992263 Apr 30 02:09:00 PM PDT 24 Apr 30 02:09:03 PM PDT 24 538001735 ps
T113 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1427519340 Apr 30 02:09:02 PM PDT 24 Apr 30 02:09:04 PM PDT 24 221125101 ps
T139 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3885485820 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:46 PM PDT 24 91156340 ps
T114 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1962722048 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:45 PM PDT 24 64524804 ps
T72 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.916805689 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:45 PM PDT 24 191740056 ps
T115 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2851916423 Apr 30 02:08:46 PM PDT 24 Apr 30 02:08:47 PM PDT 24 121313722 ps
T97 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.536688524 Apr 30 02:08:47 PM PDT 24 Apr 30 02:08:50 PM PDT 24 423956277 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3373412717 Apr 30 02:08:45 PM PDT 24 Apr 30 02:08:46 PM PDT 24 75079020 ps
T73 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4152687874 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:45 PM PDT 24 89118690 ps
T116 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2330703896 Apr 30 02:09:06 PM PDT 24 Apr 30 02:09:07 PM PDT 24 135041807 ps
T117 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2214038342 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:52 PM PDT 24 225495739 ps
T74 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1713566521 Apr 30 02:08:53 PM PDT 24 Apr 30 02:08:56 PM PDT 24 186572107 ps
T118 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1680430211 Apr 30 02:08:42 PM PDT 24 Apr 30 02:08:44 PM PDT 24 60199184 ps
T119 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1274002873 Apr 30 02:08:52 PM PDT 24 Apr 30 02:08:54 PM PDT 24 139480409 ps
T120 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1344276619 Apr 30 02:09:03 PM PDT 24 Apr 30 02:09:04 PM PDT 24 88647278 ps
T98 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2617846345 Apr 30 02:08:52 PM PDT 24 Apr 30 02:08:54 PM PDT 24 113147166 ps
T99 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1460246334 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:46 PM PDT 24 196564597 ps
T121 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1748645181 Apr 30 02:08:53 PM PDT 24 Apr 30 02:08:54 PM PDT 24 68374449 ps
T100 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2625057266 Apr 30 02:08:53 PM PDT 24 Apr 30 02:08:55 PM PDT 24 104706952 ps
T101 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.226867503 Apr 30 02:08:53 PM PDT 24 Apr 30 02:08:55 PM PDT 24 214403351 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2386155579 Apr 30 02:08:45 PM PDT 24 Apr 30 02:08:46 PM PDT 24 72703439 ps
T102 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3776880097 Apr 30 02:08:56 PM PDT 24 Apr 30 02:08:58 PM PDT 24 118490890 ps
T547 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.648705134 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:45 PM PDT 24 105780676 ps
T548 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.401583247 Apr 30 02:09:06 PM PDT 24 Apr 30 02:09:07 PM PDT 24 65946636 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3334505766 Apr 30 02:08:49 PM PDT 24 Apr 30 02:08:51 PM PDT 24 85665045 ps
T103 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.248341122 Apr 30 02:08:47 PM PDT 24 Apr 30 02:08:49 PM PDT 24 138156211 ps
T550 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2870841826 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:45 PM PDT 24 130738205 ps
T132 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1275150992 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:54 PM PDT 24 959575476 ps
T104 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2267837218 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:45 PM PDT 24 265162605 ps
T122 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3846767673 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:54 PM PDT 24 802989197 ps
T107 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2239187190 Apr 30 02:08:35 PM PDT 24 Apr 30 02:08:37 PM PDT 24 204369786 ps
T124 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1617682668 Apr 30 02:08:37 PM PDT 24 Apr 30 02:08:41 PM PDT 24 904413640 ps
T129 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2709852861 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:46 PM PDT 24 108113614 ps
T131 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3309765505 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:52 PM PDT 24 121818997 ps
T126 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1506735132 Apr 30 02:08:47 PM PDT 24 Apr 30 02:08:51 PM PDT 24 419690867 ps
T551 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2371469917 Apr 30 02:08:51 PM PDT 24 Apr 30 02:08:53 PM PDT 24 196285297 ps
T552 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3162990555 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:45 PM PDT 24 75115876 ps
T130 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3991777021 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:54 PM PDT 24 522904128 ps
T553 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2045161296 Apr 30 02:08:46 PM PDT 24 Apr 30 02:08:49 PM PDT 24 182986022 ps
T554 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1340593417 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:47 PM PDT 24 495085949 ps
T128 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3827843325 Apr 30 02:08:51 PM PDT 24 Apr 30 02:08:53 PM PDT 24 431607955 ps
T555 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1169702577 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:45 PM PDT 24 80530212 ps
T556 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3845323046 Apr 30 02:08:52 PM PDT 24 Apr 30 02:08:54 PM PDT 24 73999694 ps
T557 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.788737834 Apr 30 02:08:37 PM PDT 24 Apr 30 02:08:39 PM PDT 24 207990977 ps
T123 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.664518348 Apr 30 02:08:48 PM PDT 24 Apr 30 02:08:51 PM PDT 24 964122411 ps
T558 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1094995743 Apr 30 02:08:56 PM PDT 24 Apr 30 02:08:58 PM PDT 24 224119288 ps
T559 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.868651820 Apr 30 02:08:51 PM PDT 24 Apr 30 02:08:53 PM PDT 24 215957218 ps
T560 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.539255476 Apr 30 02:09:02 PM PDT 24 Apr 30 02:09:05 PM PDT 24 459831910 ps
T561 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.208962291 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:44 PM PDT 24 189901221 ps
T562 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2728837849 Apr 30 02:08:37 PM PDT 24 Apr 30 02:08:40 PM PDT 24 465112681 ps
T563 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3546087334 Apr 30 02:08:37 PM PDT 24 Apr 30 02:08:38 PM PDT 24 104074974 ps
T127 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3028722380 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:47 PM PDT 24 493291424 ps
T564 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3187291166 Apr 30 02:08:51 PM PDT 24 Apr 30 02:08:54 PM PDT 24 185665768 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1282888052 Apr 30 02:08:38 PM PDT 24 Apr 30 02:08:40 PM PDT 24 123147452 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2586359082 Apr 30 02:08:36 PM PDT 24 Apr 30 02:08:38 PM PDT 24 256401720 ps
T567 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.964378512 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:46 PM PDT 24 89313853 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1977350056 Apr 30 02:08:51 PM PDT 24 Apr 30 02:08:53 PM PDT 24 166901921 ps
T569 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1934208611 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:44 PM PDT 24 86818954 ps
T570 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.13763448 Apr 30 02:08:39 PM PDT 24 Apr 30 02:08:44 PM PDT 24 787655002 ps
T571 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3001207406 Apr 30 02:08:49 PM PDT 24 Apr 30 02:08:51 PM PDT 24 139914413 ps
T572 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.4149801118 Apr 30 02:08:55 PM PDT 24 Apr 30 02:08:57 PM PDT 24 433407567 ps
T573 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1433348171 Apr 30 02:08:37 PM PDT 24 Apr 30 02:08:41 PM PDT 24 950863636 ps
T574 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.752487096 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:52 PM PDT 24 66735002 ps
T138 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1181989482 Apr 30 02:08:47 PM PDT 24 Apr 30 02:08:50 PM PDT 24 470029811 ps
T575 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.769669747 Apr 30 02:08:56 PM PDT 24 Apr 30 02:08:57 PM PDT 24 60691596 ps
T576 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1970183895 Apr 30 02:08:36 PM PDT 24 Apr 30 02:08:41 PM PDT 24 808362616 ps
T577 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3871190627 Apr 30 02:08:47 PM PDT 24 Apr 30 02:08:49 PM PDT 24 127981467 ps
T578 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2012095082 Apr 30 02:08:51 PM PDT 24 Apr 30 02:08:53 PM PDT 24 134989223 ps
T579 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2933927051 Apr 30 02:08:39 PM PDT 24 Apr 30 02:08:46 PM PDT 24 488414367 ps
T580 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.68713668 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:52 PM PDT 24 225789802 ps
T581 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4094113680 Apr 30 02:09:06 PM PDT 24 Apr 30 02:09:08 PM PDT 24 178328146 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2078768190 Apr 30 02:08:38 PM PDT 24 Apr 30 02:08:40 PM PDT 24 94451564 ps
T583 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3969047150 Apr 30 02:08:48 PM PDT 24 Apr 30 02:08:51 PM PDT 24 278945264 ps
T584 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2226183677 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:46 PM PDT 24 195152735 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3276418959 Apr 30 02:08:49 PM PDT 24 Apr 30 02:08:50 PM PDT 24 90488724 ps
T586 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1770108180 Apr 30 02:08:36 PM PDT 24 Apr 30 02:08:39 PM PDT 24 462918032 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3963062745 Apr 30 02:08:42 PM PDT 24 Apr 30 02:08:47 PM PDT 24 799293319 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3213687083 Apr 30 02:08:36 PM PDT 24 Apr 30 02:08:39 PM PDT 24 493402863 ps
T589 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3891480790 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:44 PM PDT 24 129034493 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1138286724 Apr 30 02:08:41 PM PDT 24 Apr 30 02:08:44 PM PDT 24 147370907 ps
T591 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2140252914 Apr 30 02:08:52 PM PDT 24 Apr 30 02:08:54 PM PDT 24 161290081 ps
T592 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.820330647 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:52 PM PDT 24 137023894 ps
T125 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1928256166 Apr 30 02:08:52 PM PDT 24 Apr 30 02:08:56 PM PDT 24 935699261 ps
T593 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2984905932 Apr 30 02:08:41 PM PDT 24 Apr 30 02:08:42 PM PDT 24 199359205 ps
T594 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2941489717 Apr 30 02:09:04 PM PDT 24 Apr 30 02:09:06 PM PDT 24 197950402 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2536658361 Apr 30 02:08:34 PM PDT 24 Apr 30 02:08:38 PM PDT 24 222195569 ps
T596 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1350630683 Apr 30 02:09:00 PM PDT 24 Apr 30 02:09:02 PM PDT 24 211864930 ps
T597 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3822465392 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:51 PM PDT 24 106071695 ps
T598 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.633872116 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:46 PM PDT 24 497198345 ps
T599 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3474726663 Apr 30 02:09:03 PM PDT 24 Apr 30 02:09:05 PM PDT 24 110403134 ps
T600 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1761696098 Apr 30 02:09:02 PM PDT 24 Apr 30 02:09:05 PM PDT 24 785791528 ps
T601 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1422805450 Apr 30 02:08:48 PM PDT 24 Apr 30 02:08:50 PM PDT 24 166201000 ps
T602 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3700163532 Apr 30 02:08:42 PM PDT 24 Apr 30 02:08:43 PM PDT 24 92316845 ps
T603 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2817528024 Apr 30 02:08:39 PM PDT 24 Apr 30 02:08:41 PM PDT 24 208454311 ps
T604 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.620758617 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:54 PM PDT 24 793743520 ps
T605 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1423365960 Apr 30 02:08:48 PM PDT 24 Apr 30 02:08:50 PM PDT 24 64816646 ps
T606 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2281726285 Apr 30 02:08:41 PM PDT 24 Apr 30 02:08:45 PM PDT 24 275985832 ps
T607 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.760555514 Apr 30 02:08:37 PM PDT 24 Apr 30 02:08:39 PM PDT 24 120605848 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.436298412 Apr 30 02:08:42 PM PDT 24 Apr 30 02:08:44 PM PDT 24 160115070 ps
T609 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2330608294 Apr 30 02:08:44 PM PDT 24 Apr 30 02:08:45 PM PDT 24 85862932 ps
T610 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2496061199 Apr 30 02:08:57 PM PDT 24 Apr 30 02:08:58 PM PDT 24 55955771 ps
T611 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3525044668 Apr 30 02:08:51 PM PDT 24 Apr 30 02:08:53 PM PDT 24 276276196 ps
T612 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3903400428 Apr 30 02:08:50 PM PDT 24 Apr 30 02:08:52 PM PDT 24 139110463 ps
T613 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1608501237 Apr 30 02:08:56 PM PDT 24 Apr 30 02:09:00 PM PDT 24 896199523 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4212323489 Apr 30 02:08:41 PM PDT 24 Apr 30 02:08:42 PM PDT 24 79330313 ps
T615 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2695774011 Apr 30 02:08:39 PM PDT 24 Apr 30 02:08:40 PM PDT 24 101367127 ps
T616 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3095425409 Apr 30 02:08:49 PM PDT 24 Apr 30 02:08:51 PM PDT 24 134738484 ps
T617 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1762266040 Apr 30 02:08:48 PM PDT 24 Apr 30 02:08:49 PM PDT 24 73194137 ps
T618 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2086367579 Apr 30 02:08:43 PM PDT 24 Apr 30 02:08:45 PM PDT 24 127193000 ps
T619 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2784234523 Apr 30 02:08:47 PM PDT 24 Apr 30 02:08:50 PM PDT 24 202581510 ps
T620 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1379116360 Apr 30 02:08:45 PM PDT 24 Apr 30 02:08:46 PM PDT 24 92290706 ps

Test location /workspace/coverage/default/26.rstmgr_stress_all.3110885868
Short name T5
Test name
Test status
Simulation time 4836744236 ps
CPU time 17.27 seconds
Started Apr 30 01:09:05 PM PDT 24
Finished Apr 30 01:09:23 PM PDT 24
Peak memory 209352 kb
Host smart-19311422-fae6-4008-a5e1-2a52e9692550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110885868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3110885868
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.94870445
Short name T10
Test name
Test status
Simulation time 448861985 ps
CPU time 2.57 seconds
Started Apr 30 01:08:12 PM PDT 24
Finished Apr 30 01:08:15 PM PDT 24
Peak memory 200848 kb
Host smart-e1ca1f6d-ad71-4fc2-9b6d-1ab2ade961c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94870445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.94870445
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.396811744
Short name T70
Test name
Test status
Simulation time 768462165 ps
CPU time 3.1 seconds
Started Apr 30 02:08:51 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 201124 kb
Host smart-2135f308-c76e-4f52-a51a-e8501a0821fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396811744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.396811744
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2892223636
Short name T75
Test name
Test status
Simulation time 16843536833 ps
CPU time 23.79 seconds
Started Apr 30 01:05:56 PM PDT 24
Finished Apr 30 01:06:20 PM PDT 24
Peak memory 218736 kb
Host smart-9bb59a4c-7115-4029-86f1-ed4f571d9893
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892223636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2892223636
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2431979053
Short name T29
Test name
Test status
Simulation time 1224502597 ps
CPU time 5.74 seconds
Started Apr 30 01:08:20 PM PDT 24
Finished Apr 30 01:08:26 PM PDT 24
Peak memory 217980 kb
Host smart-5932dd2f-4c38-43c1-aa34-2337020ecd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431979053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2431979053
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1713566521
Short name T74
Test name
Test status
Simulation time 186572107 ps
CPU time 2.52 seconds
Started Apr 30 02:08:53 PM PDT 24
Finished Apr 30 02:08:56 PM PDT 24
Peak memory 201136 kb
Host smart-4eac0140-2b04-460e-94af-b69cd4776e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713566521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1713566521
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1980511216
Short name T109
Test name
Test status
Simulation time 9037978475 ps
CPU time 32.48 seconds
Started Apr 30 01:07:47 PM PDT 24
Finished Apr 30 01:08:20 PM PDT 24
Peak memory 201148 kb
Host smart-e151a13e-f889-4b61-8029-b910e2199ea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980511216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1980511216
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1923997481
Short name T44
Test name
Test status
Simulation time 168622387 ps
CPU time 1.16 seconds
Started Apr 30 01:05:30 PM PDT 24
Finished Apr 30 01:05:31 PM PDT 24
Peak memory 200824 kb
Host smart-07c93620-c0ac-44d5-bd25-73fae08fb765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923997481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1923997481
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.970069323
Short name T35
Test name
Test status
Simulation time 92865512 ps
CPU time 0.84 seconds
Started Apr 30 01:07:34 PM PDT 24
Finished Apr 30 01:07:35 PM PDT 24
Peak memory 200636 kb
Host smart-63dc4a59-f089-43f5-a36e-ec9ab96b824f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970069323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.970069323
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.89287070
Short name T15
Test name
Test status
Simulation time 1227962673 ps
CPU time 5.77 seconds
Started Apr 30 01:08:56 PM PDT 24
Finished Apr 30 01:09:03 PM PDT 24
Peak memory 217552 kb
Host smart-3a8bc860-76d6-4bac-9588-dc4ecd6afe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89287070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.89287070
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4174170881
Short name T68
Test name
Test status
Simulation time 896653626 ps
CPU time 3.06 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:47 PM PDT 24
Peak memory 201048 kb
Host smart-a4538474-33b8-4c6e-b629-f4b7227df095
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174170881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.4174170881
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2809978475
Short name T86
Test name
Test status
Simulation time 231456948 ps
CPU time 1.4 seconds
Started Apr 30 01:08:17 PM PDT 24
Finished Apr 30 01:08:19 PM PDT 24
Peak memory 200780 kb
Host smart-bb2faa70-0668-4a77-8aed-92f8a1e1eb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809978475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2809978475
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.664518348
Short name T123
Test name
Test status
Simulation time 964122411 ps
CPU time 3.15 seconds
Started Apr 30 02:08:48 PM PDT 24
Finished Apr 30 02:08:51 PM PDT 24
Peak memory 201128 kb
Host smart-9992bb39-1ce8-4174-b877-751baf066b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664518348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
664518348
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3490057688
Short name T40
Test name
Test status
Simulation time 2176130131 ps
CPU time 7.15 seconds
Started Apr 30 01:10:10 PM PDT 24
Finished Apr 30 01:10:17 PM PDT 24
Peak memory 217916 kb
Host smart-3d4c0926-4d5a-45f4-86d4-a22e0a0ca621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490057688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3490057688
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3776880097
Short name T102
Test name
Test status
Simulation time 118490890 ps
CPU time 1.54 seconds
Started Apr 30 02:08:56 PM PDT 24
Finished Apr 30 02:08:58 PM PDT 24
Peak memory 209280 kb
Host smart-c0b200ee-5f2e-4a69-aa3a-63ad409792ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776880097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3776880097
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1962722048
Short name T114
Test name
Test status
Simulation time 64524804 ps
CPU time 0.84 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 200832 kb
Host smart-a3124766-9b34-492b-bc56-c5df097f3eab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962722048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1962722048
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1783344828
Short name T13
Test name
Test status
Simulation time 7351874852 ps
CPU time 23.81 seconds
Started Apr 30 01:05:17 PM PDT 24
Finished Apr 30 01:05:41 PM PDT 24
Peak memory 201192 kb
Host smart-56e38afa-16d4-4a02-89a2-6f7a7eac5ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783344828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1783344828
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1144742227
Short name T24
Test name
Test status
Simulation time 207448148 ps
CPU time 0.91 seconds
Started Apr 30 01:05:32 PM PDT 24
Finished Apr 30 01:05:33 PM PDT 24
Peak memory 200612 kb
Host smart-a72ba46d-2d64-44c6-983b-8996de7b09e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144742227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1144742227
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3827843325
Short name T128
Test name
Test status
Simulation time 431607955 ps
CPU time 1.68 seconds
Started Apr 30 02:08:51 PM PDT 24
Finished Apr 30 02:08:53 PM PDT 24
Peak memory 201164 kb
Host smart-c337aacf-07c8-4e52-80b5-649084ac24e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827843325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3827843325
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1928256166
Short name T125
Test name
Test status
Simulation time 935699261 ps
CPU time 3.29 seconds
Started Apr 30 02:08:52 PM PDT 24
Finished Apr 30 02:08:56 PM PDT 24
Peak memory 201160 kb
Host smart-6e8c075c-d71c-4571-bde2-5c7fe4f70e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928256166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1928256166
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.4243985917
Short name T334
Test name
Test status
Simulation time 6459914733 ps
CPU time 27.44 seconds
Started Apr 30 01:07:40 PM PDT 24
Finished Apr 30 01:08:08 PM PDT 24
Peak memory 210052 kb
Host smart-59ce488c-8d37-4f39-9061-92790cad8f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243985917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.4243985917
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2728837849
Short name T562
Test name
Test status
Simulation time 465112681 ps
CPU time 2.88 seconds
Started Apr 30 02:08:37 PM PDT 24
Finished Apr 30 02:08:40 PM PDT 24
Peak memory 209268 kb
Host smart-ee64df02-6fc8-4506-b022-3799d7619881
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728837849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
728837849
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1970183895
Short name T576
Test name
Test status
Simulation time 808362616 ps
CPU time 4.72 seconds
Started Apr 30 02:08:36 PM PDT 24
Finished Apr 30 02:08:41 PM PDT 24
Peak memory 201080 kb
Host smart-75646525-3824-4d6d-83b4-0a30a03e5acd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970183895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
970183895
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1379116360
Short name T620
Test name
Test status
Simulation time 92290706 ps
CPU time 0.8 seconds
Started Apr 30 02:08:45 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 200840 kb
Host smart-0398c8ba-04b4-4e29-bb43-67926c7e22d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379116360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
379116360
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4152687874
Short name T73
Test name
Test status
Simulation time 89118690 ps
CPU time 0.91 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 201028 kb
Host smart-af7c714c-0a40-4753-a0ee-77c87b083714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152687874 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.4152687874
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2330608294
Short name T609
Test name
Test status
Simulation time 85862932 ps
CPU time 0.87 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 200912 kb
Host smart-382c4c6a-0da8-49c3-b298-056311b18a55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330608294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2330608294
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3001207406
Short name T571
Test name
Test status
Simulation time 139914413 ps
CPU time 1.09 seconds
Started Apr 30 02:08:49 PM PDT 24
Finished Apr 30 02:08:51 PM PDT 24
Peak memory 200948 kb
Host smart-ba5a760c-d9ae-415f-be14-a57b95a5b412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001207406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3001207406
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2536658361
Short name T595
Test name
Test status
Simulation time 222195569 ps
CPU time 3.26 seconds
Started Apr 30 02:08:34 PM PDT 24
Finished Apr 30 02:08:38 PM PDT 24
Peak memory 217388 kb
Host smart-d1f729f7-97e9-427b-8a80-41d3ac9d2690
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536658361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2536658361
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1275150992
Short name T132
Test name
Test status
Simulation time 959575476 ps
CPU time 3.07 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 200968 kb
Host smart-2e1a56ca-0215-45e7-be5b-23e481288f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275150992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1275150992
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.788737834
Short name T557
Test name
Test status
Simulation time 207990977 ps
CPU time 1.75 seconds
Started Apr 30 02:08:37 PM PDT 24
Finished Apr 30 02:08:39 PM PDT 24
Peak memory 201084 kb
Host smart-7976f70f-604a-40a5-9061-3981489155f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788737834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.788737834
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.13763448
Short name T570
Test name
Test status
Simulation time 787655002 ps
CPU time 4.54 seconds
Started Apr 30 02:08:39 PM PDT 24
Finished Apr 30 02:08:44 PM PDT 24
Peak memory 201100 kb
Host smart-7058734c-b7a2-4303-8333-0f6f11224cd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13763448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.13763448
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2695774011
Short name T615
Test name
Test status
Simulation time 101367127 ps
CPU time 0.84 seconds
Started Apr 30 02:08:39 PM PDT 24
Finished Apr 30 02:08:40 PM PDT 24
Peak memory 200776 kb
Host smart-b3ec87f6-319d-466b-8c89-349e78cb4ca2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695774011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
695774011
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1460246334
Short name T99
Test name
Test status
Simulation time 196564597 ps
CPU time 1.34 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 209164 kb
Host smart-e48e351c-1b8d-4117-ac1a-69d619af42d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460246334 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1460246334
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1762266040
Short name T617
Test name
Test status
Simulation time 73194137 ps
CPU time 0.81 seconds
Started Apr 30 02:08:48 PM PDT 24
Finished Apr 30 02:08:49 PM PDT 24
Peak memory 200712 kb
Host smart-54d8f11b-08ac-402f-befc-62ac616c25a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762266040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1762266040
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2870841826
Short name T550
Test name
Test status
Simulation time 130738205 ps
CPU time 1.13 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 200932 kb
Host smart-1ca32c60-4b11-4056-aa28-6e1ec7f557c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870841826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2870841826
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1770108180
Short name T586
Test name
Test status
Simulation time 462918032 ps
CPU time 2.87 seconds
Started Apr 30 02:08:36 PM PDT 24
Finished Apr 30 02:08:39 PM PDT 24
Peak memory 217444 kb
Host smart-22324aae-3c62-466b-8924-473e85a3c631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770108180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1770108180
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3213687083
Short name T588
Test name
Test status
Simulation time 493402863 ps
CPU time 1.93 seconds
Started Apr 30 02:08:36 PM PDT 24
Finished Apr 30 02:08:39 PM PDT 24
Peak memory 201088 kb
Host smart-11a7a607-bfdc-41f4-a4bb-180c636145be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213687083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3213687083
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2617846345
Short name T98
Test name
Test status
Simulation time 113147166 ps
CPU time 0.94 seconds
Started Apr 30 02:08:52 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 200868 kb
Host smart-cc5c5d3e-2620-40d8-bef6-e018f51a7625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617846345 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2617846345
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3845323046
Short name T556
Test name
Test status
Simulation time 73999694 ps
CPU time 0.85 seconds
Started Apr 30 02:08:52 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 200608 kb
Host smart-64fdadf7-791e-4a4a-b3e6-4b156b9556f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845323046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3845323046
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2086367579
Short name T618
Test name
Test status
Simulation time 127193000 ps
CPU time 1.03 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 200892 kb
Host smart-f70bfc27-c6d0-4f2d-84f5-db972b69fb6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086367579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2086367579
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3525044668
Short name T611
Test name
Test status
Simulation time 276276196 ps
CPU time 2.18 seconds
Started Apr 30 02:08:51 PM PDT 24
Finished Apr 30 02:08:53 PM PDT 24
Peak memory 209228 kb
Host smart-45569475-f224-424c-9fcc-661ad4d1c436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525044668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3525044668
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3028722380
Short name T127
Test name
Test status
Simulation time 493291424 ps
CPU time 2.04 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:47 PM PDT 24
Peak memory 201184 kb
Host smart-fd4ebbbf-5318-4aa9-8464-7e933f063a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028722380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3028722380
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2371469917
Short name T551
Test name
Test status
Simulation time 196285297 ps
CPU time 1.41 seconds
Started Apr 30 02:08:51 PM PDT 24
Finished Apr 30 02:08:53 PM PDT 24
Peak memory 209432 kb
Host smart-b748db05-be6d-4406-8816-408ff215c598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371469917 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2371469917
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3334505766
Short name T549
Test name
Test status
Simulation time 85665045 ps
CPU time 1 seconds
Started Apr 30 02:08:49 PM PDT 24
Finished Apr 30 02:08:51 PM PDT 24
Peak memory 200928 kb
Host smart-4db01d19-2b6b-4d0f-8ff0-36c6cd7ab603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334505766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3334505766
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2784234523
Short name T619
Test name
Test status
Simulation time 202581510 ps
CPU time 2.89 seconds
Started Apr 30 02:08:47 PM PDT 24
Finished Apr 30 02:08:50 PM PDT 24
Peak memory 217432 kb
Host smart-50f3aecc-ab04-4daf-a055-9f67004310f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784234523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2784234523
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.436298412
Short name T608
Test name
Test status
Simulation time 160115070 ps
CPU time 1.53 seconds
Started Apr 30 02:08:42 PM PDT 24
Finished Apr 30 02:08:44 PM PDT 24
Peak memory 209332 kb
Host smart-f996798f-f8c8-4092-bc6e-38585574adaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436298412 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.436298412
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3885485820
Short name T139
Test name
Test status
Simulation time 91156340 ps
CPU time 1 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 200832 kb
Host smart-25000d76-66d4-46db-85d3-792e639dac23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885485820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3885485820
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.68713668
Short name T580
Test name
Test status
Simulation time 225789802 ps
CPU time 1.54 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:52 PM PDT 24
Peak memory 201144 kb
Host smart-fdf8c25b-2aea-48fd-a271-f37e29c11782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68713668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sam
e_csr_outstanding.68713668
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.916805689
Short name T72
Test name
Test status
Simulation time 191740056 ps
CPU time 1.36 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 209144 kb
Host smart-4d410d08-6996-44e4-a5e4-3d4224dbe95a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916805689 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.916805689
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.752487096
Short name T574
Test name
Test status
Simulation time 66735002 ps
CPU time 0.77 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:52 PM PDT 24
Peak memory 200912 kb
Host smart-8b81a5e4-6959-4b53-9765-39f94cdaa802
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752487096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.752487096
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3903400428
Short name T612
Test name
Test status
Simulation time 139110463 ps
CPU time 1.28 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:52 PM PDT 24
Peak memory 201160 kb
Host smart-38364b63-a9af-41f9-b1f2-32eaebf6c9ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903400428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3903400428
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1340593417
Short name T554
Test name
Test status
Simulation time 495085949 ps
CPU time 3.5 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:47 PM PDT 24
Peak memory 209308 kb
Host smart-c8429c1b-f4e1-4411-8bc8-cd99450f24b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340593417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1340593417
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.536688524
Short name T97
Test name
Test status
Simulation time 423956277 ps
CPU time 1.9 seconds
Started Apr 30 02:08:47 PM PDT 24
Finished Apr 30 02:08:50 PM PDT 24
Peak memory 201084 kb
Host smart-66ac2a23-f091-44fc-b57f-b1196607ba16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536688524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.536688524
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3871190627
Short name T577
Test name
Test status
Simulation time 127981467 ps
CPU time 1.47 seconds
Started Apr 30 02:08:47 PM PDT 24
Finished Apr 30 02:08:49 PM PDT 24
Peak memory 209172 kb
Host smart-53e481f1-e6bf-4b44-afba-b1de85cd2c89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871190627 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3871190627
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1423365960
Short name T605
Test name
Test status
Simulation time 64816646 ps
CPU time 0.8 seconds
Started Apr 30 02:08:48 PM PDT 24
Finished Apr 30 02:08:50 PM PDT 24
Peak memory 200864 kb
Host smart-21472c6f-1895-4a84-a33b-55725f840002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423365960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1423365960
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.648705134
Short name T547
Test name
Test status
Simulation time 105780676 ps
CPU time 1.21 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 201108 kb
Host smart-25395212-460c-4ce8-b6f6-ff5db5691526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648705134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.648705134
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2267837218
Short name T104
Test name
Test status
Simulation time 265162605 ps
CPU time 2.05 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 211924 kb
Host smart-1684a358-7145-46d3-8710-5bcbf828d8c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267837218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2267837218
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.4149801118
Short name T572
Test name
Test status
Simulation time 433407567 ps
CPU time 1.68 seconds
Started Apr 30 02:08:55 PM PDT 24
Finished Apr 30 02:08:57 PM PDT 24
Peak memory 201164 kb
Host smart-bcebf071-e091-4296-ab88-e572670e25e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149801118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.4149801118
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3309765505
Short name T131
Test name
Test status
Simulation time 121818997 ps
CPU time 1.29 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:52 PM PDT 24
Peak memory 211512 kb
Host smart-acada20b-d242-4cdd-a751-acae6579dd0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309765505 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3309765505
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3276418959
Short name T585
Test name
Test status
Simulation time 90488724 ps
CPU time 0.87 seconds
Started Apr 30 02:08:49 PM PDT 24
Finished Apr 30 02:08:50 PM PDT 24
Peak memory 200864 kb
Host smart-8ea53ead-1785-48f6-81e1-56db18bb1841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276418959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3276418959
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.868651820
Short name T559
Test name
Test status
Simulation time 215957218 ps
CPU time 1.38 seconds
Started Apr 30 02:08:51 PM PDT 24
Finished Apr 30 02:08:53 PM PDT 24
Peak memory 201012 kb
Host smart-4641afef-d74a-42f8-96e5-d8fcd771725c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868651820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.868651820
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3969047150
Short name T583
Test name
Test status
Simulation time 278945264 ps
CPU time 2.06 seconds
Started Apr 30 02:08:48 PM PDT 24
Finished Apr 30 02:08:51 PM PDT 24
Peak memory 209364 kb
Host smart-c14f25f6-80af-4136-9aad-d4ea55809cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969047150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3969047150
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1181989482
Short name T138
Test name
Test status
Simulation time 470029811 ps
CPU time 1.97 seconds
Started Apr 30 02:08:47 PM PDT 24
Finished Apr 30 02:08:50 PM PDT 24
Peak memory 201080 kb
Host smart-01e24e6b-07a1-470f-b089-f46cc072cdf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181989482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1181989482
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2941489717
Short name T594
Test name
Test status
Simulation time 197950402 ps
CPU time 1.2 seconds
Started Apr 30 02:09:04 PM PDT 24
Finished Apr 30 02:09:06 PM PDT 24
Peak memory 200920 kb
Host smart-17506f83-57b8-4cad-8b94-bf424c69fe3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941489717 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2941489717
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.769669747
Short name T575
Test name
Test status
Simulation time 60691596 ps
CPU time 0.86 seconds
Started Apr 30 02:08:56 PM PDT 24
Finished Apr 30 02:08:57 PM PDT 24
Peak memory 200912 kb
Host smart-9e3a7740-f851-47fd-9a09-6949a7a63114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769669747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.769669747
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2214038342
Short name T117
Test name
Test status
Simulation time 225495739 ps
CPU time 1.41 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:52 PM PDT 24
Peak memory 201112 kb
Host smart-cc3d1757-8829-4ae5-acb9-1e634864b278
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214038342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2214038342
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.226867503
Short name T101
Test name
Test status
Simulation time 214403351 ps
CPU time 1.73 seconds
Started Apr 30 02:08:53 PM PDT 24
Finished Apr 30 02:08:55 PM PDT 24
Peak memory 209336 kb
Host smart-da9b30ea-439d-4d5e-9e4e-999a25269e10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226867503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.226867503
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.539255476
Short name T560
Test name
Test status
Simulation time 459831910 ps
CPU time 1.87 seconds
Started Apr 30 02:09:02 PM PDT 24
Finished Apr 30 02:09:05 PM PDT 24
Peak memory 201084 kb
Host smart-3309c135-d446-4e9b-8e03-965280bc45f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539255476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.539255476
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2625057266
Short name T100
Test name
Test status
Simulation time 104706952 ps
CPU time 1.02 seconds
Started Apr 30 02:08:53 PM PDT 24
Finished Apr 30 02:08:55 PM PDT 24
Peak memory 209088 kb
Host smart-fde97eac-39d5-4ac5-b3b2-027359d35737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625057266 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2625057266
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1344276619
Short name T120
Test name
Test status
Simulation time 88647278 ps
CPU time 0.85 seconds
Started Apr 30 02:09:03 PM PDT 24
Finished Apr 30 02:09:04 PM PDT 24
Peak memory 200820 kb
Host smart-752411d1-3828-4f20-a433-4d47b4f85e36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344276619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1344276619
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1427519340
Short name T113
Test name
Test status
Simulation time 221125101 ps
CPU time 1.44 seconds
Started Apr 30 02:09:02 PM PDT 24
Finished Apr 30 02:09:04 PM PDT 24
Peak memory 201104 kb
Host smart-c7a58ed3-c281-45a3-87d9-43c8c880c47c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427519340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1427519340
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.451992263
Short name T71
Test name
Test status
Simulation time 538001735 ps
CPU time 2.05 seconds
Started Apr 30 02:09:00 PM PDT 24
Finished Apr 30 02:09:03 PM PDT 24
Peak memory 201344 kb
Host smart-c1813854-fe88-4513-b79c-1b70b458493d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451992263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.451992263
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2140252914
Short name T591
Test name
Test status
Simulation time 161290081 ps
CPU time 1.52 seconds
Started Apr 30 02:08:52 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 209356 kb
Host smart-272c8e9e-b170-4afc-89ac-387c3b5d4975
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140252914 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2140252914
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1748645181
Short name T121
Test name
Test status
Simulation time 68374449 ps
CPU time 0.82 seconds
Started Apr 30 02:08:53 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 200880 kb
Host smart-627042f5-566c-4eec-afb4-8d0bdbdbbcb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748645181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1748645181
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2330703896
Short name T116
Test name
Test status
Simulation time 135041807 ps
CPU time 1.15 seconds
Started Apr 30 02:09:06 PM PDT 24
Finished Apr 30 02:09:07 PM PDT 24
Peak memory 200936 kb
Host smart-6a4cf8c0-b005-4777-a05a-236114db0863
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330703896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2330703896
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3474726663
Short name T599
Test name
Test status
Simulation time 110403134 ps
CPU time 1.57 seconds
Started Apr 30 02:09:03 PM PDT 24
Finished Apr 30 02:09:05 PM PDT 24
Peak memory 212704 kb
Host smart-d3f6da36-7601-42c5-bf69-d6c678d1cb0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474726663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3474726663
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4094113680
Short name T581
Test name
Test status
Simulation time 178328146 ps
CPU time 1.19 seconds
Started Apr 30 02:09:06 PM PDT 24
Finished Apr 30 02:09:08 PM PDT 24
Peak memory 201048 kb
Host smart-03515d36-cc35-4d3f-8e2a-71d08eb7f89a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094113680 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4094113680
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.401583247
Short name T548
Test name
Test status
Simulation time 65946636 ps
CPU time 0.74 seconds
Started Apr 30 02:09:06 PM PDT 24
Finished Apr 30 02:09:07 PM PDT 24
Peak memory 200892 kb
Host smart-281e6ae3-8594-441b-b61d-b629c8d0582a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401583247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.401583247
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3822465392
Short name T597
Test name
Test status
Simulation time 106071695 ps
CPU time 1.2 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:51 PM PDT 24
Peak memory 201060 kb
Host smart-51296a3f-2c64-48ad-ad3a-bb6715fdd3e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822465392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3822465392
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3187291166
Short name T564
Test name
Test status
Simulation time 185665768 ps
CPU time 2.61 seconds
Started Apr 30 02:08:51 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 209276 kb
Host smart-5137d5e5-3ff5-4b1d-9a87-a80f2aeea7df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187291166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3187291166
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.620758617
Short name T604
Test name
Test status
Simulation time 793743520 ps
CPU time 3.13 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 201140 kb
Host smart-7e788ff4-fa4f-41a3-9424-c167f11f489d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620758617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.620758617
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2239187190
Short name T107
Test name
Test status
Simulation time 204369786 ps
CPU time 1.56 seconds
Started Apr 30 02:08:35 PM PDT 24
Finished Apr 30 02:08:37 PM PDT 24
Peak memory 201120 kb
Host smart-897d8ef6-22e9-4a32-b804-b0f4ae5d51a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239187190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
239187190
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2933927051
Short name T579
Test name
Test status
Simulation time 488414367 ps
CPU time 6.05 seconds
Started Apr 30 02:08:39 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 201068 kb
Host smart-0c1a5451-1c82-461f-8c05-51426da2deb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933927051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
933927051
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.820330647
Short name T592
Test name
Test status
Simulation time 137023894 ps
CPU time 0.92 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:52 PM PDT 24
Peak memory 200880 kb
Host smart-8c8d593f-3517-467e-b5f9-f08c24d25f98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820330647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.820330647
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1282888052
Short name T565
Test name
Test status
Simulation time 123147452 ps
CPU time 1.34 seconds
Started Apr 30 02:08:38 PM PDT 24
Finished Apr 30 02:08:40 PM PDT 24
Peak memory 209208 kb
Host smart-6bc89c9f-e6fc-4396-8862-c79993212f91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282888052 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1282888052
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.214063345
Short name T69
Test name
Test status
Simulation time 77652910 ps
CPU time 0.81 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 200908 kb
Host smart-25184dd5-047b-4ac0-8428-7c3d1c955056
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214063345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.214063345
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2586359082
Short name T566
Test name
Test status
Simulation time 256401720 ps
CPU time 1.63 seconds
Started Apr 30 02:08:36 PM PDT 24
Finished Apr 30 02:08:38 PM PDT 24
Peak memory 201064 kb
Host smart-5b46c3b9-3404-44aa-83ff-f8b5a376a66a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586359082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2586359082
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2078768190
Short name T582
Test name
Test status
Simulation time 94451564 ps
CPU time 1.34 seconds
Started Apr 30 02:08:38 PM PDT 24
Finished Apr 30 02:08:40 PM PDT 24
Peak memory 209308 kb
Host smart-83bc7ab3-f491-41ec-b05d-60314f3b9701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078768190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2078768190
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1433348171
Short name T573
Test name
Test status
Simulation time 950863636 ps
CPU time 3.11 seconds
Started Apr 30 02:08:37 PM PDT 24
Finished Apr 30 02:08:41 PM PDT 24
Peak memory 201092 kb
Host smart-7a1b0754-641a-4d5b-9bd9-02a2525f5f41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433348171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1433348171
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1138286724
Short name T590
Test name
Test status
Simulation time 147370907 ps
CPU time 2.02 seconds
Started Apr 30 02:08:41 PM PDT 24
Finished Apr 30 02:08:44 PM PDT 24
Peak memory 209240 kb
Host smart-b52d136a-7611-457b-a8c0-2b456c2c07b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138286724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
138286724
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3963062745
Short name T587
Test name
Test status
Simulation time 799293319 ps
CPU time 4.54 seconds
Started Apr 30 02:08:42 PM PDT 24
Finished Apr 30 02:08:47 PM PDT 24
Peak memory 201044 kb
Host smart-e8895d0a-9c60-4ac7-b8c1-a1f950bacf73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963062745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
963062745
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3700163532
Short name T602
Test name
Test status
Simulation time 92316845 ps
CPU time 0.85 seconds
Started Apr 30 02:08:42 PM PDT 24
Finished Apr 30 02:08:43 PM PDT 24
Peak memory 200864 kb
Host smart-001eb4f5-769b-4a06-9a62-65b9004c6341
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700163532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
700163532
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.760555514
Short name T607
Test name
Test status
Simulation time 120605848 ps
CPU time 0.99 seconds
Started Apr 30 02:08:37 PM PDT 24
Finished Apr 30 02:08:39 PM PDT 24
Peak memory 200968 kb
Host smart-f0775549-89e1-4afe-bbb7-f1d04fb277d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760555514 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.760555514
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2386155579
Short name T546
Test name
Test status
Simulation time 72703439 ps
CPU time 0.8 seconds
Started Apr 30 02:08:45 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 200892 kb
Host smart-5ce41b6f-f092-49b0-b62a-01406c56ffa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386155579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2386155579
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2851916423
Short name T115
Test name
Test status
Simulation time 121313722 ps
CPU time 1.12 seconds
Started Apr 30 02:08:46 PM PDT 24
Finished Apr 30 02:08:47 PM PDT 24
Peak memory 200900 kb
Host smart-efbba128-ad7c-41c6-b83e-4b0f93d1aa02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851916423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2851916423
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2045161296
Short name T553
Test name
Test status
Simulation time 182986022 ps
CPU time 2.64 seconds
Started Apr 30 02:08:46 PM PDT 24
Finished Apr 30 02:08:49 PM PDT 24
Peak memory 217408 kb
Host smart-e78a166b-d612-414b-9e38-d7ef83d2bb7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045161296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2045161296
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1617682668
Short name T124
Test name
Test status
Simulation time 904413640 ps
CPU time 2.99 seconds
Started Apr 30 02:08:37 PM PDT 24
Finished Apr 30 02:08:41 PM PDT 24
Peak memory 201104 kb
Host smart-bd37fd79-5f4d-4b69-99ef-057bf86712bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617682668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1617682668
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1350630683
Short name T596
Test name
Test status
Simulation time 211864930 ps
CPU time 1.57 seconds
Started Apr 30 02:09:00 PM PDT 24
Finished Apr 30 02:09:02 PM PDT 24
Peak memory 201064 kb
Host smart-ee98b4a6-8ecd-4f19-8706-c3f4d56c437b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350630683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
350630683
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2281726285
Short name T606
Test name
Test status
Simulation time 275985832 ps
CPU time 3.36 seconds
Started Apr 30 02:08:41 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 200992 kb
Host smart-44c4a0b7-f332-454a-b531-e39b77990c40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281726285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
281726285
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3546087334
Short name T563
Test name
Test status
Simulation time 104074974 ps
CPU time 0.88 seconds
Started Apr 30 02:08:37 PM PDT 24
Finished Apr 30 02:08:38 PM PDT 24
Peak memory 200824 kb
Host smart-6c31b8ef-b9fc-4a70-ae2d-a32c90e3de04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546087334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
546087334
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1977350056
Short name T568
Test name
Test status
Simulation time 166901921 ps
CPU time 1.57 seconds
Started Apr 30 02:08:51 PM PDT 24
Finished Apr 30 02:08:53 PM PDT 24
Peak memory 213720 kb
Host smart-16196065-deef-4830-a583-3a078dc35b7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977350056 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1977350056
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3373412717
Short name T545
Test name
Test status
Simulation time 75079020 ps
CPU time 0.84 seconds
Started Apr 30 02:08:45 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 200912 kb
Host smart-f9399adc-1ea3-489c-b665-5c2a99240d57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373412717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3373412717
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4212323489
Short name T614
Test name
Test status
Simulation time 79330313 ps
CPU time 0.99 seconds
Started Apr 30 02:08:41 PM PDT 24
Finished Apr 30 02:08:42 PM PDT 24
Peak memory 200900 kb
Host smart-2733f330-a181-4231-91d3-43080e932563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212323489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4212323489
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2817528024
Short name T603
Test name
Test status
Simulation time 208454311 ps
CPU time 1.82 seconds
Started Apr 30 02:08:39 PM PDT 24
Finished Apr 30 02:08:41 PM PDT 24
Peak memory 209312 kb
Host smart-0f542237-f58f-4db7-9410-ed344c08afe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817528024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2817528024
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.208962291
Short name T561
Test name
Test status
Simulation time 189901221 ps
CPU time 1.28 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:44 PM PDT 24
Peak memory 209208 kb
Host smart-f3dbafec-8096-471d-8580-0d2192b6ea1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208962291 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.208962291
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1680430211
Short name T118
Test name
Test status
Simulation time 60199184 ps
CPU time 0.83 seconds
Started Apr 30 02:08:42 PM PDT 24
Finished Apr 30 02:08:44 PM PDT 24
Peak memory 200824 kb
Host smart-aa961387-7967-4b91-8331-f40eac2a64c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680430211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1680430211
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1169702577
Short name T555
Test name
Test status
Simulation time 80530212 ps
CPU time 0.96 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 200948 kb
Host smart-32526ee8-e99f-4538-91a2-f0a8770de33e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169702577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1169702577
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.248341122
Short name T103
Test name
Test status
Simulation time 138156211 ps
CPU time 2.07 seconds
Started Apr 30 02:08:47 PM PDT 24
Finished Apr 30 02:08:49 PM PDT 24
Peak memory 209316 kb
Host smart-75b1a2ae-4eee-48d3-be91-cae67ad32b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248341122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.248341122
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2984905932
Short name T593
Test name
Test status
Simulation time 199359205 ps
CPU time 1.27 seconds
Started Apr 30 02:08:41 PM PDT 24
Finished Apr 30 02:08:42 PM PDT 24
Peak memory 209216 kb
Host smart-d4a689ad-2ebf-485a-a700-c4821970695a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984905932 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2984905932
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1934208611
Short name T569
Test name
Test status
Simulation time 86818954 ps
CPU time 0.88 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:44 PM PDT 24
Peak memory 200884 kb
Host smart-78e9bccb-24c5-4e2d-9704-07aa71e8702b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934208611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1934208611
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2226183677
Short name T584
Test name
Test status
Simulation time 195152735 ps
CPU time 1.6 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 201120 kb
Host smart-89a5d746-c482-433b-948e-0f885a8cb996
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226183677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2226183677
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3991777021
Short name T130
Test name
Test status
Simulation time 522904128 ps
CPU time 3.78 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 209284 kb
Host smart-9a0aa449-cc60-4dc4-b169-cd22b5f01551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991777021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3991777021
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1761696098
Short name T600
Test name
Test status
Simulation time 785791528 ps
CPU time 2.84 seconds
Started Apr 30 02:09:02 PM PDT 24
Finished Apr 30 02:09:05 PM PDT 24
Peak memory 201124 kb
Host smart-c1b24194-0a80-4654-bbab-ad241566093c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761696098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1761696098
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2012095082
Short name T578
Test name
Test status
Simulation time 134989223 ps
CPU time 1.32 seconds
Started Apr 30 02:08:51 PM PDT 24
Finished Apr 30 02:08:53 PM PDT 24
Peak memory 209132 kb
Host smart-3ed16fff-90f7-4fad-9ad5-341421c42d4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012095082 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2012095082
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2496061199
Short name T610
Test name
Test status
Simulation time 55955771 ps
CPU time 0.74 seconds
Started Apr 30 02:08:57 PM PDT 24
Finished Apr 30 02:08:58 PM PDT 24
Peak memory 200820 kb
Host smart-af60a04c-0596-4e5e-b48e-8a15b6f25ea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496061199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2496061199
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1274002873
Short name T119
Test name
Test status
Simulation time 139480409 ps
CPU time 1.22 seconds
Started Apr 30 02:08:52 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 200660 kb
Host smart-0e48c198-3214-41e1-b9de-0d2cea6d8fc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274002873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1274002873
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.964378512
Short name T567
Test name
Test status
Simulation time 89313853 ps
CPU time 1.26 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 209160 kb
Host smart-893f7008-d905-4900-958d-ad4c5f5e53e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964378512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.964378512
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.633872116
Short name T598
Test name
Test status
Simulation time 497198345 ps
CPU time 1.93 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 201096 kb
Host smart-4a3aedb3-32db-48e9-87b4-e50ca416b2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633872116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
633872116
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1422805450
Short name T601
Test name
Test status
Simulation time 166201000 ps
CPU time 1.46 seconds
Started Apr 30 02:08:48 PM PDT 24
Finished Apr 30 02:08:50 PM PDT 24
Peak memory 209424 kb
Host smart-62b3ee66-e17c-45d0-949a-c33293446ff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422805450 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1422805450
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3162990555
Short name T552
Test name
Test status
Simulation time 75115876 ps
CPU time 0.82 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:45 PM PDT 24
Peak memory 200876 kb
Host smart-6fecd442-3613-411b-bfff-d1bf5b4e8e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162990555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3162990555
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3095425409
Short name T616
Test name
Test status
Simulation time 134738484 ps
CPU time 1.03 seconds
Started Apr 30 02:08:49 PM PDT 24
Finished Apr 30 02:08:51 PM PDT 24
Peak memory 200924 kb
Host smart-386e811c-30a6-4185-981f-e667b6daae46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095425409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3095425409
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2709852861
Short name T129
Test name
Test status
Simulation time 108113614 ps
CPU time 1.57 seconds
Started Apr 30 02:08:44 PM PDT 24
Finished Apr 30 02:08:46 PM PDT 24
Peak memory 201108 kb
Host smart-10cdf0c9-8373-4d39-b67d-494e20621b59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709852861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2709852861
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1608501237
Short name T613
Test name
Test status
Simulation time 896199523 ps
CPU time 3.2 seconds
Started Apr 30 02:08:56 PM PDT 24
Finished Apr 30 02:09:00 PM PDT 24
Peak memory 201128 kb
Host smart-0bb205cd-7c23-4c5c-92ed-bc23c9300cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608501237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1608501237
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3891480790
Short name T589
Test name
Test status
Simulation time 129034493 ps
CPU time 1.48 seconds
Started Apr 30 02:08:43 PM PDT 24
Finished Apr 30 02:08:44 PM PDT 24
Peak memory 209424 kb
Host smart-410eaee5-a394-4199-8b60-c10f55b218dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891480790 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3891480790
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4164946816
Short name T112
Test name
Test status
Simulation time 85207510 ps
CPU time 0.79 seconds
Started Apr 30 02:08:47 PM PDT 24
Finished Apr 30 02:08:48 PM PDT 24
Peak memory 200880 kb
Host smart-ae4362d5-48ef-4951-a6d1-68bb7fe7f3df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164946816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4164946816
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1094995743
Short name T558
Test name
Test status
Simulation time 224119288 ps
CPU time 1.49 seconds
Started Apr 30 02:08:56 PM PDT 24
Finished Apr 30 02:08:58 PM PDT 24
Peak memory 201240 kb
Host smart-1bb5b25e-bd13-4979-892c-9df883f7da21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094995743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1094995743
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1506735132
Short name T126
Test name
Test status
Simulation time 419690867 ps
CPU time 3.33 seconds
Started Apr 30 02:08:47 PM PDT 24
Finished Apr 30 02:08:51 PM PDT 24
Peak memory 209284 kb
Host smart-360c78eb-ae40-4316-b47f-2996b0982647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506735132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1506735132
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3846767673
Short name T122
Test name
Test status
Simulation time 802989197 ps
CPU time 2.94 seconds
Started Apr 30 02:08:50 PM PDT 24
Finished Apr 30 02:08:54 PM PDT 24
Peak memory 201216 kb
Host smart-9d2f554a-5eef-4c98-a197-85cc5388f24e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846767673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3846767673
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1193697580
Short name T345
Test name
Test status
Simulation time 60577462 ps
CPU time 0.71 seconds
Started Apr 30 01:05:20 PM PDT 24
Finished Apr 30 01:05:21 PM PDT 24
Peak memory 200636 kb
Host smart-a73f9098-85bf-45e8-933a-0053454397ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193697580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1193697580
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1283150301
Short name T41
Test name
Test status
Simulation time 2356919699 ps
CPU time 8.67 seconds
Started Apr 30 01:05:07 PM PDT 24
Finished Apr 30 01:05:15 PM PDT 24
Peak memory 231016 kb
Host smart-3c440f80-1131-481c-b480-6b6c27732c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283150301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1283150301
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1912262230
Short name T140
Test name
Test status
Simulation time 245698709 ps
CPU time 1.05 seconds
Started Apr 30 01:05:12 PM PDT 24
Finished Apr 30 01:05:13 PM PDT 24
Peak memory 218064 kb
Host smart-67a4fda6-6ad2-4e07-a2cf-de7b752688b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912262230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1912262230
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3802150678
Short name T293
Test name
Test status
Simulation time 226903275 ps
CPU time 0.91 seconds
Started Apr 30 01:04:53 PM PDT 24
Finished Apr 30 01:04:54 PM PDT 24
Peak memory 200612 kb
Host smart-603e911a-b98a-4ff9-9c0e-13a354afb9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802150678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3802150678
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1986012467
Short name T487
Test name
Test status
Simulation time 1281008792 ps
CPU time 5.41 seconds
Started Apr 30 01:05:00 PM PDT 24
Finished Apr 30 01:05:06 PM PDT 24
Peak memory 201108 kb
Host smart-c5e6be0b-b277-4c3b-b7c9-2655c78d27d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986012467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1986012467
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1890203868
Short name T78
Test name
Test status
Simulation time 16510547671 ps
CPU time 25.49 seconds
Started Apr 30 01:05:20 PM PDT 24
Finished Apr 30 01:05:46 PM PDT 24
Peak memory 217672 kb
Host smart-9577a786-0187-445c-a6e6-2bccd565cde8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890203868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1890203868
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1368350693
Short name T353
Test name
Test status
Simulation time 176697308 ps
CPU time 1.16 seconds
Started Apr 30 01:05:06 PM PDT 24
Finished Apr 30 01:05:07 PM PDT 24
Peak memory 200856 kb
Host smart-54d60329-cef0-4202-bde7-7fef497b00ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368350693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1368350693
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1033302647
Short name T154
Test name
Test status
Simulation time 238821850 ps
CPU time 1.42 seconds
Started Apr 30 01:04:56 PM PDT 24
Finished Apr 30 01:04:58 PM PDT 24
Peak memory 201128 kb
Host smart-0100da9c-c444-4a3b-8cd8-c23962b3956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033302647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1033302647
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3283167085
Short name T337
Test name
Test status
Simulation time 401453241 ps
CPU time 2.36 seconds
Started Apr 30 01:05:03 PM PDT 24
Finished Apr 30 01:05:06 PM PDT 24
Peak memory 200832 kb
Host smart-a0b3be4e-43cf-4ddd-b25d-c071d456160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283167085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3283167085
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1152734232
Short name T235
Test name
Test status
Simulation time 89489770 ps
CPU time 0.92 seconds
Started Apr 30 01:04:59 PM PDT 24
Finished Apr 30 01:05:00 PM PDT 24
Peak memory 200844 kb
Host smart-66b948e3-f058-4569-a7ac-c0c08309836c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152734232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1152734232
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.899031820
Short name T495
Test name
Test status
Simulation time 82913339 ps
CPU time 0.8 seconds
Started Apr 30 01:05:46 PM PDT 24
Finished Apr 30 01:05:47 PM PDT 24
Peak memory 200664 kb
Host smart-474e06f8-8136-4d30-9130-27a75888dc5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899031820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.899031820
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2274313863
Short name T537
Test name
Test status
Simulation time 1887670062 ps
CPU time 7.46 seconds
Started Apr 30 01:05:38 PM PDT 24
Finished Apr 30 01:05:46 PM PDT 24
Peak memory 217808 kb
Host smart-fabb91aa-729b-4c5b-a36e-1d75da3da807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274313863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2274313863
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2197832477
Short name T540
Test name
Test status
Simulation time 247444518 ps
CPU time 1.04 seconds
Started Apr 30 01:05:36 PM PDT 24
Finished Apr 30 01:05:38 PM PDT 24
Peak memory 218300 kb
Host smart-c0f02534-5651-406d-a5fe-cea61b94734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197832477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2197832477
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3574773123
Short name T406
Test name
Test status
Simulation time 1924216371 ps
CPU time 6.87 seconds
Started Apr 30 01:05:33 PM PDT 24
Finished Apr 30 01:05:40 PM PDT 24
Peak memory 201128 kb
Host smart-b9efefce-b47d-4b7b-ba3d-2eb2230e4f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574773123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3574773123
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.979851214
Short name T77
Test name
Test status
Simulation time 8332727786 ps
CPU time 12.79 seconds
Started Apr 30 01:05:44 PM PDT 24
Finished Apr 30 01:05:57 PM PDT 24
Peak memory 217688 kb
Host smart-870d2fb5-6718-4890-b43b-53559645bd60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979851214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.979851214
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1027965568
Short name T232
Test name
Test status
Simulation time 249905114 ps
CPU time 1.45 seconds
Started Apr 30 01:05:26 PM PDT 24
Finished Apr 30 01:05:28 PM PDT 24
Peak memory 201016 kb
Host smart-2c6fb523-450b-481d-b6c9-f9a1e22e4e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027965568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1027965568
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3151615728
Short name T431
Test name
Test status
Simulation time 8237087422 ps
CPU time 37.71 seconds
Started Apr 30 01:05:37 PM PDT 24
Finished Apr 30 01:06:15 PM PDT 24
Peak memory 201204 kb
Host smart-9e68e803-9ec6-464d-bea4-969f5c92e3d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151615728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3151615728
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3155847927
Short name T401
Test name
Test status
Simulation time 123198910 ps
CPU time 1.41 seconds
Started Apr 30 01:05:33 PM PDT 24
Finished Apr 30 01:05:35 PM PDT 24
Peak memory 200800 kb
Host smart-a27d06ae-aa58-439d-9512-2cba6404b24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155847927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3155847927
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1900464868
Short name T295
Test name
Test status
Simulation time 164359269 ps
CPU time 0.99 seconds
Started Apr 30 01:05:32 PM PDT 24
Finished Apr 30 01:05:33 PM PDT 24
Peak memory 200812 kb
Host smart-140fcec3-c004-4ec7-8b71-56cbbed798c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900464868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1900464868
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.4186949446
Short name T348
Test name
Test status
Simulation time 1227873546 ps
CPU time 5.64 seconds
Started Apr 30 01:07:29 PM PDT 24
Finished Apr 30 01:07:35 PM PDT 24
Peak memory 217512 kb
Host smart-ca5c1d3f-90b1-47c5-a282-4b510cc450f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186949446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.4186949446
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1990962446
Short name T415
Test name
Test status
Simulation time 244834341 ps
CPU time 1.03 seconds
Started Apr 30 01:07:27 PM PDT 24
Finished Apr 30 01:07:29 PM PDT 24
Peak memory 218048 kb
Host smart-3f971435-9488-46d9-8ffc-02003925052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990962446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1990962446
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3711631719
Short name T505
Test name
Test status
Simulation time 110398455 ps
CPU time 0.79 seconds
Started Apr 30 01:07:16 PM PDT 24
Finished Apr 30 01:07:17 PM PDT 24
Peak memory 200652 kb
Host smart-c7209c5e-2473-485e-bedb-466cf94b4d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711631719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3711631719
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.4118967897
Short name T325
Test name
Test status
Simulation time 1399759999 ps
CPU time 5.66 seconds
Started Apr 30 01:07:28 PM PDT 24
Finished Apr 30 01:07:34 PM PDT 24
Peak memory 201000 kb
Host smart-4dd7baa1-d43a-404d-9c41-ac753fad124f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118967897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.4118967897
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2353535792
Short name T242
Test name
Test status
Simulation time 157241163 ps
CPU time 1.19 seconds
Started Apr 30 01:07:34 PM PDT 24
Finished Apr 30 01:07:36 PM PDT 24
Peak memory 200808 kb
Host smart-8a4e6237-63fe-405b-b81b-790d26f53b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353535792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2353535792
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.835657056
Short name T389
Test name
Test status
Simulation time 201526081 ps
CPU time 1.47 seconds
Started Apr 30 01:07:28 PM PDT 24
Finished Apr 30 01:07:30 PM PDT 24
Peak memory 201028 kb
Host smart-fbdc0ca5-492f-4c11-8be4-5a444bc9d663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835657056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.835657056
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3615495376
Short name T171
Test name
Test status
Simulation time 2824852991 ps
CPU time 12.95 seconds
Started Apr 30 01:07:28 PM PDT 24
Finished Apr 30 01:07:42 PM PDT 24
Peak memory 201220 kb
Host smart-c317a5c8-714a-4d30-8f68-b2b268aa3e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615495376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3615495376
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.369055996
Short name T360
Test name
Test status
Simulation time 269079711 ps
CPU time 1.82 seconds
Started Apr 30 01:07:29 PM PDT 24
Finished Apr 30 01:07:31 PM PDT 24
Peak memory 200804 kb
Host smart-ec1ff39f-128c-48e0-b6a2-035113ddfa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369055996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.369055996
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.710321011
Short name T187
Test name
Test status
Simulation time 114155676 ps
CPU time 0.96 seconds
Started Apr 30 01:07:28 PM PDT 24
Finished Apr 30 01:07:30 PM PDT 24
Peak memory 200816 kb
Host smart-553efbb7-2754-4a45-9a4c-f59993170504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710321011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.710321011
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2484876441
Short name T230
Test name
Test status
Simulation time 69106700 ps
CPU time 0.76 seconds
Started Apr 30 01:07:34 PM PDT 24
Finished Apr 30 01:07:36 PM PDT 24
Peak memory 200708 kb
Host smart-7d010536-1c4a-478a-a921-9efb88b68d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484876441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2484876441
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.186692839
Short name T380
Test name
Test status
Simulation time 2175674314 ps
CPU time 7.94 seconds
Started Apr 30 01:07:35 PM PDT 24
Finished Apr 30 01:07:43 PM PDT 24
Peak memory 218752 kb
Host smart-6e282e2a-9253-45b7-9e21-607bc3b1b78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186692839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.186692839
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2032244838
Short name T186
Test name
Test status
Simulation time 244373280 ps
CPU time 1.04 seconds
Started Apr 30 01:07:36 PM PDT 24
Finished Apr 30 01:07:37 PM PDT 24
Peak memory 218008 kb
Host smart-d8480036-74e3-4d9e-9742-3ab8dd0cfb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032244838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2032244838
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2565095740
Short name T516
Test name
Test status
Simulation time 143316617 ps
CPU time 0.86 seconds
Started Apr 30 01:07:28 PM PDT 24
Finished Apr 30 01:07:30 PM PDT 24
Peak memory 200664 kb
Host smart-98007e09-5517-4d1e-aa86-1466c12eb348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565095740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2565095740
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4228976117
Short name T474
Test name
Test status
Simulation time 924701716 ps
CPU time 3.88 seconds
Started Apr 30 01:07:36 PM PDT 24
Finished Apr 30 01:07:40 PM PDT 24
Peak memory 201024 kb
Host smart-b1110ecb-406b-441f-856c-f53e5d215a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228976117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4228976117
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1499459017
Short name T178
Test name
Test status
Simulation time 104450417 ps
CPU time 0.99 seconds
Started Apr 30 01:07:36 PM PDT 24
Finished Apr 30 01:07:38 PM PDT 24
Peak memory 200844 kb
Host smart-9db234c7-3d30-4047-bd20-a67d2fefa281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499459017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1499459017
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.864729413
Short name T460
Test name
Test status
Simulation time 259029306 ps
CPU time 1.38 seconds
Started Apr 30 01:07:27 PM PDT 24
Finished Apr 30 01:07:29 PM PDT 24
Peak memory 201016 kb
Host smart-2142b71d-4838-4358-9d47-c3425d0b4adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864729413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.864729413
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3137252979
Short name T246
Test name
Test status
Simulation time 378454004 ps
CPU time 1.7 seconds
Started Apr 30 01:07:35 PM PDT 24
Finished Apr 30 01:07:37 PM PDT 24
Peak memory 200980 kb
Host smart-50b7fb19-4ca4-4a09-a935-29e0218f0c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137252979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3137252979
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.609071267
Short name T462
Test name
Test status
Simulation time 139081650 ps
CPU time 1.81 seconds
Started Apr 30 01:07:36 PM PDT 24
Finished Apr 30 01:07:38 PM PDT 24
Peak memory 200828 kb
Host smart-6f00b80b-f44d-4532-9a61-f42c732e4ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609071267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.609071267
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.253505180
Short name T424
Test name
Test status
Simulation time 180110994 ps
CPU time 1.12 seconds
Started Apr 30 01:07:35 PM PDT 24
Finished Apr 30 01:07:37 PM PDT 24
Peak memory 200824 kb
Host smart-96776d76-e2fe-4d91-a5fd-1c065cf75415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253505180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.253505180
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1381948149
Short name T527
Test name
Test status
Simulation time 66239115 ps
CPU time 0.71 seconds
Started Apr 30 01:07:42 PM PDT 24
Finished Apr 30 01:07:43 PM PDT 24
Peak memory 200664 kb
Host smart-6fe50c42-829f-4638-a7fe-66e332f0c959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381948149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1381948149
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.73216938
Short name T36
Test name
Test status
Simulation time 1894914714 ps
CPU time 6.56 seconds
Started Apr 30 01:07:41 PM PDT 24
Finished Apr 30 01:07:48 PM PDT 24
Peak memory 218432 kb
Host smart-e3f37afc-3673-4f35-b274-412d182c7ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73216938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.73216938
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.696990626
Short name T512
Test name
Test status
Simulation time 244154512 ps
CPU time 0.98 seconds
Started Apr 30 01:07:41 PM PDT 24
Finished Apr 30 01:07:42 PM PDT 24
Peak memory 218020 kb
Host smart-30df0a7f-f0ee-422f-80f7-d4b769d5b5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696990626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.696990626
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2218941941
Short name T466
Test name
Test status
Simulation time 149198223 ps
CPU time 0.8 seconds
Started Apr 30 01:07:40 PM PDT 24
Finished Apr 30 01:07:41 PM PDT 24
Peak memory 200712 kb
Host smart-7e6cb9de-a945-4a56-8f33-aaa679aad141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218941941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2218941941
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2490579161
Short name T519
Test name
Test status
Simulation time 860206818 ps
CPU time 4.76 seconds
Started Apr 30 01:07:41 PM PDT 24
Finished Apr 30 01:07:46 PM PDT 24
Peak memory 200992 kb
Host smart-88502c03-1e83-432e-a0a4-8a201453c70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490579161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2490579161
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3867936248
Short name T2
Test name
Test status
Simulation time 137609599 ps
CPU time 1.09 seconds
Started Apr 30 01:07:41 PM PDT 24
Finished Apr 30 01:07:43 PM PDT 24
Peak memory 200912 kb
Host smart-a4c224af-7759-4ac2-ba20-6dc16dc2b229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867936248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3867936248
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2040008079
Short name T485
Test name
Test status
Simulation time 190285682 ps
CPU time 1.36 seconds
Started Apr 30 01:07:41 PM PDT 24
Finished Apr 30 01:07:43 PM PDT 24
Peak memory 201028 kb
Host smart-61657af5-5f3b-43f5-8a8c-d28a2f6165cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040008079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2040008079
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.148086257
Short name T177
Test name
Test status
Simulation time 469537210 ps
CPU time 2.44 seconds
Started Apr 30 01:07:40 PM PDT 24
Finished Apr 30 01:07:43 PM PDT 24
Peak memory 209252 kb
Host smart-b918ec5d-7cab-49ac-9d06-8a8eaa7d3203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148086257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.148086257
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1227476480
Short name T183
Test name
Test status
Simulation time 103282895 ps
CPU time 0.91 seconds
Started Apr 30 01:07:41 PM PDT 24
Finished Apr 30 01:07:43 PM PDT 24
Peak memory 200864 kb
Host smart-54f85f71-91ce-4ee4-b94b-9fae5ab2f099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227476480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1227476480
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.740647713
Short name T268
Test name
Test status
Simulation time 69570336 ps
CPU time 0.72 seconds
Started Apr 30 01:07:48 PM PDT 24
Finished Apr 30 01:07:49 PM PDT 24
Peak memory 200656 kb
Host smart-f85ce213-41e2-465e-a0cd-199e1c5b4317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740647713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.740647713
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.159437764
Short name T63
Test name
Test status
Simulation time 1899589030 ps
CPU time 8.28 seconds
Started Apr 30 01:07:47 PM PDT 24
Finished Apr 30 01:07:56 PM PDT 24
Peak memory 217564 kb
Host smart-17f4c32c-fe85-4943-9d61-f284e7d13c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159437764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.159437764
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.63464704
Short name T249
Test name
Test status
Simulation time 244608406 ps
CPU time 1.06 seconds
Started Apr 30 01:07:47 PM PDT 24
Finished Apr 30 01:07:48 PM PDT 24
Peak memory 218256 kb
Host smart-7002d0c7-625f-4654-980c-965565ebd9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63464704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.63464704
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1129843765
Short name T226
Test name
Test status
Simulation time 93073109 ps
CPU time 0.74 seconds
Started Apr 30 01:07:41 PM PDT 24
Finished Apr 30 01:07:42 PM PDT 24
Peak memory 200712 kb
Host smart-a0cf8c8a-6c59-494a-9a20-3d3ad553eac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129843765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1129843765
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1736491556
Short name T510
Test name
Test status
Simulation time 1623546431 ps
CPU time 5.79 seconds
Started Apr 30 01:07:40 PM PDT 24
Finished Apr 30 01:07:47 PM PDT 24
Peak memory 201020 kb
Host smart-d2dd6a6e-10ce-4045-b5c9-9af2be104214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736491556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1736491556
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2802828943
Short name T236
Test name
Test status
Simulation time 146653207 ps
CPU time 1.03 seconds
Started Apr 30 01:07:47 PM PDT 24
Finished Apr 30 01:07:48 PM PDT 24
Peak memory 200872 kb
Host smart-f689eaec-75c5-4528-866c-57cdd622b2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802828943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2802828943
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2729796169
Short name T427
Test name
Test status
Simulation time 115162559 ps
CPU time 1.17 seconds
Started Apr 30 01:07:41 PM PDT 24
Finished Apr 30 01:07:43 PM PDT 24
Peak memory 201032 kb
Host smart-85e52905-f15d-43a3-87d0-7b9bdd8ebd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729796169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2729796169
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.4116580707
Short name T437
Test name
Test status
Simulation time 389448867 ps
CPU time 2.58 seconds
Started Apr 30 01:07:48 PM PDT 24
Finished Apr 30 01:07:51 PM PDT 24
Peak memory 200824 kb
Host smart-3a8e2573-e7a4-4062-8a6c-140883fb6114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116580707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.4116580707
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.949748332
Short name T459
Test name
Test status
Simulation time 191450697 ps
CPU time 1.24 seconds
Started Apr 30 01:07:48 PM PDT 24
Finished Apr 30 01:07:50 PM PDT 24
Peak memory 201088 kb
Host smart-c4c4b406-7fd7-461d-9576-ac3df87dfb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949748332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.949748332
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3789512315
Short name T475
Test name
Test status
Simulation time 86198370 ps
CPU time 0.81 seconds
Started Apr 30 01:07:52 PM PDT 24
Finished Apr 30 01:07:54 PM PDT 24
Peak memory 200688 kb
Host smart-33b8d294-804a-45d5-b5f6-845127b51ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789512315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3789512315
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2516235992
Short name T365
Test name
Test status
Simulation time 1912426105 ps
CPU time 7.33 seconds
Started Apr 30 01:07:53 PM PDT 24
Finished Apr 30 01:08:01 PM PDT 24
Peak memory 222524 kb
Host smart-020c893b-eb68-44e5-bd2b-9361ded6476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516235992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2516235992
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.762961974
Short name T327
Test name
Test status
Simulation time 245285084 ps
CPU time 1.02 seconds
Started Apr 30 01:07:53 PM PDT 24
Finished Apr 30 01:07:55 PM PDT 24
Peak memory 218124 kb
Host smart-045c85a8-7c0b-45e2-9be0-b8308609d02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762961974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.762961974
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4249106258
Short name T281
Test name
Test status
Simulation time 188485648 ps
CPU time 0.97 seconds
Started Apr 30 01:07:53 PM PDT 24
Finished Apr 30 01:07:54 PM PDT 24
Peak memory 200712 kb
Host smart-3390f8bd-9203-4ec2-b13a-e63654fd7443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249106258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4249106258
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.209961447
Short name T384
Test name
Test status
Simulation time 1770415413 ps
CPU time 6.45 seconds
Started Apr 30 01:07:55 PM PDT 24
Finished Apr 30 01:08:02 PM PDT 24
Peak memory 201096 kb
Host smart-21dc12d8-dd49-4066-bf56-a8eb28a1f330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209961447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.209961447
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1048964373
Short name T479
Test name
Test status
Simulation time 102272775 ps
CPU time 0.99 seconds
Started Apr 30 01:07:54 PM PDT 24
Finished Apr 30 01:07:56 PM PDT 24
Peak memory 200904 kb
Host smart-57a1cb97-d15c-4863-ba90-09442b2943c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048964373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1048964373
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3912205883
Short name T159
Test name
Test status
Simulation time 116163032 ps
CPU time 1.12 seconds
Started Apr 30 01:07:54 PM PDT 24
Finished Apr 30 01:07:55 PM PDT 24
Peak memory 201068 kb
Host smart-b97a0627-3111-41c4-8018-5169842fd147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912205883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3912205883
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2785626387
Short name T255
Test name
Test status
Simulation time 13043428211 ps
CPU time 40.9 seconds
Started Apr 30 01:07:53 PM PDT 24
Finished Apr 30 01:08:34 PM PDT 24
Peak memory 201188 kb
Host smart-841cf15c-941f-47c5-9775-7bef7f3ec237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785626387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2785626387
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.4028277058
Short name T225
Test name
Test status
Simulation time 131207006 ps
CPU time 1.6 seconds
Started Apr 30 01:07:51 PM PDT 24
Finished Apr 30 01:07:53 PM PDT 24
Peak memory 209060 kb
Host smart-8878cdd9-1b27-4e37-87eb-8f6cc58cf5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028277058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4028277058
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.922269467
Short name T477
Test name
Test status
Simulation time 157073030 ps
CPU time 1.23 seconds
Started Apr 30 01:07:52 PM PDT 24
Finished Apr 30 01:07:54 PM PDT 24
Peak memory 201048 kb
Host smart-bc0e17b7-8173-4f5d-90a8-4a92575b2d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922269467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.922269467
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.156498447
Short name T203
Test name
Test status
Simulation time 383080975 ps
CPU time 1.42 seconds
Started Apr 30 01:08:04 PM PDT 24
Finished Apr 30 01:08:05 PM PDT 24
Peak memory 200668 kb
Host smart-0578b818-247e-44a0-83dd-9c9f2620e8ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156498447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.156498447
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3644631187
Short name T38
Test name
Test status
Simulation time 1215966730 ps
CPU time 6.15 seconds
Started Apr 30 01:08:06 PM PDT 24
Finished Apr 30 01:08:13 PM PDT 24
Peak memory 217588 kb
Host smart-c75c26ff-2c16-40d3-9bb1-ce2ee4e71a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644631187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3644631187
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1303125449
Short name T491
Test name
Test status
Simulation time 244111436 ps
CPU time 1.05 seconds
Started Apr 30 01:08:06 PM PDT 24
Finished Apr 30 01:08:07 PM PDT 24
Peak memory 218016 kb
Host smart-2a394a50-679d-416a-a56d-eb755967c5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303125449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1303125449
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2560320136
Short name T20
Test name
Test status
Simulation time 117618969 ps
CPU time 0.79 seconds
Started Apr 30 01:08:00 PM PDT 24
Finished Apr 30 01:08:01 PM PDT 24
Peak memory 200652 kb
Host smart-1a666356-706d-4863-a5bb-03322c15dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560320136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2560320136
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2108125509
Short name T105
Test name
Test status
Simulation time 1698544378 ps
CPU time 6.46 seconds
Started Apr 30 01:08:08 PM PDT 24
Finished Apr 30 01:08:15 PM PDT 24
Peak memory 201056 kb
Host smart-88781f84-d4bc-451c-b35a-0c40c7da1af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108125509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2108125509
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1346550483
Short name T152
Test name
Test status
Simulation time 100033616 ps
CPU time 1.03 seconds
Started Apr 30 01:08:05 PM PDT 24
Finished Apr 30 01:08:07 PM PDT 24
Peak memory 200808 kb
Host smart-bd47ba3b-5f45-45a1-b2f5-c9831ffd1582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346550483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1346550483
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.385796305
Short name T484
Test name
Test status
Simulation time 250446505 ps
CPU time 1.49 seconds
Started Apr 30 01:07:53 PM PDT 24
Finished Apr 30 01:07:55 PM PDT 24
Peak memory 201068 kb
Host smart-2972e6dd-cbc8-4104-ac35-1ef447a6a306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385796305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.385796305
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.500132199
Short name T402
Test name
Test status
Simulation time 167950276 ps
CPU time 1.18 seconds
Started Apr 30 01:08:07 PM PDT 24
Finished Apr 30 01:08:08 PM PDT 24
Peak memory 200848 kb
Host smart-03a7ccaa-cf2c-46a9-af19-7a4f1c31a2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500132199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.500132199
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1787210300
Short name T326
Test name
Test status
Simulation time 140442078 ps
CPU time 1.86 seconds
Started Apr 30 01:08:05 PM PDT 24
Finished Apr 30 01:08:07 PM PDT 24
Peak memory 200776 kb
Host smart-0bb1f9ef-8e05-4709-b3c1-0a4cbcecb3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787210300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1787210300
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.775187416
Short name T496
Test name
Test status
Simulation time 79203322 ps
CPU time 0.86 seconds
Started Apr 30 01:08:07 PM PDT 24
Finished Apr 30 01:08:08 PM PDT 24
Peak memory 200876 kb
Host smart-ac402a94-fef3-4dcb-9ff5-97b6dfb274d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775187416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.775187416
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1813228840
Short name T167
Test name
Test status
Simulation time 78196687 ps
CPU time 0.76 seconds
Started Apr 30 01:08:17 PM PDT 24
Finished Apr 30 01:08:18 PM PDT 24
Peak memory 200600 kb
Host smart-ade3c3d4-1b98-4228-97d2-9ff70c13ea89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813228840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1813228840
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.976520442
Short name T39
Test name
Test status
Simulation time 2174003703 ps
CPU time 8.08 seconds
Started Apr 30 01:08:13 PM PDT 24
Finished Apr 30 01:08:21 PM PDT 24
Peak memory 222232 kb
Host smart-227d4e6a-40ac-47d3-b240-d3cb018271d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976520442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.976520442
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4164770056
Short name T497
Test name
Test status
Simulation time 244660131 ps
CPU time 1.09 seconds
Started Apr 30 01:08:16 PM PDT 24
Finished Apr 30 01:08:17 PM PDT 24
Peak memory 218028 kb
Host smart-bc6503a1-5dbc-421d-b3a2-8295ff9c63e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164770056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.4164770056
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2238748970
Short name T190
Test name
Test status
Simulation time 145624753 ps
CPU time 0.87 seconds
Started Apr 30 01:08:07 PM PDT 24
Finished Apr 30 01:08:08 PM PDT 24
Peak memory 200684 kb
Host smart-9f4215b7-c2fe-4e23-8f4b-6f23acbe39b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238748970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2238748970
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2397488202
Short name T307
Test name
Test status
Simulation time 1622880150 ps
CPU time 6.3 seconds
Started Apr 30 01:08:06 PM PDT 24
Finished Apr 30 01:08:12 PM PDT 24
Peak memory 201076 kb
Host smart-da401529-0a05-46d5-82f8-d53f2c5eb35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397488202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2397488202
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2542717362
Short name T31
Test name
Test status
Simulation time 113568463 ps
CPU time 1.05 seconds
Started Apr 30 01:08:17 PM PDT 24
Finished Apr 30 01:08:18 PM PDT 24
Peak memory 200772 kb
Host smart-16bcae85-bb3d-4c82-8339-f059c8889089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542717362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2542717362
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3305841825
Short name T471
Test name
Test status
Simulation time 119320723 ps
CPU time 1.18 seconds
Started Apr 30 01:08:05 PM PDT 24
Finished Apr 30 01:08:07 PM PDT 24
Peak memory 201092 kb
Host smart-61681355-9943-447c-a94e-8c33184a1002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305841825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3305841825
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2179832046
Short name T502
Test name
Test status
Simulation time 15093077036 ps
CPU time 49.5 seconds
Started Apr 30 01:08:12 PM PDT 24
Finished Apr 30 01:09:02 PM PDT 24
Peak memory 209392 kb
Host smart-0a3c0f57-cd23-4e8e-9f88-07456599b248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179832046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2179832046
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.85364765
Short name T146
Test name
Test status
Simulation time 62911357 ps
CPU time 0.78 seconds
Started Apr 30 01:08:20 PM PDT 24
Finished Apr 30 01:08:22 PM PDT 24
Peak memory 200556 kb
Host smart-38a15dac-98f2-4f09-b4c9-cbf5a43d85e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85364765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.85364765
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1129972427
Short name T443
Test name
Test status
Simulation time 1894094536 ps
CPU time 6.81 seconds
Started Apr 30 01:08:21 PM PDT 24
Finished Apr 30 01:08:28 PM PDT 24
Peak memory 218548 kb
Host smart-cd813e04-4c32-4a85-9902-593a728cc6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129972427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1129972427
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3577972975
Short name T472
Test name
Test status
Simulation time 244245629 ps
CPU time 1.02 seconds
Started Apr 30 01:08:18 PM PDT 24
Finished Apr 30 01:08:19 PM PDT 24
Peak memory 218012 kb
Host smart-7d9ade10-afca-471f-84f1-988abd21517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577972975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3577972975
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3051411152
Short name T339
Test name
Test status
Simulation time 99657188 ps
CPU time 0.78 seconds
Started Apr 30 01:08:16 PM PDT 24
Finished Apr 30 01:08:18 PM PDT 24
Peak memory 200616 kb
Host smart-edefdc1a-2f71-40fc-baa2-78d6cc3a5c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051411152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3051411152
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3152873883
Short name T362
Test name
Test status
Simulation time 1801755830 ps
CPU time 6.98 seconds
Started Apr 30 01:08:11 PM PDT 24
Finished Apr 30 01:08:18 PM PDT 24
Peak memory 201076 kb
Host smart-034c793c-455a-4234-9b7a-847f4408cc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152873883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3152873883
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3656655953
Short name T451
Test name
Test status
Simulation time 110528275 ps
CPU time 1.02 seconds
Started Apr 30 01:08:20 PM PDT 24
Finished Apr 30 01:08:22 PM PDT 24
Peak memory 200844 kb
Host smart-8be93d8e-21fa-4ef0-8845-8f6ad532eaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656655953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3656655953
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3768888197
Short name T409
Test name
Test status
Simulation time 125526613 ps
CPU time 1.24 seconds
Started Apr 30 01:08:13 PM PDT 24
Finished Apr 30 01:08:15 PM PDT 24
Peak memory 201056 kb
Host smart-8ae7727e-c870-4000-95ee-69afdc019434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768888197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3768888197
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1801892974
Short name T449
Test name
Test status
Simulation time 1357203864 ps
CPU time 6.97 seconds
Started Apr 30 01:08:19 PM PDT 24
Finished Apr 30 01:08:26 PM PDT 24
Peak memory 209236 kb
Host smart-663684ee-039f-4514-b274-ae149d833153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801892974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1801892974
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.537915027
Short name T378
Test name
Test status
Simulation time 325607841 ps
CPU time 2.2 seconds
Started Apr 30 01:08:18 PM PDT 24
Finished Apr 30 01:08:21 PM PDT 24
Peak memory 200768 kb
Host smart-a8a000bb-3b12-4862-aae1-3b5427c56ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537915027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.537915027
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3220960891
Short name T267
Test name
Test status
Simulation time 249567960 ps
CPU time 1.47 seconds
Started Apr 30 01:08:17 PM PDT 24
Finished Apr 30 01:08:19 PM PDT 24
Peak memory 200780 kb
Host smart-ef0afe70-c7e3-48a2-ba43-81bea0a95a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220960891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3220960891
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.777969827
Short name T458
Test name
Test status
Simulation time 58317644 ps
CPU time 0.73 seconds
Started Apr 30 01:08:18 PM PDT 24
Finished Apr 30 01:08:19 PM PDT 24
Peak memory 200576 kb
Host smart-ad4f4839-88f9-4eab-a44f-037a0187cebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777969827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.777969827
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3919295627
Short name T284
Test name
Test status
Simulation time 244119869 ps
CPU time 1.15 seconds
Started Apr 30 01:08:20 PM PDT 24
Finished Apr 30 01:08:22 PM PDT 24
Peak memory 218060 kb
Host smart-9cdf0c41-3569-48f1-9e2f-f313337dba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919295627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3919295627
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3227749986
Short name T416
Test name
Test status
Simulation time 126864742 ps
CPU time 0.78 seconds
Started Apr 30 01:08:19 PM PDT 24
Finished Apr 30 01:08:20 PM PDT 24
Peak memory 200624 kb
Host smart-3c9c7594-d60b-463d-b64a-2f7fbe61299a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227749986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3227749986
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.783399689
Short name T222
Test name
Test status
Simulation time 864279138 ps
CPU time 4.44 seconds
Started Apr 30 01:08:19 PM PDT 24
Finished Apr 30 01:08:24 PM PDT 24
Peak memory 201080 kb
Host smart-f5422f99-6b4f-4773-93b3-eb171b05f153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783399689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.783399689
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3262568891
Short name T180
Test name
Test status
Simulation time 147273712 ps
CPU time 1.06 seconds
Started Apr 30 01:08:21 PM PDT 24
Finished Apr 30 01:08:23 PM PDT 24
Peak memory 200788 kb
Host smart-fe6874e3-f52b-412c-8293-575d990ae956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262568891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3262568891
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2477861513
Short name T405
Test name
Test status
Simulation time 107657949 ps
CPU time 1.15 seconds
Started Apr 30 01:08:18 PM PDT 24
Finished Apr 30 01:08:19 PM PDT 24
Peak memory 201068 kb
Host smart-9b828f52-bb58-4acd-ace2-ac3974429638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477861513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2477861513
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.920571019
Short name T328
Test name
Test status
Simulation time 970418910 ps
CPU time 4.86 seconds
Started Apr 30 01:08:21 PM PDT 24
Finished Apr 30 01:08:26 PM PDT 24
Peak memory 201116 kb
Host smart-379d232b-7ee9-4405-bb9c-34ee9f438f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920571019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.920571019
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.993336169
Short name T347
Test name
Test status
Simulation time 552211242 ps
CPU time 2.9 seconds
Started Apr 30 01:08:22 PM PDT 24
Finished Apr 30 01:08:25 PM PDT 24
Peak memory 200908 kb
Host smart-1d9e09fe-153f-44f4-be53-d08bcddfa5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993336169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.993336169
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2421807712
Short name T248
Test name
Test status
Simulation time 156523614 ps
CPU time 1.23 seconds
Started Apr 30 01:08:20 PM PDT 24
Finished Apr 30 01:08:22 PM PDT 24
Peak memory 201004 kb
Host smart-cae554e2-2770-4680-b5a4-4b1f11899b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421807712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2421807712
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1344359474
Short name T346
Test name
Test status
Simulation time 65663140 ps
CPU time 0.76 seconds
Started Apr 30 01:08:28 PM PDT 24
Finished Apr 30 01:08:29 PM PDT 24
Peak memory 200652 kb
Host smart-3b8a5e95-43c1-4d80-8699-4e8ebde0f511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344359474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1344359474
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2667915175
Short name T392
Test name
Test status
Simulation time 1884130645 ps
CPU time 7.01 seconds
Started Apr 30 01:08:29 PM PDT 24
Finished Apr 30 01:08:36 PM PDT 24
Peak memory 218468 kb
Host smart-21e4c63b-a7ae-4e32-88dc-758630ab66a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667915175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2667915175
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1458595224
Short name T297
Test name
Test status
Simulation time 245148748 ps
CPU time 1.08 seconds
Started Apr 30 01:08:28 PM PDT 24
Finished Apr 30 01:08:30 PM PDT 24
Peak memory 218104 kb
Host smart-fde964f7-a4b8-4a5f-b896-b245e0275d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458595224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1458595224
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1402713670
Short name T19
Test name
Test status
Simulation time 166749975 ps
CPU time 0.83 seconds
Started Apr 30 01:08:20 PM PDT 24
Finished Apr 30 01:08:22 PM PDT 24
Peak memory 200672 kb
Host smart-4e19d8da-6213-4719-b10e-4973e53aed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402713670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1402713670
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.690916701
Short name T46
Test name
Test status
Simulation time 1355126087 ps
CPU time 5.84 seconds
Started Apr 30 01:08:20 PM PDT 24
Finished Apr 30 01:08:26 PM PDT 24
Peak memory 201028 kb
Host smart-c08d7ddb-f58b-45ff-a778-21707aed182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690916701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.690916701
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2558257808
Short name T514
Test name
Test status
Simulation time 100953904 ps
CPU time 0.95 seconds
Started Apr 30 01:08:26 PM PDT 24
Finished Apr 30 01:08:27 PM PDT 24
Peak memory 200828 kb
Host smart-8311b1dd-41b0-44d5-8706-304263d52b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558257808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2558257808
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.833514971
Short name T162
Test name
Test status
Simulation time 195442084 ps
CPU time 1.41 seconds
Started Apr 30 01:08:20 PM PDT 24
Finished Apr 30 01:08:22 PM PDT 24
Peak memory 201040 kb
Host smart-7e385f4d-323f-4023-b5b8-1757696d543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833514971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.833514971
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.184086266
Short name T164
Test name
Test status
Simulation time 3081313633 ps
CPU time 14.16 seconds
Started Apr 30 01:08:28 PM PDT 24
Finished Apr 30 01:08:43 PM PDT 24
Peak memory 201160 kb
Host smart-df1d9876-8e1f-43e4-8e09-8b7f4feb9edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184086266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.184086266
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.155740461
Short name T93
Test name
Test status
Simulation time 278286192 ps
CPU time 1.7 seconds
Started Apr 30 01:08:28 PM PDT 24
Finished Apr 30 01:08:30 PM PDT 24
Peak memory 200896 kb
Host smart-48efd3bc-5cb5-4923-bce3-a587533571a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155740461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.155740461
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3229549571
Short name T136
Test name
Test status
Simulation time 101364015 ps
CPU time 0.86 seconds
Started Apr 30 01:08:27 PM PDT 24
Finished Apr 30 01:08:28 PM PDT 24
Peak memory 200848 kb
Host smart-dc7826ce-a28b-482e-bf10-e6e4df7c9ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229549571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3229549571
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1401667313
Short name T233
Test name
Test status
Simulation time 84989522 ps
CPU time 0.85 seconds
Started Apr 30 01:06:02 PM PDT 24
Finished Apr 30 01:06:03 PM PDT 24
Peak memory 200732 kb
Host smart-d3d63f96-47ff-4edd-9c81-1d84112e7f33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401667313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1401667313
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.187271794
Short name T494
Test name
Test status
Simulation time 2170665857 ps
CPU time 7.49 seconds
Started Apr 30 01:05:55 PM PDT 24
Finished Apr 30 01:06:03 PM PDT 24
Peak memory 222308 kb
Host smart-c3b3fba2-34d5-4a89-974f-8f022057b696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187271794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.187271794
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2792475004
Short name T504
Test name
Test status
Simulation time 244110097 ps
CPU time 1.12 seconds
Started Apr 30 01:05:55 PM PDT 24
Finished Apr 30 01:05:57 PM PDT 24
Peak memory 218084 kb
Host smart-080c2369-39e6-48fb-81ad-cdfe75adafa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792475004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2792475004
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3312590859
Short name T17
Test name
Test status
Simulation time 163699382 ps
CPU time 0.93 seconds
Started Apr 30 01:05:44 PM PDT 24
Finished Apr 30 01:05:45 PM PDT 24
Peak memory 200576 kb
Host smart-6cac170f-6e04-4595-83c2-4afc367913a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312590859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3312590859
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2000262630
Short name T368
Test name
Test status
Simulation time 852206893 ps
CPU time 4.55 seconds
Started Apr 30 01:05:49 PM PDT 24
Finished Apr 30 01:05:54 PM PDT 24
Peak memory 201024 kb
Host smart-3ccf1039-a360-4821-b6fa-65d816bd2a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000262630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2000262630
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.731859785
Short name T539
Test name
Test status
Simulation time 106273050 ps
CPU time 0.97 seconds
Started Apr 30 01:05:51 PM PDT 24
Finished Apr 30 01:05:52 PM PDT 24
Peak memory 200916 kb
Host smart-06304c25-a641-4010-9538-f3e5ddc23cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731859785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.731859785
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.211767518
Short name T314
Test name
Test status
Simulation time 251865606 ps
CPU time 1.43 seconds
Started Apr 30 01:05:45 PM PDT 24
Finished Apr 30 01:05:46 PM PDT 24
Peak memory 201052 kb
Host smart-68b7973c-59ea-4648-a7a3-d823e467ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211767518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.211767518
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.897202258
Short name T535
Test name
Test status
Simulation time 1881375922 ps
CPU time 6.69 seconds
Started Apr 30 01:05:54 PM PDT 24
Finished Apr 30 01:06:01 PM PDT 24
Peak memory 209288 kb
Host smart-18b86469-2ceb-4469-873f-c20678382d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897202258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.897202258
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3730716128
Short name T350
Test name
Test status
Simulation time 148077665 ps
CPU time 1.86 seconds
Started Apr 30 01:05:50 PM PDT 24
Finished Apr 30 01:05:52 PM PDT 24
Peak memory 200868 kb
Host smart-1713d722-0c3d-40c0-b5f4-9b968c9d9d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730716128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3730716128
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1852210512
Short name T318
Test name
Test status
Simulation time 199499664 ps
CPU time 1.33 seconds
Started Apr 30 01:05:49 PM PDT 24
Finished Apr 30 01:05:51 PM PDT 24
Peak memory 200868 kb
Host smart-e2a25c9c-d920-4f68-9969-c05989747d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852210512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1852210512
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3355492744
Short name T176
Test name
Test status
Simulation time 68871870 ps
CPU time 0.74 seconds
Started Apr 30 01:08:37 PM PDT 24
Finished Apr 30 01:08:38 PM PDT 24
Peak memory 200688 kb
Host smart-d7c7649d-a699-49e3-a7e1-57277c996a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355492744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3355492744
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3300729045
Short name T62
Test name
Test status
Simulation time 2173259530 ps
CPU time 7.7 seconds
Started Apr 30 01:08:34 PM PDT 24
Finished Apr 30 01:08:42 PM PDT 24
Peak memory 218196 kb
Host smart-501646f8-e79e-4b13-824f-6d6cbdb6423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300729045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3300729045
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2967680596
Short name T533
Test name
Test status
Simulation time 243916370 ps
CPU time 1.14 seconds
Started Apr 30 01:08:35 PM PDT 24
Finished Apr 30 01:08:37 PM PDT 24
Peak memory 218128 kb
Host smart-11768b7a-c6ca-4213-92e8-d322f8f7fcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967680596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2967680596
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1584885088
Short name T18
Test name
Test status
Simulation time 185542148 ps
CPU time 0.83 seconds
Started Apr 30 01:08:35 PM PDT 24
Finished Apr 30 01:08:36 PM PDT 24
Peak memory 200316 kb
Host smart-581dedbc-0d6f-469a-a450-1d8a3546e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584885088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1584885088
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2200207053
Short name T245
Test name
Test status
Simulation time 870952001 ps
CPU time 5.05 seconds
Started Apr 30 01:08:36 PM PDT 24
Finished Apr 30 01:08:41 PM PDT 24
Peak memory 201276 kb
Host smart-b214771b-2930-4b94-802c-dfc1ab134743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200207053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2200207053
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.406751917
Short name T182
Test name
Test status
Simulation time 189582048 ps
CPU time 1.19 seconds
Started Apr 30 01:08:35 PM PDT 24
Finished Apr 30 01:08:36 PM PDT 24
Peak memory 200904 kb
Host smart-ec6327be-e6be-4bea-bcf6-63251a957612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406751917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.406751917
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.815616283
Short name T199
Test name
Test status
Simulation time 242361661 ps
CPU time 1.6 seconds
Started Apr 30 01:08:29 PM PDT 24
Finished Apr 30 01:08:31 PM PDT 24
Peak memory 200984 kb
Host smart-3a268c5f-49c5-4d29-bf40-6d57e903611d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815616283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.815616283
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.491268508
Short name T282
Test name
Test status
Simulation time 11383742349 ps
CPU time 41.03 seconds
Started Apr 30 01:08:34 PM PDT 24
Finished Apr 30 01:09:16 PM PDT 24
Peak memory 210536 kb
Host smart-35883b3b-898c-444c-b69f-6b6a2ea5ae48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491268508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.491268508
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.234583552
Short name T258
Test name
Test status
Simulation time 299292325 ps
CPU time 1.96 seconds
Started Apr 30 01:08:34 PM PDT 24
Finished Apr 30 01:08:36 PM PDT 24
Peak memory 209104 kb
Host smart-414ccab8-d149-4c79-9ba9-953ed977a508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234583552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.234583552
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2350029190
Short name T205
Test name
Test status
Simulation time 90522061 ps
CPU time 0.89 seconds
Started Apr 30 01:08:36 PM PDT 24
Finished Apr 30 01:08:37 PM PDT 24
Peak memory 200824 kb
Host smart-7914ac2d-7c72-4849-8f9a-c22dbd13e5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350029190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2350029190
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2941345308
Short name T407
Test name
Test status
Simulation time 62953375 ps
CPU time 0.73 seconds
Started Apr 30 01:08:48 PM PDT 24
Finished Apr 30 01:08:50 PM PDT 24
Peak memory 200696 kb
Host smart-ff3ebf5e-30c6-4fee-b047-89178bde0740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941345308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2941345308
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2006072037
Short name T430
Test name
Test status
Simulation time 1886626125 ps
CPU time 7.2 seconds
Started Apr 30 01:08:48 PM PDT 24
Finished Apr 30 01:08:55 PM PDT 24
Peak memory 217548 kb
Host smart-e98a4d56-158b-4389-bfbc-4d4f5f78c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006072037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2006072037
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3886928293
Short name T461
Test name
Test status
Simulation time 244319638 ps
CPU time 1.1 seconds
Started Apr 30 01:08:49 PM PDT 24
Finished Apr 30 01:08:50 PM PDT 24
Peak memory 218180 kb
Host smart-c2a0eebf-ab9b-4f7c-96e2-584854ecfd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886928293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3886928293
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3602173374
Short name T302
Test name
Test status
Simulation time 97785942 ps
CPU time 0.75 seconds
Started Apr 30 01:08:34 PM PDT 24
Finished Apr 30 01:08:35 PM PDT 24
Peak memory 200700 kb
Host smart-bbb561ff-5548-4d66-9d9e-141e22056e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602173374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3602173374
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.742770466
Short name T220
Test name
Test status
Simulation time 844613659 ps
CPU time 4.31 seconds
Started Apr 30 01:08:35 PM PDT 24
Finished Apr 30 01:08:39 PM PDT 24
Peak memory 200640 kb
Host smart-04dd9e64-7fd2-4acd-86c7-b201d1ca4d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742770466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.742770466
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3256247494
Short name T506
Test name
Test status
Simulation time 185284807 ps
CPU time 1.24 seconds
Started Apr 30 01:08:41 PM PDT 24
Finished Apr 30 01:08:42 PM PDT 24
Peak memory 200836 kb
Host smart-5f1c2613-1995-4818-a25e-c7e2da28ed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256247494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3256247494
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1933398968
Short name T188
Test name
Test status
Simulation time 254328338 ps
CPU time 1.58 seconds
Started Apr 30 01:08:35 PM PDT 24
Finished Apr 30 01:08:37 PM PDT 24
Peak memory 201068 kb
Host smart-0ebcaf60-2349-4a6b-b89b-93926c70f78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933398968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1933398968
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2368937102
Short name T34
Test name
Test status
Simulation time 2037706208 ps
CPU time 7.61 seconds
Started Apr 30 01:08:47 PM PDT 24
Finished Apr 30 01:08:55 PM PDT 24
Peak memory 201004 kb
Host smart-92668b8e-d0f9-4d7e-836e-af16a4af9391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368937102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2368937102
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.357482326
Short name T363
Test name
Test status
Simulation time 390455277 ps
CPU time 2.06 seconds
Started Apr 30 01:08:41 PM PDT 24
Finished Apr 30 01:08:44 PM PDT 24
Peak memory 200900 kb
Host smart-3db89184-4ece-47b9-9a38-9a4767cee0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357482326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.357482326
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1586880832
Short name T234
Test name
Test status
Simulation time 71023754 ps
CPU time 0.79 seconds
Started Apr 30 01:08:40 PM PDT 24
Finished Apr 30 01:08:41 PM PDT 24
Peak memory 200868 kb
Host smart-9af2ed90-f2cf-40f9-9974-178dd15d7db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586880832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1586880832
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.413807557
Short name T336
Test name
Test status
Simulation time 90068495 ps
CPU time 0.84 seconds
Started Apr 30 01:08:55 PM PDT 24
Finished Apr 30 01:08:56 PM PDT 24
Peak memory 200668 kb
Host smart-24f2a13a-39b8-4974-91f0-e3c4b0f10698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413807557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.413807557
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3460559649
Short name T272
Test name
Test status
Simulation time 2365598730 ps
CPU time 8.14 seconds
Started Apr 30 01:08:47 PM PDT 24
Finished Apr 30 01:08:56 PM PDT 24
Peak memory 218664 kb
Host smart-128dc72c-df0e-4433-a1bc-1228663ed5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460559649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3460559649
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4244402164
Short name T144
Test name
Test status
Simulation time 244695305 ps
CPU time 1.19 seconds
Started Apr 30 01:08:50 PM PDT 24
Finished Apr 30 01:08:51 PM PDT 24
Peak memory 218312 kb
Host smart-dbc3f712-5e36-4770-ba2e-684990100c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244402164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.4244402164
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4254452726
Short name T323
Test name
Test status
Simulation time 167904767 ps
CPU time 0.86 seconds
Started Apr 30 01:08:48 PM PDT 24
Finished Apr 30 01:08:49 PM PDT 24
Peak memory 200632 kb
Host smart-3bf11a27-23de-4a45-b63c-cc3017a72db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254452726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4254452726
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1894862767
Short name T490
Test name
Test status
Simulation time 1386246418 ps
CPU time 5.4 seconds
Started Apr 30 01:08:48 PM PDT 24
Finished Apr 30 01:08:54 PM PDT 24
Peak memory 201036 kb
Host smart-579acce2-757d-4979-a3e5-379e0868ba54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894862767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1894862767
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.727086712
Short name T239
Test name
Test status
Simulation time 177610896 ps
CPU time 1.2 seconds
Started Apr 30 01:08:47 PM PDT 24
Finished Apr 30 01:08:49 PM PDT 24
Peak memory 200764 kb
Host smart-157958b3-f6bb-43ed-9e9c-1eefcbef7114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727086712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.727086712
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2031254092
Short name T95
Test name
Test status
Simulation time 124208425 ps
CPU time 1.23 seconds
Started Apr 30 01:08:48 PM PDT 24
Finished Apr 30 01:08:50 PM PDT 24
Peak memory 201064 kb
Host smart-671b0392-1e1c-496a-89d3-2139a225b737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031254092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2031254092
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2607801627
Short name T224
Test name
Test status
Simulation time 8011594916 ps
CPU time 28.4 seconds
Started Apr 30 01:08:54 PM PDT 24
Finished Apr 30 01:09:23 PM PDT 24
Peak memory 201188 kb
Host smart-e6fc78bd-3ce6-428a-ab09-1372c923c497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607801627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2607801627
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2201613414
Short name T455
Test name
Test status
Simulation time 479618742 ps
CPU time 2.79 seconds
Started Apr 30 01:08:49 PM PDT 24
Finished Apr 30 01:08:53 PM PDT 24
Peak memory 200860 kb
Host smart-8a7d6082-bc5b-44d5-9bda-be9fa40ea085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201613414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2201613414
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2631793646
Short name T14
Test name
Test status
Simulation time 80903447 ps
CPU time 0.86 seconds
Started Apr 30 01:08:47 PM PDT 24
Finished Apr 30 01:08:48 PM PDT 24
Peak memory 200804 kb
Host smart-3ad1c83a-c05d-4be2-9d64-4d2f99e8a3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631793646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2631793646
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.332630973
Short name T150
Test name
Test status
Simulation time 75733059 ps
CPU time 0.77 seconds
Started Apr 30 01:08:54 PM PDT 24
Finished Apr 30 01:08:55 PM PDT 24
Peak memory 200652 kb
Host smart-e2e0b292-7997-45b0-9c75-0bf99bb89ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332630973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.332630973
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2990925204
Short name T403
Test name
Test status
Simulation time 243790794 ps
CPU time 1.09 seconds
Started Apr 30 01:08:56 PM PDT 24
Finished Apr 30 01:08:58 PM PDT 24
Peak memory 218180 kb
Host smart-4afd805f-0e8d-448f-ba9a-dd9d77e3a667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990925204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2990925204
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.536254519
Short name T223
Test name
Test status
Simulation time 137655987 ps
CPU time 0.82 seconds
Started Apr 30 01:08:55 PM PDT 24
Finished Apr 30 01:08:57 PM PDT 24
Peak memory 200696 kb
Host smart-4d021ecb-0464-4c27-8763-12e9196d6e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536254519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.536254519
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1576391940
Short name T432
Test name
Test status
Simulation time 1001613448 ps
CPU time 5.03 seconds
Started Apr 30 01:08:56 PM PDT 24
Finished Apr 30 01:09:02 PM PDT 24
Peak memory 201060 kb
Host smart-659553de-9011-404b-ab27-855e54425c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576391940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1576391940
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3026433088
Short name T84
Test name
Test status
Simulation time 153150506 ps
CPU time 1.13 seconds
Started Apr 30 01:08:56 PM PDT 24
Finished Apr 30 01:08:58 PM PDT 24
Peak memory 200900 kb
Host smart-04881ba5-f529-4fb9-ab33-dca24fa26074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026433088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3026433088
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1531897952
Short name T185
Test name
Test status
Simulation time 245947337 ps
CPU time 1.53 seconds
Started Apr 30 01:08:55 PM PDT 24
Finished Apr 30 01:08:57 PM PDT 24
Peak memory 201036 kb
Host smart-7cc47549-3042-4057-96d5-ea9933544a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531897952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1531897952
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1479187062
Short name T371
Test name
Test status
Simulation time 1271502446 ps
CPU time 5.41 seconds
Started Apr 30 01:08:59 PM PDT 24
Finished Apr 30 01:09:04 PM PDT 24
Peak memory 201032 kb
Host smart-d5fc9ada-e464-42f9-be0c-9c8ab6bc3912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479187062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1479187062
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3606171519
Short name T251
Test name
Test status
Simulation time 432610371 ps
CPU time 2.36 seconds
Started Apr 30 01:08:56 PM PDT 24
Finished Apr 30 01:08:59 PM PDT 24
Peak memory 200820 kb
Host smart-eb03078d-1d32-4ce1-abf3-450af7355b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606171519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3606171519
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4006975276
Short name T513
Test name
Test status
Simulation time 159540085 ps
CPU time 1.11 seconds
Started Apr 30 01:08:56 PM PDT 24
Finished Apr 30 01:08:58 PM PDT 24
Peak memory 200848 kb
Host smart-1780f409-1ccd-4006-b8a4-e69711f1bbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006975276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4006975276
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.399805484
Short name T381
Test name
Test status
Simulation time 61828138 ps
CPU time 0.73 seconds
Started Apr 30 01:09:02 PM PDT 24
Finished Apr 30 01:09:03 PM PDT 24
Peak memory 200664 kb
Host smart-1eb2d261-d1b6-477b-9e34-cc9bba7038de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399805484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.399805484
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.915328495
Short name T11
Test name
Test status
Simulation time 2368668821 ps
CPU time 7.98 seconds
Started Apr 30 01:08:55 PM PDT 24
Finished Apr 30 01:09:03 PM PDT 24
Peak memory 222540 kb
Host smart-10c384f3-caf1-47ed-96a5-ba990c01a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915328495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.915328495
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1518776493
Short name T352
Test name
Test status
Simulation time 244743815 ps
CPU time 1.03 seconds
Started Apr 30 01:08:55 PM PDT 24
Finished Apr 30 01:08:57 PM PDT 24
Peak memory 218084 kb
Host smart-78f009e2-b130-42c1-8d61-d36351fa7b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518776493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1518776493
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2607409861
Short name T275
Test name
Test status
Simulation time 199361648 ps
CPU time 0.84 seconds
Started Apr 30 01:08:55 PM PDT 24
Finished Apr 30 01:08:56 PM PDT 24
Peak memory 200620 kb
Host smart-a2d97ffb-164b-45e9-a6eb-34d13632c336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607409861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2607409861
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2498862249
Short name T173
Test name
Test status
Simulation time 1252616814 ps
CPU time 5.51 seconds
Started Apr 30 01:08:56 PM PDT 24
Finished Apr 30 01:09:02 PM PDT 24
Peak memory 201056 kb
Host smart-9fe8d4f1-4cb7-4cdc-9da8-28c97b80daeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498862249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2498862249
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3916053324
Short name T200
Test name
Test status
Simulation time 176447528 ps
CPU time 1.11 seconds
Started Apr 30 01:08:53 PM PDT 24
Finished Apr 30 01:08:55 PM PDT 24
Peak memory 200876 kb
Host smart-7bcfa505-33d2-4203-930d-4965c4287dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916053324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3916053324
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4179677664
Short name T366
Test name
Test status
Simulation time 128942082 ps
CPU time 1.18 seconds
Started Apr 30 01:08:56 PM PDT 24
Finished Apr 30 01:08:57 PM PDT 24
Peak memory 201024 kb
Host smart-72fb0459-18be-43a0-9acf-f8a654e71602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179677664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4179677664
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1770029089
Short name T133
Test name
Test status
Simulation time 9810160565 ps
CPU time 31.34 seconds
Started Apr 30 01:09:01 PM PDT 24
Finished Apr 30 01:09:33 PM PDT 24
Peak memory 209420 kb
Host smart-d9e5c8b8-7bc3-4905-ae0c-3e689d56e513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770029089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1770029089
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4178283563
Short name T202
Test name
Test status
Simulation time 412326242 ps
CPU time 2.25 seconds
Started Apr 30 01:08:55 PM PDT 24
Finished Apr 30 01:08:58 PM PDT 24
Peak memory 200860 kb
Host smart-55224e07-197f-4143-82c2-852703752d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178283563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4178283563
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3931093736
Short name T174
Test name
Test status
Simulation time 114690790 ps
CPU time 0.99 seconds
Started Apr 30 01:08:55 PM PDT 24
Finished Apr 30 01:08:57 PM PDT 24
Peak memory 200780 kb
Host smart-fe3a4104-c6ca-4484-8e9c-c7867d70a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931093736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3931093736
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1410660911
Short name T444
Test name
Test status
Simulation time 72108964 ps
CPU time 0.75 seconds
Started Apr 30 01:09:04 PM PDT 24
Finished Apr 30 01:09:05 PM PDT 24
Peak memory 200728 kb
Host smart-a2c97682-92eb-469f-b212-1c2a249a435d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410660911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1410660911
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3550893107
Short name T57
Test name
Test status
Simulation time 2359139851 ps
CPU time 7.53 seconds
Started Apr 30 01:09:00 PM PDT 24
Finished Apr 30 01:09:08 PM PDT 24
Peak memory 218648 kb
Host smart-3b9c98be-2cb5-4997-9484-276954f00b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550893107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3550893107
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4191220997
Short name T82
Test name
Test status
Simulation time 245374919 ps
CPU time 1.01 seconds
Started Apr 30 01:09:08 PM PDT 24
Finished Apr 30 01:09:09 PM PDT 24
Peak memory 218060 kb
Host smart-ab089863-aba3-48fb-95e6-0541bd1bb192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191220997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4191220997
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1764967903
Short name T263
Test name
Test status
Simulation time 185408534 ps
CPU time 0.91 seconds
Started Apr 30 01:09:08 PM PDT 24
Finished Apr 30 01:09:09 PM PDT 24
Peak memory 200648 kb
Host smart-af798d72-96bc-466f-a6b7-d3b9d63681b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764967903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1764967903
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1256417575
Short name T446
Test name
Test status
Simulation time 1035207799 ps
CPU time 4.96 seconds
Started Apr 30 01:09:05 PM PDT 24
Finished Apr 30 01:09:11 PM PDT 24
Peak memory 201028 kb
Host smart-8c9ed81c-2931-46b4-9961-3a488a537537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256417575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1256417575
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.493500352
Short name T58
Test name
Test status
Simulation time 153496722 ps
CPU time 1.04 seconds
Started Apr 30 01:08:59 PM PDT 24
Finished Apr 30 01:09:00 PM PDT 24
Peak memory 200880 kb
Host smart-073098c6-2290-435a-a142-9f7321bf1a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493500352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.493500352
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.498827312
Short name T247
Test name
Test status
Simulation time 236237935 ps
CPU time 1.34 seconds
Started Apr 30 01:09:00 PM PDT 24
Finished Apr 30 01:09:01 PM PDT 24
Peak memory 201004 kb
Host smart-4247b830-0ffd-44d2-96a4-6fd52f62b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498827312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.498827312
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.889070480
Short name T422
Test name
Test status
Simulation time 2657512902 ps
CPU time 12.16 seconds
Started Apr 30 01:08:59 PM PDT 24
Finished Apr 30 01:09:11 PM PDT 24
Peak memory 201112 kb
Host smart-86bfd916-4a84-4cee-9ed5-0a24bb881ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889070480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.889070480
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3893944716
Short name T192
Test name
Test status
Simulation time 362570841 ps
CPU time 2.54 seconds
Started Apr 30 01:09:00 PM PDT 24
Finished Apr 30 01:09:03 PM PDT 24
Peak memory 200756 kb
Host smart-fda77e45-63c5-46ee-aef9-45a4d22e3d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893944716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3893944716
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.272098673
Short name T309
Test name
Test status
Simulation time 79813649 ps
CPU time 0.82 seconds
Started Apr 30 01:09:00 PM PDT 24
Finished Apr 30 01:09:01 PM PDT 24
Peak memory 200904 kb
Host smart-0932fb6f-b76e-4e2e-b745-54fbd38f5ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272098673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.272098673
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2904609589
Short name T445
Test name
Test status
Simulation time 72274812 ps
CPU time 0.77 seconds
Started Apr 30 01:09:07 PM PDT 24
Finished Apr 30 01:09:08 PM PDT 24
Peak memory 200740 kb
Host smart-93f828d4-828f-499e-b74f-52162536ecc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904609589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2904609589
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2471314038
Short name T55
Test name
Test status
Simulation time 1224617852 ps
CPU time 5.21 seconds
Started Apr 30 01:09:05 PM PDT 24
Finished Apr 30 01:09:11 PM PDT 24
Peak memory 217664 kb
Host smart-3b7efc1f-ff20-44f7-af2b-018806d5c380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471314038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2471314038
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1766435832
Short name T434
Test name
Test status
Simulation time 243995390 ps
CPU time 1.11 seconds
Started Apr 30 01:09:06 PM PDT 24
Finished Apr 30 01:09:07 PM PDT 24
Peak memory 218072 kb
Host smart-d5300180-d560-4ff4-9fe0-c09fba637844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766435832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1766435832
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2780583877
Short name T22
Test name
Test status
Simulation time 141690779 ps
CPU time 0.82 seconds
Started Apr 30 01:09:00 PM PDT 24
Finished Apr 30 01:09:01 PM PDT 24
Peak memory 200680 kb
Host smart-6f54809c-0f24-4ac5-8259-51e598a773db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780583877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2780583877
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.127576368
Short name T425
Test name
Test status
Simulation time 1340589399 ps
CPU time 5.88 seconds
Started Apr 30 01:09:02 PM PDT 24
Finished Apr 30 01:09:08 PM PDT 24
Peak memory 201036 kb
Host smart-81c906dc-0070-487c-bf84-e8498a7c4931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127576368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.127576368
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3073312852
Short name T523
Test name
Test status
Simulation time 145415392 ps
CPU time 1.08 seconds
Started Apr 30 01:09:06 PM PDT 24
Finished Apr 30 01:09:07 PM PDT 24
Peak memory 200864 kb
Host smart-11e7fc2e-406d-4845-878c-bbf9c7186bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073312852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3073312852
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1411522309
Short name T426
Test name
Test status
Simulation time 122825220 ps
CPU time 1.19 seconds
Started Apr 30 01:09:08 PM PDT 24
Finished Apr 30 01:09:10 PM PDT 24
Peak memory 201024 kb
Host smart-3af89163-7ed4-47a7-8f03-30af61cee66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411522309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1411522309
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.313475086
Short name T169
Test name
Test status
Simulation time 475666999 ps
CPU time 2.54 seconds
Started Apr 30 01:09:07 PM PDT 24
Finished Apr 30 01:09:10 PM PDT 24
Peak memory 200860 kb
Host smart-948b47db-ee8b-40f3-935d-33915b84e410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313475086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.313475086
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2758353552
Short name T391
Test name
Test status
Simulation time 114740954 ps
CPU time 1.01 seconds
Started Apr 30 01:09:08 PM PDT 24
Finished Apr 30 01:09:09 PM PDT 24
Peak memory 200844 kb
Host smart-d76b02ea-02a9-4396-bd39-a865e26c90e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758353552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2758353552
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1416145190
Short name T59
Test name
Test status
Simulation time 59529041 ps
CPU time 0.71 seconds
Started Apr 30 01:09:18 PM PDT 24
Finished Apr 30 01:09:19 PM PDT 24
Peak memory 200600 kb
Host smart-32657e61-1c44-4638-9d6a-837615894b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416145190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1416145190
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2162454485
Short name T49
Test name
Test status
Simulation time 1226631173 ps
CPU time 5.31 seconds
Started Apr 30 01:09:11 PM PDT 24
Finished Apr 30 01:09:17 PM PDT 24
Peak memory 218584 kb
Host smart-a0bf8477-9417-4b31-bdaa-3a6cb622e372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162454485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2162454485
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2061773341
Short name T543
Test name
Test status
Simulation time 243999682 ps
CPU time 1.08 seconds
Started Apr 30 01:09:17 PM PDT 24
Finished Apr 30 01:09:18 PM PDT 24
Peak memory 218160 kb
Host smart-63aa23ef-471d-4669-b090-964fdd1fa974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061773341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2061773341
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.4034791786
Short name T400
Test name
Test status
Simulation time 80324349 ps
CPU time 0.72 seconds
Started Apr 30 01:09:10 PM PDT 24
Finished Apr 30 01:09:11 PM PDT 24
Peak memory 200652 kb
Host smart-83c08e8c-002a-41de-9658-490f33486de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034791786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.4034791786
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.442619782
Short name T489
Test name
Test status
Simulation time 1723453103 ps
CPU time 6.32 seconds
Started Apr 30 01:09:05 PM PDT 24
Finished Apr 30 01:09:12 PM PDT 24
Peak memory 201092 kb
Host smart-d1b92bf5-7d13-4a1b-852e-824f96cbf221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442619782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.442619782
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1709887382
Short name T266
Test name
Test status
Simulation time 145439493 ps
CPU time 1.1 seconds
Started Apr 30 01:09:06 PM PDT 24
Finished Apr 30 01:09:07 PM PDT 24
Peak memory 200828 kb
Host smart-d4cb13a9-3d4e-44e6-b48d-cbfbba09aae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709887382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1709887382
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.62033255
Short name T91
Test name
Test status
Simulation time 123571118 ps
CPU time 1.17 seconds
Started Apr 30 01:09:07 PM PDT 24
Finished Apr 30 01:09:09 PM PDT 24
Peak memory 201004 kb
Host smart-544cadc2-5819-4bd5-a015-37bd606adde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62033255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.62033255
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.947323428
Short name T354
Test name
Test status
Simulation time 679778392 ps
CPU time 3.17 seconds
Started Apr 30 01:09:12 PM PDT 24
Finished Apr 30 01:09:16 PM PDT 24
Peak memory 201012 kb
Host smart-5a4b011e-a3b2-47ef-a4ee-d9f7b1a33537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947323428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.947323428
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.645836660
Short name T450
Test name
Test status
Simulation time 340291652 ps
CPU time 2.13 seconds
Started Apr 30 01:09:07 PM PDT 24
Finished Apr 30 01:09:09 PM PDT 24
Peak memory 209068 kb
Host smart-830bfe75-f0a8-4340-b02a-017a5067c1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645836660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.645836660
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1831912028
Short name T231
Test name
Test status
Simulation time 186530614 ps
CPU time 1.21 seconds
Started Apr 30 01:09:06 PM PDT 24
Finished Apr 30 01:09:08 PM PDT 24
Peak memory 200912 kb
Host smart-f4b80129-f2f0-498b-8b98-6e1b5cfe3a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831912028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1831912028
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2157624266
Short name T30
Test name
Test status
Simulation time 102665377 ps
CPU time 0.84 seconds
Started Apr 30 01:09:20 PM PDT 24
Finished Apr 30 01:09:21 PM PDT 24
Peak memory 200656 kb
Host smart-349141a3-4445-4aa9-81ba-d8dcea43f8d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157624266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2157624266
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.176853232
Short name T209
Test name
Test status
Simulation time 1225465662 ps
CPU time 5.37 seconds
Started Apr 30 01:09:19 PM PDT 24
Finished Apr 30 01:09:25 PM PDT 24
Peak memory 217752 kb
Host smart-d9b8c529-f53e-4197-8552-0bfa2a8efbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176853232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.176853232
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3635191808
Short name T492
Test name
Test status
Simulation time 245071853 ps
CPU time 1.11 seconds
Started Apr 30 01:09:25 PM PDT 24
Finished Apr 30 01:09:26 PM PDT 24
Peak memory 218136 kb
Host smart-4bd7b473-cb30-4958-b699-e09ad264dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635191808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3635191808
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.381705065
Short name T499
Test name
Test status
Simulation time 155955648 ps
CPU time 0.88 seconds
Started Apr 30 01:09:18 PM PDT 24
Finished Apr 30 01:09:19 PM PDT 24
Peak memory 200588 kb
Host smart-f828d90f-9e6c-4a7d-8def-c86aad7d2343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381705065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.381705065
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.669555142
Short name T149
Test name
Test status
Simulation time 794363156 ps
CPU time 4.08 seconds
Started Apr 30 01:09:18 PM PDT 24
Finished Apr 30 01:09:23 PM PDT 24
Peak memory 200972 kb
Host smart-12921d1c-1eab-4ba3-9a58-9768aa0baa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669555142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.669555142
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3353540411
Short name T262
Test name
Test status
Simulation time 146939496 ps
CPU time 1.16 seconds
Started Apr 30 01:09:13 PM PDT 24
Finished Apr 30 01:09:14 PM PDT 24
Peak memory 200828 kb
Host smart-47aa562b-a03b-4aa7-a7dc-466a5ea02141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353540411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3353540411
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1601232794
Short name T243
Test name
Test status
Simulation time 198783040 ps
CPU time 1.38 seconds
Started Apr 30 01:09:12 PM PDT 24
Finished Apr 30 01:09:14 PM PDT 24
Peak memory 201088 kb
Host smart-7f0eb0f9-43fc-47d2-9274-6051966b4128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601232794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1601232794
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.358316451
Short name T338
Test name
Test status
Simulation time 5825291270 ps
CPU time 24.36 seconds
Started Apr 30 01:09:18 PM PDT 24
Finished Apr 30 01:09:43 PM PDT 24
Peak memory 217532 kb
Host smart-1d08c315-b681-4357-818c-b03ca460eb90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358316451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.358316451
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3117027746
Short name T161
Test name
Test status
Simulation time 340780822 ps
CPU time 2.29 seconds
Started Apr 30 01:09:12 PM PDT 24
Finished Apr 30 01:09:15 PM PDT 24
Peak memory 209032 kb
Host smart-2fd09b87-d4b4-4fd6-904b-a63a7501cad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117027746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3117027746
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2736942455
Short name T311
Test name
Test status
Simulation time 140577799 ps
CPU time 1.18 seconds
Started Apr 30 01:09:17 PM PDT 24
Finished Apr 30 01:09:18 PM PDT 24
Peak memory 200780 kb
Host smart-3ae4666c-eac1-4a8e-80fe-bbd35c861e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736942455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2736942455
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2489992646
Short name T299
Test name
Test status
Simulation time 66281814 ps
CPU time 0.76 seconds
Started Apr 30 01:09:23 PM PDT 24
Finished Apr 30 01:09:24 PM PDT 24
Peak memory 200668 kb
Host smart-8ab75363-c8af-4003-b3b6-670ab3a88d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489992646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2489992646
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2348578532
Short name T507
Test name
Test status
Simulation time 1899371267 ps
CPU time 6.75 seconds
Started Apr 30 01:09:27 PM PDT 24
Finished Apr 30 01:09:34 PM PDT 24
Peak memory 222156 kb
Host smart-062a8cda-97be-4a8f-89d6-136a94687144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348578532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2348578532
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3877657079
Short name T524
Test name
Test status
Simulation time 244149476 ps
CPU time 1.06 seconds
Started Apr 30 01:09:24 PM PDT 24
Finished Apr 30 01:09:25 PM PDT 24
Peak memory 218072 kb
Host smart-c4d2cc53-9d3f-4f4b-b742-2546dae01d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877657079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3877657079
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2018434902
Short name T329
Test name
Test status
Simulation time 181286891 ps
CPU time 0.9 seconds
Started Apr 30 01:09:21 PM PDT 24
Finished Apr 30 01:09:22 PM PDT 24
Peak memory 200676 kb
Host smart-4fd9e0c1-7ed1-4819-b517-b1dac6c63943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018434902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2018434902
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2249143223
Short name T32
Test name
Test status
Simulation time 1344006426 ps
CPU time 6.09 seconds
Started Apr 30 01:09:17 PM PDT 24
Finished Apr 30 01:09:24 PM PDT 24
Peak memory 201008 kb
Host smart-a5fe17dd-0e81-48d5-971a-27877361ffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249143223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2249143223
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3790487427
Short name T253
Test name
Test status
Simulation time 100495980 ps
CPU time 0.93 seconds
Started Apr 30 01:09:26 PM PDT 24
Finished Apr 30 01:09:27 PM PDT 24
Peak memory 200796 kb
Host smart-dd54aad1-1fd3-4a5c-94af-634f2c5a146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790487427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3790487427
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3982302041
Short name T303
Test name
Test status
Simulation time 117075862 ps
CPU time 1.2 seconds
Started Apr 30 01:09:19 PM PDT 24
Finished Apr 30 01:09:21 PM PDT 24
Peak memory 201100 kb
Host smart-5ce47690-b979-4d27-bbcf-841e6ea27bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982302041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3982302041
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3589149172
Short name T189
Test name
Test status
Simulation time 8934185155 ps
CPU time 32.47 seconds
Started Apr 30 01:09:26 PM PDT 24
Finished Apr 30 01:09:59 PM PDT 24
Peak memory 210044 kb
Host smart-ee759ffe-feb8-4a25-bc04-17112e7e0971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589149172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3589149172
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2602122118
Short name T90
Test name
Test status
Simulation time 286651535 ps
CPU time 1.95 seconds
Started Apr 30 01:09:19 PM PDT 24
Finished Apr 30 01:09:21 PM PDT 24
Peak memory 200828 kb
Host smart-af563bcc-e8d2-43ed-8b81-386922637e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602122118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2602122118
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3325961787
Short name T454
Test name
Test status
Simulation time 85074990 ps
CPU time 0.82 seconds
Started Apr 30 01:09:21 PM PDT 24
Finished Apr 30 01:09:23 PM PDT 24
Peak memory 200868 kb
Host smart-d29e2d61-6e59-4c0a-8bd8-fb0201a21ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325961787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3325961787
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1980761580
Short name T441
Test name
Test status
Simulation time 72748937 ps
CPU time 0.75 seconds
Started Apr 30 01:06:13 PM PDT 24
Finished Apr 30 01:06:14 PM PDT 24
Peak memory 200624 kb
Host smart-6bd8e4be-27fa-4b05-838b-3d60454c3f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980761580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1980761580
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.4021846835
Short name T60
Test name
Test status
Simulation time 2184047305 ps
CPU time 8.1 seconds
Started Apr 30 01:06:15 PM PDT 24
Finished Apr 30 01:06:24 PM PDT 24
Peak memory 230936 kb
Host smart-3d712cbf-085c-4e51-96a9-1f3ff8ae117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021846835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.4021846835
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3602544006
Short name T398
Test name
Test status
Simulation time 244874455 ps
CPU time 1.03 seconds
Started Apr 30 01:06:14 PM PDT 24
Finished Apr 30 01:06:15 PM PDT 24
Peak memory 218052 kb
Host smart-0c2d7789-5ba7-42de-ba8e-1c8f05e2495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602544006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3602544006
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1774269037
Short name T260
Test name
Test status
Simulation time 82732858 ps
CPU time 0.74 seconds
Started Apr 30 01:06:07 PM PDT 24
Finished Apr 30 01:06:08 PM PDT 24
Peak memory 200672 kb
Host smart-298c2b3e-084b-4951-ab5e-c648dc5dcfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774269037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1774269037
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2351305768
Short name T52
Test name
Test status
Simulation time 1497006854 ps
CPU time 6.3 seconds
Started Apr 30 01:06:09 PM PDT 24
Finished Apr 30 01:06:16 PM PDT 24
Peak memory 201076 kb
Host smart-056261b9-4022-4ba8-ab52-9d74506cdcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351305768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2351305768
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1858722201
Short name T79
Test name
Test status
Simulation time 8444804236 ps
CPU time 12.5 seconds
Started Apr 30 01:06:18 PM PDT 24
Finished Apr 30 01:06:31 PM PDT 24
Peak memory 217724 kb
Host smart-6566e1d4-d678-47f1-92a2-ab7062e5f361
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858722201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1858722201
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1493607477
Short name T417
Test name
Test status
Simulation time 147705485 ps
CPU time 1.05 seconds
Started Apr 30 01:06:08 PM PDT 24
Finished Apr 30 01:06:10 PM PDT 24
Peak memory 200756 kb
Host smart-5a9ec804-dd5d-4a76-a409-d163c73400d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493607477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1493607477
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2049751923
Short name T483
Test name
Test status
Simulation time 196990110 ps
CPU time 1.6 seconds
Started Apr 30 01:06:01 PM PDT 24
Finished Apr 30 01:06:03 PM PDT 24
Peak memory 201084 kb
Host smart-f9f4c794-58a2-48b3-91c5-8f3aa456b9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049751923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2049751923
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2542521822
Short name T241
Test name
Test status
Simulation time 3781813123 ps
CPU time 12.64 seconds
Started Apr 30 01:06:16 PM PDT 24
Finished Apr 30 01:06:29 PM PDT 24
Peak memory 201144 kb
Host smart-1d5ccd58-c6f8-43dc-85be-c919c58fea83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542521822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2542521822
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.4133939137
Short name T319
Test name
Test status
Simulation time 426531180 ps
CPU time 2.38 seconds
Started Apr 30 01:06:09 PM PDT 24
Finished Apr 30 01:06:11 PM PDT 24
Peak memory 209092 kb
Host smart-b9dd1795-3666-4ab2-b64c-a81c24816100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133939137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4133939137
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2298755300
Short name T515
Test name
Test status
Simulation time 94355112 ps
CPU time 0.83 seconds
Started Apr 30 01:06:09 PM PDT 24
Finished Apr 30 01:06:10 PM PDT 24
Peak memory 200824 kb
Host smart-15b54284-e8ce-4553-b50c-1128a80b3f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298755300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2298755300
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3577580682
Short name T404
Test name
Test status
Simulation time 74155463 ps
CPU time 0.74 seconds
Started Apr 30 01:09:32 PM PDT 24
Finished Apr 30 01:09:33 PM PDT 24
Peak memory 200612 kb
Host smart-d78dc6db-fd68-4cb5-81b6-bbd03e2e02cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577580682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3577580682
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.102122398
Short name T276
Test name
Test status
Simulation time 1904925901 ps
CPU time 7.79 seconds
Started Apr 30 01:09:31 PM PDT 24
Finished Apr 30 01:09:39 PM PDT 24
Peak memory 218060 kb
Host smart-28294d3f-2c67-4b41-805b-86a617ea6f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102122398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.102122398
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2805199715
Short name T413
Test name
Test status
Simulation time 243493432 ps
CPU time 1.05 seconds
Started Apr 30 01:09:32 PM PDT 24
Finished Apr 30 01:09:33 PM PDT 24
Peak memory 217952 kb
Host smart-817fc056-3dbd-4774-8c0e-bf95bb051552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805199715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2805199715
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2898989198
Short name T486
Test name
Test status
Simulation time 191539574 ps
CPU time 0.87 seconds
Started Apr 30 01:09:27 PM PDT 24
Finished Apr 30 01:09:28 PM PDT 24
Peak memory 200584 kb
Host smart-67455a43-e9d2-4da4-8f4f-3dc472fcbbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898989198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2898989198
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3466218923
Short name T27
Test name
Test status
Simulation time 947075541 ps
CPU time 4.71 seconds
Started Apr 30 01:09:24 PM PDT 24
Finished Apr 30 01:09:29 PM PDT 24
Peak memory 201004 kb
Host smart-3f2b30a9-07e5-42a3-9328-b0b1b691197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466218923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3466218923
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1988570019
Short name T85
Test name
Test status
Simulation time 161413039 ps
CPU time 1.1 seconds
Started Apr 30 01:09:31 PM PDT 24
Finished Apr 30 01:09:32 PM PDT 24
Peak memory 200904 kb
Host smart-03913b7a-3c62-40d5-969b-c41e8d73f4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988570019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1988570019
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4262590883
Short name T179
Test name
Test status
Simulation time 198497434 ps
CPU time 1.39 seconds
Started Apr 30 01:09:27 PM PDT 24
Finished Apr 30 01:09:29 PM PDT 24
Peak memory 201068 kb
Host smart-97ce1118-5291-4b6f-bd99-89c32bb9d768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262590883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4262590883
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1687829470
Short name T92
Test name
Test status
Simulation time 274190616 ps
CPU time 1.63 seconds
Started Apr 30 01:09:28 PM PDT 24
Finished Apr 30 01:09:30 PM PDT 24
Peak memory 200992 kb
Host smart-d6cffd10-3ee9-4ac2-87c2-73f0fdd470c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687829470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1687829470
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1139619913
Short name T304
Test name
Test status
Simulation time 123496538 ps
CPU time 1.61 seconds
Started Apr 30 01:09:30 PM PDT 24
Finished Apr 30 01:09:33 PM PDT 24
Peak memory 200860 kb
Host smart-b407e91c-1790-4107-a943-958ffa1d1a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139619913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1139619913
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3926733160
Short name T252
Test name
Test status
Simulation time 81746352 ps
CPU time 0.88 seconds
Started Apr 30 01:09:28 PM PDT 24
Finished Apr 30 01:09:30 PM PDT 24
Peak memory 200884 kb
Host smart-493389b5-fb29-4009-b9ce-6eba255ebf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926733160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3926733160
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3286281253
Short name T442
Test name
Test status
Simulation time 60146383 ps
CPU time 0.75 seconds
Started Apr 30 01:09:37 PM PDT 24
Finished Apr 30 01:09:38 PM PDT 24
Peak memory 200924 kb
Host smart-eb9bb50d-f87f-4908-9b7f-c34bc8dedcd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286281253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3286281253
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.147454745
Short name T436
Test name
Test status
Simulation time 2369923109 ps
CPU time 7.6 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:44 PM PDT 24
Peak memory 222744 kb
Host smart-bc13f168-a5cb-4cd4-8ffa-f1dc18757109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147454745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.147454745
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2197446955
Short name T473
Test name
Test status
Simulation time 244565148 ps
CPU time 1.13 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:38 PM PDT 24
Peak memory 218252 kb
Host smart-aae23099-2106-4962-a1f1-1645c99af6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197446955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2197446955
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1414177251
Short name T388
Test name
Test status
Simulation time 120032188 ps
CPU time 0.79 seconds
Started Apr 30 01:09:29 PM PDT 24
Finished Apr 30 01:09:30 PM PDT 24
Peak memory 200672 kb
Host smart-69c70aeb-5e4e-41b2-834f-96ec7f0d7df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414177251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1414177251
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2937032093
Short name T470
Test name
Test status
Simulation time 1052463435 ps
CPU time 4.99 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:42 PM PDT 24
Peak memory 201056 kb
Host smart-569f8bcb-8131-46a8-b478-74eaef0bd7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937032093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2937032093
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1694746611
Short name T414
Test name
Test status
Simulation time 154657345 ps
CPU time 1.22 seconds
Started Apr 30 01:09:37 PM PDT 24
Finished Apr 30 01:09:39 PM PDT 24
Peak memory 200800 kb
Host smart-b42d6f91-a638-4707-ab7c-e2831f53bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694746611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1694746611
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.639950569
Short name T157
Test name
Test status
Simulation time 112738732 ps
CPU time 1.19 seconds
Started Apr 30 01:09:31 PM PDT 24
Finished Apr 30 01:09:32 PM PDT 24
Peak memory 200952 kb
Host smart-a137fbb9-b517-442c-9f55-17b05f592322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639950569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.639950569
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.961959640
Short name T358
Test name
Test status
Simulation time 2572047293 ps
CPU time 11.68 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:48 PM PDT 24
Peak memory 201144 kb
Host smart-fe9ff45a-5794-4199-ba92-58c264f7a2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961959640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.961959640
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2480889513
Short name T356
Test name
Test status
Simulation time 321834558 ps
CPU time 2.18 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:39 PM PDT 24
Peak memory 200852 kb
Host smart-17235ec0-e275-40ec-be7e-02e2c512c547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480889513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2480889513
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2536863576
Short name T385
Test name
Test status
Simulation time 85022028 ps
CPU time 0.88 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:38 PM PDT 24
Peak memory 200748 kb
Host smart-dda5923d-6dcd-4f8e-8dd9-822172550f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536863576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2536863576
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.34162361
Short name T316
Test name
Test status
Simulation time 80321757 ps
CPU time 0.79 seconds
Started Apr 30 01:09:44 PM PDT 24
Finished Apr 30 01:09:46 PM PDT 24
Peak memory 200692 kb
Host smart-1531d132-a38a-4bc3-a092-1be3b732b697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34162361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.34162361
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3741444623
Short name T387
Test name
Test status
Simulation time 1229838592 ps
CPU time 5.5 seconds
Started Apr 30 01:09:38 PM PDT 24
Finished Apr 30 01:09:43 PM PDT 24
Peak memory 217556 kb
Host smart-618454e5-da82-490d-bbf9-4d06ba2eeb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741444623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3741444623
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1353906276
Short name T342
Test name
Test status
Simulation time 244486825 ps
CPU time 0.99 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:37 PM PDT 24
Peak memory 218032 kb
Host smart-453b05fb-1a17-4e4d-9430-e2d38dc9aee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353906276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1353906276
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1032082086
Short name T221
Test name
Test status
Simulation time 203981562 ps
CPU time 0.9 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:37 PM PDT 24
Peak memory 200648 kb
Host smart-e0287651-dafb-4a07-b81b-f896c1b07264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032082086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1032082086
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.194762648
Short name T313
Test name
Test status
Simulation time 957999439 ps
CPU time 4.85 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:41 PM PDT 24
Peak memory 201024 kb
Host smart-3817476e-cdca-46d2-bad5-16926ae50099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194762648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.194762648
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1636293018
Short name T503
Test name
Test status
Simulation time 113491736 ps
CPU time 1.03 seconds
Started Apr 30 01:09:36 PM PDT 24
Finished Apr 30 01:09:37 PM PDT 24
Peak memory 200804 kb
Host smart-94f8f3d5-394d-4097-ad93-ab1547a7153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636293018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1636293018
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1821884295
Short name T464
Test name
Test status
Simulation time 122413381 ps
CPU time 1.23 seconds
Started Apr 30 01:09:37 PM PDT 24
Finished Apr 30 01:09:39 PM PDT 24
Peak memory 201032 kb
Host smart-8a5dafa3-88a9-4323-978a-1bf03ef18669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821884295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1821884295
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.774316394
Short name T531
Test name
Test status
Simulation time 11537124800 ps
CPU time 39.16 seconds
Started Apr 30 01:09:44 PM PDT 24
Finished Apr 30 01:10:24 PM PDT 24
Peak memory 209404 kb
Host smart-2f8908b6-7fdf-4e20-b5b1-14fccde28e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774316394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.774316394
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.85493548
Short name T214
Test name
Test status
Simulation time 346442768 ps
CPU time 2.24 seconds
Started Apr 30 01:09:37 PM PDT 24
Finished Apr 30 01:09:39 PM PDT 24
Peak memory 200860 kb
Host smart-c6a70a4c-eceb-4702-a90c-2c5d59bf5372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85493548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.85493548
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.505420452
Short name T9
Test name
Test status
Simulation time 68783404 ps
CPU time 0.71 seconds
Started Apr 30 01:09:35 PM PDT 24
Finished Apr 30 01:09:36 PM PDT 24
Peak memory 200856 kb
Host smart-95327a72-4e1a-4152-b413-d5559cc15af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505420452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.505420452
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3634954405
Short name T396
Test name
Test status
Simulation time 82773689 ps
CPU time 0.85 seconds
Started Apr 30 01:09:44 PM PDT 24
Finished Apr 30 01:09:46 PM PDT 24
Peak memory 200648 kb
Host smart-e37bdaff-81c9-4460-bdce-447e3afa73b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634954405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3634954405
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1055091899
Short name T280
Test name
Test status
Simulation time 2368553949 ps
CPU time 8.96 seconds
Started Apr 30 01:09:42 PM PDT 24
Finished Apr 30 01:09:51 PM PDT 24
Peak memory 218688 kb
Host smart-4d60fed9-1071-49b2-a5c4-87b3877732b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055091899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1055091899
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1877887029
Short name T300
Test name
Test status
Simulation time 244107467 ps
CPU time 1.1 seconds
Started Apr 30 01:09:45 PM PDT 24
Finished Apr 30 01:09:46 PM PDT 24
Peak memory 218056 kb
Host smart-2d757a5f-7e71-4d92-bde9-5c1922e695d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877887029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1877887029
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1689001035
Short name T23
Test name
Test status
Simulation time 218331363 ps
CPU time 0.92 seconds
Started Apr 30 01:09:44 PM PDT 24
Finished Apr 30 01:09:46 PM PDT 24
Peak memory 200660 kb
Host smart-08a32587-0e77-48a0-a7f0-0a01420ce204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689001035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1689001035
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3679534457
Short name T340
Test name
Test status
Simulation time 2019554740 ps
CPU time 7.16 seconds
Started Apr 30 01:09:42 PM PDT 24
Finished Apr 30 01:09:50 PM PDT 24
Peak memory 200960 kb
Host smart-eb6fe8ea-b1e2-42e9-9aed-12c19ae75f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679534457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3679534457
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3277013444
Short name T279
Test name
Test status
Simulation time 189493825 ps
CPU time 1.21 seconds
Started Apr 30 01:09:44 PM PDT 24
Finished Apr 30 01:09:46 PM PDT 24
Peak memory 200864 kb
Host smart-022ff76e-cff7-4846-8a98-be07ec501962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277013444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3277013444
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3636196370
Short name T301
Test name
Test status
Simulation time 196623222 ps
CPU time 1.36 seconds
Started Apr 30 01:09:43 PM PDT 24
Finished Apr 30 01:09:44 PM PDT 24
Peak memory 201088 kb
Host smart-a4fb85f4-5254-422e-9777-3cb3fc58c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636196370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3636196370
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.606684729
Short name T467
Test name
Test status
Simulation time 1539129660 ps
CPU time 6 seconds
Started Apr 30 01:09:42 PM PDT 24
Finished Apr 30 01:09:48 PM PDT 24
Peak memory 201080 kb
Host smart-fcafefc7-7427-405e-af3d-b5a08f97bcde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606684729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.606684729
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2784597829
Short name T94
Test name
Test status
Simulation time 359861828 ps
CPU time 2.16 seconds
Started Apr 30 01:09:43 PM PDT 24
Finished Apr 30 01:09:45 PM PDT 24
Peak memory 200912 kb
Host smart-0c69e483-4f38-49c6-804a-60a02a59e333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784597829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2784597829
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.448867463
Short name T53
Test name
Test status
Simulation time 116452266 ps
CPU time 0.89 seconds
Started Apr 30 01:09:45 PM PDT 24
Finished Apr 30 01:09:47 PM PDT 24
Peak memory 200888 kb
Host smart-8ccfcac2-e8c4-4f6c-9836-326c1ce9f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448867463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.448867463
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3074928698
Short name T207
Test name
Test status
Simulation time 71613050 ps
CPU time 0.76 seconds
Started Apr 30 01:09:48 PM PDT 24
Finished Apr 30 01:09:49 PM PDT 24
Peak memory 200688 kb
Host smart-680131f1-bba7-4f1b-82ca-04a8c74cc72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074928698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3074928698
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3625589323
Short name T50
Test name
Test status
Simulation time 1899877721 ps
CPU time 7.8 seconds
Started Apr 30 01:09:48 PM PDT 24
Finished Apr 30 01:09:56 PM PDT 24
Peak memory 222136 kb
Host smart-32bd7b82-32c1-4525-b9e8-7d9390f295d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625589323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3625589323
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4147179449
Short name T156
Test name
Test status
Simulation time 245032773 ps
CPU time 1.03 seconds
Started Apr 30 01:09:50 PM PDT 24
Finished Apr 30 01:09:52 PM PDT 24
Peak memory 218068 kb
Host smart-be762ae6-d9df-439d-8025-978f88b9872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147179449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4147179449
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2609454054
Short name T219
Test name
Test status
Simulation time 153957540 ps
CPU time 0.81 seconds
Started Apr 30 01:09:43 PM PDT 24
Finished Apr 30 01:09:44 PM PDT 24
Peak memory 200696 kb
Host smart-0d8b18c5-b483-4342-8a3a-269d0fcfe25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609454054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2609454054
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.846368382
Short name T134
Test name
Test status
Simulation time 1910872248 ps
CPU time 7.35 seconds
Started Apr 30 01:09:45 PM PDT 24
Finished Apr 30 01:09:53 PM PDT 24
Peak memory 201032 kb
Host smart-2dad042b-0c8f-4a48-9cea-c941d6c4d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846368382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.846368382
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1488746995
Short name T534
Test name
Test status
Simulation time 99029408 ps
CPU time 1.06 seconds
Started Apr 30 01:09:49 PM PDT 24
Finished Apr 30 01:09:51 PM PDT 24
Peak memory 200804 kb
Host smart-1c5ba514-70e8-4609-b25b-b64351bd801a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488746995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1488746995
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3317768722
Short name T151
Test name
Test status
Simulation time 200537019 ps
CPU time 1.44 seconds
Started Apr 30 01:09:43 PM PDT 24
Finished Apr 30 01:09:45 PM PDT 24
Peak memory 201068 kb
Host smart-52bfc28d-9415-4ef5-b2f1-e8cfa0c2eb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317768722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3317768722
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1280482677
Short name T469
Test name
Test status
Simulation time 6987376345 ps
CPU time 31.37 seconds
Started Apr 30 01:09:51 PM PDT 24
Finished Apr 30 01:10:23 PM PDT 24
Peak memory 201144 kb
Host smart-ce64802f-87bc-4399-8dc4-7e48cd9b5efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280482677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1280482677
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.618509912
Short name T65
Test name
Test status
Simulation time 484123211 ps
CPU time 2.62 seconds
Started Apr 30 01:09:42 PM PDT 24
Finished Apr 30 01:09:46 PM PDT 24
Peak memory 200760 kb
Host smart-94ec1626-321a-4f07-803b-1682877a83c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618509912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.618509912
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.749443179
Short name T238
Test name
Test status
Simulation time 135330247 ps
CPU time 1.13 seconds
Started Apr 30 01:09:43 PM PDT 24
Finished Apr 30 01:09:45 PM PDT 24
Peak memory 200752 kb
Host smart-475940ec-897b-462d-97e8-e7afecefc60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749443179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.749443179
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2880954131
Short name T218
Test name
Test status
Simulation time 54153418 ps
CPU time 0.69 seconds
Started Apr 30 01:09:49 PM PDT 24
Finished Apr 30 01:09:51 PM PDT 24
Peak memory 200620 kb
Host smart-4257d56a-430c-4c16-ae57-aed8dbae8cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880954131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2880954131
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.4260760539
Short name T43
Test name
Test status
Simulation time 1895249907 ps
CPU time 6.71 seconds
Started Apr 30 01:09:49 PM PDT 24
Finished Apr 30 01:09:57 PM PDT 24
Peak memory 218564 kb
Host smart-16abb94e-8623-438d-8321-29dc85f86380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260760539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.4260760539
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3016568230
Short name T418
Test name
Test status
Simulation time 244329599 ps
CPU time 1.02 seconds
Started Apr 30 01:09:51 PM PDT 24
Finished Apr 30 01:09:52 PM PDT 24
Peak memory 218036 kb
Host smart-b81afc4a-f621-431b-804d-d2ca0cc91227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016568230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3016568230
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3333150482
Short name T286
Test name
Test status
Simulation time 126574624 ps
CPU time 0.78 seconds
Started Apr 30 01:09:52 PM PDT 24
Finished Apr 30 01:09:53 PM PDT 24
Peak memory 200660 kb
Host smart-493eb7f6-0815-45a5-8a8a-483ba0152283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333150482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3333150482
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1196811911
Short name T181
Test name
Test status
Simulation time 699293189 ps
CPU time 4.15 seconds
Started Apr 30 01:09:50 PM PDT 24
Finished Apr 30 01:09:55 PM PDT 24
Peak memory 201060 kb
Host smart-024cb37a-0e18-4acc-9587-69ae71250883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196811911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1196811911
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3951812236
Short name T193
Test name
Test status
Simulation time 96566259 ps
CPU time 0.97 seconds
Started Apr 30 01:09:51 PM PDT 24
Finished Apr 30 01:09:53 PM PDT 24
Peak memory 200840 kb
Host smart-f79bf855-2f65-4eda-b709-09eff76900ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951812236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3951812236
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.23244739
Short name T357
Test name
Test status
Simulation time 253783605 ps
CPU time 1.54 seconds
Started Apr 30 01:09:52 PM PDT 24
Finished Apr 30 01:09:54 PM PDT 24
Peak memory 201044 kb
Host smart-da330cc1-4dcf-455a-8eb6-74881f1f2b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23244739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.23244739
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3728493847
Short name T435
Test name
Test status
Simulation time 6193838865 ps
CPU time 25.21 seconds
Started Apr 30 01:09:51 PM PDT 24
Finished Apr 30 01:10:17 PM PDT 24
Peak memory 210400 kb
Host smart-9b03983f-8dda-4379-900a-cf8edd47c995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728493847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3728493847
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.203334085
Short name T408
Test name
Test status
Simulation time 144329700 ps
CPU time 1.68 seconds
Started Apr 30 01:09:49 PM PDT 24
Finished Apr 30 01:09:52 PM PDT 24
Peak memory 209116 kb
Host smart-e701c2a0-0924-43a0-973e-22b95299ec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203334085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.203334085
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1559015960
Short name T333
Test name
Test status
Simulation time 173441460 ps
CPU time 1.19 seconds
Started Apr 30 01:09:50 PM PDT 24
Finished Apr 30 01:09:52 PM PDT 24
Peak memory 200824 kb
Host smart-2379f9db-ede4-4cb2-bd40-f1ac707ef1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559015960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1559015960
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.540440988
Short name T291
Test name
Test status
Simulation time 89328336 ps
CPU time 0.81 seconds
Started Apr 30 01:09:54 PM PDT 24
Finished Apr 30 01:09:56 PM PDT 24
Peak memory 200692 kb
Host smart-3575af94-4581-4a1f-83f7-2d457632783a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540440988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.540440988
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2892911573
Short name T367
Test name
Test status
Simulation time 2355716036 ps
CPU time 7.9 seconds
Started Apr 30 01:09:54 PM PDT 24
Finished Apr 30 01:10:03 PM PDT 24
Peak memory 222680 kb
Host smart-4aae81f3-bd3b-43b8-afc0-51616756dfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892911573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2892911573
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3835492126
Short name T16
Test name
Test status
Simulation time 245624592 ps
CPU time 1.09 seconds
Started Apr 30 01:09:54 PM PDT 24
Finished Apr 30 01:09:56 PM PDT 24
Peak memory 218036 kb
Host smart-ee4f1386-1668-45ed-be5a-65881986d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835492126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3835492126
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1443187670
Short name T25
Test name
Test status
Simulation time 196440184 ps
CPU time 0.9 seconds
Started Apr 30 01:09:56 PM PDT 24
Finished Apr 30 01:09:57 PM PDT 24
Peak memory 200616 kb
Host smart-b5d4f593-7631-4b82-843c-80cd9bac1db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443187670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1443187670
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1028315513
Short name T108
Test name
Test status
Simulation time 1698458974 ps
CPU time 6.53 seconds
Started Apr 30 01:09:57 PM PDT 24
Finished Apr 30 01:10:04 PM PDT 24
Peak memory 201100 kb
Host smart-965189c9-4071-498c-af12-05b3e5bb7947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028315513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1028315513
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4076388213
Short name T51
Test name
Test status
Simulation time 95531464 ps
CPU time 0.96 seconds
Started Apr 30 01:09:56 PM PDT 24
Finished Apr 30 01:09:58 PM PDT 24
Peak memory 200900 kb
Host smart-ae228132-4367-4bed-ba21-1c83708f294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076388213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4076388213
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2531476833
Short name T240
Test name
Test status
Simulation time 123081301 ps
CPU time 1.17 seconds
Started Apr 30 01:09:49 PM PDT 24
Finished Apr 30 01:09:50 PM PDT 24
Peak memory 201064 kb
Host smart-573d0dba-76b9-4423-88b1-10b8aca2d54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531476833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2531476833
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2254134755
Short name T184
Test name
Test status
Simulation time 5602776328 ps
CPU time 20.45 seconds
Started Apr 30 01:09:55 PM PDT 24
Finished Apr 30 01:10:15 PM PDT 24
Peak memory 201108 kb
Host smart-73252865-39dd-49fe-a0db-290ffca36c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254134755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2254134755
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1629137649
Short name T290
Test name
Test status
Simulation time 437959196 ps
CPU time 2.44 seconds
Started Apr 30 01:09:57 PM PDT 24
Finished Apr 30 01:10:00 PM PDT 24
Peak memory 200924 kb
Host smart-bad33a82-2536-4043-b50f-77707dd59515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629137649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1629137649
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2049476199
Short name T160
Test name
Test status
Simulation time 87037943 ps
CPU time 0.86 seconds
Started Apr 30 01:09:54 PM PDT 24
Finished Apr 30 01:09:56 PM PDT 24
Peak memory 200912 kb
Host smart-02059288-7d90-4331-8d0b-eda1e3262040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049476199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2049476199
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2375131159
Short name T330
Test name
Test status
Simulation time 70483310 ps
CPU time 0.83 seconds
Started Apr 30 01:10:02 PM PDT 24
Finished Apr 30 01:10:03 PM PDT 24
Peak memory 200740 kb
Host smart-04911825-bde8-4395-aedf-426e27edcf83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375131159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2375131159
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1369561615
Short name T56
Test name
Test status
Simulation time 1229504614 ps
CPU time 5.36 seconds
Started Apr 30 01:10:02 PM PDT 24
Finished Apr 30 01:10:08 PM PDT 24
Peak memory 217552 kb
Host smart-2c46f0d1-03b3-4592-85f6-4d9fad825351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369561615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1369561615
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1961592658
Short name T526
Test name
Test status
Simulation time 243413008 ps
CPU time 1.16 seconds
Started Apr 30 01:10:04 PM PDT 24
Finished Apr 30 01:10:05 PM PDT 24
Peak memory 218296 kb
Host smart-974b824a-0fcb-45fd-aec0-b973edc9a3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961592658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1961592658
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.130805507
Short name T482
Test name
Test status
Simulation time 99368643 ps
CPU time 0.73 seconds
Started Apr 30 01:09:56 PM PDT 24
Finished Apr 30 01:09:57 PM PDT 24
Peak memory 200608 kb
Host smart-7b949fbe-057c-4e5a-a4b1-096337234061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130805507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.130805507
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.61573376
Short name T137
Test name
Test status
Simulation time 1535464065 ps
CPU time 7.87 seconds
Started Apr 30 01:09:54 PM PDT 24
Finished Apr 30 01:10:03 PM PDT 24
Peak memory 201028 kb
Host smart-a05bd26d-000f-4688-8e14-493dad46d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61573376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.61573376
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.575659095
Short name T278
Test name
Test status
Simulation time 106740557 ps
CPU time 0.99 seconds
Started Apr 30 01:10:04 PM PDT 24
Finished Apr 30 01:10:06 PM PDT 24
Peak memory 200860 kb
Host smart-8414dc11-f119-4f9b-b16a-ba71cf21dbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575659095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.575659095
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.831192697
Short name T170
Test name
Test status
Simulation time 119438698 ps
CPU time 1.18 seconds
Started Apr 30 01:09:57 PM PDT 24
Finished Apr 30 01:09:58 PM PDT 24
Peak memory 201084 kb
Host smart-039313b0-df36-4110-aa7b-f8ca9e486f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831192697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.831192697
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.777525856
Short name T370
Test name
Test status
Simulation time 11313963931 ps
CPU time 41.58 seconds
Started Apr 30 01:10:02 PM PDT 24
Finished Apr 30 01:10:44 PM PDT 24
Peak memory 201164 kb
Host smart-6293c8c9-9ab8-44e4-84f6-0ec4ab5c303d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777525856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.777525856
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3350019141
Short name T289
Test name
Test status
Simulation time 535119014 ps
CPU time 2.86 seconds
Started Apr 30 01:10:03 PM PDT 24
Finished Apr 30 01:10:06 PM PDT 24
Peak memory 200864 kb
Host smart-0d609e4e-ec0f-46bf-bb1c-8c11919bf49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350019141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3350019141
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1977246306
Short name T168
Test name
Test status
Simulation time 285565314 ps
CPU time 1.57 seconds
Started Apr 30 01:10:03 PM PDT 24
Finished Apr 30 01:10:05 PM PDT 24
Peak memory 201008 kb
Host smart-746417b4-6b1a-4813-b13e-6a38ea78f7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977246306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1977246306
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.398000383
Short name T47
Test name
Test status
Simulation time 70773218 ps
CPU time 0.75 seconds
Started Apr 30 01:10:09 PM PDT 24
Finished Apr 30 01:10:10 PM PDT 24
Peak memory 200680 kb
Host smart-24efb7d6-23d8-4d3c-9f3b-3a8106256aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398000383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.398000383
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1970939608
Short name T54
Test name
Test status
Simulation time 1225332868 ps
CPU time 5.69 seconds
Started Apr 30 01:10:15 PM PDT 24
Finished Apr 30 01:10:22 PM PDT 24
Peak memory 217532 kb
Host smart-e9f7ff13-9a80-4034-ba58-a7b5c768440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970939608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1970939608
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1670937773
Short name T317
Test name
Test status
Simulation time 244237365 ps
CPU time 1.02 seconds
Started Apr 30 01:10:09 PM PDT 24
Finished Apr 30 01:10:10 PM PDT 24
Peak memory 218188 kb
Host smart-21596ea8-78fc-4414-b8da-b23263e74bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670937773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1670937773
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1348424292
Short name T508
Test name
Test status
Simulation time 190493013 ps
CPU time 0.92 seconds
Started Apr 30 01:10:04 PM PDT 24
Finished Apr 30 01:10:05 PM PDT 24
Peak memory 200708 kb
Host smart-8b66c6ef-a30c-408d-b426-ce7a1e727548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348424292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1348424292
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3064108174
Short name T259
Test name
Test status
Simulation time 1092204690 ps
CPU time 5.51 seconds
Started Apr 30 01:10:01 PM PDT 24
Finished Apr 30 01:10:07 PM PDT 24
Peak memory 201072 kb
Host smart-16b82316-3048-43bf-9b09-f4e96d8794f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064108174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3064108174
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3332568127
Short name T522
Test name
Test status
Simulation time 174860434 ps
CPU time 1.21 seconds
Started Apr 30 01:10:04 PM PDT 24
Finished Apr 30 01:10:05 PM PDT 24
Peak memory 200900 kb
Host smart-3fe906f9-49c8-460f-baf8-920c4951032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332568127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3332568127
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3557757772
Short name T197
Test name
Test status
Simulation time 252946923 ps
CPU time 1.44 seconds
Started Apr 30 01:10:03 PM PDT 24
Finished Apr 30 01:10:05 PM PDT 24
Peak memory 201048 kb
Host smart-bd479a2b-c289-4e54-aacb-d7ecf7c3f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557757772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3557757772
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.4075830706
Short name T83
Test name
Test status
Simulation time 192625010 ps
CPU time 1.18 seconds
Started Apr 30 01:10:09 PM PDT 24
Finished Apr 30 01:10:11 PM PDT 24
Peak memory 200692 kb
Host smart-18afd5cd-159a-4acb-b1c2-2b8e8167aa88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075830706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.4075830706
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.655224993
Short name T158
Test name
Test status
Simulation time 551585269 ps
CPU time 2.88 seconds
Started Apr 30 01:10:03 PM PDT 24
Finished Apr 30 01:10:06 PM PDT 24
Peak memory 200840 kb
Host smart-e681b222-e321-40fa-9140-3d34bd0767f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655224993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.655224993
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1186670683
Short name T206
Test name
Test status
Simulation time 298694800 ps
CPU time 1.66 seconds
Started Apr 30 01:10:02 PM PDT 24
Finished Apr 30 01:10:05 PM PDT 24
Peak memory 201128 kb
Host smart-6409f16e-2078-4114-b231-4b9c49d8dca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186670683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1186670683
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3388029151
Short name T529
Test name
Test status
Simulation time 86993435 ps
CPU time 0.82 seconds
Started Apr 30 01:10:16 PM PDT 24
Finished Apr 30 01:10:17 PM PDT 24
Peak memory 200728 kb
Host smart-bde2a9be-e13a-463c-9231-58ed51f72eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388029151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3388029151
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.420263780
Short name T33
Test name
Test status
Simulation time 245900378 ps
CPU time 1.05 seconds
Started Apr 30 01:10:10 PM PDT 24
Finished Apr 30 01:10:12 PM PDT 24
Peak memory 218224 kb
Host smart-cad63fb9-064f-4931-94f7-306e78c082c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420263780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.420263780
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.4264356636
Short name T273
Test name
Test status
Simulation time 79947388 ps
CPU time 0.72 seconds
Started Apr 30 01:10:11 PM PDT 24
Finished Apr 30 01:10:12 PM PDT 24
Peak memory 200660 kb
Host smart-579fd0e6-6010-418f-8af5-37bd98f0d19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264356636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.4264356636
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1497800209
Short name T106
Test name
Test status
Simulation time 1582541530 ps
CPU time 6.38 seconds
Started Apr 30 01:10:15 PM PDT 24
Finished Apr 30 01:10:22 PM PDT 24
Peak memory 200836 kb
Host smart-e8e6620a-9850-49d6-9ea3-d95b5ce8614b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497800209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1497800209
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2947064918
Short name T312
Test name
Test status
Simulation time 154193670 ps
CPU time 1.16 seconds
Started Apr 30 01:10:09 PM PDT 24
Finished Apr 30 01:10:11 PM PDT 24
Peak memory 200796 kb
Host smart-5f8148ae-1498-4544-8c12-5a081081552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947064918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2947064918
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2020470578
Short name T211
Test name
Test status
Simulation time 205997177 ps
CPU time 1.48 seconds
Started Apr 30 01:10:10 PM PDT 24
Finished Apr 30 01:10:12 PM PDT 24
Peak memory 201088 kb
Host smart-24080473-85af-431c-9291-3e995d44c249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020470578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2020470578
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.569748349
Short name T148
Test name
Test status
Simulation time 3013053107 ps
CPU time 13.39 seconds
Started Apr 30 01:10:15 PM PDT 24
Finished Apr 30 01:10:29 PM PDT 24
Peak memory 200936 kb
Host smart-edc921e7-dc02-45e2-a47a-1c74870e4736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569748349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.569748349
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.792414738
Short name T429
Test name
Test status
Simulation time 340376738 ps
CPU time 2.35 seconds
Started Apr 30 01:10:09 PM PDT 24
Finished Apr 30 01:10:11 PM PDT 24
Peak memory 208960 kb
Host smart-1a685572-efed-4d52-9750-e092427371ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792414738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.792414738
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.994488492
Short name T191
Test name
Test status
Simulation time 166234659 ps
CPU time 1.26 seconds
Started Apr 30 01:10:15 PM PDT 24
Finished Apr 30 01:10:17 PM PDT 24
Peak memory 200848 kb
Host smart-3eb7dedd-542c-4cce-ad17-fd8388de0937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994488492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.994488492
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3209023574
Short name T344
Test name
Test status
Simulation time 64605010 ps
CPU time 0.7 seconds
Started Apr 30 01:06:24 PM PDT 24
Finished Apr 30 01:06:25 PM PDT 24
Peak memory 200592 kb
Host smart-73fff7bc-292c-469c-8b26-ad16c6237cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209023574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3209023574
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3980671683
Short name T283
Test name
Test status
Simulation time 2156875147 ps
CPU time 7.65 seconds
Started Apr 30 01:06:26 PM PDT 24
Finished Apr 30 01:06:34 PM PDT 24
Peak memory 222648 kb
Host smart-d75fed13-516c-40d8-90bb-86d23fbc40d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980671683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3980671683
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3105774241
Short name T332
Test name
Test status
Simulation time 245193186 ps
CPU time 1.06 seconds
Started Apr 30 01:06:26 PM PDT 24
Finished Apr 30 01:06:27 PM PDT 24
Peak memory 218036 kb
Host smart-87303bf1-5dd9-4323-95cc-81ce6b70fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105774241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3105774241
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3747164374
Short name T237
Test name
Test status
Simulation time 75819287 ps
CPU time 0.71 seconds
Started Apr 30 01:06:21 PM PDT 24
Finished Apr 30 01:06:22 PM PDT 24
Peak memory 200680 kb
Host smart-0e144f1e-4502-490d-9eb3-021ffae2c7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747164374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3747164374
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1524065874
Short name T216
Test name
Test status
Simulation time 2130714812 ps
CPU time 8.02 seconds
Started Apr 30 01:06:18 PM PDT 24
Finished Apr 30 01:06:26 PM PDT 24
Peak memory 201052 kb
Host smart-9218ed0c-8a11-4297-a9a8-c9e3166483de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524065874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1524065874
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.573652511
Short name T76
Test name
Test status
Simulation time 8336887622 ps
CPU time 12.97 seconds
Started Apr 30 01:06:26 PM PDT 24
Finished Apr 30 01:06:39 PM PDT 24
Peak memory 217744 kb
Host smart-a63134ff-7b78-47cc-80d1-022767762d12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573652511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.573652511
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1448554112
Short name T145
Test name
Test status
Simulation time 145858575 ps
CPU time 1.09 seconds
Started Apr 30 01:06:25 PM PDT 24
Finished Apr 30 01:06:26 PM PDT 24
Peak memory 200844 kb
Host smart-458404ae-2e5f-4262-9450-3d400ae50afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448554112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1448554112
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2442505127
Short name T142
Test name
Test status
Simulation time 117863763 ps
CPU time 1.18 seconds
Started Apr 30 01:06:20 PM PDT 24
Finished Apr 30 01:06:21 PM PDT 24
Peak memory 201052 kb
Host smart-d158fb1f-8de4-4f43-83ae-bf0418a0926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442505127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2442505127
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.881623616
Short name T261
Test name
Test status
Simulation time 9572437959 ps
CPU time 34.68 seconds
Started Apr 30 01:06:25 PM PDT 24
Finished Apr 30 01:07:00 PM PDT 24
Peak memory 209340 kb
Host smart-a6791431-d0e7-46a5-9173-65cb4ee824f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881623616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.881623616
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1228894709
Short name T324
Test name
Test status
Simulation time 121749369 ps
CPU time 1.5 seconds
Started Apr 30 01:06:20 PM PDT 24
Finished Apr 30 01:06:22 PM PDT 24
Peak memory 200908 kb
Host smart-fde60c74-5bea-4835-b7f3-79333c6f7df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228894709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1228894709
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3136430302
Short name T265
Test name
Test status
Simulation time 167192150 ps
CPU time 1.26 seconds
Started Apr 30 01:06:18 PM PDT 24
Finished Apr 30 01:06:20 PM PDT 24
Peak memory 201060 kb
Host smart-9095ff56-5d11-46d2-8051-d5d1251fa844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136430302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3136430302
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.693253049
Short name T377
Test name
Test status
Simulation time 76116876 ps
CPU time 0.81 seconds
Started Apr 30 01:10:17 PM PDT 24
Finished Apr 30 01:10:19 PM PDT 24
Peak memory 200640 kb
Host smart-5b51d02a-7b75-4bfd-b5d8-22cf2c6a1127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693253049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.693253049
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1611865459
Short name T364
Test name
Test status
Simulation time 1902512065 ps
CPU time 6.73 seconds
Started Apr 30 01:10:14 PM PDT 24
Finished Apr 30 01:10:22 PM PDT 24
Peak memory 218460 kb
Host smart-a04c3218-0a29-4cf1-8503-04418a2c7a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611865459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1611865459
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2254819607
Short name T383
Test name
Test status
Simulation time 244905673 ps
CPU time 1.02 seconds
Started Apr 30 01:10:14 PM PDT 24
Finished Apr 30 01:10:16 PM PDT 24
Peak memory 218124 kb
Host smart-d8afd745-5dbb-47db-8410-56174ea8c8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254819607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2254819607
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.62797621
Short name T376
Test name
Test status
Simulation time 182406030 ps
CPU time 0.88 seconds
Started Apr 30 01:10:16 PM PDT 24
Finished Apr 30 01:10:17 PM PDT 24
Peak memory 200692 kb
Host smart-6d9959d5-9ddb-4e0d-820a-804cb05fa1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62797621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.62797621
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4067262289
Short name T341
Test name
Test status
Simulation time 1361616758 ps
CPU time 5.64 seconds
Started Apr 30 01:10:16 PM PDT 24
Finished Apr 30 01:10:22 PM PDT 24
Peak memory 201032 kb
Host smart-ea551736-e3a7-445a-bf55-45b047e200b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067262289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4067262289
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4008228847
Short name T277
Test name
Test status
Simulation time 103832145 ps
CPU time 0.97 seconds
Started Apr 30 01:10:15 PM PDT 24
Finished Apr 30 01:10:17 PM PDT 24
Peak memory 200916 kb
Host smart-5c2f7e79-5332-4cf3-827e-95e37fc748b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008228847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4008228847
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.954913500
Short name T517
Test name
Test status
Simulation time 198208964 ps
CPU time 1.44 seconds
Started Apr 30 01:10:15 PM PDT 24
Finished Apr 30 01:10:18 PM PDT 24
Peak memory 201024 kb
Host smart-6eca254e-4151-421f-bdea-300ffd07d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954913500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.954913500
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2776115222
Short name T305
Test name
Test status
Simulation time 13018376444 ps
CPU time 46.45 seconds
Started Apr 30 01:10:15 PM PDT 24
Finished Apr 30 01:11:03 PM PDT 24
Peak memory 209392 kb
Host smart-a3e01ac5-a4fe-47c4-927c-6d35d03ff6ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776115222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2776115222
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.632838950
Short name T254
Test name
Test status
Simulation time 154199744 ps
CPU time 1.79 seconds
Started Apr 30 01:10:14 PM PDT 24
Finished Apr 30 01:10:16 PM PDT 24
Peak memory 200796 kb
Host smart-06616bba-ef9a-45d6-807e-9682842bee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632838950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.632838950
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2464837819
Short name T542
Test name
Test status
Simulation time 143955751 ps
CPU time 1.08 seconds
Started Apr 30 01:10:16 PM PDT 24
Finished Apr 30 01:10:18 PM PDT 24
Peak memory 201108 kb
Host smart-41f971aa-1ef5-4cc7-b37d-4a0297022792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464837819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2464837819
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3992762585
Short name T213
Test name
Test status
Simulation time 66315425 ps
CPU time 0.72 seconds
Started Apr 30 01:10:22 PM PDT 24
Finished Apr 30 01:10:23 PM PDT 24
Peak memory 200704 kb
Host smart-0de23e74-b755-49f3-b085-34f5ccba44d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992762585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3992762585
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2080593163
Short name T440
Test name
Test status
Simulation time 1219169749 ps
CPU time 5.75 seconds
Started Apr 30 01:10:21 PM PDT 24
Finished Apr 30 01:10:28 PM PDT 24
Peak memory 222444 kb
Host smart-ade256f1-2bcf-4f22-ad6b-500b56cee4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080593163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2080593163
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.759459467
Short name T143
Test name
Test status
Simulation time 245074919 ps
CPU time 1.1 seconds
Started Apr 30 01:10:20 PM PDT 24
Finished Apr 30 01:10:22 PM PDT 24
Peak memory 218248 kb
Host smart-88cc1edc-2951-4a6d-bc80-cdac9e300007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759459467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.759459467
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3131161116
Short name T229
Test name
Test status
Simulation time 193917309 ps
CPU time 0.85 seconds
Started Apr 30 01:10:17 PM PDT 24
Finished Apr 30 01:10:19 PM PDT 24
Peak memory 200648 kb
Host smart-a09e5bc7-2e0e-42fc-890a-b7079dbcac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131161116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3131161116
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1980250752
Short name T456
Test name
Test status
Simulation time 1961752549 ps
CPU time 7.02 seconds
Started Apr 30 01:10:17 PM PDT 24
Finished Apr 30 01:10:25 PM PDT 24
Peak memory 201060 kb
Host smart-f6d8dcdc-6efe-4e44-ba55-2b6118b3b6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980250752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1980250752
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1785174626
Short name T528
Test name
Test status
Simulation time 182363196 ps
CPU time 1.16 seconds
Started Apr 30 01:10:22 PM PDT 24
Finished Apr 30 01:10:24 PM PDT 24
Peak memory 200856 kb
Host smart-e917e002-d07c-47ab-b96d-8e56aa25c196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785174626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1785174626
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.683893874
Short name T165
Test name
Test status
Simulation time 195654771 ps
CPU time 1.4 seconds
Started Apr 30 01:10:15 PM PDT 24
Finished Apr 30 01:10:17 PM PDT 24
Peak memory 201028 kb
Host smart-6551713d-175c-4d6d-aa6a-1676abf07d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683893874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.683893874
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3083184589
Short name T306
Test name
Test status
Simulation time 3411841613 ps
CPU time 11.62 seconds
Started Apr 30 01:10:23 PM PDT 24
Finished Apr 30 01:10:35 PM PDT 24
Peak memory 201164 kb
Host smart-2ead14bc-26e2-4c55-bbc0-c354974bb569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083184589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3083184589
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.780765088
Short name T96
Test name
Test status
Simulation time 152485720 ps
CPU time 1.91 seconds
Started Apr 30 01:10:21 PM PDT 24
Finished Apr 30 01:10:23 PM PDT 24
Peak memory 200848 kb
Host smart-eca8a974-2532-4193-9b5a-7f510236d0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780765088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.780765088
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2192767938
Short name T390
Test name
Test status
Simulation time 117916486 ps
CPU time 0.98 seconds
Started Apr 30 01:10:14 PM PDT 24
Finished Apr 30 01:10:16 PM PDT 24
Peak memory 200804 kb
Host smart-990f32cf-0222-4775-ba30-3931d0c0a892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192767938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2192767938
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2309263393
Short name T375
Test name
Test status
Simulation time 67522123 ps
CPU time 0.76 seconds
Started Apr 30 01:10:21 PM PDT 24
Finished Apr 30 01:10:23 PM PDT 24
Peak memory 200728 kb
Host smart-0a558aa7-16f4-43ed-867b-104ba9e643cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309263393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2309263393
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.500808793
Short name T386
Test name
Test status
Simulation time 1876633300 ps
CPU time 8.19 seconds
Started Apr 30 01:10:22 PM PDT 24
Finished Apr 30 01:10:31 PM PDT 24
Peak memory 221868 kb
Host smart-e00fa0d4-b27c-4a4d-9251-f7981f3a9c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500808793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.500808793
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.466998709
Short name T463
Test name
Test status
Simulation time 244232855 ps
CPU time 1.06 seconds
Started Apr 30 01:10:21 PM PDT 24
Finished Apr 30 01:10:23 PM PDT 24
Peak memory 218036 kb
Host smart-6bf8bba3-d405-4760-8457-421e2d827389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466998709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.466998709
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.480222822
Short name T393
Test name
Test status
Simulation time 80869083 ps
CPU time 0.76 seconds
Started Apr 30 01:10:22 PM PDT 24
Finished Apr 30 01:10:23 PM PDT 24
Peak memory 200660 kb
Host smart-5da6c194-baca-44fc-862d-cfb90f7e6a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480222822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.480222822
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3243505655
Short name T250
Test name
Test status
Simulation time 925578732 ps
CPU time 4.45 seconds
Started Apr 30 01:10:22 PM PDT 24
Finished Apr 30 01:10:27 PM PDT 24
Peak memory 201060 kb
Host smart-4d7e9571-43ed-4a65-908c-73d93a5c15f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243505655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3243505655
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2047875341
Short name T448
Test name
Test status
Simulation time 147161310 ps
CPU time 1.13 seconds
Started Apr 30 01:10:23 PM PDT 24
Finished Apr 30 01:10:25 PM PDT 24
Peak memory 200880 kb
Host smart-dbadc6a1-36b2-4d0f-aef6-70b6329cbea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047875341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2047875341
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2121554564
Short name T423
Test name
Test status
Simulation time 195702177 ps
CPU time 1.4 seconds
Started Apr 30 01:10:22 PM PDT 24
Finished Apr 30 01:10:24 PM PDT 24
Peak memory 201088 kb
Host smart-c4623e1f-ce6a-4764-b760-fd21739d0164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121554564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2121554564
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2474188165
Short name T500
Test name
Test status
Simulation time 5929951024 ps
CPU time 19.41 seconds
Started Apr 30 01:10:24 PM PDT 24
Finished Apr 30 01:10:43 PM PDT 24
Peak memory 201132 kb
Host smart-cc36fbf1-40a5-4edc-9446-1d83d94244e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474188165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2474188165
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.4058518706
Short name T308
Test name
Test status
Simulation time 141580427 ps
CPU time 1.79 seconds
Started Apr 30 01:10:21 PM PDT 24
Finished Apr 30 01:10:23 PM PDT 24
Peak memory 200900 kb
Host smart-a387c3d0-02c5-436c-ba2c-4247fbc6cf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058518706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.4058518706
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.538636341
Short name T453
Test name
Test status
Simulation time 220496351 ps
CPU time 1.32 seconds
Started Apr 30 01:10:23 PM PDT 24
Finished Apr 30 01:10:24 PM PDT 24
Peak memory 200880 kb
Host smart-59c23015-190e-4ef5-9669-737c14ec7518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538636341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.538636341
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2033825481
Short name T196
Test name
Test status
Simulation time 59538781 ps
CPU time 0.69 seconds
Started Apr 30 01:10:29 PM PDT 24
Finished Apr 30 01:10:30 PM PDT 24
Peak memory 200652 kb
Host smart-f394ee2f-ec64-4d13-80c4-3334d07ab987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033825481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2033825481
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1843915118
Short name T256
Test name
Test status
Simulation time 1899299714 ps
CPU time 6.67 seconds
Started Apr 30 01:10:34 PM PDT 24
Finished Apr 30 01:10:41 PM PDT 24
Peak memory 222568 kb
Host smart-ee995ffa-6961-421f-8921-d330bbc9beb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843915118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1843915118
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3295169992
Short name T1
Test name
Test status
Simulation time 244038960 ps
CPU time 1.08 seconds
Started Apr 30 01:10:29 PM PDT 24
Finished Apr 30 01:10:31 PM PDT 24
Peak memory 218084 kb
Host smart-a5314807-c826-4b17-9a58-ae7caa9ecc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295169992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3295169992
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.4125720407
Short name T217
Test name
Test status
Simulation time 202816412 ps
CPU time 0.96 seconds
Started Apr 30 01:10:34 PM PDT 24
Finished Apr 30 01:10:35 PM PDT 24
Peak memory 200616 kb
Host smart-154b4371-efa8-4212-a8d9-24279c14fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125720407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.4125720407
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1031000638
Short name T493
Test name
Test status
Simulation time 1156366561 ps
CPU time 5.09 seconds
Started Apr 30 01:10:27 PM PDT 24
Finished Apr 30 01:10:32 PM PDT 24
Peak memory 201012 kb
Host smart-ecd6ed6a-190c-4fc9-be08-9c4174389a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031000638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1031000638
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2541114851
Short name T395
Test name
Test status
Simulation time 154036070 ps
CPU time 1.06 seconds
Started Apr 30 01:10:28 PM PDT 24
Finished Apr 30 01:10:29 PM PDT 24
Peak memory 200876 kb
Host smart-f5a1b8e2-51d1-4c71-9cb4-e7c85bed7527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541114851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2541114851
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.519867547
Short name T287
Test name
Test status
Simulation time 253775521 ps
CPU time 1.53 seconds
Started Apr 30 01:10:23 PM PDT 24
Finished Apr 30 01:10:25 PM PDT 24
Peak memory 201088 kb
Host smart-ea9b9f1e-0848-4760-8a6c-c1e0a3dedba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519867547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.519867547
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1975669961
Short name T498
Test name
Test status
Simulation time 7086037239 ps
CPU time 22.54 seconds
Started Apr 30 01:10:28 PM PDT 24
Finished Apr 30 01:10:51 PM PDT 24
Peak memory 201144 kb
Host smart-f9aba877-00f2-470a-97d3-b2699dfd41ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975669961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1975669961
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3267162536
Short name T538
Test name
Test status
Simulation time 143905024 ps
CPU time 1.66 seconds
Started Apr 30 01:10:27 PM PDT 24
Finished Apr 30 01:10:29 PM PDT 24
Peak memory 200828 kb
Host smart-2860e45e-288b-4515-b9bf-4643b9631123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267162536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3267162536
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2491010882
Short name T88
Test name
Test status
Simulation time 217524308 ps
CPU time 1.3 seconds
Started Apr 30 01:10:34 PM PDT 24
Finished Apr 30 01:10:36 PM PDT 24
Peak memory 200812 kb
Host smart-d906d151-5ac3-4c92-b9bf-68281005697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491010882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2491010882
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4016367191
Short name T298
Test name
Test status
Simulation time 65325218 ps
CPU time 0.7 seconds
Started Apr 30 01:10:32 PM PDT 24
Finished Apr 30 01:10:33 PM PDT 24
Peak memory 200628 kb
Host smart-6252b38c-fef9-49ff-9155-98129866db3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016367191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4016367191
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1050590911
Short name T315
Test name
Test status
Simulation time 2166132761 ps
CPU time 7.36 seconds
Started Apr 30 01:10:34 PM PDT 24
Finished Apr 30 01:10:42 PM PDT 24
Peak memory 222680 kb
Host smart-d2e7d796-4892-4ade-981b-3691d32ee6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050590911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1050590911
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3096108201
Short name T488
Test name
Test status
Simulation time 244080436 ps
CPU time 1.08 seconds
Started Apr 30 01:10:33 PM PDT 24
Finished Apr 30 01:10:35 PM PDT 24
Peak memory 218076 kb
Host smart-59829214-48e1-48d2-8133-458702b4fe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096108201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3096108201
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.302043083
Short name T521
Test name
Test status
Simulation time 132908817 ps
CPU time 0.83 seconds
Started Apr 30 01:10:28 PM PDT 24
Finished Apr 30 01:10:30 PM PDT 24
Peak memory 200668 kb
Host smart-c5df6d82-386b-4336-8f4e-7e715db37048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302043083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.302043083
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.978962453
Short name T481
Test name
Test status
Simulation time 1552253472 ps
CPU time 5.83 seconds
Started Apr 30 01:10:27 PM PDT 24
Finished Apr 30 01:10:34 PM PDT 24
Peak memory 200948 kb
Host smart-6df6d9f8-3b94-44f3-9b16-591b877e579c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978962453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.978962453
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1673841152
Short name T198
Test name
Test status
Simulation time 140366070 ps
CPU time 1.09 seconds
Started Apr 30 01:10:29 PM PDT 24
Finished Apr 30 01:10:31 PM PDT 24
Peak memory 200804 kb
Host smart-ec653d60-1d9f-4bb5-858f-a230c0354190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673841152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1673841152
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2431642342
Short name T399
Test name
Test status
Simulation time 204697819 ps
CPU time 1.45 seconds
Started Apr 30 01:10:34 PM PDT 24
Finished Apr 30 01:10:36 PM PDT 24
Peak memory 200996 kb
Host smart-709b02b0-b677-448e-b92e-4e3ed330d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431642342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2431642342
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.386564801
Short name T433
Test name
Test status
Simulation time 5867029386 ps
CPU time 20 seconds
Started Apr 30 01:10:32 PM PDT 24
Finished Apr 30 01:10:53 PM PDT 24
Peak memory 209380 kb
Host smart-4c8c7f89-0ddb-40de-b18a-6d76b237350b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386564801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.386564801
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1113013508
Short name T147
Test name
Test status
Simulation time 422038622 ps
CPU time 2.38 seconds
Started Apr 30 01:10:26 PM PDT 24
Finished Apr 30 01:10:29 PM PDT 24
Peak memory 208960 kb
Host smart-81231d5f-430c-4307-b22e-27ee7b6d1b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113013508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1113013508
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2241185624
Short name T382
Test name
Test status
Simulation time 79913136 ps
CPU time 0.86 seconds
Started Apr 30 01:10:28 PM PDT 24
Finished Apr 30 01:10:29 PM PDT 24
Peak memory 200880 kb
Host smart-391bc4b1-4b5c-44a4-9b2d-1b9d9909833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241185624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2241185624
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3647817947
Short name T349
Test name
Test status
Simulation time 76164705 ps
CPU time 0.84 seconds
Started Apr 30 01:10:39 PM PDT 24
Finished Apr 30 01:10:40 PM PDT 24
Peak memory 200728 kb
Host smart-56a74980-b9e5-4132-a1e8-789898b388ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647817947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3647817947
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.56196407
Short name T270
Test name
Test status
Simulation time 1226752470 ps
CPU time 5.3 seconds
Started Apr 30 01:10:32 PM PDT 24
Finished Apr 30 01:10:37 PM PDT 24
Peak memory 218560 kb
Host smart-90ac6ca4-3ef8-4ef3-85f8-405e245382fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56196407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.56196407
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.860119803
Short name T520
Test name
Test status
Simulation time 245663775 ps
CPU time 1.11 seconds
Started Apr 30 01:10:32 PM PDT 24
Finished Apr 30 01:10:34 PM PDT 24
Peak memory 218024 kb
Host smart-e598aa4b-a21b-4ce1-8f2e-c641d7e0b92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860119803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.860119803
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3735871153
Short name T201
Test name
Test status
Simulation time 160329529 ps
CPU time 0.83 seconds
Started Apr 30 01:10:33 PM PDT 24
Finished Apr 30 01:10:34 PM PDT 24
Peak memory 200644 kb
Host smart-6bc78724-991e-49f3-bbb0-88c5f7af3d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735871153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3735871153
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.34214326
Short name T227
Test name
Test status
Simulation time 1888959292 ps
CPU time 7.05 seconds
Started Apr 30 01:10:32 PM PDT 24
Finished Apr 30 01:10:40 PM PDT 24
Peak memory 201084 kb
Host smart-d9d51542-968d-4e30-9938-c7b080bdffa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34214326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.34214326
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2915112350
Short name T294
Test name
Test status
Simulation time 145356047 ps
CPU time 1.1 seconds
Started Apr 30 01:10:32 PM PDT 24
Finished Apr 30 01:10:34 PM PDT 24
Peak memory 200880 kb
Host smart-140e8e97-0a93-47e3-8159-4f2d5caacf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915112350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2915112350
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3716043267
Short name T412
Test name
Test status
Simulation time 257568900 ps
CPU time 1.59 seconds
Started Apr 30 01:10:34 PM PDT 24
Finished Apr 30 01:10:36 PM PDT 24
Peak memory 201096 kb
Host smart-60cb03d8-382a-4c5e-b817-9292a9cee0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716043267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3716043267
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.478886471
Short name T135
Test name
Test status
Simulation time 7001544745 ps
CPU time 24.96 seconds
Started Apr 30 01:10:32 PM PDT 24
Finished Apr 30 01:10:58 PM PDT 24
Peak memory 209388 kb
Host smart-2f444141-00ca-48f8-8e7b-7fa2c18f738a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478886471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.478886471
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.279683419
Short name T379
Test name
Test status
Simulation time 434585763 ps
CPU time 2.41 seconds
Started Apr 30 01:10:36 PM PDT 24
Finished Apr 30 01:10:39 PM PDT 24
Peak memory 200864 kb
Host smart-29404747-3d03-4dc8-ba0b-2491948855b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279683419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.279683419
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.730940507
Short name T335
Test name
Test status
Simulation time 199789759 ps
CPU time 1.29 seconds
Started Apr 30 01:10:34 PM PDT 24
Finished Apr 30 01:10:36 PM PDT 24
Peak memory 200828 kb
Host smart-a98c4f44-3552-4ebc-bfdf-67c9537af878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730940507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.730940507
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3872188063
Short name T321
Test name
Test status
Simulation time 61485031 ps
CPU time 0.75 seconds
Started Apr 30 01:10:51 PM PDT 24
Finished Apr 30 01:10:52 PM PDT 24
Peak memory 200668 kb
Host smart-5baaad2b-8270-4d39-98e5-6fca70cc21c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872188063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3872188063
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.286894032
Short name T269
Test name
Test status
Simulation time 2354225627 ps
CPU time 8.4 seconds
Started Apr 30 01:10:46 PM PDT 24
Finished Apr 30 01:10:55 PM PDT 24
Peak memory 222760 kb
Host smart-7955f891-4f71-4c31-bcec-25b8e3bc65c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286894032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.286894032
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3134999667
Short name T215
Test name
Test status
Simulation time 244075129 ps
CPU time 1.01 seconds
Started Apr 30 01:10:49 PM PDT 24
Finished Apr 30 01:10:51 PM PDT 24
Peak memory 218292 kb
Host smart-42390764-92fd-49ba-9f1d-43f7a91d4597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134999667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3134999667
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2914244071
Short name T544
Test name
Test status
Simulation time 187399438 ps
CPU time 0.89 seconds
Started Apr 30 01:10:39 PM PDT 24
Finished Apr 30 01:10:40 PM PDT 24
Peak memory 200612 kb
Host smart-df3ecdef-f812-437d-9d7b-493008c339d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914244071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2914244071
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1392359812
Short name T310
Test name
Test status
Simulation time 1546551184 ps
CPU time 5.48 seconds
Started Apr 30 01:10:38 PM PDT 24
Finished Apr 30 01:10:44 PM PDT 24
Peak memory 200988 kb
Host smart-c33313fc-ab4f-47a4-abb0-6d3d88ccf6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392359812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1392359812
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.401644528
Short name T374
Test name
Test status
Simulation time 106078896 ps
CPU time 1 seconds
Started Apr 30 01:10:39 PM PDT 24
Finished Apr 30 01:10:41 PM PDT 24
Peak memory 200832 kb
Host smart-2c5bd7c1-f1c5-46e9-927c-2cc1e94096ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401644528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.401644528
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2789529336
Short name T66
Test name
Test status
Simulation time 202824791 ps
CPU time 1.34 seconds
Started Apr 30 01:10:39 PM PDT 24
Finished Apr 30 01:10:41 PM PDT 24
Peak memory 201032 kb
Host smart-a52b6c2e-49d6-41b5-813e-967b973945b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789529336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2789529336
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2711275509
Short name T372
Test name
Test status
Simulation time 1396416716 ps
CPU time 5.88 seconds
Started Apr 30 01:10:50 PM PDT 24
Finished Apr 30 01:10:56 PM PDT 24
Peak memory 209308 kb
Host smart-c0eda811-db6e-438c-80fd-e924665cd6e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711275509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2711275509
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3182193919
Short name T4
Test name
Test status
Simulation time 152161044 ps
CPU time 1.73 seconds
Started Apr 30 01:10:42 PM PDT 24
Finished Apr 30 01:10:44 PM PDT 24
Peak memory 200828 kb
Host smart-aa30bfd6-c927-477e-bd49-b7e913feb8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182193919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3182193919
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2895394047
Short name T468
Test name
Test status
Simulation time 160661200 ps
CPU time 1.16 seconds
Started Apr 30 01:10:39 PM PDT 24
Finished Apr 30 01:10:40 PM PDT 24
Peak memory 201028 kb
Host smart-570b00ee-7b28-435f-a56a-1779c6080f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895394047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2895394047
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.4136691357
Short name T478
Test name
Test status
Simulation time 86784543 ps
CPU time 0.79 seconds
Started Apr 30 01:10:51 PM PDT 24
Finished Apr 30 01:10:52 PM PDT 24
Peak memory 200736 kb
Host smart-22c31112-b4d7-4107-b175-b60e5cd3c9e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136691357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.4136691357
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3247486489
Short name T536
Test name
Test status
Simulation time 2175013778 ps
CPU time 7.85 seconds
Started Apr 30 01:10:51 PM PDT 24
Finished Apr 30 01:10:59 PM PDT 24
Peak memory 217740 kb
Host smart-271b4cea-5fe8-47f5-b0c5-5fcbf2966e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247486489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3247486489
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.325217178
Short name T476
Test name
Test status
Simulation time 244451858 ps
CPU time 1.03 seconds
Started Apr 30 01:10:50 PM PDT 24
Finished Apr 30 01:10:51 PM PDT 24
Peak memory 218116 kb
Host smart-aa8eb999-0abf-4b8b-af2b-2586a372c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325217178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.325217178
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.148388129
Short name T420
Test name
Test status
Simulation time 129899347 ps
CPU time 0.86 seconds
Started Apr 30 01:10:50 PM PDT 24
Finished Apr 30 01:10:51 PM PDT 24
Peak memory 200708 kb
Host smart-bd017e65-d896-44c8-9580-86a5c89f0c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148388129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.148388129
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3468377029
Short name T45
Test name
Test status
Simulation time 753537948 ps
CPU time 3.92 seconds
Started Apr 30 01:10:50 PM PDT 24
Finished Apr 30 01:10:54 PM PDT 24
Peak memory 201092 kb
Host smart-4acddf61-f42f-463c-b5bc-64ebddf45f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468377029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3468377029
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.276735922
Short name T320
Test name
Test status
Simulation time 147399055 ps
CPU time 1.12 seconds
Started Apr 30 01:10:47 PM PDT 24
Finished Apr 30 01:10:49 PM PDT 24
Peak memory 200904 kb
Host smart-53c4251c-53c4-4bff-b26f-226f11feb0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276735922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.276735922
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2154553073
Short name T373
Test name
Test status
Simulation time 251779149 ps
CPU time 1.54 seconds
Started Apr 30 01:10:49 PM PDT 24
Finished Apr 30 01:10:51 PM PDT 24
Peak memory 201036 kb
Host smart-d22a4d39-9f79-4452-bffc-839bc3f84ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154553073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2154553073
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.259181361
Short name T64
Test name
Test status
Simulation time 929120024 ps
CPU time 4.19 seconds
Started Apr 30 01:10:47 PM PDT 24
Finished Apr 30 01:10:52 PM PDT 24
Peak memory 209280 kb
Host smart-77bf83fd-a1ff-4f58-b04d-00d0e9a7185c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259181361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.259181361
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.533312952
Short name T421
Test name
Test status
Simulation time 489983848 ps
CPU time 2.81 seconds
Started Apr 30 01:10:49 PM PDT 24
Finished Apr 30 01:10:52 PM PDT 24
Peak memory 200840 kb
Host smart-068d719c-5103-4319-adf4-d6a7e8086460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533312952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.533312952
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2972742043
Short name T153
Test name
Test status
Simulation time 231285092 ps
CPU time 1.62 seconds
Started Apr 30 01:10:50 PM PDT 24
Finished Apr 30 01:10:52 PM PDT 24
Peak memory 201008 kb
Host smart-278540b7-dd2c-423d-963e-c6e985079717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972742043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2972742043
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1726706574
Short name T292
Test name
Test status
Simulation time 68122602 ps
CPU time 0.78 seconds
Started Apr 30 01:11:03 PM PDT 24
Finished Apr 30 01:11:05 PM PDT 24
Peak memory 200664 kb
Host smart-b9bf1b4b-0289-4478-90c1-20aec53eb2fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726706574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1726706574
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1617741609
Short name T394
Test name
Test status
Simulation time 1877624306 ps
CPU time 7.26 seconds
Started Apr 30 01:11:01 PM PDT 24
Finished Apr 30 01:11:09 PM PDT 24
Peak memory 218788 kb
Host smart-bb3b2a75-61cb-408c-befd-afd06e8b9c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617741609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1617741609
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2043564704
Short name T518
Test name
Test status
Simulation time 244035287 ps
CPU time 1.17 seconds
Started Apr 30 01:11:01 PM PDT 24
Finished Apr 30 01:11:03 PM PDT 24
Peak memory 218072 kb
Host smart-5d9e3d7a-9b50-4d46-bb62-4a6e2fe4979f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043564704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2043564704
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3928327036
Short name T26
Test name
Test status
Simulation time 88455040 ps
CPU time 0.83 seconds
Started Apr 30 01:11:03 PM PDT 24
Finished Apr 30 01:11:04 PM PDT 24
Peak memory 200652 kb
Host smart-9cae620d-8f8a-43da-822e-4f57e2bdf532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928327036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3928327036
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.829099465
Short name T264
Test name
Test status
Simulation time 1763077958 ps
CPU time 7.03 seconds
Started Apr 30 01:11:03 PM PDT 24
Finished Apr 30 01:11:10 PM PDT 24
Peak memory 201052 kb
Host smart-8ab79d0c-9efe-4c21-b154-0e93c44e3239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829099465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.829099465
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3419710048
Short name T288
Test name
Test status
Simulation time 164440960 ps
CPU time 1.1 seconds
Started Apr 30 01:11:03 PM PDT 24
Finished Apr 30 01:11:04 PM PDT 24
Peak memory 200840 kb
Host smart-a512e6a0-72f6-47fa-b5c5-648dcf5a4b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419710048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3419710048
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1335334154
Short name T447
Test name
Test status
Simulation time 187740793 ps
CPU time 1.45 seconds
Started Apr 30 01:11:02 PM PDT 24
Finished Apr 30 01:11:04 PM PDT 24
Peak memory 201088 kb
Host smart-e78b1855-3c0a-4535-b8ae-fa9a67ff8891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335334154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1335334154
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2232678629
Short name T163
Test name
Test status
Simulation time 5751168845 ps
CPU time 24.69 seconds
Started Apr 30 01:11:01 PM PDT 24
Finished Apr 30 01:11:26 PM PDT 24
Peak memory 209408 kb
Host smart-746bd9ea-aa2d-4535-a7fb-17bba726e601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232678629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2232678629
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3718157122
Short name T172
Test name
Test status
Simulation time 391034241 ps
CPU time 2.31 seconds
Started Apr 30 01:11:01 PM PDT 24
Finished Apr 30 01:11:04 PM PDT 24
Peak memory 200824 kb
Host smart-9c9cdba8-a18c-4fbf-809a-010057b632d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718157122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3718157122
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2166727363
Short name T410
Test name
Test status
Simulation time 240322681 ps
CPU time 1.36 seconds
Started Apr 30 01:11:02 PM PDT 24
Finished Apr 30 01:11:04 PM PDT 24
Peak memory 200840 kb
Host smart-b086bfa9-b356-4ea2-885c-1d16739950c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166727363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2166727363
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4167322084
Short name T6
Test name
Test status
Simulation time 77580581 ps
CPU time 0.83 seconds
Started Apr 30 01:11:03 PM PDT 24
Finished Apr 30 01:11:05 PM PDT 24
Peak memory 200728 kb
Host smart-ab4dcd94-cb90-435f-aad1-ac05c8c52310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167322084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4167322084
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3871901850
Short name T48
Test name
Test status
Simulation time 2368677590 ps
CPU time 8.76 seconds
Started Apr 30 01:11:02 PM PDT 24
Finished Apr 30 01:11:11 PM PDT 24
Peak memory 222480 kb
Host smart-b57e4310-45d4-4c0e-bcad-b19c635dbe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871901850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3871901850
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3363134553
Short name T81
Test name
Test status
Simulation time 244540263 ps
CPU time 1.14 seconds
Started Apr 30 01:11:02 PM PDT 24
Finished Apr 30 01:11:04 PM PDT 24
Peak memory 218128 kb
Host smart-d16bb19a-3966-4ce9-b58c-b3a7ea9fb1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363134553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3363134553
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2499974873
Short name T397
Test name
Test status
Simulation time 108996974 ps
CPU time 0.77 seconds
Started Apr 30 01:11:03 PM PDT 24
Finished Apr 30 01:11:04 PM PDT 24
Peak memory 200708 kb
Host smart-f39fe2d3-6108-49be-a63f-4af60fb55621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499974873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2499974873
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.524091516
Short name T28
Test name
Test status
Simulation time 1525208958 ps
CPU time 5.8 seconds
Started Apr 30 01:11:01 PM PDT 24
Finished Apr 30 01:11:08 PM PDT 24
Peak memory 201032 kb
Host smart-958dca6b-1171-4ec5-a929-31d8a06079bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524091516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.524091516
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3038279337
Short name T3
Test name
Test status
Simulation time 176955888 ps
CPU time 1.22 seconds
Started Apr 30 01:11:01 PM PDT 24
Finished Apr 30 01:11:03 PM PDT 24
Peak memory 200848 kb
Host smart-356ff319-d7e7-4ba4-95f9-6f94e847eda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038279337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3038279337
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.861356174
Short name T89
Test name
Test status
Simulation time 126072554 ps
CPU time 1.21 seconds
Started Apr 30 01:11:01 PM PDT 24
Finished Apr 30 01:11:02 PM PDT 24
Peak memory 200980 kb
Host smart-885d1fce-ca72-4811-9ce2-83d2423b9785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861356174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.861356174
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.999924467
Short name T195
Test name
Test status
Simulation time 3306098710 ps
CPU time 15.07 seconds
Started Apr 30 01:11:03 PM PDT 24
Finished Apr 30 01:11:18 PM PDT 24
Peak memory 201176 kb
Host smart-ab70916a-d460-4de4-8b8f-6e7df54657d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999924467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.999924467
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.743232545
Short name T541
Test name
Test status
Simulation time 146313904 ps
CPU time 1.69 seconds
Started Apr 30 01:11:01 PM PDT 24
Finished Apr 30 01:11:03 PM PDT 24
Peak memory 200824 kb
Host smart-bcd29f52-f71c-4abd-812b-5217b4e4c025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743232545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.743232545
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1851779941
Short name T359
Test name
Test status
Simulation time 138208326 ps
CPU time 1.12 seconds
Started Apr 30 01:11:03 PM PDT 24
Finished Apr 30 01:11:05 PM PDT 24
Peak memory 200888 kb
Host smart-a772d01d-2f60-433a-9b23-4cfa6c776868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851779941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1851779941
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1375669196
Short name T244
Test name
Test status
Simulation time 71858166 ps
CPU time 0.77 seconds
Started Apr 30 01:06:38 PM PDT 24
Finished Apr 30 01:06:39 PM PDT 24
Peak memory 200640 kb
Host smart-e5c2142a-6737-4822-a691-3f9bea387957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375669196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1375669196
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.128505431
Short name T343
Test name
Test status
Simulation time 2177884870 ps
CPU time 8.09 seconds
Started Apr 30 01:06:32 PM PDT 24
Finished Apr 30 01:06:41 PM PDT 24
Peak memory 230012 kb
Host smart-687d53a0-f191-4b16-a4c6-ad56cb5d7021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128505431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.128505431
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2434737597
Short name T511
Test name
Test status
Simulation time 244287800 ps
CPU time 1.05 seconds
Started Apr 30 01:06:30 PM PDT 24
Finished Apr 30 01:06:32 PM PDT 24
Peak memory 218180 kb
Host smart-1bee7364-a60b-452b-94d5-7764efc73756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434737597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2434737597
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3963530808
Short name T411
Test name
Test status
Simulation time 93873811 ps
CPU time 0.77 seconds
Started Apr 30 01:06:25 PM PDT 24
Finished Apr 30 01:06:26 PM PDT 24
Peak memory 200712 kb
Host smart-1ec95d3d-c1a7-4744-b792-40e0a465eb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963530808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3963530808
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1018086502
Short name T12
Test name
Test status
Simulation time 1588542818 ps
CPU time 6.24 seconds
Started Apr 30 01:06:31 PM PDT 24
Finished Apr 30 01:06:37 PM PDT 24
Peak memory 201052 kb
Host smart-519042c8-59d9-4f15-933b-2f9ec2ee68d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018086502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1018086502
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4192459384
Short name T194
Test name
Test status
Simulation time 143239121 ps
CPU time 1.21 seconds
Started Apr 30 01:06:34 PM PDT 24
Finished Apr 30 01:06:35 PM PDT 24
Peak memory 200820 kb
Host smart-15e20d80-e34a-4c1b-8dde-8f17b8dff4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192459384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4192459384
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.236866062
Short name T452
Test name
Test status
Simulation time 192280601 ps
CPU time 1.45 seconds
Started Apr 30 01:06:27 PM PDT 24
Finished Apr 30 01:06:29 PM PDT 24
Peak memory 201024 kb
Host smart-4602257b-d341-4fbd-b5be-45eaf8c1d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236866062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.236866062
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3406505485
Short name T331
Test name
Test status
Simulation time 5768734512 ps
CPU time 20.07 seconds
Started Apr 30 01:06:37 PM PDT 24
Finished Apr 30 01:06:57 PM PDT 24
Peak memory 209412 kb
Host smart-ddf6b12c-9429-4e7d-b7bb-b24deacb3686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406505485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3406505485
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.46009156
Short name T155
Test name
Test status
Simulation time 272959351 ps
CPU time 1.89 seconds
Started Apr 30 01:06:30 PM PDT 24
Finished Apr 30 01:06:33 PM PDT 24
Peak memory 200844 kb
Host smart-4c46c19e-4fed-45a1-b0fa-0977907771ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46009156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.46009156
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3397972213
Short name T210
Test name
Test status
Simulation time 106077853 ps
CPU time 0.99 seconds
Started Apr 30 01:06:31 PM PDT 24
Finished Apr 30 01:06:32 PM PDT 24
Peak memory 200868 kb
Host smart-9d4bb9fc-f8c2-4ea6-8a15-e0dee39a7bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397972213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3397972213
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.658688083
Short name T228
Test name
Test status
Simulation time 76897103 ps
CPU time 0.77 seconds
Started Apr 30 01:06:50 PM PDT 24
Finished Apr 30 01:06:51 PM PDT 24
Peak memory 200556 kb
Host smart-20c02871-af26-4152-b44b-438e4942c026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658688083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.658688083
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3735724411
Short name T61
Test name
Test status
Simulation time 1878387381 ps
CPU time 7.83 seconds
Started Apr 30 01:06:51 PM PDT 24
Finished Apr 30 01:06:59 PM PDT 24
Peak memory 230900 kb
Host smart-8a34fda8-557e-4688-840a-e5753ed8e073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735724411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3735724411
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1142022325
Short name T351
Test name
Test status
Simulation time 243860686 ps
CPU time 1.14 seconds
Started Apr 30 01:06:51 PM PDT 24
Finished Apr 30 01:06:53 PM PDT 24
Peak memory 218036 kb
Host smart-dfeddae9-3a51-4ab2-a353-cfcedd060a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142022325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1142022325
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2479523373
Short name T21
Test name
Test status
Simulation time 175577159 ps
CPU time 0.84 seconds
Started Apr 30 01:06:35 PM PDT 24
Finished Apr 30 01:06:37 PM PDT 24
Peak memory 200692 kb
Host smart-24c277b6-f529-48db-aa89-1bcbae95dcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479523373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2479523373
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2774604474
Short name T525
Test name
Test status
Simulation time 1905511659 ps
CPU time 6.81 seconds
Started Apr 30 01:06:44 PM PDT 24
Finished Apr 30 01:06:51 PM PDT 24
Peak memory 201124 kb
Host smart-f0360432-7333-4e52-898a-90e2a16d32ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774604474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2774604474
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3959830430
Short name T465
Test name
Test status
Simulation time 102746817 ps
CPU time 0.94 seconds
Started Apr 30 01:06:50 PM PDT 24
Finished Apr 30 01:06:52 PM PDT 24
Peak memory 200756 kb
Host smart-8c0acd1f-dc8c-4a13-8155-07bcc559178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959830430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3959830430
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3033453805
Short name T141
Test name
Test status
Simulation time 194083859 ps
CPU time 1.39 seconds
Started Apr 30 01:06:36 PM PDT 24
Finished Apr 30 01:06:38 PM PDT 24
Peak memory 201084 kb
Host smart-a928d62e-351c-4495-955f-304304af21bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033453805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3033453805
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2606192563
Short name T257
Test name
Test status
Simulation time 199614793 ps
CPU time 1.34 seconds
Started Apr 30 01:06:48 PM PDT 24
Finished Apr 30 01:06:50 PM PDT 24
Peak memory 200860 kb
Host smart-91faa85e-12bd-4f6d-a0a1-c520bca3fd82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606192563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2606192563
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4277700277
Short name T439
Test name
Test status
Simulation time 363275084 ps
CPU time 1.91 seconds
Started Apr 30 01:06:44 PM PDT 24
Finished Apr 30 01:06:47 PM PDT 24
Peak memory 200860 kb
Host smart-c3863fc2-6fc2-48e0-9220-ed4a25c5b1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277700277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4277700277
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3328812974
Short name T166
Test name
Test status
Simulation time 134787555 ps
CPU time 1.08 seconds
Started Apr 30 01:06:44 PM PDT 24
Finished Apr 30 01:06:46 PM PDT 24
Peak memory 200904 kb
Host smart-3fb5753b-9d97-4f4d-99c3-49c89d96ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328812974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3328812974
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2039757406
Short name T438
Test name
Test status
Simulation time 57692743 ps
CPU time 0.72 seconds
Started Apr 30 01:07:03 PM PDT 24
Finished Apr 30 01:07:04 PM PDT 24
Peak memory 200588 kb
Host smart-d64ba4c7-311c-47e9-b1ad-492a1440a99b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039757406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2039757406
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3440671541
Short name T42
Test name
Test status
Simulation time 1220293997 ps
CPU time 5.53 seconds
Started Apr 30 01:06:57 PM PDT 24
Finished Apr 30 01:07:03 PM PDT 24
Peak memory 222676 kb
Host smart-5d7ffdd6-c82e-42ab-b125-663a2b157e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440671541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3440671541
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4246105835
Short name T87
Test name
Test status
Simulation time 244613344 ps
CPU time 1.04 seconds
Started Apr 30 01:06:55 PM PDT 24
Finished Apr 30 01:06:56 PM PDT 24
Peak memory 218056 kb
Host smart-e17f4307-16d8-46d4-8b83-1963cd3d5b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246105835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4246105835
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.994961178
Short name T208
Test name
Test status
Simulation time 76863842 ps
CPU time 0.72 seconds
Started Apr 30 01:06:55 PM PDT 24
Finished Apr 30 01:06:56 PM PDT 24
Peak memory 200616 kb
Host smart-4bf7fc57-924d-42a2-a75f-06db43e35940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994961178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.994961178
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3216012123
Short name T480
Test name
Test status
Simulation time 1061913832 ps
CPU time 5.42 seconds
Started Apr 30 01:06:57 PM PDT 24
Finished Apr 30 01:07:02 PM PDT 24
Peak memory 201128 kb
Host smart-337cb3f1-32c3-4c8e-a35a-45a4f6947d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216012123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3216012123
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1821027475
Short name T530
Test name
Test status
Simulation time 135486197 ps
CPU time 1.04 seconds
Started Apr 30 01:06:58 PM PDT 24
Finished Apr 30 01:07:00 PM PDT 24
Peak memory 200860 kb
Host smart-b2e42c66-9189-4eab-9347-d9b9558deb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821027475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1821027475
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1949549322
Short name T369
Test name
Test status
Simulation time 184942360 ps
CPU time 1.43 seconds
Started Apr 30 01:06:51 PM PDT 24
Finished Apr 30 01:06:53 PM PDT 24
Peak memory 201008 kb
Host smart-9486a39a-7e79-419e-813c-1c52fc0a15c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949549322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1949549322
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.743207658
Short name T501
Test name
Test status
Simulation time 7183172015 ps
CPU time 30.07 seconds
Started Apr 30 01:07:03 PM PDT 24
Finished Apr 30 01:07:33 PM PDT 24
Peak memory 209428 kb
Host smart-93920017-309a-48cf-b555-8a14dcb00470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743207658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.743207658
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1266216638
Short name T8
Test name
Test status
Simulation time 142958435 ps
CPU time 1.66 seconds
Started Apr 30 01:06:56 PM PDT 24
Finished Apr 30 01:06:58 PM PDT 24
Peak memory 209036 kb
Host smart-6f07205c-9659-4839-8855-68b5fedf6512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266216638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1266216638
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1145174002
Short name T80
Test name
Test status
Simulation time 95456021 ps
CPU time 0.77 seconds
Started Apr 30 01:06:56 PM PDT 24
Finished Apr 30 01:06:57 PM PDT 24
Peak memory 200884 kb
Host smart-869f7e4e-4f37-46ba-affd-c4da57fcc2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145174002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1145174002
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1013324047
Short name T67
Test name
Test status
Simulation time 91317677 ps
CPU time 0.86 seconds
Started Apr 30 01:07:17 PM PDT 24
Finished Apr 30 01:07:18 PM PDT 24
Peak memory 200632 kb
Host smart-2de8b3cf-0d50-43dd-a116-6dcdab1a7bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013324047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1013324047
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2857357784
Short name T37
Test name
Test status
Simulation time 1893883707 ps
CPU time 6.96 seconds
Started Apr 30 01:07:05 PM PDT 24
Finished Apr 30 01:07:13 PM PDT 24
Peak memory 222056 kb
Host smart-1a0809a9-7d0d-43d2-a729-9887180a5e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857357784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2857357784
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3886141534
Short name T419
Test name
Test status
Simulation time 243399544 ps
CPU time 1.12 seconds
Started Apr 30 01:07:09 PM PDT 24
Finished Apr 30 01:07:10 PM PDT 24
Peak memory 218248 kb
Host smart-9754a753-6da4-4de7-83da-77830c36620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886141534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3886141534
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2914743486
Short name T361
Test name
Test status
Simulation time 207535620 ps
CPU time 1.04 seconds
Started Apr 30 01:07:02 PM PDT 24
Finished Apr 30 01:07:04 PM PDT 24
Peak memory 200644 kb
Host smart-168ab85a-f7a7-48f3-b1cc-47ba763f07eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914743486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2914743486
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3798631223
Short name T111
Test name
Test status
Simulation time 1612546538 ps
CPU time 6.5 seconds
Started Apr 30 01:07:01 PM PDT 24
Finished Apr 30 01:07:08 PM PDT 24
Peak memory 201052 kb
Host smart-5ee482c2-21ab-4058-a8f9-75ba062e0518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798631223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3798631223
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1789380893
Short name T274
Test name
Test status
Simulation time 187157903 ps
CPU time 1.28 seconds
Started Apr 30 01:07:02 PM PDT 24
Finished Apr 30 01:07:03 PM PDT 24
Peak memory 200804 kb
Host smart-61420f18-fdc9-4f29-bbac-52e5756e0b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789380893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1789380893
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3957201767
Short name T509
Test name
Test status
Simulation time 188783198 ps
CPU time 1.32 seconds
Started Apr 30 01:07:05 PM PDT 24
Finished Apr 30 01:07:07 PM PDT 24
Peak memory 201088 kb
Host smart-8075a000-9c76-433c-b173-6adef32e4ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957201767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3957201767
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2523604331
Short name T428
Test name
Test status
Simulation time 203565306 ps
CPU time 1.52 seconds
Started Apr 30 01:07:10 PM PDT 24
Finished Apr 30 01:07:12 PM PDT 24
Peak memory 201044 kb
Host smart-25971982-c931-435c-ba52-4660725e7654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523604331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2523604331
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.964369127
Short name T175
Test name
Test status
Simulation time 264194503 ps
CPU time 1.73 seconds
Started Apr 30 01:07:04 PM PDT 24
Finished Apr 30 01:07:06 PM PDT 24
Peak memory 200908 kb
Host smart-b95d5c32-6b08-44b2-ac99-68a847e35e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964369127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.964369127
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1737250726
Short name T322
Test name
Test status
Simulation time 272998240 ps
CPU time 1.52 seconds
Started Apr 30 01:07:02 PM PDT 24
Finished Apr 30 01:07:04 PM PDT 24
Peak memory 200880 kb
Host smart-ddaf5446-6c56-4630-ac87-65f9805ac465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737250726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1737250726
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1719962115
Short name T204
Test name
Test status
Simulation time 64121590 ps
CPU time 0.78 seconds
Started Apr 30 01:07:27 PM PDT 24
Finished Apr 30 01:07:28 PM PDT 24
Peak memory 200632 kb
Host smart-8b266647-44b7-407f-9f1a-2f1911b621a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719962115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1719962115
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2437481683
Short name T296
Test name
Test status
Simulation time 2369726238 ps
CPU time 8.42 seconds
Started Apr 30 01:07:26 PM PDT 24
Finished Apr 30 01:07:35 PM PDT 24
Peak memory 218352 kb
Host smart-3cf8e99e-a150-4f4d-b156-5bde011f8251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437481683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2437481683
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3859956241
Short name T271
Test name
Test status
Simulation time 244496035 ps
CPU time 1.03 seconds
Started Apr 30 01:07:15 PM PDT 24
Finished Apr 30 01:07:16 PM PDT 24
Peak memory 217992 kb
Host smart-c5ebb4c0-614f-4570-917a-e915772561eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859956241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3859956241
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.852735961
Short name T285
Test name
Test status
Simulation time 145867606 ps
CPU time 0.84 seconds
Started Apr 30 01:07:10 PM PDT 24
Finished Apr 30 01:07:11 PM PDT 24
Peak memory 200720 kb
Host smart-0489205d-9379-43de-aa38-e090202e41ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852735961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.852735961
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3561804845
Short name T457
Test name
Test status
Simulation time 1563548761 ps
CPU time 5.54 seconds
Started Apr 30 01:07:10 PM PDT 24
Finished Apr 30 01:07:16 PM PDT 24
Peak memory 201036 kb
Host smart-55fee0dc-9955-4f2a-8e62-6acced986653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561804845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3561804845
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3981643747
Short name T212
Test name
Test status
Simulation time 185575265 ps
CPU time 1.21 seconds
Started Apr 30 01:07:27 PM PDT 24
Finished Apr 30 01:07:29 PM PDT 24
Peak memory 200824 kb
Host smart-ab741cb2-a163-4c5d-b89d-45e44742a072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981643747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3981643747
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1702845054
Short name T532
Test name
Test status
Simulation time 123987540 ps
CPU time 1.19 seconds
Started Apr 30 01:07:10 PM PDT 24
Finished Apr 30 01:07:12 PM PDT 24
Peak memory 201020 kb
Host smart-ef52a590-02bd-490a-80bb-75f64132e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702845054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1702845054
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1244381042
Short name T110
Test name
Test status
Simulation time 3462761617 ps
CPU time 14.86 seconds
Started Apr 30 01:07:16 PM PDT 24
Finished Apr 30 01:07:31 PM PDT 24
Peak memory 209456 kb
Host smart-0e1e11c5-8418-4658-b363-de5c14c8e4a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244381042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1244381042
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.892068244
Short name T355
Test name
Test status
Simulation time 356701203 ps
CPU time 2.45 seconds
Started Apr 30 01:07:11 PM PDT 24
Finished Apr 30 01:07:13 PM PDT 24
Peak memory 200836 kb
Host smart-392d9b78-1f9a-4939-869b-2f84bdbb0f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892068244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.892068244
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2662500490
Short name T7
Test name
Test status
Simulation time 98740512 ps
CPU time 0.91 seconds
Started Apr 30 01:07:07 PM PDT 24
Finished Apr 30 01:07:09 PM PDT 24
Peak memory 200868 kb
Host smart-e0949b84-7e75-4a19-9b80-fb8582df15cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662500490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2662500490
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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