Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8236

1

T2

3

T3

31

T7

14

auto[1]

11494

1

T1

4

T2

1

T3

27

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5999	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6598	1			T1	2		T2	1		T3	17
reset_info_cp[2]	3065	1			T1	1		T3	11		T4	1
reset_info_cp[4]	4115	1			T1	1		T3	15		T4	1
reset_info_cp[8]	119	1			T3	1		T13	1		T53	1
reset_info_cp[16]	117	1			T13	2		T25	2		T94	1
reset_info_cp[32]	126	1			T1	1		T8	2		T13	1
reset_info_cp[64]	106	1			T3	1		T7	1		T8	2
reset_info_cp[128]	105	1			T2	1		T25	2		T53	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3113	1			T3	9		T7	14		T8	18
reset_info_cp[1]	auto[1]	2865	1			T1	1		T3	7		T4	1
reset_info_cp[2]	auto[0]	901	1			T3	3		T13	18		T86	4
reset_info_cp[2]	auto[1]	2164	1			T1	1		T3	8		T4	1
reset_info_cp[4]	auto[0]	1472	1			T3	9		T13	27		T86	8
reset_info_cp[4]	auto[1]	2643	1			T1	1		T3	6		T4	1
reset_info_cp[8]	auto[0]	49	1			T3	1		T53	1		T97	1
reset_info_cp[8]	auto[1]	70	1			T13	1		T105	1		T39	2
reset_info_cp[16]	auto[0]	52	1			T13	2		T25	2		T97	1
reset_info_cp[16]	auto[1]	65	1			T94	1		T54	1		T32	1
reset_info_cp[32]	auto[0]	54	1			T53	3		T51	1		T97	1
reset_info_cp[32]	auto[1]	72	1			T1	1		T8	2		T13	1
reset_info_cp[64]	auto[0]	44	1			T25	1		T93	1		T103	1
reset_info_cp[64]	auto[1]	62	1			T3	1		T7	1		T8	2
reset_info_cp[128]	auto[0]	41	1			T2	1		T25	2		T95	1
reset_info_cp[128]	auto[1]	64	1			T53	1		T54	1		T120	1