Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.87 99.83 99.46 98.77


Total test records in report: 620
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T536 /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3868478107 May 02 01:35:49 PM PDT 24 May 02 01:35:51 PM PDT 24 167456188 ps
T537 /workspace/coverage/default/30.rstmgr_smoke.3783693033 May 02 01:35:15 PM PDT 24 May 02 01:35:17 PM PDT 24 194621739 ps
T538 /workspace/coverage/default/20.rstmgr_sw_rst.566976166 May 02 01:34:36 PM PDT 24 May 02 01:34:38 PM PDT 24 326080515 ps
T539 /workspace/coverage/default/28.rstmgr_smoke.2261895567 May 02 01:35:01 PM PDT 24 May 02 01:35:03 PM PDT 24 108404573 ps
T540 /workspace/coverage/default/17.rstmgr_reset.1797391776 May 02 01:34:25 PM PDT 24 May 02 01:34:32 PM PDT 24 1581629266 ps
T57 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3558570063 May 02 01:32:53 PM PDT 24 May 02 01:32:56 PM PDT 24 234287595 ps
T58 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4259322052 May 02 01:31:47 PM PDT 24 May 02 01:31:49 PM PDT 24 179954499 ps
T59 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.742241470 May 02 01:31:33 PM PDT 24 May 02 01:31:37 PM PDT 24 271994248 ps
T60 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2471335190 May 02 01:32:59 PM PDT 24 May 02 01:33:03 PM PDT 24 200833268 ps
T61 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4165078778 May 02 01:31:28 PM PDT 24 May 02 01:31:31 PM PDT 24 200159761 ps
T62 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1105131333 May 02 01:31:49 PM PDT 24 May 02 01:31:53 PM PDT 24 421990905 ps
T63 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3204885615 May 02 01:32:37 PM PDT 24 May 02 01:32:42 PM PDT 24 659281301 ps
T83 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1252139178 May 02 01:31:57 PM PDT 24 May 02 01:32:00 PM PDT 24 320607199 ps
T110 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2813330887 May 02 01:32:52 PM PDT 24 May 02 01:32:54 PM PDT 24 80659070 ps
T84 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.332044310 May 02 01:32:30 PM PDT 24 May 02 01:32:33 PM PDT 24 126280486 ps
T82 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1508199108 May 02 01:32:21 PM PDT 24 May 02 01:32:23 PM PDT 24 273167432 ps
T80 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3283403884 May 02 01:32:12 PM PDT 24 May 02 01:32:14 PM PDT 24 62285615 ps
T130 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1888090162 May 02 01:32:30 PM PDT 24 May 02 01:32:31 PM PDT 24 64362450 ps
T90 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2075271610 May 02 01:32:05 PM PDT 24 May 02 01:32:09 PM PDT 24 172370433 ps
T111 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2547607506 May 02 01:32:44 PM PDT 24 May 02 01:32:45 PM PDT 24 54830846 ps
T541 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.655367804 May 02 01:32:02 PM PDT 24 May 02 01:32:04 PM PDT 24 146774964 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.413215025 May 02 01:31:48 PM PDT 24 May 02 01:31:50 PM PDT 24 104196493 ps
T81 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.425045083 May 02 01:32:49 PM PDT 24 May 02 01:32:52 PM PDT 24 187775242 ps
T91 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1156619171 May 02 01:32:13 PM PDT 24 May 02 01:32:16 PM PDT 24 126942327 ps
T104 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1809119183 May 02 01:32:45 PM PDT 24 May 02 01:32:48 PM PDT 24 170070106 ps
T543 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.66865051 May 02 01:33:00 PM PDT 24 May 02 01:33:02 PM PDT 24 80243984 ps
T67 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4276533908 May 02 01:32:29 PM PDT 24 May 02 01:32:33 PM PDT 24 875662730 ps
T78 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2506757476 May 02 01:32:12 PM PDT 24 May 02 01:32:15 PM PDT 24 646504016 ps
T544 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3519008315 May 02 01:32:39 PM PDT 24 May 02 01:32:41 PM PDT 24 172609129 ps
T79 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1143922292 May 02 01:31:48 PM PDT 24 May 02 01:31:51 PM PDT 24 463957174 ps
T88 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3816109497 May 02 01:32:29 PM PDT 24 May 02 01:32:31 PM PDT 24 467873292 ps
T112 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.456179748 May 02 01:32:40 PM PDT 24 May 02 01:32:43 PM PDT 24 128455661 ps
T124 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3478303790 May 02 01:31:56 PM PDT 24 May 02 01:32:00 PM PDT 24 882994431 ps
T545 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4149629070 May 02 01:32:43 PM PDT 24 May 02 01:32:45 PM PDT 24 195123131 ps
T113 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2927395747 May 02 01:32:20 PM PDT 24 May 02 01:32:22 PM PDT 24 68664180 ps
T114 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.920619538 May 02 01:32:29 PM PDT 24 May 02 01:32:31 PM PDT 24 216777584 ps
T126 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2900271870 May 02 01:32:35 PM PDT 24 May 02 01:32:38 PM PDT 24 464822774 ps
T546 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.198420954 May 02 01:32:22 PM PDT 24 May 02 01:32:23 PM PDT 24 114940444 ps
T547 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1028158812 May 02 01:31:42 PM PDT 24 May 02 01:31:44 PM PDT 24 87816765 ps
T125 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3438509327 May 02 01:32:14 PM PDT 24 May 02 01:32:18 PM PDT 24 917537750 ps
T89 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1776293553 May 02 01:32:22 PM PDT 24 May 02 01:32:26 PM PDT 24 885163723 ps
T115 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.945158736 May 02 01:32:36 PM PDT 24 May 02 01:32:38 PM PDT 24 55413415 ps
T548 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3358540890 May 02 01:32:35 PM PDT 24 May 02 01:32:37 PM PDT 24 127817557 ps
T549 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.970427428 May 02 01:32:40 PM PDT 24 May 02 01:32:43 PM PDT 24 104995295 ps
T550 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.332214564 May 02 01:32:20 PM PDT 24 May 02 01:32:21 PM PDT 24 75249448 ps
T551 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3532551601 May 02 01:32:30 PM PDT 24 May 02 01:32:32 PM PDT 24 196522796 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.241525016 May 02 01:32:03 PM PDT 24 May 02 01:32:05 PM PDT 24 67492235 ps
T553 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2651568403 May 02 01:33:00 PM PDT 24 May 02 01:33:02 PM PDT 24 59452341 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1153590193 May 02 01:31:44 PM PDT 24 May 02 01:31:46 PM PDT 24 97075915 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2195757740 May 02 01:31:34 PM PDT 24 May 02 01:31:36 PM PDT 24 118194267 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1017773857 May 02 01:31:40 PM PDT 24 May 02 01:31:47 PM PDT 24 794958057 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3081676964 May 02 01:31:56 PM PDT 24 May 02 01:31:57 PM PDT 24 97290559 ps
T558 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.607710241 May 02 01:32:30 PM PDT 24 May 02 01:32:34 PM PDT 24 952706791 ps
T559 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.474310545 May 02 01:32:59 PM PDT 24 May 02 01:33:02 PM PDT 24 195314461 ps
T560 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.564016721 May 02 01:31:24 PM PDT 24 May 02 01:31:26 PM PDT 24 88946872 ps
T561 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3767300865 May 02 01:31:32 PM PDT 24 May 02 01:31:35 PM PDT 24 322916139 ps
T562 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3078130378 May 02 01:32:54 PM PDT 24 May 02 01:32:58 PM PDT 24 520951974 ps
T563 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.448025578 May 02 01:32:20 PM PDT 24 May 02 01:32:22 PM PDT 24 267112214 ps
T564 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2640483415 May 02 01:32:13 PM PDT 24 May 02 01:32:16 PM PDT 24 367235268 ps
T565 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2048680153 May 02 01:32:50 PM PDT 24 May 02 01:32:52 PM PDT 24 183404434 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2295308943 May 02 01:32:31 PM PDT 24 May 02 01:32:33 PM PDT 24 188942090 ps
T567 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2040555629 May 02 01:32:45 PM PDT 24 May 02 01:32:46 PM PDT 24 63158091 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.92293989 May 02 01:32:13 PM PDT 24 May 02 01:32:15 PM PDT 24 102899746 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.429771232 May 02 01:32:05 PM PDT 24 May 02 01:32:18 PM PDT 24 2278373998 ps
T128 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2628278492 May 02 01:32:52 PM PDT 24 May 02 01:32:55 PM PDT 24 997793278 ps
T85 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.292047386 May 02 01:32:44 PM PDT 24 May 02 01:32:47 PM PDT 24 795323849 ps
T570 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2534644187 May 02 01:32:34 PM PDT 24 May 02 01:32:36 PM PDT 24 74942802 ps
T571 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3030865881 May 02 01:31:49 PM PDT 24 May 02 01:31:50 PM PDT 24 102703100 ps
T572 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2412477109 May 02 01:32:52 PM PDT 24 May 02 01:32:54 PM PDT 24 125865687 ps
T573 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3049850263 May 02 01:32:59 PM PDT 24 May 02 01:33:01 PM PDT 24 78451232 ps
T574 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2665967522 May 02 01:31:22 PM PDT 24 May 02 01:31:25 PM PDT 24 484359356 ps
T127 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1089816915 May 02 01:32:49 PM PDT 24 May 02 01:32:52 PM PDT 24 416627014 ps
T575 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3669076925 May 02 01:32:52 PM PDT 24 May 02 01:32:54 PM PDT 24 124578854 ps
T576 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3385032356 May 02 01:32:55 PM PDT 24 May 02 01:32:57 PM PDT 24 170487602 ps
T577 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2492248262 May 02 01:31:23 PM PDT 24 May 02 01:31:24 PM PDT 24 88325647 ps
T578 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.70807892 May 02 01:32:35 PM PDT 24 May 02 01:32:37 PM PDT 24 80361721 ps
T579 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.331922339 May 02 01:32:22 PM PDT 24 May 02 01:32:24 PM PDT 24 115407166 ps
T580 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.33117849 May 02 01:32:36 PM PDT 24 May 02 01:32:38 PM PDT 24 65150876 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2912555732 May 02 01:32:30 PM PDT 24 May 02 01:32:33 PM PDT 24 175244727 ps
T582 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1704645262 May 02 01:32:21 PM PDT 24 May 02 01:32:24 PM PDT 24 298320156 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.598643369 May 02 01:31:54 PM PDT 24 May 02 01:31:56 PM PDT 24 132526695 ps
T584 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2067451072 May 02 01:32:21 PM PDT 24 May 02 01:32:23 PM PDT 24 213165580 ps
T585 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3288359545 May 02 01:31:47 PM PDT 24 May 02 01:31:48 PM PDT 24 77941193 ps
T586 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2791523373 May 02 01:31:55 PM PDT 24 May 02 01:31:57 PM PDT 24 174162962 ps
T587 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2093794097 May 02 01:32:51 PM PDT 24 May 02 01:32:55 PM PDT 24 398281795 ps
T588 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3229768781 May 02 01:32:55 PM PDT 24 May 02 01:32:57 PM PDT 24 127039461 ps
T589 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.587237253 May 02 01:32:40 PM PDT 24 May 02 01:32:41 PM PDT 24 127119225 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2281217756 May 02 01:32:13 PM PDT 24 May 02 01:32:15 PM PDT 24 153397150 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.998175303 May 02 01:32:05 PM PDT 24 May 02 01:32:07 PM PDT 24 167190614 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1956021276 May 02 01:31:55 PM PDT 24 May 02 01:32:06 PM PDT 24 2296100346 ps
T593 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.456032467 May 02 01:32:44 PM PDT 24 May 02 01:32:49 PM PDT 24 508454085 ps
T594 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3824735842 May 02 01:32:51 PM PDT 24 May 02 01:32:53 PM PDT 24 467537231 ps
T595 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1085193433 May 02 01:32:52 PM PDT 24 May 02 01:32:55 PM PDT 24 490496568 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3970453922 May 02 01:32:04 PM PDT 24 May 02 01:32:05 PM PDT 24 79650396 ps
T597 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2570038556 May 02 01:31:31 PM PDT 24 May 02 01:31:33 PM PDT 24 155286391 ps
T598 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3030652587 May 02 01:31:47 PM PDT 24 May 02 01:31:55 PM PDT 24 1538214446 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1297414972 May 02 01:31:40 PM PDT 24 May 02 01:31:45 PM PDT 24 494576499 ps
T600 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4212154899 May 02 01:32:30 PM PDT 24 May 02 01:32:32 PM PDT 24 137233702 ps
T601 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1440574579 May 02 01:32:12 PM PDT 24 May 02 01:32:16 PM PDT 24 172984631 ps
T602 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4010581551 May 02 01:33:00 PM PDT 24 May 02 01:33:03 PM PDT 24 417163631 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1458744631 May 02 01:32:13 PM PDT 24 May 02 01:32:15 PM PDT 24 79862678 ps
T604 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2937893222 May 02 01:32:29 PM PDT 24 May 02 01:32:31 PM PDT 24 67399263 ps
T605 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2254260055 May 02 01:32:52 PM PDT 24 May 02 01:32:54 PM PDT 24 62064479 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3329947844 May 02 01:32:51 PM PDT 24 May 02 01:32:53 PM PDT 24 206288487 ps
T607 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3509083033 May 02 01:32:13 PM PDT 24 May 02 01:32:15 PM PDT 24 116071342 ps
T608 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.585218572 May 02 01:32:52 PM PDT 24 May 02 01:32:54 PM PDT 24 75904420 ps
T609 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2996827320 May 02 01:33:01 PM PDT 24 May 02 01:33:04 PM PDT 24 129612716 ps
T129 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1904892286 May 02 01:32:05 PM PDT 24 May 02 01:32:09 PM PDT 24 923706711 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.533896967 May 02 01:31:55 PM PDT 24 May 02 01:31:58 PM PDT 24 259167857 ps
T611 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2694282101 May 02 01:31:55 PM PDT 24 May 02 01:31:57 PM PDT 24 74276334 ps
T612 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.681594021 May 02 01:32:55 PM PDT 24 May 02 01:32:57 PM PDT 24 109900486 ps
T613 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.140906516 May 02 01:31:32 PM PDT 24 May 02 01:31:34 PM PDT 24 100914562 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1237206692 May 02 01:32:03 PM PDT 24 May 02 01:32:04 PM PDT 24 139235244 ps
T615 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3349488894 May 02 01:32:44 PM PDT 24 May 02 01:32:46 PM PDT 24 115913185 ps
T87 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3420842035 May 02 01:32:36 PM PDT 24 May 02 01:32:40 PM PDT 24 807495901 ps
T616 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.740965192 May 02 01:32:37 PM PDT 24 May 02 01:32:41 PM PDT 24 499415774 ps
T617 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2116480111 May 02 01:33:00 PM PDT 24 May 02 01:33:03 PM PDT 24 481073118 ps
T618 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.554953878 May 02 01:32:58 PM PDT 24 May 02 01:33:00 PM PDT 24 100397646 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4274008620 May 02 01:31:45 PM PDT 24 May 02 01:31:46 PM PDT 24 102614142 ps
T620 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.578409544 May 02 01:32:45 PM PDT 24 May 02 01:32:47 PM PDT 24 89155747 ps

Test location /workspace/coverage/default/15.rstmgr_reset.2176550229
Short name T3
Test name
Test status
Simulation time 869121823 ps
CPU time 4.52 seconds
Started May 02 01:34:14 PM PDT 24
Finished May 02 01:34:20 PM PDT 24
Peak memory 201068 kb
Host smart-35ff811a-23ca-4f53-9bf5-b9563a00e72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176550229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2176550229
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1853909019
Short name T26
Test name
Test status
Simulation time 477821717 ps
CPU time 2.77 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:02 PM PDT 24
Peak memory 200864 kb
Host smart-122d6ffd-5ec7-4f65-9071-a861b49d5255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853909019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1853909019
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3451192022
Short name T8
Test name
Test status
Simulation time 1224500912 ps
CPU time 5.58 seconds
Started May 02 01:34:06 PM PDT 24
Finished May 02 01:34:13 PM PDT 24
Peak memory 218556 kb
Host smart-90bee395-6a85-4b33-962c-801bade62437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451192022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3451192022
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2471335190
Short name T60
Test name
Test status
Simulation time 200833268 ps
CPU time 2.05 seconds
Started May 02 01:32:59 PM PDT 24
Finished May 02 01:33:03 PM PDT 24
Peak memory 209364 kb
Host smart-0f5fac2a-e704-4a65-a864-a987c4ca3b7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471335190 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2471335190
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1724499231
Short name T64
Test name
Test status
Simulation time 17048785030 ps
CPU time 23.87 seconds
Started May 02 01:33:13 PM PDT 24
Finished May 02 01:33:38 PM PDT 24
Peak memory 218876 kb
Host smart-208e6306-19eb-4b4b-9e1f-df6b6fc2cbfb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724499231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1724499231
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1745662130
Short name T100
Test name
Test status
Simulation time 14157897825 ps
CPU time 46.32 seconds
Started May 02 01:35:34 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 201224 kb
Host smart-5a79200a-8995-402a-96be-15c9d49e8ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745662130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1745662130
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4276533908
Short name T67
Test name
Test status
Simulation time 875662730 ps
CPU time 3.08 seconds
Started May 02 01:32:29 PM PDT 24
Finished May 02 01:32:33 PM PDT 24
Peak memory 201156 kb
Host smart-24cda684-dd72-47d6-9e82-282fb00b1cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276533908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.4276533908
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2815308765
Short name T28
Test name
Test status
Simulation time 73871573 ps
CPU time 0.85 seconds
Started May 02 01:34:00 PM PDT 24
Finished May 02 01:34:02 PM PDT 24
Peak memory 200732 kb
Host smart-7e7b0264-9c78-47d9-b7cd-ebc251e96974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815308765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2815308765
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3778302959
Short name T147
Test name
Test status
Simulation time 103290917 ps
CPU time 1.04 seconds
Started May 02 01:33:01 PM PDT 24
Finished May 02 01:33:03 PM PDT 24
Peak memory 200800 kb
Host smart-cdcdc404-b24e-49c3-af34-ac456cddffbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778302959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3778302959
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3204885615
Short name T63
Test name
Test status
Simulation time 659281301 ps
CPU time 3.92 seconds
Started May 02 01:32:37 PM PDT 24
Finished May 02 01:32:42 PM PDT 24
Peak memory 209300 kb
Host smart-42f83380-94dc-4912-9eea-86dd8eb4df90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204885615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3204885615
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3880018429
Short name T30
Test name
Test status
Simulation time 1234671721 ps
CPU time 5.43 seconds
Started May 02 01:33:05 PM PDT 24
Finished May 02 01:33:11 PM PDT 24
Peak memory 217856 kb
Host smart-20d74ef0-b05e-44db-bc3e-caf1d73b931e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880018429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3880018429
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3159003961
Short name T25
Test name
Test status
Simulation time 272441830 ps
CPU time 1.4 seconds
Started May 02 01:35:47 PM PDT 24
Finished May 02 01:35:49 PM PDT 24
Peak memory 200852 kb
Host smart-1b6d9436-6841-4e69-94de-b0d591ac93cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159003961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3159003961
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2900271870
Short name T126
Test name
Test status
Simulation time 464822774 ps
CPU time 1.82 seconds
Started May 02 01:32:35 PM PDT 24
Finished May 02 01:32:38 PM PDT 24
Peak memory 201140 kb
Host smart-6a96ccca-ad0c-493e-a562-3eeceea745ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900271870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2900271870
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2502071534
Short name T43
Test name
Test status
Simulation time 1875500564 ps
CPU time 6.85 seconds
Started May 02 01:35:47 PM PDT 24
Finished May 02 01:35:55 PM PDT 24
Peak memory 218520 kb
Host smart-ca349df8-bb1b-476d-a70a-9596f8d59065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502071534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2502071534
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1776293553
Short name T89
Test name
Test status
Simulation time 885163723 ps
CPU time 2.92 seconds
Started May 02 01:32:22 PM PDT 24
Finished May 02 01:32:26 PM PDT 24
Peak memory 201044 kb
Host smart-f478665d-d90f-488c-8c6a-860178e9b371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776293553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1776293553
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.456179748
Short name T112
Test name
Test status
Simulation time 128455661 ps
CPU time 1.2 seconds
Started May 02 01:32:40 PM PDT 24
Finished May 02 01:32:43 PM PDT 24
Peak memory 201112 kb
Host smart-3554adff-1305-4c5d-b771-1f3776029b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456179748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.456179748
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4224093102
Short name T14
Test name
Test status
Simulation time 212699146 ps
CPU time 0.9 seconds
Started May 02 01:33:01 PM PDT 24
Finished May 02 01:33:03 PM PDT 24
Peak memory 200692 kb
Host smart-c3c91445-92f0-4b8e-afd8-141524286155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224093102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4224093102
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1113986485
Short name T159
Test name
Test status
Simulation time 133329949 ps
CPU time 1.55 seconds
Started May 02 01:34:48 PM PDT 24
Finished May 02 01:34:51 PM PDT 24
Peak memory 200852 kb
Host smart-58daa96f-e1f6-44bd-81ca-3211cc0af5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113986485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1113986485
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2570038556
Short name T597
Test name
Test status
Simulation time 155286391 ps
CPU time 1.83 seconds
Started May 02 01:31:31 PM PDT 24
Finished May 02 01:31:33 PM PDT 24
Peak memory 209268 kb
Host smart-71b66a48-8489-4f66-8839-ff609194a388
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570038556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
570038556
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.742241470
Short name T59
Test name
Test status
Simulation time 271994248 ps
CPU time 3.23 seconds
Started May 02 01:31:33 PM PDT 24
Finished May 02 01:31:37 PM PDT 24
Peak memory 201092 kb
Host smart-13992b29-7e67-45c1-9042-12bcb2acfbdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742241470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.742241470
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.564016721
Short name T560
Test name
Test status
Simulation time 88946872 ps
CPU time 0.81 seconds
Started May 02 01:31:24 PM PDT 24
Finished May 02 01:31:26 PM PDT 24
Peak memory 200752 kb
Host smart-205577af-927b-489e-8ab9-04208224213b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564016721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.564016721
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2195757740
Short name T555
Test name
Test status
Simulation time 118194267 ps
CPU time 1.21 seconds
Started May 02 01:31:34 PM PDT 24
Finished May 02 01:31:36 PM PDT 24
Peak memory 209212 kb
Host smart-8da77cad-48f1-4cab-aec7-7bcca8ed877d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195757740 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2195757740
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2492248262
Short name T577
Test name
Test status
Simulation time 88325647 ps
CPU time 0.8 seconds
Started May 02 01:31:23 PM PDT 24
Finished May 02 01:31:24 PM PDT 24
Peak memory 200800 kb
Host smart-c27ae088-6b6d-4b2f-8b84-15c65c784cdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492248262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2492248262
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.140906516
Short name T613
Test name
Test status
Simulation time 100914562 ps
CPU time 1.18 seconds
Started May 02 01:31:32 PM PDT 24
Finished May 02 01:31:34 PM PDT 24
Peak memory 201032 kb
Host smart-746d5b1d-300a-4bb9-81ba-08ad8d2edbf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140906516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.140906516
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.4165078778
Short name T61
Test name
Test status
Simulation time 200159761 ps
CPU time 2.76 seconds
Started May 02 01:31:28 PM PDT 24
Finished May 02 01:31:31 PM PDT 24
Peak memory 217528 kb
Host smart-97020b13-ec1c-48df-a6f8-24730bf42456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165078778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.4165078778
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2665967522
Short name T574
Test name
Test status
Simulation time 484359356 ps
CPU time 2.04 seconds
Started May 02 01:31:22 PM PDT 24
Finished May 02 01:31:25 PM PDT 24
Peak memory 201180 kb
Host smart-8eb6262e-f523-4682-9df5-de761ca715f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665967522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2665967522
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.655367804
Short name T541
Test name
Test status
Simulation time 146774964 ps
CPU time 1.86 seconds
Started May 02 01:32:02 PM PDT 24
Finished May 02 01:32:04 PM PDT 24
Peak memory 201056 kb
Host smart-a4046a65-6ae2-423d-82f3-f94d4f220984
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655367804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.655367804
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1017773857
Short name T556
Test name
Test status
Simulation time 794958057 ps
CPU time 4.28 seconds
Started May 02 01:31:40 PM PDT 24
Finished May 02 01:31:47 PM PDT 24
Peak memory 201032 kb
Host smart-2c1a25d9-2c6c-4993-a143-d18816e1626c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017773857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
017773857
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4274008620
Short name T619
Test name
Test status
Simulation time 102614142 ps
CPU time 0.89 seconds
Started May 02 01:31:45 PM PDT 24
Finished May 02 01:31:46 PM PDT 24
Peak memory 200868 kb
Host smart-8a6f5024-610a-4729-bf08-7524133681be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274008620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
274008620
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4259322052
Short name T58
Test name
Test status
Simulation time 179954499 ps
CPU time 1.14 seconds
Started May 02 01:31:47 PM PDT 24
Finished May 02 01:31:49 PM PDT 24
Peak memory 200968 kb
Host smart-4925ad1b-68fa-4841-b229-46ffa88e3fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259322052 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.4259322052
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1028158812
Short name T547
Test name
Test status
Simulation time 87816765 ps
CPU time 0.86 seconds
Started May 02 01:31:42 PM PDT 24
Finished May 02 01:31:44 PM PDT 24
Peak memory 200912 kb
Host smart-ba21a738-6203-4211-ad94-97f9a3141de8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028158812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1028158812
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1153590193
Short name T554
Test name
Test status
Simulation time 97075915 ps
CPU time 1.18 seconds
Started May 02 01:31:44 PM PDT 24
Finished May 02 01:31:46 PM PDT 24
Peak memory 201112 kb
Host smart-2dd82654-f0a9-48e2-9f9a-7dedb72380d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153590193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1153590193
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3767300865
Short name T561
Test name
Test status
Simulation time 322916139 ps
CPU time 2.36 seconds
Started May 02 01:31:32 PM PDT 24
Finished May 02 01:31:35 PM PDT 24
Peak memory 201132 kb
Host smart-59b2c067-9d0b-45eb-b499-137654ed65a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767300865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3767300865
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1297414972
Short name T599
Test name
Test status
Simulation time 494576499 ps
CPU time 1.9 seconds
Started May 02 01:31:40 PM PDT 24
Finished May 02 01:31:45 PM PDT 24
Peak memory 201060 kb
Host smart-7735e319-79ad-4dbb-b1ab-8b212b7ad8d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297414972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1297414972
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3519008315
Short name T544
Test name
Test status
Simulation time 172609129 ps
CPU time 1.13 seconds
Started May 02 01:32:39 PM PDT 24
Finished May 02 01:32:41 PM PDT 24
Peak memory 200892 kb
Host smart-ff9af994-39a3-458a-80e0-9af07870b326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519008315 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3519008315
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2534644187
Short name T570
Test name
Test status
Simulation time 74942802 ps
CPU time 0.81 seconds
Started May 02 01:32:34 PM PDT 24
Finished May 02 01:32:36 PM PDT 24
Peak memory 200888 kb
Host smart-61547533-b27a-4308-8698-142221497bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534644187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2534644187
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.332044310
Short name T84
Test name
Test status
Simulation time 126280486 ps
CPU time 1.72 seconds
Started May 02 01:32:30 PM PDT 24
Finished May 02 01:32:33 PM PDT 24
Peak memory 209212 kb
Host smart-909b2f8d-ca89-4678-97a0-e716129dbede
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332044310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.332044310
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.607710241
Short name T558
Test name
Test status
Simulation time 952706791 ps
CPU time 3.19 seconds
Started May 02 01:32:30 PM PDT 24
Finished May 02 01:32:34 PM PDT 24
Peak memory 201108 kb
Host smart-9d337ffe-5aaa-47fd-a777-5191a20cbd40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607710241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.607710241
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.587237253
Short name T589
Test name
Test status
Simulation time 127119225 ps
CPU time 1.02 seconds
Started May 02 01:32:40 PM PDT 24
Finished May 02 01:32:41 PM PDT 24
Peak memory 200928 kb
Host smart-c8f1e953-4375-4bc8-a1fd-3e3eae6e48c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587237253 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.587237253
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.945158736
Short name T115
Test name
Test status
Simulation time 55413415 ps
CPU time 0.72 seconds
Started May 02 01:32:36 PM PDT 24
Finished May 02 01:32:38 PM PDT 24
Peak memory 200808 kb
Host smart-bc7b9216-6e51-4ae5-9fc9-1a06cae35d91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945158736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.945158736
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.70807892
Short name T578
Test name
Test status
Simulation time 80361721 ps
CPU time 0.91 seconds
Started May 02 01:32:35 PM PDT 24
Finished May 02 01:32:37 PM PDT 24
Peak memory 200856 kb
Host smart-07a7425f-ee90-4a4e-b0fe-a89dde164112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70807892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sam
e_csr_outstanding.70807892
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.740965192
Short name T616
Test name
Test status
Simulation time 499415774 ps
CPU time 3.08 seconds
Started May 02 01:32:37 PM PDT 24
Finished May 02 01:32:41 PM PDT 24
Peak memory 209316 kb
Host smart-4735aa18-f596-4d64-84dd-f57dc3f531e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740965192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.740965192
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3358540890
Short name T548
Test name
Test status
Simulation time 127817557 ps
CPU time 0.95 seconds
Started May 02 01:32:35 PM PDT 24
Finished May 02 01:32:37 PM PDT 24
Peak memory 201012 kb
Host smart-184faac0-3fbc-4e92-b69f-63edd782cbe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358540890 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3358540890
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.33117849
Short name T580
Test name
Test status
Simulation time 65150876 ps
CPU time 0.79 seconds
Started May 02 01:32:36 PM PDT 24
Finished May 02 01:32:38 PM PDT 24
Peak memory 200876 kb
Host smart-f01d2e72-d3b6-4c46-96e9-f61850520fb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33117849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.33117849
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.970427428
Short name T549
Test name
Test status
Simulation time 104995295 ps
CPU time 1.25 seconds
Started May 02 01:32:40 PM PDT 24
Finished May 02 01:32:43 PM PDT 24
Peak memory 201068 kb
Host smart-a4f0eebb-7775-4c21-967e-c3731dc90200
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970427428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.970427428
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3420842035
Short name T87
Test name
Test status
Simulation time 807495901 ps
CPU time 2.71 seconds
Started May 02 01:32:36 PM PDT 24
Finished May 02 01:32:40 PM PDT 24
Peak memory 201124 kb
Host smart-1e94c041-5a74-4671-927e-5e971d58da38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420842035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3420842035
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3349488894
Short name T615
Test name
Test status
Simulation time 115913185 ps
CPU time 1.09 seconds
Started May 02 01:32:44 PM PDT 24
Finished May 02 01:32:46 PM PDT 24
Peak memory 209176 kb
Host smart-22dc77b6-f32d-459f-8327-5d412d3ded09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349488894 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3349488894
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2040555629
Short name T567
Test name
Test status
Simulation time 63158091 ps
CPU time 0.76 seconds
Started May 02 01:32:45 PM PDT 24
Finished May 02 01:32:46 PM PDT 24
Peak memory 200808 kb
Host smart-72024b37-ff7f-4ac5-91ee-f4fcdb386ce6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040555629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2040555629
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.578409544
Short name T620
Test name
Test status
Simulation time 89155747 ps
CPU time 1.02 seconds
Started May 02 01:32:45 PM PDT 24
Finished May 02 01:32:47 PM PDT 24
Peak memory 200952 kb
Host smart-726139c3-0cba-48f5-a8f2-e333f578722b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578409544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.578409544
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1809119183
Short name T104
Test name
Test status
Simulation time 170070106 ps
CPU time 2.46 seconds
Started May 02 01:32:45 PM PDT 24
Finished May 02 01:32:48 PM PDT 24
Peak memory 209336 kb
Host smart-825246e3-5553-47f2-b3ab-04fcb835e1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809119183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1809119183
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.292047386
Short name T85
Test name
Test status
Simulation time 795323849 ps
CPU time 2.56 seconds
Started May 02 01:32:44 PM PDT 24
Finished May 02 01:32:47 PM PDT 24
Peak memory 201104 kb
Host smart-632afbc4-0a42-49d2-952f-eaefbfd1056a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292047386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.292047386
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2048680153
Short name T565
Test name
Test status
Simulation time 183404434 ps
CPU time 1.25 seconds
Started May 02 01:32:50 PM PDT 24
Finished May 02 01:32:52 PM PDT 24
Peak memory 217276 kb
Host smart-50cb66b1-1717-4d0d-8068-b80958116a1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048680153 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2048680153
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2547607506
Short name T111
Test name
Test status
Simulation time 54830846 ps
CPU time 0.73 seconds
Started May 02 01:32:44 PM PDT 24
Finished May 02 01:32:45 PM PDT 24
Peak memory 200804 kb
Host smart-7ec081f0-e075-4015-a7ad-6242e8689b83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547607506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2547607506
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.425045083
Short name T81
Test name
Test status
Simulation time 187775242 ps
CPU time 1.46 seconds
Started May 02 01:32:49 PM PDT 24
Finished May 02 01:32:52 PM PDT 24
Peak memory 201016 kb
Host smart-11ffddc2-04f6-4883-97f4-2273514f2432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425045083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.425045083
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.456032467
Short name T593
Test name
Test status
Simulation time 508454085 ps
CPU time 3.7 seconds
Started May 02 01:32:44 PM PDT 24
Finished May 02 01:32:49 PM PDT 24
Peak memory 209316 kb
Host smart-903fe22d-1813-495a-ae80-f82c15f8a9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456032467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.456032467
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1089816915
Short name T127
Test name
Test status
Simulation time 416627014 ps
CPU time 1.93 seconds
Started May 02 01:32:49 PM PDT 24
Finished May 02 01:32:52 PM PDT 24
Peak memory 201084 kb
Host smart-3535efe2-8306-42c6-85fc-3d47dc545655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089816915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1089816915
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3385032356
Short name T576
Test name
Test status
Simulation time 170487602 ps
CPU time 1.64 seconds
Started May 02 01:32:55 PM PDT 24
Finished May 02 01:32:57 PM PDT 24
Peak memory 209420 kb
Host smart-e4deb95d-96f7-42b6-ab29-ac94a0693026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385032356 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3385032356
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2254260055
Short name T605
Test name
Test status
Simulation time 62064479 ps
CPU time 0.74 seconds
Started May 02 01:32:52 PM PDT 24
Finished May 02 01:32:54 PM PDT 24
Peak memory 200732 kb
Host smart-736c313a-1cfc-4191-99c8-862907fdacfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254260055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2254260055
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3558570063
Short name T57
Test name
Test status
Simulation time 234287595 ps
CPU time 1.63 seconds
Started May 02 01:32:53 PM PDT 24
Finished May 02 01:32:56 PM PDT 24
Peak memory 201108 kb
Host smart-878ec94b-0816-4754-82d3-8de1b466746f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558570063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3558570063
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4149629070
Short name T545
Test name
Test status
Simulation time 195123131 ps
CPU time 1.53 seconds
Started May 02 01:32:43 PM PDT 24
Finished May 02 01:32:45 PM PDT 24
Peak memory 211576 kb
Host smart-dbd633ba-448f-42be-9e26-277dc4aa87ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149629070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4149629070
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3824735842
Short name T594
Test name
Test status
Simulation time 467537231 ps
CPU time 1.76 seconds
Started May 02 01:32:51 PM PDT 24
Finished May 02 01:32:53 PM PDT 24
Peak memory 201148 kb
Host smart-049ff6be-6093-4bb8-88d0-b8741cc18366
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824735842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3824735842
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3329947844
Short name T606
Test name
Test status
Simulation time 206288487 ps
CPU time 1.21 seconds
Started May 02 01:32:51 PM PDT 24
Finished May 02 01:32:53 PM PDT 24
Peak memory 209144 kb
Host smart-a6597d31-7972-4203-aace-dbe4963a8733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329947844 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3329947844
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.585218572
Short name T608
Test name
Test status
Simulation time 75904420 ps
CPU time 0.78 seconds
Started May 02 01:32:52 PM PDT 24
Finished May 02 01:32:54 PM PDT 24
Peak memory 200864 kb
Host smart-2f183720-73fc-41c3-9ad7-223ae15ef13e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585218572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.585218572
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3669076925
Short name T575
Test name
Test status
Simulation time 124578854 ps
CPU time 1.03 seconds
Started May 02 01:32:52 PM PDT 24
Finished May 02 01:32:54 PM PDT 24
Peak memory 200936 kb
Host smart-793d17e7-a30a-4b13-ac85-f28ef6c3d41d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669076925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3669076925
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2412477109
Short name T572
Test name
Test status
Simulation time 125865687 ps
CPU time 1.74 seconds
Started May 02 01:32:52 PM PDT 24
Finished May 02 01:32:54 PM PDT 24
Peak memory 209328 kb
Host smart-971b2711-2a26-418e-a0d5-2a9187eaf73f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412477109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2412477109
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2628278492
Short name T128
Test name
Test status
Simulation time 997793278 ps
CPU time 3.05 seconds
Started May 02 01:32:52 PM PDT 24
Finished May 02 01:32:55 PM PDT 24
Peak memory 201180 kb
Host smart-a9b04171-d15a-40ba-80a3-7c4945c6f66d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628278492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2628278492
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3229768781
Short name T588
Test name
Test status
Simulation time 127039461 ps
CPU time 1.29 seconds
Started May 02 01:32:55 PM PDT 24
Finished May 02 01:32:57 PM PDT 24
Peak memory 209288 kb
Host smart-b163918b-0226-4e48-9e30-fff7a9cf4186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229768781 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3229768781
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2813330887
Short name T110
Test name
Test status
Simulation time 80659070 ps
CPU time 0.85 seconds
Started May 02 01:32:52 PM PDT 24
Finished May 02 01:32:54 PM PDT 24
Peak memory 200880 kb
Host smart-9e69d08b-834b-48d7-ae69-d663cb4589c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813330887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2813330887
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.681594021
Short name T612
Test name
Test status
Simulation time 109900486 ps
CPU time 1.22 seconds
Started May 02 01:32:55 PM PDT 24
Finished May 02 01:32:57 PM PDT 24
Peak memory 217468 kb
Host smart-2a2bba75-14ce-4519-88c8-44cfdbb5677a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681594021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.681594021
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2093794097
Short name T587
Test name
Test status
Simulation time 398281795 ps
CPU time 2.97 seconds
Started May 02 01:32:51 PM PDT 24
Finished May 02 01:32:55 PM PDT 24
Peak memory 209264 kb
Host smart-3f8bdd5d-234c-432c-8b39-c9a6bbbfd2a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093794097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2093794097
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1085193433
Short name T595
Test name
Test status
Simulation time 490496568 ps
CPU time 1.84 seconds
Started May 02 01:32:52 PM PDT 24
Finished May 02 01:32:55 PM PDT 24
Peak memory 201060 kb
Host smart-54ae4814-0ce7-4741-ab8a-beb594cf803e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085193433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1085193433
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.474310545
Short name T559
Test name
Test status
Simulation time 195314461 ps
CPU time 1.39 seconds
Started May 02 01:32:59 PM PDT 24
Finished May 02 01:33:02 PM PDT 24
Peak memory 209128 kb
Host smart-193c06ad-ddee-4936-b9c2-9cd569c303e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474310545 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.474310545
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.66865051
Short name T543
Test name
Test status
Simulation time 80243984 ps
CPU time 0.83 seconds
Started May 02 01:33:00 PM PDT 24
Finished May 02 01:33:02 PM PDT 24
Peak memory 200852 kb
Host smart-42ef2b5c-927e-4df6-947c-3fd010c0d89c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66865051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.66865051
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2996827320
Short name T609
Test name
Test status
Simulation time 129612716 ps
CPU time 1.13 seconds
Started May 02 01:33:01 PM PDT 24
Finished May 02 01:33:04 PM PDT 24
Peak memory 200872 kb
Host smart-3d222174-f9af-4513-a3f1-016e1b3c2709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996827320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2996827320
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3078130378
Short name T562
Test name
Test status
Simulation time 520951974 ps
CPU time 3.34 seconds
Started May 02 01:32:54 PM PDT 24
Finished May 02 01:32:58 PM PDT 24
Peak memory 209228 kb
Host smart-d0f71739-bc5b-48bf-8504-9f9058de5711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078130378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3078130378
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2116480111
Short name T617
Test name
Test status
Simulation time 481073118 ps
CPU time 1.84 seconds
Started May 02 01:33:00 PM PDT 24
Finished May 02 01:33:03 PM PDT 24
Peak memory 201136 kb
Host smart-ca5e5dac-0097-4f33-9572-d98ed5fb680f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116480111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2116480111
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2651568403
Short name T553
Test name
Test status
Simulation time 59452341 ps
CPU time 0.8 seconds
Started May 02 01:33:00 PM PDT 24
Finished May 02 01:33:02 PM PDT 24
Peak memory 200864 kb
Host smart-11e303ee-0dcf-4072-8e4a-d3e799c67e2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651568403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2651568403
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3049850263
Short name T573
Test name
Test status
Simulation time 78451232 ps
CPU time 0.95 seconds
Started May 02 01:32:59 PM PDT 24
Finished May 02 01:33:01 PM PDT 24
Peak memory 200968 kb
Host smart-3585daf1-b13c-4790-80e9-c04813dd5fdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049850263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3049850263
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.554953878
Short name T618
Test name
Test status
Simulation time 100397646 ps
CPU time 1.24 seconds
Started May 02 01:32:58 PM PDT 24
Finished May 02 01:33:00 PM PDT 24
Peak memory 201112 kb
Host smart-078e1847-9fd8-437a-9edf-4b6915225518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554953878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.554953878
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4010581551
Short name T602
Test name
Test status
Simulation time 417163631 ps
CPU time 1.89 seconds
Started May 02 01:33:00 PM PDT 24
Finished May 02 01:33:03 PM PDT 24
Peak memory 201060 kb
Host smart-2dc48b13-5731-4e68-98fa-a73396335b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010581551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.4010581551
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.413215025
Short name T542
Test name
Test status
Simulation time 104196493 ps
CPU time 1.22 seconds
Started May 02 01:31:48 PM PDT 24
Finished May 02 01:31:50 PM PDT 24
Peak memory 201012 kb
Host smart-628e73be-46e8-4fc1-927b-5f2f23b32767
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413215025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.413215025
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3030652587
Short name T598
Test name
Test status
Simulation time 1538214446 ps
CPU time 7.64 seconds
Started May 02 01:31:47 PM PDT 24
Finished May 02 01:31:55 PM PDT 24
Peak memory 200992 kb
Host smart-a8ec9bd9-e2b2-42bb-8e0a-c622342c0e86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030652587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
030652587
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3030865881
Short name T571
Test name
Test status
Simulation time 102703100 ps
CPU time 0.79 seconds
Started May 02 01:31:49 PM PDT 24
Finished May 02 01:31:50 PM PDT 24
Peak memory 200776 kb
Host smart-c9e611c2-6711-4a36-988a-b5d9087c2285
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030865881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
030865881
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2791523373
Short name T586
Test name
Test status
Simulation time 174162962 ps
CPU time 1.64 seconds
Started May 02 01:31:55 PM PDT 24
Finished May 02 01:31:57 PM PDT 24
Peak memory 209452 kb
Host smart-084bb77f-b0be-484b-a866-3049cf14cbb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791523373 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2791523373
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3288359545
Short name T585
Test name
Test status
Simulation time 77941193 ps
CPU time 0.81 seconds
Started May 02 01:31:47 PM PDT 24
Finished May 02 01:31:48 PM PDT 24
Peak memory 200832 kb
Host smart-8cf533be-1b05-4a88-a2c9-5bf415ad7ec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288359545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3288359545
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.598643369
Short name T583
Test name
Test status
Simulation time 132526695 ps
CPU time 1.07 seconds
Started May 02 01:31:54 PM PDT 24
Finished May 02 01:31:56 PM PDT 24
Peak memory 200924 kb
Host smart-184c5228-1dc6-4860-bb1d-d21cf1617ceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598643369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.598643369
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1105131333
Short name T62
Test name
Test status
Simulation time 421990905 ps
CPU time 3.21 seconds
Started May 02 01:31:49 PM PDT 24
Finished May 02 01:31:53 PM PDT 24
Peak memory 209308 kb
Host smart-13840d85-ce30-4914-ba79-3805e60c7fac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105131333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1105131333
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1143922292
Short name T79
Test name
Test status
Simulation time 463957174 ps
CPU time 1.85 seconds
Started May 02 01:31:48 PM PDT 24
Finished May 02 01:31:51 PM PDT 24
Peak memory 201100 kb
Host smart-869799c5-f2e0-43fc-b884-e901c8dd8389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143922292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1143922292
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.533896967
Short name T610
Test name
Test status
Simulation time 259167857 ps
CPU time 1.69 seconds
Started May 02 01:31:55 PM PDT 24
Finished May 02 01:31:58 PM PDT 24
Peak memory 201060 kb
Host smart-1d7e41ac-25ad-4c93-8dd1-20e8074fc07f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533896967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.533896967
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1956021276
Short name T592
Test name
Test status
Simulation time 2296100346 ps
CPU time 9.46 seconds
Started May 02 01:31:55 PM PDT 24
Finished May 02 01:32:06 PM PDT 24
Peak memory 201092 kb
Host smart-089f2101-d656-4960-9d7e-32df2bb85bf9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956021276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
956021276
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3081676964
Short name T557
Test name
Test status
Simulation time 97290559 ps
CPU time 0.8 seconds
Started May 02 01:31:56 PM PDT 24
Finished May 02 01:31:57 PM PDT 24
Peak memory 200776 kb
Host smart-f6038648-2f87-452e-b17d-0381707b04aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081676964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
081676964
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.998175303
Short name T591
Test name
Test status
Simulation time 167190614 ps
CPU time 1.65 seconds
Started May 02 01:32:05 PM PDT 24
Finished May 02 01:32:07 PM PDT 24
Peak memory 209388 kb
Host smart-6bde97fb-e495-4f52-a613-0d524fe9dd7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998175303 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.998175303
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2694282101
Short name T611
Test name
Test status
Simulation time 74276334 ps
CPU time 0.78 seconds
Started May 02 01:31:55 PM PDT 24
Finished May 02 01:31:57 PM PDT 24
Peak memory 200740 kb
Host smart-c624444c-ba13-49eb-85eb-c4acff7a1d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694282101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2694282101
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3970453922
Short name T596
Test name
Test status
Simulation time 79650396 ps
CPU time 0.94 seconds
Started May 02 01:32:04 PM PDT 24
Finished May 02 01:32:05 PM PDT 24
Peak memory 200956 kb
Host smart-9d30b65c-51d9-4596-a7a7-553a728700b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970453922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3970453922
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1252139178
Short name T83
Test name
Test status
Simulation time 320607199 ps
CPU time 2.4 seconds
Started May 02 01:31:57 PM PDT 24
Finished May 02 01:32:00 PM PDT 24
Peak memory 209328 kb
Host smart-2a9b6a1b-a680-4c97-adc9-b459a4622cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252139178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1252139178
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3478303790
Short name T124
Test name
Test status
Simulation time 882994431 ps
CPU time 2.97 seconds
Started May 02 01:31:56 PM PDT 24
Finished May 02 01:32:00 PM PDT 24
Peak memory 201180 kb
Host smart-fa506a14-d660-4b33-817e-b75139319706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478303790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3478303790
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2640483415
Short name T564
Test name
Test status
Simulation time 367235268 ps
CPU time 2.47 seconds
Started May 02 01:32:13 PM PDT 24
Finished May 02 01:32:16 PM PDT 24
Peak memory 201096 kb
Host smart-f00c32ba-10ad-48fd-8b10-c9440b3a437e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640483415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
640483415
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.429771232
Short name T569
Test name
Test status
Simulation time 2278373998 ps
CPU time 11.89 seconds
Started May 02 01:32:05 PM PDT 24
Finished May 02 01:32:18 PM PDT 24
Peak memory 201176 kb
Host smart-3764243a-6d01-48b1-8d83-c8ba65c9fbc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429771232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.429771232
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1237206692
Short name T614
Test name
Test status
Simulation time 139235244 ps
CPU time 0.94 seconds
Started May 02 01:32:03 PM PDT 24
Finished May 02 01:32:04 PM PDT 24
Peak memory 200792 kb
Host smart-63d5c4ef-97a1-45ae-bc39-4ad0b993ab18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237206692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
237206692
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.92293989
Short name T568
Test name
Test status
Simulation time 102899746 ps
CPU time 0.94 seconds
Started May 02 01:32:13 PM PDT 24
Finished May 02 01:32:15 PM PDT 24
Peak memory 200900 kb
Host smart-f4a08635-1381-4a6d-92c3-c1d9761dd6e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92293989 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.92293989
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.241525016
Short name T552
Test name
Test status
Simulation time 67492235 ps
CPU time 0.75 seconds
Started May 02 01:32:03 PM PDT 24
Finished May 02 01:32:05 PM PDT 24
Peak memory 200868 kb
Host smart-a876805e-8eef-4a1b-b65d-76d54c81c2b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241525016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.241525016
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2281217756
Short name T590
Test name
Test status
Simulation time 153397150 ps
CPU time 1.1 seconds
Started May 02 01:32:13 PM PDT 24
Finished May 02 01:32:15 PM PDT 24
Peak memory 200868 kb
Host smart-2ac42b43-34ca-40eb-8d4d-fcd25429ee8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281217756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2281217756
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2075271610
Short name T90
Test name
Test status
Simulation time 172370433 ps
CPU time 2.47 seconds
Started May 02 01:32:05 PM PDT 24
Finished May 02 01:32:09 PM PDT 24
Peak memory 212820 kb
Host smart-786f8d3e-c9ed-4c9e-befe-c309837d0c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075271610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2075271610
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1904892286
Short name T129
Test name
Test status
Simulation time 923706711 ps
CPU time 2.92 seconds
Started May 02 01:32:05 PM PDT 24
Finished May 02 01:32:09 PM PDT 24
Peak memory 201188 kb
Host smart-cb6e2a91-ef7b-419f-8f1f-809f41c3b1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904892286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1904892286
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3509083033
Short name T607
Test name
Test status
Simulation time 116071342 ps
CPU time 1.03 seconds
Started May 02 01:32:13 PM PDT 24
Finished May 02 01:32:15 PM PDT 24
Peak memory 201028 kb
Host smart-187dbfbd-1d29-44fd-80e3-9d21c1a47bf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509083033 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3509083033
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3283403884
Short name T80
Test name
Test status
Simulation time 62285615 ps
CPU time 0.79 seconds
Started May 02 01:32:12 PM PDT 24
Finished May 02 01:32:14 PM PDT 24
Peak memory 200880 kb
Host smart-580cf857-578a-499f-a938-b2fe8f8e1621
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283403884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3283403884
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1458744631
Short name T603
Test name
Test status
Simulation time 79862678 ps
CPU time 0.92 seconds
Started May 02 01:32:13 PM PDT 24
Finished May 02 01:32:15 PM PDT 24
Peak memory 200936 kb
Host smart-fb96a88c-4bc7-4282-bdcf-dfe79188ab72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458744631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1458744631
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1440574579
Short name T601
Test name
Test status
Simulation time 172984631 ps
CPU time 2.34 seconds
Started May 02 01:32:12 PM PDT 24
Finished May 02 01:32:16 PM PDT 24
Peak memory 209308 kb
Host smart-b704e507-09d6-4e80-b654-9646ab027078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440574579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1440574579
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2506757476
Short name T78
Test name
Test status
Simulation time 646504016 ps
CPU time 1.99 seconds
Started May 02 01:32:12 PM PDT 24
Finished May 02 01:32:15 PM PDT 24
Peak memory 201056 kb
Host smart-02104ee5-4609-4774-9aa7-b5462f9fb635
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506757476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2506757476
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.198420954
Short name T546
Test name
Test status
Simulation time 114940444 ps
CPU time 0.96 seconds
Started May 02 01:32:22 PM PDT 24
Finished May 02 01:32:23 PM PDT 24
Peak memory 200936 kb
Host smart-586355b0-0fe5-4be5-8c43-f1e7b8fc0c5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198420954 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.198420954
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.332214564
Short name T550
Test name
Test status
Simulation time 75249448 ps
CPU time 0.75 seconds
Started May 02 01:32:20 PM PDT 24
Finished May 02 01:32:21 PM PDT 24
Peak memory 200824 kb
Host smart-771e0cb5-a19c-472b-9fc0-59ba33a742c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332214564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.332214564
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1508199108
Short name T82
Test name
Test status
Simulation time 273167432 ps
CPU time 1.55 seconds
Started May 02 01:32:21 PM PDT 24
Finished May 02 01:32:23 PM PDT 24
Peak memory 201036 kb
Host smart-4446a614-9367-4f24-9af1-64e93deb505e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508199108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1508199108
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1156619171
Short name T91
Test name
Test status
Simulation time 126942327 ps
CPU time 1.98 seconds
Started May 02 01:32:13 PM PDT 24
Finished May 02 01:32:16 PM PDT 24
Peak memory 209312 kb
Host smart-822d600a-de68-4310-bd18-74f54b47ff20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156619171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1156619171
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3438509327
Short name T125
Test name
Test status
Simulation time 917537750 ps
CPU time 3.52 seconds
Started May 02 01:32:14 PM PDT 24
Finished May 02 01:32:18 PM PDT 24
Peak memory 201344 kb
Host smart-1baa4d1b-cb8e-477e-9cd7-1b2600140008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438509327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3438509327
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2067451072
Short name T584
Test name
Test status
Simulation time 213165580 ps
CPU time 1.39 seconds
Started May 02 01:32:21 PM PDT 24
Finished May 02 01:32:23 PM PDT 24
Peak memory 209236 kb
Host smart-1d10b9d2-90a1-4136-9c46-9bc74d1322cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067451072 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2067451072
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2927395747
Short name T113
Test name
Test status
Simulation time 68664180 ps
CPU time 0.73 seconds
Started May 02 01:32:20 PM PDT 24
Finished May 02 01:32:22 PM PDT 24
Peak memory 200844 kb
Host smart-03acb5ef-fdec-4080-8507-3deb97348ce6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927395747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2927395747
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.448025578
Short name T563
Test name
Test status
Simulation time 267112214 ps
CPU time 1.63 seconds
Started May 02 01:32:20 PM PDT 24
Finished May 02 01:32:22 PM PDT 24
Peak memory 201152 kb
Host smart-a8dbe327-8fcc-4d92-bc1a-1ed8b969358f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448025578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.448025578
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.331922339
Short name T579
Test name
Test status
Simulation time 115407166 ps
CPU time 1.5 seconds
Started May 02 01:32:22 PM PDT 24
Finished May 02 01:32:24 PM PDT 24
Peak memory 209404 kb
Host smart-f654c484-08aa-4939-8ed2-cbccc15777a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331922339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.331922339
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2295308943
Short name T566
Test name
Test status
Simulation time 188942090 ps
CPU time 1.24 seconds
Started May 02 01:32:31 PM PDT 24
Finished May 02 01:32:33 PM PDT 24
Peak memory 200940 kb
Host smart-112c56bf-6e15-40c6-aab1-ad2483ccbe2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295308943 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2295308943
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1888090162
Short name T130
Test name
Test status
Simulation time 64362450 ps
CPU time 0.79 seconds
Started May 02 01:32:30 PM PDT 24
Finished May 02 01:32:31 PM PDT 24
Peak memory 200832 kb
Host smart-199bc4d3-d5d8-44f6-b806-dbc12520184a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888090162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1888090162
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.920619538
Short name T114
Test name
Test status
Simulation time 216777584 ps
CPU time 1.53 seconds
Started May 02 01:32:29 PM PDT 24
Finished May 02 01:32:31 PM PDT 24
Peak memory 201100 kb
Host smart-797a620a-e6e1-4179-8085-c76fa79169c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920619538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.920619538
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1704645262
Short name T582
Test name
Test status
Simulation time 298320156 ps
CPU time 2.08 seconds
Started May 02 01:32:21 PM PDT 24
Finished May 02 01:32:24 PM PDT 24
Peak memory 209332 kb
Host smart-f577271d-3066-425a-bed7-9ec06463b695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704645262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1704645262
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3816109497
Short name T88
Test name
Test status
Simulation time 467873292 ps
CPU time 1.81 seconds
Started May 02 01:32:29 PM PDT 24
Finished May 02 01:32:31 PM PDT 24
Peak memory 201132 kb
Host smart-69e451f5-d33a-4013-bf8c-f58129fa3f63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816109497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3816109497
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4212154899
Short name T600
Test name
Test status
Simulation time 137233702 ps
CPU time 1.37 seconds
Started May 02 01:32:30 PM PDT 24
Finished May 02 01:32:32 PM PDT 24
Peak memory 214032 kb
Host smart-c590c778-9496-493e-8c28-5c368d44f6f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212154899 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.4212154899
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2937893222
Short name T604
Test name
Test status
Simulation time 67399263 ps
CPU time 0.81 seconds
Started May 02 01:32:29 PM PDT 24
Finished May 02 01:32:31 PM PDT 24
Peak memory 200900 kb
Host smart-99569252-f986-492c-a37a-16f4eb2eb9cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937893222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2937893222
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3532551601
Short name T551
Test name
Test status
Simulation time 196522796 ps
CPU time 1.46 seconds
Started May 02 01:32:30 PM PDT 24
Finished May 02 01:32:32 PM PDT 24
Peak memory 201072 kb
Host smart-3b2111b3-a201-4e3b-9d3b-e3513fc715d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532551601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3532551601
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2912555732
Short name T581
Test name
Test status
Simulation time 175244727 ps
CPU time 2.38 seconds
Started May 02 01:32:30 PM PDT 24
Finished May 02 01:32:33 PM PDT 24
Peak memory 217376 kb
Host smart-523bce56-105e-45f8-9d66-314960a5bf1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912555732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2912555732
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1917777323
Short name T248
Test name
Test status
Simulation time 62859698 ps
CPU time 0.77 seconds
Started May 02 01:33:09 PM PDT 24
Finished May 02 01:33:11 PM PDT 24
Peak memory 200620 kb
Host smart-189f371d-f4e2-4e26-9b0b-940bba3e0894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917777323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1917777323
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.927788418
Short name T178
Test name
Test status
Simulation time 243870173 ps
CPU time 1.14 seconds
Started May 02 01:33:10 PM PDT 24
Finished May 02 01:33:13 PM PDT 24
Peak memory 218152 kb
Host smart-b4aa70dc-c588-4d03-ab02-496c7daf3433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927788418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.927788418
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1675006840
Short name T455
Test name
Test status
Simulation time 787793883 ps
CPU time 4.13 seconds
Started May 02 01:33:00 PM PDT 24
Finished May 02 01:33:05 PM PDT 24
Peak memory 201032 kb
Host smart-4c45ecba-931b-46b7-89b0-dc5095d55af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675006840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1675006840
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1930181156
Short name T101
Test name
Test status
Simulation time 242107292 ps
CPU time 1.4 seconds
Started May 02 01:32:59 PM PDT 24
Finished May 02 01:33:02 PM PDT 24
Peak memory 201088 kb
Host smart-dc59e3ca-792e-4c0e-b371-27f38442d393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930181156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1930181156
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3475767305
Short name T510
Test name
Test status
Simulation time 8010754372 ps
CPU time 35.05 seconds
Started May 02 01:33:17 PM PDT 24
Finished May 02 01:33:53 PM PDT 24
Peak memory 201192 kb
Host smart-735d03e3-9dc4-4876-9cf0-baa1379186f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475767305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3475767305
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3554034871
Short name T380
Test name
Test status
Simulation time 508079412 ps
CPU time 2.61 seconds
Started May 02 01:33:00 PM PDT 24
Finished May 02 01:33:03 PM PDT 24
Peak memory 200796 kb
Host smart-be876c60-9f08-4633-ab89-6d452d41c462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554034871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3554034871
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2906779271
Short name T514
Test name
Test status
Simulation time 202441689 ps
CPU time 1.3 seconds
Started May 02 01:33:04 PM PDT 24
Finished May 02 01:33:06 PM PDT 24
Peak memory 200776 kb
Host smart-7a543f82-e5da-4c08-b1c1-ff6a8bb7ffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906779271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2906779271
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3753417543
Short name T447
Test name
Test status
Simulation time 56697359 ps
CPU time 0.74 seconds
Started May 02 01:33:18 PM PDT 24
Finished May 02 01:33:20 PM PDT 24
Peak memory 200604 kb
Host smart-f8b07ab9-da00-427d-b25b-2c14d68abdb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753417543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3753417543
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2432642866
Short name T336
Test name
Test status
Simulation time 1898555971 ps
CPU time 7.42 seconds
Started May 02 01:33:09 PM PDT 24
Finished May 02 01:33:18 PM PDT 24
Peak memory 222588 kb
Host smart-78a7d775-561d-44b1-bed4-c2059330d94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432642866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2432642866
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3953814821
Short name T481
Test name
Test status
Simulation time 244194409 ps
CPU time 1.07 seconds
Started May 02 01:33:10 PM PDT 24
Finished May 02 01:33:13 PM PDT 24
Peak memory 217976 kb
Host smart-ca3612c3-cb7d-49ae-97a6-b1b14e87e699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953814821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3953814821
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1576371778
Short name T230
Test name
Test status
Simulation time 217624426 ps
CPU time 0.98 seconds
Started May 02 01:33:11 PM PDT 24
Finished May 02 01:33:13 PM PDT 24
Peak memory 200708 kb
Host smart-db01030f-5d7b-44be-b344-0061fd85a5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576371778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1576371778
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3358127439
Short name T319
Test name
Test status
Simulation time 1525287307 ps
CPU time 5.94 seconds
Started May 02 01:33:13 PM PDT 24
Finished May 02 01:33:20 PM PDT 24
Peak memory 201036 kb
Host smart-997f3061-eeca-4f5a-a6d0-a448e9b9143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358127439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3358127439
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2260455107
Short name T69
Test name
Test status
Simulation time 8674978468 ps
CPU time 13.03 seconds
Started May 02 01:33:15 PM PDT 24
Finished May 02 01:33:29 PM PDT 24
Peak memory 217664 kb
Host smart-c008890e-c624-4789-b143-80148e4bae1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260455107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2260455107
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1036676389
Short name T120
Test name
Test status
Simulation time 171873075 ps
CPU time 1.19 seconds
Started May 02 01:33:10 PM PDT 24
Finished May 02 01:33:13 PM PDT 24
Peak memory 200804 kb
Host smart-802153ef-b8df-437e-a30f-11703070040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036676389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1036676389
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.4263949706
Short name T276
Test name
Test status
Simulation time 115614468 ps
CPU time 1.15 seconds
Started May 02 01:33:11 PM PDT 24
Finished May 02 01:33:15 PM PDT 24
Peak memory 201088 kb
Host smart-cfdf407d-72f4-4845-be51-d0c7842da245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263949706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4263949706
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.262730748
Short name T117
Test name
Test status
Simulation time 9083010439 ps
CPU time 30.82 seconds
Started May 02 01:33:16 PM PDT 24
Finished May 02 01:33:48 PM PDT 24
Peak memory 201188 kb
Host smart-aff94f92-3330-49ba-9057-97d4b2429b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262730748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.262730748
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3948757420
Short name T396
Test name
Test status
Simulation time 488820480 ps
CPU time 2.57 seconds
Started May 02 01:33:10 PM PDT 24
Finished May 02 01:33:14 PM PDT 24
Peak memory 200896 kb
Host smart-b14b862d-0f86-404c-9cce-b5bfc1fa8625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948757420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3948757420
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.996038375
Short name T316
Test name
Test status
Simulation time 95901301 ps
CPU time 0.86 seconds
Started May 02 01:33:10 PM PDT 24
Finished May 02 01:33:12 PM PDT 24
Peak memory 200864 kb
Host smart-d922137f-f7ee-48c9-9256-644d58cd61d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996038375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.996038375
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2821532168
Short name T42
Test name
Test status
Simulation time 2357048768 ps
CPU time 9.16 seconds
Started May 02 01:33:59 PM PDT 24
Finished May 02 01:34:10 PM PDT 24
Peak memory 218688 kb
Host smart-a659bb26-f266-48be-bd58-617367527ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821532168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2821532168
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3266290739
Short name T508
Test name
Test status
Simulation time 245366152 ps
CPU time 1.03 seconds
Started May 02 01:34:00 PM PDT 24
Finished May 02 01:34:03 PM PDT 24
Peak memory 218052 kb
Host smart-05613272-421a-42f2-a4c9-031975551569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266290739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3266290739
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.907217920
Short name T181
Test name
Test status
Simulation time 121071681 ps
CPU time 0.77 seconds
Started May 02 01:33:52 PM PDT 24
Finished May 02 01:33:55 PM PDT 24
Peak memory 200620 kb
Host smart-9a780d97-f7d7-42f4-b261-bed7b7919d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907217920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.907217920
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.444807976
Short name T170
Test name
Test status
Simulation time 1652452348 ps
CPU time 6.04 seconds
Started May 02 01:33:59 PM PDT 24
Finished May 02 01:34:06 PM PDT 24
Peak memory 201072 kb
Host smart-9970b264-86f6-4a71-8163-05d65d611499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444807976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.444807976
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3858829441
Short name T270
Test name
Test status
Simulation time 166450200 ps
CPU time 1.28 seconds
Started May 02 01:33:58 PM PDT 24
Finished May 02 01:34:01 PM PDT 24
Peak memory 200804 kb
Host smart-99e89eed-b9fd-4468-96d7-bfe867964ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858829441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3858829441
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.435397677
Short name T102
Test name
Test status
Simulation time 197781658 ps
CPU time 1.42 seconds
Started May 02 01:33:59 PM PDT 24
Finished May 02 01:34:02 PM PDT 24
Peak memory 201004 kb
Host smart-fe12571d-da9c-4fc8-bde0-8ab152051b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435397677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.435397677
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1311088759
Short name T465
Test name
Test status
Simulation time 6086032562 ps
CPU time 25.99 seconds
Started May 02 01:34:00 PM PDT 24
Finished May 02 01:34:28 PM PDT 24
Peak memory 201100 kb
Host smart-f759c07d-6f0c-40bf-a764-332101da3c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311088759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1311088759
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.4260909553
Short name T165
Test name
Test status
Simulation time 281527940 ps
CPU time 1.94 seconds
Started May 02 01:34:00 PM PDT 24
Finished May 02 01:34:04 PM PDT 24
Peak memory 200912 kb
Host smart-7f40fdee-9e72-41b2-8597-abf8c70aa015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260909553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.4260909553
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1988141177
Short name T209
Test name
Test status
Simulation time 179985104 ps
CPU time 1.18 seconds
Started May 02 01:34:00 PM PDT 24
Finished May 02 01:34:02 PM PDT 24
Peak memory 200836 kb
Host smart-98314da5-f02b-49d3-9f31-1bc7ce79a0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988141177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1988141177
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1050137032
Short name T489
Test name
Test status
Simulation time 77458037 ps
CPU time 0.8 seconds
Started May 02 01:34:05 PM PDT 24
Finished May 02 01:34:07 PM PDT 24
Peak memory 200692 kb
Host smart-8edf0abb-1a64-4222-8160-152ecb2aab1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050137032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1050137032
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3729902567
Short name T525
Test name
Test status
Simulation time 1221790416 ps
CPU time 5.72 seconds
Started May 02 01:34:06 PM PDT 24
Finished May 02 01:34:12 PM PDT 24
Peak memory 218576 kb
Host smart-efc9606b-a8a0-4e99-a340-d33d0df78dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729902567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3729902567
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1912046948
Short name T377
Test name
Test status
Simulation time 244523489 ps
CPU time 1.14 seconds
Started May 02 01:34:08 PM PDT 24
Finished May 02 01:34:10 PM PDT 24
Peak memory 218008 kb
Host smart-88287114-b6c2-46cf-96ff-e04e15a5ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912046948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1912046948
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2743772650
Short name T367
Test name
Test status
Simulation time 173663973 ps
CPU time 0.94 seconds
Started May 02 01:34:06 PM PDT 24
Finished May 02 01:34:07 PM PDT 24
Peak memory 200632 kb
Host smart-4d7b7132-6356-43fa-b758-50efaad08522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743772650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2743772650
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1369900430
Short name T293
Test name
Test status
Simulation time 870669022 ps
CPU time 4.4 seconds
Started May 02 01:33:57 PM PDT 24
Finished May 02 01:34:03 PM PDT 24
Peak memory 201000 kb
Host smart-067786ce-31ad-490c-8ed3-e0f413c8e2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369900430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1369900430
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.247541611
Short name T394
Test name
Test status
Simulation time 145275341 ps
CPU time 1.13 seconds
Started May 02 01:34:00 PM PDT 24
Finished May 02 01:34:03 PM PDT 24
Peak memory 200840 kb
Host smart-065ede8b-7328-4526-a7a5-d7ec8fa29376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247541611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.247541611
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1126213904
Short name T431
Test name
Test status
Simulation time 194400002 ps
CPU time 1.4 seconds
Started May 02 01:33:58 PM PDT 24
Finished May 02 01:34:00 PM PDT 24
Peak memory 201072 kb
Host smart-d085c3f8-8c9d-4f54-a791-0cbd043c6190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126213904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1126213904
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1836057996
Short name T523
Test name
Test status
Simulation time 11045697890 ps
CPU time 36.29 seconds
Started May 02 01:34:06 PM PDT 24
Finished May 02 01:34:44 PM PDT 24
Peak memory 209300 kb
Host smart-6de09716-f621-4b05-a8fa-2cf390b46e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836057996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1836057996
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3804766684
Short name T198
Test name
Test status
Simulation time 354745559 ps
CPU time 2.04 seconds
Started May 02 01:34:00 PM PDT 24
Finished May 02 01:34:03 PM PDT 24
Peak memory 200792 kb
Host smart-fb16425b-9acb-4f47-b9e8-1941bea84b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804766684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3804766684
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2457958483
Short name T466
Test name
Test status
Simulation time 89952602 ps
CPU time 0.96 seconds
Started May 02 01:34:02 PM PDT 24
Finished May 02 01:34:04 PM PDT 24
Peak memory 200920 kb
Host smart-fd69ee25-077e-4f09-a96d-46369708c6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457958483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2457958483
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1212769874
Short name T148
Test name
Test status
Simulation time 66537966 ps
CPU time 0.75 seconds
Started May 02 01:34:08 PM PDT 24
Finished May 02 01:34:09 PM PDT 24
Peak memory 200704 kb
Host smart-fce544a3-a18b-4605-b7af-744733e29af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212769874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1212769874
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2095904071
Short name T275
Test name
Test status
Simulation time 244070456 ps
CPU time 1.13 seconds
Started May 02 01:34:07 PM PDT 24
Finished May 02 01:34:09 PM PDT 24
Peak memory 218164 kb
Host smart-f4aa7f87-8884-4f50-8ca1-28a511212b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095904071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2095904071
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3431920509
Short name T16
Test name
Test status
Simulation time 104740448 ps
CPU time 0.75 seconds
Started May 02 01:34:07 PM PDT 24
Finished May 02 01:34:09 PM PDT 24
Peak memory 200672 kb
Host smart-f122f0e9-22ac-4e86-872a-e7c70fc6a082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431920509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3431920509
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3050832177
Short name T472
Test name
Test status
Simulation time 1672535798 ps
CPU time 6.12 seconds
Started May 02 01:34:14 PM PDT 24
Finished May 02 01:34:21 PM PDT 24
Peak memory 201012 kb
Host smart-c1537bfe-9c7a-4276-a0a2-ccf14ecc4a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050832177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3050832177
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2553005450
Short name T487
Test name
Test status
Simulation time 173405025 ps
CPU time 1.13 seconds
Started May 02 01:34:14 PM PDT 24
Finished May 02 01:34:16 PM PDT 24
Peak memory 200820 kb
Host smart-cd2be1ed-17c9-470c-94c5-49cd517885c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553005450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2553005450
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.894562854
Short name T373
Test name
Test status
Simulation time 116356105 ps
CPU time 1.12 seconds
Started May 02 01:34:06 PM PDT 24
Finished May 02 01:34:08 PM PDT 24
Peak memory 201084 kb
Host smart-4ed15455-c30f-4916-937f-5c6700aca6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894562854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.894562854
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1162597097
Short name T391
Test name
Test status
Simulation time 3060760894 ps
CPU time 13.92 seconds
Started May 02 01:34:10 PM PDT 24
Finished May 02 01:34:25 PM PDT 24
Peak memory 209396 kb
Host smart-9318456e-d343-444e-bde4-368dd882c60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162597097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1162597097
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2755606782
Short name T171
Test name
Test status
Simulation time 245081532 ps
CPU time 1.84 seconds
Started May 02 01:34:07 PM PDT 24
Finished May 02 01:34:10 PM PDT 24
Peak memory 200888 kb
Host smart-4207fa3f-0b6d-46e6-8d78-9d6f48f70f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755606782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2755606782
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1971287973
Short name T53
Test name
Test status
Simulation time 159581344 ps
CPU time 1.23 seconds
Started May 02 01:34:08 PM PDT 24
Finished May 02 01:34:10 PM PDT 24
Peak memory 201088 kb
Host smart-b597dfa8-2b2c-4f8d-bcea-464084d4864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971287973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1971287973
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3991201373
Short name T161
Test name
Test status
Simulation time 64577296 ps
CPU time 0.78 seconds
Started May 02 01:34:18 PM PDT 24
Finished May 02 01:34:20 PM PDT 24
Peak memory 200600 kb
Host smart-d55e6ab6-d869-4de2-9074-3039766d13d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991201373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3991201373
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3155483410
Short name T277
Test name
Test status
Simulation time 1885218059 ps
CPU time 6.68 seconds
Started May 02 01:34:15 PM PDT 24
Finished May 02 01:34:23 PM PDT 24
Peak memory 217624 kb
Host smart-777db202-b335-41a4-989f-70b4654c3245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155483410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3155483410
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.925915027
Short name T197
Test name
Test status
Simulation time 243703006 ps
CPU time 1.03 seconds
Started May 02 01:34:16 PM PDT 24
Finished May 02 01:34:19 PM PDT 24
Peak memory 218060 kb
Host smart-96dee560-04dc-41dd-8ee8-8c341cdc8d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925915027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.925915027
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.681046480
Short name T425
Test name
Test status
Simulation time 89736495 ps
CPU time 0.72 seconds
Started May 02 01:34:07 PM PDT 24
Finished May 02 01:34:08 PM PDT 24
Peak memory 200680 kb
Host smart-75ea4803-6289-4776-bb4c-7a4c7773a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681046480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.681046480
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.581679634
Short name T416
Test name
Test status
Simulation time 1597419315 ps
CPU time 6.49 seconds
Started May 02 01:34:06 PM PDT 24
Finished May 02 01:34:13 PM PDT 24
Peak memory 201084 kb
Host smart-214ce0b2-76c7-4f25-b04d-107994c794aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581679634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.581679634
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.621637836
Short name T215
Test name
Test status
Simulation time 151277803 ps
CPU time 1.1 seconds
Started May 02 01:34:09 PM PDT 24
Finished May 02 01:34:11 PM PDT 24
Peak memory 200804 kb
Host smart-708bba49-8427-4b84-aa2c-682a018d4648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621637836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.621637836
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1909978194
Short name T317
Test name
Test status
Simulation time 230651369 ps
CPU time 1.49 seconds
Started May 02 01:34:07 PM PDT 24
Finished May 02 01:34:09 PM PDT 24
Peak memory 201088 kb
Host smart-6d356e1e-bfcd-478e-a9fc-4dfdb203c10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909978194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1909978194
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1635191728
Short name T257
Test name
Test status
Simulation time 6469418574 ps
CPU time 26.24 seconds
Started May 02 01:34:16 PM PDT 24
Finished May 02 01:34:44 PM PDT 24
Peak memory 209420 kb
Host smart-658d3409-f9de-4a64-ae34-4394491d0751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635191728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1635191728
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.424330011
Short name T357
Test name
Test status
Simulation time 132200218 ps
CPU time 1.81 seconds
Started May 02 01:34:06 PM PDT 24
Finished May 02 01:34:09 PM PDT 24
Peak memory 209028 kb
Host smart-64dd4474-bb01-400d-8549-e7c63ff11d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424330011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.424330011
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3915917752
Short name T98
Test name
Test status
Simulation time 106648354 ps
CPU time 0.95 seconds
Started May 02 01:34:07 PM PDT 24
Finished May 02 01:34:09 PM PDT 24
Peak memory 200840 kb
Host smart-4c6d1939-6d8e-4599-aaad-86e657c4a980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915917752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3915917752
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.4168642505
Short name T267
Test name
Test status
Simulation time 92859333 ps
CPU time 0.85 seconds
Started May 02 01:34:15 PM PDT 24
Finished May 02 01:34:17 PM PDT 24
Peak memory 200596 kb
Host smart-c5bc7f1a-f535-4e11-b636-34a822b3c1af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168642505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.4168642505
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1501988557
Short name T231
Test name
Test status
Simulation time 1890245501 ps
CPU time 6.88 seconds
Started May 02 01:34:14 PM PDT 24
Finished May 02 01:34:22 PM PDT 24
Peak memory 218008 kb
Host smart-6037904a-57e8-4ae3-91ba-a584302c2c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501988557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1501988557
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3215877285
Short name T314
Test name
Test status
Simulation time 243330257 ps
CPU time 1.04 seconds
Started May 02 01:34:14 PM PDT 24
Finished May 02 01:34:16 PM PDT 24
Peak memory 218148 kb
Host smart-0a6631fe-91bd-4ae4-88be-c8378646b3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215877285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3215877285
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.778352377
Short name T365
Test name
Test status
Simulation time 131827852 ps
CPU time 0.83 seconds
Started May 02 01:34:15 PM PDT 24
Finished May 02 01:34:17 PM PDT 24
Peak memory 200680 kb
Host smart-011399b3-c148-48d8-b8d2-2a5e03c7a760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778352377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.778352377
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.748879609
Short name T272
Test name
Test status
Simulation time 769202619 ps
CPU time 4.18 seconds
Started May 02 01:34:14 PM PDT 24
Finished May 02 01:34:19 PM PDT 24
Peak memory 201056 kb
Host smart-80cf1ff9-1eb7-4add-bdb3-a71e31a86701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748879609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.748879609
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.914194058
Short name T449
Test name
Test status
Simulation time 181691294 ps
CPU time 1.12 seconds
Started May 02 01:34:14 PM PDT 24
Finished May 02 01:34:16 PM PDT 24
Peak memory 200800 kb
Host smart-c5f55360-081c-4172-ad03-211e68f4ebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914194058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.914194058
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2863063554
Short name T94
Test name
Test status
Simulation time 200815929 ps
CPU time 1.37 seconds
Started May 02 01:34:15 PM PDT 24
Finished May 02 01:34:17 PM PDT 24
Peak memory 200992 kb
Host smart-68c935ea-064a-41e7-a81f-843e8d94d073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863063554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2863063554
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.9039566
Short name T423
Test name
Test status
Simulation time 3404258088 ps
CPU time 14.92 seconds
Started May 02 01:34:15 PM PDT 24
Finished May 02 01:34:31 PM PDT 24
Peak memory 201192 kb
Host smart-1f9c794c-40c2-4aa4-b37a-1f7b2b389b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9039566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.9039566
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3158380534
Short name T364
Test name
Test status
Simulation time 290364676 ps
CPU time 2.06 seconds
Started May 02 01:34:15 PM PDT 24
Finished May 02 01:34:19 PM PDT 24
Peak memory 200872 kb
Host smart-8100de8b-1032-457d-aa4c-2e38abeac351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158380534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3158380534
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.4135767855
Short name T454
Test name
Test status
Simulation time 122531397 ps
CPU time 0.99 seconds
Started May 02 01:34:13 PM PDT 24
Finished May 02 01:34:15 PM PDT 24
Peak memory 200876 kb
Host smart-ce76d3eb-0e28-43a8-80a8-e18e8cd73231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135767855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.4135767855
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3772504246
Short name T439
Test name
Test status
Simulation time 65284813 ps
CPU time 0.83 seconds
Started May 02 01:34:23 PM PDT 24
Finished May 02 01:34:25 PM PDT 24
Peak memory 200704 kb
Host smart-c24d81ee-247c-447b-a866-ff4d49802569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772504246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3772504246
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3271424653
Short name T243
Test name
Test status
Simulation time 1876584515 ps
CPU time 7.47 seconds
Started May 02 01:34:14 PM PDT 24
Finished May 02 01:34:22 PM PDT 24
Peak memory 218608 kb
Host smart-a3b4291a-7f19-4512-beed-7ad4ba716b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271424653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3271424653
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1803148454
Short name T271
Test name
Test status
Simulation time 244068500 ps
CPU time 1.1 seconds
Started May 02 01:34:26 PM PDT 24
Finished May 02 01:34:28 PM PDT 24
Peak memory 218204 kb
Host smart-47037ea1-ffd6-420f-acc9-c63e5512b511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803148454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1803148454
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2672270368
Short name T184
Test name
Test status
Simulation time 97608919 ps
CPU time 0.74 seconds
Started May 02 01:34:16 PM PDT 24
Finished May 02 01:34:18 PM PDT 24
Peak memory 200660 kb
Host smart-04323ce2-f627-4cd6-9388-647bb4218e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672270368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2672270368
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3792927757
Short name T339
Test name
Test status
Simulation time 156398235 ps
CPU time 1.1 seconds
Started May 02 01:34:15 PM PDT 24
Finished May 02 01:34:17 PM PDT 24
Peak memory 200844 kb
Host smart-3b7a547e-0886-412a-a237-1ac3de8dc05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792927757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3792927757
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3769525653
Short name T297
Test name
Test status
Simulation time 113287842 ps
CPU time 1.14 seconds
Started May 02 01:34:16 PM PDT 24
Finished May 02 01:34:18 PM PDT 24
Peak memory 201032 kb
Host smart-b185ccbe-bffc-4cab-b4fe-7c0eac2a4f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769525653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3769525653
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2392171241
Short name T188
Test name
Test status
Simulation time 11425155787 ps
CPU time 41.56 seconds
Started May 02 01:34:24 PM PDT 24
Finished May 02 01:35:07 PM PDT 24
Peak memory 201204 kb
Host smart-d3c6df48-20b8-4de6-b555-a9d52c6c3f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392171241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2392171241
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.749689228
Short name T388
Test name
Test status
Simulation time 124206202 ps
CPU time 1.5 seconds
Started May 02 01:34:16 PM PDT 24
Finished May 02 01:34:18 PM PDT 24
Peak memory 200776 kb
Host smart-a55c5c6f-11e9-4ca5-808a-3dfa52cf4b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749689228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.749689228
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.581090910
Short name T512
Test name
Test status
Simulation time 70749536 ps
CPU time 0.82 seconds
Started May 02 01:34:15 PM PDT 24
Finished May 02 01:34:17 PM PDT 24
Peak memory 200808 kb
Host smart-b92296a7-8ee0-4974-888f-30860566a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581090910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.581090910
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1535905141
Short name T187
Test name
Test status
Simulation time 64696551 ps
CPU time 0.77 seconds
Started May 02 01:34:22 PM PDT 24
Finished May 02 01:34:24 PM PDT 24
Peak memory 200680 kb
Host smart-bcbd3a05-d2d9-4a50-961d-f400314966af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535905141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1535905141
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1700406588
Short name T52
Test name
Test status
Simulation time 2189247899 ps
CPU time 8.91 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:10 PM PDT 24
Peak memory 218148 kb
Host smart-11373517-7f42-4bbf-9ce1-330b0f7785c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700406588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1700406588
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.973473533
Short name T408
Test name
Test status
Simulation time 245032490 ps
CPU time 1.01 seconds
Started May 02 01:34:21 PM PDT 24
Finished May 02 01:34:23 PM PDT 24
Peak memory 218052 kb
Host smart-b2816048-8ce2-4113-848f-8137bd4d8675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973473533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.973473533
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3981803643
Short name T405
Test name
Test status
Simulation time 77481283 ps
CPU time 0.7 seconds
Started May 02 01:34:24 PM PDT 24
Finished May 02 01:34:25 PM PDT 24
Peak memory 200656 kb
Host smart-d370d198-2e0d-45aa-9693-01e0ce9a7975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981803643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3981803643
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2306863563
Short name T163
Test name
Test status
Simulation time 1303789343 ps
CPU time 5.51 seconds
Started May 02 01:34:24 PM PDT 24
Finished May 02 01:34:31 PM PDT 24
Peak memory 201000 kb
Host smart-1fcf5150-743b-4a6f-9c85-2b5d9d5683eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306863563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2306863563
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.475036382
Short name T409
Test name
Test status
Simulation time 113438753 ps
CPU time 0.98 seconds
Started May 02 01:34:21 PM PDT 24
Finished May 02 01:34:23 PM PDT 24
Peak memory 200920 kb
Host smart-af5db4b6-b501-4005-988d-a68b3210b384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475036382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.475036382
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2935207269
Short name T189
Test name
Test status
Simulation time 125825076 ps
CPU time 1.23 seconds
Started May 02 01:34:21 PM PDT 24
Finished May 02 01:34:24 PM PDT 24
Peak memory 201068 kb
Host smart-f2de6abd-14c9-461a-94a7-22cd062239e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935207269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2935207269
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3271750957
Short name T119
Test name
Test status
Simulation time 1891036098 ps
CPU time 6.62 seconds
Started May 02 01:34:22 PM PDT 24
Finished May 02 01:34:30 PM PDT 24
Peak memory 201020 kb
Host smart-b5878451-c321-45de-bb7d-a36cf44abbaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271750957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3271750957
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2976099414
Short name T225
Test name
Test status
Simulation time 373579678 ps
CPU time 2.26 seconds
Started May 02 01:34:23 PM PDT 24
Finished May 02 01:34:26 PM PDT 24
Peak memory 200844 kb
Host smart-a064cf2f-7671-4c91-b7b2-aad78906480c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976099414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2976099414
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3220537145
Short name T131
Test name
Test status
Simulation time 81983529 ps
CPU time 0.81 seconds
Started May 02 01:34:21 PM PDT 24
Finished May 02 01:34:23 PM PDT 24
Peak memory 200832 kb
Host smart-38424c05-7c1e-45fd-9747-f0f97a30e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220537145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3220537145
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1771755076
Short name T46
Test name
Test status
Simulation time 87289129 ps
CPU time 0.84 seconds
Started May 02 01:34:32 PM PDT 24
Finished May 02 01:34:34 PM PDT 24
Peak memory 200604 kb
Host smart-f40085bc-d9ab-4a6e-95b5-2d449ca15626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771755076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1771755076
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2688434170
Short name T320
Test name
Test status
Simulation time 1895748323 ps
CPU time 7.21 seconds
Started May 02 01:34:23 PM PDT 24
Finished May 02 01:34:31 PM PDT 24
Peak memory 217560 kb
Host smart-fdeb7ff4-d6f5-4094-bd16-46042c3d1979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688434170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2688434170
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.694462208
Short name T445
Test name
Test status
Simulation time 245032412 ps
CPU time 1.05 seconds
Started May 02 01:34:26 PM PDT 24
Finished May 02 01:34:28 PM PDT 24
Peak memory 218196 kb
Host smart-be82cb75-0cfe-4564-b372-8926566d9a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694462208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.694462208
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1481455483
Short name T19
Test name
Test status
Simulation time 160082229 ps
CPU time 0.88 seconds
Started May 02 01:34:23 PM PDT 24
Finished May 02 01:34:25 PM PDT 24
Peak memory 200620 kb
Host smart-19020692-2369-49c4-b110-a7a236ce148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481455483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1481455483
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1797391776
Short name T540
Test name
Test status
Simulation time 1581629266 ps
CPU time 5.74 seconds
Started May 02 01:34:25 PM PDT 24
Finished May 02 01:34:32 PM PDT 24
Peak memory 201048 kb
Host smart-6bff18f3-02fd-4f38-a632-cd05fd5b201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797391776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1797391776
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2037114737
Short name T195
Test name
Test status
Simulation time 156279338 ps
CPU time 1.1 seconds
Started May 02 01:34:24 PM PDT 24
Finished May 02 01:34:26 PM PDT 24
Peak memory 200868 kb
Host smart-f87e260c-a3bd-474f-9d7a-24b1339e96cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037114737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2037114737
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.749202622
Short name T1
Test name
Test status
Simulation time 251957351 ps
CPU time 1.39 seconds
Started May 02 01:34:21 PM PDT 24
Finished May 02 01:34:23 PM PDT 24
Peak memory 201080 kb
Host smart-b55c3cdd-5fc7-4d01-9a5e-871834b0c3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749202622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.749202622
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2694305301
Short name T301
Test name
Test status
Simulation time 5727279388 ps
CPU time 26.16 seconds
Started May 02 01:34:31 PM PDT 24
Finished May 02 01:34:58 PM PDT 24
Peak memory 209364 kb
Host smart-f9e182e7-8c51-4182-a3fc-e32d804b2de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694305301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2694305301
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.308015309
Short name T369
Test name
Test status
Simulation time 366121330 ps
CPU time 2.24 seconds
Started May 02 01:34:23 PM PDT 24
Finished May 02 01:34:26 PM PDT 24
Peak memory 200880 kb
Host smart-9a69bf9f-af3f-46df-afca-4331739bfdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308015309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.308015309
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2491806466
Short name T2
Test name
Test status
Simulation time 116113210 ps
CPU time 0.91 seconds
Started May 02 01:34:24 PM PDT 24
Finished May 02 01:34:26 PM PDT 24
Peak memory 200884 kb
Host smart-caf5c374-8104-4d72-bc65-6835b54800bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491806466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2491806466
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1237528369
Short name T486
Test name
Test status
Simulation time 64415476 ps
CPU time 0.77 seconds
Started May 02 01:34:30 PM PDT 24
Finished May 02 01:34:32 PM PDT 24
Peak memory 200680 kb
Host smart-562972d8-411b-4684-a30d-ea3048a99f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237528369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1237528369
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1376251056
Short name T34
Test name
Test status
Simulation time 1884597467 ps
CPU time 7.07 seconds
Started May 02 01:34:30 PM PDT 24
Finished May 02 01:34:38 PM PDT 24
Peak memory 217520 kb
Host smart-3414aaf3-b7b8-4732-8ad2-4305adcf35cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376251056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1376251056
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3628116159
Short name T530
Test name
Test status
Simulation time 245245745 ps
CPU time 1.01 seconds
Started May 02 01:34:30 PM PDT 24
Finished May 02 01:34:32 PM PDT 24
Peak memory 218116 kb
Host smart-5601ce6b-0223-46e9-a8d4-6a4ae39bbd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628116159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3628116159
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1155402337
Short name T402
Test name
Test status
Simulation time 106272590 ps
CPU time 0.81 seconds
Started May 02 01:34:33 PM PDT 24
Finished May 02 01:34:34 PM PDT 24
Peak memory 200684 kb
Host smart-d4567f7e-fe4c-4b5d-b8f3-f9e8c331ad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155402337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1155402337
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2127457314
Short name T296
Test name
Test status
Simulation time 1409410981 ps
CPU time 5.51 seconds
Started May 02 01:34:30 PM PDT 24
Finished May 02 01:34:36 PM PDT 24
Peak memory 201080 kb
Host smart-ccbd6948-9dfe-4420-aa55-626aab8e87a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127457314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2127457314
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2198738666
Short name T174
Test name
Test status
Simulation time 96322946 ps
CPU time 0.95 seconds
Started May 02 01:34:36 PM PDT 24
Finished May 02 01:34:37 PM PDT 24
Peak memory 200900 kb
Host smart-6d056190-9252-4261-aa5c-4bb6ac0f7072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198738666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2198738666
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1851666209
Short name T414
Test name
Test status
Simulation time 239538084 ps
CPU time 1.42 seconds
Started May 02 01:34:31 PM PDT 24
Finished May 02 01:34:34 PM PDT 24
Peak memory 201076 kb
Host smart-b9af52dd-56b5-4303-824e-12773f256a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851666209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1851666209
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2090162478
Short name T121
Test name
Test status
Simulation time 214581772 ps
CPU time 1.39 seconds
Started May 02 01:34:30 PM PDT 24
Finished May 02 01:34:32 PM PDT 24
Peak memory 201132 kb
Host smart-8de7350f-de90-4fc4-93f4-fe210d731b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090162478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2090162478
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2512755282
Short name T527
Test name
Test status
Simulation time 119863127 ps
CPU time 1.52 seconds
Started May 02 01:34:32 PM PDT 24
Finished May 02 01:34:34 PM PDT 24
Peak memory 200896 kb
Host smart-4132547b-cd18-413e-b46b-594a7d16d6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512755282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2512755282
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2185149261
Short name T448
Test name
Test status
Simulation time 92986501 ps
CPU time 0.86 seconds
Started May 02 01:34:30 PM PDT 24
Finished May 02 01:34:32 PM PDT 24
Peak memory 200908 kb
Host smart-efa05bfe-fbe5-4d10-9cf5-812842eb85ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185149261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2185149261
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2684240418
Short name T379
Test name
Test status
Simulation time 61035737 ps
CPU time 0.73 seconds
Started May 02 01:34:40 PM PDT 24
Finished May 02 01:34:42 PM PDT 24
Peak memory 200716 kb
Host smart-33b7aa4f-d9ed-4ea2-b638-2c5499a79cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684240418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2684240418
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2680113983
Short name T471
Test name
Test status
Simulation time 1892747722 ps
CPU time 7.72 seconds
Started May 02 01:34:36 PM PDT 24
Finished May 02 01:34:45 PM PDT 24
Peak memory 218600 kb
Host smart-2d5eec43-a7c5-4ab8-98c1-f127fb44e1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680113983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2680113983
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4141858252
Short name T376
Test name
Test status
Simulation time 243829369 ps
CPU time 1.11 seconds
Started May 02 01:34:39 PM PDT 24
Finished May 02 01:34:41 PM PDT 24
Peak memory 218088 kb
Host smart-20749a18-55ec-4ca4-afba-1bf8397c2142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141858252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4141858252
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1935149695
Short name T308
Test name
Test status
Simulation time 163488134 ps
CPU time 0.84 seconds
Started May 02 01:34:33 PM PDT 24
Finished May 02 01:34:35 PM PDT 24
Peak memory 200600 kb
Host smart-da826813-b7db-4359-9785-e803d54b7cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935149695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1935149695
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.845354164
Short name T180
Test name
Test status
Simulation time 704655618 ps
CPU time 3.43 seconds
Started May 02 01:34:33 PM PDT 24
Finished May 02 01:34:38 PM PDT 24
Peak memory 201020 kb
Host smart-81964f24-47ea-4973-9e4c-4a4463aa4577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845354164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.845354164
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2411598374
Short name T144
Test name
Test status
Simulation time 185775986 ps
CPU time 1.2 seconds
Started May 02 01:34:37 PM PDT 24
Finished May 02 01:34:39 PM PDT 24
Peak memory 200772 kb
Host smart-5af00dc9-e8d2-4a31-8adf-2ca0ced658cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411598374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2411598374
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3754204848
Short name T134
Test name
Test status
Simulation time 114080088 ps
CPU time 1.25 seconds
Started May 02 01:34:30 PM PDT 24
Finished May 02 01:34:32 PM PDT 24
Peak memory 201064 kb
Host smart-f3aba31b-ce58-43c9-8c1c-63b1c7a7bd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754204848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3754204848
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.99777410
Short name T103
Test name
Test status
Simulation time 9373529316 ps
CPU time 29.96 seconds
Started May 02 01:34:38 PM PDT 24
Finished May 02 01:35:09 PM PDT 24
Peak memory 201112 kb
Host smart-48bdc383-cc76-4d5f-9a04-522ae7ecb7bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99777410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.99777410
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.371779724
Short name T397
Test name
Test status
Simulation time 129033133 ps
CPU time 1.63 seconds
Started May 02 01:34:33 PM PDT 24
Finished May 02 01:34:35 PM PDT 24
Peak memory 200796 kb
Host smart-bc410558-5ad1-4be8-8d8a-d057301e77e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371779724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.371779724
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.844162273
Short name T456
Test name
Test status
Simulation time 94749734 ps
CPU time 0.88 seconds
Started May 02 01:34:32 PM PDT 24
Finished May 02 01:34:34 PM PDT 24
Peak memory 200880 kb
Host smart-da85c4c4-e8c0-4687-b07b-32333c5e1c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844162273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.844162273
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.425409954
Short name T356
Test name
Test status
Simulation time 96580392 ps
CPU time 0.84 seconds
Started May 02 01:33:20 PM PDT 24
Finished May 02 01:33:22 PM PDT 24
Peak memory 200712 kb
Host smart-c1ed917e-d37a-455a-b561-90b3b44a4f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425409954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.425409954
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3535569105
Short name T500
Test name
Test status
Simulation time 2369166069 ps
CPU time 8.68 seconds
Started May 02 01:33:17 PM PDT 24
Finished May 02 01:33:27 PM PDT 24
Peak memory 230988 kb
Host smart-9423e197-c7ed-46bc-bb6b-0540c1f8cb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535569105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3535569105
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3143060028
Short name T92
Test name
Test status
Simulation time 243870127 ps
CPU time 1.02 seconds
Started May 02 01:33:18 PM PDT 24
Finished May 02 01:33:20 PM PDT 24
Peak memory 218108 kb
Host smart-c41d715e-ee6b-42a8-9e7c-db785d33befb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143060028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3143060028
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2589438793
Short name T503
Test name
Test status
Simulation time 126623526 ps
CPU time 0.78 seconds
Started May 02 01:33:16 PM PDT 24
Finished May 02 01:33:18 PM PDT 24
Peak memory 200680 kb
Host smart-19a9c854-c707-4960-8f54-dbd66727d5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589438793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2589438793
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.926095276
Short name T264
Test name
Test status
Simulation time 1808174312 ps
CPU time 6.86 seconds
Started May 02 01:33:19 PM PDT 24
Finished May 02 01:33:27 PM PDT 24
Peak memory 201068 kb
Host smart-ea482e86-f3ae-4e0c-ab75-d187e77d83a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926095276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.926095276
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1206703630
Short name T65
Test name
Test status
Simulation time 17211580017 ps
CPU time 25.16 seconds
Started May 02 01:33:19 PM PDT 24
Finished May 02 01:33:45 PM PDT 24
Peak memory 217792 kb
Host smart-ccde19bf-558f-4eb1-af06-799fb4860537
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206703630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1206703630
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3175303392
Short name T511
Test name
Test status
Simulation time 161567723 ps
CPU time 1.1 seconds
Started May 02 01:33:18 PM PDT 24
Finished May 02 01:33:19 PM PDT 24
Peak memory 200796 kb
Host smart-acf4646d-6148-4da7-8268-df10d630ec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175303392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3175303392
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2214769536
Short name T4
Test name
Test status
Simulation time 245618708 ps
CPU time 1.44 seconds
Started May 02 01:33:17 PM PDT 24
Finished May 02 01:33:19 PM PDT 24
Peak memory 201104 kb
Host smart-528600a0-31fd-4933-b435-207e534cff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214769536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2214769536
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.381224137
Short name T71
Test name
Test status
Simulation time 3558144566 ps
CPU time 13.56 seconds
Started May 02 01:33:16 PM PDT 24
Finished May 02 01:33:31 PM PDT 24
Peak memory 201164 kb
Host smart-4a091a47-ae2f-4cfa-87ba-c6d10e8a0797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381224137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.381224137
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3626296092
Short name T74
Test name
Test status
Simulation time 322403691 ps
CPU time 2.3 seconds
Started May 02 01:33:16 PM PDT 24
Finished May 02 01:33:19 PM PDT 24
Peak memory 200832 kb
Host smart-8df96c00-50ff-4bfd-acd2-4fc126c3fdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626296092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3626296092
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.622546979
Short name T485
Test name
Test status
Simulation time 105110770 ps
CPU time 1 seconds
Started May 02 01:33:15 PM PDT 24
Finished May 02 01:33:17 PM PDT 24
Peak memory 200816 kb
Host smart-18edd593-0c55-429d-83a1-3f0e445b8af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622546979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.622546979
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1768445061
Short name T213
Test name
Test status
Simulation time 82082802 ps
CPU time 0.79 seconds
Started May 02 01:34:37 PM PDT 24
Finished May 02 01:34:38 PM PDT 24
Peak memory 200628 kb
Host smart-330679d9-873d-4537-ac38-468a2c71bcbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768445061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1768445061
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1548572286
Short name T515
Test name
Test status
Simulation time 1906042905 ps
CPU time 6.9 seconds
Started May 02 01:34:38 PM PDT 24
Finished May 02 01:34:46 PM PDT 24
Peak memory 218496 kb
Host smart-3a11cc46-3439-4371-908b-beb4596d674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548572286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1548572286
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.500506147
Short name T528
Test name
Test status
Simulation time 244749352 ps
CPU time 1.04 seconds
Started May 02 01:34:39 PM PDT 24
Finished May 02 01:34:41 PM PDT 24
Peak memory 218196 kb
Host smart-f2b9da6e-5e93-463b-9326-f6ce5821d600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500506147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.500506147
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1689008755
Short name T415
Test name
Test status
Simulation time 94105275 ps
CPU time 0.72 seconds
Started May 02 01:34:38 PM PDT 24
Finished May 02 01:34:39 PM PDT 24
Peak memory 200700 kb
Host smart-9b76b093-fc16-431b-93bd-b7bdec470c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689008755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1689008755
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2445439728
Short name T518
Test name
Test status
Simulation time 849036071 ps
CPU time 4.28 seconds
Started May 02 01:34:38 PM PDT 24
Finished May 02 01:34:43 PM PDT 24
Peak memory 200996 kb
Host smart-b5a21b3f-57be-45a7-9ae9-819d0c636bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445439728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2445439728
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1796227582
Short name T241
Test name
Test status
Simulation time 102193746 ps
CPU time 0.95 seconds
Started May 02 01:34:42 PM PDT 24
Finished May 02 01:34:43 PM PDT 24
Peak memory 200904 kb
Host smart-3f4e0b2a-114d-4872-a7e9-c2f64b9f1e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796227582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1796227582
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.848340212
Short name T156
Test name
Test status
Simulation time 231290889 ps
CPU time 1.43 seconds
Started May 02 01:34:40 PM PDT 24
Finished May 02 01:34:42 PM PDT 24
Peak memory 201092 kb
Host smart-614e37dd-9288-4129-aece-cc689265df93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848340212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.848340212
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.265957515
Short name T354
Test name
Test status
Simulation time 6339493691 ps
CPU time 26.61 seconds
Started May 02 01:34:38 PM PDT 24
Finished May 02 01:35:06 PM PDT 24
Peak memory 209392 kb
Host smart-9adf342f-ee6d-4022-80a2-e48ef305b894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265957515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.265957515
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.566976166
Short name T538
Test name
Test status
Simulation time 326080515 ps
CPU time 2.01 seconds
Started May 02 01:34:36 PM PDT 24
Finished May 02 01:34:38 PM PDT 24
Peak memory 200848 kb
Host smart-47e69162-600e-45aa-b464-263c6606f680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566976166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.566976166
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1232497237
Short name T158
Test name
Test status
Simulation time 110325200 ps
CPU time 0.9 seconds
Started May 02 01:34:38 PM PDT 24
Finished May 02 01:34:40 PM PDT 24
Peak memory 200840 kb
Host smart-27a2a187-3652-44a0-9347-c94ec05f19ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232497237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1232497237
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2902161349
Short name T305
Test name
Test status
Simulation time 77951580 ps
CPU time 0.83 seconds
Started May 02 01:34:48 PM PDT 24
Finished May 02 01:34:50 PM PDT 24
Peak memory 200712 kb
Host smart-aa4b9762-b2b1-46cc-bb93-8832ee7e075c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902161349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2902161349
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3033160588
Short name T41
Test name
Test status
Simulation time 1230668143 ps
CPU time 5.28 seconds
Started May 02 01:34:46 PM PDT 24
Finished May 02 01:34:52 PM PDT 24
Peak memory 217544 kb
Host smart-e04931a0-11d4-4245-81e4-1fa6e72f8c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033160588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3033160588
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1846533599
Short name T429
Test name
Test status
Simulation time 244497793 ps
CPU time 1.18 seconds
Started May 02 01:34:46 PM PDT 24
Finished May 02 01:34:49 PM PDT 24
Peak memory 218292 kb
Host smart-43ec0b11-8401-40fa-9843-429499b2307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846533599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1846533599
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2453486030
Short name T442
Test name
Test status
Simulation time 165202327 ps
CPU time 0.83 seconds
Started May 02 01:34:37 PM PDT 24
Finished May 02 01:34:39 PM PDT 24
Peak memory 200584 kb
Host smart-143caac5-0c0f-407a-adc3-ca80fe04019a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453486030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2453486030
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.390157540
Short name T349
Test name
Test status
Simulation time 1662053043 ps
CPU time 6.35 seconds
Started May 02 01:34:37 PM PDT 24
Finished May 02 01:34:44 PM PDT 24
Peak memory 201036 kb
Host smart-913ee4d7-9eff-4411-96bd-eb72551e9e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390157540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.390157540
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.66480693
Short name T491
Test name
Test status
Simulation time 153369125 ps
CPU time 1.08 seconds
Started May 02 01:34:46 PM PDT 24
Finished May 02 01:34:48 PM PDT 24
Peak memory 200920 kb
Host smart-2be73ac7-2db8-43c2-b9a4-e39852d2a090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66480693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.66480693
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1276887897
Short name T361
Test name
Test status
Simulation time 185457782 ps
CPU time 1.47 seconds
Started May 02 01:34:39 PM PDT 24
Finished May 02 01:34:41 PM PDT 24
Peak memory 201020 kb
Host smart-743d71fd-6a53-4308-b7b8-dd6b427e0543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276887897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1276887897
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1146066732
Short name T99
Test name
Test status
Simulation time 4286323040 ps
CPU time 15.52 seconds
Started May 02 01:34:48 PM PDT 24
Finished May 02 01:35:05 PM PDT 24
Peak memory 201236 kb
Host smart-cc040783-b29e-4321-b61d-a57f6bc0da94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146066732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1146066732
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4065847553
Short name T246
Test name
Test status
Simulation time 503664380 ps
CPU time 2.64 seconds
Started May 02 01:34:36 PM PDT 24
Finished May 02 01:34:40 PM PDT 24
Peak memory 200848 kb
Host smart-1d128d86-0b45-40ff-903f-e4af635df6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065847553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4065847553
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2641888519
Short name T206
Test name
Test status
Simulation time 131996869 ps
CPU time 1.31 seconds
Started May 02 01:34:36 PM PDT 24
Finished May 02 01:34:38 PM PDT 24
Peak memory 200868 kb
Host smart-5519db30-d00f-4e84-9a25-1e4045094f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641888519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2641888519
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2375234645
Short name T192
Test name
Test status
Simulation time 65531449 ps
CPU time 0.74 seconds
Started May 02 01:34:46 PM PDT 24
Finished May 02 01:34:48 PM PDT 24
Peak memory 200668 kb
Host smart-2929a900-ad7c-4857-a6f0-794949bbcc66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375234645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2375234645
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2137823420
Short name T295
Test name
Test status
Simulation time 2361501318 ps
CPU time 8.01 seconds
Started May 02 01:34:47 PM PDT 24
Finished May 02 01:34:56 PM PDT 24
Peak memory 222784 kb
Host smart-0b27144c-66e9-4deb-bdd0-46a29ceaf1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137823420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2137823420
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.587313892
Short name T146
Test name
Test status
Simulation time 244369099 ps
CPU time 1.09 seconds
Started May 02 01:34:43 PM PDT 24
Finished May 02 01:34:45 PM PDT 24
Peak memory 217956 kb
Host smart-3eba416f-601b-41b2-a0ec-269bc9012150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587313892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.587313892
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.685294978
Short name T200
Test name
Test status
Simulation time 213241037 ps
CPU time 0.91 seconds
Started May 02 01:34:44 PM PDT 24
Finished May 02 01:34:46 PM PDT 24
Peak memory 200636 kb
Host smart-7d99b623-39d7-4cd1-b1a9-9d971ba2b10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685294978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.685294978
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.74387931
Short name T490
Test name
Test status
Simulation time 1669211886 ps
CPU time 6.13 seconds
Started May 02 01:34:47 PM PDT 24
Finished May 02 01:34:54 PM PDT 24
Peak memory 201060 kb
Host smart-f6448d5d-3bff-44cd-b705-abc840649ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74387931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.74387931
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2164700990
Short name T153
Test name
Test status
Simulation time 180233991 ps
CPU time 1.16 seconds
Started May 02 01:34:47 PM PDT 24
Finished May 02 01:34:49 PM PDT 24
Peak memory 200848 kb
Host smart-1394c6c3-ac20-4151-b9f4-a0722d4eccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164700990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2164700990
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3300511618
Short name T392
Test name
Test status
Simulation time 120033373 ps
CPU time 1.18 seconds
Started May 02 01:34:47 PM PDT 24
Finished May 02 01:34:50 PM PDT 24
Peak memory 201060 kb
Host smart-5f877521-17f3-4587-bdc5-db8c1ff8a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300511618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3300511618
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2955643913
Short name T533
Test name
Test status
Simulation time 8245309049 ps
CPU time 36.23 seconds
Started May 02 01:34:46 PM PDT 24
Finished May 02 01:35:23 PM PDT 24
Peak memory 201256 kb
Host smart-cf1738db-1f73-4587-a4c1-0c9fef3954ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955643913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2955643913
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.235917250
Short name T253
Test name
Test status
Simulation time 184537141 ps
CPU time 1.23 seconds
Started May 02 01:34:46 PM PDT 24
Finished May 02 01:34:48 PM PDT 24
Peak memory 200864 kb
Host smart-296e5e4c-8e49-4dcb-b2ef-3ff657078612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235917250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.235917250
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.169924454
Short name T497
Test name
Test status
Simulation time 54703033 ps
CPU time 0.74 seconds
Started May 02 01:34:53 PM PDT 24
Finished May 02 01:34:55 PM PDT 24
Peak memory 200676 kb
Host smart-59b4ded8-8898-4c29-9b78-47c529e3986e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169924454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.169924454
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.381125759
Short name T39
Test name
Test status
Simulation time 2374585380 ps
CPU time 8.75 seconds
Started May 02 01:34:57 PM PDT 24
Finished May 02 01:35:06 PM PDT 24
Peak memory 218392 kb
Host smart-b30e5a2f-8aff-459a-958a-3afd1cd7ca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381125759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.381125759
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4231993747
Short name T453
Test name
Test status
Simulation time 244773446 ps
CPU time 1.06 seconds
Started May 02 01:34:53 PM PDT 24
Finished May 02 01:34:55 PM PDT 24
Peak memory 218224 kb
Host smart-38df4263-b931-4fd3-89b7-6f07720ce3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231993747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4231993747
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.30943908
Short name T362
Test name
Test status
Simulation time 177448838 ps
CPU time 0.85 seconds
Started May 02 01:34:45 PM PDT 24
Finished May 02 01:34:47 PM PDT 24
Peak memory 200660 kb
Host smart-e1722fb7-1427-4ed9-ae9c-63fc41cdf21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30943908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.30943908
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3386154712
Short name T229
Test name
Test status
Simulation time 911199381 ps
CPU time 4.61 seconds
Started May 02 01:34:45 PM PDT 24
Finished May 02 01:34:50 PM PDT 24
Peak memory 201060 kb
Host smart-16058ad1-db21-45b8-8a5a-3d263652fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386154712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3386154712
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.252078001
Short name T470
Test name
Test status
Simulation time 114154662 ps
CPU time 1.07 seconds
Started May 02 01:34:52 PM PDT 24
Finished May 02 01:34:53 PM PDT 24
Peak memory 200784 kb
Host smart-96649d96-b50e-4c8b-987b-b334a8b1a9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252078001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.252078001
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1296700935
Short name T382
Test name
Test status
Simulation time 254290766 ps
CPU time 1.56 seconds
Started May 02 01:34:45 PM PDT 24
Finished May 02 01:34:47 PM PDT 24
Peak memory 201068 kb
Host smart-06d36bef-6b6b-415c-9c29-4c1b20d944ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296700935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1296700935
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1314509980
Short name T381
Test name
Test status
Simulation time 5014322577 ps
CPU time 19.15 seconds
Started May 02 01:34:54 PM PDT 24
Finished May 02 01:35:14 PM PDT 24
Peak memory 209364 kb
Host smart-73fa2138-fedb-474d-8e97-25e933272eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314509980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1314509980
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.423440777
Short name T259
Test name
Test status
Simulation time 508703987 ps
CPU time 2.72 seconds
Started May 02 01:34:48 PM PDT 24
Finished May 02 01:34:52 PM PDT 24
Peak memory 200880 kb
Host smart-73b745fb-3277-4e1d-93aa-f3e589947dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423440777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.423440777
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3974065407
Short name T255
Test name
Test status
Simulation time 94239812 ps
CPU time 0.88 seconds
Started May 02 01:34:47 PM PDT 24
Finished May 02 01:34:49 PM PDT 24
Peak memory 200852 kb
Host smart-7b632c88-07e9-46e5-ba00-124c54569b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974065407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3974065407
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1637645656
Short name T29
Test name
Test status
Simulation time 69690400 ps
CPU time 0.74 seconds
Started May 02 01:34:54 PM PDT 24
Finished May 02 01:34:56 PM PDT 24
Peak memory 200668 kb
Host smart-bc3f8022-51d5-4435-be68-61aef8c21d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637645656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1637645656
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2809830792
Short name T505
Test name
Test status
Simulation time 1889250152 ps
CPU time 7.45 seconds
Started May 02 01:34:52 PM PDT 24
Finished May 02 01:35:00 PM PDT 24
Peak memory 217984 kb
Host smart-6860110b-18bc-4af0-af2d-affdc7536115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809830792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2809830792
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1074268735
Short name T217
Test name
Test status
Simulation time 244416266 ps
CPU time 1.08 seconds
Started May 02 01:34:54 PM PDT 24
Finished May 02 01:34:56 PM PDT 24
Peak memory 218008 kb
Host smart-1cfba723-b4f6-465a-bbc7-7c4a392fb407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074268735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1074268735
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3924629756
Short name T526
Test name
Test status
Simulation time 105077588 ps
CPU time 0.82 seconds
Started May 02 01:34:56 PM PDT 24
Finished May 02 01:34:57 PM PDT 24
Peak memory 200648 kb
Host smart-b29174a7-b0de-4bf7-80ce-9626e8f099dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924629756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3924629756
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2856080254
Short name T280
Test name
Test status
Simulation time 1171455050 ps
CPU time 4.46 seconds
Started May 02 01:34:54 PM PDT 24
Finished May 02 01:34:59 PM PDT 24
Peak memory 201036 kb
Host smart-1f3d08b5-c39a-4a9c-9a14-fa57fd4a30f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856080254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2856080254
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.420435969
Short name T239
Test name
Test status
Simulation time 156450609 ps
CPU time 1.07 seconds
Started May 02 01:34:55 PM PDT 24
Finished May 02 01:34:57 PM PDT 24
Peak memory 200840 kb
Host smart-2493c7c9-4ffc-4ee1-9dde-1f801b8c3cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420435969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.420435969
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2365467670
Short name T49
Test name
Test status
Simulation time 204908302 ps
CPU time 1.34 seconds
Started May 02 01:34:52 PM PDT 24
Finished May 02 01:34:54 PM PDT 24
Peak memory 200996 kb
Host smart-72904638-a1d1-4c53-ac04-0672379a9d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365467670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2365467670
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3767184193
Short name T384
Test name
Test status
Simulation time 6086628162 ps
CPU time 26.73 seconds
Started May 02 01:34:53 PM PDT 24
Finished May 02 01:35:21 PM PDT 24
Peak memory 210304 kb
Host smart-51a7c180-1195-4c12-9894-18da0a20116d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767184193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3767184193
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1498919253
Short name T341
Test name
Test status
Simulation time 337830965 ps
CPU time 2.13 seconds
Started May 02 01:34:53 PM PDT 24
Finished May 02 01:34:56 PM PDT 24
Peak memory 200796 kb
Host smart-652b7279-6c5c-4d62-aa81-ae263d83b51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498919253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1498919253
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2100632050
Short name T307
Test name
Test status
Simulation time 104701834 ps
CPU time 0.92 seconds
Started May 02 01:34:54 PM PDT 24
Finished May 02 01:34:56 PM PDT 24
Peak memory 200876 kb
Host smart-d8db9001-0260-4b51-a4df-582309d08e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100632050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2100632050
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.4170674275
Short name T193
Test name
Test status
Simulation time 65612973 ps
CPU time 0.83 seconds
Started May 02 01:35:01 PM PDT 24
Finished May 02 01:35:03 PM PDT 24
Peak memory 200732 kb
Host smart-25b8d9fd-2c1b-4ba7-bb38-740a1ccb3a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170674275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4170674275
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3733205876
Short name T35
Test name
Test status
Simulation time 2177177545 ps
CPU time 8.38 seconds
Started May 02 01:34:54 PM PDT 24
Finished May 02 01:35:03 PM PDT 24
Peak memory 218716 kb
Host smart-c1aec151-05e1-4c3e-95b9-3b9b38293925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733205876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3733205876
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2203347598
Short name T399
Test name
Test status
Simulation time 244692874 ps
CPU time 1.04 seconds
Started May 02 01:34:53 PM PDT 24
Finished May 02 01:34:55 PM PDT 24
Peak memory 218056 kb
Host smart-4eb5e993-df8a-4173-ba38-00ab0e592e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203347598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2203347598
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.660528240
Short name T387
Test name
Test status
Simulation time 250580248 ps
CPU time 1.04 seconds
Started May 02 01:34:52 PM PDT 24
Finished May 02 01:34:54 PM PDT 24
Peak memory 200692 kb
Host smart-bb7751fc-57ef-411d-940d-3a91da7dcf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660528240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.660528240
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1989715747
Short name T433
Test name
Test status
Simulation time 1614369416 ps
CPU time 6.13 seconds
Started May 02 01:34:53 PM PDT 24
Finished May 02 01:35:00 PM PDT 24
Peak memory 201028 kb
Host smart-ed2ae3d9-7737-4557-bbd5-b154378d5c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989715747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1989715747
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3296339683
Short name T427
Test name
Test status
Simulation time 144208377 ps
CPU time 1.05 seconds
Started May 02 01:34:53 PM PDT 24
Finished May 02 01:34:55 PM PDT 24
Peak memory 200840 kb
Host smart-562eece3-c7bb-4e9e-ab19-5e226d889a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296339683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3296339683
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2412488700
Short name T348
Test name
Test status
Simulation time 119948986 ps
CPU time 1.26 seconds
Started May 02 01:34:53 PM PDT 24
Finished May 02 01:34:55 PM PDT 24
Peak memory 201056 kb
Host smart-f55126d7-c168-4b59-ab6f-1326da0a117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412488700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2412488700
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.801431448
Short name T304
Test name
Test status
Simulation time 10277285370 ps
CPU time 34.08 seconds
Started May 02 01:34:55 PM PDT 24
Finished May 02 01:35:30 PM PDT 24
Peak memory 201164 kb
Host smart-5124e2c1-16ba-477a-8fa1-f093bbae93b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801431448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.801431448
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1042132069
Short name T175
Test name
Test status
Simulation time 340243580 ps
CPU time 2.27 seconds
Started May 02 01:34:52 PM PDT 24
Finished May 02 01:34:55 PM PDT 24
Peak memory 200892 kb
Host smart-f1cabfce-0b82-4492-a030-313b9846b984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042132069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1042132069
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2489899210
Short name T162
Test name
Test status
Simulation time 243148241 ps
CPU time 1.23 seconds
Started May 02 01:34:52 PM PDT 24
Finished May 02 01:34:54 PM PDT 24
Peak memory 200852 kb
Host smart-1ef90ed8-b0e1-4c00-a37d-65827e77a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489899210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2489899210
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.4071396882
Short name T261
Test name
Test status
Simulation time 72572318 ps
CPU time 0.77 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:02 PM PDT 24
Peak memory 200628 kb
Host smart-b8a20c89-972d-4f10-bad7-3defba52c9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071396882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4071396882
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.366116835
Short name T32
Test name
Test status
Simulation time 2342839006 ps
CPU time 8.31 seconds
Started May 02 01:35:01 PM PDT 24
Finished May 02 01:35:11 PM PDT 24
Peak memory 218360 kb
Host smart-5efc5c42-6fc8-42dd-a8bc-11633f3639ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366116835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.366116835
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.855427563
Short name T506
Test name
Test status
Simulation time 244194674 ps
CPU time 1.2 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:02 PM PDT 24
Peak memory 218120 kb
Host smart-083bc912-847c-4faa-910e-46cdf5cd110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855427563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.855427563
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2828616832
Short name T18
Test name
Test status
Simulation time 192702170 ps
CPU time 0.89 seconds
Started May 02 01:34:59 PM PDT 24
Finished May 02 01:35:01 PM PDT 24
Peak memory 200664 kb
Host smart-8d6d0401-b33e-4f07-b46b-d3b040e69b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828616832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2828616832
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1642530656
Short name T86
Test name
Test status
Simulation time 796286816 ps
CPU time 4.62 seconds
Started May 02 01:35:02 PM PDT 24
Finished May 02 01:35:08 PM PDT 24
Peak memory 201096 kb
Host smart-86f4a9a5-92fd-4a92-8d51-305aeb3781b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642530656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1642530656
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3312959380
Short name T333
Test name
Test status
Simulation time 147656569 ps
CPU time 1.07 seconds
Started May 02 01:34:58 PM PDT 24
Finished May 02 01:35:00 PM PDT 24
Peak memory 200828 kb
Host smart-976033b6-d2c1-4db3-8f9a-9501421a561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312959380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3312959380
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3354257013
Short name T498
Test name
Test status
Simulation time 116531728 ps
CPU time 1.21 seconds
Started May 02 01:35:01 PM PDT 24
Finished May 02 01:35:04 PM PDT 24
Peak memory 200960 kb
Host smart-7de5e5cc-7005-4df6-a295-044d345f6669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354257013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3354257013
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3498525101
Short name T285
Test name
Test status
Simulation time 8850554440 ps
CPU time 27.95 seconds
Started May 02 01:35:03 PM PDT 24
Finished May 02 01:35:32 PM PDT 24
Peak memory 201172 kb
Host smart-a3e121e7-1eac-4dba-91e3-d040b5f209cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498525101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3498525101
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.934320059
Short name T281
Test name
Test status
Simulation time 248198718 ps
CPU time 1.75 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:03 PM PDT 24
Peak memory 200872 kb
Host smart-49f42ad2-9481-4ca0-828a-fd6ffe7ee5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934320059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.934320059
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.372997717
Short name T347
Test name
Test status
Simulation time 205159240 ps
CPU time 1.27 seconds
Started May 02 01:34:59 PM PDT 24
Finished May 02 01:35:02 PM PDT 24
Peak memory 200936 kb
Host smart-98ec5b07-355a-4798-a08b-0d8ffca30757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372997717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.372997717
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2464855477
Short name T142
Test name
Test status
Simulation time 67405276 ps
CPU time 0.74 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:02 PM PDT 24
Peak memory 200668 kb
Host smart-de1cca2b-d494-408d-8593-2bb2e027a439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464855477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2464855477
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1645807724
Short name T344
Test name
Test status
Simulation time 1907626315 ps
CPU time 7.01 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:08 PM PDT 24
Peak memory 217696 kb
Host smart-88541064-0beb-455d-9bfe-7f35e70a6614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645807724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1645807724
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.717467851
Short name T450
Test name
Test status
Simulation time 244358737 ps
CPU time 1.04 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:02 PM PDT 24
Peak memory 218040 kb
Host smart-092d7776-0cbe-4bea-995c-6ff7d661265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717467851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.717467851
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2058507842
Short name T323
Test name
Test status
Simulation time 199663933 ps
CPU time 0.9 seconds
Started May 02 01:35:06 PM PDT 24
Finished May 02 01:35:08 PM PDT 24
Peak memory 200708 kb
Host smart-c221c6b0-ddc6-460f-a344-3e62a7342102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058507842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2058507842
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.937345600
Short name T522
Test name
Test status
Simulation time 1803374909 ps
CPU time 6.38 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:07 PM PDT 24
Peak memory 200992 kb
Host smart-ddf143fe-548d-4fd7-bc19-a7afc29e5d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937345600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.937345600
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1936462157
Short name T265
Test name
Test status
Simulation time 177243348 ps
CPU time 1.2 seconds
Started May 02 01:35:03 PM PDT 24
Finished May 02 01:35:05 PM PDT 24
Peak memory 200848 kb
Host smart-0694d998-d2b3-4392-9735-cc9ec5aa49dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936462157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1936462157
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1556009099
Short name T407
Test name
Test status
Simulation time 257031251 ps
CPU time 1.63 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:03 PM PDT 24
Peak memory 201048 kb
Host smart-856dae78-06c7-4ce6-9ee1-32bde062552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556009099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1556009099
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3614174083
Short name T378
Test name
Test status
Simulation time 8807275545 ps
CPU time 32.78 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:34 PM PDT 24
Peak memory 201140 kb
Host smart-dd310c00-9008-48bb-8b6b-2fb8a20cb14f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614174083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3614174083
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3840369839
Short name T96
Test name
Test status
Simulation time 516195212 ps
CPU time 2.82 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:04 PM PDT 24
Peak memory 200892 kb
Host smart-c101fd9a-8697-4b46-94a6-c550ad2d253f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840369839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3840369839
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2868863187
Short name T315
Test name
Test status
Simulation time 75815584 ps
CPU time 0.87 seconds
Started May 02 01:35:02 PM PDT 24
Finished May 02 01:35:04 PM PDT 24
Peak memory 200848 kb
Host smart-b81bf948-c6b6-4d96-90a4-8cebba392c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868863187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2868863187
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1210471517
Short name T185
Test name
Test status
Simulation time 70242202 ps
CPU time 0.75 seconds
Started May 02 01:35:13 PM PDT 24
Finished May 02 01:35:15 PM PDT 24
Peak memory 200676 kb
Host smart-6141c1bd-c961-45d7-990c-7ef0b84426c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210471517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1210471517
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.616634321
Short name T343
Test name
Test status
Simulation time 2348930573 ps
CPU time 8.23 seconds
Started May 02 01:34:59 PM PDT 24
Finished May 02 01:35:08 PM PDT 24
Peak memory 222804 kb
Host smart-f1a2b948-bf55-4ea1-9b04-7ba223b0e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616634321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.616634321
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2616611520
Short name T477
Test name
Test status
Simulation time 244654869 ps
CPU time 1.15 seconds
Started May 02 01:35:00 PM PDT 24
Finished May 02 01:35:02 PM PDT 24
Peak memory 218060 kb
Host smart-dd7718b8-58e9-4312-ada7-a52e017fb575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616611520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2616611520
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4117152143
Short name T309
Test name
Test status
Simulation time 231905204 ps
CPU time 0.93 seconds
Started May 02 01:35:02 PM PDT 24
Finished May 02 01:35:04 PM PDT 24
Peak memory 200628 kb
Host smart-f918a9af-20f2-4208-941a-1ca23557a74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117152143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4117152143
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2627409608
Short name T493
Test name
Test status
Simulation time 913331766 ps
CPU time 4.33 seconds
Started May 02 01:35:03 PM PDT 24
Finished May 02 01:35:08 PM PDT 24
Peak memory 201040 kb
Host smart-5c2ae229-fd0e-4533-b6c8-98a8da22e4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627409608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2627409608
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3243789941
Short name T258
Test name
Test status
Simulation time 183499198 ps
CPU time 1.23 seconds
Started May 02 01:35:01 PM PDT 24
Finished May 02 01:35:04 PM PDT 24
Peak memory 200884 kb
Host smart-592d7cd1-6b7a-4b93-bc3e-5ea7e6be2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243789941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3243789941
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2261895567
Short name T539
Test name
Test status
Simulation time 108404573 ps
CPU time 1.22 seconds
Started May 02 01:35:01 PM PDT 24
Finished May 02 01:35:03 PM PDT 24
Peak memory 201068 kb
Host smart-d301c71a-effb-4344-ace7-10c056fb4388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261895567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2261895567
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3363153252
Short name T6
Test name
Test status
Simulation time 203166720 ps
CPU time 1.13 seconds
Started May 02 01:35:12 PM PDT 24
Finished May 02 01:35:14 PM PDT 24
Peak memory 200856 kb
Host smart-91a275b8-c0c5-4728-b4d8-57e47106922e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363153252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3363153252
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2374698889
Short name T287
Test name
Test status
Simulation time 390446786 ps
CPU time 2.27 seconds
Started May 02 01:35:02 PM PDT 24
Finished May 02 01:35:05 PM PDT 24
Peak memory 200836 kb
Host smart-c7f3dff9-068e-459e-a15f-46182482ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374698889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2374698889
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2650720712
Short name T208
Test name
Test status
Simulation time 150907313 ps
CPU time 1.23 seconds
Started May 02 01:34:59 PM PDT 24
Finished May 02 01:35:02 PM PDT 24
Peak memory 201052 kb
Host smart-2350ac9c-e2c7-4cec-be18-0fda352d69bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650720712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2650720712
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3206360100
Short name T201
Test name
Test status
Simulation time 79073864 ps
CPU time 0.79 seconds
Started May 02 01:35:13 PM PDT 24
Finished May 02 01:35:15 PM PDT 24
Peak memory 200644 kb
Host smart-0832071d-cce2-468f-b536-7615e549f20a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206360100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3206360100
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1276329644
Short name T359
Test name
Test status
Simulation time 1225046316 ps
CPU time 5.47 seconds
Started May 02 01:35:17 PM PDT 24
Finished May 02 01:35:24 PM PDT 24
Peak memory 218628 kb
Host smart-f886f82e-31c9-48d4-90e5-c83efe1c2047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276329644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1276329644
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.725651620
Short name T494
Test name
Test status
Simulation time 243868253 ps
CPU time 1.04 seconds
Started May 02 01:35:13 PM PDT 24
Finished May 02 01:35:15 PM PDT 24
Peak memory 218068 kb
Host smart-fe53f2c6-6fa1-4820-9b60-236e0654b179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725651620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.725651620
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.555992104
Short name T328
Test name
Test status
Simulation time 78701785 ps
CPU time 0.73 seconds
Started May 02 01:35:15 PM PDT 24
Finished May 02 01:35:16 PM PDT 24
Peak memory 200688 kb
Host smart-1b1e0d87-7a8e-47d3-9232-d0291db59ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555992104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.555992104
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.909215474
Short name T109
Test name
Test status
Simulation time 803497637 ps
CPU time 3.92 seconds
Started May 02 01:35:14 PM PDT 24
Finished May 02 01:35:19 PM PDT 24
Peak memory 201072 kb
Host smart-e35e0162-6095-447c-8ad5-5b41f5e6c993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909215474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.909215474
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2760606053
Short name T284
Test name
Test status
Simulation time 167403674 ps
CPU time 1.15 seconds
Started May 02 01:35:14 PM PDT 24
Finished May 02 01:35:16 PM PDT 24
Peak memory 200840 kb
Host smart-554b1f99-636b-463c-aec8-be5a6c593c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760606053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2760606053
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1807872781
Short name T150
Test name
Test status
Simulation time 204689579 ps
CPU time 1.32 seconds
Started May 02 01:35:15 PM PDT 24
Finished May 02 01:35:18 PM PDT 24
Peak memory 201096 kb
Host smart-f4592435-53b9-427b-9332-4f26736928e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807872781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1807872781
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.271915630
Short name T214
Test name
Test status
Simulation time 6115696518 ps
CPU time 23.18 seconds
Started May 02 01:35:16 PM PDT 24
Finished May 02 01:35:41 PM PDT 24
Peak memory 201184 kb
Host smart-ad04d78a-3e5f-4dd7-b68d-a6da16d5505b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271915630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.271915630
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1497747237
Short name T474
Test name
Test status
Simulation time 147939163 ps
CPU time 1.74 seconds
Started May 02 01:35:14 PM PDT 24
Finished May 02 01:35:17 PM PDT 24
Peak memory 200884 kb
Host smart-6e0a0cf4-069d-449b-836f-9b9705428ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497747237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1497747237
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3976805954
Short name T446
Test name
Test status
Simulation time 163703495 ps
CPU time 1.21 seconds
Started May 02 01:35:15 PM PDT 24
Finished May 02 01:35:18 PM PDT 24
Peak memory 201092 kb
Host smart-35fb6929-6f22-486d-b91c-a299c8b9c24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976805954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3976805954
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2170044751
Short name T219
Test name
Test status
Simulation time 80615086 ps
CPU time 0.82 seconds
Started May 02 01:33:27 PM PDT 24
Finished May 02 01:33:29 PM PDT 24
Peak memory 200696 kb
Host smart-c61bfcc1-fff1-4733-a86d-15aa3611ba3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170044751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2170044751
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3970656317
Short name T55
Test name
Test status
Simulation time 1917088802 ps
CPU time 6.77 seconds
Started May 02 01:33:23 PM PDT 24
Finished May 02 01:33:31 PM PDT 24
Peak memory 218000 kb
Host smart-883fef70-11cc-446a-ba73-3f30713ed4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970656317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3970656317
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.4044752881
Short name T10
Test name
Test status
Simulation time 244663365 ps
CPU time 1.05 seconds
Started May 02 01:33:26 PM PDT 24
Finished May 02 01:33:28 PM PDT 24
Peak memory 218068 kb
Host smart-f6d46996-dd76-4c5b-9208-b9d4eb075b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044752881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.4044752881
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3629395004
Short name T299
Test name
Test status
Simulation time 123693841 ps
CPU time 0.78 seconds
Started May 02 01:33:16 PM PDT 24
Finished May 02 01:33:18 PM PDT 24
Peak memory 200692 kb
Host smart-67d194ee-add0-4aaf-8ace-1858e00917b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629395004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3629395004
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.139394654
Short name T441
Test name
Test status
Simulation time 2021597734 ps
CPU time 7.7 seconds
Started May 02 01:33:24 PM PDT 24
Finished May 02 01:33:33 PM PDT 24
Peak memory 201100 kb
Host smart-9ca9d7ec-cdcd-450c-b8a9-b62ae2e0becd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139394654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.139394654
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1359412420
Short name T66
Test name
Test status
Simulation time 16521585710 ps
CPU time 29.75 seconds
Started May 02 01:33:26 PM PDT 24
Finished May 02 01:33:57 PM PDT 24
Peak memory 218076 kb
Host smart-319576f2-3b1a-4a8f-aeb0-ed076b319a9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359412420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1359412420
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3638966040
Short name T256
Test name
Test status
Simulation time 108448343 ps
CPU time 1 seconds
Started May 02 01:33:27 PM PDT 24
Finished May 02 01:33:28 PM PDT 24
Peak memory 200804 kb
Host smart-609f2c6f-711c-4b10-b282-383591d662f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638966040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3638966040
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.694132361
Short name T374
Test name
Test status
Simulation time 122402346 ps
CPU time 1.27 seconds
Started May 02 01:33:16 PM PDT 24
Finished May 02 01:33:18 PM PDT 24
Peak memory 201016 kb
Host smart-21a39a97-75ed-41df-9cba-9f9048f54f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694132361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.694132361
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1437295492
Short name T168
Test name
Test status
Simulation time 482698060 ps
CPU time 2.61 seconds
Started May 02 01:33:26 PM PDT 24
Finished May 02 01:33:30 PM PDT 24
Peak memory 201076 kb
Host smart-7b926774-9340-4d42-bf04-c1718f9ff82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437295492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1437295492
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2207893649
Short name T173
Test name
Test status
Simulation time 449532751 ps
CPU time 2.36 seconds
Started May 02 01:33:25 PM PDT 24
Finished May 02 01:33:28 PM PDT 24
Peak memory 200836 kb
Host smart-92b5536d-7654-4385-9a32-8adfe886d291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207893649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2207893649
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2891477860
Short name T139
Test name
Test status
Simulation time 86581587 ps
CPU time 0.84 seconds
Started May 02 01:33:23 PM PDT 24
Finished May 02 01:33:25 PM PDT 24
Peak memory 200840 kb
Host smart-efe10cc3-458f-4eff-9422-28c5520572a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891477860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2891477860
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1351564527
Short name T152
Test name
Test status
Simulation time 58485412 ps
CPU time 0.72 seconds
Started May 02 01:35:20 PM PDT 24
Finished May 02 01:35:22 PM PDT 24
Peak memory 200700 kb
Host smart-347b6770-c8a6-43eb-a1c1-c227bd9d2176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351564527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1351564527
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1906489955
Short name T31
Test name
Test status
Simulation time 1227243169 ps
CPU time 5.36 seconds
Started May 02 01:35:12 PM PDT 24
Finished May 02 01:35:19 PM PDT 24
Peak memory 218560 kb
Host smart-fcaef8fb-0fa7-42a4-9fbd-40705ac4cb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906489955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1906489955
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3710692258
Short name T233
Test name
Test status
Simulation time 243614366 ps
CPU time 1.09 seconds
Started May 02 01:35:14 PM PDT 24
Finished May 02 01:35:16 PM PDT 24
Peak memory 218236 kb
Host smart-680cea12-ac29-4dea-a68a-b8d4568c5689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710692258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3710692258
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3477468208
Short name T502
Test name
Test status
Simulation time 127076491 ps
CPU time 0.81 seconds
Started May 02 01:35:11 PM PDT 24
Finished May 02 01:35:13 PM PDT 24
Peak memory 200656 kb
Host smart-ebe7ac47-ab04-4513-81e6-ce9547202194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477468208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3477468208
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.4038360793
Short name T51
Test name
Test status
Simulation time 794502334 ps
CPU time 4.12 seconds
Started May 02 01:35:12 PM PDT 24
Finished May 02 01:35:18 PM PDT 24
Peak memory 201060 kb
Host smart-b6c1fcc5-d1ce-4ae6-ba95-cbc5a8589d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038360793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4038360793
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1360628253
Short name T372
Test name
Test status
Simulation time 145611077 ps
CPU time 1.09 seconds
Started May 02 01:35:13 PM PDT 24
Finished May 02 01:35:15 PM PDT 24
Peak memory 200900 kb
Host smart-ecf346a9-eaac-4aed-af7b-f4fff78ec13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360628253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1360628253
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3783693033
Short name T537
Test name
Test status
Simulation time 194621739 ps
CPU time 1.43 seconds
Started May 02 01:35:15 PM PDT 24
Finished May 02 01:35:17 PM PDT 24
Peak memory 201020 kb
Host smart-b2830b01-a4ea-4849-93a0-4d0038631222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783693033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3783693033
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2803422002
Short name T95
Test name
Test status
Simulation time 3608315357 ps
CPU time 13.15 seconds
Started May 02 01:35:17 PM PDT 24
Finished May 02 01:35:32 PM PDT 24
Peak memory 201176 kb
Host smart-93ba298b-48fc-4b8c-aebc-50f3ba6c8bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803422002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2803422002
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3263695105
Short name T216
Test name
Test status
Simulation time 429957979 ps
CPU time 2.32 seconds
Started May 02 01:35:13 PM PDT 24
Finished May 02 01:35:16 PM PDT 24
Peak memory 209056 kb
Host smart-64f4d694-3f78-451b-adab-29aba8317fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263695105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3263695105
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.651308520
Short name T504
Test name
Test status
Simulation time 237040589 ps
CPU time 1.68 seconds
Started May 02 01:35:13 PM PDT 24
Finished May 02 01:35:16 PM PDT 24
Peak memory 201056 kb
Host smart-b33f27f7-7c13-48fd-999c-92f9a96b1aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651308520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.651308520
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2286890671
Short name T23
Test name
Test status
Simulation time 102444975 ps
CPU time 0.84 seconds
Started May 02 01:35:17 PM PDT 24
Finished May 02 01:35:20 PM PDT 24
Peak memory 200728 kb
Host smart-4f2b076c-9efe-4637-b01b-fc05796e6956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286890671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2286890671
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3018904252
Short name T37
Test name
Test status
Simulation time 1900328234 ps
CPU time 7.52 seconds
Started May 02 01:35:15 PM PDT 24
Finished May 02 01:35:24 PM PDT 24
Peak memory 218560 kb
Host smart-f4b950b8-9361-4bda-b94f-6caaf9de3a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018904252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3018904252
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3659339035
Short name T355
Test name
Test status
Simulation time 245904074 ps
CPU time 1.1 seconds
Started May 02 01:35:20 PM PDT 24
Finished May 02 01:35:22 PM PDT 24
Peak memory 218168 kb
Host smart-84ee99c5-6b7d-47df-98f2-1f80d894682f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659339035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3659339035
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3232103565
Short name T473
Test name
Test status
Simulation time 187280313 ps
CPU time 0.85 seconds
Started May 02 01:35:17 PM PDT 24
Finished May 02 01:35:19 PM PDT 24
Peak memory 200684 kb
Host smart-e346b377-ecb6-461d-9bfc-e34c4e9cdd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232103565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3232103565
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.455090658
Short name T291
Test name
Test status
Simulation time 1031830196 ps
CPU time 5.03 seconds
Started May 02 01:35:17 PM PDT 24
Finished May 02 01:35:24 PM PDT 24
Peak memory 201080 kb
Host smart-8e589cc6-487f-481b-b94f-e31974cb5c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455090658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.455090658
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.539736598
Short name T199
Test name
Test status
Simulation time 113149545 ps
CPU time 1.01 seconds
Started May 02 01:35:21 PM PDT 24
Finished May 02 01:35:23 PM PDT 24
Peak memory 200876 kb
Host smart-a1789ab0-a0e5-4155-9d05-ccbee2aedd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539736598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.539736598
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.4255078492
Short name T385
Test name
Test status
Simulation time 194162387 ps
CPU time 1.34 seconds
Started May 02 01:35:19 PM PDT 24
Finished May 02 01:35:21 PM PDT 24
Peak memory 201008 kb
Host smart-02b72510-45b9-41d1-a52f-45c82ddaad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255078492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.4255078492
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2660523699
Short name T194
Test name
Test status
Simulation time 7999311665 ps
CPU time 30.4 seconds
Started May 02 01:35:22 PM PDT 24
Finished May 02 01:35:53 PM PDT 24
Peak memory 201256 kb
Host smart-15896c3a-3cb9-4e62-9385-d345c31e0dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660523699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2660523699
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.539360763
Short name T303
Test name
Test status
Simulation time 127897323 ps
CPU time 1.7 seconds
Started May 02 01:35:15 PM PDT 24
Finished May 02 01:35:18 PM PDT 24
Peak memory 200844 kb
Host smart-3f983194-8423-4a25-98ce-bafffcab3f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539360763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.539360763
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2631436429
Short name T235
Test name
Test status
Simulation time 125317726 ps
CPU time 0.97 seconds
Started May 02 01:35:15 PM PDT 24
Finished May 02 01:35:17 PM PDT 24
Peak memory 200804 kb
Host smart-9c6a6272-a72a-4296-9436-bf37498c59b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631436429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2631436429
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.274253580
Short name T251
Test name
Test status
Simulation time 66574871 ps
CPU time 0.75 seconds
Started May 02 01:35:16 PM PDT 24
Finished May 02 01:35:18 PM PDT 24
Peak memory 200664 kb
Host smart-c4a61f9c-02ad-448e-9973-ec8f1a2d858a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274253580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.274253580
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.7745406
Short name T434
Test name
Test status
Simulation time 1226084955 ps
CPU time 5.5 seconds
Started May 02 01:35:21 PM PDT 24
Finished May 02 01:35:28 PM PDT 24
Peak memory 222592 kb
Host smart-8ddec832-c59e-4b7c-bd96-558b22912255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7745406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.7745406
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4132799395
Short name T318
Test name
Test status
Simulation time 244742468 ps
CPU time 1.06 seconds
Started May 02 01:35:20 PM PDT 24
Finished May 02 01:35:23 PM PDT 24
Peak memory 217984 kb
Host smart-1546f575-efe0-4494-9cce-b5ab226d7f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132799395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4132799395
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2335286056
Short name T484
Test name
Test status
Simulation time 177830370 ps
CPU time 0.84 seconds
Started May 02 01:35:19 PM PDT 24
Finished May 02 01:35:21 PM PDT 24
Peak memory 200584 kb
Host smart-38d8307b-a128-48d4-919e-43c62aeb76f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335286056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2335286056
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.4120220923
Short name T452
Test name
Test status
Simulation time 1536162675 ps
CPU time 5.41 seconds
Started May 02 01:35:18 PM PDT 24
Finished May 02 01:35:25 PM PDT 24
Peak memory 201108 kb
Host smart-9c133355-1d9a-4e29-8195-2c2d786e9ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120220923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.4120220923
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.390798284
Short name T176
Test name
Test status
Simulation time 166161173 ps
CPU time 1.2 seconds
Started May 02 01:35:18 PM PDT 24
Finished May 02 01:35:21 PM PDT 24
Peak memory 200900 kb
Host smart-e6775b3f-66f6-4c88-9175-4d62d78ac672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390798284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.390798284
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.4256911550
Short name T12
Test name
Test status
Simulation time 112156117 ps
CPU time 1.18 seconds
Started May 02 01:35:18 PM PDT 24
Finished May 02 01:35:21 PM PDT 24
Peak memory 201012 kb
Host smart-7aafc1fe-5cb4-475b-b497-dc1c8ac91962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256911550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.4256911550
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.550395329
Short name T334
Test name
Test status
Simulation time 7189124567 ps
CPU time 25.05 seconds
Started May 02 01:35:17 PM PDT 24
Finished May 02 01:35:44 PM PDT 24
Peak memory 210196 kb
Host smart-558da0a9-6e78-4876-b3e3-143d4ee1989a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550395329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.550395329
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.211375509
Short name T151
Test name
Test status
Simulation time 289235819 ps
CPU time 1.96 seconds
Started May 02 01:35:16 PM PDT 24
Finished May 02 01:35:19 PM PDT 24
Peak memory 209108 kb
Host smart-90226d9d-5956-4c6e-b55c-34c5aa802e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211375509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.211375509
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1353004879
Short name T190
Test name
Test status
Simulation time 153783118 ps
CPU time 1.12 seconds
Started May 02 01:35:17 PM PDT 24
Finished May 02 01:35:20 PM PDT 24
Peak memory 200852 kb
Host smart-0c159abe-ca4e-4efe-a862-bbf934f3eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353004879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1353004879
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.644760515
Short name T321
Test name
Test status
Simulation time 74616848 ps
CPU time 0.78 seconds
Started May 02 01:35:23 PM PDT 24
Finished May 02 01:35:25 PM PDT 24
Peak memory 200604 kb
Host smart-3fd7f342-20c6-494c-8a8e-69b5dc075a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644760515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.644760515
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3606796830
Short name T352
Test name
Test status
Simulation time 1902345250 ps
CPU time 6.77 seconds
Started May 02 01:35:20 PM PDT 24
Finished May 02 01:35:28 PM PDT 24
Peak memory 218476 kb
Host smart-d09fe351-e983-4fd7-a040-eb3a5cc25254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606796830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3606796830
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3446243097
Short name T300
Test name
Test status
Simulation time 243983833 ps
CPU time 1.16 seconds
Started May 02 01:35:25 PM PDT 24
Finished May 02 01:35:27 PM PDT 24
Peak memory 218284 kb
Host smart-99eee40e-4675-43b5-80d1-00b20f003d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446243097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3446243097
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.981397692
Short name T22
Test name
Test status
Simulation time 163903372 ps
CPU time 0.86 seconds
Started May 02 01:35:17 PM PDT 24
Finished May 02 01:35:19 PM PDT 24
Peak memory 200700 kb
Host smart-3e588097-ce56-4f93-8ca9-298c1d397ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981397692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.981397692
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.940396990
Short name T411
Test name
Test status
Simulation time 1859286118 ps
CPU time 7.62 seconds
Started May 02 01:35:21 PM PDT 24
Finished May 02 01:35:30 PM PDT 24
Peak memory 201100 kb
Host smart-57f44cb4-e1fb-49c7-880b-f05445110f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940396990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.940396990
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3114834402
Short name T279
Test name
Test status
Simulation time 160164510 ps
CPU time 1.15 seconds
Started May 02 01:35:17 PM PDT 24
Finished May 02 01:35:20 PM PDT 24
Peak memory 200840 kb
Host smart-b35640f6-9d43-48b8-a6b5-2e90cca7f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114834402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3114834402
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2984016330
Short name T368
Test name
Test status
Simulation time 116735615 ps
CPU time 1.22 seconds
Started May 02 01:35:20 PM PDT 24
Finished May 02 01:35:23 PM PDT 24
Peak memory 201052 kb
Host smart-2b5b9d31-89b3-4a63-a0ab-d25dc3448995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984016330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2984016330
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2707112073
Short name T501
Test name
Test status
Simulation time 2495554831 ps
CPU time 10.95 seconds
Started May 02 01:35:24 PM PDT 24
Finished May 02 01:35:36 PM PDT 24
Peak memory 201348 kb
Host smart-3e668dd1-f7ba-4783-b8b2-1155df46957a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707112073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2707112073
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.961910482
Short name T228
Test name
Test status
Simulation time 407527394 ps
CPU time 2.11 seconds
Started May 02 01:35:22 PM PDT 24
Finished May 02 01:35:25 PM PDT 24
Peak memory 200900 kb
Host smart-14b94b6c-9598-4b32-8937-b86670966187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961910482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.961910482
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3258597199
Short name T329
Test name
Test status
Simulation time 86496628 ps
CPU time 0.89 seconds
Started May 02 01:35:21 PM PDT 24
Finished May 02 01:35:23 PM PDT 24
Peak memory 200868 kb
Host smart-9924e334-e60f-4f44-8d98-b00cc915908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258597199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3258597199
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1512777638
Short name T132
Test name
Test status
Simulation time 62855662 ps
CPU time 0.73 seconds
Started May 02 01:35:32 PM PDT 24
Finished May 02 01:35:34 PM PDT 24
Peak memory 200648 kb
Host smart-064ba9a1-d636-4c7a-a358-134d8420d85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512777638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1512777638
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.305967265
Short name T36
Test name
Test status
Simulation time 2354133578 ps
CPU time 8.12 seconds
Started May 02 01:35:22 PM PDT 24
Finished May 02 01:35:32 PM PDT 24
Peak memory 222752 kb
Host smart-6d9a0b3c-4934-4425-95d3-61d1d0082588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305967265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.305967265
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1414780403
Short name T482
Test name
Test status
Simulation time 244652967 ps
CPU time 1.1 seconds
Started May 02 01:35:33 PM PDT 24
Finished May 02 01:35:36 PM PDT 24
Peak memory 218020 kb
Host smart-ead7ad12-c967-4195-bfa3-6c68fbbb3f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414780403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1414780403
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3511610784
Short name T358
Test name
Test status
Simulation time 182872357 ps
CPU time 0.9 seconds
Started May 02 01:35:22 PM PDT 24
Finished May 02 01:35:24 PM PDT 24
Peak memory 200624 kb
Host smart-43c3b151-7ae2-403b-8f1c-bb0ff7d755dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511610784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3511610784
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2222040930
Short name T294
Test name
Test status
Simulation time 2104089259 ps
CPU time 8.34 seconds
Started May 02 01:35:32 PM PDT 24
Finished May 02 01:35:43 PM PDT 24
Peak memory 201012 kb
Host smart-70dc7025-0ee2-4bf6-b7a3-894dd39f4400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222040930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2222040930
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1777944118
Short name T135
Test name
Test status
Simulation time 107165037 ps
CPU time 1 seconds
Started May 02 01:35:33 PM PDT 24
Finished May 02 01:35:35 PM PDT 24
Peak memory 200828 kb
Host smart-dff7591e-267f-4862-8145-771bb6983c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777944118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1777944118
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1695591696
Short name T335
Test name
Test status
Simulation time 120119973 ps
CPU time 1.16 seconds
Started May 02 01:35:25 PM PDT 24
Finished May 02 01:35:27 PM PDT 24
Peak memory 201024 kb
Host smart-72274621-5f6e-4152-8771-c16f3fb9bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695591696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1695591696
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3995184563
Short name T166
Test name
Test status
Simulation time 146447723 ps
CPU time 1.02 seconds
Started May 02 01:35:23 PM PDT 24
Finished May 02 01:35:26 PM PDT 24
Peak memory 200920 kb
Host smart-87f433b6-d590-47bf-ac6a-12ccfef30a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995184563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3995184563
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3404433426
Short name T302
Test name
Test status
Simulation time 150785461 ps
CPU time 1.84 seconds
Started May 02 01:35:23 PM PDT 24
Finished May 02 01:35:26 PM PDT 24
Peak memory 200840 kb
Host smart-8090135c-a005-4fd5-9dfa-ed6c1d950e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404433426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3404433426
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2893017289
Short name T401
Test name
Test status
Simulation time 83109120 ps
CPU time 0.89 seconds
Started May 02 01:35:33 PM PDT 24
Finished May 02 01:35:35 PM PDT 24
Peak memory 200656 kb
Host smart-159cab07-fec2-4d4d-92a0-04b8bbf0ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893017289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2893017289
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2556254580
Short name T70
Test name
Test status
Simulation time 78149967 ps
CPU time 0.82 seconds
Started May 02 01:35:31 PM PDT 24
Finished May 02 01:35:33 PM PDT 24
Peak memory 200692 kb
Host smart-7540275f-2222-4514-8819-f9a29b1c0fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556254580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2556254580
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1562643767
Short name T460
Test name
Test status
Simulation time 2175378156 ps
CPU time 8.01 seconds
Started May 02 01:35:24 PM PDT 24
Finished May 02 01:35:34 PM PDT 24
Peak memory 218196 kb
Host smart-345b4650-869d-4797-9781-4299ae3c02d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562643767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1562643767
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3669799625
Short name T283
Test name
Test status
Simulation time 243863943 ps
CPU time 1.05 seconds
Started May 02 01:35:30 PM PDT 24
Finished May 02 01:35:33 PM PDT 24
Peak memory 218264 kb
Host smart-020bb886-332a-4e99-bd64-cce0d266fd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669799625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3669799625
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.478717988
Short name T11
Test name
Test status
Simulation time 89524085 ps
CPU time 0.78 seconds
Started May 02 01:35:23 PM PDT 24
Finished May 02 01:35:24 PM PDT 24
Peak memory 200708 kb
Host smart-73c475da-ed86-4539-9c27-d03120dd92bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478717988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.478717988
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3347687894
Short name T298
Test name
Test status
Simulation time 1829095509 ps
CPU time 6.8 seconds
Started May 02 01:35:33 PM PDT 24
Finished May 02 01:35:41 PM PDT 24
Peak memory 201012 kb
Host smart-22c6200c-5700-4628-9026-e0428c21472d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347687894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3347687894
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2114357007
Short name T437
Test name
Test status
Simulation time 144033861 ps
CPU time 1.12 seconds
Started May 02 01:35:25 PM PDT 24
Finished May 02 01:35:27 PM PDT 24
Peak memory 200836 kb
Host smart-c5950f56-6ad0-4b5c-b746-12f8a1f506f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114357007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2114357007
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3259248478
Short name T274
Test name
Test status
Simulation time 242401070 ps
CPU time 1.49 seconds
Started May 02 01:35:25 PM PDT 24
Finished May 02 01:35:27 PM PDT 24
Peak memory 201048 kb
Host smart-59a168eb-a4f6-42d1-8b5a-3deab41c73b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259248478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3259248478
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1022115860
Short name T269
Test name
Test status
Simulation time 1958870755 ps
CPU time 8.16 seconds
Started May 02 01:35:30 PM PDT 24
Finished May 02 01:35:39 PM PDT 24
Peak memory 209280 kb
Host smart-8beca844-6815-429d-be60-5001fee266ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022115860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1022115860
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1056511414
Short name T363
Test name
Test status
Simulation time 312649884 ps
CPU time 1.92 seconds
Started May 02 01:35:23 PM PDT 24
Finished May 02 01:35:26 PM PDT 24
Peak memory 200864 kb
Host smart-69fa9bac-02fb-4f86-a8cb-f2c167a96fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056511414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1056511414
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.108831922
Short name T350
Test name
Test status
Simulation time 146198667 ps
CPU time 1.16 seconds
Started May 02 01:35:22 PM PDT 24
Finished May 02 01:35:25 PM PDT 24
Peak memory 200908 kb
Host smart-ec37fee8-b1f2-4ce1-b622-d2d9c743fe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108831922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.108831922
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1084031115
Short name T5
Test name
Test status
Simulation time 74615925 ps
CPU time 0.78 seconds
Started May 02 01:35:30 PM PDT 24
Finished May 02 01:35:32 PM PDT 24
Peak memory 200680 kb
Host smart-cf84ffc6-f350-46f5-bdc6-04e814e5afe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084031115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1084031115
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2001942224
Short name T44
Test name
Test status
Simulation time 2376306228 ps
CPU time 8.69 seconds
Started May 02 01:35:30 PM PDT 24
Finished May 02 01:35:40 PM PDT 24
Peak memory 218460 kb
Host smart-b5934e47-7f83-47f1-899b-9c082ec3e8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001942224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2001942224
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1766666010
Short name T263
Test name
Test status
Simulation time 244035008 ps
CPU time 1.04 seconds
Started May 02 01:35:32 PM PDT 24
Finished May 02 01:35:34 PM PDT 24
Peak memory 218116 kb
Host smart-27eb07ad-8fcc-4309-8dda-4dbe53c41b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766666010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1766666010
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3522336831
Short name T15
Test name
Test status
Simulation time 131355810 ps
CPU time 0.83 seconds
Started May 02 01:35:29 PM PDT 24
Finished May 02 01:35:31 PM PDT 24
Peak memory 200648 kb
Host smart-116ca259-5fec-4d67-8fc1-2ce57d8151b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522336831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3522336831
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.397728047
Short name T404
Test name
Test status
Simulation time 1067461014 ps
CPU time 4.84 seconds
Started May 02 01:35:30 PM PDT 24
Finished May 02 01:35:36 PM PDT 24
Peak memory 201040 kb
Host smart-6c8e4e0b-d726-4374-9fce-ffa5c0f629c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397728047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.397728047
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4207914526
Short name T262
Test name
Test status
Simulation time 191742286 ps
CPU time 1.21 seconds
Started May 02 01:35:31 PM PDT 24
Finished May 02 01:35:34 PM PDT 24
Peak memory 200844 kb
Host smart-336cbd05-fb77-402f-8ae4-3707059a1084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207914526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4207914526
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1928922663
Short name T311
Test name
Test status
Simulation time 116824232 ps
CPU time 1.28 seconds
Started May 02 01:35:32 PM PDT 24
Finished May 02 01:35:35 PM PDT 24
Peak memory 201076 kb
Host smart-48977c37-e8b1-42be-a217-edc2497611b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928922663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1928922663
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.927484239
Short name T177
Test name
Test status
Simulation time 134285698 ps
CPU time 1.53 seconds
Started May 02 01:35:31 PM PDT 24
Finished May 02 01:35:34 PM PDT 24
Peak memory 209120 kb
Host smart-8920202f-0217-48a7-94a0-eae3cb555e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927484239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.927484239
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1014948175
Short name T436
Test name
Test status
Simulation time 110781980 ps
CPU time 0.97 seconds
Started May 02 01:35:47 PM PDT 24
Finished May 02 01:35:49 PM PDT 24
Peak memory 200896 kb
Host smart-bc213282-c4fa-49ff-848d-5b138f16ab18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014948175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1014948175
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1186463909
Short name T137
Test name
Test status
Simulation time 62903923 ps
CPU time 0.76 seconds
Started May 02 01:35:37 PM PDT 24
Finished May 02 01:35:39 PM PDT 24
Peak memory 200684 kb
Host smart-0e0c978b-975e-4b91-bfc5-6465add1e742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186463909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1186463909
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1986144002
Short name T54
Test name
Test status
Simulation time 1224297896 ps
CPU time 5.73 seconds
Started May 02 01:35:30 PM PDT 24
Finished May 02 01:35:37 PM PDT 24
Peak memory 222624 kb
Host smart-77d9e6f0-1a06-4783-807d-d4a85f9abc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986144002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1986144002
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2074972530
Short name T398
Test name
Test status
Simulation time 246079208 ps
CPU time 1.11 seconds
Started May 02 01:35:33 PM PDT 24
Finished May 02 01:35:36 PM PDT 24
Peak memory 218300 kb
Host smart-5b9aab82-8cd4-4221-a027-255db1ef1113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074972530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2074972530
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2928842703
Short name T342
Test name
Test status
Simulation time 193455019 ps
CPU time 0.88 seconds
Started May 02 01:35:32 PM PDT 24
Finished May 02 01:35:34 PM PDT 24
Peak memory 200684 kb
Host smart-1f689b7c-91d1-4b76-8f11-83024b4792d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928842703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2928842703
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1006119269
Short name T406
Test name
Test status
Simulation time 1763633533 ps
CPU time 7.17 seconds
Started May 02 01:35:30 PM PDT 24
Finished May 02 01:35:39 PM PDT 24
Peak memory 201040 kb
Host smart-7aabe128-733a-445e-bfdc-c655f62679fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006119269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1006119269
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.967791478
Short name T418
Test name
Test status
Simulation time 104664966 ps
CPU time 1.04 seconds
Started May 02 01:35:29 PM PDT 24
Finished May 02 01:35:31 PM PDT 24
Peak memory 200880 kb
Host smart-9624b1cc-1455-4526-a751-f6435283f619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967791478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.967791478
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.474729261
Short name T202
Test name
Test status
Simulation time 255583057 ps
CPU time 1.54 seconds
Started May 02 01:35:30 PM PDT 24
Finished May 02 01:35:32 PM PDT 24
Peak memory 201068 kb
Host smart-8f013cf5-465d-48ea-9620-265f17a09ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474729261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.474729261
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3043937567
Short name T250
Test name
Test status
Simulation time 2282800301 ps
CPU time 11.56 seconds
Started May 02 01:35:32 PM PDT 24
Finished May 02 01:35:45 PM PDT 24
Peak memory 217424 kb
Host smart-6cd1d28d-1c5d-4f4f-97b5-12ea038e7eb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043937567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3043937567
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1270196644
Short name T149
Test name
Test status
Simulation time 330245503 ps
CPU time 2.09 seconds
Started May 02 01:35:30 PM PDT 24
Finished May 02 01:35:33 PM PDT 24
Peak memory 200864 kb
Host smart-01f238e7-22c6-48b5-a6af-289620fbf63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270196644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1270196644
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.4006156758
Short name T464
Test name
Test status
Simulation time 179286551 ps
CPU time 1.26 seconds
Started May 02 01:35:33 PM PDT 24
Finished May 02 01:35:36 PM PDT 24
Peak memory 201112 kb
Host smart-fcc694c1-de49-43b4-98a0-cc33dea5aaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006156758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.4006156758
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1548599221
Short name T516
Test name
Test status
Simulation time 95494582 ps
CPU time 0.88 seconds
Started May 02 01:35:41 PM PDT 24
Finished May 02 01:35:43 PM PDT 24
Peak memory 200644 kb
Host smart-86913270-84da-4576-ac1b-c8fa112a8afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548599221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1548599221
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2868946105
Short name T247
Test name
Test status
Simulation time 1231091532 ps
CPU time 5.26 seconds
Started May 02 01:35:36 PM PDT 24
Finished May 02 01:35:43 PM PDT 24
Peak memory 217956 kb
Host smart-b0af166a-db63-44f6-a5ff-e795f094474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868946105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2868946105
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.503704923
Short name T467
Test name
Test status
Simulation time 244118579 ps
CPU time 1.18 seconds
Started May 02 01:35:40 PM PDT 24
Finished May 02 01:35:43 PM PDT 24
Peak memory 218036 kb
Host smart-128ae977-87f9-4f22-a4e1-c049bbf55d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503704923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.503704923
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3950035382
Short name T196
Test name
Test status
Simulation time 232446303 ps
CPU time 1.03 seconds
Started May 02 01:35:39 PM PDT 24
Finished May 02 01:35:41 PM PDT 24
Peak memory 200660 kb
Host smart-9407b80a-048e-4b36-bfee-082fd3b700c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950035382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3950035382
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1796905683
Short name T116
Test name
Test status
Simulation time 1427464122 ps
CPU time 5.41 seconds
Started May 02 01:35:38 PM PDT 24
Finished May 02 01:35:44 PM PDT 24
Peak memory 201096 kb
Host smart-b074b88f-2046-4d77-a585-83eb7328ddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796905683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1796905683
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2046430969
Short name T480
Test name
Test status
Simulation time 179332483 ps
CPU time 1.11 seconds
Started May 02 01:35:38 PM PDT 24
Finished May 02 01:35:40 PM PDT 24
Peak memory 200880 kb
Host smart-50b1ced6-4597-4b32-9e60-897e7e71117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046430969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2046430969
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1036878220
Short name T27
Test name
Test status
Simulation time 112781012 ps
CPU time 1.14 seconds
Started May 02 01:35:38 PM PDT 24
Finished May 02 01:35:40 PM PDT 24
Peak memory 200996 kb
Host smart-328362e5-8e56-49e8-b83b-4dd29589af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036878220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1036878220
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.346805609
Short name T461
Test name
Test status
Simulation time 3812557479 ps
CPU time 14.65 seconds
Started May 02 01:35:39 PM PDT 24
Finished May 02 01:35:55 PM PDT 24
Peak memory 209416 kb
Host smart-fcbe8617-439c-4cbe-989f-0f3825bc87ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346805609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.346805609
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2919685278
Short name T330
Test name
Test status
Simulation time 453123976 ps
CPU time 2.5 seconds
Started May 02 01:35:39 PM PDT 24
Finished May 02 01:35:42 PM PDT 24
Peak memory 200916 kb
Host smart-12bdb5a8-78a5-4717-a7eb-016d08aec929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919685278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2919685278
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.945231325
Short name T435
Test name
Test status
Simulation time 144914567 ps
CPU time 1.16 seconds
Started May 02 01:35:40 PM PDT 24
Finished May 02 01:35:43 PM PDT 24
Peak memory 200856 kb
Host smart-ee998e26-5149-4dd1-adf1-33eb918f4ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945231325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.945231325
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3451388202
Short name T346
Test name
Test status
Simulation time 80982336 ps
CPU time 0.8 seconds
Started May 02 01:35:38 PM PDT 24
Finished May 02 01:35:40 PM PDT 24
Peak memory 200708 kb
Host smart-8ca461d9-9609-4fb2-a417-1db6580ae478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451388202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3451388202
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1491092195
Short name T33
Test name
Test status
Simulation time 1896248013 ps
CPU time 7.33 seconds
Started May 02 01:35:39 PM PDT 24
Finished May 02 01:35:47 PM PDT 24
Peak memory 222664 kb
Host smart-543ca2d5-9c0e-4295-8c32-a72e8a9ac4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491092195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1491092195
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3479585116
Short name T400
Test name
Test status
Simulation time 245035918 ps
CPU time 1.1 seconds
Started May 02 01:35:39 PM PDT 24
Finished May 02 01:35:41 PM PDT 24
Peak memory 218088 kb
Host smart-03f8e98a-bd5a-44b9-9a0f-3b62cb8946e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479585116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3479585116
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1875307652
Short name T532
Test name
Test status
Simulation time 82827888 ps
CPU time 0.75 seconds
Started May 02 01:35:36 PM PDT 24
Finished May 02 01:35:38 PM PDT 24
Peak memory 200612 kb
Host smart-9e6eb938-b188-4176-9acf-884746f9823b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875307652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1875307652
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1144234073
Short name T191
Test name
Test status
Simulation time 742539610 ps
CPU time 3.66 seconds
Started May 02 01:35:37 PM PDT 24
Finished May 02 01:35:42 PM PDT 24
Peak memory 201044 kb
Host smart-0761ab13-db65-4b34-b477-7edf8ad2e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144234073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1144234073
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.4129027797
Short name T172
Test name
Test status
Simulation time 144690714 ps
CPU time 1.1 seconds
Started May 02 01:35:37 PM PDT 24
Finished May 02 01:35:39 PM PDT 24
Peak memory 200852 kb
Host smart-4b363579-3aba-4c52-a98c-a29c26489380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129027797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.4129027797
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.208454153
Short name T524
Test name
Test status
Simulation time 234330109 ps
CPU time 1.41 seconds
Started May 02 01:35:42 PM PDT 24
Finished May 02 01:35:44 PM PDT 24
Peak memory 201024 kb
Host smart-5b4f8847-3799-41e6-914e-97e835a2df4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208454153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.208454153
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.778182488
Short name T211
Test name
Test status
Simulation time 3998471939 ps
CPU time 16.91 seconds
Started May 02 01:35:37 PM PDT 24
Finished May 02 01:35:55 PM PDT 24
Peak memory 210960 kb
Host smart-a994c527-318b-4abf-bf52-f32694eb1cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778182488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.778182488
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4246905802
Short name T234
Test name
Test status
Simulation time 134610167 ps
CPU time 1.76 seconds
Started May 02 01:35:36 PM PDT 24
Finished May 02 01:35:39 PM PDT 24
Peak memory 200880 kb
Host smart-4178f091-9fbb-4f7a-9381-9f2f749dc767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246905802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4246905802
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3739128361
Short name T458
Test name
Test status
Simulation time 152698774 ps
CPU time 1.07 seconds
Started May 02 01:35:38 PM PDT 24
Finished May 02 01:35:41 PM PDT 24
Peak memory 200848 kb
Host smart-7f385007-63c1-421f-b75d-674491124a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739128361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3739128361
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1278229169
Short name T326
Test name
Test status
Simulation time 61065780 ps
CPU time 0.72 seconds
Started May 02 01:33:33 PM PDT 24
Finished May 02 01:33:35 PM PDT 24
Peak memory 200700 kb
Host smart-39050b60-159e-4e80-be87-ccaadac29728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278229169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1278229169
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2507978799
Short name T38
Test name
Test status
Simulation time 1893123906 ps
CPU time 7.58 seconds
Started May 02 01:33:23 PM PDT 24
Finished May 02 01:33:32 PM PDT 24
Peak memory 218564 kb
Host smart-ddd4d03e-c2c6-4e68-a1f0-f303f4c7e9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507978799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2507978799
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3306660809
Short name T50
Test name
Test status
Simulation time 244277114 ps
CPU time 1.15 seconds
Started May 02 01:33:42 PM PDT 24
Finished May 02 01:33:44 PM PDT 24
Peak memory 218012 kb
Host smart-df73a552-f94b-405c-a7ed-54531562a6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306660809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3306660809
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3482879086
Short name T475
Test name
Test status
Simulation time 127832813 ps
CPU time 0.8 seconds
Started May 02 01:33:28 PM PDT 24
Finished May 02 01:33:29 PM PDT 24
Peak memory 200588 kb
Host smart-870955b9-51d5-42d5-9481-2ae841e37964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482879086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3482879086
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2488127436
Short name T440
Test name
Test status
Simulation time 1876418486 ps
CPU time 7.58 seconds
Started May 02 01:33:28 PM PDT 24
Finished May 02 01:33:36 PM PDT 24
Peak memory 201004 kb
Host smart-a8cfd345-7981-4134-b8a0-12c911b7d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488127436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2488127436
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1877410118
Short name T68
Test name
Test status
Simulation time 8343677350 ps
CPU time 14.5 seconds
Started May 02 01:33:36 PM PDT 24
Finished May 02 01:33:51 PM PDT 24
Peak memory 221684 kb
Host smart-0bc1ec19-c0b2-4529-8e21-0e63586e986f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877410118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1877410118
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3838893368
Short name T292
Test name
Test status
Simulation time 153195957 ps
CPU time 1.18 seconds
Started May 02 01:33:27 PM PDT 24
Finished May 02 01:33:29 PM PDT 24
Peak memory 200920 kb
Host smart-fd4db7fc-e0f3-44f1-be49-4f499c876a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838893368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3838893368
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1377561692
Short name T479
Test name
Test status
Simulation time 248453388 ps
CPU time 1.44 seconds
Started May 02 01:33:26 PM PDT 24
Finished May 02 01:33:28 PM PDT 24
Peak memory 200972 kb
Host smart-9a146709-69f3-4499-9fc5-f915e7d692c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377561692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1377561692
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3452254115
Short name T351
Test name
Test status
Simulation time 12521763563 ps
CPU time 39.9 seconds
Started May 02 01:33:33 PM PDT 24
Finished May 02 01:34:14 PM PDT 24
Peak memory 201132 kb
Host smart-7f1e9c8f-d63d-4d12-a756-015553e79c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452254115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3452254115
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3277133716
Short name T169
Test name
Test status
Simulation time 372445498 ps
CPU time 2.37 seconds
Started May 02 01:33:24 PM PDT 24
Finished May 02 01:33:27 PM PDT 24
Peak memory 200872 kb
Host smart-d5765036-e39a-4abe-90ce-a18294adca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277133716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3277133716
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1163413407
Short name T426
Test name
Test status
Simulation time 289818852 ps
CPU time 1.48 seconds
Started May 02 01:33:24 PM PDT 24
Finished May 02 01:33:26 PM PDT 24
Peak memory 201088 kb
Host smart-d5e81c48-2adf-41a2-8ae2-13c7525f2f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163413407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1163413407
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2249615013
Short name T133
Test name
Test status
Simulation time 67486878 ps
CPU time 0.8 seconds
Started May 02 01:35:48 PM PDT 24
Finished May 02 01:35:49 PM PDT 24
Peak memory 200676 kb
Host smart-ddf2aa8b-233b-4ce9-ad24-d3bbeca18cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249615013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2249615013
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3732507461
Short name T325
Test name
Test status
Simulation time 2350767455 ps
CPU time 8.36 seconds
Started May 02 01:35:36 PM PDT 24
Finished May 02 01:35:46 PM PDT 24
Peak memory 222476 kb
Host smart-2a6d2968-0844-40d7-8b13-8170f2465ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732507461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3732507461
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1498430576
Short name T495
Test name
Test status
Simulation time 244618172 ps
CPU time 1.1 seconds
Started May 02 01:35:48 PM PDT 24
Finished May 02 01:35:50 PM PDT 24
Peak memory 218244 kb
Host smart-31179d65-150e-4f5b-91d7-dc0767792abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498430576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1498430576
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.864158472
Short name T395
Test name
Test status
Simulation time 98528294 ps
CPU time 0.74 seconds
Started May 02 01:35:37 PM PDT 24
Finished May 02 01:35:39 PM PDT 24
Peak memory 200616 kb
Host smart-ad1d1bc2-ce2f-4406-ad15-e59ccb1fea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864158472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.864158472
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.521983
Short name T324
Test name
Test status
Simulation time 1925879056 ps
CPU time 7.12 seconds
Started May 02 01:35:41 PM PDT 24
Finished May 02 01:35:49 PM PDT 24
Peak memory 201052 kb
Host smart-bfe4a187-59de-4714-9876-bcd6e0ca5121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.521983
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.330875449
Short name T313
Test name
Test status
Simulation time 150188677 ps
CPU time 1.18 seconds
Started May 02 01:35:36 PM PDT 24
Finished May 02 01:35:38 PM PDT 24
Peak memory 200884 kb
Host smart-a1c980e1-14a5-470f-8b0c-debdb821c442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330875449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.330875449
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.291028991
Short name T444
Test name
Test status
Simulation time 118112672 ps
CPU time 1.22 seconds
Started May 02 01:35:41 PM PDT 24
Finished May 02 01:35:44 PM PDT 24
Peak memory 201024 kb
Host smart-7f55e4d5-d436-4c5e-8fec-d92337495ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291028991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.291028991
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1394259467
Short name T509
Test name
Test status
Simulation time 10220953756 ps
CPU time 33.46 seconds
Started May 02 01:35:50 PM PDT 24
Finished May 02 01:36:24 PM PDT 24
Peak memory 201212 kb
Host smart-51f52940-1967-4f9e-aed5-427dcbb786a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394259467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1394259467
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3287244606
Short name T207
Test name
Test status
Simulation time 392491021 ps
CPU time 2.36 seconds
Started May 02 01:35:38 PM PDT 24
Finished May 02 01:35:42 PM PDT 24
Peak memory 200852 kb
Host smart-2e398f7a-4302-400b-91db-88552ccdf0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287244606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3287244606
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1276784840
Short name T72
Test name
Test status
Simulation time 222783114 ps
CPU time 1.33 seconds
Started May 02 01:35:39 PM PDT 24
Finished May 02 01:35:41 PM PDT 24
Peak memory 200888 kb
Host smart-a616db55-95a9-4fe2-8bfb-1119444d9d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276784840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1276784840
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1738694664
Short name T73
Test name
Test status
Simulation time 65903210 ps
CPU time 0.78 seconds
Started May 02 01:35:49 PM PDT 24
Finished May 02 01:35:51 PM PDT 24
Peak memory 200676 kb
Host smart-34391bb4-d9c8-46a8-8827-94b84cc26675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738694664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1738694664
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.909979249
Short name T7
Test name
Test status
Simulation time 1224294647 ps
CPU time 5.67 seconds
Started May 02 01:35:49 PM PDT 24
Finished May 02 01:35:56 PM PDT 24
Peak memory 222640 kb
Host smart-38acbb3a-dcc9-4593-be36-c24a1b17099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909979249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.909979249
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1100672891
Short name T138
Test name
Test status
Simulation time 245831320 ps
CPU time 1.05 seconds
Started May 02 01:35:48 PM PDT 24
Finished May 02 01:35:51 PM PDT 24
Peak memory 218060 kb
Host smart-b1f7c87f-1970-4bfd-8692-1fccf7b1f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100672891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1100672891
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.960705604
Short name T183
Test name
Test status
Simulation time 207108735 ps
CPU time 0.93 seconds
Started May 02 01:35:52 PM PDT 24
Finished May 02 01:35:53 PM PDT 24
Peak memory 200708 kb
Host smart-e6d8d91e-c474-41a2-862a-9a4c1ff98fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960705604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.960705604
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3229675449
Short name T77
Test name
Test status
Simulation time 1552505358 ps
CPU time 6.16 seconds
Started May 02 01:35:53 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 200996 kb
Host smart-3aed45d8-79b9-4f66-9c56-7ba19dfc9217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229675449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3229675449
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2612633097
Short name T48
Test name
Test status
Simulation time 152866261 ps
CPU time 1.2 seconds
Started May 02 01:35:50 PM PDT 24
Finished May 02 01:35:52 PM PDT 24
Peak memory 200888 kb
Host smart-fc1be60f-0ef5-4e87-a889-67689f886c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612633097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2612633097
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.884015277
Short name T310
Test name
Test status
Simulation time 118481493 ps
CPU time 1.16 seconds
Started May 02 01:35:48 PM PDT 24
Finished May 02 01:35:51 PM PDT 24
Peak memory 201088 kb
Host smart-0b4c34c2-38be-41e1-8cc1-0ac03b9b45ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884015277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.884015277
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.594345389
Short name T186
Test name
Test status
Simulation time 1249373304 ps
CPU time 6.49 seconds
Started May 02 01:35:49 PM PDT 24
Finished May 02 01:35:56 PM PDT 24
Peak memory 200996 kb
Host smart-6b565aa8-eb76-41f8-b053-b65371de83fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594345389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.594345389
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.585150030
Short name T56
Test name
Test status
Simulation time 155620983 ps
CPU time 1.74 seconds
Started May 02 01:35:46 PM PDT 24
Finished May 02 01:35:49 PM PDT 24
Peak memory 200840 kb
Host smart-4f2628bc-c04e-406d-a08f-5f993b5ece56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585150030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.585150030
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.46008478
Short name T249
Test name
Test status
Simulation time 101111785 ps
CPU time 0.93 seconds
Started May 02 01:35:49 PM PDT 24
Finished May 02 01:35:51 PM PDT 24
Peak memory 200892 kb
Host smart-e1b50846-a505-4854-b6a4-792916892c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46008478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.46008478
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.759098597
Short name T331
Test name
Test status
Simulation time 70028253 ps
CPU time 0.77 seconds
Started May 02 01:35:48 PM PDT 24
Finished May 02 01:35:50 PM PDT 24
Peak memory 200668 kb
Host smart-064c80d9-8024-4caf-8fe4-bb428d16219b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759098597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.759098597
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.674006448
Short name T278
Test name
Test status
Simulation time 245404701 ps
CPU time 1 seconds
Started May 02 01:35:48 PM PDT 24
Finished May 02 01:35:50 PM PDT 24
Peak memory 218084 kb
Host smart-59b4eaed-5ff8-459a-8265-513dcab37975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674006448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.674006448
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1720372937
Short name T322
Test name
Test status
Simulation time 184820853 ps
CPU time 0.87 seconds
Started May 02 01:35:48 PM PDT 24
Finished May 02 01:35:50 PM PDT 24
Peak memory 200624 kb
Host smart-b120575e-4cbc-4965-9886-67ebf0136fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720372937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1720372937
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.205025011
Short name T337
Test name
Test status
Simulation time 1384914906 ps
CPU time 5.87 seconds
Started May 02 01:35:48 PM PDT 24
Finished May 02 01:35:54 PM PDT 24
Peak memory 201112 kb
Host smart-4068cc24-dd27-4e62-8ddd-e2618a46d386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205025011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.205025011
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3868478107
Short name T536
Test name
Test status
Simulation time 167456188 ps
CPU time 1.17 seconds
Started May 02 01:35:49 PM PDT 24
Finished May 02 01:35:51 PM PDT 24
Peak memory 200772 kb
Host smart-dc808aa0-36c1-46d3-ab69-74aa5cb8a3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868478107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3868478107
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3613049624
Short name T145
Test name
Test status
Simulation time 118914277 ps
CPU time 1.2 seconds
Started May 02 01:35:47 PM PDT 24
Finished May 02 01:35:48 PM PDT 24
Peak memory 201036 kb
Host smart-59391258-62bc-478d-aaf0-30ebf05591f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613049624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3613049624
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1674993280
Short name T118
Test name
Test status
Simulation time 8706067150 ps
CPU time 28.28 seconds
Started May 02 01:35:49 PM PDT 24
Finished May 02 01:36:19 PM PDT 24
Peak memory 201224 kb
Host smart-b03578e8-22e4-44c9-a264-7f67103513f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674993280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1674993280
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1763259071
Short name T332
Test name
Test status
Simulation time 541999431 ps
CPU time 2.99 seconds
Started May 02 01:35:50 PM PDT 24
Finished May 02 01:35:54 PM PDT 24
Peak memory 200852 kb
Host smart-d8813af8-5335-4892-8920-4816cdd923e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763259071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1763259071
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3302757162
Short name T438
Test name
Test status
Simulation time 64858158 ps
CPU time 0.74 seconds
Started May 02 01:35:56 PM PDT 24
Finished May 02 01:35:58 PM PDT 24
Peak memory 200696 kb
Host smart-fe9cdc65-b218-45e6-8ce3-a81c2b127545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302757162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3302757162
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1994514398
Short name T519
Test name
Test status
Simulation time 1222037372 ps
CPU time 5.79 seconds
Started May 02 01:35:56 PM PDT 24
Finished May 02 01:36:03 PM PDT 24
Peak memory 218032 kb
Host smart-7577f3e8-4fc6-45ec-9367-674f7eb2e069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994514398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1994514398
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3404104354
Short name T462
Test name
Test status
Simulation time 243652335 ps
CPU time 1.13 seconds
Started May 02 01:35:59 PM PDT 24
Finished May 02 01:36:02 PM PDT 24
Peak memory 218120 kb
Host smart-9005fcc8-0eb5-4ccd-a4d4-5297dfc23287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404104354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3404104354
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2531169634
Short name T483
Test name
Test status
Simulation time 188652596 ps
CPU time 0.88 seconds
Started May 02 01:35:59 PM PDT 24
Finished May 02 01:36:01 PM PDT 24
Peak memory 200656 kb
Host smart-c6187aeb-8b68-4d0b-91bb-19275c904e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531169634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2531169634
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1201407388
Short name T254
Test name
Test status
Simulation time 664953912 ps
CPU time 3.85 seconds
Started May 02 01:36:00 PM PDT 24
Finished May 02 01:36:05 PM PDT 24
Peak memory 200964 kb
Host smart-7f589e03-e214-46db-a174-1e45f56bb0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201407388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1201407388
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2286614439
Short name T521
Test name
Test status
Simulation time 97656313 ps
CPU time 1.02 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:35:59 PM PDT 24
Peak memory 200824 kb
Host smart-a2006544-275b-408e-9230-09d562562c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286614439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2286614439
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2885656784
Short name T386
Test name
Test status
Simulation time 192995327 ps
CPU time 1.41 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 200996 kb
Host smart-319e6019-9ae0-45d3-b88c-d9ee9677c135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885656784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2885656784
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3543171354
Short name T252
Test name
Test status
Simulation time 8110178058 ps
CPU time 31.78 seconds
Started May 02 01:36:00 PM PDT 24
Finished May 02 01:36:33 PM PDT 24
Peak memory 209476 kb
Host smart-2c446596-78af-4715-9920-305611661a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543171354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3543171354
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2294886069
Short name T143
Test name
Test status
Simulation time 467655007 ps
CPU time 2.49 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:01 PM PDT 24
Peak memory 200816 kb
Host smart-7fcf75d8-25ee-4753-be3e-9fcd4a29b3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294886069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2294886069
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3273947697
Short name T507
Test name
Test status
Simulation time 73080892 ps
CPU time 0.78 seconds
Started May 02 01:35:59 PM PDT 24
Finished May 02 01:36:02 PM PDT 24
Peak memory 200916 kb
Host smart-b48e9553-7d09-4f93-8fa1-106af925a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273947697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3273947697
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2956074689
Short name T443
Test name
Test status
Simulation time 60865598 ps
CPU time 0.79 seconds
Started May 02 01:36:00 PM PDT 24
Finished May 02 01:36:02 PM PDT 24
Peak memory 200704 kb
Host smart-9b59042d-0990-437a-b311-622927fd0164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956074689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2956074689
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3433153975
Short name T226
Test name
Test status
Simulation time 1215330565 ps
CPU time 5.75 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:04 PM PDT 24
Peak memory 222632 kb
Host smart-2c17f20e-e2dc-4ea5-96af-923e40fcd9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433153975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3433153975
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.414866948
Short name T520
Test name
Test status
Simulation time 244401393 ps
CPU time 1.09 seconds
Started May 02 01:35:56 PM PDT 24
Finished May 02 01:35:59 PM PDT 24
Peak memory 218048 kb
Host smart-8e86faf8-bae5-425a-98ad-efacf2cbdf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414866948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.414866948
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.123264571
Short name T212
Test name
Test status
Simulation time 119189899 ps
CPU time 0.8 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:35:59 PM PDT 24
Peak memory 200660 kb
Host smart-396acaed-fce2-40a5-8f29-2cdb54f01e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123264571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.123264571
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.834178301
Short name T245
Test name
Test status
Simulation time 775032155 ps
CPU time 3.83 seconds
Started May 02 01:35:56 PM PDT 24
Finished May 02 01:36:01 PM PDT 24
Peak memory 201012 kb
Host smart-b2dec1db-f1aa-4f22-855d-4dcd5aba91bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834178301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.834178301
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2014658126
Short name T496
Test name
Test status
Simulation time 106539867 ps
CPU time 1.03 seconds
Started May 02 01:35:58 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 200864 kb
Host smart-aa03f55a-0526-422b-a78e-e747764c1d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014658126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2014658126
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.913402202
Short name T370
Test name
Test status
Simulation time 119189769 ps
CPU time 1.16 seconds
Started May 02 01:35:56 PM PDT 24
Finished May 02 01:35:59 PM PDT 24
Peak memory 201092 kb
Host smart-cb3b44e2-b81e-4c44-8a6c-f312014ac845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913402202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.913402202
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2275825821
Short name T154
Test name
Test status
Simulation time 373498254 ps
CPU time 1.95 seconds
Started May 02 01:35:58 PM PDT 24
Finished May 02 01:36:01 PM PDT 24
Peak memory 201104 kb
Host smart-cbc2c374-5188-4d1e-b4bf-150782cc6be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275825821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2275825821
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3885378544
Short name T47
Test name
Test status
Simulation time 134149725 ps
CPU time 1.65 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:01 PM PDT 24
Peak memory 200880 kb
Host smart-d3434bec-0941-47bc-ba30-0f44dd82005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885378544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3885378544
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3260051224
Short name T210
Test name
Test status
Simulation time 215909992 ps
CPU time 1.36 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 200852 kb
Host smart-c2a3bccd-1b5b-40d9-b0ef-4bf767d20d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260051224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3260051224
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2147173779
Short name T424
Test name
Test status
Simulation time 88657708 ps
CPU time 0.91 seconds
Started May 02 01:35:58 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 200716 kb
Host smart-12660124-350f-4344-b684-8bf308b55bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147173779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2147173779
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.718895013
Short name T531
Test name
Test status
Simulation time 2353642285 ps
CPU time 8.03 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:06 PM PDT 24
Peak memory 218720 kb
Host smart-18abdb28-cadc-4f05-9ccc-c3d5177267f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718895013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.718895013
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.40650620
Short name T312
Test name
Test status
Simulation time 244660912 ps
CPU time 1.07 seconds
Started May 02 01:35:59 PM PDT 24
Finished May 02 01:36:01 PM PDT 24
Peak memory 217952 kb
Host smart-f2ae8b9e-6388-4c09-b386-72ad5aa3c665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40650620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.40650620
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1372953280
Short name T535
Test name
Test status
Simulation time 240538069 ps
CPU time 0.94 seconds
Started May 02 01:35:55 PM PDT 24
Finished May 02 01:35:58 PM PDT 24
Peak memory 200688 kb
Host smart-ccd77ee4-9f1e-4b1f-ad3c-fe5d4abff128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372953280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1372953280
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.21243837
Short name T221
Test name
Test status
Simulation time 1310038682 ps
CPU time 5.4 seconds
Started May 02 01:35:55 PM PDT 24
Finished May 02 01:36:02 PM PDT 24
Peak memory 201048 kb
Host smart-a89c46ce-559a-4652-949e-8440366a7daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21243837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.21243837
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2378360487
Short name T140
Test name
Test status
Simulation time 151196874 ps
CPU time 1.13 seconds
Started May 02 01:35:58 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 200836 kb
Host smart-83206592-d105-49b5-b923-8dcf350252ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378360487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2378360487
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3934327021
Short name T236
Test name
Test status
Simulation time 113661721 ps
CPU time 1.23 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 201072 kb
Host smart-88300fed-1ee8-4d7c-8b5d-fc00cf6edc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934327021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3934327021
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.4229119488
Short name T422
Test name
Test status
Simulation time 5464690354 ps
CPU time 25.24 seconds
Started May 02 01:35:58 PM PDT 24
Finished May 02 01:36:25 PM PDT 24
Peak memory 201196 kb
Host smart-ee796976-6c2b-40d2-83f6-78193e373923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229119488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.4229119488
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1520102121
Short name T75
Test name
Test status
Simulation time 111621906 ps
CPU time 1.45 seconds
Started May 02 01:35:58 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 200888 kb
Host smart-39006297-867a-418b-84ae-2054455103a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520102121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1520102121
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.528740386
Short name T203
Test name
Test status
Simulation time 101583138 ps
CPU time 0.93 seconds
Started May 02 01:35:58 PM PDT 24
Finished May 02 01:36:01 PM PDT 24
Peak memory 200772 kb
Host smart-596d6973-4bed-4d1e-86b1-37b869a953f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528740386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.528740386
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.784477334
Short name T306
Test name
Test status
Simulation time 78737676 ps
CPU time 0.8 seconds
Started May 02 01:36:03 PM PDT 24
Finished May 02 01:36:05 PM PDT 24
Peak memory 200676 kb
Host smart-a7a2b7db-2148-4ed3-8d7e-2be32d21e72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784477334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.784477334
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1603227219
Short name T45
Test name
Test status
Simulation time 1218031442 ps
CPU time 5.51 seconds
Started May 02 01:35:58 PM PDT 24
Finished May 02 01:36:05 PM PDT 24
Peak memory 218544 kb
Host smart-c554edf8-454c-4ca8-883b-6b944463d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603227219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1603227219
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.13608623
Short name T393
Test name
Test status
Simulation time 244371774 ps
CPU time 1.07 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 218032 kb
Host smart-f36b54a0-09d6-4112-b15c-4f5b0ca63ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13608623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.13608623
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.548198939
Short name T17
Test name
Test status
Simulation time 179489604 ps
CPU time 0.99 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 200708 kb
Host smart-3896428a-6df9-4ca9-8ae0-6f5df342204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548198939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.548198939
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3636645244
Short name T242
Test name
Test status
Simulation time 1092328346 ps
CPU time 4.54 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:04 PM PDT 24
Peak memory 201028 kb
Host smart-446c7f29-ca41-43e2-80d1-bb5f5518fc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636645244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3636645244
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.337030380
Short name T282
Test name
Test status
Simulation time 95192366 ps
CPU time 1.02 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 200900 kb
Host smart-dc2307d0-920f-418f-9c79-e6f181217253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337030380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.337030380
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.390745556
Short name T218
Test name
Test status
Simulation time 260165008 ps
CPU time 1.44 seconds
Started May 02 01:35:57 PM PDT 24
Finished May 02 01:36:00 PM PDT 24
Peak memory 201112 kb
Host smart-e00dc1d4-32dd-4dfb-a802-d878e775d4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390745556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.390745556
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3402922941
Short name T107
Test name
Test status
Simulation time 3500430304 ps
CPU time 18.22 seconds
Started May 02 01:36:03 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 209392 kb
Host smart-a8696746-e37e-4b23-8c8a-6fc670b6feb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402922941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3402922941
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1224203140
Short name T238
Test name
Test status
Simulation time 112193038 ps
CPU time 1.04 seconds
Started May 02 01:35:59 PM PDT 24
Finished May 02 01:36:01 PM PDT 24
Peak memory 200892 kb
Host smart-5948e446-e102-4871-9a33-97c9279aa4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224203140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1224203140
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.625991043
Short name T240
Test name
Test status
Simulation time 78733077 ps
CPU time 0.78 seconds
Started May 02 01:36:05 PM PDT 24
Finished May 02 01:36:07 PM PDT 24
Peak memory 200668 kb
Host smart-074e17c9-12f9-4974-bb38-cb5ac9b72c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625991043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.625991043
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.950900049
Short name T513
Test name
Test status
Simulation time 1219452009 ps
CPU time 5.46 seconds
Started May 02 01:36:06 PM PDT 24
Finished May 02 01:36:13 PM PDT 24
Peak memory 230856 kb
Host smart-12ddb9eb-f494-42ef-8bf7-6d2f57bdbbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950900049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.950900049
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1360410797
Short name T457
Test name
Test status
Simulation time 245315782 ps
CPU time 1.09 seconds
Started May 02 01:36:07 PM PDT 24
Finished May 02 01:36:09 PM PDT 24
Peak memory 218120 kb
Host smart-3d7e77f8-5ac1-4782-a5b0-2e8821cd1a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360410797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1360410797
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2970493991
Short name T517
Test name
Test status
Simulation time 99149259 ps
CPU time 0.79 seconds
Started May 02 01:36:06 PM PDT 24
Finished May 02 01:36:08 PM PDT 24
Peak memory 200664 kb
Host smart-cb6684a4-a426-4758-aa49-8b7e495826d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970493991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2970493991
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3484127391
Short name T421
Test name
Test status
Simulation time 1564248908 ps
CPU time 6.25 seconds
Started May 02 01:36:06 PM PDT 24
Finished May 02 01:36:14 PM PDT 24
Peak memory 201096 kb
Host smart-c875040a-ea88-4458-a151-66c1f879dc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484127391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3484127391
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3099624451
Short name T136
Test name
Test status
Simulation time 186417263 ps
CPU time 1.15 seconds
Started May 02 01:36:05 PM PDT 24
Finished May 02 01:36:07 PM PDT 24
Peak memory 200848 kb
Host smart-051c7cab-98e9-44a2-8362-eebef709195a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099624451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3099624451
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3876989194
Short name T167
Test name
Test status
Simulation time 192625007 ps
CPU time 1.3 seconds
Started May 02 01:36:05 PM PDT 24
Finished May 02 01:36:07 PM PDT 24
Peak memory 201024 kb
Host smart-35cc9f6a-edc7-4e9c-b501-e07c3311e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876989194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3876989194
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3646566096
Short name T499
Test name
Test status
Simulation time 8327129927 ps
CPU time 28.66 seconds
Started May 02 01:36:04 PM PDT 24
Finished May 02 01:36:33 PM PDT 24
Peak memory 201124 kb
Host smart-553f04c3-8d04-442d-bbb7-941a28dd82c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646566096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3646566096
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.4232023634
Short name T463
Test name
Test status
Simulation time 347492913 ps
CPU time 2.43 seconds
Started May 02 01:36:06 PM PDT 24
Finished May 02 01:36:10 PM PDT 24
Peak memory 200884 kb
Host smart-eb66f529-136c-42fb-9883-d6f492e5f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232023634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4232023634
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2917092945
Short name T157
Test name
Test status
Simulation time 126568030 ps
CPU time 0.99 seconds
Started May 02 01:36:05 PM PDT 24
Finished May 02 01:36:07 PM PDT 24
Peak memory 200636 kb
Host smart-cdc72d53-9d80-4a48-b3c1-f984b2bad032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917092945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2917092945
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1942403062
Short name T412
Test name
Test status
Simulation time 89453695 ps
CPU time 0.83 seconds
Started May 02 01:36:09 PM PDT 24
Finished May 02 01:36:11 PM PDT 24
Peak memory 200600 kb
Host smart-88e994ab-f737-4e9a-8082-2ed01ea65968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942403062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1942403062
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.891386452
Short name T403
Test name
Test status
Simulation time 2356224212 ps
CPU time 8 seconds
Started May 02 01:36:07 PM PDT 24
Finished May 02 01:36:16 PM PDT 24
Peak memory 218028 kb
Host smart-0c271d3e-ec88-428c-b336-a77e88f3af19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891386452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.891386452
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.4043982905
Short name T290
Test name
Test status
Simulation time 244523480 ps
CPU time 1.04 seconds
Started May 02 01:36:06 PM PDT 24
Finished May 02 01:36:08 PM PDT 24
Peak memory 218020 kb
Host smart-3aa3aded-df4b-4be8-bc7f-a829d668930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043982905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.4043982905
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.886531488
Short name T21
Test name
Test status
Simulation time 71856203 ps
CPU time 0.73 seconds
Started May 02 01:36:06 PM PDT 24
Finished May 02 01:36:08 PM PDT 24
Peak memory 200628 kb
Host smart-8e0b5b2f-8280-4471-9052-0c2926e5e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886531488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.886531488
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3393357077
Short name T220
Test name
Test status
Simulation time 898622840 ps
CPU time 4.2 seconds
Started May 02 01:36:05 PM PDT 24
Finished May 02 01:36:11 PM PDT 24
Peak memory 200836 kb
Host smart-6a68272a-5854-468c-b96a-41647fe71234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393357077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3393357077
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1678408345
Short name T237
Test name
Test status
Simulation time 186073767 ps
CPU time 1.15 seconds
Started May 02 01:36:07 PM PDT 24
Finished May 02 01:36:09 PM PDT 24
Peak memory 200900 kb
Host smart-f11a28ab-5dd6-442d-8c07-159f69639561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678408345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1678408345
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.4238500824
Short name T476
Test name
Test status
Simulation time 242909751 ps
CPU time 1.51 seconds
Started May 02 01:36:04 PM PDT 24
Finished May 02 01:36:07 PM PDT 24
Peak memory 200996 kb
Host smart-a0281ef5-aa93-4f27-a807-99f0758abb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238500824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.4238500824
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2114554156
Short name T13
Test name
Test status
Simulation time 4056767054 ps
CPU time 17.88 seconds
Started May 02 01:36:07 PM PDT 24
Finished May 02 01:36:26 PM PDT 24
Peak memory 209416 kb
Host smart-5a1ae9de-7dec-47f1-9567-e77a734ab316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114554156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2114554156
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2147121515
Short name T222
Test name
Test status
Simulation time 292452733 ps
CPU time 1.91 seconds
Started May 02 01:36:04 PM PDT 24
Finished May 02 01:36:07 PM PDT 24
Peak memory 200916 kb
Host smart-5fdf5415-1fe4-425e-92dc-f799f7f52767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147121515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2147121515
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.111542838
Short name T205
Test name
Test status
Simulation time 69574952 ps
CPU time 0.77 seconds
Started May 02 01:36:04 PM PDT 24
Finished May 02 01:36:05 PM PDT 24
Peak memory 200888 kb
Host smart-8fd2de7d-6f4f-4bef-98a8-db8ef0783890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111542838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.111542838
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1013253874
Short name T413
Test name
Test status
Simulation time 71774052 ps
CPU time 0.76 seconds
Started May 02 01:36:11 PM PDT 24
Finished May 02 01:36:14 PM PDT 24
Peak memory 200712 kb
Host smart-aa82b067-e72d-4217-b92c-083932b0b7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013253874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1013253874
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3416849530
Short name T390
Test name
Test status
Simulation time 2370642004 ps
CPU time 8.09 seconds
Started May 02 01:36:12 PM PDT 24
Finished May 02 01:36:22 PM PDT 24
Peak memory 218368 kb
Host smart-5b4909d8-1adc-4389-800b-c5537d80a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416849530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3416849530
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2066736081
Short name T327
Test name
Test status
Simulation time 245038005 ps
CPU time 1.08 seconds
Started May 02 01:36:11 PM PDT 24
Finished May 02 01:36:15 PM PDT 24
Peak memory 218108 kb
Host smart-d25212c6-0024-436f-a9c0-5dc2897a016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066736081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2066736081
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1165514148
Short name T273
Test name
Test status
Simulation time 91816470 ps
CPU time 0.76 seconds
Started May 02 01:36:06 PM PDT 24
Finished May 02 01:36:09 PM PDT 24
Peak memory 200632 kb
Host smart-0715069f-7cb8-49af-8b4a-b701e85ba56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165514148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1165514148
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2012358637
Short name T375
Test name
Test status
Simulation time 810543305 ps
CPU time 4.31 seconds
Started May 02 01:36:06 PM PDT 24
Finished May 02 01:36:12 PM PDT 24
Peak memory 201028 kb
Host smart-152d6aaa-df2a-4d5c-a662-818ee1e56234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012358637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2012358637
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.893149459
Short name T286
Test name
Test status
Simulation time 167862747 ps
CPU time 1.26 seconds
Started May 02 01:36:07 PM PDT 24
Finished May 02 01:36:10 PM PDT 24
Peak memory 200904 kb
Host smart-e1ddb050-ef20-4e3c-a96d-54990fbc6412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893149459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.893149459
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3000303901
Short name T227
Test name
Test status
Simulation time 122448318 ps
CPU time 1.18 seconds
Started May 02 01:36:08 PM PDT 24
Finished May 02 01:36:11 PM PDT 24
Peak memory 200964 kb
Host smart-892f8308-9316-4464-827c-128da78309f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000303901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3000303901
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.549370104
Short name T360
Test name
Test status
Simulation time 7268000349 ps
CPU time 26.77 seconds
Started May 02 01:36:11 PM PDT 24
Finished May 02 01:36:39 PM PDT 24
Peak memory 201192 kb
Host smart-2aaeb1de-33bc-4e2b-b2e6-01cfac49c4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549370104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.549370104
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2715558747
Short name T430
Test name
Test status
Simulation time 157566798 ps
CPU time 1.84 seconds
Started May 02 01:36:05 PM PDT 24
Finished May 02 01:36:08 PM PDT 24
Peak memory 200884 kb
Host smart-9c963505-f0c2-4547-9501-34282f124d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715558747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2715558747
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1241831180
Short name T204
Test name
Test status
Simulation time 67619209 ps
CPU time 0.76 seconds
Started May 02 01:36:09 PM PDT 24
Finished May 02 01:36:11 PM PDT 24
Peak memory 200776 kb
Host smart-cbeab0ac-9c60-49ef-96ea-3191c5bce5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241831180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1241831180
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2407734662
Short name T164
Test name
Test status
Simulation time 64581285 ps
CPU time 0.69 seconds
Started May 02 01:33:33 PM PDT 24
Finished May 02 01:33:35 PM PDT 24
Peak memory 200668 kb
Host smart-18663ba6-d216-48bb-9b3f-78daf8f1d36c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407734662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2407734662
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1636194679
Short name T410
Test name
Test status
Simulation time 1907620572 ps
CPU time 7.17 seconds
Started May 02 01:33:41 PM PDT 24
Finished May 02 01:33:49 PM PDT 24
Peak memory 218600 kb
Host smart-12b33732-aa89-4a11-a062-967d13e0a5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636194679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1636194679
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2945597395
Short name T155
Test name
Test status
Simulation time 244777617 ps
CPU time 1.19 seconds
Started May 02 01:33:42 PM PDT 24
Finished May 02 01:33:44 PM PDT 24
Peak memory 218268 kb
Host smart-593a5fb5-7a55-4599-aa46-899b6ba976c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945597395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2945597395
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3187973355
Short name T492
Test name
Test status
Simulation time 105403623 ps
CPU time 0.76 seconds
Started May 02 01:33:32 PM PDT 24
Finished May 02 01:33:34 PM PDT 24
Peak memory 200680 kb
Host smart-35dd7a2c-b911-4f4c-b688-8ea3ebbb4e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187973355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3187973355
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.305716369
Short name T260
Test name
Test status
Simulation time 1453825075 ps
CPU time 5.9 seconds
Started May 02 01:33:34 PM PDT 24
Finished May 02 01:33:41 PM PDT 24
Peak memory 200996 kb
Host smart-e20d9b78-0f63-4b52-a518-2bf98c9c0093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305716369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.305716369
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1695104856
Short name T141
Test name
Test status
Simulation time 182654452 ps
CPU time 1.22 seconds
Started May 02 01:33:32 PM PDT 24
Finished May 02 01:33:34 PM PDT 24
Peak memory 200864 kb
Host smart-6eeafc52-db47-4c82-867c-3d57159df75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695104856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1695104856
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.776236589
Short name T268
Test name
Test status
Simulation time 218781050 ps
CPU time 1.39 seconds
Started May 02 01:33:35 PM PDT 24
Finished May 02 01:33:37 PM PDT 24
Peak memory 201100 kb
Host smart-805c6aa4-4284-4073-979c-f11a1e4af1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776236589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.776236589
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2822574783
Short name T288
Test name
Test status
Simulation time 1628372991 ps
CPU time 5.95 seconds
Started May 02 01:33:31 PM PDT 24
Finished May 02 01:33:38 PM PDT 24
Peak memory 209284 kb
Host smart-407d43d6-ecb3-47b9-a944-9bf829db730a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822574783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2822574783
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1042463862
Short name T289
Test name
Test status
Simulation time 327360452 ps
CPU time 2.19 seconds
Started May 02 01:33:36 PM PDT 24
Finished May 02 01:33:39 PM PDT 24
Peak memory 200860 kb
Host smart-5a803efe-48fa-4d60-b5fe-4caabb779091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042463862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1042463862
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1337028955
Short name T366
Test name
Test status
Simulation time 107784074 ps
CPU time 1.06 seconds
Started May 02 01:33:42 PM PDT 24
Finished May 02 01:33:44 PM PDT 24
Peak memory 200824 kb
Host smart-3639b439-3360-412d-9d2d-7d537d654061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337028955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1337028955
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.16305411
Short name T224
Test name
Test status
Simulation time 78915947 ps
CPU time 0.78 seconds
Started May 02 01:33:44 PM PDT 24
Finished May 02 01:33:45 PM PDT 24
Peak memory 200704 kb
Host smart-7e4a0d5d-57ea-4d61-9661-d06518964e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16305411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.16305411
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1842301988
Short name T383
Test name
Test status
Simulation time 1219631749 ps
CPU time 5.96 seconds
Started May 02 01:33:43 PM PDT 24
Finished May 02 01:33:50 PM PDT 24
Peak memory 222656 kb
Host smart-8f31e45b-77ee-4525-af09-05fd2f69dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842301988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1842301988
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2742469178
Short name T534
Test name
Test status
Simulation time 243774528 ps
CPU time 1.1 seconds
Started May 02 01:33:42 PM PDT 24
Finished May 02 01:33:44 PM PDT 24
Peak memory 218152 kb
Host smart-71c8323d-3353-4aae-a2ce-adf0a1061eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742469178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2742469178
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2363658719
Short name T419
Test name
Test status
Simulation time 161041582 ps
CPU time 0.86 seconds
Started May 02 01:33:34 PM PDT 24
Finished May 02 01:33:36 PM PDT 24
Peak memory 200708 kb
Host smart-58d54fe4-0289-4ccd-9dd0-698f200add0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363658719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2363658719
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.104593669
Short name T160
Test name
Test status
Simulation time 1494665850 ps
CPU time 5.71 seconds
Started May 02 01:33:35 PM PDT 24
Finished May 02 01:33:42 PM PDT 24
Peak memory 201016 kb
Host smart-275866d2-1f24-4df8-9b78-ec76fe874772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104593669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.104593669
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3618903614
Short name T24
Test name
Test status
Simulation time 149566446 ps
CPU time 1.12 seconds
Started May 02 01:33:32 PM PDT 24
Finished May 02 01:33:34 PM PDT 24
Peak memory 200844 kb
Host smart-cfd8aeb0-e9f4-44ed-8a1d-512cdf255669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618903614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3618903614
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.68816404
Short name T469
Test name
Test status
Simulation time 230817506 ps
CPU time 1.48 seconds
Started May 02 01:33:33 PM PDT 24
Finished May 02 01:33:36 PM PDT 24
Peak memory 200948 kb
Host smart-50b57206-af6e-4539-8da8-db51ec58b14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68816404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.68816404
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3762129619
Short name T468
Test name
Test status
Simulation time 10136821746 ps
CPU time 34.99 seconds
Started May 02 01:33:45 PM PDT 24
Finished May 02 01:34:21 PM PDT 24
Peak memory 201132 kb
Host smart-7f0bf8e0-e522-4117-a4dc-c1c46d4c3527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762129619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3762129619
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1478531675
Short name T417
Test name
Test status
Simulation time 349411512 ps
CPU time 2.2 seconds
Started May 02 01:33:32 PM PDT 24
Finished May 02 01:33:35 PM PDT 24
Peak memory 200856 kb
Host smart-18d3f1bd-d1b9-4bef-a6ee-586c52151ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478531675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1478531675
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2010325105
Short name T97
Test name
Test status
Simulation time 138650531 ps
CPU time 1.09 seconds
Started May 02 01:33:34 PM PDT 24
Finished May 02 01:33:36 PM PDT 24
Peak memory 200844 kb
Host smart-aee955c2-11e9-47e0-ac79-de2060c23629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010325105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2010325105
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.105987660
Short name T488
Test name
Test status
Simulation time 84871977 ps
CPU time 0.81 seconds
Started May 02 01:33:44 PM PDT 24
Finished May 02 01:33:46 PM PDT 24
Peak memory 200688 kb
Host smart-0a440f4f-6b8a-41b3-9415-9ecb5c713f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105987660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.105987660
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1349289146
Short name T40
Test name
Test status
Simulation time 1225796302 ps
CPU time 5.22 seconds
Started May 02 01:33:43 PM PDT 24
Finished May 02 01:33:49 PM PDT 24
Peak memory 230208 kb
Host smart-f7d37a12-166b-40b9-ba6c-0f17f0cc05f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349289146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1349289146
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3985229450
Short name T232
Test name
Test status
Simulation time 243945220 ps
CPU time 1.11 seconds
Started May 02 01:33:45 PM PDT 24
Finished May 02 01:33:47 PM PDT 24
Peak memory 218052 kb
Host smart-efe44cd5-baa6-4733-9f14-563108411891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985229450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3985229450
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2368118038
Short name T182
Test name
Test status
Simulation time 80655138 ps
CPU time 0.71 seconds
Started May 02 01:33:43 PM PDT 24
Finished May 02 01:33:45 PM PDT 24
Peak memory 200688 kb
Host smart-533fb036-1e55-4dcc-bdb2-5165599916b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368118038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2368118038
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2525597485
Short name T371
Test name
Test status
Simulation time 1473288524 ps
CPU time 5.41 seconds
Started May 02 01:33:46 PM PDT 24
Finished May 02 01:33:52 PM PDT 24
Peak memory 200968 kb
Host smart-6f3ef37c-3c13-4707-9910-5766de4e259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525597485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2525597485
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4255062967
Short name T123
Test name
Test status
Simulation time 157897929 ps
CPU time 1.09 seconds
Started May 02 01:33:43 PM PDT 24
Finished May 02 01:33:44 PM PDT 24
Peak memory 200856 kb
Host smart-89ab88eb-7211-4bc3-8e58-74b85a7cf1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255062967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4255062967
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.349288025
Short name T223
Test name
Test status
Simulation time 185822917 ps
CPU time 1.34 seconds
Started May 02 01:33:43 PM PDT 24
Finished May 02 01:33:46 PM PDT 24
Peak memory 200968 kb
Host smart-373781e3-e51a-49e8-a60c-b5182631d699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349288025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.349288025
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1133375553
Short name T108
Test name
Test status
Simulation time 7741755694 ps
CPU time 33.93 seconds
Started May 02 01:33:44 PM PDT 24
Finished May 02 01:34:19 PM PDT 24
Peak memory 201168 kb
Host smart-f9a6f6a5-0c7e-4a75-8c61-72b0fb234819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133375553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1133375553
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.684694394
Short name T9
Test name
Test status
Simulation time 489449704 ps
CPU time 2.4 seconds
Started May 02 01:33:44 PM PDT 24
Finished May 02 01:33:47 PM PDT 24
Peak memory 200876 kb
Host smart-eae9f727-77b4-4707-8f66-59f84d3e5461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684694394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.684694394
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3067191377
Short name T76
Test name
Test status
Simulation time 123232732 ps
CPU time 0.93 seconds
Started May 02 01:33:45 PM PDT 24
Finished May 02 01:33:47 PM PDT 24
Peak memory 200816 kb
Host smart-0b18aa35-4dff-4b4b-8d30-f01d30d0858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067191377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3067191377
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2817532474
Short name T345
Test name
Test status
Simulation time 78775584 ps
CPU time 0.83 seconds
Started May 02 01:33:59 PM PDT 24
Finished May 02 01:34:01 PM PDT 24
Peak memory 200648 kb
Host smart-df20d1cc-bcca-45d9-b4db-899647619342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817532474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2817532474
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.733075188
Short name T266
Test name
Test status
Simulation time 1236746271 ps
CPU time 6.15 seconds
Started May 02 01:33:51 PM PDT 24
Finished May 02 01:33:59 PM PDT 24
Peak memory 221948 kb
Host smart-14d4beb6-d6d7-409b-a3b8-7ca7487fea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733075188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.733075188
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2990580836
Short name T478
Test name
Test status
Simulation time 244619957 ps
CPU time 0.99 seconds
Started May 02 01:33:56 PM PDT 24
Finished May 02 01:33:58 PM PDT 24
Peak memory 218108 kb
Host smart-48d223f0-e31f-402a-9b0f-9947ff406ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990580836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2990580836
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1061984655
Short name T20
Test name
Test status
Simulation time 176568446 ps
CPU time 0.83 seconds
Started May 02 01:33:43 PM PDT 24
Finished May 02 01:33:45 PM PDT 24
Peak memory 200620 kb
Host smart-03fc9550-0508-4489-9fbc-125298bdc90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061984655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1061984655
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1100549191
Short name T106
Test name
Test status
Simulation time 863836644 ps
CPU time 4.21 seconds
Started May 02 01:33:45 PM PDT 24
Finished May 02 01:33:50 PM PDT 24
Peak memory 201064 kb
Host smart-e0dd329b-5e62-4c3c-bb5c-33a37b24dee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100549191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1100549191
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.180767654
Short name T389
Test name
Test status
Simulation time 107582867 ps
CPU time 0.98 seconds
Started May 02 01:33:53 PM PDT 24
Finished May 02 01:33:57 PM PDT 24
Peak memory 200792 kb
Host smart-2708c255-ec20-4303-a5b0-4c9cdbb4523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180767654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.180767654
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2017894906
Short name T122
Test name
Test status
Simulation time 263195517 ps
CPU time 1.53 seconds
Started May 02 01:33:42 PM PDT 24
Finished May 02 01:33:44 PM PDT 24
Peak memory 201100 kb
Host smart-caa5de6b-1f36-4e05-9354-6fab3df1db30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017894906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2017894906
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2030121334
Short name T105
Test name
Test status
Simulation time 1451256613 ps
CPU time 5.34 seconds
Started May 02 01:33:53 PM PDT 24
Finished May 02 01:34:00 PM PDT 24
Peak memory 201092 kb
Host smart-e2b2138a-a3fb-4d82-b58d-e783d3d6d27b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030121334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2030121334
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3099731363
Short name T179
Test name
Test status
Simulation time 118950291 ps
CPU time 1.62 seconds
Started May 02 01:33:59 PM PDT 24
Finished May 02 01:34:01 PM PDT 24
Peak memory 200820 kb
Host smart-c48f5606-41dc-4109-a741-95848c6bfb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099731363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3099731363
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1645001218
Short name T420
Test name
Test status
Simulation time 257154601 ps
CPU time 1.41 seconds
Started May 02 01:33:42 PM PDT 24
Finished May 02 01:33:44 PM PDT 24
Peak memory 200856 kb
Host smart-b49ea862-94d3-4072-b9a6-948c872f7fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645001218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1645001218
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3688568853
Short name T428
Test name
Test status
Simulation time 79327575 ps
CPU time 0.84 seconds
Started May 02 01:34:00 PM PDT 24
Finished May 02 01:34:02 PM PDT 24
Peak memory 200652 kb
Host smart-13738baa-315a-4ca3-90d5-2b006129d703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688568853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3688568853
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2931113568
Short name T340
Test name
Test status
Simulation time 1221455603 ps
CPU time 5.52 seconds
Started May 02 01:33:54 PM PDT 24
Finished May 02 01:34:01 PM PDT 24
Peak memory 230252 kb
Host smart-8ac0e929-01e3-4db3-9bb9-b9d4959cff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931113568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2931113568
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3645447965
Short name T451
Test name
Test status
Simulation time 245863060 ps
CPU time 1.03 seconds
Started May 02 01:33:51 PM PDT 24
Finished May 02 01:33:53 PM PDT 24
Peak memory 218348 kb
Host smart-37aa2393-ed95-44ba-a4cb-6a7087023b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645447965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3645447965
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1277358681
Short name T353
Test name
Test status
Simulation time 114329167 ps
CPU time 0.82 seconds
Started May 02 01:33:52 PM PDT 24
Finished May 02 01:33:55 PM PDT 24
Peak memory 200668 kb
Host smart-9869649f-53dc-45f8-a757-de7e8c6b7220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277358681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1277358681
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3861723243
Short name T93
Test name
Test status
Simulation time 1767330499 ps
CPU time 6.36 seconds
Started May 02 01:33:54 PM PDT 24
Finished May 02 01:34:02 PM PDT 24
Peak memory 200748 kb
Host smart-b583fd17-df3e-4a57-8447-dd2878f2651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861723243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3861723243
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.338497250
Short name T529
Test name
Test status
Simulation time 173371447 ps
CPU time 1.15 seconds
Started May 02 01:33:54 PM PDT 24
Finished May 02 01:33:57 PM PDT 24
Peak memory 200592 kb
Host smart-44f056c1-bc4c-42f5-add0-0ada24cc643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338497250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.338497250
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.417128236
Short name T244
Test name
Test status
Simulation time 220375376 ps
CPU time 1.42 seconds
Started May 02 01:33:50 PM PDT 24
Finished May 02 01:33:52 PM PDT 24
Peak memory 201056 kb
Host smart-6f0033d3-151e-4513-8076-031749f1844d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417128236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.417128236
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.610445620
Short name T459
Test name
Test status
Simulation time 2315589137 ps
CPU time 9.38 seconds
Started May 02 01:33:52 PM PDT 24
Finished May 02 01:34:03 PM PDT 24
Peak memory 209380 kb
Host smart-f5de039d-19fb-4d71-b962-fc1861877371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610445620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.610445620
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.779687492
Short name T432
Test name
Test status
Simulation time 465734181 ps
CPU time 2.61 seconds
Started May 02 01:33:51 PM PDT 24
Finished May 02 01:33:56 PM PDT 24
Peak memory 200900 kb
Host smart-c3965a85-12aa-476e-b3c5-34318dbb9f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779687492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.779687492
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3525454721
Short name T338
Test name
Test status
Simulation time 86782324 ps
CPU time 0.87 seconds
Started May 02 01:33:52 PM PDT 24
Finished May 02 01:33:55 PM PDT 24
Peak memory 200900 kb
Host smart-a1e32c90-8da0-44cd-b343-18fe4df2a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525454721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3525454721
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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