Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7609

1

T2

31

T3

157

T10

18

auto[1]

10803

1

T2

26

T3

168

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5620	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6230	1			T1	1		T2	15		T3	106
reset_info_cp[2]	2926	1			T2	8		T3	48		T5	1
reset_info_cp[4]	3722	1			T2	14		T3	82		T5	1
reset_info_cp[8]	121	1			T3	3		T10	1		T27	1
reset_info_cp[16]	118	1			T3	2		T10	1		T53	1
reset_info_cp[32]	93	1			T2	1		T3	1		T50	1
reset_info_cp[64]	98	1			T3	2		T10	2		T54	1
reset_info_cp[128]	104	1			T3	2		T14	1		T46	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2947	1			T2	10		T3	53		T14	8
reset_info_cp[1]	auto[1]	2663	1			T2	4		T3	52		T5	1
reset_info_cp[2]	auto[0]	916	1			T2	4		T3	20		T14	2
reset_info_cp[2]	auto[1]	2010	1			T2	4		T3	28		T5	1
reset_info_cp[4]	auto[0]	1245	1			T2	4		T3	30		T14	4
reset_info_cp[4]	auto[1]	2477	1			T2	10		T3	52		T5	1
reset_info_cp[8]	auto[0]	56	1			T3	2		T10	1		T27	1
reset_info_cp[8]	auto[1]	65	1			T3	1		T85	2		T129	1
reset_info_cp[16]	auto[0]	37	1			T10	1		T54	1		T132	2
reset_info_cp[16]	auto[1]	81	1			T3	2		T53	1		T85	1
reset_info_cp[32]	auto[0]	34	1			T50	1		T90	1		T108	1
reset_info_cp[32]	auto[1]	59	1			T2	1		T3	1		T52	1
reset_info_cp[64]	auto[0]	41	1			T10	2		T55	1		T90	1
reset_info_cp[64]	auto[1]	57	1			T3	2		T54	1		T55	1
reset_info_cp[128]	auto[0]	41	1			T14	1		T108	2		T133	1
reset_info_cp[128]	auto[1]	63	1			T3	2		T46	1		T82	1