SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
99.43 | 99.40 | 99.24 | 99.87 | 99.83 | 99.46 | 98.77 |
T536 | /workspace/coverage/default/46.rstmgr_reset.4276757986 | May 05 12:26:10 PM PDT 24 | May 05 12:26:16 PM PDT 24 | 1053499079 ps | ||
T537 | /workspace/coverage/default/16.rstmgr_reset.2431478396 | May 05 12:25:05 PM PDT 24 | May 05 12:25:12 PM PDT 24 | 1490256862 ps | ||
T538 | /workspace/coverage/default/46.rstmgr_por_stretcher.1520833522 | May 05 12:25:54 PM PDT 24 | May 05 12:25:57 PM PDT 24 | 183538587 ps | ||
T539 | /workspace/coverage/default/29.rstmgr_alert_test.3709816488 | May 05 12:25:28 PM PDT 24 | May 05 12:25:30 PM PDT 24 | 78120348 ps | ||
T540 | /workspace/coverage/default/25.rstmgr_por_stretcher.1947023361 | May 05 12:25:32 PM PDT 24 | May 05 12:25:34 PM PDT 24 | 268112398 ps | ||
T69 | /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3678707680 | May 05 12:24:12 PM PDT 24 | May 05 12:24:18 PM PDT 24 | 215652775 ps | ||
T70 | /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1011600589 | May 05 12:23:52 PM PDT 24 | May 05 12:23:55 PM PDT 24 | 61659681 ps | ||
T71 | /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.609487812 | May 05 12:20:40 PM PDT 24 | May 05 12:20:44 PM PDT 24 | 822789004 ps | ||
T73 | /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2314078328 | May 05 12:24:21 PM PDT 24 | May 05 12:24:24 PM PDT 24 | 127405437 ps | ||
T72 | /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1055983650 | May 05 12:19:25 PM PDT 24 | May 05 12:19:29 PM PDT 24 | 888907097 ps | ||
T541 | /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.436962647 | May 05 12:24:52 PM PDT 24 | May 05 12:24:56 PM PDT 24 | 61946451 ps | ||
T120 | /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1107559904 | May 05 12:20:07 PM PDT 24 | May 05 12:20:08 PM PDT 24 | 72743999 ps | ||
T121 | /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1529558968 | May 05 12:22:25 PM PDT 24 | May 05 12:22:27 PM PDT 24 | 82984716 ps | ||
T74 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3648519391 | May 05 12:24:10 PM PDT 24 | May 05 12:24:16 PM PDT 24 | 163649110 ps | ||
T75 | /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2618247739 | May 05 12:20:50 PM PDT 24 | May 05 12:20:54 PM PDT 24 | 469080089 ps | ||
T91 | /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.145152768 | May 05 12:24:16 PM PDT 24 | May 05 12:24:20 PM PDT 24 | 108070813 ps | ||
T93 | /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3943994788 | May 05 12:22:25 PM PDT 24 | May 05 12:22:27 PM PDT 24 | 448872172 ps | ||
T100 | /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1593970403 | May 05 12:22:47 PM PDT 24 | May 05 12:22:50 PM PDT 24 | 439614796 ps | ||
T92 | /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.416393162 | May 05 12:23:48 PM PDT 24 | May 05 12:23:51 PM PDT 24 | 112374161 ps | ||
T542 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1746373653 | May 05 12:19:55 PM PDT 24 | May 05 12:19:57 PM PDT 24 | 138153234 ps | ||
T112 | /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3480152626 | May 05 12:22:28 PM PDT 24 | May 05 12:22:29 PM PDT 24 | 101406931 ps | ||
T122 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1150906126 | May 05 12:24:04 PM PDT 24 | May 05 12:24:09 PM PDT 24 | 71902380 ps | ||
T102 | /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3887792757 | May 05 12:22:08 PM PDT 24 | May 05 12:22:11 PM PDT 24 | 802254297 ps | ||
T94 | /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1172078363 | May 05 12:24:05 PM PDT 24 | May 05 12:24:10 PM PDT 24 | 198244652 ps | ||
T123 | /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2258293997 | May 05 12:24:50 PM PDT 24 | May 05 12:24:55 PM PDT 24 | 98615401 ps | ||
T101 | /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2550127183 | May 05 12:23:49 PM PDT 24 | May 05 12:23:51 PM PDT 24 | 116406421 ps | ||
T95 | /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4094282200 | May 05 12:23:49 PM PDT 24 | May 05 12:23:53 PM PDT 24 | 422413493 ps | ||
T98 | /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.713717656 | May 05 12:21:51 PM PDT 24 | May 05 12:21:55 PM PDT 24 | 801992435 ps | ||
T96 | /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1586634275 | May 05 12:24:05 PM PDT 24 | May 05 12:24:10 PM PDT 24 | 213533964 ps | ||
T124 | /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3979439603 | May 05 12:21:41 PM PDT 24 | May 05 12:21:43 PM PDT 24 | 97354988 ps | ||
T107 | /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2481643774 | May 05 12:21:27 PM PDT 24 | May 05 12:21:31 PM PDT 24 | 478113533 ps | ||
T105 | /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2650078862 | May 05 12:24:21 PM PDT 24 | May 05 12:24:24 PM PDT 24 | 372484529 ps | ||
T125 | /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.540349885 | May 05 12:20:34 PM PDT 24 | May 05 12:20:35 PM PDT 24 | 145480566 ps | ||
T543 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.172010024 | May 05 12:24:00 PM PDT 24 | May 05 12:24:09 PM PDT 24 | 1548953074 ps | ||
T126 | /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2662344313 | May 05 12:24:49 PM PDT 24 | May 05 12:24:53 PM PDT 24 | 83038237 ps | ||
T544 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.874819284 | May 05 12:23:48 PM PDT 24 | May 05 12:23:51 PM PDT 24 | 347279245 ps | ||
T127 | /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2837908438 | May 05 12:22:08 PM PDT 24 | May 05 12:22:10 PM PDT 24 | 100984715 ps | ||
T545 | /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1738477221 | May 05 12:20:34 PM PDT 24 | May 05 12:20:38 PM PDT 24 | 888869604 ps | ||
T546 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2659687057 | May 05 12:24:00 PM PDT 24 | May 05 12:24:02 PM PDT 24 | 71945435 ps | ||
T547 | /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4041920639 | May 05 12:24:16 PM PDT 24 | May 05 12:24:20 PM PDT 24 | 208693814 ps | ||
T548 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.140911552 | May 05 12:20:08 PM PDT 24 | May 05 12:20:14 PM PDT 24 | 1193667673 ps | ||
T549 | /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2685862558 | May 05 12:20:08 PM PDT 24 | May 05 12:20:09 PM PDT 24 | 137532234 ps | ||
T106 | /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.340956028 | May 05 12:22:49 PM PDT 24 | May 05 12:22:52 PM PDT 24 | 217447960 ps | ||
T550 | /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1497096316 | May 05 12:24:13 PM PDT 24 | May 05 12:24:19 PM PDT 24 | 489044545 ps | ||
T551 | /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1256579457 | May 05 12:24:36 PM PDT 24 | May 05 12:24:39 PM PDT 24 | 161780164 ps | ||
T552 | /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3676101167 | May 05 12:24:34 PM PDT 24 | May 05 12:24:37 PM PDT 24 | 232540915 ps | ||
T553 | /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.519365263 | May 05 12:24:34 PM PDT 24 | May 05 12:24:38 PM PDT 24 | 412027453 ps | ||
T554 | /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1206584616 | May 05 12:22:23 PM PDT 24 | May 05 12:22:24 PM PDT 24 | 105688762 ps | ||
T555 | /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.564543903 | May 05 12:24:50 PM PDT 24 | May 05 12:24:57 PM PDT 24 | 245286780 ps | ||
T556 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3943059009 | May 05 12:21:44 PM PDT 24 | May 05 12:21:46 PM PDT 24 | 174777554 ps | ||
T557 | /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.450566484 | May 05 12:20:33 PM PDT 24 | May 05 12:20:34 PM PDT 24 | 83411675 ps | ||
T558 | /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1017023972 | May 05 12:24:20 PM PDT 24 | May 05 12:24:22 PM PDT 24 | 205108959 ps | ||
T559 | /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3561762850 | May 05 12:21:43 PM PDT 24 | May 05 12:21:45 PM PDT 24 | 72662768 ps | ||
T560 | /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3631056215 | May 05 12:24:38 PM PDT 24 | May 05 12:24:41 PM PDT 24 | 128744066 ps | ||
T561 | /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3161744640 | May 05 12:19:20 PM PDT 24 | May 05 12:19:25 PM PDT 24 | 868040844 ps | ||
T103 | /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3100879839 | May 05 12:21:28 PM PDT 24 | May 05 12:21:30 PM PDT 24 | 423034201 ps | ||
T562 | /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1161407812 | May 05 12:24:16 PM PDT 24 | May 05 12:24:19 PM PDT 24 | 57272044 ps | ||
T563 | /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3399403725 | May 05 12:22:00 PM PDT 24 | May 05 12:22:02 PM PDT 24 | 70529036 ps | ||
T564 | /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1571045924 | May 05 12:24:49 PM PDT 24 | May 05 12:24:52 PM PDT 24 | 65105396 ps | ||
T565 | /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.821121584 | May 05 12:20:15 PM PDT 24 | May 05 12:20:18 PM PDT 24 | 118067487 ps | ||
T566 | /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3136780658 | May 05 12:24:51 PM PDT 24 | May 05 12:24:56 PM PDT 24 | 134697522 ps | ||
T567 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.700484156 | May 05 12:24:30 PM PDT 24 | May 05 12:24:42 PM PDT 24 | 2300502940 ps | ||
T568 | /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3510120042 | May 05 12:21:50 PM PDT 24 | May 05 12:21:51 PM PDT 24 | 72242389 ps | ||
T569 | /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2951674233 | May 05 12:24:20 PM PDT 24 | May 05 12:24:22 PM PDT 24 | 73124388 ps | ||
T570 | /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.98970731 | May 05 12:20:55 PM PDT 24 | May 05 12:20:56 PM PDT 24 | 142359808 ps | ||
T571 | /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2072626915 | May 05 12:24:34 PM PDT 24 | May 05 12:24:37 PM PDT 24 | 160953429 ps | ||
T572 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.545178791 | May 05 12:20:34 PM PDT 24 | May 05 12:20:42 PM PDT 24 | 1568712725 ps | ||
T573 | /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.333479079 | May 05 12:20:01 PM PDT 24 | May 05 12:20:04 PM PDT 24 | 165107815 ps | ||
T574 | /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3096784852 | May 05 12:24:12 PM PDT 24 | May 05 12:24:17 PM PDT 24 | 80205992 ps | ||
T575 | /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2994309336 | May 05 12:24:00 PM PDT 24 | May 05 12:24:03 PM PDT 24 | 433528943 ps | ||
T576 | /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2556496425 | May 05 12:21:21 PM PDT 24 | May 05 12:21:25 PM PDT 24 | 606961901 ps | ||
T577 | /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.265354124 | May 05 12:24:10 PM PDT 24 | May 05 12:24:18 PM PDT 24 | 410571634 ps | ||
T578 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.318852791 | May 05 12:19:54 PM PDT 24 | May 05 12:19:56 PM PDT 24 | 227856059 ps | ||
T130 | /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.56976258 | May 05 12:21:33 PM PDT 24 | May 05 12:21:35 PM PDT 24 | 414626353 ps | ||
T579 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2894887746 | May 05 12:21:41 PM PDT 24 | May 05 12:21:43 PM PDT 24 | 117481162 ps | ||
T580 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3795647047 | May 05 12:23:54 PM PDT 24 | May 05 12:23:57 PM PDT 24 | 130198220 ps | ||
T581 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2162102849 | May 05 12:24:10 PM PDT 24 | May 05 12:24:15 PM PDT 24 | 95156040 ps | ||
T131 | /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.149318478 | May 05 12:24:04 PM PDT 24 | May 05 12:24:09 PM PDT 24 | 435532959 ps | ||
T582 | /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3907815430 | May 05 12:20:54 PM PDT 24 | May 05 12:20:57 PM PDT 24 | 615081354 ps | ||
T583 | /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.195459060 | May 05 12:21:43 PM PDT 24 | May 05 12:21:46 PM PDT 24 | 188415803 ps | ||
T584 | /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.193937352 | May 05 12:22:11 PM PDT 24 | May 05 12:22:13 PM PDT 24 | 104497133 ps | ||
T585 | /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3277403531 | May 05 12:20:57 PM PDT 24 | May 05 12:20:58 PM PDT 24 | 84410400 ps | ||
T586 | /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1832563060 | May 05 12:24:21 PM PDT 24 | May 05 12:24:23 PM PDT 24 | 80650963 ps | ||
T587 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3663468522 | May 05 12:20:13 PM PDT 24 | May 05 12:20:15 PM PDT 24 | 180278847 ps | ||
T588 | /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2841297142 | May 05 12:24:00 PM PDT 24 | May 05 12:24:02 PM PDT 24 | 109831440 ps | ||
T589 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.320596800 | May 05 12:20:46 PM PDT 24 | May 05 12:20:49 PM PDT 24 | 152492422 ps | ||
T590 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.731833400 | May 05 12:24:24 PM PDT 24 | May 05 12:24:34 PM PDT 24 | 1539333456 ps | ||
T591 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.395283389 | May 05 12:24:00 PM PDT 24 | May 05 12:24:02 PM PDT 24 | 208038832 ps | ||
T592 | /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2758486037 | May 05 12:21:17 PM PDT 24 | May 05 12:21:18 PM PDT 24 | 130941113 ps | ||
T593 | /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2652950992 | May 05 12:24:05 PM PDT 24 | May 05 12:24:11 PM PDT 24 | 138702344 ps | ||
T594 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.433925161 | May 05 12:24:04 PM PDT 24 | May 05 12:24:09 PM PDT 24 | 114192927 ps | ||
T595 | /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.542065374 | May 05 12:20:43 PM PDT 24 | May 05 12:20:44 PM PDT 24 | 81161096 ps | ||
T104 | /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.186501137 | May 05 12:21:26 PM PDT 24 | May 05 12:21:29 PM PDT 24 | 479205123 ps | ||
T99 | /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3429794572 | May 05 12:24:36 PM PDT 24 | May 05 12:24:41 PM PDT 24 | 890421362 ps | ||
T596 | /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2395964199 | May 05 12:24:03 PM PDT 24 | May 05 12:24:06 PM PDT 24 | 68283123 ps | ||
T597 | /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.200234974 | May 05 12:20:57 PM PDT 24 | May 05 12:20:58 PM PDT 24 | 117563481 ps | ||
T598 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.79754548 | May 05 12:24:40 PM PDT 24 | May 05 12:24:42 PM PDT 24 | 68249359 ps | ||
T599 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.622983781 | May 05 12:24:04 PM PDT 24 | May 05 12:24:08 PM PDT 24 | 73814290 ps | ||
T600 | /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3593766455 | May 05 12:19:59 PM PDT 24 | May 05 12:20:04 PM PDT 24 | 926960825 ps | ||
T601 | /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1352590584 | May 05 12:24:06 PM PDT 24 | May 05 12:24:12 PM PDT 24 | 81281667 ps | ||
T602 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4170044324 | May 05 12:24:05 PM PDT 24 | May 05 12:24:10 PM PDT 24 | 65740421 ps | ||
T603 | /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2870390812 | May 05 12:22:25 PM PDT 24 | May 05 12:22:29 PM PDT 24 | 872986756 ps | ||
T604 | /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1253890330 | May 05 12:22:36 PM PDT 24 | May 05 12:22:37 PM PDT 24 | 132612507 ps | ||
T605 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1519689044 | May 05 12:24:05 PM PDT 24 | May 05 12:24:10 PM PDT 24 | 97121547 ps | ||
T606 | /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2878587523 | May 05 12:24:05 PM PDT 24 | May 05 12:24:12 PM PDT 24 | 162360032 ps | ||
T607 | /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1591280110 | May 05 12:24:21 PM PDT 24 | May 05 12:24:23 PM PDT 24 | 78039895 ps | ||
T608 | /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2987792325 | May 05 12:24:14 PM PDT 24 | May 05 12:24:19 PM PDT 24 | 129272601 ps | ||
T609 | /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3216844124 | May 05 12:24:20 PM PDT 24 | May 05 12:24:24 PM PDT 24 | 273249757 ps | ||
T610 | /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2610869284 | May 05 12:20:10 PM PDT 24 | May 05 12:20:12 PM PDT 24 | 122775493 ps | ||
T97 | /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2724961581 | May 05 12:20:16 PM PDT 24 | May 05 12:20:19 PM PDT 24 | 891038655 ps | ||
T611 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2159641159 | May 05 12:23:51 PM PDT 24 | May 05 12:23:54 PM PDT 24 | 152734257 ps | ||
T612 | /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1586792619 | May 05 12:24:51 PM PDT 24 | May 05 12:24:57 PM PDT 24 | 459116527 ps | ||
T613 | /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1161837105 | May 05 12:20:44 PM PDT 24 | May 05 12:20:46 PM PDT 24 | 124207242 ps | ||
T614 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1223787671 | May 05 12:24:04 PM PDT 24 | May 05 12:24:09 PM PDT 24 | 359239622 ps | ||
T615 | /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2611573170 | May 05 12:23:47 PM PDT 24 | May 05 12:23:52 PM PDT 24 | 235990413 ps | ||
T616 | /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.673099980 | May 05 12:23:52 PM PDT 24 | May 05 12:23:55 PM PDT 24 | 135373829 ps | ||
T617 | /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3390986385 | May 05 12:20:16 PM PDT 24 | May 05 12:20:17 PM PDT 24 | 75234656 ps | ||
T618 | /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2482624621 | May 05 12:22:01 PM PDT 24 | May 05 12:22:04 PM PDT 24 | 805948635 ps | ||
T619 | /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1245428294 | May 05 12:24:16 PM PDT 24 | May 05 12:24:20 PM PDT 24 | 154867096 ps | ||
T620 | /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1399724058 | May 05 12:24:10 PM PDT 24 | May 05 12:24:16 PM PDT 24 | 137654608 ps |
Test location | /workspace/coverage/default/13.rstmgr_stress_all.1454640394 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 5382031499 ps |
CPU time | 22.95 seconds |
Started | May 05 12:25:11 PM PDT 24 |
Finished | May 05 12:25:35 PM PDT 24 |
Peak memory | 209240 kb |
Host | smart-97ef9c9f-280e-420c-8c18-4228ccdd2193 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454640394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1454640394 |
Directory | /workspace/13.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/27.rstmgr_sw_rst.918810158 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 123166342 ps |
CPU time | 1.57 seconds |
Started | May 05 12:25:34 PM PDT 24 |
Finished | May 05 12:25:36 PM PDT 24 |
Peak memory | 200812 kb |
Host | smart-b098fe6e-8dd8-4462-abb9-ea2d5076fced |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918810158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.918810158 |
Directory | /workspace/27.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2314078328 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 127405437 ps |
CPU time | 1.44 seconds |
Started | May 05 12:24:21 PM PDT 24 |
Finished | May 05 12:24:24 PM PDT 24 |
Peak memory | 208796 kb |
Host | smart-b0745336-bc3b-48e2-92ee-84c589d0e6e2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314078328 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2314078328 |
Directory | /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rstmgr_sec_cm.3520327486 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 16865258447 ps |
CPU time | 24.79 seconds |
Started | May 05 12:21:12 PM PDT 24 |
Finished | May 05 12:21:37 PM PDT 24 |
Peak memory | 218560 kb |
Host | smart-2d0a296d-89dc-4070-8148-86d82db52a77 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520327486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3520327486 |
Directory | /workspace/0.rstmgr_sec_cm/latest |
Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2259492754 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1225296887 ps |
CPU time | 5.25 seconds |
Started | May 05 12:25:01 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 217760 kb |
Host | smart-da455486-e0ee-463a-99c9-2921d6bd1bd8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259492754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2259492754 |
Directory | /workspace/11.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/19.rstmgr_stress_all.1732196341 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 10731913330 ps |
CPU time | 37.78 seconds |
Started | May 05 12:25:17 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 201024 kb |
Host | smart-58ddf448-9b94-4805-856a-6a4a1651d6ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732196341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1732196341 |
Directory | /workspace/19.rstmgr_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.713717656 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 801992435 ps |
CPU time | 3.08 seconds |
Started | May 05 12:21:51 PM PDT 24 |
Finished | May 05 12:21:55 PM PDT 24 |
Peak memory | 200520 kb |
Host | smart-37241d65-bf4d-4e73-8965-4cf545c27795 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713717656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err .713717656 |
Directory | /workspace/17.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/10.rstmgr_alert_test.90459022 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 63695651 ps |
CPU time | 0.85 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:24:51 PM PDT 24 |
Peak memory | 200536 kb |
Host | smart-26c0c247-7216-4960-9fa6-8b5e0ca158c0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90459022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.90459022 |
Directory | /workspace/10.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2707235758 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 184490314 ps |
CPU time | 1.22 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:06 PM PDT 24 |
Peak memory | 200684 kb |
Host | smart-028df2eb-a4d5-436e-aa4c-407689c8b966 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707235758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2707235758 |
Directory | /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3909602393 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 1230535085 ps |
CPU time | 5.91 seconds |
Started | May 05 12:25:17 PM PDT 24 |
Finished | May 05 12:25:24 PM PDT 24 |
Peak memory | 218328 kb |
Host | smart-0e9a2b4e-3ebe-4852-9093-9e602fa76aa7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909602393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3909602393 |
Directory | /workspace/19.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2650078862 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 372484529 ps |
CPU time | 2.74 seconds |
Started | May 05 12:24:21 PM PDT 24 |
Finished | May 05 12:24:24 PM PDT 24 |
Peak memory | 212444 kb |
Host | smart-bcd4e3ca-75fe-4974-a811-0f07156ee8d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650078862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2650078862 |
Directory | /workspace/7.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4249549268 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 116326223 ps |
CPU time | 0.92 seconds |
Started | May 05 12:25:05 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 200744 kb |
Host | smart-efbfde68-ab5b-4cfc-a961-46d5c88054ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249549268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4249549268 |
Directory | /workspace/4.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3678707680 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 215652775 ps |
CPU time | 1.44 seconds |
Started | May 05 12:24:12 PM PDT 24 |
Finished | May 05 12:24:18 PM PDT 24 |
Peak memory | 199152 kb |
Host | smart-d6df7c32-b122-444e-bdec-fe24c74125e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678707680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s ame_csr_outstanding.3678707680 |
Directory | /workspace/10.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3100879839 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 423034201 ps |
CPU time | 1.69 seconds |
Started | May 05 12:21:28 PM PDT 24 |
Finished | May 05 12:21:30 PM PDT 24 |
Peak memory | 200792 kb |
Host | smart-b97ac372-74d7-4432-8172-964efa272df8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100879839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er r.3100879839 |
Directory | /workspace/18.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3892156342 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 2182424835 ps |
CPU time | 8.7 seconds |
Started | May 05 12:25:12 PM PDT 24 |
Finished | May 05 12:25:22 PM PDT 24 |
Peak memory | 222464 kb |
Host | smart-8e93c681-8f1c-417d-977f-05a9de2db579 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3892156342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3892156342 |
Directory | /workspace/16.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3631056215 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 128744066 ps |
CPU time | 1.39 seconds |
Started | May 05 12:24:38 PM PDT 24 |
Finished | May 05 12:24:41 PM PDT 24 |
Peak memory | 208336 kb |
Host | smart-d014d77a-7a1d-4fb4-a061-0eac55ab3227 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631056215 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3631056215 |
Directory | /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rstmgr_por_stretcher.965289842 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 195983777 ps |
CPU time | 0.94 seconds |
Started | May 05 12:23:51 PM PDT 24 |
Finished | May 05 12:23:54 PM PDT 24 |
Peak memory | 199464 kb |
Host | smart-effa9464-4712-4c74-bb5d-9ce658184926 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965289842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.965289842 |
Directory | /workspace/0.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.918766458 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 244316903 ps |
CPU time | 1.03 seconds |
Started | May 05 12:25:02 PM PDT 24 |
Finished | May 05 12:25:04 PM PDT 24 |
Peak memory | 218060 kb |
Host | smart-7cc91051-0dc6-4ef3-bdd3-34a7029f19ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918766458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.918766458 |
Directory | /workspace/17.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2724961581 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 891038655 ps |
CPU time | 3.08 seconds |
Started | May 05 12:20:16 PM PDT 24 |
Finished | May 05 12:20:19 PM PDT 24 |
Peak memory | 200508 kb |
Host | smart-eab22e65-ed0c-49bd-bdf5-11ae24ea09c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724961581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err .2724961581 |
Directory | /workspace/2.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.433925161 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 114192927 ps |
CPU time | 1.36 seconds |
Started | May 05 12:24:04 PM PDT 24 |
Finished | May 05 12:24:09 PM PDT 24 |
Peak memory | 198680 kb |
Host | smart-fbc1c0cd-0a01-4d9d-8ec2-ee4ae8bc955a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433925161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.433925161 |
Directory | /workspace/0.rstmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.731833400 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 1539333456 ps |
CPU time | 8.19 seconds |
Started | May 05 12:24:24 PM PDT 24 |
Finished | May 05 12:24:34 PM PDT 24 |
Peak memory | 207492 kb |
Host | smart-b92353c3-6912-4ac0-95b5-dd6df72c27cd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731833400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.731833400 |
Directory | /workspace/0.rstmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2159641159 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 152734257 ps |
CPU time | 1.01 seconds |
Started | May 05 12:23:51 PM PDT 24 |
Finished | May 05 12:23:54 PM PDT 24 |
Peak memory | 198712 kb |
Host | smart-de234812-e6f7-4383-9dda-0ae0592532d6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159641159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2 159641159 |
Directory | /workspace/0.rstmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3663468522 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 180278847 ps |
CPU time | 1.24 seconds |
Started | May 05 12:20:13 PM PDT 24 |
Finished | May 05 12:20:15 PM PDT 24 |
Peak memory | 208540 kb |
Host | smart-516dba88-dbf0-43a8-9536-44d986794e55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663468522 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3663468522 |
Directory | /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.79754548 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 68249359 ps |
CPU time | 0.78 seconds |
Started | May 05 12:24:40 PM PDT 24 |
Finished | May 05 12:24:42 PM PDT 24 |
Peak memory | 200060 kb |
Host | smart-38e58851-6253-4399-9979-925a8ce1e8d5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79754548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.79754548 |
Directory | /workspace/0.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1352590584 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 81281667 ps |
CPU time | 0.96 seconds |
Started | May 05 12:24:06 PM PDT 24 |
Finished | May 05 12:24:12 PM PDT 24 |
Peak memory | 199932 kb |
Host | smart-7e06c90b-6f98-41b4-971e-60472e6b77eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352590584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa me_csr_outstanding.1352590584 |
Directory | /workspace/0.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1586634275 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 213533964 ps |
CPU time | 1.95 seconds |
Started | May 05 12:24:05 PM PDT 24 |
Finished | May 05 12:24:10 PM PDT 24 |
Peak memory | 208384 kb |
Host | smart-feb48e4b-bcf1-470a-a52c-bc47a0674e9f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586634275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1586634275 |
Directory | /workspace/0.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3593766455 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 926960825 ps |
CPU time | 3.57 seconds |
Started | May 05 12:19:59 PM PDT 24 |
Finished | May 05 12:20:04 PM PDT 24 |
Peak memory | 200452 kb |
Host | smart-ef0451de-bee7-470b-8b66-06f003563770 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593766455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err .3593766455 |
Directory | /workspace/0.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1223787671 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 359239622 ps |
CPU time | 2.56 seconds |
Started | May 05 12:24:04 PM PDT 24 |
Finished | May 05 12:24:09 PM PDT 24 |
Peak memory | 199552 kb |
Host | smart-b29134a1-83c6-4c5b-b0b4-7b9dd595eac5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223787671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1 223787671 |
Directory | /workspace/1.rstmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.140911552 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 1193667673 ps |
CPU time | 4.97 seconds |
Started | May 05 12:20:08 PM PDT 24 |
Finished | May 05 12:20:14 PM PDT 24 |
Peak memory | 200428 kb |
Host | smart-88184572-5023-4b17-8633-d79d5ad36449 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140911552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.140911552 |
Directory | /workspace/1.rstmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1746373653 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 138153234 ps |
CPU time | 1.01 seconds |
Started | May 05 12:19:55 PM PDT 24 |
Finished | May 05 12:19:57 PM PDT 24 |
Peak memory | 200528 kb |
Host | smart-b74dfa54-62aa-4ce4-9397-5b095b369def |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746373653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1 746373653 |
Directory | /workspace/1.rstmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.318852791 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 227856059 ps |
CPU time | 1.35 seconds |
Started | May 05 12:19:54 PM PDT 24 |
Finished | May 05 12:19:56 PM PDT 24 |
Peak memory | 209012 kb |
Host | smart-048186c9-f674-455a-b94a-cce4a1d304a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318852791 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.318852791 |
Directory | /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.622983781 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 73814290 ps |
CPU time | 0.84 seconds |
Started | May 05 12:24:04 PM PDT 24 |
Finished | May 05 12:24:08 PM PDT 24 |
Peak memory | 198632 kb |
Host | smart-795102ad-49c7-4d48-9984-43cf8853e1d0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622983781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.622983781 |
Directory | /workspace/1.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1399724058 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 137654608 ps |
CPU time | 1.3 seconds |
Started | May 05 12:24:10 PM PDT 24 |
Finished | May 05 12:24:16 PM PDT 24 |
Peak memory | 200396 kb |
Host | smart-34bd1367-4049-41d6-9e38-6831f40396c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399724058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa me_csr_outstanding.1399724058 |
Directory | /workspace/1.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2878587523 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 162360032 ps |
CPU time | 2.15 seconds |
Started | May 05 12:24:05 PM PDT 24 |
Finished | May 05 12:24:12 PM PDT 24 |
Peak memory | 208384 kb |
Host | smart-8fce9d5a-f9eb-44fd-b2b6-6d67e1493303 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878587523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2878587523 |
Directory | /workspace/1.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2994309336 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 433528943 ps |
CPU time | 1.83 seconds |
Started | May 05 12:24:00 PM PDT 24 |
Finished | May 05 12:24:03 PM PDT 24 |
Peak memory | 199416 kb |
Host | smart-3ce4a015-bd58-4312-aeac-4b3925a2bf0d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994309336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err .2994309336 |
Directory | /workspace/1.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.195459060 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 188415803 ps |
CPU time | 1.98 seconds |
Started | May 05 12:21:43 PM PDT 24 |
Finished | May 05 12:21:46 PM PDT 24 |
Peak memory | 208740 kb |
Host | smart-578c9ac3-59aa-46da-b51f-5e08c8f12872 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195459060 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.195459060 |
Directory | /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2662344313 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 83038237 ps |
CPU time | 0.81 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:24:53 PM PDT 24 |
Peak memory | 199896 kb |
Host | smart-65c0237a-fab4-40ba-b268-7266ab2bc3cc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662344313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2662344313 |
Directory | /workspace/10.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.340956028 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 217447960 ps |
CPU time | 2.94 seconds |
Started | May 05 12:22:49 PM PDT 24 |
Finished | May 05 12:22:52 PM PDT 24 |
Peak memory | 208628 kb |
Host | smart-20e355b7-4d2e-49d9-a807-dfe30e06b147 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340956028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.340956028 |
Directory | /workspace/10.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.56976258 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 414626353 ps |
CPU time | 1.76 seconds |
Started | May 05 12:21:33 PM PDT 24 |
Finished | May 05 12:21:35 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-1aca37bf-17f0-485d-871d-0d953768193a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56976258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.56976258 |
Directory | /workspace/10.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.333479079 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 165107815 ps |
CPU time | 1.56 seconds |
Started | May 05 12:20:01 PM PDT 24 |
Finished | May 05 12:20:04 PM PDT 24 |
Peak memory | 208672 kb |
Host | smart-02906c75-d451-4bb6-9b52-58df61f301f4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333479079 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.333479079 |
Directory | /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3096784852 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 80205992 ps |
CPU time | 0.86 seconds |
Started | May 05 12:24:12 PM PDT 24 |
Finished | May 05 12:24:17 PM PDT 24 |
Peak memory | 198544 kb |
Host | smart-ea9ad366-90cd-46d4-9474-4f232bdb0311 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096784852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3096784852 |
Directory | /workspace/11.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2758486037 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 130941113 ps |
CPU time | 1.14 seconds |
Started | May 05 12:21:17 PM PDT 24 |
Finished | May 05 12:21:18 PM PDT 24 |
Peak memory | 200304 kb |
Host | smart-cfa1d652-4162-4f47-af41-599d87f87fd2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758486037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s ame_csr_outstanding.2758486037 |
Directory | /workspace/11.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1172078363 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 198244652 ps |
CPU time | 1.77 seconds |
Started | May 05 12:24:05 PM PDT 24 |
Finished | May 05 12:24:10 PM PDT 24 |
Peak memory | 208276 kb |
Host | smart-2b8a72ba-d7c7-4219-882a-88bdd6142bd9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172078363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1172078363 |
Directory | /workspace/11.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1593970403 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 439614796 ps |
CPU time | 1.85 seconds |
Started | May 05 12:22:47 PM PDT 24 |
Finished | May 05 12:22:50 PM PDT 24 |
Peak memory | 200528 kb |
Host | smart-11cedb8d-b769-493e-a31b-9d767a9dd81c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593970403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er r.1593970403 |
Directory | /workspace/11.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2072626915 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 160953429 ps |
CPU time | 1.34 seconds |
Started | May 05 12:24:34 PM PDT 24 |
Finished | May 05 12:24:37 PM PDT 24 |
Peak memory | 206736 kb |
Host | smart-06dec1b6-117e-4903-93f5-497ce6005d8c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072626915 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2072626915 |
Directory | /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3561762850 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 72662768 ps |
CPU time | 0.84 seconds |
Started | May 05 12:21:43 PM PDT 24 |
Finished | May 05 12:21:45 PM PDT 24 |
Peak memory | 200180 kb |
Host | smart-52766e89-bc8f-4917-8597-188ca1b804ec |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561762850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3561762850 |
Directory | /workspace/12.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.540349885 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 145480566 ps |
CPU time | 1.19 seconds |
Started | May 05 12:20:34 PM PDT 24 |
Finished | May 05 12:20:35 PM PDT 24 |
Peak memory | 200236 kb |
Host | smart-2e71391e-cfa3-4168-afd2-6738d7fbec73 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540349885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa me_csr_outstanding.540349885 |
Directory | /workspace/12.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1161837105 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 124207242 ps |
CPU time | 1.85 seconds |
Started | May 05 12:20:44 PM PDT 24 |
Finished | May 05 12:20:46 PM PDT 24 |
Peak memory | 208652 kb |
Host | smart-902e837e-f5a7-4b21-995c-f6f5e03e68b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161837105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1161837105 |
Directory | /workspace/12.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1497096316 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 489044545 ps |
CPU time | 2.04 seconds |
Started | May 05 12:24:13 PM PDT 24 |
Finished | May 05 12:24:19 PM PDT 24 |
Peak memory | 199144 kb |
Host | smart-9106daf2-feda-4faa-95fe-735c4d416ecb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497096316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er r.1497096316 |
Directory | /workspace/12.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2610869284 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 122775493 ps |
CPU time | 1.05 seconds |
Started | May 05 12:20:10 PM PDT 24 |
Finished | May 05 12:20:12 PM PDT 24 |
Peak memory | 200268 kb |
Host | smart-24e46c01-5efe-426d-a9e5-01dbaeb1fc53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610869284 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2610869284 |
Directory | /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.542065374 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 81161096 ps |
CPU time | 0.88 seconds |
Started | May 05 12:20:43 PM PDT 24 |
Finished | May 05 12:20:44 PM PDT 24 |
Peak memory | 200216 kb |
Host | smart-365ac22a-aab9-497c-a34e-3586104a2e07 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542065374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.542065374 |
Directory | /workspace/13.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3676101167 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 232540915 ps |
CPU time | 1.74 seconds |
Started | May 05 12:24:34 PM PDT 24 |
Finished | May 05 12:24:37 PM PDT 24 |
Peak memory | 200204 kb |
Host | smart-bfe85fc9-128b-4f82-92ac-73575810f9e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676101167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s ame_csr_outstanding.3676101167 |
Directory | /workspace/13.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.519365263 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 412027453 ps |
CPU time | 2.78 seconds |
Started | May 05 12:24:34 PM PDT 24 |
Finished | May 05 12:24:38 PM PDT 24 |
Peak memory | 208388 kb |
Host | smart-ca582d58-29cc-45e2-8e83-a1f1f6a90a08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519365263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.519365263 |
Directory | /workspace/13.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.186501137 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 479205123 ps |
CPU time | 1.99 seconds |
Started | May 05 12:21:26 PM PDT 24 |
Finished | May 05 12:21:29 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-c3ebfd86-3975-4024-af26-74a1655ccc8a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186501137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err .186501137 |
Directory | /workspace/13.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1256579457 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 161780164 ps |
CPU time | 1.42 seconds |
Started | May 05 12:24:36 PM PDT 24 |
Finished | May 05 12:24:39 PM PDT 24 |
Peak memory | 212176 kb |
Host | smart-e91895e4-f14a-4211-ba7f-f891a8e9706b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256579457 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1256579457 |
Directory | /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2395964199 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 68283123 ps |
CPU time | 0.81 seconds |
Started | May 05 12:24:03 PM PDT 24 |
Finished | May 05 12:24:06 PM PDT 24 |
Peak memory | 199904 kb |
Host | smart-a1320e7a-ddb1-4baa-adb1-4c0e289fa8b9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395964199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2395964199 |
Directory | /workspace/14.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.98970731 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 142359808 ps |
CPU time | 1.2 seconds |
Started | May 05 12:20:55 PM PDT 24 |
Finished | May 05 12:20:56 PM PDT 24 |
Peak memory | 200312 kb |
Host | smart-832b3c0e-5d11-4105-b42a-89fb8d9e191c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98970731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sam e_csr_outstanding.98970731 |
Directory | /workspace/14.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2618247739 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 469080089 ps |
CPU time | 3.4 seconds |
Started | May 05 12:20:50 PM PDT 24 |
Finished | May 05 12:20:54 PM PDT 24 |
Peak memory | 208744 kb |
Host | smart-ce331bdb-0439-43a3-858f-41889bd74e9b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618247739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2618247739 |
Directory | /workspace/14.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3907815430 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 615081354 ps |
CPU time | 2.2 seconds |
Started | May 05 12:20:54 PM PDT 24 |
Finished | May 05 12:20:57 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-22348303-9c6e-455b-aa7e-a00b6917d391 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907815430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er r.3907815430 |
Directory | /workspace/14.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3390986385 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 75234656 ps |
CPU time | 0.81 seconds |
Started | May 05 12:20:16 PM PDT 24 |
Finished | May 05 12:20:17 PM PDT 24 |
Peak memory | 200168 kb |
Host | smart-c7032161-c9f9-4360-a565-fe00071d74b8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390986385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3390986385 |
Directory | /workspace/15.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3136780658 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 134697522 ps |
CPU time | 1.23 seconds |
Started | May 05 12:24:51 PM PDT 24 |
Finished | May 05 12:24:56 PM PDT 24 |
Peak memory | 200436 kb |
Host | smart-a869cc59-0ff6-4895-8819-aec52bcfdea7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136780658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s ame_csr_outstanding.3136780658 |
Directory | /workspace/15.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3216844124 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 273249757 ps |
CPU time | 2.02 seconds |
Started | May 05 12:24:20 PM PDT 24 |
Finished | May 05 12:24:24 PM PDT 24 |
Peak memory | 207752 kb |
Host | smart-8d61961d-de41-4d9f-9569-2989f9051ece |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216844124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3216844124 |
Directory | /workspace/15.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3429794572 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 890421362 ps |
CPU time | 3.36 seconds |
Started | May 05 12:24:36 PM PDT 24 |
Finished | May 05 12:24:41 PM PDT 24 |
Peak memory | 200444 kb |
Host | smart-12347f6a-1654-471d-9ba2-c0c866cd2498 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429794572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er r.3429794572 |
Directory | /workspace/15.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2550127183 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 116406421 ps |
CPU time | 1.1 seconds |
Started | May 05 12:23:49 PM PDT 24 |
Finished | May 05 12:23:51 PM PDT 24 |
Peak memory | 208120 kb |
Host | smart-994a10ac-c35f-4760-8898-ba1668e00573 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550127183 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2550127183 |
Directory | /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3510120042 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 72242389 ps |
CPU time | 0.79 seconds |
Started | May 05 12:21:50 PM PDT 24 |
Finished | May 05 12:21:51 PM PDT 24 |
Peak memory | 200264 kb |
Host | smart-fff4fe59-f3a0-4dcc-a5e9-630a5c033bf0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510120042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3510120042 |
Directory | /workspace/16.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2951674233 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 73124388 ps |
CPU time | 0.92 seconds |
Started | May 05 12:24:20 PM PDT 24 |
Finished | May 05 12:24:22 PM PDT 24 |
Peak memory | 200268 kb |
Host | smart-5d0b5e99-755f-4127-a35e-a306ee7952d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951674233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s ame_csr_outstanding.2951674233 |
Directory | /workspace/16.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1586792619 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 459116527 ps |
CPU time | 3.01 seconds |
Started | May 05 12:24:51 PM PDT 24 |
Finished | May 05 12:24:57 PM PDT 24 |
Peak memory | 208564 kb |
Host | smart-6da9e3fe-2bde-42aa-9290-cab9c60d8b57 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586792619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1586792619 |
Directory | /workspace/16.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2870390812 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 872986756 ps |
CPU time | 3.07 seconds |
Started | May 05 12:22:25 PM PDT 24 |
Finished | May 05 12:22:29 PM PDT 24 |
Peak memory | 200568 kb |
Host | smart-7216ed34-2459-4076-a4f2-c1680aaa2d09 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870390812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er r.2870390812 |
Directory | /workspace/16.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1591280110 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 78039895 ps |
CPU time | 0.78 seconds |
Started | May 05 12:24:21 PM PDT 24 |
Finished | May 05 12:24:23 PM PDT 24 |
Peak memory | 200208 kb |
Host | smart-1978ac35-002c-4bf7-980e-40798666b9fd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591280110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1591280110 |
Directory | /workspace/17.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2837908438 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 100984715 ps |
CPU time | 1.27 seconds |
Started | May 05 12:22:08 PM PDT 24 |
Finished | May 05 12:22:10 PM PDT 24 |
Peak memory | 200524 kb |
Host | smart-b590e4cc-0857-4447-a910-725f73ec7754 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837908438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s ame_csr_outstanding.2837908438 |
Directory | /workspace/17.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.416393162 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 112374161 ps |
CPU time | 1.52 seconds |
Started | May 05 12:23:48 PM PDT 24 |
Finished | May 05 12:23:51 PM PDT 24 |
Peak memory | 207408 kb |
Host | smart-a103a58e-4cb8-4dec-bf5d-0cbfffd37b5f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416393162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.416393162 |
Directory | /workspace/17.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1206584616 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 105688762 ps |
CPU time | 1 seconds |
Started | May 05 12:22:23 PM PDT 24 |
Finished | May 05 12:22:24 PM PDT 24 |
Peak memory | 200412 kb |
Host | smart-bd25307d-a7d8-4221-996a-0fb53d9387ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206584616 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1206584616 |
Directory | /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.436962647 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 61946451 ps |
CPU time | 0.76 seconds |
Started | May 05 12:24:52 PM PDT 24 |
Finished | May 05 12:24:56 PM PDT 24 |
Peak memory | 200108 kb |
Host | smart-84687d0b-1453-490e-b03f-410dd4926638 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436962647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.436962647 |
Directory | /workspace/18.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1529558968 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 82984716 ps |
CPU time | 0.96 seconds |
Started | May 05 12:22:25 PM PDT 24 |
Finished | May 05 12:22:27 PM PDT 24 |
Peak memory | 200292 kb |
Host | smart-e364f8d3-2b80-4d07-9071-4f2e2bc8a0c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529558968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s ame_csr_outstanding.1529558968 |
Directory | /workspace/18.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2556496425 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 606961901 ps |
CPU time | 3.87 seconds |
Started | May 05 12:21:21 PM PDT 24 |
Finished | May 05 12:21:25 PM PDT 24 |
Peak memory | 216808 kb |
Host | smart-0b35a241-9d95-48d2-b2ea-2d2e45cbc98d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556496425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2556496425 |
Directory | /workspace/18.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.200234974 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 117563481 ps |
CPU time | 1.02 seconds |
Started | May 05 12:20:57 PM PDT 24 |
Finished | May 05 12:20:58 PM PDT 24 |
Peak memory | 200372 kb |
Host | smart-5a20260e-bf75-424c-92ce-16aa4a23c21a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200234974 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.200234974 |
Directory | /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1107559904 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 72743999 ps |
CPU time | 0.75 seconds |
Started | May 05 12:20:07 PM PDT 24 |
Finished | May 05 12:20:08 PM PDT 24 |
Peak memory | 200212 kb |
Host | smart-b7dc0a41-2459-4267-a358-47251eb727a5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107559904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1107559904 |
Directory | /workspace/19.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2258293997 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 98615401 ps |
CPU time | 1.18 seconds |
Started | May 05 12:24:50 PM PDT 24 |
Finished | May 05 12:24:55 PM PDT 24 |
Peak memory | 200240 kb |
Host | smart-5b732eb9-2302-41dc-be44-10e5302ed9cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258293997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s ame_csr_outstanding.2258293997 |
Directory | /workspace/19.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2481643774 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 478113533 ps |
CPU time | 3.39 seconds |
Started | May 05 12:21:27 PM PDT 24 |
Finished | May 05 12:21:31 PM PDT 24 |
Peak memory | 208600 kb |
Host | smart-d621a92f-7784-48a5-8100-14164336e07c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481643774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2481643774 |
Directory | /workspace/19.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1055983650 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 888907097 ps |
CPU time | 3.23 seconds |
Started | May 05 12:19:25 PM PDT 24 |
Finished | May 05 12:19:29 PM PDT 24 |
Peak memory | 200444 kb |
Host | smart-96706ca2-06d2-4611-b4bf-75285657c820 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055983650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er r.1055983650 |
Directory | /workspace/19.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.320596800 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 152492422 ps |
CPU time | 2.02 seconds |
Started | May 05 12:20:46 PM PDT 24 |
Finished | May 05 12:20:49 PM PDT 24 |
Peak memory | 200412 kb |
Host | smart-7c6ea26f-0c36-4013-8e6c-763fd24ed0fc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320596800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.320596800 |
Directory | /workspace/2.rstmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.700484156 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 2300502940 ps |
CPU time | 10.62 seconds |
Started | May 05 12:24:30 PM PDT 24 |
Finished | May 05 12:24:42 PM PDT 24 |
Peak memory | 199488 kb |
Host | smart-ac5cbb0e-4dce-4f5e-aaa1-8c006b71dc43 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700484156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.700484156 |
Directory | /workspace/2.rstmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1519689044 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 97121547 ps |
CPU time | 0.83 seconds |
Started | May 05 12:24:05 PM PDT 24 |
Finished | May 05 12:24:10 PM PDT 24 |
Peak memory | 199896 kb |
Host | smart-6db3d7b3-fa0d-4045-b9f7-dd7ac4379299 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519689044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1 519689044 |
Directory | /workspace/2.rstmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3648519391 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 163649110 ps |
CPU time | 1.47 seconds |
Started | May 05 12:24:10 PM PDT 24 |
Finished | May 05 12:24:16 PM PDT 24 |
Peak memory | 208740 kb |
Host | smart-4ed23e02-0141-4b11-8c23-75cc92acf4ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648519391 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3648519391 |
Directory | /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4170044324 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 65740421 ps |
CPU time | 0.74 seconds |
Started | May 05 12:24:05 PM PDT 24 |
Finished | May 05 12:24:10 PM PDT 24 |
Peak memory | 199916 kb |
Host | smart-928030cf-eb6d-4d30-b0bc-631045bc4d76 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170044324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.4170044324 |
Directory | /workspace/2.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2652950992 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 138702344 ps |
CPU time | 1.08 seconds |
Started | May 05 12:24:05 PM PDT 24 |
Finished | May 05 12:24:11 PM PDT 24 |
Peak memory | 199976 kb |
Host | smart-0d6861d8-443a-47d9-95b1-6dde4c3ce717 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652950992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa me_csr_outstanding.2652950992 |
Directory | /workspace/2.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.265354124 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 410571634 ps |
CPU time | 3.02 seconds |
Started | May 05 12:24:10 PM PDT 24 |
Finished | May 05 12:24:18 PM PDT 24 |
Peak memory | 208652 kb |
Host | smart-62148fcd-8388-4d22-be41-cc332c31bd02 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265354124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.265354124 |
Directory | /workspace/2.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.395283389 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 208038832 ps |
CPU time | 1.58 seconds |
Started | May 05 12:24:00 PM PDT 24 |
Finished | May 05 12:24:02 PM PDT 24 |
Peak memory | 199860 kb |
Host | smart-85e06cc6-afe3-4ccc-ba14-4b968f499343 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395283389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.395283389 |
Directory | /workspace/3.rstmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.545178791 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 1568712725 ps |
CPU time | 8.11 seconds |
Started | May 05 12:20:34 PM PDT 24 |
Finished | May 05 12:20:42 PM PDT 24 |
Peak memory | 200412 kb |
Host | smart-3af190f2-6d65-4a07-9ca2-22f9d0358061 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545178791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.545178791 |
Directory | /workspace/3.rstmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2162102849 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 95156040 ps |
CPU time | 0.82 seconds |
Started | May 05 12:24:10 PM PDT 24 |
Finished | May 05 12:24:15 PM PDT 24 |
Peak memory | 199924 kb |
Host | smart-5a387a5d-3331-4d61-80c3-de6013c28b76 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162102849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2 162102849 |
Directory | /workspace/3.rstmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3795647047 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 130198220 ps |
CPU time | 1.08 seconds |
Started | May 05 12:23:54 PM PDT 24 |
Finished | May 05 12:23:57 PM PDT 24 |
Peak memory | 208512 kb |
Host | smart-b41c8709-bd0b-494c-86d4-f3a15569bb60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795647047 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3795647047 |
Directory | /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1150906126 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 71902380 ps |
CPU time | 0.84 seconds |
Started | May 05 12:24:04 PM PDT 24 |
Finished | May 05 12:24:09 PM PDT 24 |
Peak memory | 199812 kb |
Host | smart-e32ccd8b-8f66-479b-bbe2-1a8a30febdb9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150906126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1150906126 |
Directory | /workspace/3.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.450566484 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 83411675 ps |
CPU time | 0.99 seconds |
Started | May 05 12:20:33 PM PDT 24 |
Finished | May 05 12:20:34 PM PDT 24 |
Peak memory | 200240 kb |
Host | smart-4ea2a988-2a0e-4744-a87c-a280fbb10c81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450566484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam e_csr_outstanding.450566484 |
Directory | /workspace/3.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2841297142 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 109831440 ps |
CPU time | 1.49 seconds |
Started | May 05 12:24:00 PM PDT 24 |
Finished | May 05 12:24:02 PM PDT 24 |
Peak memory | 207084 kb |
Host | smart-9edceedc-1b47-4688-9b83-7a32f7b324e2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841297142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2841297142 |
Directory | /workspace/3.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.149318478 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 435532959 ps |
CPU time | 1.67 seconds |
Started | May 05 12:24:04 PM PDT 24 |
Finished | May 05 12:24:09 PM PDT 24 |
Peak memory | 200040 kb |
Host | smart-26189a35-1756-4271-a1f0-072da44e8aab |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149318478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err. 149318478 |
Directory | /workspace/3.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.874819284 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 347279245 ps |
CPU time | 2.28 seconds |
Started | May 05 12:23:48 PM PDT 24 |
Finished | May 05 12:23:51 PM PDT 24 |
Peak memory | 200212 kb |
Host | smart-e9dcde33-2354-4f48-9fe6-968d95234f1d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874819284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.874819284 |
Directory | /workspace/4.rstmgr_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.172010024 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 1548953074 ps |
CPU time | 8.39 seconds |
Started | May 05 12:24:00 PM PDT 24 |
Finished | May 05 12:24:09 PM PDT 24 |
Peak memory | 198816 kb |
Host | smart-61121ec6-5220-4807-8f5a-0552431d951d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172010024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.172010024 |
Directory | /workspace/4.rstmgr_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2894887746 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 117481162 ps |
CPU time | 0.89 seconds |
Started | May 05 12:21:41 PM PDT 24 |
Finished | May 05 12:21:43 PM PDT 24 |
Peak memory | 200244 kb |
Host | smart-bba89986-3ffb-4bdf-b0ea-3c444872b003 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894887746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2 894887746 |
Directory | /workspace/4.rstmgr_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3943059009 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 174777554 ps |
CPU time | 1.21 seconds |
Started | May 05 12:21:44 PM PDT 24 |
Finished | May 05 12:21:46 PM PDT 24 |
Peak memory | 208556 kb |
Host | smart-0591390b-9e49-44c6-afd5-bc6f4045dcbd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943059009 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3943059009 |
Directory | /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2659687057 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 71945435 ps |
CPU time | 0.81 seconds |
Started | May 05 12:24:00 PM PDT 24 |
Finished | May 05 12:24:02 PM PDT 24 |
Peak memory | 199808 kb |
Host | smart-2df4e799-cada-416f-9f88-f55f56c3caa9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659687057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2659687057 |
Directory | /workspace/4.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3979439603 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 97354988 ps |
CPU time | 1.28 seconds |
Started | May 05 12:21:41 PM PDT 24 |
Finished | May 05 12:21:43 PM PDT 24 |
Peak memory | 200480 kb |
Host | smart-ea3d6f6c-e086-440e-8eff-efb3e9efcd94 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979439603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa me_csr_outstanding.3979439603 |
Directory | /workspace/4.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.821121584 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 118067487 ps |
CPU time | 1.59 seconds |
Started | May 05 12:20:15 PM PDT 24 |
Finished | May 05 12:20:18 PM PDT 24 |
Peak memory | 200396 kb |
Host | smart-f6103b32-8f02-4be7-9d31-80e9ca7f3de6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821121584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.821121584 |
Directory | /workspace/4.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.609487812 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 822789004 ps |
CPU time | 2.93 seconds |
Started | May 05 12:20:40 PM PDT 24 |
Finished | May 05 12:20:44 PM PDT 24 |
Peak memory | 200488 kb |
Host | smart-3601bca3-9725-4c67-9bc9-b93811233617 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609487812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err. 609487812 |
Directory | /workspace/4.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2987792325 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 129272601 ps |
CPU time | 1.11 seconds |
Started | May 05 12:24:14 PM PDT 24 |
Finished | May 05 12:24:19 PM PDT 24 |
Peak memory | 199196 kb |
Host | smart-9f77dc45-d9e1-489b-b974-6236b789b2b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987792325 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2987792325 |
Directory | /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1011600589 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 61659681 ps |
CPU time | 0.74 seconds |
Started | May 05 12:23:52 PM PDT 24 |
Finished | May 05 12:23:55 PM PDT 24 |
Peak memory | 199924 kb |
Host | smart-9ac84844-9561-4a86-920e-95f312e6f5d4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011600589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1011600589 |
Directory | /workspace/5.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.673099980 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 135373829 ps |
CPU time | 1.32 seconds |
Started | May 05 12:23:52 PM PDT 24 |
Finished | May 05 12:23:55 PM PDT 24 |
Peak memory | 199952 kb |
Host | smart-02ae0689-80ed-4010-b4f7-9ad67308f407 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673099980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam e_csr_outstanding.673099980 |
Directory | /workspace/5.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2611573170 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 235990413 ps |
CPU time | 3.63 seconds |
Started | May 05 12:23:47 PM PDT 24 |
Finished | May 05 12:23:52 PM PDT 24 |
Peak memory | 208308 kb |
Host | smart-59447166-f508-495d-ae8b-748f6b893e23 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611573170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2611573170 |
Directory | /workspace/5.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1738477221 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 888869604 ps |
CPU time | 2.95 seconds |
Started | May 05 12:20:34 PM PDT 24 |
Finished | May 05 12:20:38 PM PDT 24 |
Peak memory | 200488 kb |
Host | smart-eae07d7a-c5b3-4f1f-9fff-d06702749fb2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738477221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err .1738477221 |
Directory | /workspace/5.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1245428294 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 154867096 ps |
CPU time | 1.13 seconds |
Started | May 05 12:24:16 PM PDT 24 |
Finished | May 05 12:24:20 PM PDT 24 |
Peak memory | 208040 kb |
Host | smart-5d1ecbd8-e0c7-42d7-ab9e-a0fde5bc8435 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245428294 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1245428294 |
Directory | /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1161407812 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 57272044 ps |
CPU time | 0.79 seconds |
Started | May 05 12:24:16 PM PDT 24 |
Finished | May 05 12:24:19 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-97f2cb08-d7de-4165-85f8-cd78bac2f3b0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161407812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1161407812 |
Directory | /workspace/6.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4041920639 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 208693814 ps |
CPU time | 1.58 seconds |
Started | May 05 12:24:16 PM PDT 24 |
Finished | May 05 12:24:20 PM PDT 24 |
Peak memory | 200024 kb |
Host | smart-5a6a3352-edf5-4e37-ada2-d93480add792 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041920639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa me_csr_outstanding.4041920639 |
Directory | /workspace/6.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.145152768 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 108070813 ps |
CPU time | 1.62 seconds |
Started | May 05 12:24:16 PM PDT 24 |
Finished | May 05 12:24:20 PM PDT 24 |
Peak memory | 210432 kb |
Host | smart-36a709a9-5384-4c4a-a4b3-ba39c8b302aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145152768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.145152768 |
Directory | /workspace/6.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3887792757 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 802254297 ps |
CPU time | 2.93 seconds |
Started | May 05 12:22:08 PM PDT 24 |
Finished | May 05 12:22:11 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-b41dc0cf-8998-41eb-86cb-599dc45a1fb2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887792757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err .3887792757 |
Directory | /workspace/6.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.193937352 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 104497133 ps |
CPU time | 0.96 seconds |
Started | May 05 12:22:11 PM PDT 24 |
Finished | May 05 12:22:13 PM PDT 24 |
Peak memory | 200400 kb |
Host | smart-cac3d9dc-8900-4549-8a5d-51773a6b10d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193937352 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.193937352 |
Directory | /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1832563060 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 80650963 ps |
CPU time | 0.82 seconds |
Started | May 05 12:24:21 PM PDT 24 |
Finished | May 05 12:24:23 PM PDT 24 |
Peak memory | 200208 kb |
Host | smart-bd81f0e1-973b-4550-8ef9-e09e878b4848 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832563060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1832563060 |
Directory | /workspace/7.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1017023972 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 205108959 ps |
CPU time | 1.32 seconds |
Started | May 05 12:24:20 PM PDT 24 |
Finished | May 05 12:24:22 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-3879abab-efb9-406e-be1b-7e38c4d3f656 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017023972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa me_csr_outstanding.1017023972 |
Directory | /workspace/7.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3943994788 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 448872172 ps |
CPU time | 1.78 seconds |
Started | May 05 12:22:25 PM PDT 24 |
Finished | May 05 12:22:27 PM PDT 24 |
Peak memory | 200544 kb |
Host | smart-f74c1246-c5f9-4713-928a-6d9c9869171f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943994788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err .3943994788 |
Directory | /workspace/7.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3480152626 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 101406931 ps |
CPU time | 1.05 seconds |
Started | May 05 12:22:28 PM PDT 24 |
Finished | May 05 12:22:29 PM PDT 24 |
Peak memory | 208656 kb |
Host | smart-5f77631b-302a-4c5e-80a8-7c976a7469b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480152626 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3480152626 |
Directory | /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3399403725 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 70529036 ps |
CPU time | 0.87 seconds |
Started | May 05 12:22:00 PM PDT 24 |
Finished | May 05 12:22:02 PM PDT 24 |
Peak memory | 200284 kb |
Host | smart-e5c257bf-2086-48e0-861e-b10856bf2777 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399403725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3399403725 |
Directory | /workspace/8.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2685862558 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 137532234 ps |
CPU time | 1.08 seconds |
Started | May 05 12:20:08 PM PDT 24 |
Finished | May 05 12:20:09 PM PDT 24 |
Peak memory | 200288 kb |
Host | smart-3ac566e8-ee70-43e8-a97f-fa5ce692ae7f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685862558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa me_csr_outstanding.2685862558 |
Directory | /workspace/8.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4094282200 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 422413493 ps |
CPU time | 2.99 seconds |
Started | May 05 12:23:49 PM PDT 24 |
Finished | May 05 12:23:53 PM PDT 24 |
Peak memory | 200188 kb |
Host | smart-7970b091-50ac-4623-aa43-10261acfd415 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094282200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.4094282200 |
Directory | /workspace/8.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2482624621 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 805948635 ps |
CPU time | 2.91 seconds |
Started | May 05 12:22:01 PM PDT 24 |
Finished | May 05 12:22:04 PM PDT 24 |
Peak memory | 200520 kb |
Host | smart-e26a2b85-cb4c-4659-ad68-c9f43126171c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482624621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err .2482624621 |
Directory | /workspace/8.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1253890330 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 132612507 ps |
CPU time | 1.08 seconds |
Started | May 05 12:22:36 PM PDT 24 |
Finished | May 05 12:22:37 PM PDT 24 |
Peak memory | 200488 kb |
Host | smart-ae43b578-59c1-40cd-8e1b-649e284b4557 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253890330 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1253890330 |
Directory | /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1571045924 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 65105396 ps |
CPU time | 0.77 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:24:52 PM PDT 24 |
Peak memory | 199324 kb |
Host | smart-9e077837-9de8-462d-ad61-e10aff34dd84 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571045924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1571045924 |
Directory | /workspace/9.rstmgr_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3277403531 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 84410400 ps |
CPU time | 1.02 seconds |
Started | May 05 12:20:57 PM PDT 24 |
Finished | May 05 12:20:58 PM PDT 24 |
Peak memory | 200268 kb |
Host | smart-c5d24793-06e2-4e6c-9fc4-c15ad9e800ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277403531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa me_csr_outstanding.3277403531 |
Directory | /workspace/9.rstmgr_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.564543903 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 245286780 ps |
CPU time | 3.6 seconds |
Started | May 05 12:24:50 PM PDT 24 |
Finished | May 05 12:24:57 PM PDT 24 |
Peak memory | 208364 kb |
Host | smart-ddfa4549-796c-4ef0-9f5b-1ab36942b021 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564543903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.564543903 |
Directory | /workspace/9.rstmgr_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3161744640 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 868040844 ps |
CPU time | 3.47 seconds |
Started | May 05 12:19:20 PM PDT 24 |
Finished | May 05 12:19:25 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-b36b4031-582d-4439-834f-6fd21445f435 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161744640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err .3161744640 |
Directory | /workspace/9.rstmgr_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rstmgr_alert_test.2975368400 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 57898442 ps |
CPU time | 0.78 seconds |
Started | May 05 12:20:57 PM PDT 24 |
Finished | May 05 12:20:58 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-dfcc7cdc-1e3d-481b-85f6-8667ad49781c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975368400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2975368400 |
Directory | /workspace/0.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2948485764 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 1225785904 ps |
CPU time | 5.83 seconds |
Started | May 05 12:24:00 PM PDT 24 |
Finished | May 05 12:24:07 PM PDT 24 |
Peak memory | 217860 kb |
Host | smart-525d7dda-5524-4530-912c-96f26eac732f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2948485764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2948485764 |
Directory | /workspace/0.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4017114574 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 245290137 ps |
CPU time | 1.06 seconds |
Started | May 05 12:24:04 PM PDT 24 |
Finished | May 05 12:24:09 PM PDT 24 |
Peak memory | 216676 kb |
Host | smart-b67ca34c-72c5-493e-a45d-10e147ccddbc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017114574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4017114574 |
Directory | /workspace/0.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/0.rstmgr_reset.4114546736 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 1205714409 ps |
CPU time | 4.82 seconds |
Started | May 05 12:24:04 PM PDT 24 |
Finished | May 05 12:24:13 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-3519be76-5280-4b21-b03e-4fa78a998974 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114546736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.4114546736 |
Directory | /workspace/0.rstmgr_reset/latest |
Test location | /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.436768911 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 109666503 ps |
CPU time | 1.02 seconds |
Started | May 05 12:24:01 PM PDT 24 |
Finished | May 05 12:24:03 PM PDT 24 |
Peak memory | 200424 kb |
Host | smart-89f9b9c3-3311-4c65-9c12-8edad9c82b62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436768911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.436768911 |
Directory | /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/0.rstmgr_smoke.2952740015 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 110279978 ps |
CPU time | 1.16 seconds |
Started | May 05 12:23:51 PM PDT 24 |
Finished | May 05 12:23:54 PM PDT 24 |
Peak memory | 199464 kb |
Host | smart-f73e7a55-e8a9-40d1-87c6-b8f0938610fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952740015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2952740015 |
Directory | /workspace/0.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/0.rstmgr_stress_all.689819038 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 955820475 ps |
CPU time | 4.09 seconds |
Started | May 05 12:21:11 PM PDT 24 |
Finished | May 05 12:21:16 PM PDT 24 |
Peak memory | 200864 kb |
Host | smart-776ea69a-7756-43a2-8036-b8db15e6e98c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689819038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.689819038 |
Directory | /workspace/0.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/0.rstmgr_sw_rst.4048134283 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 402287443 ps |
CPU time | 2.24 seconds |
Started | May 05 12:20:55 PM PDT 24 |
Finished | May 05 12:20:57 PM PDT 24 |
Peak memory | 200752 kb |
Host | smart-3e58b18a-f1c8-492f-b152-dfec6af45016 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048134283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4048134283 |
Directory | /workspace/0.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.902985795 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 159415406 ps |
CPU time | 1.23 seconds |
Started | May 05 12:21:44 PM PDT 24 |
Finished | May 05 12:21:46 PM PDT 24 |
Peak memory | 200920 kb |
Host | smart-7fad9ece-595c-48af-a162-a328a07b47d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902985795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.902985795 |
Directory | /workspace/0.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/1.rstmgr_alert_test.3382581802 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 51705619 ps |
CPU time | 0.77 seconds |
Started | May 05 12:24:12 PM PDT 24 |
Finished | May 05 12:24:17 PM PDT 24 |
Peak memory | 198720 kb |
Host | smart-3aa63c3d-9ad9-476b-82b6-f39ca45026d8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382581802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3382581802 |
Directory | /workspace/1.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3006605567 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 1229085536 ps |
CPU time | 5.95 seconds |
Started | May 05 12:24:05 PM PDT 24 |
Finished | May 05 12:24:16 PM PDT 24 |
Peak memory | 216976 kb |
Host | smart-ac2433f4-e2bf-4ca4-b556-8510536f70e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3006605567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3006605567 |
Directory | /workspace/1.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1174677722 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 243447866 ps |
CPU time | 1.05 seconds |
Started | May 05 12:24:06 PM PDT 24 |
Finished | May 05 12:24:12 PM PDT 24 |
Peak memory | 217740 kb |
Host | smart-896c219a-c5d7-4485-842c-5f23049a1b37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174677722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1174677722 |
Directory | /workspace/1.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/1.rstmgr_por_stretcher.1638264912 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 96612242 ps |
CPU time | 0.81 seconds |
Started | May 05 12:24:10 PM PDT 24 |
Finished | May 05 12:24:15 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-8cd4cfe7-2027-4d1f-84f6-556e5d8add93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638264912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1638264912 |
Directory | /workspace/1.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/1.rstmgr_reset.488067008 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 1121119052 ps |
CPU time | 5.12 seconds |
Started | May 05 12:24:11 PM PDT 24 |
Finished | May 05 12:24:20 PM PDT 24 |
Peak memory | 200868 kb |
Host | smart-3d9b3e22-a652-49f3-956a-42361cc7ff48 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488067008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.488067008 |
Directory | /workspace/1.rstmgr_reset/latest |
Test location | /workspace/coverage/default/1.rstmgr_sec_cm.4023898294 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 8792811864 ps |
CPU time | 14.44 seconds |
Started | May 05 12:24:12 PM PDT 24 |
Finished | May 05 12:24:31 PM PDT 24 |
Peak memory | 216504 kb |
Host | smart-ef46c688-574d-4139-b80f-58a3b0160c02 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023898294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4023898294 |
Directory | /workspace/1.rstmgr_sec_cm/latest |
Test location | /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2996919626 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 97696652 ps |
CPU time | 1.04 seconds |
Started | May 05 12:20:41 PM PDT 24 |
Finished | May 05 12:20:42 PM PDT 24 |
Peak memory | 201040 kb |
Host | smart-472000b1-c686-405a-bc54-587b24983d50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996919626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2996919626 |
Directory | /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/1.rstmgr_smoke.2662873637 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 118822232 ps |
CPU time | 1.31 seconds |
Started | May 05 12:20:51 PM PDT 24 |
Finished | May 05 12:20:53 PM PDT 24 |
Peak memory | 200972 kb |
Host | smart-cca729dd-8bb6-491f-a42c-82afbb1eab7f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662873637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2662873637 |
Directory | /workspace/1.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/1.rstmgr_stress_all.3285121658 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 600070253 ps |
CPU time | 2.47 seconds |
Started | May 05 12:24:05 PM PDT 24 |
Finished | May 05 12:24:12 PM PDT 24 |
Peak memory | 200644 kb |
Host | smart-4d3a4ceb-8981-462e-9c21-a4b1d6c5da6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285121658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3285121658 |
Directory | /workspace/1.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/1.rstmgr_sw_rst.3032975948 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 445235820 ps |
CPU time | 2.33 seconds |
Started | May 05 12:24:06 PM PDT 24 |
Finished | May 05 12:24:14 PM PDT 24 |
Peak memory | 200484 kb |
Host | smart-e323b06e-5564-4370-869b-0a880ce6d70c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032975948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3032975948 |
Directory | /workspace/1.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3035440881 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 118946057 ps |
CPU time | 1.05 seconds |
Started | May 05 12:24:05 PM PDT 24 |
Finished | May 05 12:24:09 PM PDT 24 |
Peak memory | 200388 kb |
Host | smart-cfa33d11-4bc1-4bfc-9797-1bc318cf2e6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035440881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3035440881 |
Directory | /workspace/1.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3898674852 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 2172005811 ps |
CPU time | 7.24 seconds |
Started | May 05 12:25:11 PM PDT 24 |
Finished | May 05 12:25:20 PM PDT 24 |
Peak memory | 218520 kb |
Host | smart-338753be-18e7-4b8c-b6cd-972e47540bd9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898674852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3898674852 |
Directory | /workspace/10.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1860227757 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 244246213 ps |
CPU time | 1.17 seconds |
Started | May 05 12:24:52 PM PDT 24 |
Finished | May 05 12:24:56 PM PDT 24 |
Peak memory | 217852 kb |
Host | smart-c476fc2d-287d-4bdc-a46e-9601d3507fd6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860227757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1860227757 |
Directory | /workspace/10.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/10.rstmgr_por_stretcher.2300812310 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 182659199 ps |
CPU time | 0.82 seconds |
Started | May 05 12:25:01 PM PDT 24 |
Finished | May 05 12:25:03 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-fa7c8015-7cfb-469e-9d68-1c3a9bee8d5f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300812310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2300812310 |
Directory | /workspace/10.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/10.rstmgr_reset.4274159878 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 844154943 ps |
CPU time | 4.34 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:12 PM PDT 24 |
Peak memory | 200900 kb |
Host | smart-613b3280-0bf3-4bad-b9c2-d2ec7b6353a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274159878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.4274159878 |
Directory | /workspace/10.rstmgr_reset/latest |
Test location | /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1142131147 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 177492024 ps |
CPU time | 1.14 seconds |
Started | May 05 12:24:55 PM PDT 24 |
Finished | May 05 12:24:58 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-3a422824-96b4-40c4-ab9b-edaa98f15534 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142131147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1142131147 |
Directory | /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/10.rstmgr_smoke.2845064620 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 114938893 ps |
CPU time | 1.15 seconds |
Started | May 05 12:25:09 PM PDT 24 |
Finished | May 05 12:25:12 PM PDT 24 |
Peak memory | 200764 kb |
Host | smart-a1adb033-d15c-44cc-ae68-0a893ee15297 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2845064620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2845064620 |
Directory | /workspace/10.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/10.rstmgr_stress_all.1664421610 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 7084954126 ps |
CPU time | 24.68 seconds |
Started | May 05 12:25:00 PM PDT 24 |
Finished | May 05 12:25:26 PM PDT 24 |
Peak memory | 209160 kb |
Host | smart-08326263-958b-45c2-a337-ae54da08c015 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664421610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1664421610 |
Directory | /workspace/10.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/10.rstmgr_sw_rst.3829370661 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 130291323 ps |
CPU time | 1.64 seconds |
Started | May 05 12:24:50 PM PDT 24 |
Finished | May 05 12:24:55 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-3f8c7286-da0d-42dd-9ad3-5e52c3d2b27b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829370661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3829370661 |
Directory | /workspace/10.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1904320992 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 183540313 ps |
CPU time | 1.21 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 200716 kb |
Host | smart-01e4c6d5-ad6b-4e3c-a04f-ffa8a494b0a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904320992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1904320992 |
Directory | /workspace/10.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/11.rstmgr_alert_test.1686414084 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 75287366 ps |
CPU time | 0.76 seconds |
Started | May 05 12:25:01 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-eda508e4-18de-476e-9ec9-9575543be4a4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686414084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1686414084 |
Directory | /workspace/11.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.261211542 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 243702454 ps |
CPU time | 1.21 seconds |
Started | May 05 12:24:56 PM PDT 24 |
Finished | May 05 12:24:59 PM PDT 24 |
Peak memory | 218024 kb |
Host | smart-b753051a-91a3-4ccd-ba4a-c10ca53354b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=261211542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.261211542 |
Directory | /workspace/11.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/11.rstmgr_por_stretcher.511936064 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 159447069 ps |
CPU time | 0.88 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:24:53 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-0727b440-8aff-4020-8a5f-6f853e68a1f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511936064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.511936064 |
Directory | /workspace/11.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/11.rstmgr_reset.2868915978 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1840170603 ps |
CPU time | 6.18 seconds |
Started | May 05 12:25:08 PM PDT 24 |
Finished | May 05 12:25:16 PM PDT 24 |
Peak memory | 200888 kb |
Host | smart-0956aebe-9ad8-41e4-8e2f-2b2b1c53f9e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868915978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2868915978 |
Directory | /workspace/11.rstmgr_reset/latest |
Test location | /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.965150573 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 102913689 ps |
CPU time | 1.06 seconds |
Started | May 05 12:25:20 PM PDT 24 |
Finished | May 05 12:25:22 PM PDT 24 |
Peak memory | 200736 kb |
Host | smart-6c0dd148-8a11-46f7-8652-e1c2671ba692 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965150573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.965150573 |
Directory | /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/11.rstmgr_smoke.3018889951 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 201161978 ps |
CPU time | 1.32 seconds |
Started | May 05 12:24:50 PM PDT 24 |
Finished | May 05 12:24:55 PM PDT 24 |
Peak memory | 201064 kb |
Host | smart-c9cf84ff-4f5c-43cb-a32f-79bb2b545e1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018889951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3018889951 |
Directory | /workspace/11.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/11.rstmgr_stress_all.774450930 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 4680576924 ps |
CPU time | 17.61 seconds |
Started | May 05 12:24:50 PM PDT 24 |
Finished | May 05 12:25:11 PM PDT 24 |
Peak memory | 200968 kb |
Host | smart-7b7e2f7c-3b4e-429d-bd7f-ab3ef3bf33b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774450930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.774450930 |
Directory | /workspace/11.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/11.rstmgr_sw_rst.3744960374 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 405999364 ps |
CPU time | 2.24 seconds |
Started | May 05 12:25:13 PM PDT 24 |
Finished | May 05 12:25:17 PM PDT 24 |
Peak memory | 200736 kb |
Host | smart-29969a12-ac37-4d6d-bff7-613debed12bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744960374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3744960374 |
Directory | /workspace/11.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3738236592 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 97611760 ps |
CPU time | 0.92 seconds |
Started | May 05 12:25:01 PM PDT 24 |
Finished | May 05 12:25:04 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-7566e679-a984-4258-83dd-1226237a6521 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738236592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3738236592 |
Directory | /workspace/11.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/12.rstmgr_alert_test.4135279759 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 65819067 ps |
CPU time | 0.74 seconds |
Started | May 05 12:25:07 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 200524 kb |
Host | smart-0186a7a7-1b84-405f-a5d1-1bad6942e153 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135279759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4135279759 |
Directory | /workspace/12.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1447016441 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 1220256934 ps |
CPU time | 5.52 seconds |
Started | May 05 12:25:01 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 218316 kb |
Host | smart-5c580e7e-4e0c-40c3-ac1f-d2c55ee469dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447016441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1447016441 |
Directory | /workspace/12.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3049723530 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 243620853 ps |
CPU time | 1.14 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 217908 kb |
Host | smart-48d63cac-8553-41f7-8490-14421ad75292 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3049723530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3049723530 |
Directory | /workspace/12.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/12.rstmgr_por_stretcher.3055742726 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 86981513 ps |
CPU time | 0.77 seconds |
Started | May 05 12:25:13 PM PDT 24 |
Finished | May 05 12:25:16 PM PDT 24 |
Peak memory | 200536 kb |
Host | smart-d74ae37e-5e97-4436-a2d9-9ccd477e2cc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055742726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3055742726 |
Directory | /workspace/12.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/12.rstmgr_reset.1231354723 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 765037112 ps |
CPU time | 3.74 seconds |
Started | May 05 12:24:55 PM PDT 24 |
Finished | May 05 12:25:01 PM PDT 24 |
Peak memory | 200856 kb |
Host | smart-71b904d4-93de-41fb-90b9-93e3a4b9b5ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231354723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1231354723 |
Directory | /workspace/12.rstmgr_reset/latest |
Test location | /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2581758069 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 115748111 ps |
CPU time | 0.98 seconds |
Started | May 05 12:25:01 PM PDT 24 |
Finished | May 05 12:25:04 PM PDT 24 |
Peak memory | 200684 kb |
Host | smart-16319f26-516e-4080-ada3-2900c78a75c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581758069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2581758069 |
Directory | /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/12.rstmgr_smoke.2980636360 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 221153404 ps |
CPU time | 1.51 seconds |
Started | May 05 12:25:13 PM PDT 24 |
Finished | May 05 12:25:17 PM PDT 24 |
Peak memory | 200924 kb |
Host | smart-5e051b9d-cec0-4e9d-9e4d-c0f1a50be2e6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980636360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2980636360 |
Directory | /workspace/12.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/12.rstmgr_stress_all.4168918236 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 7096421040 ps |
CPU time | 29.1 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:35 PM PDT 24 |
Peak memory | 201084 kb |
Host | smart-6f0c09d7-9cdd-463f-b4b0-d24873af6216 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168918236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.4168918236 |
Directory | /workspace/12.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/12.rstmgr_sw_rst.3911576622 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 358156451 ps |
CPU time | 1.97 seconds |
Started | May 05 12:25:08 PM PDT 24 |
Finished | May 05 12:25:12 PM PDT 24 |
Peak memory | 208972 kb |
Host | smart-b50ca429-665b-4e8c-905a-f474ad23e881 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911576622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3911576622 |
Directory | /workspace/12.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1880074973 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 182362338 ps |
CPU time | 1.26 seconds |
Started | May 05 12:25:01 PM PDT 24 |
Finished | May 05 12:25:04 PM PDT 24 |
Peak memory | 200684 kb |
Host | smart-156c6f2c-7916-473d-a107-23ac9b3bb1a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880074973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1880074973 |
Directory | /workspace/12.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/13.rstmgr_alert_test.3784888274 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 74691089 ps |
CPU time | 0.79 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 200596 kb |
Host | smart-ac9f8b47-eecd-471b-93cd-e502469423cf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784888274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3784888274 |
Directory | /workspace/13.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3769771142 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 1892053230 ps |
CPU time | 7.77 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:16 PM PDT 24 |
Peak memory | 222324 kb |
Host | smart-fdb473d6-2193-42c3-97b8-c6d77234721e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769771142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3769771142 |
Directory | /workspace/13.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1834455829 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 243824024 ps |
CPU time | 1.13 seconds |
Started | May 05 12:25:11 PM PDT 24 |
Finished | May 05 12:25:14 PM PDT 24 |
Peak memory | 217800 kb |
Host | smart-da9980b0-da05-4354-a5b1-8ae014f17ada |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834455829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1834455829 |
Directory | /workspace/13.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/13.rstmgr_por_stretcher.2801694982 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 191832664 ps |
CPU time | 0.86 seconds |
Started | May 05 12:25:00 PM PDT 24 |
Finished | May 05 12:25:03 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-e3f286d2-7343-4445-a89f-4f01b0064762 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801694982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2801694982 |
Directory | /workspace/13.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/13.rstmgr_reset.1730029574 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 1670876645 ps |
CPU time | 7 seconds |
Started | May 05 12:25:02 PM PDT 24 |
Finished | May 05 12:25:11 PM PDT 24 |
Peak memory | 200852 kb |
Host | smart-c2d7749c-8988-4b27-b3bd-7bf57d7e5c8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730029574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1730029574 |
Directory | /workspace/13.rstmgr_reset/latest |
Test location | /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4151686868 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 178582095 ps |
CPU time | 1.21 seconds |
Started | May 05 12:25:02 PM PDT 24 |
Finished | May 05 12:25:05 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-2093855c-9605-47fe-8acc-2d5d4094bedf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4151686868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4151686868 |
Directory | /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/13.rstmgr_smoke.3514319985 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 189986551 ps |
CPU time | 1.32 seconds |
Started | May 05 12:24:58 PM PDT 24 |
Finished | May 05 12:25:01 PM PDT 24 |
Peak memory | 200884 kb |
Host | smart-87f11039-f35f-4c17-af8b-a56ba866cccf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514319985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3514319985 |
Directory | /workspace/13.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/13.rstmgr_sw_rst.4111864622 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 116864755 ps |
CPU time | 1.56 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:07 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-82247cff-def9-4d9b-94ef-627add4bd1b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111864622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.4111864622 |
Directory | /workspace/13.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.800233545 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 100941277 ps |
CPU time | 0.85 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:05 PM PDT 24 |
Peak memory | 200772 kb |
Host | smart-29519d18-2506-415d-a6fc-f5bc03a5e379 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800233545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.800233545 |
Directory | /workspace/13.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/14.rstmgr_alert_test.1398778461 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 74453680 ps |
CPU time | 0.82 seconds |
Started | May 05 12:24:55 PM PDT 24 |
Finished | May 05 12:25:00 PM PDT 24 |
Peak memory | 200572 kb |
Host | smart-d7ad6321-179c-4509-99c5-3054e56f694b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398778461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1398778461 |
Directory | /workspace/14.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.548275414 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 1230573826 ps |
CPU time | 5.36 seconds |
Started | May 05 12:26:07 PM PDT 24 |
Finished | May 05 12:26:13 PM PDT 24 |
Peak memory | 220344 kb |
Host | smart-ecb3b689-5f9c-4a18-b7ae-63b3f2e0f156 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548275414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.548275414 |
Directory | /workspace/14.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3968935639 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 244398524 ps |
CPU time | 1.12 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:07 PM PDT 24 |
Peak memory | 217804 kb |
Host | smart-9b6e386c-7b0f-4354-933c-73589707435b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968935639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3968935639 |
Directory | /workspace/14.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/14.rstmgr_por_stretcher.4173056727 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 173149864 ps |
CPU time | 0.9 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:07 PM PDT 24 |
Peak memory | 200516 kb |
Host | smart-69adb72e-645e-459d-94e9-db28fff8def9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173056727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4173056727 |
Directory | /workspace/14.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/14.rstmgr_reset.4258758526 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 811360869 ps |
CPU time | 3.97 seconds |
Started | May 05 12:25:08 PM PDT 24 |
Finished | May 05 12:25:14 PM PDT 24 |
Peak memory | 200956 kb |
Host | smart-a432d8cb-b2ab-4bbf-b45b-0dcd96f65417 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258758526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4258758526 |
Directory | /workspace/14.rstmgr_reset/latest |
Test location | /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2266450187 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 147482652 ps |
CPU time | 1.07 seconds |
Started | May 05 12:25:11 PM PDT 24 |
Finished | May 05 12:25:13 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-03360596-6644-49cf-b2d3-783ca45c7c11 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266450187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2266450187 |
Directory | /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/14.rstmgr_smoke.1164621368 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 112613055 ps |
CPU time | 1.08 seconds |
Started | May 05 12:26:40 PM PDT 24 |
Finished | May 05 12:26:42 PM PDT 24 |
Peak memory | 200928 kb |
Host | smart-8f2adf5f-0074-4ca2-9e44-c01b04539dd2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164621368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1164621368 |
Directory | /workspace/14.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/14.rstmgr_stress_all.2392936417 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 4996533043 ps |
CPU time | 20.88 seconds |
Started | May 05 12:25:15 PM PDT 24 |
Finished | May 05 12:25:38 PM PDT 24 |
Peak memory | 201140 kb |
Host | smart-c82460cc-70a8-467c-8e55-fceb55caac2e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392936417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2392936417 |
Directory | /workspace/14.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/14.rstmgr_sw_rst.2827916289 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 537541283 ps |
CPU time | 2.81 seconds |
Started | May 05 12:25:17 PM PDT 24 |
Finished | May 05 12:25:21 PM PDT 24 |
Peak memory | 200692 kb |
Host | smart-ec313933-2167-40fb-a7bd-703910181c4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827916289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2827916289 |
Directory | /workspace/14.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2920795165 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 74952675 ps |
CPU time | 0.77 seconds |
Started | May 05 12:26:07 PM PDT 24 |
Finished | May 05 12:26:14 PM PDT 24 |
Peak memory | 200536 kb |
Host | smart-bb5c9970-cf48-4eaf-8916-e355583c1cbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2920795165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2920795165 |
Directory | /workspace/14.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/15.rstmgr_alert_test.1486424463 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 67738753 ps |
CPU time | 0.74 seconds |
Started | May 05 12:25:26 PM PDT 24 |
Finished | May 05 12:25:27 PM PDT 24 |
Peak memory | 200616 kb |
Host | smart-06331ad3-772c-467a-80c1-ca689de45c05 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486424463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1486424463 |
Directory | /workspace/15.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.846640684 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 1904388883 ps |
CPU time | 6.79 seconds |
Started | May 05 12:25:14 PM PDT 24 |
Finished | May 05 12:25:22 PM PDT 24 |
Peak memory | 218376 kb |
Host | smart-38c67f04-a209-4b75-b4a3-941642f09a62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=846640684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.846640684 |
Directory | /workspace/15.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.624443868 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 250231219 ps |
CPU time | 1.04 seconds |
Started | May 05 12:26:36 PM PDT 24 |
Finished | May 05 12:26:38 PM PDT 24 |
Peak memory | 217876 kb |
Host | smart-0e138453-f205-49cc-81e6-f78a670550fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624443868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.624443868 |
Directory | /workspace/15.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/15.rstmgr_por_stretcher.311043040 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 100111711 ps |
CPU time | 0.81 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:07 PM PDT 24 |
Peak memory | 200848 kb |
Host | smart-d0893236-d442-4604-a8d7-a3c8392a4e9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311043040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.311043040 |
Directory | /workspace/15.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/15.rstmgr_reset.3833740469 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 2179468145 ps |
CPU time | 7.82 seconds |
Started | May 05 12:25:09 PM PDT 24 |
Finished | May 05 12:25:19 PM PDT 24 |
Peak memory | 201048 kb |
Host | smart-83e1e9e1-d92d-415c-9cb4-a5b5392ea369 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833740469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3833740469 |
Directory | /workspace/15.rstmgr_reset/latest |
Test location | /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3199978907 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 149190654 ps |
CPU time | 1.14 seconds |
Started | May 05 12:25:12 PM PDT 24 |
Finished | May 05 12:25:15 PM PDT 24 |
Peak memory | 200704 kb |
Host | smart-946b9303-717e-4c9a-80f9-2412176103e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199978907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3199978907 |
Directory | /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/15.rstmgr_smoke.3447610152 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 247439453 ps |
CPU time | 1.5 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 200960 kb |
Host | smart-77283627-fedf-447a-a82e-f81213a9fcf1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447610152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3447610152 |
Directory | /workspace/15.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/15.rstmgr_stress_all.749747866 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 4733484054 ps |
CPU time | 14.71 seconds |
Started | May 05 12:25:05 PM PDT 24 |
Finished | May 05 12:25:21 PM PDT 24 |
Peak memory | 201004 kb |
Host | smart-f2d4d284-355d-42de-b0b3-1d8de9a4607d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749747866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.749747866 |
Directory | /workspace/15.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/15.rstmgr_sw_rst.4030013814 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 280618891 ps |
CPU time | 1.76 seconds |
Started | May 05 12:26:27 PM PDT 24 |
Finished | May 05 12:26:30 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-0eaa4bdf-9674-4cdb-8b3a-141ff81cab7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030013814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.4030013814 |
Directory | /workspace/15.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.882763667 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 109897471 ps |
CPU time | 1 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:06 PM PDT 24 |
Peak memory | 200788 kb |
Host | smart-94890cc1-db3d-4d30-8ba2-ad76aac687dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882763667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.882763667 |
Directory | /workspace/15.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/16.rstmgr_alert_test.3676846167 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 73869574 ps |
CPU time | 0.83 seconds |
Started | May 05 12:26:07 PM PDT 24 |
Finished | May 05 12:26:09 PM PDT 24 |
Peak memory | 198640 kb |
Host | smart-6244c805-5034-467c-b560-3cdb2b545d37 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676846167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3676846167 |
Directory | /workspace/16.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2115513131 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 243656527 ps |
CPU time | 1.13 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:06 PM PDT 24 |
Peak memory | 218100 kb |
Host | smart-8121a22f-5b4c-4412-b871-f8b2b2ebfac0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115513131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2115513131 |
Directory | /workspace/16.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/16.rstmgr_por_stretcher.2672723878 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 121069515 ps |
CPU time | 0.75 seconds |
Started | May 05 12:25:11 PM PDT 24 |
Finished | May 05 12:25:13 PM PDT 24 |
Peak memory | 200516 kb |
Host | smart-f92a6b80-9160-40ec-a917-e968cd99d1df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2672723878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2672723878 |
Directory | /workspace/16.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/16.rstmgr_reset.2431478396 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 1490256862 ps |
CPU time | 5.68 seconds |
Started | May 05 12:25:05 PM PDT 24 |
Finished | May 05 12:25:12 PM PDT 24 |
Peak memory | 200952 kb |
Host | smart-a86db544-91f2-4ca6-b575-2fc276b8b871 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431478396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2431478396 |
Directory | /workspace/16.rstmgr_reset/latest |
Test location | /workspace/coverage/default/16.rstmgr_smoke.2174694906 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 126373974 ps |
CPU time | 1.29 seconds |
Started | May 05 12:25:13 PM PDT 24 |
Finished | May 05 12:25:16 PM PDT 24 |
Peak memory | 200892 kb |
Host | smart-ceab9a3b-f489-4a2d-a2ca-6ae14cfeb301 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174694906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2174694906 |
Directory | /workspace/16.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/16.rstmgr_stress_all.1994484416 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 876458194 ps |
CPU time | 3.67 seconds |
Started | May 05 12:26:24 PM PDT 24 |
Finished | May 05 12:26:29 PM PDT 24 |
Peak memory | 200936 kb |
Host | smart-29f05960-c211-4bc4-ae52-1c3d831523fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994484416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1994484416 |
Directory | /workspace/16.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/16.rstmgr_sw_rst.3110055798 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 400403293 ps |
CPU time | 2.06 seconds |
Started | May 05 12:26:31 PM PDT 24 |
Finished | May 05 12:26:34 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-d453d305-691b-4e1b-a9a9-b3cbf588c66d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110055798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3110055798 |
Directory | /workspace/16.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.53523153 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 265863849 ps |
CPU time | 1.47 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:10 PM PDT 24 |
Peak memory | 200860 kb |
Host | smart-69a1f634-68fd-4748-8718-d504d6213f62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53523153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.53523153 |
Directory | /workspace/16.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/17.rstmgr_alert_test.223931962 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 68445427 ps |
CPU time | 0.74 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:06 PM PDT 24 |
Peak memory | 200592 kb |
Host | smart-04c5fae9-1a71-4166-b1e4-d55f7d5bebe4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223931962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.223931962 |
Directory | /workspace/17.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2724745043 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 2351304873 ps |
CPU time | 8.71 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:14 PM PDT 24 |
Peak memory | 218156 kb |
Host | smart-34b69519-2ab6-4760-9205-60377d17d212 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724745043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2724745043 |
Directory | /workspace/17.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/17.rstmgr_por_stretcher.805264112 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 92827623 ps |
CPU time | 0.8 seconds |
Started | May 05 12:25:08 PM PDT 24 |
Finished | May 05 12:25:15 PM PDT 24 |
Peak memory | 200584 kb |
Host | smart-1c456f32-9fec-4299-b2ae-4ad43678cff8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805264112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.805264112 |
Directory | /workspace/17.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/17.rstmgr_reset.2591060606 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 1353786162 ps |
CPU time | 5.14 seconds |
Started | May 05 12:25:08 PM PDT 24 |
Finished | May 05 12:25:15 PM PDT 24 |
Peak memory | 200952 kb |
Host | smart-4bcdace0-518d-42f3-ab42-269297eed560 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591060606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2591060606 |
Directory | /workspace/17.rstmgr_reset/latest |
Test location | /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2934622135 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 108363871 ps |
CPU time | 1 seconds |
Started | May 05 12:25:07 PM PDT 24 |
Finished | May 05 12:25:10 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-fa4ef560-92d1-40cf-a056-2d819c92c7a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2934622135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2934622135 |
Directory | /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/17.rstmgr_smoke.4061883205 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 226414742 ps |
CPU time | 1.41 seconds |
Started | May 05 12:25:05 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 200944 kb |
Host | smart-60faa560-9810-4dc0-a5fc-a5850e021cda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061883205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.4061883205 |
Directory | /workspace/17.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/17.rstmgr_stress_all.1701744827 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 15372451493 ps |
CPU time | 51.23 seconds |
Started | May 05 12:25:16 PM PDT 24 |
Finished | May 05 12:26:09 PM PDT 24 |
Peak memory | 209300 kb |
Host | smart-3405ae08-7449-4c06-8a4b-86cf40ea028e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701744827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1701744827 |
Directory | /workspace/17.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/17.rstmgr_sw_rst.2029342618 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 375159160 ps |
CPU time | 2.13 seconds |
Started | May 05 12:25:11 PM PDT 24 |
Finished | May 05 12:25:15 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-27d48056-cccc-4aec-9921-fc452d2081fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029342618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2029342618 |
Directory | /workspace/17.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2469498988 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 212732969 ps |
CPU time | 1.41 seconds |
Started | May 05 12:25:02 PM PDT 24 |
Finished | May 05 12:25:05 PM PDT 24 |
Peak memory | 200772 kb |
Host | smart-6d0373a5-5234-4784-bb2f-da8af82a151f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469498988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2469498988 |
Directory | /workspace/17.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/18.rstmgr_alert_test.1521799523 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 68568957 ps |
CPU time | 0.78 seconds |
Started | May 05 12:26:07 PM PDT 24 |
Finished | May 05 12:26:09 PM PDT 24 |
Peak memory | 198496 kb |
Host | smart-0cb96d89-50d7-4af4-8127-1c638aaf86a8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521799523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1521799523 |
Directory | /workspace/18.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2870049145 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 1891004694 ps |
CPU time | 7.32 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:17 PM PDT 24 |
Peak memory | 218416 kb |
Host | smart-ca71c84c-f9be-4796-b424-7c2944ea02fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870049145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2870049145 |
Directory | /workspace/18.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1124827838 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 244325984 ps |
CPU time | 1.07 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 217804 kb |
Host | smart-2e96f477-582f-41ca-8c05-16f3e60a1693 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124827838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1124827838 |
Directory | /workspace/18.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/18.rstmgr_por_stretcher.3929412502 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 82164630 ps |
CPU time | 0.73 seconds |
Started | May 05 12:25:01 PM PDT 24 |
Finished | May 05 12:25:04 PM PDT 24 |
Peak memory | 200500 kb |
Host | smart-c686df09-9b3b-45c2-b322-325f07c5ec7f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929412502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3929412502 |
Directory | /workspace/18.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/18.rstmgr_reset.553863815 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 1789511263 ps |
CPU time | 6.26 seconds |
Started | May 05 12:25:15 PM PDT 24 |
Finished | May 05 12:25:22 PM PDT 24 |
Peak memory | 200972 kb |
Host | smart-515e1dd4-bd29-4c90-bfbe-aa0d55bac19c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553863815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.553863815 |
Directory | /workspace/18.rstmgr_reset/latest |
Test location | /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2972024019 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 101153353 ps |
CPU time | 0.97 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:07 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-d353dea9-b917-402a-87b6-656a02c464dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972024019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2972024019 |
Directory | /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/18.rstmgr_smoke.646137527 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 120689452 ps |
CPU time | 1.17 seconds |
Started | May 05 12:25:12 PM PDT 24 |
Finished | May 05 12:25:14 PM PDT 24 |
Peak memory | 200900 kb |
Host | smart-797b71c4-e3b1-4723-a139-f0ee2e721f93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646137527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.646137527 |
Directory | /workspace/18.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/18.rstmgr_stress_all.2496125857 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 3475144104 ps |
CPU time | 11.81 seconds |
Started | May 05 12:26:34 PM PDT 24 |
Finished | May 05 12:26:46 PM PDT 24 |
Peak memory | 201060 kb |
Host | smart-91fa2025-24e5-4a79-940e-4ccb58337d98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496125857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2496125857 |
Directory | /workspace/18.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/18.rstmgr_sw_rst.3692656759 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 392196122 ps |
CPU time | 2.33 seconds |
Started | May 05 12:24:55 PM PDT 24 |
Finished | May 05 12:25:00 PM PDT 24 |
Peak memory | 200748 kb |
Host | smart-ac958c0d-b917-4ac9-9731-18e85f21f0ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692656759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3692656759 |
Directory | /workspace/18.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.206834275 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 58367956 ps |
CPU time | 0.78 seconds |
Started | May 05 12:25:05 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-855d62ec-63c6-4564-a458-2ad1ec01d820 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206834275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.206834275 |
Directory | /workspace/18.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/19.rstmgr_alert_test.721535691 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 80274846 ps |
CPU time | 0.8 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:06 PM PDT 24 |
Peak memory | 200516 kb |
Host | smart-ebf15413-b23f-47be-b8c3-cc6fd938a4d9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721535691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.721535691 |
Directory | /workspace/19.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3230322351 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 244484994 ps |
CPU time | 1.05 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 217860 kb |
Host | smart-5376e745-2675-406f-aae2-f70357005867 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230322351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3230322351 |
Directory | /workspace/19.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/19.rstmgr_por_stretcher.381844162 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 90454299 ps |
CPU time | 0.78 seconds |
Started | May 05 12:25:12 PM PDT 24 |
Finished | May 05 12:25:14 PM PDT 24 |
Peak memory | 200476 kb |
Host | smart-5eceff53-c5f2-4713-8411-999337588505 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381844162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.381844162 |
Directory | /workspace/19.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/19.rstmgr_reset.2326202253 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 831737309 ps |
CPU time | 4.01 seconds |
Started | May 05 12:26:07 PM PDT 24 |
Finished | May 05 12:26:12 PM PDT 24 |
Peak memory | 198752 kb |
Host | smart-7bef6b07-7f38-45e8-8a38-26d483f7d6b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326202253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2326202253 |
Directory | /workspace/19.rstmgr_reset/latest |
Test location | /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3503445448 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 139409412 ps |
CPU time | 1.09 seconds |
Started | May 05 12:25:12 PM PDT 24 |
Finished | May 05 12:25:14 PM PDT 24 |
Peak memory | 200768 kb |
Host | smart-dfa466da-ae76-4fdb-9338-04a4507607e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503445448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3503445448 |
Directory | /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/19.rstmgr_smoke.2457910103 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 202750085 ps |
CPU time | 1.47 seconds |
Started | May 05 12:25:15 PM PDT 24 |
Finished | May 05 12:25:18 PM PDT 24 |
Peak memory | 200852 kb |
Host | smart-bed57a7c-45a0-4897-a173-96665cd2060f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2457910103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2457910103 |
Directory | /workspace/19.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/19.rstmgr_sw_rst.563052954 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 431333573 ps |
CPU time | 2.46 seconds |
Started | May 05 12:25:07 PM PDT 24 |
Finished | May 05 12:25:11 PM PDT 24 |
Peak memory | 208928 kb |
Host | smart-50188280-ea53-46f1-9f12-ccafd0647ced |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=563052954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.563052954 |
Directory | /workspace/19.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.51005293 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 117564142 ps |
CPU time | 1 seconds |
Started | May 05 12:25:07 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-ad22043c-cac4-4f08-8674-bbec32f91c80 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51005293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.51005293 |
Directory | /workspace/19.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/2.rstmgr_alert_test.578528503 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 78329865 ps |
CPU time | 0.77 seconds |
Started | May 05 12:21:55 PM PDT 24 |
Finished | May 05 12:21:56 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-e34a0ab2-2655-404a-9fa7-75805a63a2b0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578528503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.578528503 |
Directory | /workspace/2.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2577692923 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 1884419583 ps |
CPU time | 7.23 seconds |
Started | May 05 12:22:03 PM PDT 24 |
Finished | May 05 12:22:12 PM PDT 24 |
Peak memory | 217444 kb |
Host | smart-480af656-28f1-4660-8283-f12af6bbfbf1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2577692923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2577692923 |
Directory | /workspace/2.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3413707026 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 244237157 ps |
CPU time | 1.14 seconds |
Started | May 05 12:24:12 PM PDT 24 |
Finished | May 05 12:24:18 PM PDT 24 |
Peak memory | 216248 kb |
Host | smart-5f659e8f-1fc8-420d-9646-2dad6af5f390 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413707026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3413707026 |
Directory | /workspace/2.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/2.rstmgr_por_stretcher.2682739800 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 126272041 ps |
CPU time | 0.78 seconds |
Started | May 05 12:22:39 PM PDT 24 |
Finished | May 05 12:22:40 PM PDT 24 |
Peak memory | 200516 kb |
Host | smart-5864cb01-a124-45f8-9a11-9930375f0e68 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682739800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2682739800 |
Directory | /workspace/2.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/2.rstmgr_reset.3351547789 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 1168709214 ps |
CPU time | 4.67 seconds |
Started | May 05 12:21:35 PM PDT 24 |
Finished | May 05 12:21:40 PM PDT 24 |
Peak memory | 200896 kb |
Host | smart-f133be4a-6ca2-4de0-9f82-0e63074bad2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351547789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3351547789 |
Directory | /workspace/2.rstmgr_reset/latest |
Test location | /workspace/coverage/default/2.rstmgr_sec_cm.219644996 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 16509403252 ps |
CPU time | 26.71 seconds |
Started | May 05 12:24:34 PM PDT 24 |
Finished | May 05 12:25:02 PM PDT 24 |
Peak memory | 217356 kb |
Host | smart-13e0f636-aadf-4112-8df7-54e53a2467bd |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219644996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.219644996 |
Directory | /workspace/2.rstmgr_sec_cm/latest |
Test location | /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2238860336 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 177744145 ps |
CPU time | 1.21 seconds |
Started | May 05 12:23:30 PM PDT 24 |
Finished | May 05 12:23:32 PM PDT 24 |
Peak memory | 200748 kb |
Host | smart-e5b9af33-006e-49dd-83a5-4c884c0ebec2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238860336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2238860336 |
Directory | /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/2.rstmgr_smoke.4158558860 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 259189672 ps |
CPU time | 1.63 seconds |
Started | May 05 12:20:52 PM PDT 24 |
Finished | May 05 12:20:54 PM PDT 24 |
Peak memory | 201272 kb |
Host | smart-d180963a-aa7d-4a2a-a916-9c66c96e700e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158558860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4158558860 |
Directory | /workspace/2.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/2.rstmgr_stress_all.1672927895 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 5175316262 ps |
CPU time | 18.34 seconds |
Started | May 05 12:20:01 PM PDT 24 |
Finished | May 05 12:20:20 PM PDT 24 |
Peak memory | 210844 kb |
Host | smart-79e934dd-e8b6-4d9e-a196-8cfa6da11e6f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672927895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1672927895 |
Directory | /workspace/2.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/2.rstmgr_sw_rst.3915092555 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 462078416 ps |
CPU time | 2.45 seconds |
Started | May 05 12:23:27 PM PDT 24 |
Finished | May 05 12:23:30 PM PDT 24 |
Peak memory | 200704 kb |
Host | smart-cee9ad7f-49fb-4f5e-a1e7-ceabafc2da09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915092555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3915092555 |
Directory | /workspace/2.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3069393409 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 110940274 ps |
CPU time | 1.12 seconds |
Started | May 05 12:23:00 PM PDT 24 |
Finished | May 05 12:23:02 PM PDT 24 |
Peak memory | 200752 kb |
Host | smart-62e7cf65-5ba8-4455-8c89-35b38a28992e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069393409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3069393409 |
Directory | /workspace/2.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/20.rstmgr_alert_test.1128472161 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 78987105 ps |
CPU time | 0.87 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:06 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-6cc19792-a174-4712-aec4-b5e233de7804 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128472161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1128472161 |
Directory | /workspace/20.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1973928032 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 1217415344 ps |
CPU time | 5.61 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:11 PM PDT 24 |
Peak memory | 218248 kb |
Host | smart-eb74b8b2-1b3e-464f-a711-89c64f6f3218 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1973928032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1973928032 |
Directory | /workspace/20.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1782354276 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 245946532 ps |
CPU time | 1.06 seconds |
Started | May 05 12:25:10 PM PDT 24 |
Finished | May 05 12:25:13 PM PDT 24 |
Peak memory | 217988 kb |
Host | smart-9306f6bf-2766-429c-9cac-b550f5866f36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782354276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1782354276 |
Directory | /workspace/20.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/20.rstmgr_por_stretcher.3624254897 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 113791179 ps |
CPU time | 0.79 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:07 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-b7b0bfcb-8c51-420c-a65e-fedc0a61c9af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3624254897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3624254897 |
Directory | /workspace/20.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/20.rstmgr_reset.2635684089 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 1725123957 ps |
CPU time | 6.71 seconds |
Started | May 05 12:25:27 PM PDT 24 |
Finished | May 05 12:25:34 PM PDT 24 |
Peak memory | 200868 kb |
Host | smart-8dd582f6-3337-4ca1-81a2-ba4446fd14c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635684089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2635684089 |
Directory | /workspace/20.rstmgr_reset/latest |
Test location | /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4091776652 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 109066645 ps |
CPU time | 1.02 seconds |
Started | May 05 12:25:35 PM PDT 24 |
Finished | May 05 12:25:37 PM PDT 24 |
Peak memory | 200780 kb |
Host | smart-3216fbdf-9299-4f7d-8939-36d59ab3e1aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091776652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4091776652 |
Directory | /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/20.rstmgr_smoke.4118036699 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 205914097 ps |
CPU time | 1.46 seconds |
Started | May 05 12:25:04 PM PDT 24 |
Finished | May 05 12:25:07 PM PDT 24 |
Peak memory | 200872 kb |
Host | smart-c9b4da6a-6064-423a-93ad-6c19cc77aacf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4118036699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4118036699 |
Directory | /workspace/20.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/20.rstmgr_stress_all.4140858026 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 19645233597 ps |
CPU time | 72.28 seconds |
Started | May 05 12:25:12 PM PDT 24 |
Finished | May 05 12:26:26 PM PDT 24 |
Peak memory | 209292 kb |
Host | smart-a1fcff7e-8db9-467b-a352-8ccc0a4bc271 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140858026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4140858026 |
Directory | /workspace/20.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/20.rstmgr_sw_rst.985635486 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 134288462 ps |
CPU time | 1.66 seconds |
Started | May 05 12:25:02 PM PDT 24 |
Finished | May 05 12:25:05 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-b27eb56b-d861-4409-8c41-532ee6f7eb18 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985635486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.985635486 |
Directory | /workspace/20.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.829325187 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 82736747 ps |
CPU time | 0.84 seconds |
Started | May 05 12:25:15 PM PDT 24 |
Finished | May 05 12:25:17 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-0167dedc-3883-4625-b0b1-e98c36930873 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829325187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.829325187 |
Directory | /workspace/20.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/21.rstmgr_alert_test.1328164484 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 72692357 ps |
CPU time | 0.77 seconds |
Started | May 05 12:25:16 PM PDT 24 |
Finished | May 05 12:25:18 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-bc963355-ec38-434d-b0cf-ae50f111718e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328164484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1328164484 |
Directory | /workspace/21.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2428081563 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 1225300073 ps |
CPU time | 5.39 seconds |
Started | May 05 12:25:17 PM PDT 24 |
Finished | May 05 12:25:23 PM PDT 24 |
Peak memory | 217300 kb |
Host | smart-6b9208f3-e98c-4455-a5b3-06f94da9c355 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428081563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2428081563 |
Directory | /workspace/21.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2051813296 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 244205055 ps |
CPU time | 1.02 seconds |
Started | May 05 12:25:13 PM PDT 24 |
Finished | May 05 12:25:21 PM PDT 24 |
Peak memory | 217928 kb |
Host | smart-843525b2-576a-4669-a158-746cd719dce0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051813296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2051813296 |
Directory | /workspace/21.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/21.rstmgr_por_stretcher.2558845930 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 170899953 ps |
CPU time | 0.87 seconds |
Started | May 05 12:25:12 PM PDT 24 |
Finished | May 05 12:25:14 PM PDT 24 |
Peak memory | 200628 kb |
Host | smart-8a34f068-de82-4b83-841c-1880f84d2418 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558845930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2558845930 |
Directory | /workspace/21.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/21.rstmgr_reset.3521039076 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 837751116 ps |
CPU time | 4.15 seconds |
Started | May 05 12:25:17 PM PDT 24 |
Finished | May 05 12:25:22 PM PDT 24 |
Peak memory | 200876 kb |
Host | smart-c66a7625-80ee-418e-9353-1dc32aae67dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521039076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3521039076 |
Directory | /workspace/21.rstmgr_reset/latest |
Test location | /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1372601019 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 110570387 ps |
CPU time | 1.02 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 200780 kb |
Host | smart-98b79aa7-a512-4d75-adc9-ab0c745592a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372601019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1372601019 |
Directory | /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/21.rstmgr_smoke.1706951007 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 219534046 ps |
CPU time | 1.51 seconds |
Started | May 05 12:25:36 PM PDT 24 |
Finished | May 05 12:25:38 PM PDT 24 |
Peak memory | 200956 kb |
Host | smart-a356b089-7a5b-44d8-b884-54838c517abf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706951007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1706951007 |
Directory | /workspace/21.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/21.rstmgr_stress_all.269116214 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 2313001874 ps |
CPU time | 9.22 seconds |
Started | May 05 12:25:02 PM PDT 24 |
Finished | May 05 12:25:13 PM PDT 24 |
Peak memory | 209264 kb |
Host | smart-b63f10b4-8d80-4f7f-a87f-6107251f5897 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269116214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.269116214 |
Directory | /workspace/21.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/21.rstmgr_sw_rst.310843657 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 134286700 ps |
CPU time | 1.56 seconds |
Started | May 05 12:25:07 PM PDT 24 |
Finished | May 05 12:25:10 PM PDT 24 |
Peak memory | 208980 kb |
Host | smart-95bf4286-8e67-4270-aea1-2afd9f52f6b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310843657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.310843657 |
Directory | /workspace/21.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2727825933 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 241290222 ps |
CPU time | 1.46 seconds |
Started | May 05 12:25:15 PM PDT 24 |
Finished | May 05 12:25:18 PM PDT 24 |
Peak memory | 200848 kb |
Host | smart-a13883d3-45e2-4167-a51c-d3b105c82648 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2727825933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2727825933 |
Directory | /workspace/21.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/22.rstmgr_alert_test.1450727387 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 76495863 ps |
CPU time | 0.84 seconds |
Started | May 05 12:26:17 PM PDT 24 |
Finished | May 05 12:26:20 PM PDT 24 |
Peak memory | 197656 kb |
Host | smart-452a12b8-b3c1-44c0-803b-68f437dbe722 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450727387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1450727387 |
Directory | /workspace/22.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1063561097 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 1889301146 ps |
CPU time | 7.02 seconds |
Started | May 05 12:25:34 PM PDT 24 |
Finished | May 05 12:25:42 PM PDT 24 |
Peak memory | 218332 kb |
Host | smart-777a5b61-d993-4cde-a132-8db7a8602464 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063561097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1063561097 |
Directory | /workspace/22.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1917286299 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 244997448 ps |
CPU time | 1.04 seconds |
Started | May 05 12:25:14 PM PDT 24 |
Finished | May 05 12:25:17 PM PDT 24 |
Peak memory | 217896 kb |
Host | smart-7fa8f242-9c4b-429f-a059-24630dbd9477 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917286299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1917286299 |
Directory | /workspace/22.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/22.rstmgr_por_stretcher.259376788 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 179784739 ps |
CPU time | 0.82 seconds |
Started | May 05 12:25:10 PM PDT 24 |
Finished | May 05 12:25:12 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-317245ea-02aa-4e9f-8157-7cfc364ca52a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259376788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.259376788 |
Directory | /workspace/22.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/22.rstmgr_reset.1562074485 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 1575219874 ps |
CPU time | 6.29 seconds |
Started | May 05 12:25:11 PM PDT 24 |
Finished | May 05 12:25:18 PM PDT 24 |
Peak memory | 200888 kb |
Host | smart-db1375b5-bcc4-47a7-86e1-0482a5df7de3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562074485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1562074485 |
Directory | /workspace/22.rstmgr_reset/latest |
Test location | /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3820281100 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 106154602 ps |
CPU time | 1.05 seconds |
Started | May 05 12:25:13 PM PDT 24 |
Finished | May 05 12:25:16 PM PDT 24 |
Peak memory | 200728 kb |
Host | smart-d380bfc5-661d-4da7-b139-946c698966ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3820281100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3820281100 |
Directory | /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/22.rstmgr_smoke.1705922924 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 122359980 ps |
CPU time | 1.14 seconds |
Started | May 05 12:25:18 PM PDT 24 |
Finished | May 05 12:25:20 PM PDT 24 |
Peak memory | 200964 kb |
Host | smart-64d995a9-c2cf-42d0-8232-85c11ca1eb60 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705922924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1705922924 |
Directory | /workspace/22.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/22.rstmgr_stress_all.1146015446 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 14176610718 ps |
CPU time | 48.05 seconds |
Started | May 05 12:26:17 PM PDT 24 |
Finished | May 05 12:27:07 PM PDT 24 |
Peak memory | 206648 kb |
Host | smart-0f43d52a-fc5a-4985-a331-15add294b7ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146015446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1146015446 |
Directory | /workspace/22.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/22.rstmgr_sw_rst.2656797082 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 451525964 ps |
CPU time | 2.69 seconds |
Started | May 05 12:25:18 PM PDT 24 |
Finished | May 05 12:25:21 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-2573d28a-3a53-4075-9419-bd68166b00c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656797082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2656797082 |
Directory | /workspace/22.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1612746385 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 146772322 ps |
CPU time | 1.16 seconds |
Started | May 05 12:25:20 PM PDT 24 |
Finished | May 05 12:25:22 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-d12178ad-7ece-42c2-b12f-10e31dd5320f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612746385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1612746385 |
Directory | /workspace/22.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/23.rstmgr_alert_test.1009703130 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 88612693 ps |
CPU time | 0.82 seconds |
Started | May 05 12:25:23 PM PDT 24 |
Finished | May 05 12:25:24 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-bbb5cdb0-3f90-4e8a-b9e6-711d45b986fc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009703130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1009703130 |
Directory | /workspace/23.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.798987783 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 1220669573 ps |
CPU time | 5.48 seconds |
Started | May 05 12:25:13 PM PDT 24 |
Finished | May 05 12:25:20 PM PDT 24 |
Peak memory | 218340 kb |
Host | smart-e00ad6d3-c2c6-4947-afd1-f0f7b2f73d25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798987783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.798987783 |
Directory | /workspace/23.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3657947245 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 244907193 ps |
CPU time | 1.04 seconds |
Started | May 05 12:25:20 PM PDT 24 |
Finished | May 05 12:25:22 PM PDT 24 |
Peak memory | 217780 kb |
Host | smart-dba69157-2ee7-4d90-8a0e-f3d4ab002f3c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657947245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3657947245 |
Directory | /workspace/23.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/23.rstmgr_por_stretcher.1101688110 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 153315887 ps |
CPU time | 0.88 seconds |
Started | May 05 12:25:17 PM PDT 24 |
Finished | May 05 12:25:19 PM PDT 24 |
Peak memory | 200560 kb |
Host | smart-3e5d9d1e-8fa4-49dd-963e-d7bd0acf9b74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101688110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1101688110 |
Directory | /workspace/23.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/23.rstmgr_reset.2141295882 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 813573089 ps |
CPU time | 4.45 seconds |
Started | May 05 12:26:35 PM PDT 24 |
Finished | May 05 12:26:40 PM PDT 24 |
Peak memory | 200880 kb |
Host | smart-bf1536ac-2e48-4ed9-b5cd-88d3a6e3f78c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141295882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2141295882 |
Directory | /workspace/23.rstmgr_reset/latest |
Test location | /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1213030259 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 144985767 ps |
CPU time | 1.14 seconds |
Started | May 05 12:25:37 PM PDT 24 |
Finished | May 05 12:25:39 PM PDT 24 |
Peak memory | 200732 kb |
Host | smart-ab2a1015-6d75-4fdf-9bb5-377e7f33e17c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213030259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1213030259 |
Directory | /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/23.rstmgr_smoke.2308916453 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 106409473 ps |
CPU time | 1.08 seconds |
Started | May 05 12:26:33 PM PDT 24 |
Finished | May 05 12:26:35 PM PDT 24 |
Peak memory | 200840 kb |
Host | smart-00d01c8e-11b2-420e-999b-f59baf7e1b03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2308916453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2308916453 |
Directory | /workspace/23.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/23.rstmgr_stress_all.1252706512 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 4953739165 ps |
CPU time | 18.58 seconds |
Started | May 05 12:25:18 PM PDT 24 |
Finished | May 05 12:25:37 PM PDT 24 |
Peak memory | 201084 kb |
Host | smart-315e8477-fc4a-4dbe-ad03-5d7c4dca0b1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252706512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1252706512 |
Directory | /workspace/23.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/23.rstmgr_sw_rst.2492467531 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 512493545 ps |
CPU time | 2.75 seconds |
Started | May 05 12:26:17 PM PDT 24 |
Finished | May 05 12:26:21 PM PDT 24 |
Peak memory | 197976 kb |
Host | smart-c8de90f7-464e-40c7-9d6b-531ad2aaee3a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492467531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2492467531 |
Directory | /workspace/23.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1221335032 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 273113453 ps |
CPU time | 1.5 seconds |
Started | May 05 12:26:17 PM PDT 24 |
Finished | May 05 12:26:20 PM PDT 24 |
Peak memory | 198432 kb |
Host | smart-371af7a3-a48b-4be8-8bcc-962099ea57eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221335032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1221335032 |
Directory | /workspace/23.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/24.rstmgr_alert_test.251054206 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 76369227 ps |
CPU time | 0.81 seconds |
Started | May 05 12:25:29 PM PDT 24 |
Finished | May 05 12:25:31 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-dacf776d-2741-4e85-889d-d0b026e57e82 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251054206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.251054206 |
Directory | /workspace/24.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3475844311 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 1909087998 ps |
CPU time | 6.86 seconds |
Started | May 05 12:25:27 PM PDT 24 |
Finished | May 05 12:25:35 PM PDT 24 |
Peak memory | 218452 kb |
Host | smart-fc8b8234-6de5-46b8-a78c-85b05334a8b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475844311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3475844311 |
Directory | /workspace/24.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3616205442 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 244865693 ps |
CPU time | 1.03 seconds |
Started | May 05 12:25:27 PM PDT 24 |
Finished | May 05 12:25:29 PM PDT 24 |
Peak memory | 217944 kb |
Host | smart-42745a6e-df3a-429b-a605-730dcdcf8fbd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3616205442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3616205442 |
Directory | /workspace/24.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/24.rstmgr_por_stretcher.2865989404 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 153859767 ps |
CPU time | 0.84 seconds |
Started | May 05 12:25:25 PM PDT 24 |
Finished | May 05 12:25:26 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-e6dfb10c-9800-43a4-b8c8-0461b9b97f15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865989404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2865989404 |
Directory | /workspace/24.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/24.rstmgr_reset.1120169957 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1847666282 ps |
CPU time | 6.78 seconds |
Started | May 05 12:25:15 PM PDT 24 |
Finished | May 05 12:25:24 PM PDT 24 |
Peak memory | 200832 kb |
Host | smart-b2df242b-3414-4f26-91c8-1e8a62c4b943 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120169957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1120169957 |
Directory | /workspace/24.rstmgr_reset/latest |
Test location | /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1422668078 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 101076874 ps |
CPU time | 0.95 seconds |
Started | May 05 12:25:31 PM PDT 24 |
Finished | May 05 12:25:33 PM PDT 24 |
Peak memory | 200764 kb |
Host | smart-a6125b67-84a8-48ab-ab68-5c9dfb5481a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422668078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1422668078 |
Directory | /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/24.rstmgr_smoke.1475596110 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 193233278 ps |
CPU time | 1.29 seconds |
Started | May 05 12:25:31 PM PDT 24 |
Finished | May 05 12:25:33 PM PDT 24 |
Peak memory | 200904 kb |
Host | smart-d6992fb4-46ba-46f8-8a24-b2e1f61900af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475596110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1475596110 |
Directory | /workspace/24.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/24.rstmgr_stress_all.4161570442 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 9688941717 ps |
CPU time | 39.77 seconds |
Started | May 05 12:25:24 PM PDT 24 |
Finished | May 05 12:26:04 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-c45b8c07-ec2d-4cbf-aa9a-e34e06230b26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161570442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4161570442 |
Directory | /workspace/24.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/24.rstmgr_sw_rst.2167447133 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 388746471 ps |
CPU time | 2.44 seconds |
Started | May 05 12:26:17 PM PDT 24 |
Finished | May 05 12:26:21 PM PDT 24 |
Peak memory | 197672 kb |
Host | smart-67e9c6b2-453d-456b-a5ce-ff9a81b4d04a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167447133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2167447133 |
Directory | /workspace/24.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2669857068 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 167279868 ps |
CPU time | 1.11 seconds |
Started | May 05 12:25:24 PM PDT 24 |
Finished | May 05 12:25:26 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-58fd4e22-14d2-45bc-8cd7-8a17b5b0e820 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2669857068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2669857068 |
Directory | /workspace/24.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/25.rstmgr_alert_test.3111008351 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 66949895 ps |
CPU time | 0.72 seconds |
Started | May 05 12:25:39 PM PDT 24 |
Finished | May 05 12:25:41 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-a5046ded-c0f8-4a1c-9fad-b944daec732d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111008351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3111008351 |
Directory | /workspace/25.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3822650125 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 1223087056 ps |
CPU time | 5.42 seconds |
Started | May 05 12:25:41 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 217532 kb |
Host | smart-be80a539-edf4-4902-b78d-a995f11e313e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3822650125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3822650125 |
Directory | /workspace/25.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3136246686 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 244575058 ps |
CPU time | 1.11 seconds |
Started | May 05 12:25:26 PM PDT 24 |
Finished | May 05 12:25:28 PM PDT 24 |
Peak memory | 217844 kb |
Host | smart-b2a59604-004c-4e4b-a4ef-27cecb1cee5e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136246686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3136246686 |
Directory | /workspace/25.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/25.rstmgr_por_stretcher.1947023361 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 268112398 ps |
CPU time | 0.94 seconds |
Started | May 05 12:25:32 PM PDT 24 |
Finished | May 05 12:25:34 PM PDT 24 |
Peak memory | 200532 kb |
Host | smart-2ebcb8ff-9917-4cc8-b752-5fd6326d9430 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947023361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1947023361 |
Directory | /workspace/25.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/25.rstmgr_reset.2010032919 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 1629748859 ps |
CPU time | 6.17 seconds |
Started | May 05 12:25:48 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 200996 kb |
Host | smart-2d9b3840-8e93-4701-940f-4032d159b01e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010032919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2010032919 |
Directory | /workspace/25.rstmgr_reset/latest |
Test location | /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.4087213552 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 96161658 ps |
CPU time | 0.97 seconds |
Started | May 05 12:25:37 PM PDT 24 |
Finished | May 05 12:25:39 PM PDT 24 |
Peak memory | 200800 kb |
Host | smart-ab032fcf-bc5c-448b-a21f-8316a9515ad0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087213552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.4087213552 |
Directory | /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/25.rstmgr_smoke.3841635385 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 216614034 ps |
CPU time | 1.42 seconds |
Started | May 05 12:25:29 PM PDT 24 |
Finished | May 05 12:25:31 PM PDT 24 |
Peak memory | 200864 kb |
Host | smart-4a39fed3-e70b-4f8c-87e0-90685703fe21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841635385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3841635385 |
Directory | /workspace/25.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/25.rstmgr_stress_all.952811794 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 314861915 ps |
CPU time | 1.65 seconds |
Started | May 05 12:25:39 PM PDT 24 |
Finished | May 05 12:25:42 PM PDT 24 |
Peak memory | 200976 kb |
Host | smart-eda5ef59-32d6-4207-9978-c12428fa9515 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952811794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.952811794 |
Directory | /workspace/25.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/25.rstmgr_sw_rst.679698504 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 142942337 ps |
CPU time | 1.81 seconds |
Started | May 05 12:25:35 PM PDT 24 |
Finished | May 05 12:25:38 PM PDT 24 |
Peak memory | 200800 kb |
Host | smart-c69be856-8b5f-4e0e-8165-7fb14392d180 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679698504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.679698504 |
Directory | /workspace/25.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2815470891 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 156903175 ps |
CPU time | 1.11 seconds |
Started | May 05 12:25:34 PM PDT 24 |
Finished | May 05 12:25:36 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-c8f4ce17-9720-4ea5-9d03-5b4851ca9b64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815470891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2815470891 |
Directory | /workspace/25.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/26.rstmgr_alert_test.1120007184 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 87195671 ps |
CPU time | 0.87 seconds |
Started | May 05 12:25:28 PM PDT 24 |
Finished | May 05 12:25:29 PM PDT 24 |
Peak memory | 200536 kb |
Host | smart-2f395b2e-faeb-4555-99d8-1ce7f628e67b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120007184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1120007184 |
Directory | /workspace/26.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.477706371 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1223216960 ps |
CPU time | 5.81 seconds |
Started | May 05 12:25:26 PM PDT 24 |
Finished | May 05 12:25:33 PM PDT 24 |
Peak memory | 217220 kb |
Host | smart-ed13891e-504f-4f07-b02f-a9f14f6ae05f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=477706371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.477706371 |
Directory | /workspace/26.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1998729806 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 244402278 ps |
CPU time | 1.05 seconds |
Started | May 05 12:25:25 PM PDT 24 |
Finished | May 05 12:25:27 PM PDT 24 |
Peak memory | 217904 kb |
Host | smart-718c68cd-08c2-497f-a542-9d144f1e250a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998729806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1998729806 |
Directory | /workspace/26.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/26.rstmgr_por_stretcher.2778811050 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 156155609 ps |
CPU time | 0.82 seconds |
Started | May 05 12:25:39 PM PDT 24 |
Finished | May 05 12:25:41 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-e22f16de-3e72-4f1d-84d1-05a438440641 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2778811050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2778811050 |
Directory | /workspace/26.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/26.rstmgr_reset.3890382836 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 1021585375 ps |
CPU time | 4.68 seconds |
Started | May 05 12:25:29 PM PDT 24 |
Finished | May 05 12:25:34 PM PDT 24 |
Peak memory | 201100 kb |
Host | smart-6a177ffd-af21-4f62-8e08-7770f1d4645d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3890382836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3890382836 |
Directory | /workspace/26.rstmgr_reset/latest |
Test location | /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3249540076 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 110323842 ps |
CPU time | 1.03 seconds |
Started | May 05 12:25:28 PM PDT 24 |
Finished | May 05 12:25:30 PM PDT 24 |
Peak memory | 200732 kb |
Host | smart-d7ac22ac-4b66-422a-8bc7-74542e456602 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249540076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3249540076 |
Directory | /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/26.rstmgr_smoke.4283889911 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 121910488 ps |
CPU time | 1.21 seconds |
Started | May 05 12:25:39 PM PDT 24 |
Finished | May 05 12:25:42 PM PDT 24 |
Peak memory | 200920 kb |
Host | smart-0f31a44b-79a3-4581-a996-fcbf3e4c15fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283889911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4283889911 |
Directory | /workspace/26.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/26.rstmgr_stress_all.3891366444 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 507448817 ps |
CPU time | 2.82 seconds |
Started | May 05 12:25:19 PM PDT 24 |
Finished | May 05 12:25:22 PM PDT 24 |
Peak memory | 200956 kb |
Host | smart-61203f1e-4419-4d85-ad7b-434f137513e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891366444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3891366444 |
Directory | /workspace/26.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/26.rstmgr_sw_rst.2969813859 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 312815005 ps |
CPU time | 2.06 seconds |
Started | May 05 12:25:17 PM PDT 24 |
Finished | May 05 12:25:20 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-bb635e4a-f5e3-4ac0-a05b-dc57264fad82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969813859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2969813859 |
Directory | /workspace/26.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3757129211 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 166040209 ps |
CPU time | 1.24 seconds |
Started | May 05 12:25:36 PM PDT 24 |
Finished | May 05 12:25:38 PM PDT 24 |
Peak memory | 200960 kb |
Host | smart-244a221a-f2f7-44b8-aa9c-5c6ab49f5d0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757129211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3757129211 |
Directory | /workspace/26.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/27.rstmgr_alert_test.3361323699 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 83904265 ps |
CPU time | 0.8 seconds |
Started | May 05 12:25:38 PM PDT 24 |
Finished | May 05 12:25:40 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-9d49f2ca-8413-43b9-a4c1-8a527c10762f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361323699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3361323699 |
Directory | /workspace/27.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2794771409 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 2187209115 ps |
CPU time | 7.62 seconds |
Started | May 05 12:25:26 PM PDT 24 |
Finished | May 05 12:25:34 PM PDT 24 |
Peak memory | 221504 kb |
Host | smart-e04ace85-0ec5-4fdd-a7af-ea6c08f63229 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794771409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2794771409 |
Directory | /workspace/27.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.4048437214 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 244149289 ps |
CPU time | 1.16 seconds |
Started | May 05 12:25:34 PM PDT 24 |
Finished | May 05 12:25:37 PM PDT 24 |
Peak memory | 218028 kb |
Host | smart-65b3ea8a-dc7d-40ef-a63a-44a82a2ee286 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048437214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.4048437214 |
Directory | /workspace/27.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/27.rstmgr_por_stretcher.3048172990 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 79689854 ps |
CPU time | 0.74 seconds |
Started | May 05 12:25:28 PM PDT 24 |
Finished | May 05 12:25:30 PM PDT 24 |
Peak memory | 200500 kb |
Host | smart-c0575801-afdc-4e71-86a3-7d09d0030272 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048172990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3048172990 |
Directory | /workspace/27.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/27.rstmgr_reset.2071874648 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 945290993 ps |
CPU time | 4.48 seconds |
Started | May 05 12:25:27 PM PDT 24 |
Finished | May 05 12:25:32 PM PDT 24 |
Peak memory | 200908 kb |
Host | smart-6e9890e6-5095-4797-90e3-9fd9c53db8d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071874648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2071874648 |
Directory | /workspace/27.rstmgr_reset/latest |
Test location | /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.601719926 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 108161248 ps |
CPU time | 1.02 seconds |
Started | May 05 12:25:19 PM PDT 24 |
Finished | May 05 12:25:21 PM PDT 24 |
Peak memory | 200764 kb |
Host | smart-440d7223-f3a4-451b-ad00-217f15afb5c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601719926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.601719926 |
Directory | /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/27.rstmgr_smoke.3263359544 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 197700801 ps |
CPU time | 1.53 seconds |
Started | May 05 12:25:16 PM PDT 24 |
Finished | May 05 12:25:19 PM PDT 24 |
Peak memory | 201100 kb |
Host | smart-5d009345-ee6d-4252-b4ce-77f7b1c5b34b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263359544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3263359544 |
Directory | /workspace/27.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/27.rstmgr_stress_all.1514716155 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 3621469669 ps |
CPU time | 14.3 seconds |
Started | May 05 12:25:35 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 209180 kb |
Host | smart-f572079d-f542-4e52-b5f3-6085a4ff2448 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514716155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1514716155 |
Directory | /workspace/27.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.559723635 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 282499126 ps |
CPU time | 1.69 seconds |
Started | May 05 12:25:20 PM PDT 24 |
Finished | May 05 12:25:28 PM PDT 24 |
Peak memory | 200896 kb |
Host | smart-98e7312a-32b0-4b8d-a0ad-42b7d10dcdee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559723635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.559723635 |
Directory | /workspace/27.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/28.rstmgr_alert_test.1570147261 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 71324647 ps |
CPU time | 0.75 seconds |
Started | May 05 12:25:39 PM PDT 24 |
Finished | May 05 12:25:41 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-e346c0d1-e013-4d46-9c90-89ed1e01fa2f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570147261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1570147261 |
Directory | /workspace/28.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3607870768 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 1223285545 ps |
CPU time | 5.93 seconds |
Started | May 05 12:25:30 PM PDT 24 |
Finished | May 05 12:25:37 PM PDT 24 |
Peak memory | 230280 kb |
Host | smart-ba5384c5-9dbf-4d08-adb4-b1b77be9c82d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607870768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3607870768 |
Directory | /workspace/28.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3251485690 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 245648531 ps |
CPU time | 1.06 seconds |
Started | May 05 12:25:27 PM PDT 24 |
Finished | May 05 12:25:29 PM PDT 24 |
Peak memory | 217864 kb |
Host | smart-2e90fb5d-3c73-4c22-b2d7-ee8885b217a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251485690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3251485690 |
Directory | /workspace/28.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/28.rstmgr_por_stretcher.969345773 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 222983895 ps |
CPU time | 0.96 seconds |
Started | May 05 12:25:46 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 200496 kb |
Host | smart-a44763e4-d471-46cd-8fc2-53b0ff4c969b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=969345773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.969345773 |
Directory | /workspace/28.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/28.rstmgr_reset.1759537346 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 1300755559 ps |
CPU time | 5.45 seconds |
Started | May 05 12:25:40 PM PDT 24 |
Finished | May 05 12:25:47 PM PDT 24 |
Peak memory | 200924 kb |
Host | smart-e4c74194-13be-4153-9969-abeee72b1c93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759537346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1759537346 |
Directory | /workspace/28.rstmgr_reset/latest |
Test location | /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3442172488 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 169332475 ps |
CPU time | 1.22 seconds |
Started | May 05 12:25:26 PM PDT 24 |
Finished | May 05 12:25:28 PM PDT 24 |
Peak memory | 201048 kb |
Host | smart-a25c5bc3-00ff-45d5-8aae-b39b27b0cd43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442172488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3442172488 |
Directory | /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/28.rstmgr_smoke.2406346765 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 121364580 ps |
CPU time | 1.25 seconds |
Started | May 05 12:25:33 PM PDT 24 |
Finished | May 05 12:25:35 PM PDT 24 |
Peak memory | 200988 kb |
Host | smart-aa93bc9b-a623-4e30-904b-f042b38b46ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406346765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2406346765 |
Directory | /workspace/28.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/28.rstmgr_stress_all.236798954 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 6027536479 ps |
CPU time | 20.11 seconds |
Started | May 05 12:25:24 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 200968 kb |
Host | smart-e3342c47-356d-431e-bcc6-0d43377c557a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236798954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.236798954 |
Directory | /workspace/28.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/28.rstmgr_sw_rst.2868949386 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 358905342 ps |
CPU time | 2.25 seconds |
Started | May 05 12:25:33 PM PDT 24 |
Finished | May 05 12:25:36 PM PDT 24 |
Peak memory | 200668 kb |
Host | smart-3821fe4f-18d8-4828-baa3-f765e89bd185 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868949386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2868949386 |
Directory | /workspace/28.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3021652619 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 209193095 ps |
CPU time | 1.33 seconds |
Started | May 05 12:25:17 PM PDT 24 |
Finished | May 05 12:25:22 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-d50c3a33-9b2d-4c5c-9c08-74e9286cc295 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021652619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3021652619 |
Directory | /workspace/28.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/29.rstmgr_alert_test.3709816488 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 78120348 ps |
CPU time | 0.8 seconds |
Started | May 05 12:25:28 PM PDT 24 |
Finished | May 05 12:25:30 PM PDT 24 |
Peak memory | 200472 kb |
Host | smart-fbfd9b5e-5122-42aa-b443-9fcf74aa5f2d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709816488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3709816488 |
Directory | /workspace/29.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1182012829 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1242377079 ps |
CPU time | 5.55 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:59 PM PDT 24 |
Peak memory | 217760 kb |
Host | smart-7429645b-f74d-4ee4-9684-277b6204bdfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182012829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1182012829 |
Directory | /workspace/29.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3132498608 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 243952357 ps |
CPU time | 1.03 seconds |
Started | May 05 12:25:41 PM PDT 24 |
Finished | May 05 12:25:43 PM PDT 24 |
Peak memory | 218076 kb |
Host | smart-e0382d3e-585b-46e4-b37f-2da402b6eb2d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3132498608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3132498608 |
Directory | /workspace/29.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/29.rstmgr_por_stretcher.125349429 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 160328999 ps |
CPU time | 0.89 seconds |
Started | May 05 12:25:26 PM PDT 24 |
Finished | May 05 12:25:28 PM PDT 24 |
Peak memory | 200584 kb |
Host | smart-168105de-8e47-4a52-a802-b4f7b4ab17fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125349429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.125349429 |
Directory | /workspace/29.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/29.rstmgr_reset.329954224 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 1473993415 ps |
CPU time | 5.46 seconds |
Started | May 05 12:25:41 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 200876 kb |
Host | smart-e7c7223b-d489-4d14-a811-b257fe97687c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329954224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.329954224 |
Directory | /workspace/29.rstmgr_reset/latest |
Test location | /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4196722879 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 154534983 ps |
CPU time | 1.15 seconds |
Started | May 05 12:26:55 PM PDT 24 |
Finished | May 05 12:26:58 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-e6f5200d-588f-4189-a4c2-d9a370b7cc60 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196722879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4196722879 |
Directory | /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/29.rstmgr_smoke.2215629852 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 129442842 ps |
CPU time | 1.27 seconds |
Started | May 05 12:25:24 PM PDT 24 |
Finished | May 05 12:25:26 PM PDT 24 |
Peak memory | 200992 kb |
Host | smart-9a46f120-5250-4f23-a9cc-816a6b5f0809 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215629852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2215629852 |
Directory | /workspace/29.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/29.rstmgr_stress_all.1295790371 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 4276111597 ps |
CPU time | 18.89 seconds |
Started | May 05 12:25:29 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 210836 kb |
Host | smart-725f6c73-f13e-46ef-967b-1a1f15b4079b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295790371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1295790371 |
Directory | /workspace/29.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/29.rstmgr_sw_rst.3554846528 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 337073413 ps |
CPU time | 2.44 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:25:46 PM PDT 24 |
Peak memory | 201024 kb |
Host | smart-352138e9-7420-4b37-80ad-83de8bf19897 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554846528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3554846528 |
Directory | /workspace/29.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2362027565 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 91944389 ps |
CPU time | 0.86 seconds |
Started | May 05 12:25:31 PM PDT 24 |
Finished | May 05 12:25:33 PM PDT 24 |
Peak memory | 200736 kb |
Host | smart-2157036a-d3a1-40a9-bc1e-7c2fe3918002 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362027565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2362027565 |
Directory | /workspace/29.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/3.rstmgr_alert_test.3928499468 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 66779486 ps |
CPU time | 0.76 seconds |
Started | May 05 12:25:47 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 200216 kb |
Host | smart-ec63e475-0dc6-46ac-b357-8574e9fbfc04 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928499468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3928499468 |
Directory | /workspace/3.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.265967624 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 1909006840 ps |
CPU time | 7.06 seconds |
Started | May 05 12:25:11 PM PDT 24 |
Finished | May 05 12:25:20 PM PDT 24 |
Peak memory | 218404 kb |
Host | smart-23f423da-9c02-4f87-8c22-9d0115143df9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265967624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.265967624 |
Directory | /workspace/3.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1021204183 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 244737717 ps |
CPU time | 1.03 seconds |
Started | May 05 12:24:59 PM PDT 24 |
Finished | May 05 12:25:01 PM PDT 24 |
Peak memory | 217968 kb |
Host | smart-d49017c9-eb76-489b-b4d0-1b8e38a435c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021204183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1021204183 |
Directory | /workspace/3.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/3.rstmgr_por_stretcher.3384571594 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 100362957 ps |
CPU time | 0.75 seconds |
Started | May 05 12:24:34 PM PDT 24 |
Finished | May 05 12:24:36 PM PDT 24 |
Peak memory | 200296 kb |
Host | smart-5e37bdac-c252-421b-902d-0c5f67069704 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3384571594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3384571594 |
Directory | /workspace/3.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/3.rstmgr_reset.1557933631 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 977739226 ps |
CPU time | 4.87 seconds |
Started | May 05 12:20:56 PM PDT 24 |
Finished | May 05 12:21:02 PM PDT 24 |
Peak memory | 200988 kb |
Host | smart-16cd1a7e-181a-4b99-a269-1fdb3c85fc34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1557933631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1557933631 |
Directory | /workspace/3.rstmgr_reset/latest |
Test location | /workspace/coverage/default/3.rstmgr_sec_cm.2513298592 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 8350386022 ps |
CPU time | 15.02 seconds |
Started | May 05 12:24:54 PM PDT 24 |
Finished | May 05 12:25:12 PM PDT 24 |
Peak memory | 217376 kb |
Host | smart-17eb2976-39d3-4af8-b1c8-8d9482d128f2 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513298592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2513298592 |
Directory | /workspace/3.rstmgr_sec_cm/latest |
Test location | /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3082051759 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 99989383 ps |
CPU time | 0.97 seconds |
Started | May 05 12:24:48 PM PDT 24 |
Finished | May 05 12:24:51 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-d3283e87-f172-490b-a022-97bacd48187f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082051759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3082051759 |
Directory | /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/3.rstmgr_smoke.2513289861 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 255983632 ps |
CPU time | 1.76 seconds |
Started | May 05 12:22:09 PM PDT 24 |
Finished | May 05 12:22:11 PM PDT 24 |
Peak memory | 200964 kb |
Host | smart-5a359b46-5c05-4447-8df0-e50129004ae5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2513289861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2513289861 |
Directory | /workspace/3.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/3.rstmgr_stress_all.4197019924 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 2117931663 ps |
CPU time | 7.73 seconds |
Started | May 05 12:24:54 PM PDT 24 |
Finished | May 05 12:25:04 PM PDT 24 |
Peak memory | 200896 kb |
Host | smart-22455190-a7bf-458b-be12-eeba7c5949a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197019924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.4197019924 |
Directory | /workspace/3.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/3.rstmgr_sw_rst.1031433394 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 407238655 ps |
CPU time | 2.32 seconds |
Started | May 05 12:21:26 PM PDT 24 |
Finished | May 05 12:21:29 PM PDT 24 |
Peak memory | 200780 kb |
Host | smart-e47449ad-c84c-44eb-a969-f1799d7fb391 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031433394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1031433394 |
Directory | /workspace/3.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3268134832 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 136497798 ps |
CPU time | 1.08 seconds |
Started | May 05 12:24:37 PM PDT 24 |
Finished | May 05 12:24:40 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-48f0a47e-ae5f-4f72-825d-028d972ab78a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3268134832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3268134832 |
Directory | /workspace/3.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/30.rstmgr_alert_test.3442462631 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 67071747 ps |
CPU time | 0.74 seconds |
Started | May 05 12:26:30 PM PDT 24 |
Finished | May 05 12:26:31 PM PDT 24 |
Peak memory | 200468 kb |
Host | smart-17da2496-45d3-4cd1-93fc-8a659dc228d8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442462631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3442462631 |
Directory | /workspace/30.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1989665603 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 2350890113 ps |
CPU time | 7.66 seconds |
Started | May 05 12:25:36 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 218168 kb |
Host | smart-eac65f75-8b09-4648-9e0b-723b877c724c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989665603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1989665603 |
Directory | /workspace/30.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2849095533 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 244153884 ps |
CPU time | 1.08 seconds |
Started | May 05 12:25:36 PM PDT 24 |
Finished | May 05 12:25:38 PM PDT 24 |
Peak memory | 217916 kb |
Host | smart-3a0aa7e1-dbbf-4d34-8a92-51ba1d9dd598 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2849095533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2849095533 |
Directory | /workspace/30.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/30.rstmgr_por_stretcher.2942746734 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 136208362 ps |
CPU time | 0.82 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-ae2dec19-4197-4a58-b42e-df0bcb719f9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2942746734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2942746734 |
Directory | /workspace/30.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/30.rstmgr_reset.4235122343 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 1670428851 ps |
CPU time | 6.5 seconds |
Started | May 05 12:25:48 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 200868 kb |
Host | smart-b91d991d-72f8-46aa-b1ca-4f918bcdb8a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235122343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4235122343 |
Directory | /workspace/30.rstmgr_reset/latest |
Test location | /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.265149597 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 153116256 ps |
CPU time | 1.11 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:25:44 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-530482dd-b7f1-4683-9c72-6e8746e44bef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265149597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.265149597 |
Directory | /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/30.rstmgr_smoke.3614233443 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 197275902 ps |
CPU time | 1.32 seconds |
Started | May 05 12:25:35 PM PDT 24 |
Finished | May 05 12:25:37 PM PDT 24 |
Peak memory | 200884 kb |
Host | smart-a9b4cdbc-2275-4e00-adbd-3db0e2af9e6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614233443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3614233443 |
Directory | /workspace/30.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/30.rstmgr_stress_all.2023120691 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 9419901020 ps |
CPU time | 31.03 seconds |
Started | May 05 12:25:45 PM PDT 24 |
Finished | May 05 12:26:17 PM PDT 24 |
Peak memory | 209204 kb |
Host | smart-3f9deb4d-d972-4a67-8889-e254e2e7f870 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023120691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2023120691 |
Directory | /workspace/30.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/30.rstmgr_sw_rst.592216757 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 246534709 ps |
CPU time | 1.8 seconds |
Started | May 05 12:25:28 PM PDT 24 |
Finished | May 05 12:25:30 PM PDT 24 |
Peak memory | 200712 kb |
Host | smart-4b3723b2-691d-4c9e-9a9c-866c398415e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592216757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.592216757 |
Directory | /workspace/30.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.653236954 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 194161773 ps |
CPU time | 1.18 seconds |
Started | May 05 12:25:29 PM PDT 24 |
Finished | May 05 12:25:31 PM PDT 24 |
Peak memory | 200760 kb |
Host | smart-2c2831c4-3c52-4aa5-91cb-ad0d2ea21469 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653236954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.653236954 |
Directory | /workspace/30.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/31.rstmgr_alert_test.669338278 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 66612964 ps |
CPU time | 0.75 seconds |
Started | May 05 12:25:47 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-41c93a5b-3492-43ae-abba-0087dbfd8b75 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669338278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.669338278 |
Directory | /workspace/31.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.54274017 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 1233792596 ps |
CPU time | 5.59 seconds |
Started | May 05 12:25:31 PM PDT 24 |
Finished | May 05 12:25:37 PM PDT 24 |
Peak memory | 217752 kb |
Host | smart-cfa8df29-395c-4550-a52e-2025dc66bd2f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54274017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.54274017 |
Directory | /workspace/31.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3587805908 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 243945599 ps |
CPU time | 1.07 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 217760 kb |
Host | smart-820b3310-4647-476f-8c1e-3958dfa8aa93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3587805908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3587805908 |
Directory | /workspace/31.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/31.rstmgr_por_stretcher.2185118562 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 87203562 ps |
CPU time | 0.74 seconds |
Started | May 05 12:25:30 PM PDT 24 |
Finished | May 05 12:25:32 PM PDT 24 |
Peak memory | 200544 kb |
Host | smart-c51eecde-8c83-40f3-9a33-7deb189306be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2185118562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2185118562 |
Directory | /workspace/31.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/31.rstmgr_reset.4090839195 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 1759672248 ps |
CPU time | 6.32 seconds |
Started | May 05 12:25:40 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 200928 kb |
Host | smart-ba92e1d4-000f-4109-bf32-282968af7222 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090839195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4090839195 |
Directory | /workspace/31.rstmgr_reset/latest |
Test location | /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.4146875393 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 110237148 ps |
CPU time | 0.96 seconds |
Started | May 05 12:25:32 PM PDT 24 |
Finished | May 05 12:25:34 PM PDT 24 |
Peak memory | 200784 kb |
Host | smart-564af9f7-168a-4b5d-b06e-3491fd7ec7cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146875393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.4146875393 |
Directory | /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/31.rstmgr_smoke.2186146610 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 124400596 ps |
CPU time | 1.19 seconds |
Started | May 05 12:25:28 PM PDT 24 |
Finished | May 05 12:25:30 PM PDT 24 |
Peak memory | 200832 kb |
Host | smart-c2163f07-33d3-4992-b857-8c784debea21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186146610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2186146610 |
Directory | /workspace/31.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/31.rstmgr_stress_all.356228804 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 580207073 ps |
CPU time | 2.68 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:25:46 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-ee76b8df-ef4a-4df2-a22f-1fe720e0c1b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356228804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.356228804 |
Directory | /workspace/31.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/31.rstmgr_sw_rst.1123526453 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 148162465 ps |
CPU time | 1.67 seconds |
Started | May 05 12:25:29 PM PDT 24 |
Finished | May 05 12:25:31 PM PDT 24 |
Peak memory | 200692 kb |
Host | smart-c7141c55-5381-4ede-bf96-e6653d262a05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123526453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1123526453 |
Directory | /workspace/31.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.393242733 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 111701485 ps |
CPU time | 0.98 seconds |
Started | May 05 12:25:34 PM PDT 24 |
Finished | May 05 12:25:35 PM PDT 24 |
Peak memory | 200632 kb |
Host | smart-7a06455a-e491-4d93-a2b8-87f2c5d3d32f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393242733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.393242733 |
Directory | /workspace/31.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/32.rstmgr_alert_test.2751028368 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 70485051 ps |
CPU time | 0.78 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-3eafd1b8-2e46-4689-9f79-824e9906a4cc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751028368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2751028368 |
Directory | /workspace/32.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2225409097 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 1231451410 ps |
CPU time | 5.68 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 218428 kb |
Host | smart-3dbf5e36-e679-4c16-b36a-84e932d31cef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225409097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2225409097 |
Directory | /workspace/32.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2068187376 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 243998514 ps |
CPU time | 1.07 seconds |
Started | May 05 12:25:46 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 217924 kb |
Host | smart-24078efe-403b-4238-907e-0842fea2141e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068187376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2068187376 |
Directory | /workspace/32.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/32.rstmgr_por_stretcher.3039185508 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 127165736 ps |
CPU time | 0.81 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-891fb17d-4e43-4dee-83b3-24380cd88e0a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039185508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3039185508 |
Directory | /workspace/32.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/32.rstmgr_reset.10903870 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 708459225 ps |
CPU time | 3.68 seconds |
Started | May 05 12:25:27 PM PDT 24 |
Finished | May 05 12:25:32 PM PDT 24 |
Peak memory | 200916 kb |
Host | smart-b5ae5d81-a9c7-4101-90df-d61498fcb2eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10903870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.10903870 |
Directory | /workspace/32.rstmgr_reset/latest |
Test location | /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3546463196 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 181748652 ps |
CPU time | 1.18 seconds |
Started | May 05 12:25:38 PM PDT 24 |
Finished | May 05 12:25:40 PM PDT 24 |
Peak memory | 200684 kb |
Host | smart-24628139-8c0a-48a1-9632-e8df26abe745 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546463196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3546463196 |
Directory | /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/32.rstmgr_smoke.2425789076 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 119740464 ps |
CPU time | 1.16 seconds |
Started | May 05 12:25:29 PM PDT 24 |
Finished | May 05 12:25:31 PM PDT 24 |
Peak memory | 200836 kb |
Host | smart-3f089ebb-afa8-44ea-8991-28a7b39a20a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425789076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2425789076 |
Directory | /workspace/32.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/32.rstmgr_stress_all.2526621776 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 4213476660 ps |
CPU time | 15.84 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:26:10 PM PDT 24 |
Peak memory | 209204 kb |
Host | smart-f37ae465-1cef-4b87-a4b9-41001f088c8f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526621776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2526621776 |
Directory | /workspace/32.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/32.rstmgr_sw_rst.1433875296 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 123121878 ps |
CPU time | 1.41 seconds |
Started | May 05 12:25:34 PM PDT 24 |
Finished | May 05 12:25:36 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-b7e809db-c481-4e2e-8e7f-43245a359547 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433875296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1433875296 |
Directory | /workspace/32.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.503727016 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 210117868 ps |
CPU time | 1.26 seconds |
Started | May 05 12:25:38 PM PDT 24 |
Finished | May 05 12:25:41 PM PDT 24 |
Peak memory | 200748 kb |
Host | smart-fb51dc14-e79f-4699-bd0e-f022f1bc184c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=503727016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.503727016 |
Directory | /workspace/32.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/33.rstmgr_alert_test.2314927701 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 68272210 ps |
CPU time | 0.79 seconds |
Started | May 05 12:25:46 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-de809873-7603-4d8d-ad13-0a219147885f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314927701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2314927701 |
Directory | /workspace/33.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.4193512701 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 2360762985 ps |
CPU time | 7.69 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:26:01 PM PDT 24 |
Peak memory | 217784 kb |
Host | smart-04aa5562-988a-4ee7-a2fc-6727aa8b8aa8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4193512701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.4193512701 |
Directory | /workspace/33.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3259376295 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 244405457 ps |
CPU time | 1.07 seconds |
Started | May 05 12:25:36 PM PDT 24 |
Finished | May 05 12:25:38 PM PDT 24 |
Peak memory | 217948 kb |
Host | smart-b390bb99-8ac5-43cb-9ec4-666b547e88b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3259376295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3259376295 |
Directory | /workspace/33.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/33.rstmgr_por_stretcher.2124774517 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 192647690 ps |
CPU time | 0.86 seconds |
Started | May 05 12:25:47 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 200520 kb |
Host | smart-515d73f7-b90e-40f5-a15c-6b5455a5050c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124774517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2124774517 |
Directory | /workspace/33.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/33.rstmgr_reset.1386388972 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1743080529 ps |
CPU time | 6.46 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:51 PM PDT 24 |
Peak memory | 200996 kb |
Host | smart-08cb1791-8785-4a7d-97fb-aa862acd9139 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386388972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1386388972 |
Directory | /workspace/33.rstmgr_reset/latest |
Test location | /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.677915401 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 102703822 ps |
CPU time | 0.98 seconds |
Started | May 05 12:25:34 PM PDT 24 |
Finished | May 05 12:25:36 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-23479ea3-f8d5-4d99-a1b7-5603c272eed4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677915401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.677915401 |
Directory | /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/33.rstmgr_smoke.888397857 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 120188914 ps |
CPU time | 1.17 seconds |
Started | May 05 12:25:45 PM PDT 24 |
Finished | May 05 12:25:47 PM PDT 24 |
Peak memory | 200960 kb |
Host | smart-ff733594-e674-4e2f-9a76-133df1c9a7a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888397857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.888397857 |
Directory | /workspace/33.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/33.rstmgr_stress_all.3696152597 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 1526328881 ps |
CPU time | 6.22 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:59 PM PDT 24 |
Peak memory | 200996 kb |
Host | smart-e3de125c-d97c-42a5-9b93-e2df65ae4c79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696152597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3696152597 |
Directory | /workspace/33.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/33.rstmgr_sw_rst.1539806605 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 431990871 ps |
CPU time | 2.46 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:25:58 PM PDT 24 |
Peak memory | 208964 kb |
Host | smart-a655bf88-5843-494a-a08f-e6dc7bdc64b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539806605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1539806605 |
Directory | /workspace/33.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.532719133 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 158070453 ps |
CPU time | 1.2 seconds |
Started | May 05 12:25:37 PM PDT 24 |
Finished | May 05 12:25:39 PM PDT 24 |
Peak memory | 200904 kb |
Host | smart-82463966-1a37-498a-a207-73c1fe1bfdf3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532719133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.532719133 |
Directory | /workspace/33.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/34.rstmgr_alert_test.1904647942 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 85939701 ps |
CPU time | 0.8 seconds |
Started | May 05 12:25:38 PM PDT 24 |
Finished | May 05 12:25:40 PM PDT 24 |
Peak memory | 200528 kb |
Host | smart-36ebad7e-91e1-4663-89fa-65d99218c32c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904647942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1904647942 |
Directory | /workspace/34.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3191330634 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 2354674552 ps |
CPU time | 7.4 seconds |
Started | May 05 12:25:41 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 217680 kb |
Host | smart-79d7b69f-27ec-40cb-acfe-26641295fab3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191330634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3191330634 |
Directory | /workspace/34.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1363411706 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 248280742 ps |
CPU time | 1.02 seconds |
Started | May 05 12:25:39 PM PDT 24 |
Finished | May 05 12:25:41 PM PDT 24 |
Peak memory | 209524 kb |
Host | smart-e4c4d1c5-2157-4b09-a18d-0bbe67a9bf73 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1363411706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1363411706 |
Directory | /workspace/34.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/34.rstmgr_por_stretcher.518514582 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 145870074 ps |
CPU time | 0.86 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 200588 kb |
Host | smart-78326d5a-5464-4150-a44d-62a5370794c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=518514582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.518514582 |
Directory | /workspace/34.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/34.rstmgr_reset.904844165 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 976535452 ps |
CPU time | 4.84 seconds |
Started | May 05 12:25:46 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 200956 kb |
Host | smart-c733e974-de9d-4503-ba45-a9549cde73d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=904844165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.904844165 |
Directory | /workspace/34.rstmgr_reset/latest |
Test location | /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2540301057 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 107700660 ps |
CPU time | 1.05 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:46 PM PDT 24 |
Peak memory | 200732 kb |
Host | smart-f7a775bf-d145-4875-8265-7754e560865e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540301057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2540301057 |
Directory | /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/34.rstmgr_smoke.927187626 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 121207050 ps |
CPU time | 1.26 seconds |
Started | May 05 12:25:38 PM PDT 24 |
Finished | May 05 12:25:41 PM PDT 24 |
Peak memory | 200840 kb |
Host | smart-8d55e8fb-e8b7-4213-ac63-8d721ff88900 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927187626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.927187626 |
Directory | /workspace/34.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/34.rstmgr_stress_all.2717333527 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 8257773131 ps |
CPU time | 27.87 seconds |
Started | May 05 12:25:44 PM PDT 24 |
Finished | May 05 12:26:13 PM PDT 24 |
Peak memory | 201032 kb |
Host | smart-f4db5e03-6c70-4f4d-9fe3-db6b3052132e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717333527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2717333527 |
Directory | /workspace/34.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/34.rstmgr_sw_rst.2289608982 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 312950469 ps |
CPU time | 2.15 seconds |
Started | May 05 12:25:48 PM PDT 24 |
Finished | May 05 12:25:51 PM PDT 24 |
Peak memory | 200788 kb |
Host | smart-dd502ad8-1d6d-4a11-884b-3563e615946d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289608982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2289608982 |
Directory | /workspace/34.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1986021450 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 86527838 ps |
CPU time | 0.83 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:25:57 PM PDT 24 |
Peak memory | 200680 kb |
Host | smart-a41a0272-059c-4f30-ab60-2db73d2a723c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986021450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1986021450 |
Directory | /workspace/34.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/35.rstmgr_alert_test.1868888937 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 60165888 ps |
CPU time | 0.75 seconds |
Started | May 05 12:25:32 PM PDT 24 |
Finished | May 05 12:25:33 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-9be6c600-4d0e-410b-bf4f-ea0679e0d2fb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868888937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1868888937 |
Directory | /workspace/35.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1700579931 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 1227213858 ps |
CPU time | 5.29 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:59 PM PDT 24 |
Peak memory | 222436 kb |
Host | smart-7570a71f-5a3e-4a1a-bee3-1df706f62e0d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700579931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1700579931 |
Directory | /workspace/35.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3391232981 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 243866292 ps |
CPU time | 1.13 seconds |
Started | May 05 12:25:37 PM PDT 24 |
Finished | May 05 12:25:39 PM PDT 24 |
Peak memory | 217948 kb |
Host | smart-99d63095-5dc2-483a-9e18-9dd7261359e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391232981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3391232981 |
Directory | /workspace/35.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/35.rstmgr_por_stretcher.3331923175 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 242613775 ps |
CPU time | 1.01 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200460 kb |
Host | smart-87b96f32-5785-491f-aa06-4d1779910be6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331923175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3331923175 |
Directory | /workspace/35.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/35.rstmgr_reset.2811838735 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 862945786 ps |
CPU time | 4.04 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 200820 kb |
Host | smart-a58330b3-09c8-44fc-989a-0b78dc3e650a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811838735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2811838735 |
Directory | /workspace/35.rstmgr_reset/latest |
Test location | /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4275094981 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 148234215 ps |
CPU time | 1.13 seconds |
Started | May 05 12:25:34 PM PDT 24 |
Finished | May 05 12:25:36 PM PDT 24 |
Peak memory | 200732 kb |
Host | smart-ecd0eac9-9d8f-4077-9e86-3d69ffad78b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275094981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4275094981 |
Directory | /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/35.rstmgr_smoke.360514232 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 200567332 ps |
CPU time | 1.4 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:46 PM PDT 24 |
Peak memory | 200900 kb |
Host | smart-cf1ce397-b601-4a50-8796-8771ba49426b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360514232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.360514232 |
Directory | /workspace/35.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/35.rstmgr_stress_all.266414674 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 9513991351 ps |
CPU time | 33.57 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:26:18 PM PDT 24 |
Peak memory | 209312 kb |
Host | smart-e846ef35-3faf-42fe-ab4d-706325884ea3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266414674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.266414674 |
Directory | /workspace/35.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/35.rstmgr_sw_rst.1460685447 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 384654173 ps |
CPU time | 2.2 seconds |
Started | May 05 12:25:47 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 200700 kb |
Host | smart-0c874581-937f-4075-abaa-f449e11983a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460685447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1460685447 |
Directory | /workspace/35.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3330605467 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 116024312 ps |
CPU time | 1.04 seconds |
Started | May 05 12:25:44 PM PDT 24 |
Finished | May 05 12:25:46 PM PDT 24 |
Peak memory | 200844 kb |
Host | smart-3b36f1f9-baab-4c77-a452-7c39be0f5a7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330605467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3330605467 |
Directory | /workspace/35.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/36.rstmgr_alert_test.3838907892 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 66979948 ps |
CPU time | 0.77 seconds |
Started | May 05 12:25:48 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 200536 kb |
Host | smart-ec07e87e-95cf-42ed-85bb-44c9d784c684 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838907892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3838907892 |
Directory | /workspace/36.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4051628606 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 1229957076 ps |
CPU time | 5.6 seconds |
Started | May 05 12:25:41 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 218388 kb |
Host | smart-701d9662-a2f1-4abe-8fa6-138399f0c666 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051628606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4051628606 |
Directory | /workspace/36.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3769036061 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 243654755 ps |
CPU time | 1.19 seconds |
Started | May 05 12:25:44 PM PDT 24 |
Finished | May 05 12:25:47 PM PDT 24 |
Peak memory | 217844 kb |
Host | smart-432ef2e7-b146-43dd-9d27-41b2eff8a184 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769036061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3769036061 |
Directory | /workspace/36.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/36.rstmgr_por_stretcher.2021022797 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 85735226 ps |
CPU time | 0.74 seconds |
Started | May 05 12:25:41 PM PDT 24 |
Finished | May 05 12:25:43 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-8c3d6cd7-b947-4138-af2a-0a2ee963f53c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2021022797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2021022797 |
Directory | /workspace/36.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/36.rstmgr_reset.1258749425 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 2306133792 ps |
CPU time | 8.31 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 201152 kb |
Host | smart-87e1cce5-6564-49de-852a-1eddcc52857e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258749425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1258749425 |
Directory | /workspace/36.rstmgr_reset/latest |
Test location | /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.53596571 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 102985519 ps |
CPU time | 0.95 seconds |
Started | May 05 12:25:47 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 200744 kb |
Host | smart-7baf9da5-94fa-453a-bb36-36323adfb01c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53596571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.53596571 |
Directory | /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/36.rstmgr_smoke.331169190 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 114068866 ps |
CPU time | 1.16 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200988 kb |
Host | smart-1e77fea5-e11a-4cd4-a268-610a2fe996df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=331169190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.331169190 |
Directory | /workspace/36.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/36.rstmgr_stress_all.2067733543 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 3430722161 ps |
CPU time | 15.49 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:25:59 PM PDT 24 |
Peak memory | 201016 kb |
Host | smart-e645351b-eccb-4a1f-af60-60a6f61ba52f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067733543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2067733543 |
Directory | /workspace/36.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/36.rstmgr_sw_rst.3532559389 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 267539938 ps |
CPU time | 1.77 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 200624 kb |
Host | smart-073694e0-5403-41fa-b849-0d36139550d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532559389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3532559389 |
Directory | /workspace/36.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3143666790 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 127865879 ps |
CPU time | 1.14 seconds |
Started | May 05 12:25:44 PM PDT 24 |
Finished | May 05 12:25:47 PM PDT 24 |
Peak memory | 200724 kb |
Host | smart-04c43aa0-ae1b-4967-842f-e8b94b80de7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143666790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3143666790 |
Directory | /workspace/36.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/37.rstmgr_alert_test.4191711455 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 63112457 ps |
CPU time | 0.75 seconds |
Started | May 05 12:25:27 PM PDT 24 |
Finished | May 05 12:25:29 PM PDT 24 |
Peak memory | 200612 kb |
Host | smart-d69e77bf-e6fb-4efc-b713-ee87b80ede7d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191711455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4191711455 |
Directory | /workspace/37.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3458405236 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1229918134 ps |
CPU time | 5.38 seconds |
Started | May 05 12:25:38 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 218340 kb |
Host | smart-afd4dbb9-7d24-4dbc-8813-20116c56b377 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458405236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3458405236 |
Directory | /workspace/37.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1054265171 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 244948861 ps |
CPU time | 1.2 seconds |
Started | May 05 12:25:36 PM PDT 24 |
Finished | May 05 12:25:38 PM PDT 24 |
Peak memory | 217756 kb |
Host | smart-75f3a4a0-ce45-447a-98e5-ad53e9a31234 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054265171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1054265171 |
Directory | /workspace/37.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/37.rstmgr_por_stretcher.4003001846 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 134325865 ps |
CPU time | 0.78 seconds |
Started | May 05 12:25:44 PM PDT 24 |
Finished | May 05 12:25:46 PM PDT 24 |
Peak memory | 200472 kb |
Host | smart-35cf33b8-ed3e-47ea-8b37-01181358ad27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003001846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.4003001846 |
Directory | /workspace/37.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/37.rstmgr_reset.776977653 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 1576131282 ps |
CPU time | 5.79 seconds |
Started | May 05 12:25:45 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 200956 kb |
Host | smart-6b2ef612-96c9-4a89-ab64-b268bb0ec427 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=776977653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.776977653 |
Directory | /workspace/37.rstmgr_reset/latest |
Test location | /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1240024474 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 164167019 ps |
CPU time | 1.13 seconds |
Started | May 05 12:25:40 PM PDT 24 |
Finished | May 05 12:25:43 PM PDT 24 |
Peak memory | 200736 kb |
Host | smart-6ce17fef-6f35-45f3-b4d8-b7fd0a7f5d2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240024474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1240024474 |
Directory | /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/37.rstmgr_smoke.2163140296 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 239567284 ps |
CPU time | 1.4 seconds |
Started | May 05 12:25:47 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 200940 kb |
Host | smart-37627825-0b0c-4ca4-8176-5d524d3223dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163140296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2163140296 |
Directory | /workspace/37.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/37.rstmgr_stress_all.2688531271 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 6985838707 ps |
CPU time | 24.83 seconds |
Started | May 05 12:25:36 PM PDT 24 |
Finished | May 05 12:26:02 PM PDT 24 |
Peak memory | 200972 kb |
Host | smart-bad7032f-b42f-40aa-a963-925cbf22ae72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688531271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2688531271 |
Directory | /workspace/37.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/37.rstmgr_sw_rst.1742636847 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 360412775 ps |
CPU time | 2.04 seconds |
Started | May 05 12:25:46 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 200812 kb |
Host | smart-de5103ad-fd98-4a07-a8ac-b052e0faa9b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742636847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1742636847 |
Directory | /workspace/37.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2327090286 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 71909396 ps |
CPU time | 0.76 seconds |
Started | May 05 12:25:30 PM PDT 24 |
Finished | May 05 12:25:32 PM PDT 24 |
Peak memory | 200756 kb |
Host | smart-afa1ae60-8f99-4aa1-aade-293875a95ba3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2327090286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2327090286 |
Directory | /workspace/37.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/38.rstmgr_alert_test.2460225606 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 64067318 ps |
CPU time | 0.73 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200520 kb |
Host | smart-0aacb9c1-9f0c-4169-843e-6d6bb47d9f93 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460225606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2460225606 |
Directory | /workspace/38.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3714692567 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 1229415698 ps |
CPU time | 5.57 seconds |
Started | May 05 12:25:45 PM PDT 24 |
Finished | May 05 12:25:51 PM PDT 24 |
Peak memory | 221964 kb |
Host | smart-e1c68390-b47c-4e07-9468-11e30017fd4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714692567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3714692567 |
Directory | /workspace/38.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3240815287 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 243613595 ps |
CPU time | 1.11 seconds |
Started | May 05 12:25:45 PM PDT 24 |
Finished | May 05 12:25:47 PM PDT 24 |
Peak memory | 217896 kb |
Host | smart-0122cd01-6b18-42c2-a16e-2986b52facf2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240815287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3240815287 |
Directory | /workspace/38.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/38.rstmgr_por_stretcher.3236961111 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 220112105 ps |
CPU time | 0.89 seconds |
Started | May 05 12:25:35 PM PDT 24 |
Finished | May 05 12:25:37 PM PDT 24 |
Peak memory | 200604 kb |
Host | smart-5b5faa80-03d7-448e-9824-8a617b5d7a17 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236961111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3236961111 |
Directory | /workspace/38.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/38.rstmgr_reset.4173272845 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 1048331747 ps |
CPU time | 4.75 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 200952 kb |
Host | smart-ae95d47f-b997-4023-aaed-2417621596b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173272845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.4173272845 |
Directory | /workspace/38.rstmgr_reset/latest |
Test location | /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3542879747 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 107276441 ps |
CPU time | 1.01 seconds |
Started | May 05 12:25:41 PM PDT 24 |
Finished | May 05 12:25:43 PM PDT 24 |
Peak memory | 200816 kb |
Host | smart-0bf64b61-4e97-4497-84e2-6545e617e092 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542879747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3542879747 |
Directory | /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/38.rstmgr_smoke.3079867042 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 234875887 ps |
CPU time | 1.48 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 200940 kb |
Host | smart-c9236ff3-f36e-40af-909b-84a43990f0f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079867042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3079867042 |
Directory | /workspace/38.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/38.rstmgr_stress_all.3929525023 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 2313122868 ps |
CPU time | 10.93 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 209168 kb |
Host | smart-220d3548-623c-4bd0-b1ee-a00c75ae6647 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929525023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3929525023 |
Directory | /workspace/38.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/38.rstmgr_sw_rst.386100324 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 305024034 ps |
CPU time | 1.99 seconds |
Started | May 05 12:25:50 PM PDT 24 |
Finished | May 05 12:25:53 PM PDT 24 |
Peak memory | 209040 kb |
Host | smart-c38db22b-4e49-4284-8243-b51524098740 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386100324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.386100324 |
Directory | /workspace/38.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3632702788 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 177565951 ps |
CPU time | 1.32 seconds |
Started | May 05 12:25:46 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 200732 kb |
Host | smart-44edb39f-3172-4208-b437-82db046c6df1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632702788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3632702788 |
Directory | /workspace/38.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/39.rstmgr_alert_test.758836896 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 70733223 ps |
CPU time | 0.77 seconds |
Started | May 05 12:26:07 PM PDT 24 |
Finished | May 05 12:26:08 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-e73419f5-6056-4339-9ac1-fc9e806f7fe7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758836896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.758836896 |
Directory | /workspace/39.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2923252329 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 2360291258 ps |
CPU time | 8.42 seconds |
Started | May 05 12:25:55 PM PDT 24 |
Finished | May 05 12:26:05 PM PDT 24 |
Peak memory | 222608 kb |
Host | smart-36eb4d6d-b8be-46fa-a947-e0b377dd480c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923252329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2923252329 |
Directory | /workspace/39.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.389037627 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 243454583 ps |
CPU time | 1.14 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 217948 kb |
Host | smart-64e3c9b9-cb2b-49ed-9233-c017b2e8c178 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389037627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.389037627 |
Directory | /workspace/39.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/39.rstmgr_por_stretcher.3540946593 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 120666695 ps |
CPU time | 0.84 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 200580 kb |
Host | smart-00d899c1-cdad-4a1b-ae9e-6b941369b29b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540946593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3540946593 |
Directory | /workspace/39.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/39.rstmgr_reset.1663511056 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 838130419 ps |
CPU time | 4.02 seconds |
Started | May 05 12:26:11 PM PDT 24 |
Finished | May 05 12:26:16 PM PDT 24 |
Peak memory | 200864 kb |
Host | smart-1b650f5c-09b4-4eb9-a0e5-daf0ec97c278 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663511056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1663511056 |
Directory | /workspace/39.rstmgr_reset/latest |
Test location | /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1631772448 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 168621838 ps |
CPU time | 1.18 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 200792 kb |
Host | smart-1dd69126-0d65-4857-90dc-fe5d9a25e380 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631772448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1631772448 |
Directory | /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/39.rstmgr_smoke.3462520937 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 242957854 ps |
CPU time | 1.36 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:53 PM PDT 24 |
Peak memory | 200964 kb |
Host | smart-dfda636c-e576-446d-ac7e-e712a255b47a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462520937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3462520937 |
Directory | /workspace/39.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/39.rstmgr_stress_all.3289554463 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 112165114 ps |
CPU time | 0.85 seconds |
Started | May 05 12:25:55 PM PDT 24 |
Finished | May 05 12:25:58 PM PDT 24 |
Peak memory | 200508 kb |
Host | smart-ef668e2e-6dbd-449f-9504-e7474f37b3b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289554463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3289554463 |
Directory | /workspace/39.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/39.rstmgr_sw_rst.3885573536 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 364415151 ps |
CPU time | 2.2 seconds |
Started | May 05 12:25:50 PM PDT 24 |
Finished | May 05 12:25:53 PM PDT 24 |
Peak memory | 200744 kb |
Host | smart-b37995e2-d5b3-4fb3-9e5b-16f192b833ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885573536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3885573536 |
Directory | /workspace/39.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3621097977 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 142325260 ps |
CPU time | 1.12 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:25:51 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-94c44559-9b24-4763-bcf9-6e3e4f73e533 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621097977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3621097977 |
Directory | /workspace/39.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/4.rstmgr_alert_test.4092445606 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 79274745 ps |
CPU time | 0.77 seconds |
Started | May 05 12:24:53 PM PDT 24 |
Finished | May 05 12:24:57 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-3ebefca5-2caf-42b2-917e-dc93d690b627 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092445606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4092445606 |
Directory | /workspace/4.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.650334114 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 2186294109 ps |
CPU time | 7.19 seconds |
Started | May 05 12:24:51 PM PDT 24 |
Finished | May 05 12:25:02 PM PDT 24 |
Peak memory | 222352 kb |
Host | smart-19b0a14e-65a8-4cec-9438-f38bfad9bf7e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650334114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.650334114 |
Directory | /workspace/4.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.676529827 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 243791848 ps |
CPU time | 1.08 seconds |
Started | May 05 12:24:54 PM PDT 24 |
Finished | May 05 12:24:58 PM PDT 24 |
Peak memory | 217756 kb |
Host | smart-b4898d8a-8522-4b4f-8f64-8ec771ab718b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676529827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.676529827 |
Directory | /workspace/4.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/4.rstmgr_por_stretcher.3215163795 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 226495514 ps |
CPU time | 0.96 seconds |
Started | May 05 12:25:00 PM PDT 24 |
Finished | May 05 12:25:02 PM PDT 24 |
Peak memory | 200456 kb |
Host | smart-5f77c0e3-886a-41e0-bc77-b44a8a37f5a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215163795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3215163795 |
Directory | /workspace/4.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/4.rstmgr_reset.1514609179 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 1411128083 ps |
CPU time | 5.57 seconds |
Started | May 05 12:26:03 PM PDT 24 |
Finished | May 05 12:26:10 PM PDT 24 |
Peak memory | 200836 kb |
Host | smart-3c691661-3a40-48c3-a0dd-5f45af9c1aaa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514609179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1514609179 |
Directory | /workspace/4.rstmgr_reset/latest |
Test location | /workspace/coverage/default/4.rstmgr_sec_cm.294976066 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 8277018045 ps |
CPU time | 15.95 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:25:08 PM PDT 24 |
Peak memory | 218244 kb |
Host | smart-483e7cd1-abba-4b64-8d3c-353d31e7decd |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294976066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.294976066 |
Directory | /workspace/4.rstmgr_sec_cm/latest |
Test location | /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2046127807 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 105124663 ps |
CPU time | 1.02 seconds |
Started | May 05 12:24:48 PM PDT 24 |
Finished | May 05 12:24:51 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-cdab93b3-44d5-4535-9c96-e1f3f961f910 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046127807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2046127807 |
Directory | /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/4.rstmgr_smoke.3214977497 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 198696148 ps |
CPU time | 1.29 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:24:54 PM PDT 24 |
Peak memory | 200968 kb |
Host | smart-2aadc893-befd-4205-89c7-72ea9ee21feb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214977497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3214977497 |
Directory | /workspace/4.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/4.rstmgr_stress_all.3700368690 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 3325056704 ps |
CPU time | 11.4 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:25:04 PM PDT 24 |
Peak memory | 200964 kb |
Host | smart-5cafae2b-5b39-43ce-8185-58f1f288e43e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700368690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3700368690 |
Directory | /workspace/4.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/4.rstmgr_sw_rst.3790619379 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 138368301 ps |
CPU time | 1.67 seconds |
Started | May 05 12:25:00 PM PDT 24 |
Finished | May 05 12:25:03 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-958ee2f0-b881-4373-9f23-d7da5618e644 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3790619379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3790619379 |
Directory | /workspace/4.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/40.rstmgr_alert_test.3067553508 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 85410578 ps |
CPU time | 0.78 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:46 PM PDT 24 |
Peak memory | 200588 kb |
Host | smart-dd2bbe58-5d21-40a8-9b5e-d65233db4868 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067553508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3067553508 |
Directory | /workspace/40.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2078311110 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1887375189 ps |
CPU time | 7.18 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:26:02 PM PDT 24 |
Peak memory | 217868 kb |
Host | smart-b23606ae-1aff-411e-962f-43d2d95f4bcc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078311110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2078311110 |
Directory | /workspace/40.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1850492074 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 244413631 ps |
CPU time | 1.11 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 217936 kb |
Host | smart-c64a75ba-e7d0-4764-926c-cf8d3d56b52f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850492074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1850492074 |
Directory | /workspace/40.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/40.rstmgr_por_stretcher.1084305521 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 79040549 ps |
CPU time | 0.75 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 200492 kb |
Host | smart-adcae9d9-598f-44f7-bf85-820fa718b18c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084305521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1084305521 |
Directory | /workspace/40.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/40.rstmgr_reset.2007044539 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 1578668649 ps |
CPU time | 5.62 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:26:00 PM PDT 24 |
Peak memory | 200992 kb |
Host | smart-3e659879-7555-4380-ab22-6a1d428cc8a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007044539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2007044539 |
Directory | /workspace/40.rstmgr_reset/latest |
Test location | /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2425047575 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 142870355 ps |
CPU time | 1.12 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200844 kb |
Host | smart-80e9beef-88f4-4c29-a954-2bd8139adca4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425047575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2425047575 |
Directory | /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/40.rstmgr_smoke.3758575750 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 252611224 ps |
CPU time | 1.4 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 200820 kb |
Host | smart-f610b014-3019-417d-ad22-3b4f2ec33990 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3758575750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3758575750 |
Directory | /workspace/40.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/40.rstmgr_stress_all.3357092687 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 5869209633 ps |
CPU time | 19.27 seconds |
Started | May 05 12:26:02 PM PDT 24 |
Finished | May 05 12:26:22 PM PDT 24 |
Peak memory | 209312 kb |
Host | smart-9c8700ab-d72d-4e89-b867-71e5ff49b546 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357092687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3357092687 |
Directory | /workspace/40.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/40.rstmgr_sw_rst.333991361 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 128441709 ps |
CPU time | 1.59 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 200776 kb |
Host | smart-609adbad-d8cd-4bc3-a8c9-07d511413c0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333991361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.333991361 |
Directory | /workspace/40.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2262262027 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 152359055 ps |
CPU time | 1.06 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:25:57 PM PDT 24 |
Peak memory | 200784 kb |
Host | smart-9eb66d34-fc47-4770-a281-84aa9eb6bd96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2262262027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2262262027 |
Directory | /workspace/40.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/41.rstmgr_alert_test.108129582 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 77064739 ps |
CPU time | 0.75 seconds |
Started | May 05 12:25:45 PM PDT 24 |
Finished | May 05 12:25:47 PM PDT 24 |
Peak memory | 200576 kb |
Host | smart-a4e1aba9-6847-4bdb-9d72-d3be9a512845 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108129582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.108129582 |
Directory | /workspace/41.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1035321482 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 1223083978 ps |
CPU time | 5.46 seconds |
Started | May 05 12:25:35 PM PDT 24 |
Finished | May 05 12:25:41 PM PDT 24 |
Peak memory | 222316 kb |
Host | smart-27c2cc11-81fa-47b9-b8fb-82963095dbec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035321482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1035321482 |
Directory | /workspace/41.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2172690797 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 244288941 ps |
CPU time | 1.06 seconds |
Started | May 05 12:25:50 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 217972 kb |
Host | smart-81f76d21-4f8d-42f6-8c49-6a6c305278b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172690797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2172690797 |
Directory | /workspace/41.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/41.rstmgr_por_stretcher.3546041359 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 150730522 ps |
CPU time | 0.88 seconds |
Started | May 05 12:25:48 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 200500 kb |
Host | smart-7a455d1f-67ef-4b56-b360-5bb8c27938db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546041359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3546041359 |
Directory | /workspace/41.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/41.rstmgr_reset.2261871230 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 1859842198 ps |
CPU time | 6.9 seconds |
Started | May 05 12:25:41 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 200952 kb |
Host | smart-5a118326-6432-4ae3-b490-57078ef74d93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261871230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2261871230 |
Directory | /workspace/41.rstmgr_reset/latest |
Test location | /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1283857175 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 184282258 ps |
CPU time | 1.2 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 200692 kb |
Host | smart-3f483630-8e18-41f9-8f94-ef2e3ed83dc1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283857175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1283857175 |
Directory | /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/41.rstmgr_smoke.1033884698 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 236830048 ps |
CPU time | 1.37 seconds |
Started | May 05 12:25:35 PM PDT 24 |
Finished | May 05 12:25:38 PM PDT 24 |
Peak memory | 200984 kb |
Host | smart-4518bb1f-9bae-4d80-aeaf-c34ae9302170 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033884698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1033884698 |
Directory | /workspace/41.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/41.rstmgr_stress_all.443254548 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 6179576210 ps |
CPU time | 30.02 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:26:13 PM PDT 24 |
Peak memory | 209268 kb |
Host | smart-caa5e572-cacd-4f66-a221-6f89115071c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443254548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.443254548 |
Directory | /workspace/41.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/41.rstmgr_sw_rst.3969157475 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 151690043 ps |
CPU time | 1.76 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200708 kb |
Host | smart-aa53c3dd-ff58-4686-9357-9ec9a5ccebb2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969157475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3969157475 |
Directory | /workspace/41.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2899362627 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 112241546 ps |
CPU time | 1.09 seconds |
Started | May 05 12:25:39 PM PDT 24 |
Finished | May 05 12:25:42 PM PDT 24 |
Peak memory | 200744 kb |
Host | smart-c8e68f21-a3fe-459f-a4aa-41946f6f97dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899362627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2899362627 |
Directory | /workspace/41.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/42.rstmgr_alert_test.2861599167 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 78207842 ps |
CPU time | 0.8 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-40c3aadd-c997-4d1d-b546-3072503c4f7d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861599167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2861599167 |
Directory | /workspace/42.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3363672966 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 1228086841 ps |
CPU time | 5.79 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:59 PM PDT 24 |
Peak memory | 217764 kb |
Host | smart-5f7e9117-2474-425c-8689-72719988b75f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363672966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3363672966 |
Directory | /workspace/42.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3422803413 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 244158824 ps |
CPU time | 1.16 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:46 PM PDT 24 |
Peak memory | 217876 kb |
Host | smart-f15108a2-c877-475a-a7a4-c14d623b5a6c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422803413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3422803413 |
Directory | /workspace/42.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/42.rstmgr_por_stretcher.2224225567 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 200617809 ps |
CPU time | 0.93 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 200568 kb |
Host | smart-062f9ec6-7a5c-4c66-822d-3a864293eca5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224225567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2224225567 |
Directory | /workspace/42.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/42.rstmgr_reset.722397834 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 1444135000 ps |
CPU time | 5.98 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:26:01 PM PDT 24 |
Peak memory | 200956 kb |
Host | smart-fee69e9b-db43-4a0d-b506-0dd65f938548 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722397834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.722397834 |
Directory | /workspace/42.rstmgr_reset/latest |
Test location | /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2226747735 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 170528474 ps |
CPU time | 1.18 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 200772 kb |
Host | smart-73fb0424-74ef-43b1-bbea-e5e205d85498 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226747735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2226747735 |
Directory | /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/42.rstmgr_smoke.2668887162 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 252405891 ps |
CPU time | 1.41 seconds |
Started | May 05 12:26:00 PM PDT 24 |
Finished | May 05 12:26:02 PM PDT 24 |
Peak memory | 200956 kb |
Host | smart-391d9d67-24c0-44c7-a5eb-cee12c7044a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668887162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2668887162 |
Directory | /workspace/42.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/42.rstmgr_stress_all.1612787799 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 2189960063 ps |
CPU time | 7.82 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:26:01 PM PDT 24 |
Peak memory | 200968 kb |
Host | smart-4d1f5ffb-b533-4c63-acd3-aa8b1540d1d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612787799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1612787799 |
Directory | /workspace/42.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/42.rstmgr_sw_rst.2220960715 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 117616170 ps |
CPU time | 1.44 seconds |
Started | May 05 12:25:46 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 200752 kb |
Host | smart-9e70395b-4d74-4f6d-b32e-d7b5ee5e19cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220960715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2220960715 |
Directory | /workspace/42.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3774829758 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 87540614 ps |
CPU time | 0.89 seconds |
Started | May 05 12:25:50 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 200708 kb |
Host | smart-a698b4b9-1994-46d2-a0a0-77a569c20ab5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3774829758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3774829758 |
Directory | /workspace/42.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/43.rstmgr_alert_test.3795824490 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 51480167 ps |
CPU time | 0.7 seconds |
Started | May 05 12:25:48 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-4b5422d0-62da-42bc-b92a-ed55591c3c6b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795824490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3795824490 |
Directory | /workspace/43.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1561906680 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 1882335227 ps |
CPU time | 6.7 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:26:01 PM PDT 24 |
Peak memory | 222440 kb |
Host | smart-494f7f65-1cbb-4cb6-acd4-286e7ff32de5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561906680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1561906680 |
Directory | /workspace/43.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1168059019 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 243869082 ps |
CPU time | 1.07 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 217984 kb |
Host | smart-fcf64001-0e6c-46d1-a51d-320e4819ce75 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168059019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1168059019 |
Directory | /workspace/43.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/43.rstmgr_por_stretcher.1505775414 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 201078042 ps |
CPU time | 0.88 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:25:44 PM PDT 24 |
Peak memory | 200532 kb |
Host | smart-e3baed2f-13d8-43f3-9f08-58b69112ff62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505775414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1505775414 |
Directory | /workspace/43.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/43.rstmgr_reset.1850914406 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 1695130054 ps |
CPU time | 5.95 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:59 PM PDT 24 |
Peak memory | 200968 kb |
Host | smart-db21653a-29f0-4126-bb36-6cad4ba5fdf0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850914406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1850914406 |
Directory | /workspace/43.rstmgr_reset/latest |
Test location | /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3306011343 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 161191483 ps |
CPU time | 1.11 seconds |
Started | May 05 12:25:55 PM PDT 24 |
Finished | May 05 12:25:58 PM PDT 24 |
Peak memory | 200688 kb |
Host | smart-4a19622e-4557-40c7-b824-178f44e9443a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306011343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3306011343 |
Directory | /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/43.rstmgr_smoke.451668295 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 257189822 ps |
CPU time | 1.48 seconds |
Started | May 05 12:25:36 PM PDT 24 |
Finished | May 05 12:25:38 PM PDT 24 |
Peak memory | 201012 kb |
Host | smart-1eadb5c2-f59a-43d1-82ab-57adcafbc431 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451668295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.451668295 |
Directory | /workspace/43.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/43.rstmgr_stress_all.2122599210 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 1293623632 ps |
CPU time | 4.94 seconds |
Started | May 05 12:25:40 PM PDT 24 |
Finished | May 05 12:25:47 PM PDT 24 |
Peak memory | 200900 kb |
Host | smart-f7e6b466-71ae-444e-9c3e-6c11ebde5b80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122599210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2122599210 |
Directory | /workspace/43.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/43.rstmgr_sw_rst.2664746112 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 121287687 ps |
CPU time | 1.43 seconds |
Started | May 05 12:25:46 PM PDT 24 |
Finished | May 05 12:25:49 PM PDT 24 |
Peak memory | 208904 kb |
Host | smart-f0819cd4-7d72-4a51-9dd9-2a7570bda407 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664746112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2664746112 |
Directory | /workspace/43.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3702517120 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 109444393 ps |
CPU time | 0.87 seconds |
Started | May 05 12:25:35 PM PDT 24 |
Finished | May 05 12:25:37 PM PDT 24 |
Peak memory | 200772 kb |
Host | smart-ed937e33-8177-4921-a17b-56bd8b7f4544 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3702517120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3702517120 |
Directory | /workspace/43.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/44.rstmgr_alert_test.467754438 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 67416214 ps |
CPU time | 0.84 seconds |
Started | May 05 12:25:57 PM PDT 24 |
Finished | May 05 12:25:59 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-82d2d7ac-0276-4d1a-bfaf-a78c7017ed96 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467754438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.467754438 |
Directory | /workspace/44.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.860335888 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 2172874688 ps |
CPU time | 8.23 seconds |
Started | May 05 12:25:48 PM PDT 24 |
Finished | May 05 12:25:58 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-f1a032c5-e5f6-4dff-836a-bcf02f2494c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860335888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.860335888 |
Directory | /workspace/44.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4031738040 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 248623461 ps |
CPU time | 1.05 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:25:57 PM PDT 24 |
Peak memory | 218040 kb |
Host | smart-eeab1fa6-0253-479b-a2b7-23f23d5952fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031738040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4031738040 |
Directory | /workspace/44.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/44.rstmgr_por_stretcher.12891801 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 222774206 ps |
CPU time | 0.93 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:53 PM PDT 24 |
Peak memory | 200496 kb |
Host | smart-cdd24166-6a05-4ce5-8b34-dd13bab1cad9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12891801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.12891801 |
Directory | /workspace/44.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/44.rstmgr_reset.3642530154 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 1358660082 ps |
CPU time | 6.14 seconds |
Started | May 05 12:25:41 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 200932 kb |
Host | smart-3eb2cbb7-5e74-4552-8172-a43487236d55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3642530154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3642530154 |
Directory | /workspace/44.rstmgr_reset/latest |
Test location | /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.820196531 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 105362547 ps |
CPU time | 0.98 seconds |
Started | May 05 12:26:01 PM PDT 24 |
Finished | May 05 12:26:02 PM PDT 24 |
Peak memory | 200760 kb |
Host | smart-fd54eb2a-e072-4eb0-aa96-b72456319c43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820196531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.820196531 |
Directory | /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/44.rstmgr_smoke.2510291947 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 197109705 ps |
CPU time | 1.37 seconds |
Started | May 05 12:25:58 PM PDT 24 |
Finished | May 05 12:26:01 PM PDT 24 |
Peak memory | 200908 kb |
Host | smart-97993214-84b8-4af1-8dc8-e621872ad0d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510291947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2510291947 |
Directory | /workspace/44.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/44.rstmgr_stress_all.4057303406 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 319824381 ps |
CPU time | 1.56 seconds |
Started | May 05 12:25:58 PM PDT 24 |
Finished | May 05 12:26:00 PM PDT 24 |
Peak memory | 200536 kb |
Host | smart-79753cd2-689a-49ba-97aa-020ce277138b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057303406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.4057303406 |
Directory | /workspace/44.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/44.rstmgr_sw_rst.3008626871 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 373033585 ps |
CPU time | 2.31 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-effd48cd-b5b3-4714-88b3-f7eafdb36337 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008626871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3008626871 |
Directory | /workspace/44.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3315572306 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 169150986 ps |
CPU time | 1.22 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 200820 kb |
Host | smart-742e9fea-30b6-4122-b8a2-554a98c1d906 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315572306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3315572306 |
Directory | /workspace/44.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/45.rstmgr_alert_test.2319265669 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 93107922 ps |
CPU time | 0.91 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-2f0401c3-ae44-4591-bc4e-7231c2f443ee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319265669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2319265669 |
Directory | /workspace/45.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1079007868 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 1226865114 ps |
CPU time | 5.7 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:26:01 PM PDT 24 |
Peak memory | 217796 kb |
Host | smart-583b5896-7d97-49d3-9288-27a32deb3ee3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1079007868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1079007868 |
Directory | /workspace/45.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4139783149 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 254578129 ps |
CPU time | 1.06 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:25:51 PM PDT 24 |
Peak memory | 217964 kb |
Host | smart-6d0cb8ff-b636-4f38-8f1b-c2afdfdcf9fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139783149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4139783149 |
Directory | /workspace/45.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/45.rstmgr_por_stretcher.2622235514 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 111286824 ps |
CPU time | 0.79 seconds |
Started | May 05 12:25:58 PM PDT 24 |
Finished | May 05 12:25:59 PM PDT 24 |
Peak memory | 200568 kb |
Host | smart-033c8f2e-4447-422d-9f8f-a1bae5e57471 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622235514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2622235514 |
Directory | /workspace/45.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/45.rstmgr_reset.2718204980 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 1059755474 ps |
CPU time | 5.27 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:25:48 PM PDT 24 |
Peak memory | 200948 kb |
Host | smart-6a557638-9d7e-45db-8fc3-9c10c99b8c4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2718204980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2718204980 |
Directory | /workspace/45.rstmgr_reset/latest |
Test location | /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3756664596 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 106815956 ps |
CPU time | 0.96 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200652 kb |
Host | smart-02e318d8-b2b7-4e1e-b622-142352f4b2b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756664596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3756664596 |
Directory | /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/45.rstmgr_smoke.1706421654 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 201700952 ps |
CPU time | 1.32 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 200988 kb |
Host | smart-27b555c3-7ef1-46d5-91dc-c77b070e8007 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706421654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1706421654 |
Directory | /workspace/45.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/45.rstmgr_stress_all.1655421418 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 16647697226 ps |
CPU time | 51.96 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:26:46 PM PDT 24 |
Peak memory | 209340 kb |
Host | smart-7d4cb5cf-e0c0-44bd-a1ea-40c78e1617db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655421418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1655421418 |
Directory | /workspace/45.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/45.rstmgr_sw_rst.926533427 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 409151466 ps |
CPU time | 2.18 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 208872 kb |
Host | smart-daa741a7-a61f-4756-87d4-34837413c31e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926533427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.926533427 |
Directory | /workspace/45.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.421617218 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 144694212 ps |
CPU time | 1.12 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:25:57 PM PDT 24 |
Peak memory | 200724 kb |
Host | smart-d0a1999e-e50a-41c0-8810-5f5f99e22d5c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421617218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.421617218 |
Directory | /workspace/45.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/46.rstmgr_alert_test.2900133343 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 69527252 ps |
CPU time | 0.77 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:25:57 PM PDT 24 |
Peak memory | 200600 kb |
Host | smart-9b7e101f-8519-439f-be44-4324e0b8d639 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900133343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2900133343 |
Directory | /workspace/46.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2491328739 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 1221924075 ps |
CPU time | 5.6 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:26:01 PM PDT 24 |
Peak memory | 222448 kb |
Host | smart-b7fafd1b-76da-4a15-811d-e2fc68c545fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491328739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2491328739 |
Directory | /workspace/46.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2895922590 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 246371271 ps |
CPU time | 1.12 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 217920 kb |
Host | smart-ffd6fea9-c11c-4920-b3d3-522a13d8f5ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895922590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2895922590 |
Directory | /workspace/46.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/46.rstmgr_por_stretcher.1520833522 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 183538587 ps |
CPU time | 0.88 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:25:57 PM PDT 24 |
Peak memory | 200500 kb |
Host | smart-5bfdbb41-6d13-402c-8093-aff4545feb90 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1520833522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1520833522 |
Directory | /workspace/46.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/46.rstmgr_reset.4276757986 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 1053499079 ps |
CPU time | 5.68 seconds |
Started | May 05 12:26:10 PM PDT 24 |
Finished | May 05 12:26:16 PM PDT 24 |
Peak memory | 200984 kb |
Host | smart-809d291c-c05b-45ad-b65d-d150c29f027f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276757986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.4276757986 |
Directory | /workspace/46.rstmgr_reset/latest |
Test location | /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2569423385 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 106068294 ps |
CPU time | 1.01 seconds |
Started | May 05 12:25:50 PM PDT 24 |
Finished | May 05 12:25:52 PM PDT 24 |
Peak memory | 200704 kb |
Host | smart-6b718ba8-a842-4451-977e-6f700e8bd4f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569423385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2569423385 |
Directory | /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/46.rstmgr_smoke.652302084 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 196496854 ps |
CPU time | 1.41 seconds |
Started | May 05 12:25:47 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 200968 kb |
Host | smart-baea8d35-20ac-4e98-bc29-4e285a83a17e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=652302084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.652302084 |
Directory | /workspace/46.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/46.rstmgr_stress_all.4044762606 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 5537952500 ps |
CPU time | 24.35 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:26:17 PM PDT 24 |
Peak memory | 201028 kb |
Host | smart-2fa0e1c6-05ed-416a-8711-2434ae042a7f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044762606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4044762606 |
Directory | /workspace/46.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/46.rstmgr_sw_rst.3266120933 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 489372816 ps |
CPU time | 2.51 seconds |
Started | May 05 12:26:01 PM PDT 24 |
Finished | May 05 12:26:04 PM PDT 24 |
Peak memory | 200664 kb |
Host | smart-fc5e8f91-fcf0-4c1d-91a4-2f25deb879a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266120933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3266120933 |
Directory | /workspace/46.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2882149876 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 122910837 ps |
CPU time | 1.04 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200684 kb |
Host | smart-1006aacb-0ed6-4336-ba97-ff0710bea4d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882149876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2882149876 |
Directory | /workspace/46.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/47.rstmgr_alert_test.1932468129 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 65400206 ps |
CPU time | 0.74 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 200520 kb |
Host | smart-7343f34a-feb5-4920-8573-c446e067e800 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932468129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1932468129 |
Directory | /workspace/47.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.309481068 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 1221576181 ps |
CPU time | 5.34 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:26:00 PM PDT 24 |
Peak memory | 218308 kb |
Host | smart-c79020cb-8ee8-4553-98cd-bbee01180cd0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309481068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.309481068 |
Directory | /workspace/47.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3422939151 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 244320902 ps |
CPU time | 1.14 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 217932 kb |
Host | smart-53ccb5df-a6ac-4e92-8c2e-f263698f16ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422939151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3422939151 |
Directory | /workspace/47.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/47.rstmgr_por_stretcher.161449610 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 142656163 ps |
CPU time | 0.86 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 200520 kb |
Host | smart-23792e3c-0934-4025-9937-57c060ea7ac4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161449610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.161449610 |
Directory | /workspace/47.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/47.rstmgr_reset.114913571 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 1269499687 ps |
CPU time | 5.12 seconds |
Started | May 05 12:25:55 PM PDT 24 |
Finished | May 05 12:26:02 PM PDT 24 |
Peak memory | 200976 kb |
Host | smart-f77da253-b81d-455c-908d-7f41b219e3c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114913571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.114913571 |
Directory | /workspace/47.rstmgr_reset/latest |
Test location | /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3283271808 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 180786402 ps |
CPU time | 1.3 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:25:55 PM PDT 24 |
Peak memory | 200728 kb |
Host | smart-71ce7f28-bcb2-4100-8db3-fd1b89c4b563 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283271808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3283271808 |
Directory | /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/47.rstmgr_smoke.2125771936 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 237774631 ps |
CPU time | 1.56 seconds |
Started | May 05 12:26:02 PM PDT 24 |
Finished | May 05 12:26:04 PM PDT 24 |
Peak memory | 200988 kb |
Host | smart-c56d241d-3a1b-43ef-9693-2dbd5df8fd09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125771936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2125771936 |
Directory | /workspace/47.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/47.rstmgr_stress_all.605758020 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 4417766115 ps |
CPU time | 15.09 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:26:09 PM PDT 24 |
Peak memory | 209280 kb |
Host | smart-0047ecfd-4677-4107-9af9-eddcc68d92d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605758020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.605758020 |
Directory | /workspace/47.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/47.rstmgr_sw_rst.594670772 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 147439209 ps |
CPU time | 1.84 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:46 PM PDT 24 |
Peak memory | 200684 kb |
Host | smart-c20790ec-3746-402b-88b9-8c58145ac123 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594670772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.594670772 |
Directory | /workspace/47.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2945521780 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 118651949 ps |
CPU time | 0.98 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:25:51 PM PDT 24 |
Peak memory | 200736 kb |
Host | smart-0fe05996-a3ee-474c-ae3e-dfee5c71304c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945521780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2945521780 |
Directory | /workspace/47.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/48.rstmgr_alert_test.2964611207 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 62870008 ps |
CPU time | 0.77 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200544 kb |
Host | smart-65077c2e-efa8-49dc-8590-df19ab94618f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964611207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2964611207 |
Directory | /workspace/48.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.92831665 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2184969140 ps |
CPU time | 7.4 seconds |
Started | May 05 12:25:52 PM PDT 24 |
Finished | May 05 12:26:01 PM PDT 24 |
Peak memory | 218464 kb |
Host | smart-fea1339c-e049-41dd-b8d9-3499fdcfb1b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92831665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.92831665 |
Directory | /workspace/48.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3065439298 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 243738102 ps |
CPU time | 1.17 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 217904 kb |
Host | smart-47d5c27e-d365-462f-955c-d40708e0c1f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3065439298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3065439298 |
Directory | /workspace/48.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/48.rstmgr_por_stretcher.3061522524 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 132747517 ps |
CPU time | 0.84 seconds |
Started | May 05 12:25:51 PM PDT 24 |
Finished | May 05 12:25:54 PM PDT 24 |
Peak memory | 200620 kb |
Host | smart-153aaccc-6500-4cae-a920-ab1ccef2004c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3061522524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3061522524 |
Directory | /workspace/48.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/48.rstmgr_reset.4281225773 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 1586869112 ps |
CPU time | 5.87 seconds |
Started | May 05 12:25:58 PM PDT 24 |
Finished | May 05 12:26:05 PM PDT 24 |
Peak memory | 200972 kb |
Host | smart-39561166-b135-4309-a25f-456905ba5199 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281225773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4281225773 |
Directory | /workspace/48.rstmgr_reset/latest |
Test location | /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.741916097 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 106868998 ps |
CPU time | 1.04 seconds |
Started | May 05 12:25:55 PM PDT 24 |
Finished | May 05 12:25:57 PM PDT 24 |
Peak memory | 200808 kb |
Host | smart-1eb6ee87-d28b-4c50-b624-f7b2bfea96f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=741916097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.741916097 |
Directory | /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/48.rstmgr_smoke.3499829472 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 202080437 ps |
CPU time | 1.32 seconds |
Started | May 05 12:25:47 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 200920 kb |
Host | smart-fe6a0750-94da-414e-8623-bf662cbb91fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499829472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3499829472 |
Directory | /workspace/48.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/48.rstmgr_stress_all.868372147 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 4308111941 ps |
CPU time | 14.94 seconds |
Started | May 05 12:25:47 PM PDT 24 |
Finished | May 05 12:26:03 PM PDT 24 |
Peak memory | 210724 kb |
Host | smart-a3ff0fb0-8395-44aa-8956-aba71562c16e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868372147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.868372147 |
Directory | /workspace/48.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/48.rstmgr_sw_rst.2122189998 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 281497809 ps |
CPU time | 1.82 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:25:58 PM PDT 24 |
Peak memory | 200808 kb |
Host | smart-9d588a8c-7f81-448c-abce-ee96fbf68281 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122189998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2122189998 |
Directory | /workspace/48.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3424075382 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 120366399 ps |
CPU time | 1.02 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:25:57 PM PDT 24 |
Peak memory | 200728 kb |
Host | smart-496861b8-ddc2-479b-96ef-048c7ca67e58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424075382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3424075382 |
Directory | /workspace/48.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/49.rstmgr_alert_test.349892472 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 75607062 ps |
CPU time | 0.79 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200608 kb |
Host | smart-fa566b88-89b0-4cf3-b399-25feab777e0d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349892472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.349892472 |
Directory | /workspace/49.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.480404651 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 1219326088 ps |
CPU time | 5.46 seconds |
Started | May 05 12:25:54 PM PDT 24 |
Finished | May 05 12:26:02 PM PDT 24 |
Peak memory | 217352 kb |
Host | smart-cff68295-bc13-47a3-8835-bbcefa4d77e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480404651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.480404651 |
Directory | /workspace/49.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2056344377 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 244655125 ps |
CPU time | 1.04 seconds |
Started | May 05 12:25:43 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 218032 kb |
Host | smart-0ee1c4e4-bf0a-4bba-a999-43521d7499d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056344377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2056344377 |
Directory | /workspace/49.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/49.rstmgr_por_stretcher.110441994 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 128078836 ps |
CPU time | 0.84 seconds |
Started | May 05 12:25:53 PM PDT 24 |
Finished | May 05 12:25:56 PM PDT 24 |
Peak memory | 200564 kb |
Host | smart-b9fbdebc-2e0c-42cf-bc6b-1072d442aa99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110441994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.110441994 |
Directory | /workspace/49.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/49.rstmgr_reset.2945728521 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 682285007 ps |
CPU time | 3.7 seconds |
Started | May 05 12:25:57 PM PDT 24 |
Finished | May 05 12:26:01 PM PDT 24 |
Peak memory | 201236 kb |
Host | smart-b45c7c58-2850-44f3-aced-056aff133489 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945728521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2945728521 |
Directory | /workspace/49.rstmgr_reset/latest |
Test location | /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.451993640 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 112116001 ps |
CPU time | 1.07 seconds |
Started | May 05 12:25:48 PM PDT 24 |
Finished | May 05 12:25:50 PM PDT 24 |
Peak memory | 200804 kb |
Host | smart-9c8641e5-b8fa-4800-8d15-397e27bc7a87 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451993640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.451993640 |
Directory | /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/49.rstmgr_smoke.1235103049 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 182999174 ps |
CPU time | 1.45 seconds |
Started | May 05 12:25:42 PM PDT 24 |
Finished | May 05 12:25:45 PM PDT 24 |
Peak memory | 200940 kb |
Host | smart-e0642f9f-4d48-4193-bdc4-9e91444fcecb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235103049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1235103049 |
Directory | /workspace/49.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/49.rstmgr_stress_all.598962904 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 7170845978 ps |
CPU time | 29.26 seconds |
Started | May 05 12:25:49 PM PDT 24 |
Finished | May 05 12:26:20 PM PDT 24 |
Peak memory | 201156 kb |
Host | smart-3f7e30a7-98d3-4298-be67-5f0a3e66c306 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598962904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.598962904 |
Directory | /workspace/49.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/49.rstmgr_sw_rst.1888847131 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 127444784 ps |
CPU time | 1.58 seconds |
Started | May 05 12:25:50 PM PDT 24 |
Finished | May 05 12:25:53 PM PDT 24 |
Peak memory | 200804 kb |
Host | smart-fe744e7a-399e-4a7c-8202-58201d6c769c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888847131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1888847131 |
Directory | /workspace/49.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1591109281 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 284121984 ps |
CPU time | 1.56 seconds |
Started | May 05 12:25:48 PM PDT 24 |
Finished | May 05 12:25:51 PM PDT 24 |
Peak memory | 200948 kb |
Host | smart-5da16fb5-2dc5-47c4-ad7b-5cc80e9ea936 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591109281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1591109281 |
Directory | /workspace/49.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/5.rstmgr_alert_test.4044225099 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 64276713 ps |
CPU time | 0.75 seconds |
Started | May 05 12:24:51 PM PDT 24 |
Finished | May 05 12:24:55 PM PDT 24 |
Peak memory | 200428 kb |
Host | smart-c4ca8b73-d1e0-4b1f-947d-54ab5add697b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044225099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4044225099 |
Directory | /workspace/5.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2718131147 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 1884760720 ps |
CPU time | 6.6 seconds |
Started | May 05 12:24:58 PM PDT 24 |
Finished | May 05 12:25:06 PM PDT 24 |
Peak memory | 222324 kb |
Host | smart-e38062ca-eceb-4037-935f-91585dcdfc14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2718131147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2718131147 |
Directory | /workspace/5.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.653780495 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 244111933 ps |
CPU time | 1.07 seconds |
Started | May 05 12:25:09 PM PDT 24 |
Finished | May 05 12:25:12 PM PDT 24 |
Peak memory | 217788 kb |
Host | smart-7b8ccbbd-158e-43ed-9ec1-a3c8fbeb0355 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653780495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.653780495 |
Directory | /workspace/5.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/5.rstmgr_por_stretcher.3020081907 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 216070522 ps |
CPU time | 0.9 seconds |
Started | May 05 12:24:53 PM PDT 24 |
Finished | May 05 12:24:57 PM PDT 24 |
Peak memory | 200512 kb |
Host | smart-adb4afd2-135c-4baa-b27d-8b992d2a1ecf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020081907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3020081907 |
Directory | /workspace/5.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/5.rstmgr_reset.4022498435 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 2114627672 ps |
CPU time | 7.33 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:24:59 PM PDT 24 |
Peak memory | 200852 kb |
Host | smart-2cedd4ff-0e9c-410e-8c5c-90904fdc5c81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4022498435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4022498435 |
Directory | /workspace/5.rstmgr_reset/latest |
Test location | /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3254370243 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 157443807 ps |
CPU time | 1.1 seconds |
Started | May 05 12:25:00 PM PDT 24 |
Finished | May 05 12:25:02 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-65854fb8-a93a-401e-8522-3b08307c6413 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3254370243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3254370243 |
Directory | /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/5.rstmgr_smoke.3707661656 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 194316624 ps |
CPU time | 1.4 seconds |
Started | May 05 12:24:47 PM PDT 24 |
Finished | May 05 12:24:50 PM PDT 24 |
Peak memory | 200992 kb |
Host | smart-2628eb79-3c1f-4294-9352-08d7bd699b20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707661656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3707661656 |
Directory | /workspace/5.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/5.rstmgr_stress_all.934574590 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 12256548907 ps |
CPU time | 42.14 seconds |
Started | May 05 12:24:48 PM PDT 24 |
Finished | May 05 12:25:32 PM PDT 24 |
Peak memory | 209208 kb |
Host | smart-d77422f3-4f8a-4759-b177-58fd4cad03ea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934574590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.934574590 |
Directory | /workspace/5.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/5.rstmgr_sw_rst.4038367114 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 137291592 ps |
CPU time | 1.77 seconds |
Started | May 05 12:25:00 PM PDT 24 |
Finished | May 05 12:25:03 PM PDT 24 |
Peak memory | 200660 kb |
Host | smart-76b5f082-c4c0-4bc3-8a35-f70afad8c3e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038367114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.4038367114 |
Directory | /workspace/5.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.102545973 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 122161330 ps |
CPU time | 1.08 seconds |
Started | May 05 12:24:51 PM PDT 24 |
Finished | May 05 12:24:55 PM PDT 24 |
Peak memory | 200740 kb |
Host | smart-c76d3255-c544-4f3d-aa0f-89855abc0793 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102545973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.102545973 |
Directory | /workspace/5.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/6.rstmgr_alert_test.3995265219 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 71364088 ps |
CPU time | 0.79 seconds |
Started | May 05 12:25:05 PM PDT 24 |
Finished | May 05 12:25:07 PM PDT 24 |
Peak memory | 200544 kb |
Host | smart-ad674018-e35c-4a74-9511-b2fd60664ec5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995265219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3995265219 |
Directory | /workspace/6.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2131171450 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 2359426358 ps |
CPU time | 8.93 seconds |
Started | May 05 12:24:50 PM PDT 24 |
Finished | May 05 12:25:02 PM PDT 24 |
Peak memory | 222576 kb |
Host | smart-8503bfc5-f416-4702-bf23-4a1fb58693bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131171450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2131171450 |
Directory | /workspace/6.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.105421294 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 245275792 ps |
CPU time | 1.13 seconds |
Started | May 05 12:24:56 PM PDT 24 |
Finished | May 05 12:25:02 PM PDT 24 |
Peak memory | 217956 kb |
Host | smart-88b55188-5dc0-4874-9b69-97e59c2620a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105421294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.105421294 |
Directory | /workspace/6.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/6.rstmgr_por_stretcher.2346735617 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 205690071 ps |
CPU time | 0.98 seconds |
Started | May 05 12:24:48 PM PDT 24 |
Finished | May 05 12:24:51 PM PDT 24 |
Peak memory | 200488 kb |
Host | smart-4719e5b4-be86-4e16-89bc-76d96cd2d361 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346735617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2346735617 |
Directory | /workspace/6.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/6.rstmgr_reset.2340475349 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 836419004 ps |
CPU time | 4.26 seconds |
Started | May 05 12:24:57 PM PDT 24 |
Finished | May 05 12:25:03 PM PDT 24 |
Peak memory | 200876 kb |
Host | smart-ac14c670-a37e-4d2b-916a-50e840bb37c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340475349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2340475349 |
Directory | /workspace/6.rstmgr_reset/latest |
Test location | /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1158360545 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 172153912 ps |
CPU time | 1.18 seconds |
Started | May 05 12:24:59 PM PDT 24 |
Finished | May 05 12:25:01 PM PDT 24 |
Peak memory | 200676 kb |
Host | smart-9ce3057f-b94a-4a30-b4e1-b9f818bad451 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1158360545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1158360545 |
Directory | /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/6.rstmgr_smoke.1908932800 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 117455222 ps |
CPU time | 1.16 seconds |
Started | May 05 12:24:57 PM PDT 24 |
Finished | May 05 12:25:00 PM PDT 24 |
Peak memory | 200876 kb |
Host | smart-da7febc1-d247-4dc8-9e18-8c5d726ceaf0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908932800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1908932800 |
Directory | /workspace/6.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/6.rstmgr_stress_all.3800061402 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 682578652 ps |
CPU time | 2.74 seconds |
Started | May 05 12:24:50 PM PDT 24 |
Finished | May 05 12:24:56 PM PDT 24 |
Peak memory | 200864 kb |
Host | smart-8b271206-6f26-488a-9b98-8fc68ff21b7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800061402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3800061402 |
Directory | /workspace/6.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/6.rstmgr_sw_rst.2466129776 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 156115666 ps |
CPU time | 1.85 seconds |
Started | May 05 12:24:50 PM PDT 24 |
Finished | May 05 12:24:55 PM PDT 24 |
Peak memory | 200648 kb |
Host | smart-485fc61e-26fb-4f70-986b-5e483fddf2af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466129776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2466129776 |
Directory | /workspace/6.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3340578651 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 80607706 ps |
CPU time | 0.83 seconds |
Started | May 05 12:24:57 PM PDT 24 |
Finished | May 05 12:25:00 PM PDT 24 |
Peak memory | 200704 kb |
Host | smart-480c7567-8b02-40e6-b5cf-faab6118b97f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340578651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3340578651 |
Directory | /workspace/6.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/7.rstmgr_alert_test.2682341621 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 66741413 ps |
CPU time | 0.77 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:24:53 PM PDT 24 |
Peak memory | 200552 kb |
Host | smart-1acba0f3-d69d-4910-bc42-a0f34ff47f64 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682341621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2682341621 |
Directory | /workspace/7.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.339000557 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 1231466551 ps |
CPU time | 5.19 seconds |
Started | May 05 12:24:59 PM PDT 24 |
Finished | May 05 12:25:06 PM PDT 24 |
Peak memory | 217340 kb |
Host | smart-a49846a5-e578-4129-aa08-e393ce351c64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339000557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.339000557 |
Directory | /workspace/7.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.481911355 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 244862272 ps |
CPU time | 1.16 seconds |
Started | May 05 12:25:02 PM PDT 24 |
Finished | May 05 12:25:05 PM PDT 24 |
Peak memory | 218064 kb |
Host | smart-b3bd256c-61fb-47fc-88c1-1524146cf0e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481911355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.481911355 |
Directory | /workspace/7.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/7.rstmgr_por_stretcher.2051590606 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 180451108 ps |
CPU time | 0.94 seconds |
Started | May 05 12:25:08 PM PDT 24 |
Finished | May 05 12:25:11 PM PDT 24 |
Peak memory | 200556 kb |
Host | smart-f427b817-4696-4d5c-a60d-a3ea9341b644 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051590606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2051590606 |
Directory | /workspace/7.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/7.rstmgr_reset.3148320325 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 834001060 ps |
CPU time | 4.17 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 200860 kb |
Host | smart-28ce9b5e-f727-4d2b-8112-940355ad8734 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148320325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3148320325 |
Directory | /workspace/7.rstmgr_reset/latest |
Test location | /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1805779121 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 105273945 ps |
CPU time | 0.97 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:24:51 PM PDT 24 |
Peak memory | 200720 kb |
Host | smart-d88abf6c-453f-4b72-8a39-0ff32c4a0552 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805779121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1805779121 |
Directory | /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/7.rstmgr_smoke.109852004 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 122021833 ps |
CPU time | 1.19 seconds |
Started | May 05 12:24:55 PM PDT 24 |
Finished | May 05 12:24:58 PM PDT 24 |
Peak memory | 200872 kb |
Host | smart-51fb7ff5-0dc2-4eb0-af09-c2a812d779a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109852004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.109852004 |
Directory | /workspace/7.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/7.rstmgr_stress_all.250035582 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 2738796912 ps |
CPU time | 9.71 seconds |
Started | May 05 12:25:08 PM PDT 24 |
Finished | May 05 12:25:20 PM PDT 24 |
Peak memory | 209372 kb |
Host | smart-4854ffb7-bd87-4658-aa57-6e06392c4b98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250035582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.250035582 |
Directory | /workspace/7.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/7.rstmgr_sw_rst.4084914153 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 148122361 ps |
CPU time | 1.84 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:07 PM PDT 24 |
Peak memory | 200692 kb |
Host | smart-63194931-5e73-48b7-b469-4ea623bef08a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084914153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.4084914153 |
Directory | /workspace/7.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3739796438 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 74065325 ps |
CPU time | 0.78 seconds |
Started | May 05 12:25:07 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 200744 kb |
Host | smart-6d8dacf5-8466-456d-b028-d750f0967515 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739796438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3739796438 |
Directory | /workspace/7.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/8.rstmgr_alert_test.720409424 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 71913871 ps |
CPU time | 0.76 seconds |
Started | May 05 12:25:10 PM PDT 24 |
Finished | May 05 12:25:12 PM PDT 24 |
Peak memory | 200480 kb |
Host | smart-b2f9f90e-567e-4a6a-83c2-ea79859f5f95 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720409424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.720409424 |
Directory | /workspace/8.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1835289744 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 2361667678 ps |
CPU time | 8.88 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:25:01 PM PDT 24 |
Peak memory | 218788 kb |
Host | smart-349ea8f6-6e3a-4cd9-aefc-45fbf9a81beb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835289744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1835289744 |
Directory | /workspace/8.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2809903627 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 244190953 ps |
CPU time | 1.07 seconds |
Started | May 05 12:24:55 PM PDT 24 |
Finished | May 05 12:24:59 PM PDT 24 |
Peak memory | 217960 kb |
Host | smart-87b4bd28-ef6f-4e3d-8701-ecbc15e2cd24 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809903627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2809903627 |
Directory | /workspace/8.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/8.rstmgr_por_stretcher.483293179 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 148406028 ps |
CPU time | 0.82 seconds |
Started | May 05 12:25:06 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 200540 kb |
Host | smart-9e2a0a72-cd2e-451b-9fce-199233ab9810 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=483293179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.483293179 |
Directory | /workspace/8.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/8.rstmgr_reset.938022650 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 766335353 ps |
CPU time | 3.65 seconds |
Started | May 05 12:24:51 PM PDT 24 |
Finished | May 05 12:24:58 PM PDT 24 |
Peak memory | 200860 kb |
Host | smart-f2aea5bc-f1f1-462d-96fa-975173ebf943 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938022650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.938022650 |
Directory | /workspace/8.rstmgr_reset/latest |
Test location | /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2275480003 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 178983190 ps |
CPU time | 1.21 seconds |
Started | May 05 12:24:59 PM PDT 24 |
Finished | May 05 12:25:02 PM PDT 24 |
Peak memory | 200656 kb |
Host | smart-c6bb7b8a-bd0a-46b2-acf6-67e43e3caf05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275480003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2275480003 |
Directory | /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/8.rstmgr_smoke.3446252697 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 184985701 ps |
CPU time | 1.28 seconds |
Started | May 05 12:25:01 PM PDT 24 |
Finished | May 05 12:25:04 PM PDT 24 |
Peak memory | 200920 kb |
Host | smart-6be3cf20-aad1-494a-919d-dded258856d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446252697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3446252697 |
Directory | /workspace/8.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/8.rstmgr_stress_all.2221825032 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 8052395597 ps |
CPU time | 24.24 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:29 PM PDT 24 |
Peak memory | 209208 kb |
Host | smart-4ec671c4-0eb9-40eb-b90e-816b0fea0ded |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221825032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2221825032 |
Directory | /workspace/8.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/8.rstmgr_sw_rst.1141339374 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 118989729 ps |
CPU time | 1.54 seconds |
Started | May 05 12:24:49 PM PDT 24 |
Finished | May 05 12:24:54 PM PDT 24 |
Peak memory | 200844 kb |
Host | smart-ee4df550-f3b1-4b13-8c2f-48eb040b45ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141339374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1141339374 |
Directory | /workspace/8.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2184421647 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 173740347 ps |
CPU time | 1.28 seconds |
Started | May 05 12:24:58 PM PDT 24 |
Finished | May 05 12:25:02 PM PDT 24 |
Peak memory | 200888 kb |
Host | smart-00a3171b-160c-4167-ab11-c5f95dd4b1f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2184421647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2184421647 |
Directory | /workspace/8.rstmgr_sw_rst_reset_race/latest |
Test location | /workspace/coverage/default/9.rstmgr_alert_test.2254511862 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 67737910 ps |
CPU time | 0.79 seconds |
Started | May 05 12:25:17 PM PDT 24 |
Finished | May 05 12:25:19 PM PDT 24 |
Peak memory | 200560 kb |
Host | smart-c3591c3f-830a-4b1c-a62a-a106d1c481ba |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254511862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2254511862 |
Directory | /workspace/9.rstmgr_alert_test/latest |
Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2641225934 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 1225618274 ps |
CPU time | 5.94 seconds |
Started | May 05 12:25:07 PM PDT 24 |
Finished | May 05 12:25:15 PM PDT 24 |
Peak memory | 217324 kb |
Host | smart-d235481c-462a-40f8-a702-58300a9ade43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641225934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2641225934 |
Directory | /workspace/9.rstmgr_leaf_rst_cnsty/latest |
Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3761814387 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 243913621 ps |
CPU time | 1.07 seconds |
Started | May 05 12:24:51 PM PDT 24 |
Finished | May 05 12:24:55 PM PDT 24 |
Peak memory | 217796 kb |
Host | smart-21d68a9a-91ac-4d88-8765-dd071d60e503 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761814387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3761814387 |
Directory | /workspace/9.rstmgr_leaf_rst_shadow_attack/latest |
Test location | /workspace/coverage/default/9.rstmgr_por_stretcher.3904873398 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 73820700 ps |
CPU time | 0.74 seconds |
Started | May 05 12:25:03 PM PDT 24 |
Finished | May 05 12:25:05 PM PDT 24 |
Peak memory | 200548 kb |
Host | smart-fc4c30c0-ffab-40e8-aa00-a6ee1f165dd9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904873398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3904873398 |
Directory | /workspace/9.rstmgr_por_stretcher/latest |
Test location | /workspace/coverage/default/9.rstmgr_reset.2596557232 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 1066494166 ps |
CPU time | 4.68 seconds |
Started | May 05 12:24:54 PM PDT 24 |
Finished | May 05 12:25:01 PM PDT 24 |
Peak memory | 200852 kb |
Host | smart-9ac7d98e-54d0-4612-b874-982639b1b065 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596557232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2596557232 |
Directory | /workspace/9.rstmgr_reset/latest |
Test location | /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.540620390 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 171032727 ps |
CPU time | 1.28 seconds |
Started | May 05 12:25:13 PM PDT 24 |
Finished | May 05 12:25:16 PM PDT 24 |
Peak memory | 200748 kb |
Host | smart-5a742c52-92ef-4acb-a52b-c4592343854e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540620390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.540620390 |
Directory | /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
Test location | /workspace/coverage/default/9.rstmgr_smoke.2204922376 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 249284250 ps |
CPU time | 1.48 seconds |
Started | May 05 12:25:05 PM PDT 24 |
Finished | May 05 12:25:09 PM PDT 24 |
Peak memory | 200952 kb |
Host | smart-846143f7-bfd4-40f3-b336-ace5c8c2790f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204922376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2204922376 |
Directory | /workspace/9.rstmgr_smoke/latest |
Test location | /workspace/coverage/default/9.rstmgr_stress_all.3111063214 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 1975136317 ps |
CPU time | 8.14 seconds |
Started | May 05 12:24:55 PM PDT 24 |
Finished | May 05 12:25:05 PM PDT 24 |
Peak memory | 200872 kb |
Host | smart-e1338e21-54e6-47cd-9513-187d1a8dbc8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111063214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3111063214 |
Directory | /workspace/9.rstmgr_stress_all/latest |
Test location | /workspace/coverage/default/9.rstmgr_sw_rst.206663151 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 353943697 ps |
CPU time | 2.06 seconds |
Started | May 05 12:25:10 PM PDT 24 |
Finished | May 05 12:25:13 PM PDT 24 |
Peak memory | 200696 kb |
Host | smart-d2a11aeb-d1f9-47bd-bb64-1b4446ff223e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206663151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.206663151 |
Directory | /workspace/9.rstmgr_sw_rst/latest |
Test location | /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2207466231 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 163077737 ps |
CPU time | 1.08 seconds |
Started | May 05 12:24:48 PM PDT 24 |
Finished | May 05 12:24:50 PM PDT 24 |
Peak memory | 200808 kb |
Host | smart-4cb3021b-cfd5-4009-a628-6a5e4350e017 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207466231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2207466231 |
Directory | /workspace/9.rstmgr_sw_rst_reset_race/latest |
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