Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9141

1

T1

12

T2

18

T3

20

auto[1]

11657

1

T1

1

T2

83

T3

81

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6380	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6968	1			T1	1		T2	27		T3	27
reset_info_cp[2]	3185	1			T2	15		T3	15		T8	8
reset_info_cp[4]	4295	1			T2	18		T3	16		T8	11
reset_info_cp[8]	100	1			T4	1		T6	1		T9	3
reset_info_cp[16]	103	1			T1	2		T81	1		T77	1
reset_info_cp[32]	124	1			T4	1		T8	1		T10	2
reset_info_cp[64]	142	1			T1	1		T6	1		T13	2
reset_info_cp[128]	121	1			T3	1		T6	1		T9	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3439	1			T2	18		T3	20		T8	10
reset_info_cp[1]	auto[1]	2909	1			T2	8		T3	6		T8	11
reset_info_cp[2]	auto[0]	1046	1			T8	2		T77	22		T79	6
reset_info_cp[2]	auto[1]	2139	1			T2	15		T3	15		T8	6
reset_info_cp[4]	auto[0]	1594	1			T8	5		T77	32		T79	7
reset_info_cp[4]	auto[1]	2701	1			T2	18		T3	16		T8	6
reset_info_cp[8]	auto[0]	38	1			T6	1		T32	1		T138	1
reset_info_cp[8]	auto[1]	62	1			T4	1		T9	3		T13	1
reset_info_cp[16]	auto[0]	48	1			T1	2		T81	1		T77	1
reset_info_cp[16]	auto[1]	55	1			T42	1		T44	1		T49	1
reset_info_cp[32]	auto[0]	53	1			T4	1		T8	1		T10	2
reset_info_cp[32]	auto[1]	71	1			T35	2		T84	1		T49	1
reset_info_cp[64]	auto[0]	58	1			T6	1		T32	1		T98	1
reset_info_cp[64]	auto[1]	84	1			T1	1		T13	2		T48	1
reset_info_cp[128]	auto[0]	48	1			T77	2		T83	1		T86	3
reset_info_cp[128]	auto[1]	73	1			T3	1		T6	1		T9	2