Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T541 /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3760126426 May 07 12:36:09 PM PDT 24 May 07 12:36:13 PM PDT 24 106411626 ps
T542 /workspace/coverage/default/39.rstmgr_alert_test.3133916806 May 07 12:36:05 PM PDT 24 May 07 12:36:07 PM PDT 24 65607201 ps
T543 /workspace/coverage/default/10.rstmgr_alert_test.331628827 May 07 12:35:30 PM PDT 24 May 07 12:35:36 PM PDT 24 71190324 ps
T544 /workspace/coverage/default/5.rstmgr_reset.4131442321 May 07 12:35:27 PM PDT 24 May 07 12:35:35 PM PDT 24 1215833413 ps
T545 /workspace/coverage/default/38.rstmgr_por_stretcher.4164299894 May 07 12:36:03 PM PDT 24 May 07 12:36:05 PM PDT 24 159651324 ps
T53 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.523512456 May 07 12:35:12 PM PDT 24 May 07 12:35:15 PM PDT 24 75814031 ps
T54 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1470845705 May 07 12:34:58 PM PDT 24 May 07 12:35:01 PM PDT 24 79457337 ps
T55 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1164196557 May 07 12:35:12 PM PDT 24 May 07 12:35:15 PM PDT 24 64116924 ps
T56 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1493289505 May 07 12:35:06 PM PDT 24 May 07 12:35:08 PM PDT 24 77778414 ps
T57 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2143702062 May 07 12:35:19 PM PDT 24 May 07 12:35:23 PM PDT 24 138982506 ps
T58 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.870338634 May 07 12:35:19 PM PDT 24 May 07 12:35:23 PM PDT 24 472992714 ps
T59 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2780933398 May 07 12:35:05 PM PDT 24 May 07 12:35:10 PM PDT 24 116658482 ps
T546 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2668196269 May 07 12:34:46 PM PDT 24 May 07 12:34:50 PM PDT 24 73240435 ps
T60 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3080686912 May 07 12:35:08 PM PDT 24 May 07 12:35:13 PM PDT 24 415070234 ps
T64 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3953680795 May 07 12:34:57 PM PDT 24 May 07 12:34:59 PM PDT 24 181026450 ps
T93 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3280219299 May 07 12:35:07 PM PDT 24 May 07 12:35:13 PM PDT 24 940376016 ps
T109 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2118248816 May 07 12:34:52 PM PDT 24 May 07 12:34:55 PM PDT 24 160993013 ps
T547 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.884785918 May 07 12:34:36 PM PDT 24 May 07 12:34:41 PM PDT 24 66523205 ps
T548 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3331991168 May 07 12:35:00 PM PDT 24 May 07 12:35:10 PM PDT 24 1563796898 ps
T87 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1458142660 May 07 12:35:08 PM PDT 24 May 07 12:35:12 PM PDT 24 464037969 ps
T549 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2644421202 May 07 12:35:04 PM PDT 24 May 07 12:35:07 PM PDT 24 82693206 ps
T88 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2924539630 May 07 12:34:58 PM PDT 24 May 07 12:35:01 PM PDT 24 117736382 ps
T110 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.323203536 May 07 12:34:43 PM PDT 24 May 07 12:34:47 PM PDT 24 59616723 ps
T550 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2784857114 May 07 12:34:38 PM PDT 24 May 07 12:34:46 PM PDT 24 784746742 ps
T94 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.482493118 May 07 12:35:19 PM PDT 24 May 07 12:35:23 PM PDT 24 458323490 ps
T89 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.900327541 May 07 12:35:01 PM PDT 24 May 07 12:35:04 PM PDT 24 191571958 ps
T111 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3978441144 May 07 12:34:58 PM PDT 24 May 07 12:35:01 PM PDT 24 209443835 ps
T112 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3828119793 May 07 12:35:07 PM PDT 24 May 07 12:35:10 PM PDT 24 68945153 ps
T90 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3479933640 May 07 12:35:07 PM PDT 24 May 07 12:35:11 PM PDT 24 228192325 ps
T91 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1900820857 May 07 12:35:19 PM PDT 24 May 07 12:35:23 PM PDT 24 159496604 ps
T92 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3992795927 May 07 12:34:57 PM PDT 24 May 07 12:35:00 PM PDT 24 493075221 ps
T95 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4270811504 May 07 12:35:15 PM PDT 24 May 07 12:35:18 PM PDT 24 115364001 ps
T113 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2877999160 May 07 12:34:45 PM PDT 24 May 07 12:34:49 PM PDT 24 128455873 ps
T96 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1521169700 May 07 12:35:03 PM PDT 24 May 07 12:35:08 PM PDT 24 333992835 ps
T121 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.997114113 May 07 12:34:44 PM PDT 24 May 07 12:34:49 PM PDT 24 128532624 ps
T551 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3516038924 May 07 12:34:57 PM PDT 24 May 07 12:35:00 PM PDT 24 205157597 ps
T126 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2838784651 May 07 12:34:42 PM PDT 24 May 07 12:34:47 PM PDT 24 181319583 ps
T124 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3541376592 May 07 12:34:56 PM PDT 24 May 07 12:35:00 PM PDT 24 788911149 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1909989814 May 07 12:35:03 PM PDT 24 May 07 12:35:06 PM PDT 24 149492967 ps
T553 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3988760734 May 07 12:34:38 PM PDT 24 May 07 12:34:44 PM PDT 24 161110044 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3625841780 May 07 12:34:51 PM PDT 24 May 07 12:34:53 PM PDT 24 147522667 ps
T114 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3174436983 May 07 12:34:59 PM PDT 24 May 07 12:35:01 PM PDT 24 71039429 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.545130578 May 07 12:35:03 PM PDT 24 May 07 12:35:07 PM PDT 24 361692250 ps
T127 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3587200532 May 07 12:34:42 PM PDT 24 May 07 12:34:47 PM PDT 24 124909276 ps
T123 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3608881707 May 07 12:35:09 PM PDT 24 May 07 12:35:11 PM PDT 24 113740372 ps
T556 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3606150585 May 07 12:35:01 PM PDT 24 May 07 12:35:04 PM PDT 24 102451037 ps
T116 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1685407339 May 07 12:35:02 PM PDT 24 May 07 12:35:05 PM PDT 24 168866067 ps
T115 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1869304472 May 07 12:34:49 PM PDT 24 May 07 12:34:52 PM PDT 24 136366085 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.577936737 May 07 12:34:43 PM PDT 24 May 07 12:34:50 PM PDT 24 201192780 ps
T558 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2240132349 May 07 12:34:53 PM PDT 24 May 07 12:34:55 PM PDT 24 60200514 ps
T559 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1787830526 May 07 12:35:09 PM PDT 24 May 07 12:35:11 PM PDT 24 76991843 ps
T560 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1054908189 May 07 12:35:10 PM PDT 24 May 07 12:35:12 PM PDT 24 100732332 ps
T561 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3023790283 May 07 12:35:13 PM PDT 24 May 07 12:35:16 PM PDT 24 84912815 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4101619857 May 07 12:34:45 PM PDT 24 May 07 12:34:49 PM PDT 24 112535078 ps
T122 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.438269545 May 07 12:35:13 PM PDT 24 May 07 12:35:18 PM PDT 24 516403266 ps
T563 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4098507247 May 07 12:34:39 PM PDT 24 May 07 12:34:43 PM PDT 24 63529702 ps
T564 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4078503418 May 07 12:35:00 PM PDT 24 May 07 12:35:02 PM PDT 24 196692118 ps
T565 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3591651719 May 07 12:34:47 PM PDT 24 May 07 12:34:53 PM PDT 24 514746613 ps
T566 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.357078022 May 07 12:35:05 PM PDT 24 May 07 12:35:08 PM PDT 24 188439929 ps
T567 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.617009849 May 07 12:35:17 PM PDT 24 May 07 12:35:19 PM PDT 24 130275840 ps
T568 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.433107358 May 07 12:35:03 PM PDT 24 May 07 12:35:06 PM PDT 24 84273957 ps
T137 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1050774305 May 07 12:35:05 PM PDT 24 May 07 12:35:09 PM PDT 24 431987420 ps
T569 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.239080171 May 07 12:34:52 PM PDT 24 May 07 12:34:55 PM PDT 24 152657385 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.148895668 May 07 12:35:01 PM PDT 24 May 07 12:35:04 PM PDT 24 137495535 ps
T136 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2172745148 May 07 12:34:54 PM PDT 24 May 07 12:34:58 PM PDT 24 785003464 ps
T571 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1103919663 May 07 12:35:16 PM PDT 24 May 07 12:35:19 PM PDT 24 230167198 ps
T572 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3385180443 May 07 12:34:39 PM PDT 24 May 07 12:34:44 PM PDT 24 136065525 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3231859367 May 07 12:34:42 PM PDT 24 May 07 12:34:47 PM PDT 24 126568438 ps
T574 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.820955048 May 07 12:35:05 PM PDT 24 May 07 12:35:10 PM PDT 24 275400499 ps
T575 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3684733809 May 07 12:34:51 PM PDT 24 May 07 12:34:53 PM PDT 24 75612605 ps
T576 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2279495991 May 07 12:35:07 PM PDT 24 May 07 12:35:12 PM PDT 24 776295123 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1702628172 May 07 12:34:38 PM PDT 24 May 07 12:34:44 PM PDT 24 462625813 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3113770135 May 07 12:34:39 PM PDT 24 May 07 12:34:46 PM PDT 24 215240872 ps
T579 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.523500466 May 07 12:34:59 PM PDT 24 May 07 12:35:03 PM PDT 24 235000035 ps
T580 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3560002582 May 07 12:35:15 PM PDT 24 May 07 12:35:18 PM PDT 24 207657303 ps
T581 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2809840779 May 07 12:35:10 PM PDT 24 May 07 12:35:12 PM PDT 24 91816240 ps
T117 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.748413688 May 07 12:34:40 PM PDT 24 May 07 12:34:47 PM PDT 24 778167983 ps
T582 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1096579812 May 07 12:35:06 PM PDT 24 May 07 12:35:08 PM PDT 24 58784164 ps
T583 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.581424496 May 07 12:34:39 PM PDT 24 May 07 12:34:44 PM PDT 24 160024001 ps
T584 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1567273255 May 07 12:34:37 PM PDT 24 May 07 12:34:43 PM PDT 24 493070976 ps
T585 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2265616978 May 07 12:35:11 PM PDT 24 May 07 12:35:14 PM PDT 24 146529955 ps
T586 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2631719481 May 07 12:35:03 PM PDT 24 May 07 12:35:06 PM PDT 24 193069710 ps
T587 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.694324994 May 07 12:34:56 PM PDT 24 May 07 12:35:01 PM PDT 24 541077418 ps
T588 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2034433923 May 07 12:34:55 PM PDT 24 May 07 12:34:57 PM PDT 24 260916173 ps
T589 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1924903751 May 07 12:35:00 PM PDT 24 May 07 12:35:03 PM PDT 24 301203322 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1695300152 May 07 12:35:07 PM PDT 24 May 07 12:35:09 PM PDT 24 102277453 ps
T125 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2151193976 May 07 12:35:18 PM PDT 24 May 07 12:35:23 PM PDT 24 930041905 ps
T591 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4019840629 May 07 12:35:20 PM PDT 24 May 07 12:35:24 PM PDT 24 466907354 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1092225342 May 07 12:34:43 PM PDT 24 May 07 12:34:47 PM PDT 24 151750031 ps
T593 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3731159717 May 07 12:35:16 PM PDT 24 May 07 12:35:18 PM PDT 24 69190837 ps
T594 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.56675680 May 07 12:35:09 PM PDT 24 May 07 12:35:13 PM PDT 24 329243830 ps
T595 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.779882078 May 07 12:35:09 PM PDT 24 May 07 12:35:15 PM PDT 24 467656805 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3658691530 May 07 12:35:06 PM PDT 24 May 07 12:35:08 PM PDT 24 72443409 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1940051972 May 07 12:35:01 PM PDT 24 May 07 12:35:03 PM PDT 24 66324544 ps
T598 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1033796126 May 07 12:34:51 PM PDT 24 May 07 12:34:53 PM PDT 24 64165038 ps
T118 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2837673985 May 07 12:34:46 PM PDT 24 May 07 12:34:52 PM PDT 24 922955907 ps
T599 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2199152170 May 07 12:35:09 PM PDT 24 May 07 12:35:12 PM PDT 24 129333462 ps
T600 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3284436232 May 07 12:34:50 PM PDT 24 May 07 12:34:55 PM PDT 24 605086152 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.748022763 May 07 12:34:37 PM PDT 24 May 07 12:34:42 PM PDT 24 78205199 ps
T119 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1151130291 May 07 12:35:11 PM PDT 24 May 07 12:35:17 PM PDT 24 936702017 ps
T602 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3533594658 May 07 12:35:11 PM PDT 24 May 07 12:35:14 PM PDT 24 224282529 ps
T603 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1525290128 May 07 12:35:09 PM PDT 24 May 07 12:35:14 PM PDT 24 874293370 ps
T604 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1238771481 May 07 12:35:12 PM PDT 24 May 07 12:35:17 PM PDT 24 943920316 ps
T605 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1556987224 May 07 12:34:58 PM PDT 24 May 07 12:35:03 PM PDT 24 275195665 ps
T606 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.13121598 May 07 12:34:41 PM PDT 24 May 07 12:34:48 PM PDT 24 790751079 ps
T607 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3570758020 May 07 12:34:39 PM PDT 24 May 07 12:34:45 PM PDT 24 173159339 ps
T608 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1922972474 May 07 12:35:04 PM PDT 24 May 07 12:35:06 PM PDT 24 69272853 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.218912034 May 07 12:35:19 PM PDT 24 May 07 12:35:23 PM PDT 24 125241684 ps
T610 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1828820779 May 07 12:34:43 PM PDT 24 May 07 12:34:48 PM PDT 24 212776755 ps
T611 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2700552500 May 07 12:34:58 PM PDT 24 May 07 12:35:01 PM PDT 24 191660953 ps
T612 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1762476541 May 07 12:35:03 PM PDT 24 May 07 12:35:06 PM PDT 24 131162625 ps
T613 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.999055794 May 07 12:35:10 PM PDT 24 May 07 12:35:14 PM PDT 24 130617364 ps
T614 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2900246449 May 07 12:34:52 PM PDT 24 May 07 12:34:58 PM PDT 24 798235625 ps
T615 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1006620825 May 07 12:35:13 PM PDT 24 May 07 12:35:16 PM PDT 24 121782385 ps
T616 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4122440959 May 07 12:35:03 PM PDT 24 May 07 12:35:08 PM PDT 24 493501890 ps
T120 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1717495657 May 07 12:34:39 PM PDT 24 May 07 12:34:46 PM PDT 24 877032826 ps
T617 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3524390305 May 07 12:34:45 PM PDT 24 May 07 12:34:49 PM PDT 24 136609066 ps
T618 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3226301898 May 07 12:34:40 PM PDT 24 May 07 12:34:45 PM PDT 24 183023923 ps
T619 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2069923779 May 07 12:35:04 PM PDT 24 May 07 12:35:08 PM PDT 24 194490275 ps
T620 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.629831581 May 07 12:35:02 PM PDT 24 May 07 12:35:05 PM PDT 24 174406271 ps

Test location /workspace/coverage/default/20.rstmgr_reset.3344597350
Short name T8
Test name
Test status
Simulation time 922075340 ps
CPU time 4.52 seconds
Started May 07 12:35:37 PM PDT 24
Finished May 07 12:35:44 PM PDT 24
Peak memory 200936 kb
Host smart-cd0aeb4e-ec83-44a0-ac47-ec454761a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344597350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3344597350
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3967066672
Short name T7
Test name
Test status
Simulation time 122651256 ps
CPU time 1.53 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:19 PM PDT 24
Peak memory 209048 kb
Host smart-2f40f121-8ef4-495f-b822-a516369d3257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967066672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3967066672
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2015656416
Short name T34
Test name
Test status
Simulation time 2172678105 ps
CPU time 7.69 seconds
Started May 07 12:35:59 PM PDT 24
Finished May 07 12:36:08 PM PDT 24
Peak memory 217560 kb
Host smart-e0b27b5b-af74-43ee-b01a-aba5f7618efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015656416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2015656416
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3953680795
Short name T64
Test name
Test status
Simulation time 181026450 ps
CPU time 1.12 seconds
Started May 07 12:34:57 PM PDT 24
Finished May 07 12:34:59 PM PDT 24
Peak memory 208456 kb
Host smart-67c96616-52f3-4a9b-a6de-0864601f8163
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953680795 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3953680795
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3325774277
Short name T66
Test name
Test status
Simulation time 17647386002 ps
CPU time 26.53 seconds
Started May 07 12:35:10 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 217532 kb
Host smart-330ec1b2-7f59-400f-853b-3d542fcbb1f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325774277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3325774277
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2610299505
Short name T86
Test name
Test status
Simulation time 11802657863 ps
CPU time 40.6 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:37:01 PM PDT 24
Peak memory 209328 kb
Host smart-d2a1a0da-f700-44e8-8e68-2f4a80bbaba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610299505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2610299505
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.870338634
Short name T58
Test name
Test status
Simulation time 472992714 ps
CPU time 1.93 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:23 PM PDT 24
Peak memory 200620 kb
Host smart-b4e05b5a-04d6-4025-8d3a-df167df7223e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870338634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.870338634
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.119767760
Short name T26
Test name
Test status
Simulation time 64160420 ps
CPU time 0.73 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 200596 kb
Host smart-9ec7dd75-4b8d-4168-8adf-9db17ca1e0c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119767760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.119767760
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.76864398
Short name T48
Test name
Test status
Simulation time 2363917023 ps
CPU time 9 seconds
Started May 07 12:35:21 PM PDT 24
Finished May 07 12:35:32 PM PDT 24
Peak memory 222348 kb
Host smart-a754e693-4254-4d72-9926-683b2c98b70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76864398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.76864398
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.438269545
Short name T122
Test name
Test status
Simulation time 516403266 ps
CPU time 3.47 seconds
Started May 07 12:35:13 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 208616 kb
Host smart-23977be0-0530-4924-a9e9-a4cadeb4694f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438269545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.438269545
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1257773411
Short name T185
Test name
Test status
Simulation time 8953271057 ps
CPU time 30.45 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:36:03 PM PDT 24
Peak memory 210884 kb
Host smart-72908275-4d1a-42fd-b28f-12b57675301a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257773411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1257773411
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4013167226
Short name T162
Test name
Test status
Simulation time 107908315 ps
CPU time 0.98 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 200800 kb
Host smart-ad1f6453-b302-43c4-80d4-7e93de644adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013167226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4013167226
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.774818337
Short name T165
Test name
Test status
Simulation time 95900600 ps
CPU time 0.91 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 200796 kb
Host smart-b7a4f487-c302-4309-9dfc-f29acf98cc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774818337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.774818337
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3080686912
Short name T60
Test name
Test status
Simulation time 415070234 ps
CPU time 2.94 seconds
Started May 07 12:35:08 PM PDT 24
Finished May 07 12:35:13 PM PDT 24
Peak memory 208744 kb
Host smart-b14e93cf-3a77-4004-a882-944d8f5478aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080686912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3080686912
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3546704894
Short name T2
Test name
Test status
Simulation time 2356132727 ps
CPU time 7.78 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:57 PM PDT 24
Peak memory 222196 kb
Host smart-59182053-9608-40d5-b816-b968f2768e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546704894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3546704894
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2151193976
Short name T125
Test name
Test status
Simulation time 930041905 ps
CPU time 3.03 seconds
Started May 07 12:35:18 PM PDT 24
Finished May 07 12:35:23 PM PDT 24
Peak memory 200552 kb
Host smart-89c1d5ae-d261-4861-996d-0a5dc72cacbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151193976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2151193976
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2837673985
Short name T118
Test name
Test status
Simulation time 922955907 ps
CPU time 3.39 seconds
Started May 07 12:34:46 PM PDT 24
Finished May 07 12:34:52 PM PDT 24
Peak memory 199580 kb
Host smart-039f09fd-848a-4426-a153-5ddd56680d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837673985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2837673985
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1470845705
Short name T54
Test name
Test status
Simulation time 79457337 ps
CPU time 0.9 seconds
Started May 07 12:34:58 PM PDT 24
Finished May 07 12:35:01 PM PDT 24
Peak memory 200232 kb
Host smart-2fd4eabf-6ada-4ffc-a50f-8eacf3cb1cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470845705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1470845705
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.318511712
Short name T22
Test name
Test status
Simulation time 231983835 ps
CPU time 0.98 seconds
Started May 07 12:35:22 PM PDT 24
Finished May 07 12:35:25 PM PDT 24
Peak memory 200528 kb
Host smart-c9018ee3-3984-4264-bc91-9b25d183a461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318511712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.318511712
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3391085011
Short name T37
Test name
Test status
Simulation time 1224085637 ps
CPU time 5.48 seconds
Started May 07 12:35:18 PM PDT 24
Finished May 07 12:35:25 PM PDT 24
Peak memory 218376 kb
Host smart-fdcbb2e2-8076-466a-8838-8d79fdd8614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391085011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3391085011
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3231859367
Short name T573
Test name
Test status
Simulation time 126568438 ps
CPU time 1.7 seconds
Started May 07 12:34:42 PM PDT 24
Finished May 07 12:34:47 PM PDT 24
Peak memory 208644 kb
Host smart-fe89d09b-0fb7-4942-a964-098ffb70abcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231859367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3231859367
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3988760734
Short name T553
Test name
Test status
Simulation time 161110044 ps
CPU time 1.95 seconds
Started May 07 12:34:38 PM PDT 24
Finished May 07 12:34:44 PM PDT 24
Peak memory 200368 kb
Host smart-6f77249f-a979-46ab-b4c9-2a3ec07c92c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988760734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
988760734
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3331991168
Short name T548
Test name
Test status
Simulation time 1563796898 ps
CPU time 8.67 seconds
Started May 07 12:35:00 PM PDT 24
Finished May 07 12:35:10 PM PDT 24
Peak memory 200308 kb
Host smart-b03e2f2b-5f0a-47b2-a241-10c3b9f99eb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331991168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
331991168
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3606150585
Short name T556
Test name
Test status
Simulation time 102451037 ps
CPU time 0.83 seconds
Started May 07 12:35:01 PM PDT 24
Finished May 07 12:35:04 PM PDT 24
Peak memory 200232 kb
Host smart-c3968734-db5d-46c4-bc4c-a5d242a19f87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606150585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
606150585
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2240132349
Short name T558
Test name
Test status
Simulation time 60200514 ps
CPU time 0.79 seconds
Started May 07 12:34:53 PM PDT 24
Finished May 07 12:34:55 PM PDT 24
Peak memory 200284 kb
Host smart-d71f4acd-63e7-48a5-81c7-7571478f3baf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240132349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2240132349
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.581424496
Short name T583
Test name
Test status
Simulation time 160024001 ps
CPU time 1.12 seconds
Started May 07 12:34:39 PM PDT 24
Finished May 07 12:34:44 PM PDT 24
Peak memory 200272 kb
Host smart-b461475b-e32e-490e-9803-1edc54000533
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581424496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.581424496
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3992795927
Short name T92
Test name
Test status
Simulation time 493075221 ps
CPU time 1.84 seconds
Started May 07 12:34:57 PM PDT 24
Finished May 07 12:35:00 PM PDT 24
Peak memory 200428 kb
Host smart-169d6f85-0bdd-4983-948f-d6bb2d08c490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992795927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3992795927
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.545130578
Short name T555
Test name
Test status
Simulation time 361692250 ps
CPU time 2.72 seconds
Started May 07 12:35:03 PM PDT 24
Finished May 07 12:35:07 PM PDT 24
Peak memory 200408 kb
Host smart-b5d144e1-c0b0-49ce-bdcb-0de0e015c079
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545130578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.545130578
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.820955048
Short name T574
Test name
Test status
Simulation time 275400499 ps
CPU time 3.49 seconds
Started May 07 12:35:05 PM PDT 24
Finished May 07 12:35:10 PM PDT 24
Peak memory 200424 kb
Host smart-ba4ab507-5109-44cb-9aba-e5f291bdbea9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820955048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.820955048
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4101619857
Short name T562
Test name
Test status
Simulation time 112535078 ps
CPU time 0.85 seconds
Started May 07 12:34:45 PM PDT 24
Finished May 07 12:34:49 PM PDT 24
Peak memory 200216 kb
Host smart-f13b6cee-96ea-4d65-9e4e-bef76529ea81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101619857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
101619857
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2700552500
Short name T611
Test name
Test status
Simulation time 191660953 ps
CPU time 1.16 seconds
Started May 07 12:34:58 PM PDT 24
Finished May 07 12:35:01 PM PDT 24
Peak memory 208488 kb
Host smart-0af8bbd0-a55f-4398-a29c-5d2ddf837247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700552500 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2700552500
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2877999160
Short name T113
Test name
Test status
Simulation time 128455873 ps
CPU time 1.09 seconds
Started May 07 12:34:45 PM PDT 24
Finished May 07 12:34:49 PM PDT 24
Peak memory 200296 kb
Host smart-0ace7701-bac9-4b0b-a85c-3a6397649456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877999160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2877999160
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3591651719
Short name T565
Test name
Test status
Simulation time 514746613 ps
CPU time 3.64 seconds
Started May 07 12:34:47 PM PDT 24
Finished May 07 12:34:53 PM PDT 24
Peak memory 208620 kb
Host smart-da4d45e0-3357-44eb-a0ab-34e12638d49f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591651719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3591651719
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.13121598
Short name T606
Test name
Test status
Simulation time 790751079 ps
CPU time 2.84 seconds
Started May 07 12:34:41 PM PDT 24
Finished May 07 12:34:48 PM PDT 24
Peak memory 200460 kb
Host smart-3aec9e6d-0b87-401d-9db9-2ee40dd34f33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13121598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.13121598
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4270811504
Short name T95
Test name
Test status
Simulation time 115364001 ps
CPU time 1.3 seconds
Started May 07 12:35:15 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 208504 kb
Host smart-10106702-1578-4b41-8d9f-ca903403f078
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270811504 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.4270811504
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.323203536
Short name T110
Test name
Test status
Simulation time 59616723 ps
CPU time 0.78 seconds
Started May 07 12:34:43 PM PDT 24
Finished May 07 12:34:47 PM PDT 24
Peak memory 200196 kb
Host smart-826411b8-7164-426b-89d5-ea4881f942da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323203536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.323203536
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3978441144
Short name T111
Test name
Test status
Simulation time 209443835 ps
CPU time 1.31 seconds
Started May 07 12:34:58 PM PDT 24
Finished May 07 12:35:01 PM PDT 24
Peak memory 200428 kb
Host smart-56b04ba8-b76e-482d-9823-ae3c86a67354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978441144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3978441144
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.218912034
Short name T609
Test name
Test status
Simulation time 125241684 ps
CPU time 1.02 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:23 PM PDT 24
Peak memory 200320 kb
Host smart-81e9a444-844b-4cd8-9c0e-04d74f893dce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218912034 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.218912034
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3731159717
Short name T593
Test name
Test status
Simulation time 69190837 ps
CPU time 0.9 seconds
Started May 07 12:35:16 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 200240 kb
Host smart-582544d9-c7bf-4fa7-98af-9d9cd412dfc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731159717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3731159717
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1762476541
Short name T612
Test name
Test status
Simulation time 131162625 ps
CPU time 1.45 seconds
Started May 07 12:35:03 PM PDT 24
Finished May 07 12:35:06 PM PDT 24
Peak memory 200432 kb
Host smart-49082161-e64d-414c-912d-05211b144129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762476541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1762476541
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.56675680
Short name T594
Test name
Test status
Simulation time 329243830 ps
CPU time 2.43 seconds
Started May 07 12:35:09 PM PDT 24
Finished May 07 12:35:13 PM PDT 24
Peak memory 216708 kb
Host smart-699f9259-e863-4343-a30b-1ba4d5576bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56675680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.56675680
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1525290128
Short name T603
Test name
Test status
Simulation time 874293370 ps
CPU time 3.39 seconds
Started May 07 12:35:09 PM PDT 24
Finished May 07 12:35:14 PM PDT 24
Peak memory 200480 kb
Host smart-964038a8-4a8a-4723-b640-b08de6750cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525290128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1525290128
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2143702062
Short name T57
Test name
Test status
Simulation time 138982506 ps
CPU time 1.18 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:23 PM PDT 24
Peak memory 210612 kb
Host smart-e45ded12-1012-4f78-8495-ff4d5086d23e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143702062 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2143702062
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2809840779
Short name T581
Test name
Test status
Simulation time 91816240 ps
CPU time 0.9 seconds
Started May 07 12:35:10 PM PDT 24
Finished May 07 12:35:12 PM PDT 24
Peak memory 200296 kb
Host smart-0a97caf8-5093-49e1-a838-46d3bfab2e96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809840779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2809840779
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2265616978
Short name T585
Test name
Test status
Simulation time 146529955 ps
CPU time 1.22 seconds
Started May 07 12:35:11 PM PDT 24
Finished May 07 12:35:14 PM PDT 24
Peak memory 200616 kb
Host smart-fd03f648-3b3a-4b7c-9e92-1bb1fc3b414e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265616978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2265616978
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3284436232
Short name T600
Test name
Test status
Simulation time 605086152 ps
CPU time 3.65 seconds
Started May 07 12:34:50 PM PDT 24
Finished May 07 12:34:55 PM PDT 24
Peak memory 208628 kb
Host smart-ff6dd280-c18e-40ef-8a56-32e62260a089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284436232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3284436232
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1458142660
Short name T87
Test name
Test status
Simulation time 464037969 ps
CPU time 2.11 seconds
Started May 07 12:35:08 PM PDT 24
Finished May 07 12:35:12 PM PDT 24
Peak memory 200516 kb
Host smart-1d27c506-4225-4d23-99a7-c7ef49a7fc65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458142660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1458142660
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3533594658
Short name T602
Test name
Test status
Simulation time 224282529 ps
CPU time 1.41 seconds
Started May 07 12:35:11 PM PDT 24
Finished May 07 12:35:14 PM PDT 24
Peak memory 211196 kb
Host smart-9099a0a7-3bad-4fe6-9acb-06a1abffafcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533594658 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3533594658
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2644421202
Short name T549
Test name
Test status
Simulation time 82693206 ps
CPU time 0.84 seconds
Started May 07 12:35:04 PM PDT 24
Finished May 07 12:35:07 PM PDT 24
Peak memory 200232 kb
Host smart-5ea6c1a9-eb52-47da-becf-603a0ed916d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644421202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2644421202
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1869304472
Short name T115
Test name
Test status
Simulation time 136366085 ps
CPU time 1.31 seconds
Started May 07 12:34:49 PM PDT 24
Finished May 07 12:34:52 PM PDT 24
Peak memory 200316 kb
Host smart-23fefbb4-cde3-48f8-897e-b20efec9974d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869304472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1869304472
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2279495991
Short name T576
Test name
Test status
Simulation time 776295123 ps
CPU time 2.76 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:12 PM PDT 24
Peak memory 200452 kb
Host smart-037d22ba-ada0-49dc-b608-97150891ff91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279495991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2279495991
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.629831581
Short name T620
Test name
Test status
Simulation time 174406271 ps
CPU time 1.61 seconds
Started May 07 12:35:02 PM PDT 24
Finished May 07 12:35:05 PM PDT 24
Peak memory 208680 kb
Host smart-26a0977d-b028-457f-b750-c3c56d153e52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629831581 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.629831581
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1096579812
Short name T582
Test name
Test status
Simulation time 58784164 ps
CPU time 0.74 seconds
Started May 07 12:35:06 PM PDT 24
Finished May 07 12:35:08 PM PDT 24
Peak memory 200136 kb
Host smart-d75dbdc4-dd6b-4c9d-85a0-8ed63e2cee06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096579812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1096579812
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3560002582
Short name T580
Test name
Test status
Simulation time 207657303 ps
CPU time 1.43 seconds
Started May 07 12:35:15 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 200468 kb
Host smart-56d4d68e-b599-4471-bc6a-8f6768d2766b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560002582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3560002582
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.779882078
Short name T595
Test name
Test status
Simulation time 467656805 ps
CPU time 3.65 seconds
Started May 07 12:35:09 PM PDT 24
Finished May 07 12:35:15 PM PDT 24
Peak memory 212020 kb
Host smart-c845434f-c1c2-4aaa-b0dd-4eb910211196
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779882078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.779882078
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1238771481
Short name T604
Test name
Test status
Simulation time 943920316 ps
CPU time 3.11 seconds
Started May 07 12:35:12 PM PDT 24
Finished May 07 12:35:17 PM PDT 24
Peak memory 200512 kb
Host smart-2230af9b-5298-4c46-b8d4-c15fadb4b0c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238771481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1238771481
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1685407339
Short name T116
Test name
Test status
Simulation time 168866067 ps
CPU time 1.52 seconds
Started May 07 12:35:02 PM PDT 24
Finished May 07 12:35:05 PM PDT 24
Peak memory 213216 kb
Host smart-8ec17cbc-6774-4485-ae3c-e3c40cd032e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685407339 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1685407339
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3174436983
Short name T114
Test name
Test status
Simulation time 71039429 ps
CPU time 0.78 seconds
Started May 07 12:34:59 PM PDT 24
Finished May 07 12:35:01 PM PDT 24
Peak memory 200196 kb
Host smart-b74e6008-807d-4b88-98f4-610e1ca857f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174436983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3174436983
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.523512456
Short name T53
Test name
Test status
Simulation time 75814031 ps
CPU time 1.02 seconds
Started May 07 12:35:12 PM PDT 24
Finished May 07 12:35:15 PM PDT 24
Peak memory 200228 kb
Host smart-36f4e546-6d31-47bd-b23a-28fe88a89ef8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523512456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.523512456
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2069923779
Short name T619
Test name
Test status
Simulation time 194490275 ps
CPU time 2.84 seconds
Started May 07 12:35:04 PM PDT 24
Finished May 07 12:35:08 PM PDT 24
Peak memory 212020 kb
Host smart-e49463d9-0acd-48df-9ee5-afceb7d77ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069923779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2069923779
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1050774305
Short name T137
Test name
Test status
Simulation time 431987420 ps
CPU time 1.91 seconds
Started May 07 12:35:05 PM PDT 24
Finished May 07 12:35:09 PM PDT 24
Peak memory 200456 kb
Host smart-b57fdbde-1173-4139-b452-7b46ddb4b95b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050774305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1050774305
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.357078022
Short name T566
Test name
Test status
Simulation time 188439929 ps
CPU time 1.86 seconds
Started May 07 12:35:05 PM PDT 24
Finished May 07 12:35:08 PM PDT 24
Peak memory 208720 kb
Host smart-8baaf0ef-2853-4690-8834-1f1cca9ab446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357078022 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.357078022
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1164196557
Short name T55
Test name
Test status
Simulation time 64116924 ps
CPU time 0.85 seconds
Started May 07 12:35:12 PM PDT 24
Finished May 07 12:35:15 PM PDT 24
Peak memory 200168 kb
Host smart-f24d642d-0a1d-402e-b4b9-d71d09551149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164196557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1164196557
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1054908189
Short name T560
Test name
Test status
Simulation time 100732332 ps
CPU time 1.21 seconds
Started May 07 12:35:10 PM PDT 24
Finished May 07 12:35:12 PM PDT 24
Peak memory 200484 kb
Host smart-c3f927ac-96d5-4556-aa87-398760002095
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054908189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1054908189
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4122440959
Short name T616
Test name
Test status
Simulation time 493501890 ps
CPU time 3.09 seconds
Started May 07 12:35:03 PM PDT 24
Finished May 07 12:35:08 PM PDT 24
Peak memory 208664 kb
Host smart-0d676ae9-f298-4c88-bd3c-eafdc95d6e36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122440959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4122440959
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4019840629
Short name T591
Test name
Test status
Simulation time 466907354 ps
CPU time 1.82 seconds
Started May 07 12:35:20 PM PDT 24
Finished May 07 12:35:24 PM PDT 24
Peak memory 200500 kb
Host smart-495b94bf-8ee7-404e-a83c-bdf0c58bb003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019840629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.4019840629
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1900820857
Short name T91
Test name
Test status
Simulation time 159496604 ps
CPU time 1.15 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:23 PM PDT 24
Peak memory 200332 kb
Host smart-46e084a0-b58c-4d5c-8c9c-92f023b27945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900820857 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1900820857
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1493289505
Short name T56
Test name
Test status
Simulation time 77778414 ps
CPU time 0.85 seconds
Started May 07 12:35:06 PM PDT 24
Finished May 07 12:35:08 PM PDT 24
Peak memory 200172 kb
Host smart-fd4b227e-7a2f-4f7e-ba5f-7e7751309302
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493289505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1493289505
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.617009849
Short name T567
Test name
Test status
Simulation time 130275840 ps
CPU time 1.32 seconds
Started May 07 12:35:17 PM PDT 24
Finished May 07 12:35:19 PM PDT 24
Peak memory 200512 kb
Host smart-1565ae2a-0b52-4063-b5ea-fb7b869ac490
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617009849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.617009849
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2780933398
Short name T59
Test name
Test status
Simulation time 116658482 ps
CPU time 1.72 seconds
Started May 07 12:35:05 PM PDT 24
Finished May 07 12:35:10 PM PDT 24
Peak memory 211368 kb
Host smart-3e6f4eed-0455-4003-906c-ce4d780220c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780933398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2780933398
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3541376592
Short name T124
Test name
Test status
Simulation time 788911149 ps
CPU time 3.17 seconds
Started May 07 12:34:56 PM PDT 24
Finished May 07 12:35:00 PM PDT 24
Peak memory 200452 kb
Host smart-3933df73-fb23-4581-bc51-ad60a3734f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541376592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3541376592
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2199152170
Short name T599
Test name
Test status
Simulation time 129333462 ps
CPU time 1.1 seconds
Started May 07 12:35:09 PM PDT 24
Finished May 07 12:35:12 PM PDT 24
Peak memory 200336 kb
Host smart-1e7baeb5-8c43-4d6b-9fdb-1ab6210c45ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199152170 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2199152170
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3828119793
Short name T112
Test name
Test status
Simulation time 68945153 ps
CPU time 0.9 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:10 PM PDT 24
Peak memory 200200 kb
Host smart-f9de800c-cbd7-4251-8c25-708cf61a342a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828119793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3828119793
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1103919663
Short name T571
Test name
Test status
Simulation time 230167198 ps
CPU time 1.58 seconds
Started May 07 12:35:16 PM PDT 24
Finished May 07 12:35:19 PM PDT 24
Peak memory 200436 kb
Host smart-7a703405-546a-453b-a80e-2fd68f5accfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103919663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1103919663
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2924539630
Short name T88
Test name
Test status
Simulation time 117736382 ps
CPU time 1.69 seconds
Started May 07 12:34:58 PM PDT 24
Finished May 07 12:35:01 PM PDT 24
Peak memory 208596 kb
Host smart-99080131-b210-406c-8cbd-3e705ca92f79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924539630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2924539630
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3608881707
Short name T123
Test name
Test status
Simulation time 113740372 ps
CPU time 0.96 seconds
Started May 07 12:35:09 PM PDT 24
Finished May 07 12:35:11 PM PDT 24
Peak memory 200320 kb
Host smart-f3b2d1b9-b4ea-4f37-a102-ba313a65958d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608881707 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3608881707
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1922972474
Short name T608
Test name
Test status
Simulation time 69272853 ps
CPU time 0.77 seconds
Started May 07 12:35:04 PM PDT 24
Finished May 07 12:35:06 PM PDT 24
Peak memory 200108 kb
Host smart-3f0b329f-9eef-4759-a94d-c18d46a0de1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922972474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1922972474
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1787830526
Short name T559
Test name
Test status
Simulation time 76991843 ps
CPU time 0.99 seconds
Started May 07 12:35:09 PM PDT 24
Finished May 07 12:35:11 PM PDT 24
Peak memory 200340 kb
Host smart-5c4ef2f6-c822-4a60-8787-8a1850cb48b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787830526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1787830526
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1521169700
Short name T96
Test name
Test status
Simulation time 333992835 ps
CPU time 2.49 seconds
Started May 07 12:35:03 PM PDT 24
Finished May 07 12:35:08 PM PDT 24
Peak memory 216748 kb
Host smart-190cab00-4524-4195-b242-7ce00226082c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521169700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1521169700
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1828820779
Short name T610
Test name
Test status
Simulation time 212776755 ps
CPU time 1.52 seconds
Started May 07 12:34:43 PM PDT 24
Finished May 07 12:34:48 PM PDT 24
Peak memory 200444 kb
Host smart-218a322a-a78f-4ea3-8b79-251dd788acc9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828820779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
828820779
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2900246449
Short name T614
Test name
Test status
Simulation time 798235625 ps
CPU time 4.25 seconds
Started May 07 12:34:52 PM PDT 24
Finished May 07 12:34:58 PM PDT 24
Peak memory 200404 kb
Host smart-2d090ad2-9073-4776-8ea9-22b193c44652
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900246449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
900246449
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3625841780
Short name T554
Test name
Test status
Simulation time 147522667 ps
CPU time 0.93 seconds
Started May 07 12:34:51 PM PDT 24
Finished May 07 12:34:53 PM PDT 24
Peak memory 200216 kb
Host smart-11fd1811-9c10-4ea0-a408-cf26328b6178
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625841780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
625841780
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2631719481
Short name T586
Test name
Test status
Simulation time 193069710 ps
CPU time 1.21 seconds
Started May 07 12:35:03 PM PDT 24
Finished May 07 12:35:06 PM PDT 24
Peak memory 208496 kb
Host smart-c1698a93-134c-4330-991a-b56c77a4be2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631719481 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2631719481
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.748022763
Short name T601
Test name
Test status
Simulation time 78205199 ps
CPU time 0.83 seconds
Started May 07 12:34:37 PM PDT 24
Finished May 07 12:34:42 PM PDT 24
Peak memory 200144 kb
Host smart-65082e36-43e4-4260-bd03-85387630b60d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748022763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.748022763
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2034433923
Short name T588
Test name
Test status
Simulation time 260916173 ps
CPU time 1.55 seconds
Started May 07 12:34:55 PM PDT 24
Finished May 07 12:34:57 PM PDT 24
Peak memory 200428 kb
Host smart-79624c44-1f00-4cba-83fe-2150229b5b9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034433923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2034433923
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.148895668
Short name T570
Test name
Test status
Simulation time 137495535 ps
CPU time 2.19 seconds
Started May 07 12:35:01 PM PDT 24
Finished May 07 12:35:04 PM PDT 24
Peak memory 208608 kb
Host smart-e06b351a-cf8b-40c0-bc82-3bb6e3d142dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148895668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.148895668
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1717495657
Short name T120
Test name
Test status
Simulation time 877032826 ps
CPU time 3.01 seconds
Started May 07 12:34:39 PM PDT 24
Finished May 07 12:34:46 PM PDT 24
Peak memory 200448 kb
Host smart-5b128f8a-eda6-4962-be98-b1702373111a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717495657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1717495657
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4078503418
Short name T564
Test name
Test status
Simulation time 196692118 ps
CPU time 1.58 seconds
Started May 07 12:35:00 PM PDT 24
Finished May 07 12:35:02 PM PDT 24
Peak memory 200288 kb
Host smart-793a42a9-9d85-476f-ae35-29f1d018a2cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078503418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
078503418
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2784857114
Short name T550
Test name
Test status
Simulation time 784746742 ps
CPU time 4.34 seconds
Started May 07 12:34:38 PM PDT 24
Finished May 07 12:34:46 PM PDT 24
Peak memory 200352 kb
Host smart-8c8c933b-ca5c-4a0d-82d3-80ab5073e730
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784857114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
784857114
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1909989814
Short name T552
Test name
Test status
Simulation time 149492967 ps
CPU time 0.99 seconds
Started May 07 12:35:03 PM PDT 24
Finished May 07 12:35:06 PM PDT 24
Peak memory 200172 kb
Host smart-e4b96446-e2b4-4ca4-8651-408c140d8bfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909989814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
909989814
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.900327541
Short name T89
Test name
Test status
Simulation time 191571958 ps
CPU time 1.29 seconds
Started May 07 12:35:01 PM PDT 24
Finished May 07 12:35:04 PM PDT 24
Peak memory 208428 kb
Host smart-c733ef29-4eb2-450e-8140-46d2aa823c26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900327541 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.900327541
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3658691530
Short name T596
Test name
Test status
Simulation time 72443409 ps
CPU time 0.85 seconds
Started May 07 12:35:06 PM PDT 24
Finished May 07 12:35:08 PM PDT 24
Peak memory 200204 kb
Host smart-ece68f46-1713-4bc6-a5bc-f14ef830b34d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658691530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3658691530
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1092225342
Short name T592
Test name
Test status
Simulation time 151750031 ps
CPU time 1.19 seconds
Started May 07 12:34:43 PM PDT 24
Finished May 07 12:34:47 PM PDT 24
Peak memory 200244 kb
Host smart-3f58335f-3564-48ca-a8f8-a2890a259666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092225342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1092225342
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.577936737
Short name T557
Test name
Test status
Simulation time 201192780 ps
CPU time 2.91 seconds
Started May 07 12:34:43 PM PDT 24
Finished May 07 12:34:50 PM PDT 24
Peak memory 208696 kb
Host smart-74db9200-2c9b-4595-afca-d284a36e47b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577936737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.577936737
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2172745148
Short name T136
Test name
Test status
Simulation time 785003464 ps
CPU time 2.88 seconds
Started May 07 12:34:54 PM PDT 24
Finished May 07 12:34:58 PM PDT 24
Peak memory 200452 kb
Host smart-e12e28b7-e10b-4d91-9783-c4a8f6753592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172745148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2172745148
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3516038924
Short name T551
Test name
Test status
Simulation time 205157597 ps
CPU time 1.57 seconds
Started May 07 12:34:57 PM PDT 24
Finished May 07 12:35:00 PM PDT 24
Peak memory 200372 kb
Host smart-53bd7627-49f8-4564-8049-8303c4fc2ab0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516038924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
516038924
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1556987224
Short name T605
Test name
Test status
Simulation time 275195665 ps
CPU time 3.16 seconds
Started May 07 12:34:58 PM PDT 24
Finished May 07 12:35:03 PM PDT 24
Peak memory 200468 kb
Host smart-0354b505-a477-4704-9513-6f1485d1e2d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556987224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
556987224
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1695300152
Short name T590
Test name
Test status
Simulation time 102277453 ps
CPU time 0.84 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:09 PM PDT 24
Peak memory 200212 kb
Host smart-feff1ee1-7056-4e17-bbda-005181020109
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695300152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
695300152
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3479933640
Short name T90
Test name
Test status
Simulation time 228192325 ps
CPU time 1.41 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:11 PM PDT 24
Peak memory 208504 kb
Host smart-c02b06cd-ec3e-4137-8be4-261700e59c5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479933640 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3479933640
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1940051972
Short name T597
Test name
Test status
Simulation time 66324544 ps
CPU time 0.77 seconds
Started May 07 12:35:01 PM PDT 24
Finished May 07 12:35:03 PM PDT 24
Peak memory 200188 kb
Host smart-c05c3ef1-deb5-4205-8f89-5c598128f34e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940051972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1940051972
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2118248816
Short name T109
Test name
Test status
Simulation time 160993013 ps
CPU time 1.21 seconds
Started May 07 12:34:52 PM PDT 24
Finished May 07 12:34:55 PM PDT 24
Peak memory 200244 kb
Host smart-3754be03-b422-4f1c-b9c8-6ff5c38c36be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118248816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2118248816
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3113770135
Short name T578
Test name
Test status
Simulation time 215240872 ps
CPU time 3.09 seconds
Started May 07 12:34:39 PM PDT 24
Finished May 07 12:34:46 PM PDT 24
Peak memory 200512 kb
Host smart-879b7399-4763-4c28-9341-de87bfd520b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113770135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3113770135
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3280219299
Short name T93
Test name
Test status
Simulation time 940376016 ps
CPU time 3.46 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:13 PM PDT 24
Peak memory 200460 kb
Host smart-98a3dd73-d9c6-4bd3-a7eb-b1ada69dfe26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280219299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3280219299
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3570758020
Short name T607
Test name
Test status
Simulation time 173159339 ps
CPU time 1.14 seconds
Started May 07 12:34:39 PM PDT 24
Finished May 07 12:34:45 PM PDT 24
Peak memory 208516 kb
Host smart-479af38c-e1d9-4c3b-8bd1-7593a0669754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570758020 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3570758020
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2668196269
Short name T546
Test name
Test status
Simulation time 73240435 ps
CPU time 0.82 seconds
Started May 07 12:34:46 PM PDT 24
Finished May 07 12:34:50 PM PDT 24
Peak memory 200180 kb
Host smart-2ac40fb0-cc1d-4b91-acff-6af2e97327c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668196269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2668196269
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.239080171
Short name T569
Test name
Test status
Simulation time 152657385 ps
CPU time 1.1 seconds
Started May 07 12:34:52 PM PDT 24
Finished May 07 12:34:55 PM PDT 24
Peak memory 200236 kb
Host smart-ae6560e9-3ed9-493e-8f8d-a682d9a7b1f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239080171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.239080171
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.999055794
Short name T613
Test name
Test status
Simulation time 130617364 ps
CPU time 1.74 seconds
Started May 07 12:35:10 PM PDT 24
Finished May 07 12:35:14 PM PDT 24
Peak memory 208668 kb
Host smart-1a0b80b9-b481-4013-80b2-9ded4f4a9e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999055794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.999055794
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.482493118
Short name T94
Test name
Test status
Simulation time 458323490 ps
CPU time 1.95 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:23 PM PDT 24
Peak memory 200468 kb
Host smart-c8481779-c477-4e37-9ffc-32ec9a148848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482493118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
482493118
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1006620825
Short name T615
Test name
Test status
Simulation time 121782385 ps
CPU time 1.16 seconds
Started May 07 12:35:13 PM PDT 24
Finished May 07 12:35:16 PM PDT 24
Peak memory 208492 kb
Host smart-ea8b7574-29aa-4d47-81a3-4759255c8bc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006620825 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1006620825
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.884785918
Short name T547
Test name
Test status
Simulation time 66523205 ps
CPU time 0.79 seconds
Started May 07 12:34:36 PM PDT 24
Finished May 07 12:34:41 PM PDT 24
Peak memory 200164 kb
Host smart-874e2f3f-9006-4f20-b2d4-bc4368667ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884785918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.884785918
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.433107358
Short name T568
Test name
Test status
Simulation time 84273957 ps
CPU time 0.93 seconds
Started May 07 12:35:03 PM PDT 24
Finished May 07 12:35:06 PM PDT 24
Peak memory 200216 kb
Host smart-21d0c24c-c663-4207-89c2-cd5cebc9a5ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433107358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.433107358
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.694324994
Short name T587
Test name
Test status
Simulation time 541077418 ps
CPU time 3.65 seconds
Started May 07 12:34:56 PM PDT 24
Finished May 07 12:35:01 PM PDT 24
Peak memory 211428 kb
Host smart-4a9a31ab-3369-489c-9a60-fdfb5fa58201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694324994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.694324994
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1702628172
Short name T577
Test name
Test status
Simulation time 462625813 ps
CPU time 2 seconds
Started May 07 12:34:38 PM PDT 24
Finished May 07 12:34:44 PM PDT 24
Peak memory 200580 kb
Host smart-8adbb94e-5c25-42e1-8d65-f79bc406415b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702628172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1702628172
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2838784651
Short name T126
Test name
Test status
Simulation time 181319583 ps
CPU time 1.61 seconds
Started May 07 12:34:42 PM PDT 24
Finished May 07 12:34:47 PM PDT 24
Peak memory 209028 kb
Host smart-035138c1-d8fa-494a-a0c2-a44e2bac102b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838784651 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2838784651
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1033796126
Short name T598
Test name
Test status
Simulation time 64165038 ps
CPU time 0.86 seconds
Started May 07 12:34:51 PM PDT 24
Finished May 07 12:34:53 PM PDT 24
Peak memory 200152 kb
Host smart-171fa596-02ef-4a9b-a8f9-dbf5991d2e52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033796126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1033796126
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3684733809
Short name T575
Test name
Test status
Simulation time 75612605 ps
CPU time 0.96 seconds
Started May 07 12:34:51 PM PDT 24
Finished May 07 12:34:53 PM PDT 24
Peak memory 200284 kb
Host smart-1c718e02-60ab-473c-a303-5405bc5622c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684733809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3684733809
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.523500466
Short name T579
Test name
Test status
Simulation time 235000035 ps
CPU time 1.89 seconds
Started May 07 12:34:59 PM PDT 24
Finished May 07 12:35:03 PM PDT 24
Peak memory 208608 kb
Host smart-5aaacf9c-1115-4b2e-b5ed-6f56b79705a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523500466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.523500466
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1567273255
Short name T584
Test name
Test status
Simulation time 493070976 ps
CPU time 1.93 seconds
Started May 07 12:34:37 PM PDT 24
Finished May 07 12:34:43 PM PDT 24
Peak memory 200432 kb
Host smart-c61f56b9-b812-44f8-93a7-6a4dc9492774
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567273255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1567273255
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3385180443
Short name T572
Test name
Test status
Simulation time 136065525 ps
CPU time 1.05 seconds
Started May 07 12:34:39 PM PDT 24
Finished May 07 12:34:44 PM PDT 24
Peak memory 208496 kb
Host smart-5d741202-480b-45c8-99e4-69e86424ff0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385180443 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3385180443
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4098507247
Short name T563
Test name
Test status
Simulation time 63529702 ps
CPU time 0.82 seconds
Started May 07 12:34:39 PM PDT 24
Finished May 07 12:34:43 PM PDT 24
Peak memory 200176 kb
Host smart-d6e7fe91-6fc3-455d-b125-727c67988904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098507247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4098507247
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3524390305
Short name T617
Test name
Test status
Simulation time 136609066 ps
CPU time 1.09 seconds
Started May 07 12:34:45 PM PDT 24
Finished May 07 12:34:49 PM PDT 24
Peak memory 200280 kb
Host smart-7e2d8bef-bc43-4909-828f-5a64858e2a1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524390305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3524390305
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.997114113
Short name T121
Test name
Test status
Simulation time 128532624 ps
CPU time 1.69 seconds
Started May 07 12:34:44 PM PDT 24
Finished May 07 12:34:49 PM PDT 24
Peak memory 200460 kb
Host smart-8629b218-a9f7-4bc1-bb60-2e371a480ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997114113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.997114113
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.748413688
Short name T117
Test name
Test status
Simulation time 778167983 ps
CPU time 2.85 seconds
Started May 07 12:34:40 PM PDT 24
Finished May 07 12:34:47 PM PDT 24
Peak memory 200464 kb
Host smart-b10351bb-fac9-459e-aebf-d76c93f767c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748413688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
748413688
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3226301898
Short name T618
Test name
Test status
Simulation time 183023923 ps
CPU time 1.21 seconds
Started May 07 12:34:40 PM PDT 24
Finished May 07 12:34:45 PM PDT 24
Peak memory 200320 kb
Host smart-dd053ea2-d61d-4998-999a-02379bbae142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226301898 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3226301898
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3023790283
Short name T561
Test name
Test status
Simulation time 84912815 ps
CPU time 0.9 seconds
Started May 07 12:35:13 PM PDT 24
Finished May 07 12:35:16 PM PDT 24
Peak memory 200164 kb
Host smart-1d03a7f6-7d79-4325-be3f-bee1a8bf7da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023790283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3023790283
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1924903751
Short name T589
Test name
Test status
Simulation time 301203322 ps
CPU time 1.67 seconds
Started May 07 12:35:00 PM PDT 24
Finished May 07 12:35:03 PM PDT 24
Peak memory 200520 kb
Host smart-ee8ce1fa-b0e0-4531-be45-2e795c9db9fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924903751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1924903751
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3587200532
Short name T127
Test name
Test status
Simulation time 124909276 ps
CPU time 1.81 seconds
Started May 07 12:34:42 PM PDT 24
Finished May 07 12:34:47 PM PDT 24
Peak memory 211252 kb
Host smart-325d24c2-db95-4bbd-ba9b-f31dcea33faf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587200532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3587200532
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1151130291
Short name T119
Test name
Test status
Simulation time 936702017 ps
CPU time 3.23 seconds
Started May 07 12:35:11 PM PDT 24
Finished May 07 12:35:17 PM PDT 24
Peak memory 200548 kb
Host smart-55c8eecd-8e8f-457e-972d-18f8d6b6c2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151130291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1151130291
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.382712243
Short name T158
Test name
Test status
Simulation time 66695632 ps
CPU time 0.78 seconds
Started May 07 12:35:17 PM PDT 24
Finished May 07 12:35:20 PM PDT 24
Peak memory 200464 kb
Host smart-22e38e7b-c3b8-44bc-8cfa-8a2aecbdaede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382712243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.382712243
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1993290301
Short name T259
Test name
Test status
Simulation time 1897205335 ps
CPU time 7.27 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:16 PM PDT 24
Peak memory 222392 kb
Host smart-0921fce5-934a-4f49-9358-d4a626bcea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993290301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1993290301
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1626436828
Short name T459
Test name
Test status
Simulation time 244167209 ps
CPU time 1.08 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:10 PM PDT 24
Peak memory 217856 kb
Host smart-68612123-bf82-4ff1-ab0a-906685b30f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626436828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1626436828
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1451946932
Short name T210
Test name
Test status
Simulation time 97578758 ps
CPU time 0.83 seconds
Started May 07 12:35:02 PM PDT 24
Finished May 07 12:35:04 PM PDT 24
Peak memory 200528 kb
Host smart-27d5cac5-b166-46f2-924c-1177503c375d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451946932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1451946932
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3493651694
Short name T531
Test name
Test status
Simulation time 1195700449 ps
CPU time 4.73 seconds
Started May 07 12:35:06 PM PDT 24
Finished May 07 12:35:12 PM PDT 24
Peak memory 200968 kb
Host smart-79f2a9e2-2599-4575-99e0-f6b7c2b3321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493651694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3493651694
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.174888888
Short name T279
Test name
Test status
Simulation time 96996391 ps
CPU time 0.99 seconds
Started May 07 12:35:04 PM PDT 24
Finished May 07 12:35:06 PM PDT 24
Peak memory 200724 kb
Host smart-d378330c-bae6-454d-a6b0-28b523fee830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174888888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.174888888
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1675825581
Short name T192
Test name
Test status
Simulation time 114410502 ps
CPU time 1.21 seconds
Started May 07 12:35:12 PM PDT 24
Finished May 07 12:35:15 PM PDT 24
Peak memory 201020 kb
Host smart-9f6f74ac-d29e-4553-9b84-85801796ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675825581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1675825581
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3237370653
Short name T178
Test name
Test status
Simulation time 7204081593 ps
CPU time 26.68 seconds
Started May 07 12:34:51 PM PDT 24
Finished May 07 12:35:19 PM PDT 24
Peak memory 201084 kb
Host smart-2b15fe8b-1061-4b27-9a73-c76b92f2c05a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237370653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3237370653
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1365015528
Short name T251
Test name
Test status
Simulation time 133827837 ps
CPU time 1.58 seconds
Started May 07 12:35:18 PM PDT 24
Finished May 07 12:35:21 PM PDT 24
Peak memory 209056 kb
Host smart-553a6fb1-a9c2-4df2-b549-84f727a70c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365015528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1365015528
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3150200070
Short name T442
Test name
Test status
Simulation time 103656755 ps
CPU time 0.93 seconds
Started May 07 12:34:49 PM PDT 24
Finished May 07 12:34:52 PM PDT 24
Peak memory 200732 kb
Host smart-1c1a8ddb-254c-4137-8d39-b6468bbcafab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150200070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3150200070
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2562379096
Short name T300
Test name
Test status
Simulation time 80317536 ps
CPU time 0.87 seconds
Started May 07 12:35:10 PM PDT 24
Finished May 07 12:35:12 PM PDT 24
Peak memory 200640 kb
Host smart-b8419c9f-91f0-416f-ab57-453ba49edd99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562379096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2562379096
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2114774296
Short name T326
Test name
Test status
Simulation time 244499286 ps
CPU time 1.12 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:10 PM PDT 24
Peak memory 217984 kb
Host smart-ec7cae7f-a827-46e0-a7a4-e44ddafcb44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114774296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2114774296
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3718879834
Short name T98
Test name
Test status
Simulation time 771499707 ps
CPU time 3.7 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:12 PM PDT 24
Peak memory 200936 kb
Host smart-75e001a9-c729-4da8-948c-69b62bea2ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718879834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3718879834
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3526092543
Short name T62
Test name
Test status
Simulation time 9792815257 ps
CPU time 15.2 seconds
Started May 07 12:35:18 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 217568 kb
Host smart-b6557a1a-6b29-4941-8c3e-f04b2190485f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526092543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3526092543
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.417254094
Short name T286
Test name
Test status
Simulation time 157278116 ps
CPU time 1.21 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:22 PM PDT 24
Peak memory 200812 kb
Host smart-bfe456fa-3048-45ea-ae4e-be53d7a3e2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417254094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.417254094
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3002769408
Short name T344
Test name
Test status
Simulation time 119613944 ps
CPU time 1.22 seconds
Started May 07 12:35:12 PM PDT 24
Finished May 07 12:35:16 PM PDT 24
Peak memory 200928 kb
Host smart-38094da4-4f72-4d1f-b498-83a1b44c008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002769408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3002769408
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1530311106
Short name T107
Test name
Test status
Simulation time 11548573184 ps
CPU time 44.49 seconds
Started May 07 12:35:09 PM PDT 24
Finished May 07 12:35:55 PM PDT 24
Peak memory 201044 kb
Host smart-4f4c3ecd-7bc7-4339-b294-4903108806a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530311106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1530311106
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1991090861
Short name T444
Test name
Test status
Simulation time 504651664 ps
CPU time 2.74 seconds
Started May 07 12:35:13 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 200684 kb
Host smart-839789b5-f8ca-4958-b2b0-3b66ad8f6089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991090861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1991090861
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1766244756
Short name T527
Test name
Test status
Simulation time 182773692 ps
CPU time 1.19 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:22 PM PDT 24
Peak memory 200728 kb
Host smart-a0c1d677-98a5-4390-91b0-81cd91e855d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766244756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1766244756
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.331628827
Short name T543
Test name
Test status
Simulation time 71190324 ps
CPU time 0.8 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 200880 kb
Host smart-99cf92a9-fa5d-4575-ada8-e2ac6fbc6f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331628827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.331628827
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2011881839
Short name T466
Test name
Test status
Simulation time 1229287979 ps
CPU time 5.56 seconds
Started May 07 12:35:23 PM PDT 24
Finished May 07 12:35:30 PM PDT 24
Peak memory 218472 kb
Host smart-013fae7e-9363-43ea-849f-c4289598240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011881839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2011881839
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.295798012
Short name T435
Test name
Test status
Simulation time 243956802 ps
CPU time 1.06 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:22 PM PDT 24
Peak memory 217944 kb
Host smart-f750ed56-8648-4dcf-ab3c-968594c7bfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295798012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.295798012
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.861885977
Short name T18
Test name
Test status
Simulation time 198325249 ps
CPU time 0.93 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:32 PM PDT 24
Peak memory 200124 kb
Host smart-acd22c9f-514b-45ca-9d17-ec42411d876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861885977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.861885977
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3175513219
Short name T476
Test name
Test status
Simulation time 967381040 ps
CPU time 4.73 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 201040 kb
Host smart-6cda2267-ce73-435c-b1c3-f291f69282f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175513219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3175513219
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1076968333
Short name T154
Test name
Test status
Simulation time 123708270 ps
CPU time 1.2 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200952 kb
Host smart-d698bef9-5fc0-4b03-9a3d-c72087c52e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076968333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1076968333
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3699566824
Short name T375
Test name
Test status
Simulation time 1137958863 ps
CPU time 5.45 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:33 PM PDT 24
Peak memory 200896 kb
Host smart-baa0f155-2260-4dca-bbf6-a34042b0a088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699566824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3699566824
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2446683034
Short name T539
Test name
Test status
Simulation time 474451631 ps
CPU time 2.6 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200732 kb
Host smart-f0fa8be9-326a-4f69-b8f6-50b653044435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446683034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2446683034
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3110909193
Short name T312
Test name
Test status
Simulation time 97075888 ps
CPU time 0.87 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 200800 kb
Host smart-064aaa7d-c9cc-40b2-92bc-0073524fde6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110909193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3110909193
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2052077155
Short name T430
Test name
Test status
Simulation time 81955445 ps
CPU time 0.78 seconds
Started May 07 12:35:34 PM PDT 24
Finished May 07 12:35:39 PM PDT 24
Peak memory 200552 kb
Host smart-67a3699c-7d77-4ae9-8bf4-6b8cb6f2593f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052077155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2052077155
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3495161111
Short name T39
Test name
Test status
Simulation time 1229120260 ps
CPU time 5.69 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 230612 kb
Host smart-49737b84-34ee-4343-8fa5-e89412371c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495161111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3495161111
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.958510489
Short name T174
Test name
Test status
Simulation time 244166837 ps
CPU time 1.06 seconds
Started May 07 12:35:33 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 217960 kb
Host smart-947db6ec-dd35-418e-abce-48a4baa42a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958510489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.958510489
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3657727773
Short name T342
Test name
Test status
Simulation time 172694820 ps
CPU time 0.88 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:32 PM PDT 24
Peak memory 200544 kb
Host smart-e2f6f656-392b-4015-973f-db0b9823504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657727773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3657727773
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1542857970
Short name T482
Test name
Test status
Simulation time 738528430 ps
CPU time 4.07 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 201004 kb
Host smart-4c09281f-cb4c-458d-aa83-c18843a4da55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542857970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1542857970
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2842770508
Short name T504
Test name
Test status
Simulation time 104863361 ps
CPU time 1.01 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 200696 kb
Host smart-429cfce0-f400-47b4-8de1-73e508438104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842770508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2842770508
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2761965786
Short name T353
Test name
Test status
Simulation time 121497173 ps
CPU time 1.2 seconds
Started May 07 12:35:36 PM PDT 24
Finished May 07 12:35:40 PM PDT 24
Peak memory 200984 kb
Host smart-f070ce76-1a63-4d7d-a2b4-e7daf69b6927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761965786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2761965786
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.158347965
Short name T313
Test name
Test status
Simulation time 6798260960 ps
CPU time 24.76 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:56 PM PDT 24
Peak memory 201104 kb
Host smart-6edba20c-5e76-49b8-b327-80d77f379e30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158347965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.158347965
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2233056007
Short name T277
Test name
Test status
Simulation time 153868942 ps
CPU time 1.9 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200792 kb
Host smart-6a3b680e-bad7-4368-a1c6-e183bc0d315f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233056007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2233056007
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2508723702
Short name T179
Test name
Test status
Simulation time 92689033 ps
CPU time 0.89 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:30 PM PDT 24
Peak memory 200696 kb
Host smart-f869308c-22d8-401e-8397-49dbe7565418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508723702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2508723702
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4097750792
Short name T155
Test name
Test status
Simulation time 58783482 ps
CPU time 0.74 seconds
Started May 07 12:35:37 PM PDT 24
Finished May 07 12:35:40 PM PDT 24
Peak memory 200492 kb
Host smart-ff6e8737-53a7-41f2-89e7-71af41c2e36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097750792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4097750792
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.581174964
Short name T49
Test name
Test status
Simulation time 2363333033 ps
CPU time 7.91 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 222496 kb
Host smart-bcfeb9bb-d3f3-4e4b-8f03-51104d209f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581174964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.581174964
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3776148589
Short name T191
Test name
Test status
Simulation time 243953304 ps
CPU time 1.04 seconds
Started May 07 12:35:23 PM PDT 24
Finished May 07 12:35:26 PM PDT 24
Peak memory 217884 kb
Host smart-7f2f07e8-8cb5-4bd6-93ee-f1c33beba2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776148589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3776148589
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1157688285
Short name T206
Test name
Test status
Simulation time 161445153 ps
CPU time 0.9 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:28 PM PDT 24
Peak memory 200628 kb
Host smart-61b2aa59-0655-4e1d-8d3d-0653f9bc0384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157688285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1157688285
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.946414547
Short name T437
Test name
Test status
Simulation time 818610877 ps
CPU time 4.22 seconds
Started May 07 12:35:40 PM PDT 24
Finished May 07 12:35:45 PM PDT 24
Peak memory 200636 kb
Host smart-023fb890-9ee4-40bf-8e5f-d3cb0d276816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946414547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.946414547
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1435723158
Short name T262
Test name
Test status
Simulation time 101739725 ps
CPU time 0.99 seconds
Started May 07 12:35:39 PM PDT 24
Finished May 07 12:35:41 PM PDT 24
Peak memory 200808 kb
Host smart-2e25503b-9af7-44eb-84ea-091ced7dd5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435723158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1435723158
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3916996109
Short name T85
Test name
Test status
Simulation time 199497108 ps
CPU time 1.3 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:29 PM PDT 24
Peak memory 200876 kb
Host smart-75072f18-98a5-4ad9-ab1e-9a0e088b03b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916996109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3916996109
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.777656969
Short name T213
Test name
Test status
Simulation time 5916582633 ps
CPU time 21.47 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 209316 kb
Host smart-2bee1296-6e3b-4b56-a87c-bb73ea667ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777656969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.777656969
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3786805522
Short name T307
Test name
Test status
Simulation time 308082708 ps
CPU time 2.03 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 200800 kb
Host smart-fbad93f3-a522-4955-ba83-8ff0fdfdae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786805522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3786805522
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2313174314
Short name T1
Test name
Test status
Simulation time 123529652 ps
CPU time 1.08 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:29 PM PDT 24
Peak memory 200816 kb
Host smart-43000904-632e-4c3f-9a57-73227e55b6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313174314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2313174314
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3443991890
Short name T101
Test name
Test status
Simulation time 76772145 ps
CPU time 0.82 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:29 PM PDT 24
Peak memory 200644 kb
Host smart-4157aeac-4269-4f5b-b0ff-1c6ea85376e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443991890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3443991890
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3955575540
Short name T272
Test name
Test status
Simulation time 245407990 ps
CPU time 1.01 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:29 PM PDT 24
Peak memory 217960 kb
Host smart-4e1bef82-b7e1-4300-99c7-15cbe5abdc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955575540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3955575540
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1212630030
Short name T24
Test name
Test status
Simulation time 184575406 ps
CPU time 0.89 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:30 PM PDT 24
Peak memory 200528 kb
Host smart-e5638a83-15dd-46f3-948d-9d44de374c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212630030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1212630030
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1238206827
Short name T433
Test name
Test status
Simulation time 964289329 ps
CPU time 4.61 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200984 kb
Host smart-eeb68ba9-df78-4017-9239-d4c088dadb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238206827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1238206827
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1389563749
Short name T483
Test name
Test status
Simulation time 94863388 ps
CPU time 0.97 seconds
Started May 07 12:35:23 PM PDT 24
Finished May 07 12:35:27 PM PDT 24
Peak memory 200704 kb
Host smart-981e8934-547e-460c-93c7-858ba082f45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389563749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1389563749
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1929221064
Short name T254
Test name
Test status
Simulation time 199576762 ps
CPU time 1.31 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 200988 kb
Host smart-2368193a-fd68-4bff-b476-a4bc3dd018b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929221064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1929221064
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1553784220
Short name T77
Test name
Test status
Simulation time 3965605012 ps
CPU time 17.16 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:49 PM PDT 24
Peak memory 209236 kb
Host smart-f0a14c8d-0319-49cc-b660-6a8faf1ccd51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553784220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1553784220
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.744432117
Short name T256
Test name
Test status
Simulation time 372824641 ps
CPU time 2.34 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:32 PM PDT 24
Peak memory 200684 kb
Host smart-461b0f60-2f9c-4169-928c-c3db06ba0f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744432117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.744432117
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3810346052
Short name T520
Test name
Test status
Simulation time 128404286 ps
CPU time 0.98 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:30 PM PDT 24
Peak memory 200812 kb
Host smart-e7b197b6-555f-42e4-a555-133633773e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810346052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3810346052
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.4049978840
Short name T167
Test name
Test status
Simulation time 64779734 ps
CPU time 0.74 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200596 kb
Host smart-df98aab6-97c7-41c9-a8b5-faae94dd694a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049978840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.4049978840
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1876318401
Short name T194
Test name
Test status
Simulation time 2166469239 ps
CPU time 7.76 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 222496 kb
Host smart-a58754db-2d40-4b23-bb15-3c8dbbe0c6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876318401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1876318401
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3391995480
Short name T175
Test name
Test status
Simulation time 243740153 ps
CPU time 1.18 seconds
Started May 07 12:35:40 PM PDT 24
Finished May 07 12:35:42 PM PDT 24
Peak memory 217940 kb
Host smart-85f3dbd2-9b99-4a28-83dd-f0decbcb60b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391995480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3391995480
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1234328107
Short name T421
Test name
Test status
Simulation time 211157935 ps
CPU time 1.01 seconds
Started May 07 12:35:22 PM PDT 24
Finished May 07 12:35:25 PM PDT 24
Peak memory 200552 kb
Host smart-735d4cfe-1352-4a78-848d-4668bb4856c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234328107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1234328107
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3242327557
Short name T364
Test name
Test status
Simulation time 682823919 ps
CPU time 3.55 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:32 PM PDT 24
Peak memory 200940 kb
Host smart-6ddaf6a6-a88f-44f9-a916-70bda6eaf830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242327557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3242327557
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.251095001
Short name T141
Test name
Test status
Simulation time 146277154 ps
CPU time 1.08 seconds
Started May 07 12:35:20 PM PDT 24
Finished May 07 12:35:23 PM PDT 24
Peak memory 200788 kb
Host smart-adeaa53e-5e11-45f5-9399-f8f907eda28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251095001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.251095001
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3871130753
Short name T534
Test name
Test status
Simulation time 110240788 ps
CPU time 1.15 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:29 PM PDT 24
Peak memory 200996 kb
Host smart-1b2795dc-4947-4b4b-b308-fab07f2822af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871130753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3871130753
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1219828379
Short name T501
Test name
Test status
Simulation time 9873975379 ps
CPU time 34 seconds
Started May 07 12:35:45 PM PDT 24
Finished May 07 12:36:20 PM PDT 24
Peak memory 209244 kb
Host smart-d7f60858-d570-4bf6-a6ce-cb88d86a12db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219828379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1219828379
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.533450464
Short name T208
Test name
Test status
Simulation time 385941675 ps
CPU time 2.43 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:24 PM PDT 24
Peak memory 200740 kb
Host smart-4bc39b0d-3a80-4212-a476-ff621dd1762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533450464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.533450464
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.31625076
Short name T392
Test name
Test status
Simulation time 176206900 ps
CPU time 1.12 seconds
Started May 07 12:35:23 PM PDT 24
Finished May 07 12:35:27 PM PDT 24
Peak memory 200752 kb
Host smart-033029a8-1edf-4037-ad2d-0d00c98cd7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31625076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.31625076
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.278291729
Short name T464
Test name
Test status
Simulation time 80872276 ps
CPU time 0.83 seconds
Started May 07 12:35:33 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200132 kb
Host smart-223802cf-a531-42f8-8c19-e1fffa155d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278291729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.278291729
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2085721409
Short name T480
Test name
Test status
Simulation time 1894305947 ps
CPU time 8.06 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:44 PM PDT 24
Peak memory 217892 kb
Host smart-19b880c8-4d9d-415c-abde-a3f9d8bda8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085721409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2085721409
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.447421693
Short name T387
Test name
Test status
Simulation time 244027892 ps
CPU time 1.14 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:28 PM PDT 24
Peak memory 217880 kb
Host smart-c8da4916-2f27-4b4e-845a-eb5fe2e00b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447421693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.447421693
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.846328218
Short name T397
Test name
Test status
Simulation time 99830637 ps
CPU time 0.74 seconds
Started May 07 12:35:33 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200624 kb
Host smart-868d110a-4029-4b39-9c39-b482fa5482bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846328218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.846328218
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3341206625
Short name T362
Test name
Test status
Simulation time 942571596 ps
CPU time 4.73 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:39 PM PDT 24
Peak memory 200928 kb
Host smart-96b65e48-2902-4a65-baf3-bb08c5c63d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341206625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3341206625
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1298779814
Short name T170
Test name
Test status
Simulation time 147407963 ps
CPU time 1.16 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200808 kb
Host smart-722b7dc8-566a-4dff-aa33-598c8a78b0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298779814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1298779814
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.180247845
Short name T188
Test name
Test status
Simulation time 193815668 ps
CPU time 1.39 seconds
Started May 07 12:35:31 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 201024 kb
Host smart-972bc162-a961-4f0f-9507-10b49de52464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180247845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.180247845
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.356189863
Short name T270
Test name
Test status
Simulation time 7313747885 ps
CPU time 24.7 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:57 PM PDT 24
Peak memory 201084 kb
Host smart-421cd542-3c20-48f6-9f16-a6b9fc32764c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356189863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.356189863
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2270825895
Short name T458
Test name
Test status
Simulation time 384788986 ps
CPU time 2.25 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 208884 kb
Host smart-1bc3c035-fda8-4fd7-955d-95962ed17880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270825895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2270825895
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1047941793
Short name T152
Test name
Test status
Simulation time 117824202 ps
CPU time 0.92 seconds
Started May 07 12:35:35 PM PDT 24
Finished May 07 12:35:39 PM PDT 24
Peak memory 200804 kb
Host smart-92333656-2d94-444b-8dcb-8beb762e6d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047941793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1047941793
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1091500017
Short name T236
Test name
Test status
Simulation time 1227421651 ps
CPU time 5.66 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:33 PM PDT 24
Peak memory 222436 kb
Host smart-7427e83a-7b5a-493d-a6fc-f5b0d9ef7604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091500017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1091500017
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2628732043
Short name T386
Test name
Test status
Simulation time 244568335 ps
CPU time 1.11 seconds
Started May 07 12:35:39 PM PDT 24
Finished May 07 12:35:42 PM PDT 24
Peak memory 217944 kb
Host smart-ffeba807-e861-4fa4-a3b2-392b305bb4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628732043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2628732043
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2166699237
Short name T462
Test name
Test status
Simulation time 219792239 ps
CPU time 0.93 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:33 PM PDT 24
Peak memory 200628 kb
Host smart-bee1a91f-89a3-4897-b5e0-814edb86a563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166699237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2166699237
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1985799958
Short name T417
Test name
Test status
Simulation time 1537302200 ps
CPU time 5.38 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200940 kb
Host smart-4be3a4ec-664d-456f-bc84-23e4a0bfef12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985799958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1985799958
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1617988846
Short name T515
Test name
Test status
Simulation time 146067372 ps
CPU time 1.13 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200780 kb
Host smart-7776ed99-ef89-4d91-8d92-0a245a799f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617988846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1617988846
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.424800639
Short name T145
Test name
Test status
Simulation time 197372937 ps
CPU time 1.34 seconds
Started May 07 12:35:35 PM PDT 24
Finished May 07 12:35:40 PM PDT 24
Peak memory 200976 kb
Host smart-4b6a6289-f2ee-4525-b794-21d37e219b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424800639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.424800639
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2725668263
Short name T425
Test name
Test status
Simulation time 9347355619 ps
CPU time 33.76 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:36:06 PM PDT 24
Peak memory 209348 kb
Host smart-33d70b1b-7a3a-45f9-be64-7db040648413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725668263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2725668263
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1739762173
Short name T246
Test name
Test status
Simulation time 277334078 ps
CPU time 1.9 seconds
Started May 07 12:35:44 PM PDT 24
Finished May 07 12:35:47 PM PDT 24
Peak memory 200788 kb
Host smart-a6231c01-de29-4b4e-a4e7-7ed562588bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739762173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1739762173
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.787229438
Short name T222
Test name
Test status
Simulation time 141159899 ps
CPU time 1.12 seconds
Started May 07 12:35:33 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200812 kb
Host smart-3666e353-6ff3-4d83-8ed3-0d13bab6f577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787229438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.787229438
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2632169719
Short name T255
Test name
Test status
Simulation time 61233212 ps
CPU time 0.76 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:30 PM PDT 24
Peak memory 200660 kb
Host smart-1f63daca-c089-49d3-9c22-4c01c521a5f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632169719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2632169719
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.131891963
Short name T404
Test name
Test status
Simulation time 1899956483 ps
CPU time 7.28 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 230124 kb
Host smart-04be6cd5-e382-45fe-9eb5-6da71814b2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131891963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.131891963
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1465813933
Short name T487
Test name
Test status
Simulation time 243999956 ps
CPU time 1.07 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 217892 kb
Host smart-8a58abcb-d08d-442f-b884-c241b3c19c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465813933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1465813933
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3510501569
Short name T394
Test name
Test status
Simulation time 144323019 ps
CPU time 0.82 seconds
Started May 07 12:35:33 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200572 kb
Host smart-acaf8774-daf5-4d23-a723-fdf74f906f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510501569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3510501569
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.4258850360
Short name T419
Test name
Test status
Simulation time 967369523 ps
CPU time 4.63 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200900 kb
Host smart-e6970e2e-59d6-4845-b08b-3cda50c3e6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258850360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4258850360
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2273362364
Short name T207
Test name
Test status
Simulation time 100162871 ps
CPU time 1.05 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 200832 kb
Host smart-9cca3d3f-b688-4185-b0d2-ca5690683bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273362364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2273362364
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3540322403
Short name T457
Test name
Test status
Simulation time 201606331 ps
CPU time 1.34 seconds
Started May 07 12:35:35 PM PDT 24
Finished May 07 12:35:40 PM PDT 24
Peak memory 200944 kb
Host smart-7c49c17c-9dc5-4055-908f-70801da107a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540322403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3540322403
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1727083637
Short name T69
Test name
Test status
Simulation time 1311123578 ps
CPU time 5.69 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:42 PM PDT 24
Peak memory 200912 kb
Host smart-762df79f-d68c-46e1-9126-0dc50cf566d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727083637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1727083637
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1211948517
Short name T163
Test name
Test status
Simulation time 112616474 ps
CPU time 1.42 seconds
Started May 07 12:35:36 PM PDT 24
Finished May 07 12:35:41 PM PDT 24
Peak memory 200792 kb
Host smart-ed3a6c57-9533-42db-93f7-cbb4c38c66fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211948517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1211948517
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.526942144
Short name T303
Test name
Test status
Simulation time 92611336 ps
CPU time 0.95 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200728 kb
Host smart-4129312c-73f6-4a02-ad20-359fa2297887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526942144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.526942144
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2537294966
Short name T516
Test name
Test status
Simulation time 92535432 ps
CPU time 0.83 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 200544 kb
Host smart-ceae6984-29cb-4e98-bf2c-3d21029a802e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537294966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2537294966
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.4101994574
Short name T389
Test name
Test status
Simulation time 1898804898 ps
CPU time 6.86 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:40 PM PDT 24
Peak memory 218364 kb
Host smart-3edf9221-4f82-4d48-b29d-208587f3f75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101994574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.4101994574
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.441281711
Short name T29
Test name
Test status
Simulation time 244151793 ps
CPU time 1.11 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 218116 kb
Host smart-0d933559-6850-4547-aabf-4665a182c3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441281711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.441281711
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.4084094036
Short name T369
Test name
Test status
Simulation time 209292098 ps
CPU time 0.96 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 200608 kb
Host smart-b5713a43-c585-4f9c-ba90-ce9a581ee708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084094036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.4084094036
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1601352606
Short name T75
Test name
Test status
Simulation time 1820993877 ps
CPU time 5.97 seconds
Started May 07 12:35:41 PM PDT 24
Finished May 07 12:35:48 PM PDT 24
Peak memory 200980 kb
Host smart-c7151b8a-8556-45a0-b989-2e954967cf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601352606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1601352606
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3645594022
Short name T132
Test name
Test status
Simulation time 179523164 ps
CPU time 1.16 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200688 kb
Host smart-97ebdb1a-0589-41e0-9055-e8edd8814538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645594022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3645594022
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3582164700
Short name T467
Test name
Test status
Simulation time 116105123 ps
CPU time 1.17 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200936 kb
Host smart-e293c7e0-ec90-40e6-9632-6bacf99c2604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582164700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3582164700
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1278310054
Short name T508
Test name
Test status
Simulation time 12475305698 ps
CPU time 45.6 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:36:21 PM PDT 24
Peak memory 209240 kb
Host smart-da437040-ba2c-43fb-94ac-eef42754e74b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278310054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1278310054
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2185407670
Short name T502
Test name
Test status
Simulation time 403792378 ps
CPU time 2.23 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 209024 kb
Host smart-8231d791-60ac-4766-9743-d639c2b02d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185407670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2185407670
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2240838139
Short name T278
Test name
Test status
Simulation time 222528909 ps
CPU time 1.18 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 200776 kb
Host smart-2c360c97-b2e6-43f6-bf74-7af39a90faaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240838139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2240838139
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2113790265
Short name T189
Test name
Test status
Simulation time 62235533 ps
CPU time 0.75 seconds
Started May 07 12:35:33 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200604 kb
Host smart-5a518c6b-fa1f-4417-b48a-a0fa91c2e0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113790265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2113790265
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.443361166
Short name T235
Test name
Test status
Simulation time 2347887571 ps
CPU time 7.61 seconds
Started May 07 12:35:42 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 218588 kb
Host smart-055200a3-fc0c-48b6-b3c8-0726f84a348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443361166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.443361166
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.297954107
Short name T528
Test name
Test status
Simulation time 245409186 ps
CPU time 1.07 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 217876 kb
Host smart-03140b30-6b92-44ea-82c7-f8967981d0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297954107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.297954107
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2055721267
Short name T521
Test name
Test status
Simulation time 218616555 ps
CPU time 1.01 seconds
Started May 07 12:35:43 PM PDT 24
Finished May 07 12:35:44 PM PDT 24
Peak memory 200584 kb
Host smart-78b57bb1-5955-40a2-b954-c495b45c359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055721267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2055721267
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2003552813
Short name T242
Test name
Test status
Simulation time 819247491 ps
CPU time 4.07 seconds
Started May 07 12:35:45 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 200948 kb
Host smart-e182125c-76e3-40ae-aaf5-d3ca6fc10394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003552813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2003552813
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1410369458
Short name T244
Test name
Test status
Simulation time 102315712 ps
CPU time 0.98 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 200720 kb
Host smart-1732ad1b-30b4-4f75-861d-13b6a8cecd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410369458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1410369458
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.650795921
Short name T496
Test name
Test status
Simulation time 257414433 ps
CPU time 1.37 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 200872 kb
Host smart-7f481eda-7ddc-4033-855f-a85b72a651e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650795921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.650795921
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4227649189
Short name T166
Test name
Test status
Simulation time 155066882 ps
CPU time 1.97 seconds
Started May 07 12:35:42 PM PDT 24
Finished May 07 12:35:45 PM PDT 24
Peak memory 200740 kb
Host smart-a85112ec-3ea6-42ee-8c8a-2c990aa8859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227649189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4227649189
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3364644599
Short name T350
Test name
Test status
Simulation time 101491569 ps
CPU time 0.83 seconds
Started May 07 12:35:22 PM PDT 24
Finished May 07 12:35:24 PM PDT 24
Peak memory 200524 kb
Host smart-f57d07cd-b99b-4d3e-b87d-0b588b26f554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364644599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3364644599
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3021298852
Short name T275
Test name
Test status
Simulation time 1226911519 ps
CPU time 5.49 seconds
Started May 07 12:35:15 PM PDT 24
Finished May 07 12:35:22 PM PDT 24
Peak memory 217828 kb
Host smart-00b939c0-d57c-4a55-90e0-80c4f8b7d574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021298852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3021298852
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1529548235
Short name T370
Test name
Test status
Simulation time 244242118 ps
CPU time 1.09 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:22 PM PDT 24
Peak memory 217828 kb
Host smart-890aed4b-03a5-401e-8ac7-a7d3e253ff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529548235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1529548235
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1855165954
Short name T238
Test name
Test status
Simulation time 121612011 ps
CPU time 0.8 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:28 PM PDT 24
Peak memory 200528 kb
Host smart-519ceae1-80b4-4299-b729-97cab4975d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855165954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1855165954
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3497016585
Short name T357
Test name
Test status
Simulation time 1043947785 ps
CPU time 4.55 seconds
Started May 07 12:35:20 PM PDT 24
Finished May 07 12:35:26 PM PDT 24
Peak memory 200880 kb
Host smart-01b07f0c-b8fa-4ab5-ac27-14528671dcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497016585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3497016585
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2633747559
Short name T65
Test name
Test status
Simulation time 8290310819 ps
CPU time 16.14 seconds
Started May 07 12:35:10 PM PDT 24
Finished May 07 12:35:28 PM PDT 24
Peak memory 217676 kb
Host smart-1e78c8e7-dc37-4fb7-95ac-ea598a48a620
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633747559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2633747559
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.635752896
Short name T522
Test name
Test status
Simulation time 110993859 ps
CPU time 0.99 seconds
Started May 07 12:35:10 PM PDT 24
Finished May 07 12:35:13 PM PDT 24
Peak memory 200748 kb
Host smart-5d179f9f-940b-4f7a-90d9-fc07cfe6200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635752896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.635752896
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2491131723
Short name T150
Test name
Test status
Simulation time 122688731 ps
CPU time 1.24 seconds
Started May 07 12:35:17 PM PDT 24
Finished May 07 12:35:20 PM PDT 24
Peak memory 200984 kb
Host smart-8026eeba-9429-4df5-ae1f-5f32be842887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491131723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2491131723
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1409793288
Short name T103
Test name
Test status
Simulation time 7250708891 ps
CPU time 24.83 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 201068 kb
Host smart-06d8098b-1132-41b0-bee3-817d63545c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409793288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1409793288
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3371717613
Short name T11
Test name
Test status
Simulation time 460538636 ps
CPU time 2.68 seconds
Started May 07 12:35:12 PM PDT 24
Finished May 07 12:35:17 PM PDT 24
Peak memory 200304 kb
Host smart-e397e8dd-cd49-441c-a1f1-29a29ac20728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371717613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3371717613
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1565608903
Short name T180
Test name
Test status
Simulation time 106830387 ps
CPU time 1.06 seconds
Started May 07 12:35:12 PM PDT 24
Finished May 07 12:35:15 PM PDT 24
Peak memory 200816 kb
Host smart-6c385829-3f10-4f00-b1a3-22b065738efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565608903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1565608903
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2728255175
Short name T514
Test name
Test status
Simulation time 73497079 ps
CPU time 0.81 seconds
Started May 07 12:35:33 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200552 kb
Host smart-afb9c9c5-d927-47fd-be85-c3f0c5e27507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728255175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2728255175
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.134485461
Short name T42
Test name
Test status
Simulation time 1891163592 ps
CPU time 7.22 seconds
Started May 07 12:35:37 PM PDT 24
Finished May 07 12:35:47 PM PDT 24
Peak memory 222392 kb
Host smart-ffb5e38c-38d2-4a0d-8cc4-97af153ba6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134485461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.134485461
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1583650664
Short name T268
Test name
Test status
Simulation time 244248416 ps
CPU time 1.14 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:30 PM PDT 24
Peak memory 217956 kb
Host smart-ec1e6e48-2edb-42e3-87e0-29a7069571f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583650664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1583650664
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.4045760532
Short name T329
Test name
Test status
Simulation time 171541577 ps
CPU time 0.87 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 200544 kb
Host smart-e4f4b3ef-d664-47d2-9d08-899e2edd0470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045760532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4045760532
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.85769954
Short name T321
Test name
Test status
Simulation time 110201784 ps
CPU time 1.01 seconds
Started May 07 12:35:36 PM PDT 24
Finished May 07 12:35:40 PM PDT 24
Peak memory 200784 kb
Host smart-ceee276e-08d3-4d57-9f09-e9ecb1698f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85769954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.85769954
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3918871539
Short name T82
Test name
Test status
Simulation time 207708463 ps
CPU time 1.31 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200764 kb
Host smart-d235eb37-2046-449e-94dc-412a34b1d335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918871539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3918871539
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3209674337
Short name T193
Test name
Test status
Simulation time 2995719456 ps
CPU time 13.16 seconds
Started May 07 12:35:36 PM PDT 24
Finished May 07 12:35:52 PM PDT 24
Peak memory 201036 kb
Host smart-4b5e2d69-cb5b-48f9-a7ba-87f3eb5d639f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209674337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3209674337
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3127072834
Short name T451
Test name
Test status
Simulation time 132025716 ps
CPU time 1.52 seconds
Started May 07 12:35:34 PM PDT 24
Finished May 07 12:35:40 PM PDT 24
Peak memory 208940 kb
Host smart-544ca6c3-c9e9-4362-8563-3a7169f12a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127072834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3127072834
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1157211617
Short name T431
Test name
Test status
Simulation time 107206137 ps
CPU time 1.01 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:33 PM PDT 24
Peak memory 200720 kb
Host smart-e2e1ab25-bca1-4f20-9b4d-1e3875a8b35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157211617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1157211617
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2399463299
Short name T31
Test name
Test status
Simulation time 72522673 ps
CPU time 0.73 seconds
Started May 07 12:35:31 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 200556 kb
Host smart-84af6c07-2836-4cbf-97c2-e60a622d4640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399463299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2399463299
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2400200430
Short name T443
Test name
Test status
Simulation time 2368182910 ps
CPU time 8.14 seconds
Started May 07 12:35:41 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 218576 kb
Host smart-d7b92ea8-bd60-483e-9dd0-30153b50eb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400200430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2400200430
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1666635462
Short name T14
Test name
Test status
Simulation time 243443295 ps
CPU time 1.2 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 218036 kb
Host smart-1a7a6973-c3f1-46ea-83bf-9cda9fecffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666635462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1666635462
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2793586018
Short name T209
Test name
Test status
Simulation time 232994036 ps
CPU time 0.97 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 200544 kb
Host smart-a6fecc23-319c-47f8-bd86-fff7fff6e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793586018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2793586018
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2331112891
Short name T215
Test name
Test status
Simulation time 1408295473 ps
CPU time 5.27 seconds
Started May 07 12:35:40 PM PDT 24
Finished May 07 12:35:46 PM PDT 24
Peak memory 201016 kb
Host smart-f08ea3fa-403d-413a-b65e-48eccee389d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331112891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2331112891
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.496054277
Short name T363
Test name
Test status
Simulation time 170782274 ps
CPU time 1.19 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:51 PM PDT 24
Peak memory 200860 kb
Host smart-ba4d3253-b9fe-40de-90a8-bf409438f620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496054277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.496054277
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3779440239
Short name T173
Test name
Test status
Simulation time 121986260 ps
CPU time 1.19 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 200988 kb
Host smart-8625d448-7dec-47ff-9a69-53157cad4aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779440239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3779440239
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2540232394
Short name T130
Test name
Test status
Simulation time 4416278485 ps
CPU time 15.01 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:48 PM PDT 24
Peak memory 201076 kb
Host smart-9c3cdbd6-cdec-480b-9871-53c707bacaba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540232394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2540232394
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.53695682
Short name T223
Test name
Test status
Simulation time 265621894 ps
CPU time 1.79 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 200688 kb
Host smart-ad684c7c-e0aa-4db7-9996-5d60cbb953d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53695682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.53695682
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1200077828
Short name T134
Test name
Test status
Simulation time 65647640 ps
CPU time 0.76 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 200800 kb
Host smart-f343b641-bf10-4a51-9aa1-d2e7f3a2af73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200077828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1200077828
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3102368583
Short name T280
Test name
Test status
Simulation time 93373920 ps
CPU time 0.88 seconds
Started May 07 12:35:33 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 200552 kb
Host smart-51918d1d-195a-4fab-8cf2-f19bc6628c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102368583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3102368583
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.4262258921
Short name T354
Test name
Test status
Simulation time 1239716582 ps
CPU time 5.5 seconds
Started May 07 12:35:36 PM PDT 24
Finished May 07 12:35:45 PM PDT 24
Peak memory 230660 kb
Host smart-8c09753f-7ebc-44b5-a3ed-0a08f89abadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262258921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4262258921
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1107612976
Short name T196
Test name
Test status
Simulation time 244191168 ps
CPU time 1.1 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 217872 kb
Host smart-f1de7ef3-2743-4f29-967b-6886aa5c99ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107612976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1107612976
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4273922444
Short name T358
Test name
Test status
Simulation time 196747865 ps
CPU time 0.88 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:35:48 PM PDT 24
Peak memory 200612 kb
Host smart-70a8b633-1f48-453c-bf6f-c697943bc311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273922444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4273922444
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3131621712
Short name T359
Test name
Test status
Simulation time 1441075556 ps
CPU time 5.17 seconds
Started May 07 12:35:43 PM PDT 24
Finished May 07 12:35:54 PM PDT 24
Peak memory 201048 kb
Host smart-f0e8bdbd-e13c-4c91-b746-0fee194ae5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131621712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3131621712
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1511396233
Short name T71
Test name
Test status
Simulation time 95780979 ps
CPU time 1.04 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 201064 kb
Host smart-15bf16dd-1a88-4097-8707-bc1de673413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511396233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1511396233
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1846186141
Short name T418
Test name
Test status
Simulation time 233621797 ps
CPU time 1.42 seconds
Started May 07 12:35:31 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 200900 kb
Host smart-35a798bb-dc1e-438c-b1f1-eac72fb666dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846186141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1846186141
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.393202793
Short name T105
Test name
Test status
Simulation time 3408142494 ps
CPU time 12.97 seconds
Started May 07 12:35:31 PM PDT 24
Finished May 07 12:35:49 PM PDT 24
Peak memory 201076 kb
Host smart-b4a0bb87-89a2-4a96-b757-4fb6b8ef9240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393202793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.393202793
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3484863025
Short name T434
Test name
Test status
Simulation time 388824655 ps
CPU time 2.66 seconds
Started May 07 12:35:56 PM PDT 24
Finished May 07 12:36:00 PM PDT 24
Peak memory 200704 kb
Host smart-43afe14e-3858-4e70-8e18-41a3f2f8e723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484863025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3484863025
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.4289958147
Short name T241
Test name
Test status
Simulation time 70734405 ps
CPU time 0.83 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:32 PM PDT 24
Peak memory 200712 kb
Host smart-89bcac7a-9947-4c32-8486-49632ef612a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289958147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.4289958147
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.263247618
Short name T228
Test name
Test status
Simulation time 67956535 ps
CPU time 0.76 seconds
Started May 07 12:35:57 PM PDT 24
Finished May 07 12:35:59 PM PDT 24
Peak memory 200648 kb
Host smart-5fc67431-4341-4b22-84bd-db2ce44ae9ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263247618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.263247618
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.4277625642
Short name T468
Test name
Test status
Simulation time 2155758640 ps
CPU time 8.05 seconds
Started May 07 12:36:04 PM PDT 24
Finished May 07 12:36:13 PM PDT 24
Peak memory 222508 kb
Host smart-9e234e40-3820-4579-9694-850e5f7708bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277625642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.4277625642
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1972645170
Short name T481
Test name
Test status
Simulation time 261413541 ps
CPU time 1.11 seconds
Started May 07 12:35:31 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 217872 kb
Host smart-a37589b1-6787-48ff-9363-2a90594f1c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972645170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1972645170
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2553028151
Short name T21
Test name
Test status
Simulation time 154622521 ps
CPU time 0.87 seconds
Started May 07 12:35:38 PM PDT 24
Finished May 07 12:35:41 PM PDT 24
Peak memory 200548 kb
Host smart-caec8ead-7293-430d-aa7a-27bdc95233ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553028151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2553028151
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2677504891
Short name T477
Test name
Test status
Simulation time 675920240 ps
CPU time 3.8 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:33 PM PDT 24
Peak memory 200916 kb
Host smart-66b583fe-a234-4e08-8eb7-cb78fde8c1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677504891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2677504891
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3905444791
Short name T169
Test name
Test status
Simulation time 176249783 ps
CPU time 1.16 seconds
Started May 07 12:35:52 PM PDT 24
Finished May 07 12:35:54 PM PDT 24
Peak memory 200832 kb
Host smart-dc978e8c-1034-4dc9-b373-3147ed97ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905444791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3905444791
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1100677259
Short name T153
Test name
Test status
Simulation time 128665122 ps
CPU time 1.21 seconds
Started May 07 12:35:40 PM PDT 24
Finished May 07 12:35:43 PM PDT 24
Peak memory 200928 kb
Host smart-b3dfe972-34d5-4a57-b891-606d9b9cdc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100677259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1100677259
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2541598141
Short name T225
Test name
Test status
Simulation time 1963634441 ps
CPU time 9.51 seconds
Started May 07 12:35:36 PM PDT 24
Finished May 07 12:35:49 PM PDT 24
Peak memory 209140 kb
Host smart-5992d3ff-20fc-45fc-a8a7-47b20645e0d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541598141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2541598141
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1719695635
Short name T28
Test name
Test status
Simulation time 147697315 ps
CPU time 1.84 seconds
Started May 07 12:35:39 PM PDT 24
Finished May 07 12:35:43 PM PDT 24
Peak memory 200736 kb
Host smart-87a94cb3-a4fb-42b6-a5c4-977c774eb84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719695635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1719695635
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.155998645
Short name T366
Test name
Test status
Simulation time 132696892 ps
CPU time 0.97 seconds
Started May 07 12:35:50 PM PDT 24
Finished May 07 12:35:52 PM PDT 24
Peak memory 200800 kb
Host smart-bb1cc742-3bde-42c3-aea2-8257a10e1035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155998645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.155998645
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1868863907
Short name T323
Test name
Test status
Simulation time 70897720 ps
CPU time 0.8 seconds
Started May 07 12:35:34 PM PDT 24
Finished May 07 12:35:39 PM PDT 24
Peak memory 200500 kb
Host smart-05475af5-53bc-4ac7-8e6c-a5baf29fbb11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868863907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1868863907
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3417840171
Short name T247
Test name
Test status
Simulation time 243442939 ps
CPU time 1.1 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:35:49 PM PDT 24
Peak memory 218016 kb
Host smart-791ac5ab-cd87-44d9-b20c-c20241458c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417840171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3417840171
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.798146508
Short name T74
Test name
Test status
Simulation time 102817646 ps
CPU time 0.84 seconds
Started May 07 12:36:04 PM PDT 24
Finished May 07 12:36:06 PM PDT 24
Peak memory 200636 kb
Host smart-90675ce2-c9ec-4781-86e4-f10ef45978cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798146508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.798146508
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.588060954
Short name T327
Test name
Test status
Simulation time 1928204522 ps
CPU time 7.26 seconds
Started May 07 12:35:52 PM PDT 24
Finished May 07 12:36:00 PM PDT 24
Peak memory 201012 kb
Host smart-ee87f0d9-49d1-4c48-9d03-985462221af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588060954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.588060954
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.737070403
Short name T355
Test name
Test status
Simulation time 144109903 ps
CPU time 1.14 seconds
Started May 07 12:35:57 PM PDT 24
Finished May 07 12:36:00 PM PDT 24
Peak memory 200784 kb
Host smart-13a29b05-e240-4607-bd2a-172edf325994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737070403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.737070403
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1566791799
Short name T12
Test name
Test status
Simulation time 116537443 ps
CPU time 1.13 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:52 PM PDT 24
Peak memory 200984 kb
Host smart-53c298a8-24b2-4215-a773-0400b4057f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566791799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1566791799
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3217931529
Short name T267
Test name
Test status
Simulation time 3714771442 ps
CPU time 17.01 seconds
Started May 07 12:35:44 PM PDT 24
Finished May 07 12:36:02 PM PDT 24
Peak memory 201092 kb
Host smart-a719219f-c968-4b5e-9ed5-02fe704446ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217931529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3217931529
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2167000775
Short name T524
Test name
Test status
Simulation time 487283772 ps
CPU time 2.62 seconds
Started May 07 12:35:42 PM PDT 24
Finished May 07 12:35:46 PM PDT 24
Peak memory 200708 kb
Host smart-8a93151e-e1e9-4c49-bac3-fcf333cc3758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167000775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2167000775
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.298454345
Short name T348
Test name
Test status
Simulation time 84617287 ps
CPU time 0.85 seconds
Started May 07 12:35:54 PM PDT 24
Finished May 07 12:35:56 PM PDT 24
Peak memory 200744 kb
Host smart-6fb08e5c-d6c4-47c6-b43f-6c6cdbe52daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298454345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.298454345
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2887677390
Short name T293
Test name
Test status
Simulation time 81190549 ps
CPU time 0.95 seconds
Started May 07 12:35:39 PM PDT 24
Finished May 07 12:35:41 PM PDT 24
Peak memory 200648 kb
Host smart-ccf4775a-af33-4281-ab90-9a7c0f36e5e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887677390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2887677390
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3322758868
Short name T43
Test name
Test status
Simulation time 2162801397 ps
CPU time 7.88 seconds
Started May 07 12:35:44 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 217512 kb
Host smart-829068ed-4bbc-4f01-84ed-be7f2e7b1bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322758868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3322758868
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2306536353
Short name T297
Test name
Test status
Simulation time 244746948 ps
CPU time 1.07 seconds
Started May 07 12:35:42 PM PDT 24
Finished May 07 12:35:44 PM PDT 24
Peak memory 217844 kb
Host smart-9add4f74-9e8b-4a3c-85d0-f0d060559876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306536353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2306536353
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3815232613
Short name T349
Test name
Test status
Simulation time 153536617 ps
CPU time 0.94 seconds
Started May 07 12:36:02 PM PDT 24
Finished May 07 12:36:04 PM PDT 24
Peak memory 200620 kb
Host smart-4b8927b8-c7e9-4be3-9c7e-edd1e11f1d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815232613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3815232613
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3346486543
Short name T517
Test name
Test status
Simulation time 714920619 ps
CPU time 3.74 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:35:51 PM PDT 24
Peak memory 200996 kb
Host smart-26184b72-4ff3-4ed4-9789-45a7647878fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346486543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3346486543
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3998689874
Short name T493
Test name
Test status
Simulation time 106913308 ps
CPU time 1.05 seconds
Started May 07 12:35:50 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 200876 kb
Host smart-dbe184fc-2168-4517-a366-9afba8d6c862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998689874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3998689874
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4283990672
Short name T367
Test name
Test status
Simulation time 119915809 ps
CPU time 1.28 seconds
Started May 07 12:35:50 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 201132 kb
Host smart-bcdd2927-bece-4507-b44b-d1207c0b4a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283990672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4283990672
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3312557138
Short name T416
Test name
Test status
Simulation time 3367478424 ps
CPU time 14.82 seconds
Started May 07 12:35:52 PM PDT 24
Finished May 07 12:36:08 PM PDT 24
Peak memory 201088 kb
Host smart-5efe7095-0be0-4584-b273-aec9a60cacd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312557138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3312557138
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.648271493
Short name T356
Test name
Test status
Simulation time 380571293 ps
CPU time 2.48 seconds
Started May 07 12:36:07 PM PDT 24
Finished May 07 12:36:12 PM PDT 24
Peak memory 200800 kb
Host smart-14b1546d-14e8-4c23-9ac1-d55bedf48e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648271493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.648271493
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1655452619
Short name T378
Test name
Test status
Simulation time 142496420 ps
CPU time 1.22 seconds
Started May 07 12:36:07 PM PDT 24
Finished May 07 12:36:10 PM PDT 24
Peak memory 200800 kb
Host smart-3f4cdeaa-f858-43e9-aaa3-ef26b103f30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655452619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1655452619
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.944174913
Short name T5
Test name
Test status
Simulation time 69163718 ps
CPU time 0.76 seconds
Started May 07 12:35:38 PM PDT 24
Finished May 07 12:35:41 PM PDT 24
Peak memory 200640 kb
Host smart-58453485-de0c-4059-96e0-7bafe4562d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944174913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.944174913
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3471193712
Short name T182
Test name
Test status
Simulation time 1229841673 ps
CPU time 6.05 seconds
Started May 07 12:36:05 PM PDT 24
Finished May 07 12:36:12 PM PDT 24
Peak memory 218280 kb
Host smart-5b845df4-6a1d-470b-9f46-e8083292971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471193712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3471193712
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2523389063
Short name T422
Test name
Test status
Simulation time 244361944 ps
CPU time 1.14 seconds
Started May 07 12:35:50 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 217912 kb
Host smart-4253ac7e-6da5-4072-8a1a-7c924594ec8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523389063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2523389063
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1812233574
Short name T17
Test name
Test status
Simulation time 129250143 ps
CPU time 0.78 seconds
Started May 07 12:35:40 PM PDT 24
Finished May 07 12:35:42 PM PDT 24
Peak memory 200308 kb
Host smart-e39242b6-a244-4a06-aa00-1975fe9527b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812233574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1812233574
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2688880741
Short name T488
Test name
Test status
Simulation time 1035864214 ps
CPU time 4.81 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:56 PM PDT 24
Peak memory 201056 kb
Host smart-25ac06b7-9c65-43cd-a3d3-1702a7b6c2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688880741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2688880741
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1517762355
Short name T474
Test name
Test status
Simulation time 113206651 ps
CPU time 1.08 seconds
Started May 07 12:35:51 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 200824 kb
Host smart-b2581d2d-e4ae-4dcf-b2a1-b7f7704c0285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517762355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1517762355
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2347635738
Short name T198
Test name
Test status
Simulation time 116529138 ps
CPU time 1.21 seconds
Started May 07 12:35:50 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 200948 kb
Host smart-b916d5a7-f908-49e3-b9bb-862f0cc58e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347635738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2347635738
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.704292095
Short name T535
Test name
Test status
Simulation time 3080303869 ps
CPU time 11.8 seconds
Started May 07 12:35:38 PM PDT 24
Finished May 07 12:35:52 PM PDT 24
Peak memory 209316 kb
Host smart-04f02859-858f-4380-bc51-f9f107c934fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704292095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.704292095
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1933601575
Short name T292
Test name
Test status
Simulation time 123872261 ps
CPU time 1.57 seconds
Started May 07 12:35:57 PM PDT 24
Finished May 07 12:36:00 PM PDT 24
Peak memory 200728 kb
Host smart-8122e098-f589-4b46-a369-3487491704ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933601575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1933601575
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1736649874
Short name T523
Test name
Test status
Simulation time 280614387 ps
CPU time 1.57 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 200752 kb
Host smart-fe581a9c-861a-4a63-b664-5c49cb6b5ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736649874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1736649874
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2952073688
Short name T499
Test name
Test status
Simulation time 102865066 ps
CPU time 0.85 seconds
Started May 07 12:35:37 PM PDT 24
Finished May 07 12:35:40 PM PDT 24
Peak memory 200588 kb
Host smart-b2e1487e-9e53-49f5-bc1a-a27aea3ce8c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952073688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2952073688
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1356141479
Short name T13
Test name
Test status
Simulation time 1231210743 ps
CPU time 5.44 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:56 PM PDT 24
Peak memory 217704 kb
Host smart-f98b24b6-3950-4fb0-8feb-afdfad1c5561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356141479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1356141479
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2779885061
Short name T409
Test name
Test status
Simulation time 243493904 ps
CPU time 1.19 seconds
Started May 07 12:35:35 PM PDT 24
Finished May 07 12:35:40 PM PDT 24
Peak memory 218152 kb
Host smart-22d2e444-d66d-4572-a4c4-c32914b3d9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779885061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2779885061
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3028982516
Short name T183
Test name
Test status
Simulation time 255321956 ps
CPU time 0.92 seconds
Started May 07 12:35:32 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 200596 kb
Host smart-3e529561-4a48-4a93-9ff2-03adfb818624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028982516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3028982516
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.4116919449
Short name T231
Test name
Test status
Simulation time 925281722 ps
CPU time 4.38 seconds
Started May 07 12:35:38 PM PDT 24
Finished May 07 12:35:44 PM PDT 24
Peak memory 200940 kb
Host smart-d0113e12-4088-4511-bd05-65a6f41756bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116919449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4116919449
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.149441346
Short name T453
Test name
Test status
Simulation time 169953528 ps
CPU time 1.17 seconds
Started May 07 12:35:45 PM PDT 24
Finished May 07 12:35:47 PM PDT 24
Peak memory 200832 kb
Host smart-adf443b3-305e-4d79-9dfd-da642bd1bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149441346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.149441346
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3215541211
Short name T27
Test name
Test status
Simulation time 195492484 ps
CPU time 1.38 seconds
Started May 07 12:35:48 PM PDT 24
Finished May 07 12:35:51 PM PDT 24
Peak memory 200984 kb
Host smart-a210048b-a6d9-44fb-b38a-eae66e7f3aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215541211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3215541211
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1500809588
Short name T230
Test name
Test status
Simulation time 2066677453 ps
CPU time 10.04 seconds
Started May 07 12:35:50 PM PDT 24
Finished May 07 12:36:02 PM PDT 24
Peak memory 201112 kb
Host smart-bc4b84e7-5da9-4408-b659-e1a8a9e72ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500809588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1500809588
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.694276104
Short name T190
Test name
Test status
Simulation time 312875734 ps
CPU time 2.1 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 200740 kb
Host smart-c54233f0-3321-42ec-a5f8-03f784091be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694276104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.694276104
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.839017378
Short name T81
Test name
Test status
Simulation time 119199346 ps
CPU time 0.97 seconds
Started May 07 12:35:57 PM PDT 24
Finished May 07 12:36:00 PM PDT 24
Peak memory 200788 kb
Host smart-ac056554-5284-4af0-9ca9-c89ce01cf0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839017378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.839017378
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.37071416
Short name T46
Test name
Test status
Simulation time 71658319 ps
CPU time 0.75 seconds
Started May 07 12:35:44 PM PDT 24
Finished May 07 12:35:46 PM PDT 24
Peak memory 200660 kb
Host smart-3458d502-115a-4a37-85ae-bdf3038f1264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37071416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.37071416
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2388858550
Short name T184
Test name
Test status
Simulation time 243539934 ps
CPU time 1.12 seconds
Started May 07 12:35:50 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 218104 kb
Host smart-a138d140-1bc6-47bb-ac9c-ae3640f81234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388858550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2388858550
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3522572569
Short name T15
Test name
Test status
Simulation time 203945411 ps
CPU time 0.96 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:35:49 PM PDT 24
Peak memory 200600 kb
Host smart-70278e94-fc6d-4d2f-8185-6f82bd753bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522572569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3522572569
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3146722973
Short name T261
Test name
Test status
Simulation time 1095368374 ps
CPU time 5.18 seconds
Started May 07 12:35:41 PM PDT 24
Finished May 07 12:35:47 PM PDT 24
Peak memory 200968 kb
Host smart-eb2e24eb-3f72-48b4-9d31-c5015a36bcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146722973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3146722973
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.607673820
Short name T102
Test name
Test status
Simulation time 153818188 ps
CPU time 1.09 seconds
Started May 07 12:35:54 PM PDT 24
Finished May 07 12:35:56 PM PDT 24
Peak memory 200824 kb
Host smart-9b8eae2a-6ab7-4bbb-bcda-2ce340a03a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607673820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.607673820
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3531422889
Short name T461
Test name
Test status
Simulation time 226567617 ps
CPU time 1.41 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:35:49 PM PDT 24
Peak memory 201024 kb
Host smart-15a77f88-7dd3-4c20-a6c1-b0cdccd14213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531422889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3531422889
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.582324055
Short name T456
Test name
Test status
Simulation time 1658635762 ps
CPU time 8.55 seconds
Started May 07 12:35:53 PM PDT 24
Finished May 07 12:36:03 PM PDT 24
Peak memory 210264 kb
Host smart-30657656-e0f9-48a5-8361-c4e63188ec07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582324055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.582324055
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.674215908
Short name T455
Test name
Test status
Simulation time 125156710 ps
CPU time 1.72 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 200852 kb
Host smart-de611402-bad8-4999-a69d-2517a51aa775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674215908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.674215908
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3759507099
Short name T324
Test name
Test status
Simulation time 103540088 ps
CPU time 0.91 seconds
Started May 07 12:35:45 PM PDT 24
Finished May 07 12:35:47 PM PDT 24
Peak memory 201048 kb
Host smart-510b75da-3ff0-44f2-a7e1-fabb9ea88b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759507099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3759507099
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3272779566
Short name T287
Test name
Test status
Simulation time 58371868 ps
CPU time 0.78 seconds
Started May 07 12:35:56 PM PDT 24
Finished May 07 12:35:58 PM PDT 24
Peak memory 200588 kb
Host smart-3feb6f9b-baff-4fc0-8cf2-f93e05fde0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272779566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3272779566
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1315551551
Short name T38
Test name
Test status
Simulation time 1879842169 ps
CPU time 6.86 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:55 PM PDT 24
Peak memory 218380 kb
Host smart-7c3fcee2-3b45-431c-97a3-44fdf29d63cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315551551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1315551551
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1731007380
Short name T227
Test name
Test status
Simulation time 244736170 ps
CPU time 1.06 seconds
Started May 07 12:35:38 PM PDT 24
Finished May 07 12:35:41 PM PDT 24
Peak memory 217956 kb
Host smart-b3ac428d-fe1f-43c2-967e-0165701c2c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731007380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1731007380
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3916973959
Short name T290
Test name
Test status
Simulation time 209905415 ps
CPU time 0.89 seconds
Started May 07 12:35:52 PM PDT 24
Finished May 07 12:35:54 PM PDT 24
Peak memory 200608 kb
Host smart-c9c5c473-76f7-4926-b3ef-37c14fc405d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916973959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3916973959
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1913801333
Short name T106
Test name
Test status
Simulation time 874587886 ps
CPU time 4.42 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:55 PM PDT 24
Peak memory 201012 kb
Host smart-20bca033-b81f-4b6c-9e01-f2821f1eee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913801333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1913801333
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3208551546
Short name T201
Test name
Test status
Simulation time 143456637 ps
CPU time 1.08 seconds
Started May 07 12:35:56 PM PDT 24
Finished May 07 12:35:59 PM PDT 24
Peak memory 200812 kb
Host smart-1c5d8267-f9af-4651-8b37-1d5b04d2e844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208551546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3208551546
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.4287817117
Short name T310
Test name
Test status
Simulation time 122698352 ps
CPU time 1.21 seconds
Started May 07 12:35:51 PM PDT 24
Finished May 07 12:35:54 PM PDT 24
Peak memory 200988 kb
Host smart-efeb51b2-8b26-4352-b686-03e142890f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287817117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.4287817117
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2316878290
Short name T491
Test name
Test status
Simulation time 14730398184 ps
CPU time 48.63 seconds
Started May 07 12:35:40 PM PDT 24
Finished May 07 12:36:30 PM PDT 24
Peak memory 209284 kb
Host smart-e8db847f-c290-40cd-bb6f-bad12f560e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316878290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2316878290
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3668649021
Short name T289
Test name
Test status
Simulation time 134874571 ps
CPU time 1.68 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:52 PM PDT 24
Peak memory 209020 kb
Host smart-7c4fcfcd-85d1-43fa-86a2-00e74cd7183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668649021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3668649021
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.477429930
Short name T221
Test name
Test status
Simulation time 85316714 ps
CPU time 0.81 seconds
Started May 07 12:35:41 PM PDT 24
Finished May 07 12:35:43 PM PDT 24
Peak memory 200780 kb
Host smart-adbf7e44-444b-4d90-aca9-1719d32e6f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477429930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.477429930
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1179583912
Short name T224
Test name
Test status
Simulation time 68659838 ps
CPU time 0.75 seconds
Started May 07 12:35:08 PM PDT 24
Finished May 07 12:35:10 PM PDT 24
Peak memory 200552 kb
Host smart-61dab2d1-7b40-4831-a3f2-b2f30e5880fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179583912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1179583912
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1063582566
Short name T41
Test name
Test status
Simulation time 1216829358 ps
CPU time 5.5 seconds
Started May 07 12:35:22 PM PDT 24
Finished May 07 12:35:29 PM PDT 24
Peak memory 218404 kb
Host smart-cac7163d-e786-400d-a66e-abd588e78913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063582566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1063582566
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1078653716
Short name T454
Test name
Test status
Simulation time 245442024 ps
CPU time 1.16 seconds
Started May 07 12:35:23 PM PDT 24
Finished May 07 12:35:26 PM PDT 24
Peak memory 217960 kb
Host smart-50446acb-4f05-4dbe-9d54-c8cf906ea4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078653716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1078653716
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1637262727
Short name T19
Test name
Test status
Simulation time 109366260 ps
CPU time 0.82 seconds
Started May 07 12:35:16 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 200132 kb
Host smart-54484af1-c81d-410f-b922-5cd7c1af9d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637262727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1637262727
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.264555126
Short name T296
Test name
Test status
Simulation time 1084126241 ps
CPU time 5.37 seconds
Started May 07 12:35:15 PM PDT 24
Finished May 07 12:35:22 PM PDT 24
Peak memory 200984 kb
Host smart-1a987acc-b569-4ff2-bbdb-20f483c7f732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264555126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.264555126
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.73229844
Short name T63
Test name
Test status
Simulation time 8354856605 ps
CPU time 14.18 seconds
Started May 07 12:35:06 PM PDT 24
Finished May 07 12:35:21 PM PDT 24
Peak memory 218192 kb
Host smart-8ae112a0-04aa-427a-8f10-e3baeedccfbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73229844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.73229844
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4139085058
Short name T233
Test name
Test status
Simulation time 154997417 ps
CPU time 1.14 seconds
Started May 07 12:35:22 PM PDT 24
Finished May 07 12:35:26 PM PDT 24
Peak memory 200828 kb
Host smart-848e8799-64fe-4ae2-98fe-d97aefb11e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139085058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4139085058
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4139044070
Short name T285
Test name
Test status
Simulation time 254870452 ps
CPU time 1.56 seconds
Started May 07 12:35:22 PM PDT 24
Finished May 07 12:35:26 PM PDT 24
Peak memory 200936 kb
Host smart-743187bf-56b2-400d-809c-a45569837068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139044070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4139044070
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1464441726
Short name T83
Test name
Test status
Simulation time 3078855691 ps
CPU time 14.96 seconds
Started May 07 12:35:08 PM PDT 24
Finished May 07 12:35:25 PM PDT 24
Peak memory 209256 kb
Host smart-dbd3bf86-48aa-402d-8438-88c6103c6f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464441726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1464441726
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.524824037
Short name T512
Test name
Test status
Simulation time 560944565 ps
CPU time 2.8 seconds
Started May 07 12:35:17 PM PDT 24
Finished May 07 12:35:22 PM PDT 24
Peak memory 200708 kb
Host smart-1d618447-6fe3-4bb4-bf6f-80dff9ae3669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524824037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.524824037
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.395980671
Short name T10
Test name
Test status
Simulation time 186748609 ps
CPU time 1.2 seconds
Started May 07 12:35:11 PM PDT 24
Finished May 07 12:35:15 PM PDT 24
Peak memory 200776 kb
Host smart-70df416b-759f-4d1f-9a67-7052df4388cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395980671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.395980671
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.302209843
Short name T305
Test name
Test status
Simulation time 66363068 ps
CPU time 0.79 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:49 PM PDT 24
Peak memory 200592 kb
Host smart-8ac87279-9774-4f4e-9482-765c498d2d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302209843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.302209843
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4172392734
Short name T301
Test name
Test status
Simulation time 2354081902 ps
CPU time 8.26 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:56 PM PDT 24
Peak memory 218156 kb
Host smart-471a3086-d948-4d42-b392-239a6af2e8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172392734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4172392734
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3198306527
Short name T308
Test name
Test status
Simulation time 243744063 ps
CPU time 1.11 seconds
Started May 07 12:35:55 PM PDT 24
Finished May 07 12:35:57 PM PDT 24
Peak memory 218120 kb
Host smart-289b42c6-f67e-415a-a791-a459f396abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198306527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3198306527
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3433050058
Short name T336
Test name
Test status
Simulation time 134406202 ps
CPU time 0.77 seconds
Started May 07 12:35:45 PM PDT 24
Finished May 07 12:35:47 PM PDT 24
Peak memory 200672 kb
Host smart-228782d0-7af6-4e12-875e-7417b3f7f572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433050058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3433050058
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1745885860
Short name T405
Test name
Test status
Simulation time 909583267 ps
CPU time 4.29 seconds
Started May 07 12:35:36 PM PDT 24
Finished May 07 12:35:43 PM PDT 24
Peak memory 200948 kb
Host smart-27c229a0-adb3-44a3-a8a2-f754fc061ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745885860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1745885860
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2059413038
Short name T518
Test name
Test status
Simulation time 151857842 ps
CPU time 1.09 seconds
Started May 07 12:35:38 PM PDT 24
Finished May 07 12:35:41 PM PDT 24
Peak memory 200804 kb
Host smart-59bb1157-45c1-4cda-9236-54ec345a4d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059413038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2059413038
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2290487239
Short name T509
Test name
Test status
Simulation time 117873883 ps
CPU time 1.19 seconds
Started May 07 12:35:56 PM PDT 24
Finished May 07 12:35:59 PM PDT 24
Peak memory 200928 kb
Host smart-8db2c153-380c-4002-ad12-e9b742b7c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290487239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2290487239
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3128109932
Short name T376
Test name
Test status
Simulation time 8907353807 ps
CPU time 30.98 seconds
Started May 07 12:36:15 PM PDT 24
Finished May 07 12:36:48 PM PDT 24
Peak memory 209272 kb
Host smart-350f59d6-a51e-41f9-bad8-478baabd4160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128109932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3128109932
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.629761463
Short name T304
Test name
Test status
Simulation time 375996210 ps
CPU time 2.08 seconds
Started May 07 12:35:41 PM PDT 24
Finished May 07 12:35:45 PM PDT 24
Peak memory 200744 kb
Host smart-ec5ae7b3-6487-4fd8-93be-5e9f58e631ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629761463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.629761463
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2083032049
Short name T298
Test name
Test status
Simulation time 65035343 ps
CPU time 0.74 seconds
Started May 07 12:35:48 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 200808 kb
Host smart-dc067ea6-4625-4d1b-9c51-15c0b6a8ee1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083032049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2083032049
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.361092665
Short name T393
Test name
Test status
Simulation time 78943515 ps
CPU time 0.8 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:52 PM PDT 24
Peak memory 200580 kb
Host smart-ce0c56db-b8bb-4b72-880a-2a513034dbfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361092665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.361092665
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2738542757
Short name T51
Test name
Test status
Simulation time 1225700174 ps
CPU time 5.9 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:57 PM PDT 24
Peak memory 222260 kb
Host smart-66d5155c-aab2-4876-901e-0bba007c6357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738542757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2738542757
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3931210702
Short name T204
Test name
Test status
Simulation time 244156700 ps
CPU time 1.17 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:51 PM PDT 24
Peak memory 218152 kb
Host smart-c692e205-7898-42c3-8315-2b6ea0fb64b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931210702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3931210702
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.988026615
Short name T500
Test name
Test status
Simulation time 76492067 ps
CPU time 0.77 seconds
Started May 07 12:35:45 PM PDT 24
Finished May 07 12:35:48 PM PDT 24
Peak memory 200616 kb
Host smart-d74086d1-dd53-4d76-826d-78461dc08b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988026615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.988026615
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1623914935
Short name T80
Test name
Test status
Simulation time 1568835644 ps
CPU time 7.06 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:58 PM PDT 24
Peak memory 200984 kb
Host smart-a20a67f7-1cc8-4ff0-8bc5-a586e3bece6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623914935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1623914935
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1009641991
Short name T368
Test name
Test status
Simulation time 141288040 ps
CPU time 1.1 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:35:48 PM PDT 24
Peak memory 200804 kb
Host smart-61f3666c-0ee9-43b8-9e1f-537133a811f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009641991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1009641991
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.4074057760
Short name T311
Test name
Test status
Simulation time 210066721 ps
CPU time 1.44 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 201024 kb
Host smart-51f058f8-f6e5-4059-9978-4f5d6a4a5519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074057760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.4074057760
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.141276364
Short name T390
Test name
Test status
Simulation time 1052418655 ps
CPU time 5.02 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:55 PM PDT 24
Peak memory 209164 kb
Host smart-2cef36c9-3e78-40f2-ba0a-b5f622f04839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141276364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.141276364
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.844268063
Short name T276
Test name
Test status
Simulation time 137707976 ps
CPU time 1.77 seconds
Started May 07 12:35:43 PM PDT 24
Finished May 07 12:35:46 PM PDT 24
Peak memory 200820 kb
Host smart-9789832a-151c-47ac-8c74-a996605d9ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844268063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.844268063
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1765313715
Short name T159
Test name
Test status
Simulation time 70204516 ps
CPU time 0.79 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:49 PM PDT 24
Peak memory 200796 kb
Host smart-4d6ef65b-937d-4dda-982a-aa7bedd990c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765313715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1765313715
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.724731170
Short name T149
Test name
Test status
Simulation time 78702523 ps
CPU time 0.92 seconds
Started May 07 12:36:00 PM PDT 24
Finished May 07 12:36:02 PM PDT 24
Peak memory 200640 kb
Host smart-2379ec1d-10cf-4a03-8271-4175f52029c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724731170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.724731170
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2341355032
Short name T50
Test name
Test status
Simulation time 1226367916 ps
CPU time 6.15 seconds
Started May 07 12:35:55 PM PDT 24
Finished May 07 12:36:02 PM PDT 24
Peak memory 222412 kb
Host smart-e7b66fb5-ea0d-4ab8-9c27-86c13e7e4c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341355032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2341355032
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3573570515
Short name T139
Test name
Test status
Simulation time 245947773 ps
CPU time 1.04 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 218044 kb
Host smart-26e771a3-a574-4118-91d5-bfd1b1a50c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573570515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3573570515
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2171118728
Short name T181
Test name
Test status
Simulation time 87984308 ps
CPU time 0.75 seconds
Started May 07 12:35:44 PM PDT 24
Finished May 07 12:35:45 PM PDT 24
Peak memory 200644 kb
Host smart-9dea7252-0766-4b34-9b44-0b08a70953aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171118728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2171118728
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2381426432
Short name T408
Test name
Test status
Simulation time 2128542059 ps
CPU time 7.34 seconds
Started May 07 12:35:41 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 200928 kb
Host smart-329535c6-6b7c-4532-989f-056bb90868ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381426432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2381426432
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1487387859
Short name T406
Test name
Test status
Simulation time 176109668 ps
CPU time 1.23 seconds
Started May 07 12:35:40 PM PDT 24
Finished May 07 12:35:43 PM PDT 24
Peak memory 200820 kb
Host smart-67420d73-fa88-4752-a505-8ee944aa9e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487387859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1487387859
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.587060202
Short name T530
Test name
Test status
Simulation time 117615894 ps
CPU time 1.16 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 200928 kb
Host smart-658d0602-73b6-4e71-bee8-9d9ac697002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587060202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.587060202
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.307245736
Short name T263
Test name
Test status
Simulation time 7238633648 ps
CPU time 26.82 seconds
Started May 07 12:35:55 PM PDT 24
Finished May 07 12:36:23 PM PDT 24
Peak memory 201148 kb
Host smart-05c53d8e-987f-4351-9c48-d24f6a21db23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307245736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.307245736
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3256130091
Short name T372
Test name
Test status
Simulation time 339784346 ps
CPU time 2.35 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 208932 kb
Host smart-5de1b08d-3be6-49ad-938d-0d8a8187572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256130091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3256130091
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.112545773
Short name T401
Test name
Test status
Simulation time 174077187 ps
CPU time 1.44 seconds
Started May 07 12:35:53 PM PDT 24
Finished May 07 12:35:55 PM PDT 24
Peak memory 200980 kb
Host smart-766f63c8-fcb1-474f-93e2-7c9269060a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112545773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.112545773
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1134223738
Short name T148
Test name
Test status
Simulation time 85563731 ps
CPU time 0.87 seconds
Started May 07 12:35:57 PM PDT 24
Finished May 07 12:35:59 PM PDT 24
Peak memory 200560 kb
Host smart-19f380dd-5b3b-4141-9bc4-5a82247b40f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134223738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1134223738
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3609546986
Short name T70
Test name
Test status
Simulation time 1886920983 ps
CPU time 6.72 seconds
Started May 07 12:36:00 PM PDT 24
Finished May 07 12:36:08 PM PDT 24
Peak memory 217972 kb
Host smart-48369e10-82cb-4bf0-b105-bc291041417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609546986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3609546986
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1443898849
Short name T440
Test name
Test status
Simulation time 244333648 ps
CPU time 1.13 seconds
Started May 07 12:35:55 PM PDT 24
Finished May 07 12:35:58 PM PDT 24
Peak memory 217916 kb
Host smart-5fe5dc60-ca4e-4fda-8f22-2e5e48f3cc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443898849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1443898849
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2801809828
Short name T479
Test name
Test status
Simulation time 122033492 ps
CPU time 0.84 seconds
Started May 07 12:36:05 PM PDT 24
Finished May 07 12:36:08 PM PDT 24
Peak memory 200644 kb
Host smart-bd6def79-871e-47f7-aa50-75db1eb33b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801809828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2801809828
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.645883437
Short name T343
Test name
Test status
Simulation time 1655660644 ps
CPU time 6.77 seconds
Started May 07 12:36:02 PM PDT 24
Finished May 07 12:36:10 PM PDT 24
Peak memory 200808 kb
Host smart-a7ce4c1f-6c86-4240-bfb5-f285b8b511da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645883437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.645883437
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3149852049
Short name T67
Test name
Test status
Simulation time 152455931 ps
CPU time 1.08 seconds
Started May 07 12:36:02 PM PDT 24
Finished May 07 12:36:05 PM PDT 24
Peak memory 200580 kb
Host smart-a44c0898-16f5-4e99-8fde-dc4a95d9d794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149852049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3149852049
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.597563677
Short name T218
Test name
Test status
Simulation time 203030033 ps
CPU time 1.47 seconds
Started May 07 12:35:53 PM PDT 24
Finished May 07 12:35:56 PM PDT 24
Peak memory 200940 kb
Host smart-1211bb29-d6f9-47d7-ab25-013dfb47ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597563677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.597563677
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2142561999
Short name T309
Test name
Test status
Simulation time 13466809377 ps
CPU time 45.77 seconds
Started May 07 12:35:57 PM PDT 24
Finished May 07 12:36:45 PM PDT 24
Peak memory 200988 kb
Host smart-80d4410a-77c5-4d99-8b8b-e2a0add8227e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142561999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2142561999
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2132315773
Short name T195
Test name
Test status
Simulation time 143279468 ps
CPU time 1.78 seconds
Started May 07 12:36:02 PM PDT 24
Finished May 07 12:36:06 PM PDT 24
Peak memory 200580 kb
Host smart-911c93ae-36de-4d39-8def-170a5a1b9b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132315773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2132315773
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.578611282
Short name T318
Test name
Test status
Simulation time 149899082 ps
CPU time 1.15 seconds
Started May 07 12:35:41 PM PDT 24
Finished May 07 12:35:43 PM PDT 24
Peak memory 200976 kb
Host smart-eca234fc-1b1c-414a-b82b-55e8204cb315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578611282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.578611282
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2696545586
Short name T199
Test name
Test status
Simulation time 72448689 ps
CPU time 0.79 seconds
Started May 07 12:35:44 PM PDT 24
Finished May 07 12:35:45 PM PDT 24
Peak memory 200556 kb
Host smart-9eaa6256-76b7-40a4-b579-76b8bad56e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696545586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2696545586
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2492378518
Short name T470
Test name
Test status
Simulation time 1884338100 ps
CPU time 7.04 seconds
Started May 07 12:36:04 PM PDT 24
Finished May 07 12:36:13 PM PDT 24
Peak memory 218480 kb
Host smart-ac867aea-d491-4ec2-a9ce-afbb4b846580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492378518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2492378518
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2881260376
Short name T396
Test name
Test status
Simulation time 244400540 ps
CPU time 1.05 seconds
Started May 07 12:35:57 PM PDT 24
Finished May 07 12:36:00 PM PDT 24
Peak memory 217992 kb
Host smart-3c7ef0b9-b966-4602-a827-3f8187d5e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881260376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2881260376
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1187794243
Short name T507
Test name
Test status
Simulation time 162991702 ps
CPU time 0.85 seconds
Started May 07 12:35:52 PM PDT 24
Finished May 07 12:35:54 PM PDT 24
Peak memory 200616 kb
Host smart-0ad5f8f2-0bf9-410f-a9ed-30ec957c89ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187794243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1187794243
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2570515956
Short name T447
Test name
Test status
Simulation time 2061045553 ps
CPU time 7.66 seconds
Started May 07 12:36:07 PM PDT 24
Finished May 07 12:36:17 PM PDT 24
Peak memory 200896 kb
Host smart-150ca429-2838-4618-9d72-9fe257053d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570515956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2570515956
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2186560342
Short name T266
Test name
Test status
Simulation time 145606403 ps
CPU time 1.11 seconds
Started May 07 12:36:08 PM PDT 24
Finished May 07 12:36:12 PM PDT 24
Peak memory 200724 kb
Host smart-51c6ebdb-f64c-496a-ac07-8c609832db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186560342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2186560342
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.468724107
Short name T243
Test name
Test status
Simulation time 193288793 ps
CPU time 1.4 seconds
Started May 07 12:35:52 PM PDT 24
Finished May 07 12:35:55 PM PDT 24
Peak memory 200964 kb
Host smart-395f4260-f740-4ce6-b16b-30b58d28ab8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468724107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.468724107
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3214943722
Short name T197
Test name
Test status
Simulation time 6401745092 ps
CPU time 22.42 seconds
Started May 07 12:35:46 PM PDT 24
Finished May 07 12:36:10 PM PDT 24
Peak memory 209244 kb
Host smart-595c0d56-3a8e-4a08-91e1-385d19e1b20c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214943722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3214943722
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.276621477
Short name T472
Test name
Test status
Simulation time 373281231 ps
CPU time 2.28 seconds
Started May 07 12:36:00 PM PDT 24
Finished May 07 12:36:04 PM PDT 24
Peak memory 200740 kb
Host smart-6ccdcda2-2961-4755-b125-84107aba4e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276621477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.276621477
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3687162011
Short name T138
Test name
Test status
Simulation time 127022437 ps
CPU time 1 seconds
Started May 07 12:35:58 PM PDT 24
Finished May 07 12:36:00 PM PDT 24
Peak memory 200756 kb
Host smart-73e38e06-97ae-4dfe-9fd3-bbdd7493da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687162011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3687162011
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.167220484
Short name T519
Test name
Test status
Simulation time 85789525 ps
CPU time 0.83 seconds
Started May 07 12:35:48 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 200600 kb
Host smart-1747090a-e0ed-4d2b-a9ec-35913293db7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167220484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.167220484
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.807407723
Short name T3
Test name
Test status
Simulation time 1226830842 ps
CPU time 5.33 seconds
Started May 07 12:36:01 PM PDT 24
Finished May 07 12:36:07 PM PDT 24
Peak memory 217428 kb
Host smart-6c9fab62-3820-4080-8536-35c5d382492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807407723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.807407723
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1405247103
Short name T460
Test name
Test status
Simulation time 246108808 ps
CPU time 1.05 seconds
Started May 07 12:35:55 PM PDT 24
Finished May 07 12:35:57 PM PDT 24
Peak memory 217940 kb
Host smart-6d900b0b-fbe4-4724-8711-da79aa0f42c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405247103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1405247103
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1616220333
Short name T20
Test name
Test status
Simulation time 176107837 ps
CPU time 0.88 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 200584 kb
Host smart-088b1660-e056-4958-ab3d-022efbc9a0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616220333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1616220333
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3583090052
Short name T494
Test name
Test status
Simulation time 783252449 ps
CPU time 3.8 seconds
Started May 07 12:35:54 PM PDT 24
Finished May 07 12:35:59 PM PDT 24
Peak memory 201024 kb
Host smart-ff14a12c-dd54-4c0f-aee4-c305c27ac05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583090052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3583090052
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4016164392
Short name T414
Test name
Test status
Simulation time 153987891 ps
CPU time 1.14 seconds
Started May 07 12:36:00 PM PDT 24
Finished May 07 12:36:03 PM PDT 24
Peak memory 200760 kb
Host smart-64b266a5-e27a-44e5-8304-13c028675780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016164392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4016164392
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.454873633
Short name T316
Test name
Test status
Simulation time 258028405 ps
CPU time 1.49 seconds
Started May 07 12:35:56 PM PDT 24
Finished May 07 12:35:59 PM PDT 24
Peak memory 200896 kb
Host smart-6ef72988-de85-41fc-8a8c-f2aecc0905d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454873633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.454873633
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3304528153
Short name T100
Test name
Test status
Simulation time 11644331486 ps
CPU time 39.61 seconds
Started May 07 12:35:52 PM PDT 24
Finished May 07 12:36:33 PM PDT 24
Peak memory 201108 kb
Host smart-8aa9176c-200b-4739-b36e-c041de51a16a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304528153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3304528153
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3224925785
Short name T30
Test name
Test status
Simulation time 407999359 ps
CPU time 2.21 seconds
Started May 07 12:36:07 PM PDT 24
Finished May 07 12:36:11 PM PDT 24
Peak memory 209036 kb
Host smart-18665a21-70f7-4f80-8ed4-1c4f866474ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224925785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3224925785
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2772095343
Short name T382
Test name
Test status
Simulation time 241530088 ps
CPU time 1.45 seconds
Started May 07 12:35:50 PM PDT 24
Finished May 07 12:35:53 PM PDT 24
Peak memory 200804 kb
Host smart-0b244650-423e-4d14-a77c-39357fe292b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772095343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2772095343
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.922808826
Short name T328
Test name
Test status
Simulation time 61286331 ps
CPU time 0.75 seconds
Started May 07 12:35:59 PM PDT 24
Finished May 07 12:36:01 PM PDT 24
Peak memory 200664 kb
Host smart-c14e9243-1254-4f53-a061-e43febe27f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922808826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.922808826
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.99971883
Short name T346
Test name
Test status
Simulation time 1903411257 ps
CPU time 7.05 seconds
Started May 07 12:35:56 PM PDT 24
Finished May 07 12:36:05 PM PDT 24
Peak memory 222452 kb
Host smart-0336b1c6-c642-451b-8ac1-025238fa39bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99971883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.99971883
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.288707116
Short name T226
Test name
Test status
Simulation time 243911752 ps
CPU time 1.14 seconds
Started May 07 12:35:47 PM PDT 24
Finished May 07 12:35:49 PM PDT 24
Peak memory 217872 kb
Host smart-7a39db8f-589c-43d1-a027-a854cf2efc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288707116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.288707116
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1155236311
Short name T533
Test name
Test status
Simulation time 107707120 ps
CPU time 0.8 seconds
Started May 07 12:36:00 PM PDT 24
Finished May 07 12:36:02 PM PDT 24
Peak memory 200640 kb
Host smart-e1d857bc-355e-41c1-b9c2-8be2cf9f9fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155236311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1155236311
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1096315741
Short name T264
Test name
Test status
Simulation time 1108664760 ps
CPU time 5.1 seconds
Started May 07 12:35:56 PM PDT 24
Finished May 07 12:36:03 PM PDT 24
Peak memory 200984 kb
Host smart-db071682-534e-4390-b826-27d5aef80664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096315741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1096315741
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3997190463
Short name T371
Test name
Test status
Simulation time 177108514 ps
CPU time 1.26 seconds
Started May 07 12:35:55 PM PDT 24
Finished May 07 12:35:58 PM PDT 24
Peak memory 200800 kb
Host smart-2ce4f830-d24c-449f-818c-15fb96559ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997190463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3997190463
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3911501651
Short name T237
Test name
Test status
Simulation time 192489160 ps
CPU time 1.33 seconds
Started May 07 12:35:56 PM PDT 24
Finished May 07 12:35:58 PM PDT 24
Peak memory 200996 kb
Host smart-60394c36-562f-481e-bd80-6aa7d7811203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911501651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3911501651
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3858341478
Short name T388
Test name
Test status
Simulation time 604905719 ps
CPU time 2.74 seconds
Started May 07 12:36:06 PM PDT 24
Finished May 07 12:36:10 PM PDT 24
Peak memory 201048 kb
Host smart-feb7ec7b-06da-4090-8fe0-03401c1d19c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858341478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3858341478
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1646513013
Short name T402
Test name
Test status
Simulation time 139565099 ps
CPU time 1.82 seconds
Started May 07 12:35:54 PM PDT 24
Finished May 07 12:35:57 PM PDT 24
Peak memory 209092 kb
Host smart-33c94a61-107d-4a46-bda0-0c50b7ee8c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646513013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1646513013
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2063070525
Short name T200
Test name
Test status
Simulation time 236321807 ps
CPU time 1.39 seconds
Started May 07 12:35:49 PM PDT 24
Finished May 07 12:35:52 PM PDT 24
Peak memory 200984 kb
Host smart-d2396bd6-8a35-426e-81e7-487137636c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063070525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2063070525
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.727436247
Short name T490
Test name
Test status
Simulation time 66480966 ps
CPU time 0.8 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:36:19 PM PDT 24
Peak memory 200596 kb
Host smart-2221493c-414c-49dd-b6b7-07f18d1d2a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727436247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.727436247
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3167144015
Short name T40
Test name
Test status
Simulation time 1895000752 ps
CPU time 7.28 seconds
Started May 07 12:36:10 PM PDT 24
Finished May 07 12:36:20 PM PDT 24
Peak memory 217868 kb
Host smart-ee4a7a17-7e5d-4f08-956d-933cde4e2ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167144015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3167144015
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1311238867
Short name T503
Test name
Test status
Simulation time 244279784 ps
CPU time 1.19 seconds
Started May 07 12:35:57 PM PDT 24
Finished May 07 12:35:59 PM PDT 24
Peak memory 217964 kb
Host smart-9618a02c-f3a7-44da-9873-912c394ca7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311238867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1311238867
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3822080400
Short name T525
Test name
Test status
Simulation time 180987536 ps
CPU time 0.89 seconds
Started May 07 12:36:13 PM PDT 24
Finished May 07 12:36:16 PM PDT 24
Peak memory 200628 kb
Host smart-da0aa752-8645-4ff5-8e86-c36e00daa51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822080400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3822080400
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1184745057
Short name T97
Test name
Test status
Simulation time 1436077972 ps
CPU time 5.53 seconds
Started May 07 12:36:03 PM PDT 24
Finished May 07 12:36:10 PM PDT 24
Peak memory 200984 kb
Host smart-c9b62d59-3c2c-4268-93ed-436635694bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184745057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1184745057
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1776232273
Short name T239
Test name
Test status
Simulation time 101855109 ps
CPU time 1.02 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:19 PM PDT 24
Peak memory 200808 kb
Host smart-09382452-dba0-4467-8010-0f78f75e0ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776232273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1776232273
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1612627505
Short name T352
Test name
Test status
Simulation time 119287807 ps
CPU time 1.3 seconds
Started May 07 12:36:00 PM PDT 24
Finished May 07 12:36:02 PM PDT 24
Peak memory 200972 kb
Host smart-02ad4abc-7c37-41e8-9989-4aa07f7e12ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612627505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1612627505
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1050188846
Short name T398
Test name
Test status
Simulation time 13160886343 ps
CPU time 45.57 seconds
Started May 07 12:36:05 PM PDT 24
Finished May 07 12:36:52 PM PDT 24
Peak memory 209332 kb
Host smart-8a4ad6c4-2c9e-48be-ab10-298bb08d2511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050188846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1050188846
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.864083594
Short name T273
Test name
Test status
Simulation time 120535712 ps
CPU time 1.49 seconds
Started May 07 12:36:14 PM PDT 24
Finished May 07 12:36:18 PM PDT 24
Peak memory 200816 kb
Host smart-1ef28e13-1530-40df-baf1-1396b394500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864083594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.864083594
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2666951379
Short name T6
Test name
Test status
Simulation time 241361196 ps
CPU time 1.4 seconds
Started May 07 12:35:55 PM PDT 24
Finished May 07 12:35:57 PM PDT 24
Peak memory 200812 kb
Host smart-da5a50e2-69a5-40f0-94b6-bc4912db1966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666951379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2666951379
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.365718993
Short name T249
Test name
Test status
Simulation time 59911970 ps
CPU time 0.76 seconds
Started May 07 12:36:01 PM PDT 24
Finished May 07 12:36:04 PM PDT 24
Peak memory 200588 kb
Host smart-af8aa04d-e1a7-4cb5-95aa-da39bd79204d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365718993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.365718993
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1266227736
Short name T347
Test name
Test status
Simulation time 1218864096 ps
CPU time 5.98 seconds
Started May 07 12:36:09 PM PDT 24
Finished May 07 12:36:17 PM PDT 24
Peak memory 222520 kb
Host smart-9438d680-dd78-45a6-a57d-4de293fe608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266227736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1266227736
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2410654948
Short name T427
Test name
Test status
Simulation time 244031846 ps
CPU time 1.07 seconds
Started May 07 12:36:06 PM PDT 24
Finished May 07 12:36:09 PM PDT 24
Peak memory 218100 kb
Host smart-1e3e9012-0967-44c9-929d-bfc6d12482ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410654948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2410654948
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4164299894
Short name T545
Test name
Test status
Simulation time 159651324 ps
CPU time 0.83 seconds
Started May 07 12:36:03 PM PDT 24
Finished May 07 12:36:05 PM PDT 24
Peak memory 200568 kb
Host smart-623df703-b440-468f-b311-481137a536a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164299894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4164299894
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1582877180
Short name T529
Test name
Test status
Simulation time 1740677521 ps
CPU time 6.29 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:24 PM PDT 24
Peak memory 200984 kb
Host smart-57f02d9c-1dc0-4c61-9c41-07cdff024542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582877180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1582877180
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2656153345
Short name T384
Test name
Test status
Simulation time 154204567 ps
CPU time 1.14 seconds
Started May 07 12:36:06 PM PDT 24
Finished May 07 12:36:10 PM PDT 24
Peak memory 200828 kb
Host smart-305eb9c8-1cdf-45b9-8b29-5d9431e2045e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656153345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2656153345
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2228780861
Short name T448
Test name
Test status
Simulation time 189112131 ps
CPU time 1.42 seconds
Started May 07 12:36:07 PM PDT 24
Finished May 07 12:36:10 PM PDT 24
Peak memory 201004 kb
Host smart-a7b4601f-8389-4cc2-a04f-fd86d96a1cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228780861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2228780861
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1452251120
Short name T129
Test name
Test status
Simulation time 10612399306 ps
CPU time 35.6 seconds
Started May 07 12:35:54 PM PDT 24
Finished May 07 12:36:31 PM PDT 24
Peak memory 209324 kb
Host smart-722bd70d-5165-41a4-9deb-9609ffea71a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452251120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1452251120
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3506063181
Short name T176
Test name
Test status
Simulation time 380949793 ps
CPU time 2.57 seconds
Started May 07 12:36:01 PM PDT 24
Finished May 07 12:36:05 PM PDT 24
Peak memory 200732 kb
Host smart-7203d35c-784d-468d-95eb-265187b5e349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506063181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3506063181
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4083107106
Short name T426
Test name
Test status
Simulation time 170855738 ps
CPU time 1.35 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:36:21 PM PDT 24
Peak memory 200988 kb
Host smart-1ac0441d-a4ca-4115-bcf4-c20b9ccb1f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083107106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4083107106
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3133916806
Short name T542
Test name
Test status
Simulation time 65607201 ps
CPU time 0.77 seconds
Started May 07 12:36:05 PM PDT 24
Finished May 07 12:36:07 PM PDT 24
Peak memory 200648 kb
Host smart-d18347ba-66ef-445d-8127-933275c6e563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133916806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3133916806
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4232920103
Short name T465
Test name
Test status
Simulation time 1234590030 ps
CPU time 5.36 seconds
Started May 07 12:36:15 PM PDT 24
Finished May 07 12:36:23 PM PDT 24
Peak memory 221944 kb
Host smart-14013f01-0b54-4155-acb6-430f50a12d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232920103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4232920103
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.176900214
Short name T492
Test name
Test status
Simulation time 244287106 ps
CPU time 1.24 seconds
Started May 07 12:36:03 PM PDT 24
Finished May 07 12:36:06 PM PDT 24
Peak memory 218068 kb
Host smart-d96151ef-1a18-4250-afab-c1e38997ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176900214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.176900214
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2093175161
Short name T486
Test name
Test status
Simulation time 161818351 ps
CPU time 0.88 seconds
Started May 07 12:35:58 PM PDT 24
Finished May 07 12:36:00 PM PDT 24
Peak memory 200572 kb
Host smart-6f58ebd6-221a-427d-b061-55df1b1ba104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093175161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2093175161
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1128737893
Short name T73
Test name
Test status
Simulation time 1402872534 ps
CPU time 5.4 seconds
Started May 07 12:36:08 PM PDT 24
Finished May 07 12:36:15 PM PDT 24
Peak memory 200988 kb
Host smart-47009be7-a3c0-4159-a323-077a75f50f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128737893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1128737893
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3109128198
Short name T281
Test name
Test status
Simulation time 174573470 ps
CPU time 1.19 seconds
Started May 07 12:36:02 PM PDT 24
Finished May 07 12:36:05 PM PDT 24
Peak memory 200704 kb
Host smart-a5a6b6ad-0246-4d51-aaad-b6c749494860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109128198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3109128198
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2616549079
Short name T319
Test name
Test status
Simulation time 248998775 ps
CPU time 1.58 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:20 PM PDT 24
Peak memory 200984 kb
Host smart-13d7e877-0537-4b6f-aab2-19f893edb0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616549079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2616549079
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2204023386
Short name T383
Test name
Test status
Simulation time 10045322364 ps
CPU time 33.22 seconds
Started May 07 12:36:12 PM PDT 24
Finished May 07 12:36:47 PM PDT 24
Peak memory 201156 kb
Host smart-ac47269f-0ee1-4fde-bb43-4d6a7014988a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204023386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2204023386
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1410422174
Short name T532
Test name
Test status
Simulation time 558576145 ps
CPU time 2.76 seconds
Started May 07 12:36:02 PM PDT 24
Finished May 07 12:36:07 PM PDT 24
Peak memory 200788 kb
Host smart-88290410-4119-45bd-baf1-7098df1da5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410422174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1410422174
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2161223797
Short name T428
Test name
Test status
Simulation time 173951466 ps
CPU time 1.13 seconds
Started May 07 12:36:11 PM PDT 24
Finished May 07 12:36:14 PM PDT 24
Peak memory 200832 kb
Host smart-5e372f15-260e-42de-9de5-fce5a98ad7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161223797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2161223797
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1208476773
Short name T445
Test name
Test status
Simulation time 65868046 ps
CPU time 0.77 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:28 PM PDT 24
Peak memory 200128 kb
Host smart-bc9aa92a-0bf5-44d9-8ba0-020586e3ddda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208476773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1208476773
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3899773244
Short name T391
Test name
Test status
Simulation time 2385057535 ps
CPU time 9.29 seconds
Started May 07 12:35:13 PM PDT 24
Finished May 07 12:35:24 PM PDT 24
Peak memory 222352 kb
Host smart-6d6701d1-7291-4d6a-89b0-43ccef1558bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899773244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3899773244
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1100268210
Short name T469
Test name
Test status
Simulation time 244238967 ps
CPU time 1.08 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 217868 kb
Host smart-183d399b-efa8-4c1e-b7f7-07afba5abd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100268210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1100268210
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3874778901
Short name T212
Test name
Test status
Simulation time 179666426 ps
CPU time 0.85 seconds
Started May 07 12:35:14 PM PDT 24
Finished May 07 12:35:16 PM PDT 24
Peak memory 200500 kb
Host smart-987851fa-6e07-42db-8e7d-dc2a0e944f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874778901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3874778901
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.657393063
Short name T485
Test name
Test status
Simulation time 1702713207 ps
CPU time 6.01 seconds
Started May 07 12:35:22 PM PDT 24
Finished May 07 12:35:30 PM PDT 24
Peak memory 201024 kb
Host smart-cebc1aac-1402-43ff-9066-6e7239641487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657393063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.657393063
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.722403165
Short name T61
Test name
Test status
Simulation time 10908525264 ps
CPU time 17.85 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:47 PM PDT 24
Peak memory 217672 kb
Host smart-9ccec527-c647-4886-b896-8966e1cb06e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722403165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.722403165
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.217427717
Short name T205
Test name
Test status
Simulation time 175402852 ps
CPU time 1.2 seconds
Started May 07 12:35:10 PM PDT 24
Finished May 07 12:35:13 PM PDT 24
Peak memory 200844 kb
Host smart-3f997a65-c7af-4ed9-97f3-692cb97484cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217427717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.217427717
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1517451579
Short name T429
Test name
Test status
Simulation time 188405369 ps
CPU time 1.48 seconds
Started May 07 12:35:13 PM PDT 24
Finished May 07 12:35:16 PM PDT 24
Peak memory 200936 kb
Host smart-9736624d-bedd-428d-b70b-0184f6771286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517451579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1517451579
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2900711602
Short name T217
Test name
Test status
Simulation time 2883338865 ps
CPU time 14.94 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:50 PM PDT 24
Peak memory 209672 kb
Host smart-c7d6aa8e-7f6f-4a5d-999d-974fd9dd3c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900711602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2900711602
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1939596040
Short name T156
Test name
Test status
Simulation time 130905029 ps
CPU time 1.77 seconds
Started May 07 12:35:11 PM PDT 24
Finished May 07 12:35:14 PM PDT 24
Peak memory 209280 kb
Host smart-e7669ef6-75c6-4f9d-8b85-72516e2b91a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939596040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1939596040
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.590684512
Short name T306
Test name
Test status
Simulation time 132691619 ps
CPU time 1.11 seconds
Started May 07 12:35:07 PM PDT 24
Finished May 07 12:35:10 PM PDT 24
Peak memory 200744 kb
Host smart-f073a4c8-aaea-4988-81cf-9a7c02efbf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590684512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.590684512
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2563593340
Short name T72
Test name
Test status
Simulation time 78957036 ps
CPU time 0.82 seconds
Started May 07 12:35:58 PM PDT 24
Finished May 07 12:36:00 PM PDT 24
Peak memory 200604 kb
Host smart-ee942dea-9681-4531-af5d-bcf30a59d620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563593340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2563593340
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.164650769
Short name T412
Test name
Test status
Simulation time 1878537800 ps
CPU time 7.09 seconds
Started May 07 12:36:10 PM PDT 24
Finished May 07 12:36:19 PM PDT 24
Peak memory 218484 kb
Host smart-b7d11d0f-ee53-4e23-a54b-a2eb709e9648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164650769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.164650769
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3052744484
Short name T202
Test name
Test status
Simulation time 246542136 ps
CPU time 1.11 seconds
Started May 07 12:36:06 PM PDT 24
Finished May 07 12:36:10 PM PDT 24
Peak memory 217936 kb
Host smart-f48d486a-60c1-4b3b-b815-4b9a266ab97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052744484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3052744484
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1552567927
Short name T325
Test name
Test status
Simulation time 124658122 ps
CPU time 0.85 seconds
Started May 07 12:36:21 PM PDT 24
Finished May 07 12:36:34 PM PDT 24
Peak memory 200648 kb
Host smart-9830de6b-f757-4bca-b659-b6ff7ad7ebc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552567927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1552567927
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3652768873
Short name T436
Test name
Test status
Simulation time 1976799506 ps
CPU time 7.96 seconds
Started May 07 12:36:12 PM PDT 24
Finished May 07 12:36:22 PM PDT 24
Peak memory 200896 kb
Host smart-d058a9c2-ef36-4ea3-8dbb-ddaa4cba0118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652768873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3652768873
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3881119927
Short name T151
Test name
Test status
Simulation time 177994699 ps
CPU time 1.22 seconds
Started May 07 12:36:07 PM PDT 24
Finished May 07 12:36:10 PM PDT 24
Peak memory 200828 kb
Host smart-7f85fd6e-7684-4d3c-8d4c-34cffec721c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881119927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3881119927
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2134599883
Short name T320
Test name
Test status
Simulation time 206150251 ps
CPU time 1.41 seconds
Started May 07 12:36:10 PM PDT 24
Finished May 07 12:36:14 PM PDT 24
Peak memory 200900 kb
Host smart-b8b573b2-4de3-4552-b4cd-fde45a2beebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134599883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2134599883
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1588031426
Short name T220
Test name
Test status
Simulation time 6611214490 ps
CPU time 24.24 seconds
Started May 07 12:36:10 PM PDT 24
Finished May 07 12:36:36 PM PDT 24
Peak memory 201084 kb
Host smart-ae98ab2d-1240-44a7-bd3f-f7b3b40c56ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588031426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1588031426
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.504444066
Short name T248
Test name
Test status
Simulation time 335320579 ps
CPU time 2.05 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:27 PM PDT 24
Peak memory 200844 kb
Host smart-ac34ed76-9518-41cf-aaf8-1859ef3fb301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504444066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.504444066
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.772979579
Short name T186
Test name
Test status
Simulation time 160082413 ps
CPU time 1.33 seconds
Started May 07 12:36:09 PM PDT 24
Finished May 07 12:36:13 PM PDT 24
Peak memory 200964 kb
Host smart-28c2e680-b5aa-47d4-96c5-3855120a158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772979579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.772979579
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1112718187
Short name T361
Test name
Test status
Simulation time 89826770 ps
CPU time 0.87 seconds
Started May 07 12:36:04 PM PDT 24
Finished May 07 12:36:06 PM PDT 24
Peak memory 200600 kb
Host smart-85bff2cf-0ca3-48e4-8f12-5710c49186fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112718187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1112718187
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3385747356
Short name T44
Test name
Test status
Simulation time 1224712215 ps
CPU time 5.73 seconds
Started May 07 12:36:14 PM PDT 24
Finished May 07 12:36:22 PM PDT 24
Peak memory 218484 kb
Host smart-46ad1fa2-2039-45f9-b0d3-e0261ab7d521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385747356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3385747356
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3087509401
Short name T142
Test name
Test status
Simulation time 245157351 ps
CPU time 1.15 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:36:21 PM PDT 24
Peak memory 218044 kb
Host smart-cd9192a8-2636-4fa1-90ad-c9cda09bef31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087509401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3087509401
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.577442313
Short name T475
Test name
Test status
Simulation time 184864329 ps
CPU time 0.9 seconds
Started May 07 12:36:10 PM PDT 24
Finished May 07 12:36:13 PM PDT 24
Peak memory 200628 kb
Host smart-b2c45b99-74e8-434f-81cc-fa17f90ee97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577442313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.577442313
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3424104120
Short name T79
Test name
Test status
Simulation time 1536871672 ps
CPU time 6.32 seconds
Started May 07 12:36:13 PM PDT 24
Finished May 07 12:36:21 PM PDT 24
Peak memory 201084 kb
Host smart-36b5fbb3-717e-43f9-b3b3-065bb2d8998e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424104120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3424104120
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.135943862
Short name T269
Test name
Test status
Simulation time 150440521 ps
CPU time 1.19 seconds
Started May 07 12:36:06 PM PDT 24
Finished May 07 12:36:08 PM PDT 24
Peak memory 200832 kb
Host smart-dae256ae-c3a0-4190-bdc3-a25e40525221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135943862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.135943862
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2907271866
Short name T441
Test name
Test status
Simulation time 114662289 ps
CPU time 1.24 seconds
Started May 07 12:36:01 PM PDT 24
Finished May 07 12:36:04 PM PDT 24
Peak memory 200904 kb
Host smart-6e3d0c0b-f881-4ad5-b2ce-c1ab45c7ec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907271866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2907271866
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3801607589
Short name T302
Test name
Test status
Simulation time 1737951383 ps
CPU time 8.53 seconds
Started May 07 12:36:09 PM PDT 24
Finished May 07 12:36:20 PM PDT 24
Peak memory 209132 kb
Host smart-62917d79-a0c6-4d06-900e-c198b5fde169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801607589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3801607589
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3017606796
Short name T135
Test name
Test status
Simulation time 504497396 ps
CPU time 2.72 seconds
Started May 07 12:36:04 PM PDT 24
Finished May 07 12:36:09 PM PDT 24
Peak memory 200744 kb
Host smart-abed0638-83d9-4f86-a7e8-a37ba8a11992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017606796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3017606796
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3710140152
Short name T415
Test name
Test status
Simulation time 133705933 ps
CPU time 1.08 seconds
Started May 07 12:36:13 PM PDT 24
Finished May 07 12:36:16 PM PDT 24
Peak memory 200796 kb
Host smart-07e4e7a8-1b73-48d3-b22b-75be1eede3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710140152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3710140152
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.525605337
Short name T211
Test name
Test status
Simulation time 60028882 ps
CPU time 0.73 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:22 PM PDT 24
Peak memory 200672 kb
Host smart-73b994b5-14b4-4240-af46-2668d4308050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525605337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.525605337
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.223349661
Short name T9
Test name
Test status
Simulation time 2175265108 ps
CPU time 8.08 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 222564 kb
Host smart-897a99cf-7ca7-4d22-8dad-1b8f481da020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223349661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.223349661
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2057263964
Short name T232
Test name
Test status
Simulation time 244702541 ps
CPU time 1.17 seconds
Started May 07 12:36:14 PM PDT 24
Finished May 07 12:36:17 PM PDT 24
Peak memory 217940 kb
Host smart-7a064eeb-6629-47fc-98c5-cb35b09e38b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057263964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2057263964
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.104365895
Short name T229
Test name
Test status
Simulation time 130320633 ps
CPU time 0.78 seconds
Started May 07 12:36:14 PM PDT 24
Finished May 07 12:36:17 PM PDT 24
Peak memory 200600 kb
Host smart-92c5d805-16a5-4c56-b0d8-00400082ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104365895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.104365895
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.216981946
Short name T330
Test name
Test status
Simulation time 847571118 ps
CPU time 4.24 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:36:24 PM PDT 24
Peak memory 200984 kb
Host smart-377d0e70-8506-4f43-80b3-7a1064602a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216981946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.216981946
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.338843870
Short name T538
Test name
Test status
Simulation time 109242181 ps
CPU time 1.02 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:24 PM PDT 24
Peak memory 198800 kb
Host smart-686d39e9-8650-4e78-8f56-2a68aebdde67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338843870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.338843870
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1214818135
Short name T78
Test name
Test status
Simulation time 195166532 ps
CPU time 1.35 seconds
Started May 07 12:36:13 PM PDT 24
Finished May 07 12:36:16 PM PDT 24
Peak memory 200984 kb
Host smart-d9ca3643-568e-494c-a290-4597b4b3e328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214818135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1214818135
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.870575979
Short name T33
Test name
Test status
Simulation time 215368058 ps
CPU time 1.19 seconds
Started May 07 12:36:14 PM PDT 24
Finished May 07 12:36:17 PM PDT 24
Peak memory 200772 kb
Host smart-0de26abd-d5f8-4783-9d69-10fc0069e2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870575979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.870575979
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3805674767
Short name T403
Test name
Test status
Simulation time 135163979 ps
CPU time 1.83 seconds
Started May 07 12:36:09 PM PDT 24
Finished May 07 12:36:13 PM PDT 24
Peak memory 200840 kb
Host smart-6b5e9b60-9a2c-4a4a-a429-6f09c57e6b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805674767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3805674767
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2932593548
Short name T478
Test name
Test status
Simulation time 207208182 ps
CPU time 1.33 seconds
Started May 07 12:36:12 PM PDT 24
Finished May 07 12:36:15 PM PDT 24
Peak memory 200804 kb
Host smart-4b1b03dd-4277-473a-bc91-310cf1529f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932593548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2932593548
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1027168144
Short name T282
Test name
Test status
Simulation time 69073333 ps
CPU time 0.79 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 198232 kb
Host smart-44e60557-7cc8-41a0-8939-6bad483a3d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027168144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1027168144
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.4293937571
Short name T36
Test name
Test status
Simulation time 1219712315 ps
CPU time 5.33 seconds
Started May 07 12:36:23 PM PDT 24
Finished May 07 12:36:32 PM PDT 24
Peak memory 218428 kb
Host smart-a74913ec-c73b-40d6-a79f-d5eff4cf7cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293937571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4293937571
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1069014812
Short name T295
Test name
Test status
Simulation time 244368195 ps
CPU time 1.13 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:36:20 PM PDT 24
Peak memory 217912 kb
Host smart-1ebce4d8-d84a-4809-b6da-475f633cbced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069014812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1069014812
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2167290693
Short name T253
Test name
Test status
Simulation time 87774446 ps
CPU time 0.74 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 200532 kb
Host smart-63783655-4c41-41e8-89b3-c27696601e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167290693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2167290693
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.130916769
Short name T274
Test name
Test status
Simulation time 1947722773 ps
CPU time 7.44 seconds
Started May 07 12:36:14 PM PDT 24
Finished May 07 12:36:23 PM PDT 24
Peak memory 201040 kb
Host smart-a561592a-e7ed-4e94-a566-ef28cc0504ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130916769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.130916769
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3719118321
Short name T540
Test name
Test status
Simulation time 96820068 ps
CPU time 1.07 seconds
Started May 07 12:36:00 PM PDT 24
Finished May 07 12:36:02 PM PDT 24
Peak memory 200808 kb
Host smart-1e02acb9-6218-417d-aa28-6ac2cc4d768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719118321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3719118321
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.4135304050
Short name T495
Test name
Test status
Simulation time 189779063 ps
CPU time 1.34 seconds
Started May 07 12:36:14 PM PDT 24
Finished May 07 12:36:18 PM PDT 24
Peak memory 200996 kb
Host smart-9b3d141e-19a2-4218-b94c-2d835cebbd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135304050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.4135304050
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2129319573
Short name T288
Test name
Test status
Simulation time 15931194963 ps
CPU time 51.55 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:37:14 PM PDT 24
Peak memory 201120 kb
Host smart-2d10b9e4-d513-447f-ad49-8c2078b37040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129319573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2129319573
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2621260416
Short name T164
Test name
Test status
Simulation time 126872259 ps
CPU time 1.42 seconds
Started May 07 12:36:02 PM PDT 24
Finished May 07 12:36:05 PM PDT 24
Peak memory 200772 kb
Host smart-0028b7b9-8a3a-43dc-85a8-292617894df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621260416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2621260416
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3846444427
Short name T505
Test name
Test status
Simulation time 114981604 ps
CPU time 0.9 seconds
Started May 07 12:36:23 PM PDT 24
Finished May 07 12:36:27 PM PDT 24
Peak memory 200804 kb
Host smart-87b9c0df-04d4-4c9b-ae03-8ea3985a8216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846444427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3846444427
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2417899928
Short name T172
Test name
Test status
Simulation time 71146419 ps
CPU time 0.76 seconds
Started May 07 12:36:14 PM PDT 24
Finished May 07 12:36:17 PM PDT 24
Peak memory 200636 kb
Host smart-7fe31ec4-81fb-44e8-853e-bec39845d468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417899928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2417899928
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2837358746
Short name T407
Test name
Test status
Simulation time 1237341397 ps
CPU time 5.87 seconds
Started May 07 12:37:48 PM PDT 24
Finished May 07 12:37:56 PM PDT 24
Peak memory 218320 kb
Host smart-74cbc73f-0a30-4b27-9661-b271a9eb418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837358746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2837358746
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3503572542
Short name T395
Test name
Test status
Simulation time 244775166 ps
CPU time 1.21 seconds
Started May 07 12:36:13 PM PDT 24
Finished May 07 12:36:16 PM PDT 24
Peak memory 218076 kb
Host smart-87b4d853-ee08-404b-9554-7b473212f0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503572542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3503572542
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2006441371
Short name T340
Test name
Test status
Simulation time 155410560 ps
CPU time 0.89 seconds
Started May 07 12:36:13 PM PDT 24
Finished May 07 12:36:15 PM PDT 24
Peak memory 200632 kb
Host smart-452fc459-fbad-47b7-bfee-b7f5a53a2b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006441371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2006441371
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.568779340
Short name T108
Test name
Test status
Simulation time 1879425003 ps
CPU time 6.73 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 198652 kb
Host smart-cb4942d4-7513-43e2-af49-e262a414098c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568779340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.568779340
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1699063042
Short name T365
Test name
Test status
Simulation time 97455783 ps
CPU time 1 seconds
Started May 07 12:36:11 PM PDT 24
Finished May 07 12:36:14 PM PDT 24
Peak memory 200812 kb
Host smart-f3926c2e-6e8f-4666-a774-9ba7517a0d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699063042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1699063042
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3941286465
Short name T177
Test name
Test status
Simulation time 247740232 ps
CPU time 1.4 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:23 PM PDT 24
Peak memory 200984 kb
Host smart-cef65fd7-eb6c-4c2c-90b6-3a88a46196ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941286465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3941286465
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3881006586
Short name T84
Test name
Test status
Simulation time 5752454799 ps
CPU time 20.81 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:44 PM PDT 24
Peak memory 209356 kb
Host smart-99dcf624-cf0b-4d41-a068-c38dc33772b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881006586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3881006586
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3351064276
Short name T131
Test name
Test status
Simulation time 129413030 ps
CPU time 0.99 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:36:20 PM PDT 24
Peak memory 200796 kb
Host smart-0f49efbb-8c25-477f-a54c-0d5e1c01628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351064276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3351064276
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3590829179
Short name T143
Test name
Test status
Simulation time 57229998 ps
CPU time 0.74 seconds
Started May 07 12:37:47 PM PDT 24
Finished May 07 12:37:48 PM PDT 24
Peak memory 200476 kb
Host smart-eb646903-5163-40dc-9ff7-3f73c0017692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590829179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3590829179
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.387763156
Short name T35
Test name
Test status
Simulation time 1224701212 ps
CPU time 5.35 seconds
Started May 07 12:36:04 PM PDT 24
Finished May 07 12:36:11 PM PDT 24
Peak memory 218328 kb
Host smart-bafa5846-5135-407e-8b8a-17416f48b520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387763156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.387763156
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3889048014
Short name T252
Test name
Test status
Simulation time 245290722 ps
CPU time 1.09 seconds
Started May 07 12:36:02 PM PDT 24
Finished May 07 12:36:04 PM PDT 24
Peak memory 217980 kb
Host smart-51f9bb91-0487-450f-a595-89dec99def36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889048014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3889048014
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1135216407
Short name T16
Test name
Test status
Simulation time 82244844 ps
CPU time 0.72 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:25 PM PDT 24
Peak memory 200580 kb
Host smart-a281e3cf-9d9f-4f8f-ae1f-1fc4701300f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135216407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1135216407
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2806203172
Short name T257
Test name
Test status
Simulation time 1778536295 ps
CPU time 6.16 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:30 PM PDT 24
Peak memory 200744 kb
Host smart-671e4e0e-95e4-4870-b3a6-ec060c7f10a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806203172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2806203172
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.4246241471
Short name T157
Test name
Test status
Simulation time 166120498 ps
CPU time 1.19 seconds
Started May 07 12:36:04 PM PDT 24
Finished May 07 12:36:07 PM PDT 24
Peak memory 200844 kb
Host smart-19f19756-bf27-467c-862d-2ab75717a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246241471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.4246241471
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1462892969
Short name T399
Test name
Test status
Simulation time 112541091 ps
CPU time 1.16 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:24 PM PDT 24
Peak memory 201004 kb
Host smart-f38730f0-395d-43ed-87a4-a1c31ad2f3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462892969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1462892969
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2768121200
Short name T337
Test name
Test status
Simulation time 5030237274 ps
CPU time 16.86 seconds
Started May 07 12:37:31 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 201140 kb
Host smart-bceabd5e-f972-404a-afae-d42c4e620282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768121200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2768121200
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2158978100
Short name T52
Test name
Test status
Simulation time 306746168 ps
CPU time 2.04 seconds
Started May 07 12:36:21 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 200812 kb
Host smart-4bcc5c78-7205-4f64-90f1-72ab397950a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158978100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2158978100
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.4090223114
Short name T351
Test name
Test status
Simulation time 133619286 ps
CPU time 1.22 seconds
Started May 07 12:36:02 PM PDT 24
Finished May 07 12:36:05 PM PDT 24
Peak memory 200808 kb
Host smart-d9077944-7146-4f44-99bf-90a899721d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090223114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4090223114
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1511060888
Short name T140
Test name
Test status
Simulation time 70113255 ps
CPU time 0.79 seconds
Started May 07 12:37:43 PM PDT 24
Finished May 07 12:37:45 PM PDT 24
Peak memory 200484 kb
Host smart-b228c9f7-c2d9-494b-bff2-a6cd0751b92b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511060888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1511060888
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1945162708
Short name T377
Test name
Test status
Simulation time 1223994038 ps
CPU time 5.03 seconds
Started May 07 12:37:31 PM PDT 24
Finished May 07 12:37:38 PM PDT 24
Peak memory 218460 kb
Host smart-85d42347-330c-469d-9791-cd3a3ec33d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945162708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1945162708
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2507166237
Short name T133
Test name
Test status
Simulation time 249406723 ps
CPU time 1.03 seconds
Started May 07 12:37:47 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 217772 kb
Host smart-f6472561-4325-4eed-a7b8-6b424bdc07ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507166237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2507166237
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3284707943
Short name T360
Test name
Test status
Simulation time 201157694 ps
CPU time 0.91 seconds
Started May 07 12:37:19 PM PDT 24
Finished May 07 12:37:24 PM PDT 24
Peak memory 198992 kb
Host smart-aa80f169-891d-40e7-9bd1-f2f4a7015be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284707943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3284707943
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3495354284
Short name T510
Test name
Test status
Simulation time 1013450558 ps
CPU time 4.53 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:33 PM PDT 24
Peak memory 201052 kb
Host smart-cd125983-8060-4ae1-8a49-803b42d452c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495354284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3495354284
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3979457820
Short name T536
Test name
Test status
Simulation time 104990545 ps
CPU time 1.08 seconds
Started May 07 12:36:06 PM PDT 24
Finished May 07 12:36:09 PM PDT 24
Peak memory 200808 kb
Host smart-88d61b15-7403-4d24-ad1e-7fd273d8b4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979457820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3979457820
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.549244853
Short name T385
Test name
Test status
Simulation time 117027577 ps
CPU time 1.13 seconds
Started May 07 12:37:19 PM PDT 24
Finished May 07 12:37:24 PM PDT 24
Peak memory 199516 kb
Host smart-1b024754-833d-4e47-826a-609e01db5287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549244853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.549244853
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3931273324
Short name T513
Test name
Test status
Simulation time 2187582804 ps
CPU time 7.9 seconds
Started May 07 12:36:09 PM PDT 24
Finished May 07 12:36:19 PM PDT 24
Peak memory 201360 kb
Host smart-aa6f7570-4f8d-4f3b-bcc2-75552356adc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931273324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3931273324
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.734966919
Short name T484
Test name
Test status
Simulation time 450698374 ps
CPU time 2.45 seconds
Started May 07 12:36:11 PM PDT 24
Finished May 07 12:36:15 PM PDT 24
Peak memory 200832 kb
Host smart-ef214c2a-dfcc-4cde-87a1-996b00f6fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734966919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.734966919
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2747290124
Short name T144
Test name
Test status
Simulation time 128359979 ps
CPU time 1.08 seconds
Started May 07 12:36:21 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 200816 kb
Host smart-8dcfb636-2413-459e-9d3a-7d219812f0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747290124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2747290124
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1628621221
Short name T291
Test name
Test status
Simulation time 81108396 ps
CPU time 0.85 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:24 PM PDT 24
Peak memory 198788 kb
Host smart-db1e513a-bdba-4ba8-a462-93fb3cfcdc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628621221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1628621221
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1291913465
Short name T216
Test name
Test status
Simulation time 1893844456 ps
CPU time 6.54 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 216988 kb
Host smart-dee4997c-b5d8-4f47-b389-5bf134c9c30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291913465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1291913465
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2776369814
Short name T284
Test name
Test status
Simulation time 244736682 ps
CPU time 1.05 seconds
Started May 07 12:36:10 PM PDT 24
Finished May 07 12:36:13 PM PDT 24
Peak memory 218044 kb
Host smart-431c7eff-74df-4295-a8b2-12048911a961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776369814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2776369814
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.959494987
Short name T23
Test name
Test status
Simulation time 234189613 ps
CPU time 0.94 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:36:22 PM PDT 24
Peak memory 200580 kb
Host smart-4d926eeb-9484-44db-a29b-5845b0014c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959494987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.959494987
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.78772962
Short name T299
Test name
Test status
Simulation time 1505506237 ps
CPU time 6.56 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:29 PM PDT 24
Peak memory 200496 kb
Host smart-c8e01817-4ae3-460b-abf9-d9a25e122cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78772962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.78772962
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2366777888
Short name T203
Test name
Test status
Simulation time 143481165 ps
CPU time 1.08 seconds
Started May 07 12:36:05 PM PDT 24
Finished May 07 12:36:08 PM PDT 24
Peak memory 200840 kb
Host smart-b51b07ee-5237-4bd4-a4b8-e58f746b1b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366777888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2366777888
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2974870260
Short name T450
Test name
Test status
Simulation time 197319674 ps
CPU time 1.46 seconds
Started May 07 12:36:08 PM PDT 24
Finished May 07 12:36:12 PM PDT 24
Peak memory 201240 kb
Host smart-4587902e-d4ab-456a-b466-36b84e59d5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974870260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2974870260
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2177830897
Short name T413
Test name
Test status
Simulation time 472744113 ps
CPU time 2.55 seconds
Started May 07 12:36:11 PM PDT 24
Finished May 07 12:36:16 PM PDT 24
Peak memory 200776 kb
Host smart-88cb1525-2e8d-4258-bd7b-03104a573a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177830897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2177830897
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3760126426
Short name T541
Test name
Test status
Simulation time 106411626 ps
CPU time 0.95 seconds
Started May 07 12:36:09 PM PDT 24
Finished May 07 12:36:13 PM PDT 24
Peak memory 200788 kb
Host smart-e82c17bc-89ba-45e4-bc48-7d641693f175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760126426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3760126426
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.279396260
Short name T537
Test name
Test status
Simulation time 66194796 ps
CPU time 0.77 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 200304 kb
Host smart-6f41dc40-f4ba-4d25-87f3-92611c2fc963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279396260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.279396260
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1324381144
Short name T333
Test name
Test status
Simulation time 2359665184 ps
CPU time 8.45 seconds
Started May 07 12:37:48 PM PDT 24
Finished May 07 12:37:59 PM PDT 24
Peak memory 218140 kb
Host smart-4f93b21e-9c8d-45b5-bcc5-0d9779b10538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324381144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1324381144
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.364784703
Short name T452
Test name
Test status
Simulation time 244610999 ps
CPU time 1.08 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:23 PM PDT 24
Peak memory 217984 kb
Host smart-b65ce38b-cd1d-469a-b202-ffb64af01442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364784703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.364784703
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3376165713
Short name T219
Test name
Test status
Simulation time 181118897 ps
CPU time 0.83 seconds
Started May 07 12:36:11 PM PDT 24
Finished May 07 12:36:14 PM PDT 24
Peak memory 200628 kb
Host smart-29bac604-5d30-49cb-ab83-b482118979c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376165713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3376165713
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2451763833
Short name T128
Test name
Test status
Simulation time 1573118505 ps
CPU time 6.28 seconds
Started May 07 12:36:09 PM PDT 24
Finished May 07 12:36:17 PM PDT 24
Peak memory 200984 kb
Host smart-c10a2dff-f973-422c-a5e1-ba2077c6152b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451763833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2451763833
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.867496639
Short name T331
Test name
Test status
Simulation time 178277081 ps
CPU time 1.17 seconds
Started May 07 12:35:59 PM PDT 24
Finished May 07 12:36:02 PM PDT 24
Peak memory 200680 kb
Host smart-7c89a146-3a94-4d23-a0a2-599bddfbfdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867496639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.867496639
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1422383429
Short name T497
Test name
Test status
Simulation time 115735439 ps
CPU time 1.19 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:19 PM PDT 24
Peak memory 200980 kb
Host smart-716756bb-2042-422b-a2bf-67e2e55d9dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422383429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1422383429
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2814007272
Short name T317
Test name
Test status
Simulation time 12149743768 ps
CPU time 39.47 seconds
Started May 07 12:36:25 PM PDT 24
Finished May 07 12:37:07 PM PDT 24
Peak memory 201168 kb
Host smart-1062a9ba-5756-4716-a83b-da0a308b53f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814007272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2814007272
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4107977069
Short name T506
Test name
Test status
Simulation time 134082155 ps
CPU time 1.7 seconds
Started May 07 12:36:13 PM PDT 24
Finished May 07 12:36:16 PM PDT 24
Peak memory 200828 kb
Host smart-584737b8-96c2-4729-ac6e-678546abab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107977069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4107977069
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2021097007
Short name T250
Test name
Test status
Simulation time 72481220 ps
CPU time 0.86 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 200316 kb
Host smart-536fbb56-1dd8-495c-a478-fc86e7b7e730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021097007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2021097007
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.558589647
Short name T341
Test name
Test status
Simulation time 62412314 ps
CPU time 0.73 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:24 PM PDT 24
Peak memory 200640 kb
Host smart-83812d7a-88b4-4c09-99b6-27238625a0c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558589647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.558589647
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2576355810
Short name T271
Test name
Test status
Simulation time 1930471603 ps
CPU time 6.91 seconds
Started May 07 12:36:21 PM PDT 24
Finished May 07 12:36:31 PM PDT 24
Peak memory 217412 kb
Host smart-45c931f9-61e7-46a2-8620-f652bf92af38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576355810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2576355810
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3687072379
Short name T146
Test name
Test status
Simulation time 244274233 ps
CPU time 1.08 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 217988 kb
Host smart-b821fd99-76f3-4d43-849c-1c7894cfd9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687072379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3687072379
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.488983959
Short name T420
Test name
Test status
Simulation time 154368203 ps
CPU time 0.85 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:24 PM PDT 24
Peak memory 200592 kb
Host smart-7f7e5abd-e633-45b1-a9a9-5248bc518925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488983959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.488983959
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.372355613
Short name T234
Test name
Test status
Simulation time 899370543 ps
CPU time 4.28 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 200936 kb
Host smart-95de62cb-3898-4fcb-8195-1c36f9f78148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372355613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.372355613
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3056217324
Short name T410
Test name
Test status
Simulation time 153871477 ps
CPU time 1.16 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 200828 kb
Host smart-23db3c6e-f75e-4ee8-8113-419bd1d2e2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056217324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3056217324
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1112392472
Short name T339
Test name
Test status
Simulation time 206367262 ps
CPU time 1.35 seconds
Started May 07 12:36:31 PM PDT 24
Finished May 07 12:36:34 PM PDT 24
Peak memory 201056 kb
Host smart-6cdfa4a8-8a10-4738-91e6-0a9939c0600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112392472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1112392472
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.576158205
Short name T260
Test name
Test status
Simulation time 15151315043 ps
CPU time 54.77 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:37:14 PM PDT 24
Peak memory 209312 kb
Host smart-63961cc4-10a9-4061-9db6-1c21e11710ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576158205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.576158205
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3743103996
Short name T498
Test name
Test status
Simulation time 343914758 ps
CPU time 2.21 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:27 PM PDT 24
Peak memory 200836 kb
Host smart-56e9d027-644e-4771-8021-83eaa8fe0604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743103996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3743103996
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.673386210
Short name T168
Test name
Test status
Simulation time 69189427 ps
CPU time 0.78 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 200800 kb
Host smart-2134cdae-99ae-4709-8280-32a2920a8d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673386210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.673386210
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.492508583
Short name T424
Test name
Test status
Simulation time 61314065 ps
CPU time 0.83 seconds
Started May 07 12:35:16 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 200532 kb
Host smart-b0e55766-9716-413e-908e-59e1ee050209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492508583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.492508583
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.4047936983
Short name T45
Test name
Test status
Simulation time 1889711868 ps
CPU time 7.1 seconds
Started May 07 12:35:17 PM PDT 24
Finished May 07 12:35:25 PM PDT 24
Peak memory 217780 kb
Host smart-83d22d67-e0ee-422f-a3e2-08acdec61625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047936983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4047936983
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2493701648
Short name T214
Test name
Test status
Simulation time 244076252 ps
CPU time 1.06 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 217856 kb
Host smart-05697ebe-1860-4324-805c-afae48d87d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493701648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2493701648
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1861898175
Short name T332
Test name
Test status
Simulation time 229952670 ps
CPU time 0.92 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:33 PM PDT 24
Peak memory 200560 kb
Host smart-5fe130ba-78a7-4287-a65a-0a77d1d7f12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861898175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1861898175
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4131442321
Short name T544
Test name
Test status
Simulation time 1215833413 ps
CPU time 4.63 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:35 PM PDT 24
Peak memory 200984 kb
Host smart-db0355d4-d64e-46ae-aa5d-18dc6d2791e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131442321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4131442321
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2510205470
Short name T25
Test name
Test status
Simulation time 150910754 ps
CPU time 1.17 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 200784 kb
Host smart-e63b0ad9-acf9-42d4-9a1c-f72a51c97488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510205470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2510205470
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2728499869
Short name T76
Test name
Test status
Simulation time 225456121 ps
CPU time 1.53 seconds
Started May 07 12:35:15 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 200908 kb
Host smart-453b3fba-fb88-4c17-93fb-059c163b4b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728499869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2728499869
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2097184452
Short name T99
Test name
Test status
Simulation time 5136664210 ps
CPU time 18.18 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:46 PM PDT 24
Peak memory 201052 kb
Host smart-292c800e-349a-4962-baaf-ea3ec6e62c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097184452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2097184452
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1329176345
Short name T471
Test name
Test status
Simulation time 299903729 ps
CPU time 2.09 seconds
Started May 07 12:35:18 PM PDT 24
Finished May 07 12:35:22 PM PDT 24
Peak memory 208964 kb
Host smart-2378ad63-5bff-45d9-a07d-60ff230a592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329176345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1329176345
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3450851570
Short name T258
Test name
Test status
Simulation time 89064299 ps
CPU time 0.84 seconds
Started May 07 12:35:23 PM PDT 24
Finished May 07 12:35:27 PM PDT 24
Peak memory 200928 kb
Host smart-59091264-9a1e-48f2-94e0-01a22ba01ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450851570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3450851570
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3162735754
Short name T439
Test name
Test status
Simulation time 79692493 ps
CPU time 0.82 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:29 PM PDT 24
Peak memory 200560 kb
Host smart-e3ab4dd6-b89b-4872-90bc-6d72e6ffd2dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162735754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3162735754
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1284619642
Short name T265
Test name
Test status
Simulation time 1901829529 ps
CPU time 6.77 seconds
Started May 07 12:35:14 PM PDT 24
Finished May 07 12:35:23 PM PDT 24
Peak memory 222452 kb
Host smart-74ea2fe5-6861-449d-a587-e5d30c9f831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284619642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1284619642
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3726095931
Short name T160
Test name
Test status
Simulation time 244292512 ps
CPU time 1.03 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 217856 kb
Host smart-4f090b6e-d83e-4577-8220-9e1dd8825383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726095931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3726095931
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2840738438
Short name T463
Test name
Test status
Simulation time 78277624 ps
CPU time 0.75 seconds
Started May 07 12:35:15 PM PDT 24
Finished May 07 12:35:17 PM PDT 24
Peak memory 200524 kb
Host smart-32392e2d-1185-44c4-b1b7-ba4a986874b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840738438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2840738438
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3205326361
Short name T449
Test name
Test status
Simulation time 1984719742 ps
CPU time 7.06 seconds
Started May 07 12:35:18 PM PDT 24
Finished May 07 12:35:26 PM PDT 24
Peak memory 201000 kb
Host smart-d021635a-7196-4b29-8634-e4d450287d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205326361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3205326361
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3673606138
Short name T380
Test name
Test status
Simulation time 146286771 ps
CPU time 1.12 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:33 PM PDT 24
Peak memory 200764 kb
Host smart-ff692e29-513c-4bf5-a3bd-cc8b1531e08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673606138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3673606138
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.182225914
Short name T373
Test name
Test status
Simulation time 204700717 ps
CPU time 1.36 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 200800 kb
Host smart-ccad0ba6-b4f8-462f-a02e-b90600f3c8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182225914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.182225914
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1211083513
Short name T171
Test name
Test status
Simulation time 1814291134 ps
CPU time 7.45 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 217252 kb
Host smart-42a6ece2-e27a-478d-ae46-fe33d8079571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211083513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1211083513
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4227630792
Short name T379
Test name
Test status
Simulation time 309317524 ps
CPU time 2.04 seconds
Started May 07 12:35:14 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 208900 kb
Host smart-35ce650b-b1e4-487c-8ba1-da75465eed6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227630792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4227630792
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.776447753
Short name T161
Test name
Test status
Simulation time 165984711 ps
CPU time 1.17 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 200720 kb
Host smart-5ba30b1d-2340-4658-a777-ed3e9cb45918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776447753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.776447753
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1039838957
Short name T47
Test name
Test status
Simulation time 64737434 ps
CPU time 0.76 seconds
Started May 07 12:35:28 PM PDT 24
Finished May 07 12:35:32 PM PDT 24
Peak memory 200636 kb
Host smart-1571fc26-7fc4-4eeb-be20-c8bced6dacec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039838957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1039838957
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2962400793
Short name T489
Test name
Test status
Simulation time 1225536645 ps
CPU time 5.5 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:34 PM PDT 24
Peak memory 218448 kb
Host smart-eec4689c-5421-4dae-b47e-f25136e67cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962400793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2962400793
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1442030108
Short name T511
Test name
Test status
Simulation time 243700175 ps
CPU time 1.1 seconds
Started May 07 12:35:21 PM PDT 24
Finished May 07 12:35:24 PM PDT 24
Peak memory 218056 kb
Host smart-651985bc-f8f5-4d3f-af08-14aad1b5f2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442030108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1442030108
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1738968077
Short name T314
Test name
Test status
Simulation time 167281686 ps
CPU time 0.85 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:29 PM PDT 24
Peak memory 200568 kb
Host smart-4e646576-7b4d-48bb-81ec-035a6691b5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738968077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1738968077
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1670739689
Short name T438
Test name
Test status
Simulation time 1558383982 ps
CPU time 5.8 seconds
Started May 07 12:35:13 PM PDT 24
Finished May 07 12:35:21 PM PDT 24
Peak memory 200924 kb
Host smart-6c45f6cb-3b20-4cf3-8956-598f57c6f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670739689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1670739689
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4212040430
Short name T283
Test name
Test status
Simulation time 183332868 ps
CPU time 1.22 seconds
Started May 07 12:35:20 PM PDT 24
Finished May 07 12:35:23 PM PDT 24
Peak memory 200856 kb
Host smart-d54a3d5d-2c17-489f-bafe-8be7174bd4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212040430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4212040430
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4207234318
Short name T322
Test name
Test status
Simulation time 195578201 ps
CPU time 1.37 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:33 PM PDT 24
Peak memory 200928 kb
Host smart-de9ecd73-9f81-46f2-89e3-5ba283c07f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207234318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4207234318
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.401546364
Short name T338
Test name
Test status
Simulation time 6479340118 ps
CPU time 20.05 seconds
Started May 07 12:35:15 PM PDT 24
Finished May 07 12:35:37 PM PDT 24
Peak memory 201016 kb
Host smart-2cbf01c2-d421-4237-8e80-55ab65203f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401546364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.401546364
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3431178228
Short name T68
Test name
Test status
Simulation time 146199156 ps
CPU time 1.77 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 200796 kb
Host smart-4262d8cf-603c-4e84-9525-6f255ebdc950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431178228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3431178228
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2247890586
Short name T4
Test name
Test status
Simulation time 261613028 ps
CPU time 1.44 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:29 PM PDT 24
Peak memory 200300 kb
Host smart-64f0e05e-b508-4ec0-96c6-e4be219eec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247890586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2247890586
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1747555886
Short name T147
Test name
Test status
Simulation time 60036849 ps
CPU time 0.71 seconds
Started May 07 12:35:19 PM PDT 24
Finished May 07 12:35:22 PM PDT 24
Peak memory 200532 kb
Host smart-d03ae772-cc16-4b7e-b754-60d2e9bedf80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747555886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1747555886
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3052759242
Short name T432
Test name
Test status
Simulation time 2360596357 ps
CPU time 8.57 seconds
Started May 07 12:35:15 PM PDT 24
Finished May 07 12:35:25 PM PDT 24
Peak memory 222344 kb
Host smart-48523a9f-6692-4ae9-a863-aae161a068f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052759242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3052759242
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2282060567
Short name T374
Test name
Test status
Simulation time 244496243 ps
CPU time 1.05 seconds
Started May 07 12:35:20 PM PDT 24
Finished May 07 12:35:24 PM PDT 24
Peak memory 217924 kb
Host smart-e48866eb-82a4-4695-b867-454d8ba01624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282060567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2282060567
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2996484831
Short name T423
Test name
Test status
Simulation time 175666408 ps
CPU time 0.97 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 200656 kb
Host smart-0aa39319-4c41-41fa-86b9-86909809921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996484831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2996484831
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1087331847
Short name T446
Test name
Test status
Simulation time 1377912604 ps
CPU time 6.19 seconds
Started May 07 12:35:24 PM PDT 24
Finished May 07 12:35:33 PM PDT 24
Peak memory 200932 kb
Host smart-5cdb169d-920e-4594-a411-e89a6359eebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087331847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1087331847
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.830807368
Short name T294
Test name
Test status
Simulation time 109450724 ps
CPU time 1.04 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:32 PM PDT 24
Peak memory 200776 kb
Host smart-40056daf-75fd-4072-992f-0fd8c9c49e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830807368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.830807368
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2556967837
Short name T245
Test name
Test status
Simulation time 231746807 ps
CPU time 1.49 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:30 PM PDT 24
Peak memory 200892 kb
Host smart-c830a96e-71ac-409d-87d5-9f8980c12824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556967837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2556967837
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1878176935
Short name T334
Test name
Test status
Simulation time 11831884824 ps
CPU time 41.46 seconds
Started May 07 12:35:12 PM PDT 24
Finished May 07 12:35:56 PM PDT 24
Peak memory 210892 kb
Host smart-2ccacdd8-ec3f-4817-b8a5-10883fd88469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878176935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1878176935
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3214915107
Short name T335
Test name
Test status
Simulation time 375152609 ps
CPU time 2.32 seconds
Started May 07 12:35:12 PM PDT 24
Finished May 07 12:35:16 PM PDT 24
Peak memory 200656 kb
Host smart-c8ab4798-0587-429a-9651-37f02aeee813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214915107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3214915107
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.970864857
Short name T32
Test name
Test status
Simulation time 209191371 ps
CPU time 1.28 seconds
Started May 07 12:35:23 PM PDT 24
Finished May 07 12:35:26 PM PDT 24
Peak memory 200808 kb
Host smart-4b6f623f-3a1b-44b9-acca-787117a614cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970864857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.970864857
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3690723873
Short name T240
Test name
Test status
Simulation time 60148391 ps
CPU time 0.73 seconds
Started May 07 12:35:30 PM PDT 24
Finished May 07 12:35:36 PM PDT 24
Peak memory 200544 kb
Host smart-358ab13c-b299-418e-b545-faf1d18b75d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690723873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3690723873
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.891425114
Short name T526
Test name
Test status
Simulation time 2344847947 ps
CPU time 8.15 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:42 PM PDT 24
Peak memory 221872 kb
Host smart-ba8476eb-7b50-4a6f-9839-397a9ba4d4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891425114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.891425114
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1904449458
Short name T411
Test name
Test status
Simulation time 244494153 ps
CPU time 1.06 seconds
Started May 07 12:35:27 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 217948 kb
Host smart-c9bb8cc9-f011-431b-812b-9a5776abdeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904449458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1904449458
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2240184980
Short name T473
Test name
Test status
Simulation time 197031634 ps
CPU time 0.89 seconds
Started May 07 12:35:15 PM PDT 24
Finished May 07 12:35:18 PM PDT 24
Peak memory 200580 kb
Host smart-cd74b062-9d75-4513-903b-e2ee3e41352d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240184980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2240184980
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1661477871
Short name T400
Test name
Test status
Simulation time 1603408758 ps
CPU time 6.3 seconds
Started May 07 12:35:29 PM PDT 24
Finished May 07 12:35:39 PM PDT 24
Peak memory 201064 kb
Host smart-71384f9c-1f72-41b4-85e3-b6493f228255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661477871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1661477871
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3339669768
Short name T187
Test name
Test status
Simulation time 109535376 ps
CPU time 1.03 seconds
Started May 07 12:35:21 PM PDT 24
Finished May 07 12:35:24 PM PDT 24
Peak memory 200720 kb
Host smart-55d83b7a-80b0-4155-9592-13d6cb76d9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339669768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3339669768
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1857718975
Short name T381
Test name
Test status
Simulation time 192065283 ps
CPU time 1.35 seconds
Started May 07 12:35:26 PM PDT 24
Finished May 07 12:35:31 PM PDT 24
Peak memory 201040 kb
Host smart-20486696-747e-44a0-9efb-be1ee072869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857718975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1857718975
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.641585732
Short name T104
Test name
Test status
Simulation time 4165816664 ps
CPU time 13.45 seconds
Started May 07 12:35:23 PM PDT 24
Finished May 07 12:35:38 PM PDT 24
Peak memory 201064 kb
Host smart-9eec42f5-2993-484a-9d08-ed45144b1f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641585732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.641585732
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2766015648
Short name T345
Test name
Test status
Simulation time 151982346 ps
CPU time 1.97 seconds
Started May 07 12:35:20 PM PDT 24
Finished May 07 12:35:24 PM PDT 24
Peak memory 200864 kb
Host smart-956f117c-1268-469b-8f80-896155191744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766015648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2766015648
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2051842089
Short name T315
Test name
Test status
Simulation time 138152476 ps
CPU time 1.1 seconds
Started May 07 12:35:25 PM PDT 24
Finished May 07 12:35:30 PM PDT 24
Peak memory 200724 kb
Host smart-33139f0a-0b5b-4c39-ab91-854e4835f4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051842089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2051842089
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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