Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8896

1

T6

329

T7

183

T10

90

auto[1]

11682

1

T1

4

T3

4

T6

305

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6315	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6877	1			T1	2		T2	1		T3	2
reset_info_cp[2]	3171	1			T1	1		T3	1		T6	84
reset_info_cp[4]	4228	1			T1	1		T3	1		T6	144
reset_info_cp[8]	112	1			T6	3		T7	3		T10	1
reset_info_cp[16]	132	1			T6	5		T7	2		T10	1
reset_info_cp[32]	106	1			T6	2		T7	1		T10	1
reset_info_cp[64]	130	1			T6	4		T10	1		T13	1
reset_info_cp[128]	127	1			T6	2		T7	1		T10	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3273	1			T6	95		T7	55		T10	29
reset_info_cp[1]	auto[1]	2984	1			T1	1		T3	1		T6	108
reset_info_cp[2]	auto[0]	1068	1			T6	43		T7	22		T10	14
reset_info_cp[2]	auto[1]	2103	1			T1	1		T3	1		T6	41
reset_info_cp[4]	auto[0]	1553	1			T6	65		T7	44		T10	22
reset_info_cp[4]	auto[1]	2675	1			T1	1		T3	1		T6	79
reset_info_cp[8]	auto[0]	42	1			T6	2		T83	1		T128	1
reset_info_cp[8]	auto[1]	70	1			T6	1		T7	3		T10	1
reset_info_cp[16]	auto[0]	54	1			T6	3		T7	1		T10	1
reset_info_cp[16]	auto[1]	78	1			T6	2		T7	1		T79	1
reset_info_cp[32]	auto[0]	36	1			T6	1		T7	1		T11	1
reset_info_cp[32]	auto[1]	70	1			T6	1		T10	1		T109	1
reset_info_cp[64]	auto[0]	51	1			T6	2		T79	1		T81	2
reset_info_cp[64]	auto[1]	79	1			T6	2		T10	1		T13	1
reset_info_cp[128]	auto[0]	65	1			T6	2		T7	1		T10	1
reset_info_cp[128]	auto[1]	62	1			T10	1		T26	1		T41	1