Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8808

1

T6

337

T7

166

T10

92

auto[1]

11770

1

T1

4

T3

4

T6

297

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6315	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6877	1			T1	2		T2	1		T3	2
reset_info_cp[2]	3171	1			T1	1		T3	1		T6	84
reset_info_cp[4]	4228	1			T1	1		T3	1		T6	144
reset_info_cp[8]	112	1			T6	3		T7	3		T10	1
reset_info_cp[16]	132	1			T6	5		T7	2		T10	1
reset_info_cp[32]	106	1			T6	2		T7	1		T10	1
reset_info_cp[64]	130	1			T6	4		T10	1		T13	1
reset_info_cp[128]	127	1			T6	2		T7	1		T10	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3314	1			T6	99		T7	47		T10	30
reset_info_cp[1]	auto[1]	2943	1			T1	1		T3	1		T6	104
reset_info_cp[2]	auto[0]	999	1			T6	40		T7	18		T10	15
reset_info_cp[2]	auto[1]	2172	1			T1	1		T3	1		T6	44
reset_info_cp[4]	auto[0]	1564	1			T6	71		T7	49		T10	13
reset_info_cp[4]	auto[1]	2664	1			T1	1		T3	1		T6	73
reset_info_cp[8]	auto[0]	53	1			T6	2		T7	2		T26	1
reset_info_cp[8]	auto[1]	59	1			T6	1		T7	1		T10	1
reset_info_cp[16]	auto[0]	49	1			T6	2		T10	1		T11	1
reset_info_cp[16]	auto[1]	83	1			T6	3		T7	2		T79	1
reset_info_cp[32]	auto[0]	37	1			T6	1		T7	1		T10	1
reset_info_cp[32]	auto[1]	69	1			T6	1		T11	1		T26	1
reset_info_cp[64]	auto[0]	55	1			T6	2		T10	1		T79	2
reset_info_cp[64]	auto[1]	75	1			T6	2		T13	1		T26	1
reset_info_cp[128]	auto[0]	56	1			T7	1		T10	2		T26	1
reset_info_cp[128]	auto[1]	71	1			T6	2		T26	2		T110	1