Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.4292439376 May 09 12:36:25 PM PDT 24 May 09 12:36:34 PM PDT 24 244698314 ps
T539 /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1444163330 May 09 12:36:30 PM PDT 24 May 09 12:36:43 PM PDT 24 1221174316 ps
T540 /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1413599312 May 09 12:37:02 PM PDT 24 May 09 12:37:20 PM PDT 24 1877497518 ps
T541 /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3132293411 May 09 12:36:44 PM PDT 24 May 09 12:36:55 PM PDT 24 198787468 ps
T542 /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.4192228237 May 09 12:36:48 PM PDT 24 May 09 12:36:59 PM PDT 24 103118607 ps
T65 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2756616644 May 09 12:33:35 PM PDT 24 May 09 12:33:47 PM PDT 24 102105216 ps
T66 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1274267137 May 09 12:33:32 PM PDT 24 May 09 12:33:45 PM PDT 24 211867221 ps
T67 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2523323807 May 09 12:34:05 PM PDT 24 May 09 12:34:14 PM PDT 24 69525617 ps
T90 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2143500236 May 09 12:33:38 PM PDT 24 May 09 12:33:49 PM PDT 24 60527213 ps
T68 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.176996247 May 09 12:33:35 PM PDT 24 May 09 12:33:47 PM PDT 24 177202440 ps
T112 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3365646350 May 09 12:33:34 PM PDT 24 May 09 12:33:46 PM PDT 24 119316960 ps
T113 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3903512312 May 09 12:33:44 PM PDT 24 May 09 12:33:55 PM PDT 24 218786575 ps
T69 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2944635637 May 09 12:33:29 PM PDT 24 May 09 12:33:43 PM PDT 24 422732610 ps
T91 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1882864011 May 09 12:33:22 PM PDT 24 May 09 12:33:35 PM PDT 24 140029058 ps
T127 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3894489577 May 09 12:33:30 PM PDT 24 May 09 12:33:47 PM PDT 24 487776736 ps
T543 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.820773653 May 09 12:33:20 PM PDT 24 May 09 12:33:32 PM PDT 24 73482270 ps
T114 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.449531202 May 09 12:33:33 PM PDT 24 May 09 12:33:45 PM PDT 24 57656725 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2899836921 May 09 12:33:16 PM PDT 24 May 09 12:33:29 PM PDT 24 142285047 ps
T115 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1885149496 May 09 12:33:16 PM PDT 24 May 09 12:33:29 PM PDT 24 79956608 ps
T70 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3876085599 May 09 12:33:40 PM PDT 24 May 09 12:33:53 PM PDT 24 468666396 ps
T545 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1642249795 May 09 12:33:24 PM PDT 24 May 09 12:33:37 PM PDT 24 96035200 ps
T105 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3149990605 May 09 12:33:15 PM PDT 24 May 09 12:33:28 PM PDT 24 133656350 ps
T71 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.55916263 May 09 12:33:33 PM PDT 24 May 09 12:33:48 PM PDT 24 614002611 ps
T88 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1695066151 May 09 12:33:31 PM PDT 24 May 09 12:33:45 PM PDT 24 940957068 ps
T89 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1501635642 May 09 12:33:28 PM PDT 24 May 09 12:33:41 PM PDT 24 434290731 ps
T97 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1175823095 May 09 12:33:40 PM PDT 24 May 09 12:33:53 PM PDT 24 197408129 ps
T116 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4177855243 May 09 12:33:33 PM PDT 24 May 09 12:33:45 PM PDT 24 194285749 ps
T117 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.560367046 May 09 12:33:21 PM PDT 24 May 09 12:33:34 PM PDT 24 92373985 ps
T118 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3616394766 May 09 12:33:53 PM PDT 24 May 09 12:34:01 PM PDT 24 61196205 ps
T87 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1176863697 May 09 12:33:38 PM PDT 24 May 09 12:33:52 PM PDT 24 417459302 ps
T106 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.291260060 May 09 12:33:50 PM PDT 24 May 09 12:34:00 PM PDT 24 426198181 ps
T107 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3675547539 May 09 12:33:15 PM PDT 24 May 09 12:33:29 PM PDT 24 179072390 ps
T546 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1232529614 May 09 12:33:35 PM PDT 24 May 09 12:33:47 PM PDT 24 213952150 ps
T92 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1585166465 May 09 12:33:13 PM PDT 24 May 09 12:33:28 PM PDT 24 312624830 ps
T108 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.563589435 May 09 12:33:19 PM PDT 24 May 09 12:33:32 PM PDT 24 118948166 ps
T547 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3508951768 May 09 12:33:36 PM PDT 24 May 09 12:33:52 PM PDT 24 1169673037 ps
T548 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1118744618 May 09 12:33:35 PM PDT 24 May 09 12:33:48 PM PDT 24 255873378 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.550260620 May 09 12:33:02 PM PDT 24 May 09 12:33:16 PM PDT 24 160688749 ps
T550 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.823220039 May 09 12:33:36 PM PDT 24 May 09 12:33:48 PM PDT 24 84193820 ps
T551 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3884895753 May 09 12:33:35 PM PDT 24 May 09 12:33:47 PM PDT 24 72525113 ps
T98 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3093306323 May 09 12:33:26 PM PDT 24 May 09 12:33:39 PM PDT 24 257773278 ps
T552 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2740673377 May 09 12:33:38 PM PDT 24 May 09 12:33:50 PM PDT 24 213158888 ps
T124 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1702656490 May 09 12:33:40 PM PDT 24 May 09 12:33:54 PM PDT 24 779707293 ps
T553 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1951935190 May 09 12:33:12 PM PDT 24 May 09 12:33:25 PM PDT 24 92078033 ps
T99 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4073583726 May 09 12:33:35 PM PDT 24 May 09 12:33:48 PM PDT 24 774905345 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3442656956 May 09 12:33:08 PM PDT 24 May 09 12:33:22 PM PDT 24 79815955 ps
T555 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1171940470 May 09 12:33:18 PM PDT 24 May 09 12:33:31 PM PDT 24 159153486 ps
T556 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3653958212 May 09 12:33:20 PM PDT 24 May 09 12:33:36 PM PDT 24 815164214 ps
T557 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1256459877 May 09 12:33:28 PM PDT 24 May 09 12:33:40 PM PDT 24 69955579 ps
T95 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2633473287 May 09 12:33:34 PM PDT 24 May 09 12:33:48 PM PDT 24 796575858 ps
T558 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3276659007 May 09 12:33:36 PM PDT 24 May 09 12:33:53 PM PDT 24 220282643 ps
T559 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.623747450 May 09 12:33:19 PM PDT 24 May 09 12:33:33 PM PDT 24 498819747 ps
T560 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.165027835 May 09 12:33:43 PM PDT 24 May 09 12:33:54 PM PDT 24 70039633 ps
T561 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3596826518 May 09 12:33:40 PM PDT 24 May 09 12:33:52 PM PDT 24 129570852 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.986070311 May 09 12:33:36 PM PDT 24 May 09 12:33:48 PM PDT 24 226742547 ps
T563 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.515051405 May 09 12:33:33 PM PDT 24 May 09 12:33:45 PM PDT 24 75703384 ps
T93 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2583931439 May 09 12:33:35 PM PDT 24 May 09 12:33:49 PM PDT 24 492789353 ps
T564 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2041305855 May 09 12:33:31 PM PDT 24 May 09 12:33:44 PM PDT 24 146078841 ps
T100 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3874020375 May 09 12:33:24 PM PDT 24 May 09 12:33:38 PM PDT 24 373691191 ps
T565 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1117055588 May 09 12:33:28 PM PDT 24 May 09 12:33:44 PM PDT 24 802367035 ps
T566 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2110678640 May 09 12:33:39 PM PDT 24 May 09 12:33:52 PM PDT 24 285693891 ps
T567 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1265862134 May 09 12:33:30 PM PDT 24 May 09 12:33:45 PM PDT 24 1029701332 ps
T101 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1401794528 May 09 12:33:32 PM PDT 24 May 09 12:33:46 PM PDT 24 210320952 ps
T568 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4230694011 May 09 12:33:41 PM PDT 24 May 09 12:33:54 PM PDT 24 483026307 ps
T569 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.977579549 May 09 12:33:34 PM PDT 24 May 09 12:33:46 PM PDT 24 66864850 ps
T570 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.390178559 May 09 12:33:30 PM PDT 24 May 09 12:33:43 PM PDT 24 108696259 ps
T571 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4205519293 May 09 12:33:37 PM PDT 24 May 09 12:33:49 PM PDT 24 132622689 ps
T572 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2051541874 May 09 12:33:34 PM PDT 24 May 09 12:33:47 PM PDT 24 121452768 ps
T573 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1207682893 May 09 12:33:09 PM PDT 24 May 09 12:33:25 PM PDT 24 472252254 ps
T574 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.952569194 May 09 12:33:10 PM PDT 24 May 09 12:33:24 PM PDT 24 156660712 ps
T575 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3508752219 May 09 12:33:53 PM PDT 24 May 09 12:34:01 PM PDT 24 140659957 ps
T576 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1158769253 May 09 12:33:29 PM PDT 24 May 09 12:33:42 PM PDT 24 123863243 ps
T577 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2591367791 May 09 12:33:34 PM PDT 24 May 09 12:33:47 PM PDT 24 121487864 ps
T578 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.542895051 May 09 12:33:52 PM PDT 24 May 09 12:34:00 PM PDT 24 87496873 ps
T125 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.534514325 May 09 12:33:31 PM PDT 24 May 09 12:33:44 PM PDT 24 468454678 ps
T579 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1203736342 May 09 12:33:53 PM PDT 24 May 09 12:34:03 PM PDT 24 877205607 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1431272962 May 09 12:33:25 PM PDT 24 May 09 12:33:39 PM PDT 24 353236329 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2144106569 May 09 12:33:28 PM PDT 24 May 09 12:33:41 PM PDT 24 413042239 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1013841602 May 09 12:33:15 PM PDT 24 May 09 12:33:28 PM PDT 24 93659720 ps
T583 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.656258228 May 09 12:33:19 PM PDT 24 May 09 12:33:37 PM PDT 24 75528365 ps
T584 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.4162579254 May 09 12:33:19 PM PDT 24 May 09 12:33:32 PM PDT 24 136579054 ps
T585 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1558004637 May 09 12:33:20 PM PDT 24 May 09 12:33:33 PM PDT 24 188528165 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1564372799 May 09 12:33:20 PM PDT 24 May 09 12:33:34 PM PDT 24 204901661 ps
T587 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3242395729 May 09 12:33:23 PM PDT 24 May 09 12:33:36 PM PDT 24 162326716 ps
T94 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.294838824 May 09 12:33:27 PM PDT 24 May 09 12:33:42 PM PDT 24 945160557 ps
T588 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3995423167 May 09 12:33:36 PM PDT 24 May 09 12:33:47 PM PDT 24 127166369 ps
T589 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.278778160 May 09 12:33:06 PM PDT 24 May 09 12:33:20 PM PDT 24 498498984 ps
T590 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1427134226 May 09 12:33:09 PM PDT 24 May 09 12:33:23 PM PDT 24 176076824 ps
T591 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.838304150 May 09 12:33:33 PM PDT 24 May 09 12:33:46 PM PDT 24 126782348 ps
T592 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2840165684 May 09 12:33:50 PM PDT 24 May 09 12:34:00 PM PDT 24 611198127 ps
T593 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1141998469 May 09 12:33:40 PM PDT 24 May 09 12:33:52 PM PDT 24 107439115 ps
T594 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1940321782 May 09 12:34:21 PM PDT 24 May 09 12:34:31 PM PDT 24 366329744 ps
T595 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3051279954 May 09 12:33:29 PM PDT 24 May 09 12:33:41 PM PDT 24 67367457 ps
T596 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3231190118 May 09 12:33:17 PM PDT 24 May 09 12:33:31 PM PDT 24 485613883 ps
T597 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.284852995 May 09 12:33:39 PM PDT 24 May 09 12:33:54 PM PDT 24 404319528 ps
T598 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2297156591 May 09 12:33:41 PM PDT 24 May 09 12:33:53 PM PDT 24 141705002 ps
T599 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.480200202 May 09 12:33:29 PM PDT 24 May 09 12:33:42 PM PDT 24 230612146 ps
T96 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1480940867 May 09 12:33:31 PM PDT 24 May 09 12:33:46 PM PDT 24 787905143 ps
T600 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3052897081 May 09 12:33:24 PM PDT 24 May 09 12:33:37 PM PDT 24 118535220 ps
T601 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2687346084 May 09 12:33:37 PM PDT 24 May 09 12:33:51 PM PDT 24 425949138 ps
T602 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2532955415 May 09 12:33:10 PM PDT 24 May 09 12:33:24 PM PDT 24 146324638 ps
T603 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.695744993 May 09 12:33:18 PM PDT 24 May 09 12:33:31 PM PDT 24 87650462 ps
T604 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2065547261 May 09 12:33:35 PM PDT 24 May 09 12:33:47 PM PDT 24 165707282 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2921592890 May 09 12:33:12 PM PDT 24 May 09 12:33:25 PM PDT 24 65861263 ps
T126 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.537813206 May 09 12:33:30 PM PDT 24 May 09 12:33:43 PM PDT 24 432993174 ps
T606 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2363268667 May 09 12:33:36 PM PDT 24 May 09 12:33:48 PM PDT 24 238322303 ps
T607 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1140145725 May 09 12:33:28 PM PDT 24 May 09 12:33:40 PM PDT 24 54664108 ps
T608 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1025289212 May 09 12:33:26 PM PDT 24 May 09 12:33:41 PM PDT 24 275816768 ps
T609 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4241687327 May 09 12:33:31 PM PDT 24 May 09 12:33:44 PM PDT 24 152485019 ps
T610 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3078400901 May 09 12:33:23 PM PDT 24 May 09 12:33:35 PM PDT 24 62781495 ps
T611 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4119142815 May 09 12:33:23 PM PDT 24 May 09 12:33:36 PM PDT 24 94615869 ps
T612 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3377537931 May 09 12:33:31 PM PDT 24 May 09 12:33:45 PM PDT 24 360527007 ps
T613 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4081419753 May 09 12:33:38 PM PDT 24 May 09 12:33:52 PM PDT 24 897032480 ps
T614 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1638460226 May 09 12:33:26 PM PDT 24 May 09 12:33:39 PM PDT 24 196945335 ps
T615 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.733889562 May 09 12:33:31 PM PDT 24 May 09 12:33:45 PM PDT 24 352241319 ps
T616 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.963622824 May 09 12:33:37 PM PDT 24 May 09 12:33:49 PM PDT 24 469619189 ps
T617 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2722269049 May 09 12:33:34 PM PDT 24 May 09 12:33:46 PM PDT 24 89361007 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2757535341 May 09 12:33:41 PM PDT 24 May 09 12:33:53 PM PDT 24 199411771 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1385894312 May 09 12:33:18 PM PDT 24 May 09 12:33:31 PM PDT 24 130075638 ps
T620 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.720086329 May 09 12:33:33 PM PDT 24 May 09 12:33:46 PM PDT 24 134945349 ps

Test location /workspace/coverage/default/7.rstmgr_stress_all.4051963148
Short name T10
Test name
Test status
Simulation time 5556907058 ps
CPU time 17.95 seconds
Started May 09 12:36:04 PM PDT 24
Finished May 09 12:36:30 PM PDT 24
Peak memory 201056 kb
Host smart-f618ddfe-e1de-48fd-aaf9-de3adb2a6067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051963148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.4051963148
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.774746932
Short name T104
Test name
Test status
Simulation time 136363155 ps
CPU time 1.54 seconds
Started May 09 12:37:08 PM PDT 24
Finished May 09 12:37:22 PM PDT 24
Peak memory 209040 kb
Host smart-aa0946d3-1f79-4f27-935c-3947a9d4a2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774746932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.774746932
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.176996247
Short name T68
Test name
Test status
Simulation time 177202440 ps
CPU time 1.17 seconds
Started May 09 12:33:35 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 208904 kb
Host smart-cad625fa-872f-4aaa-979a-597865585016
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176996247 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.176996247
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3064835803
Short name T72
Test name
Test status
Simulation time 8289089897 ps
CPU time 12.95 seconds
Started May 09 12:36:05 PM PDT 24
Finished May 09 12:36:26 PM PDT 24
Peak memory 217700 kb
Host smart-37e240cd-5418-4a74-a8a9-9e5ead0e9b6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064835803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3064835803
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1050007505
Short name T30
Test name
Test status
Simulation time 1893211022 ps
CPU time 7.03 seconds
Started May 09 12:36:03 PM PDT 24
Finished May 09 12:36:19 PM PDT 24
Peak memory 218336 kb
Host smart-bf97517d-c788-4cef-ad63-c29404e0af48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050007505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1050007505
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1695066151
Short name T88
Test name
Test status
Simulation time 940957068 ps
CPU time 3.46 seconds
Started May 09 12:33:31 PM PDT 24
Finished May 09 12:33:45 PM PDT 24
Peak memory 200344 kb
Host smart-d53f6212-bcc2-4c91-9638-a64c92a598c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695066151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1695066151
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2774043906
Short name T6
Test name
Test status
Simulation time 16479129039 ps
CPU time 59.01 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:37:06 PM PDT 24
Peak memory 209296 kb
Host smart-ae5794d7-1b64-40a3-a565-68bc2dab375d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774043906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2774043906
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1176863697
Short name T87
Test name
Test status
Simulation time 417459302 ps
CPU time 2.86 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 200428 kb
Host smart-1e54b519-8975-4171-9255-e54e633cfa1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176863697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1176863697
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2107365739
Short name T5
Test name
Test status
Simulation time 86578093 ps
CPU time 0.77 seconds
Started May 09 12:36:13 PM PDT 24
Finished May 09 12:36:22 PM PDT 24
Peak memory 200596 kb
Host smart-04521f48-afc2-4b21-9799-f686529f7851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107365739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2107365739
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.206761307
Short name T135
Test name
Test status
Simulation time 93987799 ps
CPU time 0.95 seconds
Started May 09 12:35:58 PM PDT 24
Finished May 09 12:36:08 PM PDT 24
Peak memory 200756 kb
Host smart-2f08e903-9b09-49ab-97a1-8fd0eadf8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206761307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.206761307
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2896812313
Short name T48
Test name
Test status
Simulation time 1892674326 ps
CPU time 6.68 seconds
Started May 09 12:36:33 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 218428 kb
Host smart-05147b2e-9629-4ae2-b871-31b5fcce6a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896812313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2896812313
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1702656490
Short name T124
Test name
Test status
Simulation time 779707293 ps
CPU time 2.86 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 200448 kb
Host smart-80f8f73d-a68b-4c99-83d4-a0118915a999
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702656490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1702656490
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4040818750
Short name T148
Test name
Test status
Simulation time 190570640 ps
CPU time 1.19 seconds
Started May 09 12:36:20 PM PDT 24
Finished May 09 12:36:29 PM PDT 24
Peak memory 200780 kb
Host smart-f5403005-d54f-4d0a-ab5f-894a256c22cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040818750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4040818750
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3874020375
Short name T100
Test name
Test status
Simulation time 373691191 ps
CPU time 2.71 seconds
Started May 09 12:33:24 PM PDT 24
Finished May 09 12:33:38 PM PDT 24
Peak memory 208620 kb
Host smart-5a4cca58-970d-4fba-8833-44ebf8dd74af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874020375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3874020375
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3616394766
Short name T118
Test name
Test status
Simulation time 61196205 ps
CPU time 0.75 seconds
Started May 09 12:33:53 PM PDT 24
Finished May 09 12:34:01 PM PDT 24
Peak memory 200132 kb
Host smart-49035a76-e445-44d5-99b7-197e0cafbbe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616394766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3616394766
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1318386059
Short name T16
Test name
Test status
Simulation time 182827414 ps
CPU time 0.84 seconds
Started May 09 12:35:54 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 200552 kb
Host smart-7b11aa4d-f546-45c6-adaa-e3655b74120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318386059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1318386059
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2073816246
Short name T38
Test name
Test status
Simulation time 1231618311 ps
CPU time 5.34 seconds
Started May 09 12:35:53 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 218296 kb
Host smart-97fadcb3-ff70-4899-9e21-e08aa352bfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073816246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2073816246
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.995262299
Short name T61
Test name
Test status
Simulation time 243648185 ps
CPU time 1.07 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:55 PM PDT 24
Peak memory 218076 kb
Host smart-f06b1aec-f269-41e9-88fb-82cd6b29d9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995262299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.995262299
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1480940867
Short name T96
Test name
Test status
Simulation time 787905143 ps
CPU time 3.13 seconds
Started May 09 12:33:31 PM PDT 24
Finished May 09 12:33:46 PM PDT 24
Peak memory 209608 kb
Host smart-90b29c8f-8c54-45c1-83a1-5b17e76ef932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480940867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1480940867
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.294838824
Short name T94
Test name
Test status
Simulation time 945160557 ps
CPU time 3.6 seconds
Started May 09 12:33:27 PM PDT 24
Finished May 09 12:33:42 PM PDT 24
Peak memory 200588 kb
Host smart-4512638a-67bf-46b5-907b-81bae01896ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294838824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
294838824
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1141998469
Short name T593
Test name
Test status
Simulation time 107439115 ps
CPU time 1.26 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 200248 kb
Host smart-2b665cea-bfd8-4146-8e15-c0fd1355938d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141998469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
141998469
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1025289212
Short name T608
Test name
Test status
Simulation time 275816768 ps
CPU time 3.35 seconds
Started May 09 12:33:26 PM PDT 24
Finished May 09 12:33:41 PM PDT 24
Peak memory 200484 kb
Host smart-4f894374-f522-479c-bd8b-7801105dfadc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025289212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
025289212
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2899836921
Short name T544
Test name
Test status
Simulation time 142285047 ps
CPU time 0.91 seconds
Started May 09 12:33:16 PM PDT 24
Finished May 09 12:33:29 PM PDT 24
Peak memory 200172 kb
Host smart-99fc06c8-7d72-4a5b-83d6-3da3182f171d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899836921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
899836921
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.563589435
Short name T108
Test name
Test status
Simulation time 118948166 ps
CPU time 0.99 seconds
Started May 09 12:33:19 PM PDT 24
Finished May 09 12:33:32 PM PDT 24
Peak memory 200224 kb
Host smart-64c4c263-6c7c-4b09-99a0-4992c6409e47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563589435 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.563589435
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.515051405
Short name T563
Test name
Test status
Simulation time 75703384 ps
CPU time 0.84 seconds
Started May 09 12:33:33 PM PDT 24
Finished May 09 12:33:45 PM PDT 24
Peak memory 200208 kb
Host smart-530de4de-f961-4292-b9f4-fb1a7549a2c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515051405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.515051405
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2363268667
Short name T606
Test name
Test status
Simulation time 238322303 ps
CPU time 1.56 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:48 PM PDT 24
Peak memory 200412 kb
Host smart-d60c5550-a1b7-4aaf-b319-2a35fbb14d09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363268667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2363268667
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2144106569
Short name T581
Test name
Test status
Simulation time 413042239 ps
CPU time 2.47 seconds
Started May 09 12:33:28 PM PDT 24
Finished May 09 12:33:41 PM PDT 24
Peak memory 211384 kb
Host smart-83d0645e-f674-4a0f-bacb-dac71d0709be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144106569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2144106569
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1265862134
Short name T567
Test name
Test status
Simulation time 1029701332 ps
CPU time 3.19 seconds
Started May 09 12:33:30 PM PDT 24
Finished May 09 12:33:45 PM PDT 24
Peak memory 200360 kb
Host smart-1fb5a91b-8b52-4839-82f3-a9f40cf06fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265862134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1265862134
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.550260620
Short name T549
Test name
Test status
Simulation time 160688749 ps
CPU time 1.96 seconds
Started May 09 12:33:02 PM PDT 24
Finished May 09 12:33:16 PM PDT 24
Peak memory 200440 kb
Host smart-aa650d9f-474d-4c16-920a-4dd75d1aa28d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550260620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.550260620
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1117055588
Short name T565
Test name
Test status
Simulation time 802367035 ps
CPU time 4.3 seconds
Started May 09 12:33:28 PM PDT 24
Finished May 09 12:33:44 PM PDT 24
Peak memory 216680 kb
Host smart-36ce07a8-d7bf-4367-a4e5-8e2406386121
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117055588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
117055588
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1385894312
Short name T619
Test name
Test status
Simulation time 130075638 ps
CPU time 0.86 seconds
Started May 09 12:33:18 PM PDT 24
Finished May 09 12:33:31 PM PDT 24
Peak memory 200144 kb
Host smart-80e0ac08-a79b-4d4a-aca6-e0d157b3af42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385894312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
385894312
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1427134226
Short name T590
Test name
Test status
Simulation time 176076824 ps
CPU time 1.65 seconds
Started May 09 12:33:09 PM PDT 24
Finished May 09 12:33:23 PM PDT 24
Peak memory 209136 kb
Host smart-d6a9eda1-f0b7-4708-b264-a404b6cc6765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427134226 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1427134226
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2921592890
Short name T605
Test name
Test status
Simulation time 65861263 ps
CPU time 0.77 seconds
Started May 09 12:33:12 PM PDT 24
Finished May 09 12:33:25 PM PDT 24
Peak memory 200080 kb
Host smart-1a50e0b2-f171-4e50-8bcb-c00f3320d541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921592890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2921592890
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.4162579254
Short name T584
Test name
Test status
Simulation time 136579054 ps
CPU time 1.01 seconds
Started May 09 12:33:19 PM PDT 24
Finished May 09 12:33:32 PM PDT 24
Peak memory 200236 kb
Host smart-553a5b94-a3b6-4707-a80c-a65079f718fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162579254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.4162579254
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2532955415
Short name T602
Test name
Test status
Simulation time 146324638 ps
CPU time 1.98 seconds
Started May 09 12:33:10 PM PDT 24
Finished May 09 12:33:24 PM PDT 24
Peak memory 212004 kb
Host smart-72d780d0-6d77-402c-ad52-7a96417bcde0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532955415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2532955415
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3675547539
Short name T107
Test name
Test status
Simulation time 179072390 ps
CPU time 1.58 seconds
Started May 09 12:33:15 PM PDT 24
Finished May 09 12:33:29 PM PDT 24
Peak memory 208588 kb
Host smart-05cc840e-b074-4e27-9c64-c9baa7868231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675547539 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3675547539
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1140145725
Short name T607
Test name
Test status
Simulation time 54664108 ps
CPU time 0.77 seconds
Started May 09 12:33:28 PM PDT 24
Finished May 09 12:33:40 PM PDT 24
Peak memory 200640 kb
Host smart-6c1a7036-61a0-460d-92fc-5e9175371a1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140145725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1140145725
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1118744618
Short name T548
Test name
Test status
Simulation time 255873378 ps
CPU time 1.57 seconds
Started May 09 12:33:35 PM PDT 24
Finished May 09 12:33:48 PM PDT 24
Peak memory 200556 kb
Host smart-4b26cbff-3e75-406a-b828-913f5df7d9e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118744618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1118744618
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2583931439
Short name T93
Test name
Test status
Simulation time 492789353 ps
CPU time 2.99 seconds
Started May 09 12:33:35 PM PDT 24
Finished May 09 12:33:49 PM PDT 24
Peak memory 208608 kb
Host smart-5a25eb50-9926-4c97-82a3-3e4e787523f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583931439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2583931439
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1274267137
Short name T66
Test name
Test status
Simulation time 211867221 ps
CPU time 1.4 seconds
Started May 09 12:33:32 PM PDT 24
Finished May 09 12:33:45 PM PDT 24
Peak memory 208420 kb
Host smart-d6bc8e7b-52bf-4e04-939a-ba9cf95cd397
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274267137 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1274267137
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.820773653
Short name T543
Test name
Test status
Simulation time 73482270 ps
CPU time 0.78 seconds
Started May 09 12:33:20 PM PDT 24
Finished May 09 12:33:32 PM PDT 24
Peak memory 200100 kb
Host smart-7f558d5d-bf8e-465b-8f5d-d494a38a2877
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820773653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.820773653
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1158769253
Short name T576
Test name
Test status
Simulation time 123863243 ps
CPU time 1.19 seconds
Started May 09 12:33:29 PM PDT 24
Finished May 09 12:33:42 PM PDT 24
Peak memory 200376 kb
Host smart-f3cac166-9319-4f49-81c7-3e32dc68213e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158769253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1158769253
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2687346084
Short name T601
Test name
Test status
Simulation time 425949138 ps
CPU time 2.97 seconds
Started May 09 12:33:37 PM PDT 24
Finished May 09 12:33:51 PM PDT 24
Peak memory 208736 kb
Host smart-298c9496-a693-403e-8ea1-9f5576499bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687346084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2687346084
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.537813206
Short name T126
Test name
Test status
Simulation time 432993174 ps
CPU time 1.85 seconds
Started May 09 12:33:30 PM PDT 24
Finished May 09 12:33:43 PM PDT 24
Peak memory 200484 kb
Host smart-0bec27f2-a44a-4496-9ef4-37d1ee6c3ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537813206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.537813206
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.720086329
Short name T620
Test name
Test status
Simulation time 134945349 ps
CPU time 1.07 seconds
Started May 09 12:33:33 PM PDT 24
Finished May 09 12:33:46 PM PDT 24
Peak memory 200560 kb
Host smart-76eaffed-1010-40e6-b5b9-f78c33382523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720086329 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.720086329
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3365646350
Short name T112
Test name
Test status
Simulation time 119316960 ps
CPU time 1.02 seconds
Started May 09 12:33:34 PM PDT 24
Finished May 09 12:33:46 PM PDT 24
Peak memory 200164 kb
Host smart-18e8d566-f902-4d91-9b87-7a331929e34b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365646350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3365646350
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.284852995
Short name T597
Test name
Test status
Simulation time 404319528 ps
CPU time 2.94 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 208608 kb
Host smart-bc1b78f5-d99c-4ddd-b9a2-24b4e0a1477c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284852995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.284852995
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4081419753
Short name T613
Test name
Test status
Simulation time 897032480 ps
CPU time 2.95 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 200604 kb
Host smart-2aabac9e-1c56-44a6-9397-d00903eb35e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081419753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.4081419753
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3052897081
Short name T600
Test name
Test status
Simulation time 118535220 ps
CPU time 0.95 seconds
Started May 09 12:33:24 PM PDT 24
Finished May 09 12:33:37 PM PDT 24
Peak memory 200332 kb
Host smart-3cfb806a-be5e-4402-81bf-94bee92116e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052897081 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3052897081
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.656258228
Short name T583
Test name
Test status
Simulation time 75528365 ps
CPU time 0.77 seconds
Started May 09 12:33:19 PM PDT 24
Finished May 09 12:33:37 PM PDT 24
Peak memory 200180 kb
Host smart-06f83a11-eda3-46db-bb03-eb239dedbfb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656258228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.656258228
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3995423167
Short name T588
Test name
Test status
Simulation time 127166369 ps
CPU time 1.23 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 200420 kb
Host smart-ed35a1cd-fadd-412e-bd74-65b17d07e735
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995423167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3995423167
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2591367791
Short name T577
Test name
Test status
Simulation time 121487864 ps
CPU time 1.72 seconds
Started May 09 12:33:34 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 208688 kb
Host smart-4f12212a-f678-4daa-bb78-0fe100ad82fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591367791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2591367791
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1501635642
Short name T89
Test name
Test status
Simulation time 434290731 ps
CPU time 1.71 seconds
Started May 09 12:33:28 PM PDT 24
Finished May 09 12:33:41 PM PDT 24
Peak memory 200452 kb
Host smart-a6624b76-c698-4e1c-a436-683bdfbfa011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501635642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1501635642
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.838304150
Short name T591
Test name
Test status
Simulation time 126782348 ps
CPU time 1.04 seconds
Started May 09 12:33:33 PM PDT 24
Finished May 09 12:33:46 PM PDT 24
Peak memory 208476 kb
Host smart-0da81432-5ed8-40dd-bdcb-c106e3d2586d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838304150 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.838304150
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3051279954
Short name T595
Test name
Test status
Simulation time 67367457 ps
CPU time 0.8 seconds
Started May 09 12:33:29 PM PDT 24
Finished May 09 12:33:41 PM PDT 24
Peak memory 200112 kb
Host smart-b0e1365d-e187-46bb-8eb7-9ceaa41207e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051279954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3051279954
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3903512312
Short name T113
Test name
Test status
Simulation time 218786575 ps
CPU time 1.4 seconds
Started May 09 12:33:44 PM PDT 24
Finished May 09 12:33:55 PM PDT 24
Peak memory 200604 kb
Host smart-4cc1b8af-3a5c-4b82-ae71-ac52cc1a7180
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903512312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3903512312
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3231190118
Short name T596
Test name
Test status
Simulation time 485613883 ps
CPU time 2.04 seconds
Started May 09 12:33:17 PM PDT 24
Finished May 09 12:33:31 PM PDT 24
Peak memory 200536 kb
Host smart-bbf68ecd-9a09-494a-8b8d-84c0e603a32a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231190118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3231190118
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.165027835
Short name T560
Test name
Test status
Simulation time 70039633 ps
CPU time 0.77 seconds
Started May 09 12:33:43 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 200276 kb
Host smart-ef199e04-9139-4d96-99d8-5050b05addfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165027835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.165027835
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1232529614
Short name T546
Test name
Test status
Simulation time 213952150 ps
CPU time 1.33 seconds
Started May 09 12:33:35 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 200408 kb
Host smart-c2c8c6db-5c2b-429e-aea6-545a43eff8fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232529614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1232529614
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3508752219
Short name T575
Test name
Test status
Simulation time 140659957 ps
CPU time 1.42 seconds
Started May 09 12:33:53 PM PDT 24
Finished May 09 12:34:01 PM PDT 24
Peak memory 208656 kb
Host smart-25d0518c-fff6-491d-9d58-f508d7fd4424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508752219 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3508752219
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2143500236
Short name T90
Test name
Test status
Simulation time 60527213 ps
CPU time 0.78 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:49 PM PDT 24
Peak memory 200176 kb
Host smart-1308912a-231e-4da7-99e9-f58f4c06bca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143500236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2143500236
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2740673377
Short name T552
Test name
Test status
Simulation time 213158888 ps
CPU time 1.53 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:50 PM PDT 24
Peak memory 200420 kb
Host smart-2bd85526-56cc-4ec0-8846-325984c7bebd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740673377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2740673377
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2110678640
Short name T566
Test name
Test status
Simulation time 285693891 ps
CPU time 1.94 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 200540 kb
Host smart-aad6554e-83f3-4539-b578-43374adde870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110678640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2110678640
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2840165684
Short name T592
Test name
Test status
Simulation time 611198127 ps
CPU time 2.06 seconds
Started May 09 12:33:50 PM PDT 24
Finished May 09 12:34:00 PM PDT 24
Peak memory 200404 kb
Host smart-e5558490-5ca1-4534-ac64-e6cff560ac15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840165684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2840165684
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2297156591
Short name T598
Test name
Test status
Simulation time 141705002 ps
CPU time 1.11 seconds
Started May 09 12:33:41 PM PDT 24
Finished May 09 12:33:53 PM PDT 24
Peak memory 209556 kb
Host smart-7d20ab18-0c82-4a0d-b491-49038041f68c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297156591 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2297156591
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2523323807
Short name T67
Test name
Test status
Simulation time 69525617 ps
CPU time 0.79 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 200168 kb
Host smart-42b4a77e-6d21-4e73-af79-6a727c65921b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523323807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2523323807
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.480200202
Short name T599
Test name
Test status
Simulation time 230612146 ps
CPU time 1.45 seconds
Started May 09 12:33:29 PM PDT 24
Finished May 09 12:33:42 PM PDT 24
Peak memory 200424 kb
Host smart-7eb5037b-27db-450b-ab1f-d6852db012b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480200202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.480200202
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1940321782
Short name T594
Test name
Test status
Simulation time 366329744 ps
CPU time 2.71 seconds
Started May 09 12:34:21 PM PDT 24
Finished May 09 12:34:31 PM PDT 24
Peak memory 211672 kb
Host smart-bb78328f-3276-48be-a5cd-728b2da843dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940321782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1940321782
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1203736342
Short name T579
Test name
Test status
Simulation time 877205607 ps
CPU time 3.09 seconds
Started May 09 12:33:53 PM PDT 24
Finished May 09 12:34:03 PM PDT 24
Peak memory 200464 kb
Host smart-ca7e426c-1e5b-4d15-8c29-d3403e20edc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203736342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1203736342
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1175823095
Short name T97
Test name
Test status
Simulation time 197408129 ps
CPU time 1.33 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:53 PM PDT 24
Peak memory 211184 kb
Host smart-be6360df-3242-4c4a-b1c3-e6d73b34abe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175823095 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1175823095
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.449531202
Short name T114
Test name
Test status
Simulation time 57656725 ps
CPU time 0.74 seconds
Started May 09 12:33:33 PM PDT 24
Finished May 09 12:33:45 PM PDT 24
Peak memory 200140 kb
Host smart-2a3a25d1-96c5-4572-a330-2fbcb7d67d23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449531202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.449531202
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2051541874
Short name T572
Test name
Test status
Simulation time 121452768 ps
CPU time 1.18 seconds
Started May 09 12:33:34 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 200388 kb
Host smart-3aa3b18c-8eb9-4014-9c62-251174f2829c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051541874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2051541874
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1431272962
Short name T580
Test name
Test status
Simulation time 353236329 ps
CPU time 2.64 seconds
Started May 09 12:33:25 PM PDT 24
Finished May 09 12:33:39 PM PDT 24
Peak memory 208736 kb
Host smart-8df274af-81d2-4fa2-b268-270fcd5bdbf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431272962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1431272962
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.534514325
Short name T125
Test name
Test status
Simulation time 468454678 ps
CPU time 1.91 seconds
Started May 09 12:33:31 PM PDT 24
Finished May 09 12:33:44 PM PDT 24
Peak memory 200320 kb
Host smart-14df0bd5-de0a-4f91-9129-a90e3047e83a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534514325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.534514325
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1558004637
Short name T585
Test name
Test status
Simulation time 188528165 ps
CPU time 1.23 seconds
Started May 09 12:33:20 PM PDT 24
Finished May 09 12:33:33 PM PDT 24
Peak memory 208456 kb
Host smart-c32e7369-3b60-43d3-8626-8d870a891b53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558004637 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1558004637
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1256459877
Short name T557
Test name
Test status
Simulation time 69955579 ps
CPU time 0.76 seconds
Started May 09 12:33:28 PM PDT 24
Finished May 09 12:33:40 PM PDT 24
Peak memory 200048 kb
Host smart-393fe6b0-f46a-4087-b22e-09e82a5bcbcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256459877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1256459877
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4177855243
Short name T116
Test name
Test status
Simulation time 194285749 ps
CPU time 1.36 seconds
Started May 09 12:33:33 PM PDT 24
Finished May 09 12:33:45 PM PDT 24
Peak memory 200456 kb
Host smart-a0b1e57e-b5bb-4a5b-a4cb-e0b4ed391f22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177855243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4177855243
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2041305855
Short name T564
Test name
Test status
Simulation time 146078841 ps
CPU time 2.01 seconds
Started May 09 12:33:31 PM PDT 24
Finished May 09 12:33:44 PM PDT 24
Peak memory 208492 kb
Host smart-2c0b48d8-3c7b-41a8-85a9-5d63aa0a8d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041305855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2041305855
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4230694011
Short name T568
Test name
Test status
Simulation time 483026307 ps
CPU time 1.83 seconds
Started May 09 12:33:41 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 200508 kb
Host smart-a7cfe542-3f5d-46d7-ac06-719c5c031d63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230694011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.4230694011
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4241687327
Short name T609
Test name
Test status
Simulation time 152485019 ps
CPU time 2 seconds
Started May 09 12:33:31 PM PDT 24
Finished May 09 12:33:44 PM PDT 24
Peak memory 200268 kb
Host smart-d7008c78-6480-437c-bb65-c842dc214bca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241687327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.4
241687327
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3894489577
Short name T127
Test name
Test status
Simulation time 487776736 ps
CPU time 5.48 seconds
Started May 09 12:33:30 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 216736 kb
Host smart-a7877705-a27a-47b3-b95d-295ef458c32a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894489577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
894489577
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1642249795
Short name T545
Test name
Test status
Simulation time 96035200 ps
CPU time 0.8 seconds
Started May 09 12:33:24 PM PDT 24
Finished May 09 12:33:37 PM PDT 24
Peak memory 200176 kb
Host smart-3f6d249f-0e94-4366-aa66-2ac438dc5f6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642249795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
642249795
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.952569194
Short name T574
Test name
Test status
Simulation time 156660712 ps
CPU time 1.46 seconds
Started May 09 12:33:10 PM PDT 24
Finished May 09 12:33:24 PM PDT 24
Peak memory 208664 kb
Host smart-57230e00-665c-4196-b891-32207dfc4676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952569194 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.952569194
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2722269049
Short name T617
Test name
Test status
Simulation time 89361007 ps
CPU time 0.82 seconds
Started May 09 12:33:34 PM PDT 24
Finished May 09 12:33:46 PM PDT 24
Peak memory 200144 kb
Host smart-d2d861fb-4cfb-4270-9334-15297c6d05fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722269049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2722269049
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3442656956
Short name T554
Test name
Test status
Simulation time 79815955 ps
CPU time 0.94 seconds
Started May 09 12:33:08 PM PDT 24
Finished May 09 12:33:22 PM PDT 24
Peak memory 200200 kb
Host smart-f211a5c4-9214-4b97-b7b6-ad108b929b43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442656956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3442656956
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1585166465
Short name T92
Test name
Test status
Simulation time 312624830 ps
CPU time 2.41 seconds
Started May 09 12:33:13 PM PDT 24
Finished May 09 12:33:28 PM PDT 24
Peak memory 208620 kb
Host smart-72151d88-82b1-4042-abab-875a44b24241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585166465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1585166465
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.278778160
Short name T589
Test name
Test status
Simulation time 498498984 ps
CPU time 1.95 seconds
Started May 09 12:33:06 PM PDT 24
Finished May 09 12:33:20 PM PDT 24
Peak memory 200392 kb
Host smart-6f3cbe64-c757-4afe-84ff-4ba019282306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278778160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
278778160
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1564372799
Short name T586
Test name
Test status
Simulation time 204901661 ps
CPU time 1.57 seconds
Started May 09 12:33:20 PM PDT 24
Finished May 09 12:33:34 PM PDT 24
Peak memory 200496 kb
Host smart-09000ea0-358f-4155-a06a-2bde7b31448f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564372799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
564372799
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3508951768
Short name T547
Test name
Test status
Simulation time 1169673037 ps
CPU time 5.01 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 200364 kb
Host smart-e47630c0-50b9-4858-9080-53f8a3357d10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508951768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
508951768
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2756616644
Short name T65
Test name
Test status
Simulation time 102105216 ps
CPU time 0.85 seconds
Started May 09 12:33:35 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 200164 kb
Host smart-46e76e93-e4f7-4d88-b19e-a36d0e4481fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756616644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
756616644
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2065547261
Short name T604
Test name
Test status
Simulation time 165707282 ps
CPU time 1.36 seconds
Started May 09 12:33:35 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 208688 kb
Host smart-78b6ff73-9b56-4bc9-9d9e-fedb0a21a007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065547261 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2065547261
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1951935190
Short name T553
Test name
Test status
Simulation time 92078033 ps
CPU time 0.91 seconds
Started May 09 12:33:12 PM PDT 24
Finished May 09 12:33:25 PM PDT 24
Peak memory 200080 kb
Host smart-ca6e53e2-8f02-4531-a772-13d9e50de5ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951935190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1951935190
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.823220039
Short name T550
Test name
Test status
Simulation time 84193820 ps
CPU time 0.91 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:48 PM PDT 24
Peak memory 200244 kb
Host smart-9776242e-633d-4bf6-81bc-9ff9f353ca9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823220039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.823220039
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3093306323
Short name T98
Test name
Test status
Simulation time 257773278 ps
CPU time 1.69 seconds
Started May 09 12:33:26 PM PDT 24
Finished May 09 12:33:39 PM PDT 24
Peak memory 210444 kb
Host smart-2ca0f6a3-4be8-42af-9455-d3772e99375a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093306323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3093306323
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3876085599
Short name T70
Test name
Test status
Simulation time 468666396 ps
CPU time 1.9 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:53 PM PDT 24
Peak memory 200436 kb
Host smart-3cf9435d-6908-466a-bc75-be3a6c11f698
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876085599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3876085599
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.390178559
Short name T570
Test name
Test status
Simulation time 108696259 ps
CPU time 1.25 seconds
Started May 09 12:33:30 PM PDT 24
Finished May 09 12:33:43 PM PDT 24
Peak memory 200364 kb
Host smart-96937da7-49f3-493c-addb-77f6dfdf40db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390178559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.390178559
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3653958212
Short name T556
Test name
Test status
Simulation time 815164214 ps
CPU time 4.2 seconds
Started May 09 12:33:20 PM PDT 24
Finished May 09 12:33:36 PM PDT 24
Peak memory 200344 kb
Host smart-af3b2f5e-244a-485f-9c0c-522321814175
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653958212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
653958212
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1013841602
Short name T582
Test name
Test status
Simulation time 93659720 ps
CPU time 0.84 seconds
Started May 09 12:33:15 PM PDT 24
Finished May 09 12:33:28 PM PDT 24
Peak memory 200256 kb
Host smart-8bb0c606-349a-4f6f-83c2-700b582eb1ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013841602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
013841602
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2757535341
Short name T618
Test name
Test status
Simulation time 199411771 ps
CPU time 1.34 seconds
Started May 09 12:33:41 PM PDT 24
Finished May 09 12:33:53 PM PDT 24
Peak memory 208504 kb
Host smart-af54314c-f9c4-45b9-9030-400d037d3e4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757535341 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2757535341
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1885149496
Short name T115
Test name
Test status
Simulation time 79956608 ps
CPU time 0.84 seconds
Started May 09 12:33:16 PM PDT 24
Finished May 09 12:33:29 PM PDT 24
Peak memory 200076 kb
Host smart-63f1f835-cc23-4704-afb1-c1c0ea6e2cdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885149496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1885149496
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.986070311
Short name T562
Test name
Test status
Simulation time 226742547 ps
CPU time 1.5 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:48 PM PDT 24
Peak memory 200344 kb
Host smart-6e083be3-e0f0-4818-b077-f9a4f932b7fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986070311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.986070311
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1207682893
Short name T573
Test name
Test status
Simulation time 472252254 ps
CPU time 3.08 seconds
Started May 09 12:33:09 PM PDT 24
Finished May 09 12:33:25 PM PDT 24
Peak memory 208712 kb
Host smart-329a09bc-0aad-43be-90ea-6647486046d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207682893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1207682893
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.623747450
Short name T559
Test name
Test status
Simulation time 498819747 ps
CPU time 2.1 seconds
Started May 09 12:33:19 PM PDT 24
Finished May 09 12:33:33 PM PDT 24
Peak memory 200444 kb
Host smart-0f3c6bda-82c1-46ed-9a87-6092627cc363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623747450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
623747450
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1171940470
Short name T555
Test name
Test status
Simulation time 159153486 ps
CPU time 1.44 seconds
Started May 09 12:33:18 PM PDT 24
Finished May 09 12:33:31 PM PDT 24
Peak memory 208672 kb
Host smart-195fb22a-4429-4356-8ce9-c94a1c3f6131
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171940470 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1171940470
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4119142815
Short name T611
Test name
Test status
Simulation time 94615869 ps
CPU time 1 seconds
Started May 09 12:33:23 PM PDT 24
Finished May 09 12:33:36 PM PDT 24
Peak memory 200200 kb
Host smart-049d1828-5733-4457-b5a6-a8c7f2735095
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119142815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.4119142815
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4205519293
Short name T571
Test name
Test status
Simulation time 132622689 ps
CPU time 1.01 seconds
Started May 09 12:33:37 PM PDT 24
Finished May 09 12:33:49 PM PDT 24
Peak memory 200320 kb
Host smart-67288e1e-c92a-4b6d-8944-3f1aea1a8b13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205519293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4205519293
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.733889562
Short name T615
Test name
Test status
Simulation time 352241319 ps
CPU time 2.24 seconds
Started May 09 12:33:31 PM PDT 24
Finished May 09 12:33:45 PM PDT 24
Peak memory 210800 kb
Host smart-178b4706-33cb-4728-9a63-e8ce91ff42ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733889562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.733889562
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4073583726
Short name T99
Test name
Test status
Simulation time 774905345 ps
CPU time 2.82 seconds
Started May 09 12:33:35 PM PDT 24
Finished May 09 12:33:48 PM PDT 24
Peak memory 200416 kb
Host smart-9bcfff18-1c80-4393-a92f-4aa2ddbf782b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073583726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.4073583726
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1638460226
Short name T614
Test name
Test status
Simulation time 196945335 ps
CPU time 1.3 seconds
Started May 09 12:33:26 PM PDT 24
Finished May 09 12:33:39 PM PDT 24
Peak memory 209996 kb
Host smart-9460deb6-585e-4abb-972a-23e0179b4460
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638460226 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1638460226
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.542895051
Short name T578
Test name
Test status
Simulation time 87496873 ps
CPU time 0.86 seconds
Started May 09 12:33:52 PM PDT 24
Finished May 09 12:34:00 PM PDT 24
Peak memory 200096 kb
Host smart-29998ee2-b7ac-4f59-be24-591897b70f8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542895051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.542895051
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.560367046
Short name T117
Test name
Test status
Simulation time 92373985 ps
CPU time 0.98 seconds
Started May 09 12:33:21 PM PDT 24
Finished May 09 12:33:34 PM PDT 24
Peak memory 200264 kb
Host smart-3d1b6193-943e-4d8d-9252-d18d3f0abff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560367046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.560367046
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.55916263
Short name T71
Test name
Test status
Simulation time 614002611 ps
CPU time 3.95 seconds
Started May 09 12:33:33 PM PDT 24
Finished May 09 12:33:48 PM PDT 24
Peak memory 216776 kb
Host smart-8832c83e-335e-47b5-9e19-fa1f753f6b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55916263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.55916263
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.963622824
Short name T616
Test name
Test status
Simulation time 469619189 ps
CPU time 1.89 seconds
Started May 09 12:33:37 PM PDT 24
Finished May 09 12:33:49 PM PDT 24
Peak memory 200424 kb
Host smart-25ff6387-50d5-4526-8fc7-8feed485faa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963622824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
963622824
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3242395729
Short name T587
Test name
Test status
Simulation time 162326716 ps
CPU time 1.1 seconds
Started May 09 12:33:23 PM PDT 24
Finished May 09 12:33:36 PM PDT 24
Peak memory 200316 kb
Host smart-0448ea5c-efc7-49cc-934c-d4a92da5a027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242395729 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3242395729
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.977579549
Short name T569
Test name
Test status
Simulation time 66864850 ps
CPU time 0.81 seconds
Started May 09 12:33:34 PM PDT 24
Finished May 09 12:33:46 PM PDT 24
Peak memory 200164 kb
Host smart-e34c009c-72c6-4ef2-8928-dface2b78dba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977579549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.977579549
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3276659007
Short name T558
Test name
Test status
Simulation time 220282643 ps
CPU time 1.41 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:53 PM PDT 24
Peak memory 200436 kb
Host smart-6f2083b3-962f-49e8-b06b-f288bf5fcd9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276659007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3276659007
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1401794528
Short name T101
Test name
Test status
Simulation time 210320952 ps
CPU time 2.99 seconds
Started May 09 12:33:32 PM PDT 24
Finished May 09 12:33:46 PM PDT 24
Peak memory 216780 kb
Host smart-a3eb4a14-3766-42ad-a915-1a41c9eb0149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401794528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1401794528
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2633473287
Short name T95
Test name
Test status
Simulation time 796575858 ps
CPU time 2.98 seconds
Started May 09 12:33:34 PM PDT 24
Finished May 09 12:33:48 PM PDT 24
Peak memory 200480 kb
Host smart-804c0875-60ea-4712-b587-3cd9dff122d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633473287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2633473287
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3596826518
Short name T561
Test name
Test status
Simulation time 129570852 ps
CPU time 1.39 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 208592 kb
Host smart-8ae538ba-b5ea-499d-aaff-5570ae630359
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596826518 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3596826518
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3078400901
Short name T610
Test name
Test status
Simulation time 62781495 ps
CPU time 0.74 seconds
Started May 09 12:33:23 PM PDT 24
Finished May 09 12:33:35 PM PDT 24
Peak memory 200120 kb
Host smart-9419e0b7-eac7-4142-8fef-7e799f5b69b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078400901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3078400901
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1882864011
Short name T91
Test name
Test status
Simulation time 140029058 ps
CPU time 1.24 seconds
Started May 09 12:33:22 PM PDT 24
Finished May 09 12:33:35 PM PDT 24
Peak memory 200500 kb
Host smart-3a61aff2-a396-401e-8b79-c6c1d70dc899
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882864011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1882864011
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3377537931
Short name T612
Test name
Test status
Simulation time 360527007 ps
CPU time 2.34 seconds
Started May 09 12:33:31 PM PDT 24
Finished May 09 12:33:45 PM PDT 24
Peak memory 208624 kb
Host smart-c738ddbc-303c-4990-b8fc-20ba9e1e7712
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377537931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3377537931
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.291260060
Short name T106
Test name
Test status
Simulation time 426198181 ps
CPU time 1.88 seconds
Started May 09 12:33:50 PM PDT 24
Finished May 09 12:34:00 PM PDT 24
Peak memory 200500 kb
Host smart-8c147a6e-6da9-4597-831c-6b29bd658a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291260060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
291260060
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3149990605
Short name T105
Test name
Test status
Simulation time 133656350 ps
CPU time 0.99 seconds
Started May 09 12:33:15 PM PDT 24
Finished May 09 12:33:28 PM PDT 24
Peak memory 200704 kb
Host smart-92d70f75-6a33-42e0-9015-199a2f54c65f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149990605 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3149990605
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.695744993
Short name T603
Test name
Test status
Simulation time 87650462 ps
CPU time 0.89 seconds
Started May 09 12:33:18 PM PDT 24
Finished May 09 12:33:31 PM PDT 24
Peak memory 200204 kb
Host smart-9e87d249-faff-46f2-93d6-d853fce6a195
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695744993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.695744993
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3884895753
Short name T551
Test name
Test status
Simulation time 72525113 ps
CPU time 0.92 seconds
Started May 09 12:33:35 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 200200 kb
Host smart-bd03accb-eebc-4837-b8d2-e5dbd30c2e0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884895753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3884895753
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2944635637
Short name T69
Test name
Test status
Simulation time 422732610 ps
CPU time 2.82 seconds
Started May 09 12:33:29 PM PDT 24
Finished May 09 12:33:43 PM PDT 24
Peak memory 208632 kb
Host smart-6764dbd8-c0e4-43e4-8764-cb1472157477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944635637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2944635637
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4237545443
Short name T491
Test name
Test status
Simulation time 95661363 ps
CPU time 0.82 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 200592 kb
Host smart-4490408a-df0b-4924-ac36-01019899be7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237545443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4237545443
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1087973216
Short name T376
Test name
Test status
Simulation time 1215580410 ps
CPU time 5.71 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:06 PM PDT 24
Peak memory 221436 kb
Host smart-721cab48-d6a2-417b-9cf7-8e7929a4de9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087973216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1087973216
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3312970350
Short name T296
Test name
Test status
Simulation time 245786881 ps
CPU time 1.01 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:56 PM PDT 24
Peak memory 217904 kb
Host smart-248ebfc9-8019-4b0b-b8d9-c5a8fef3da5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312970350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3312970350
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.384159213
Short name T343
Test name
Test status
Simulation time 1747876093 ps
CPU time 6.36 seconds
Started May 09 12:35:41 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 201044 kb
Host smart-4b6a38e1-c454-4e91-9ace-17fe95f52c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384159213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.384159213
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2130853142
Short name T73
Test name
Test status
Simulation time 16804334018 ps
CPU time 25 seconds
Started May 09 12:36:04 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 217612 kb
Host smart-24c9c0d3-b660-40ae-9a40-c27c509e7afe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130853142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2130853142
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3112889798
Short name T175
Test name
Test status
Simulation time 95446632 ps
CPU time 1.01 seconds
Started May 09 12:35:44 PM PDT 24
Finished May 09 12:35:51 PM PDT 24
Peak memory 200728 kb
Host smart-c7dd4aa6-ac8a-4188-b046-fc807c307c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112889798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3112889798
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.4166261043
Short name T527
Test name
Test status
Simulation time 198749322 ps
CPU time 1.38 seconds
Started May 09 12:35:41 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 201040 kb
Host smart-f7a7ea3f-05c2-4b07-a241-b04080328750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166261043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.4166261043
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1287553986
Short name T309
Test name
Test status
Simulation time 539567575 ps
CPU time 2.33 seconds
Started May 09 12:36:11 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 201000 kb
Host smart-f0675acb-d5a9-4383-b1a5-67c944e436bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287553986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1287553986
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2479497669
Short name T437
Test name
Test status
Simulation time 369363199 ps
CPU time 2.26 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:09 PM PDT 24
Peak memory 200784 kb
Host smart-59b27aa5-1b68-4564-a70f-e9ebec7e871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479497669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2479497669
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.105557242
Short name T196
Test name
Test status
Simulation time 109530273 ps
CPU time 0.89 seconds
Started May 09 12:36:00 PM PDT 24
Finished May 09 12:36:10 PM PDT 24
Peak memory 200764 kb
Host smart-4793c0cb-d9d3-4778-8175-69c947f405d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105557242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.105557242
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2008029732
Short name T510
Test name
Test status
Simulation time 79912679 ps
CPU time 0.78 seconds
Started May 09 12:35:54 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 200672 kb
Host smart-f19552ba-9018-430c-b855-e6825729bf69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008029732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2008029732
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2379872891
Short name T386
Test name
Test status
Simulation time 82445518 ps
CPU time 0.75 seconds
Started May 09 12:35:44 PM PDT 24
Finished May 09 12:35:51 PM PDT 24
Peak memory 200560 kb
Host smart-616e8a4e-5157-4a5b-b651-856cd713eb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379872891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2379872891
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3815978599
Short name T208
Test name
Test status
Simulation time 1682418559 ps
CPU time 6.29 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:36:01 PM PDT 24
Peak memory 200968 kb
Host smart-5eb3a3fd-78d7-4c31-9ed7-8ba2e868150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815978599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3815978599
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.903083880
Short name T76
Test name
Test status
Simulation time 16857868486 ps
CPU time 23.84 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:27 PM PDT 24
Peak memory 217776 kb
Host smart-e8a39b39-030b-47b3-9e29-57ca11c79b97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903083880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.903083880
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1680183443
Short name T256
Test name
Test status
Simulation time 100579977 ps
CPU time 0.97 seconds
Started May 09 12:35:47 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 200720 kb
Host smart-693739cc-d37f-496d-9d05-928fbf027d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680183443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1680183443
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1921110569
Short name T252
Test name
Test status
Simulation time 253073411 ps
CPU time 1.47 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 200972 kb
Host smart-84153827-d5ab-4ab6-ac9e-face0ff1ec79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921110569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1921110569
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2954493122
Short name T378
Test name
Test status
Simulation time 123232808 ps
CPU time 1.02 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 200748 kb
Host smart-897ebcc3-65e2-4702-a333-c94172248854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954493122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2954493122
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.129151954
Short name T202
Test name
Test status
Simulation time 492161234 ps
CPU time 2.45 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 200760 kb
Host smart-7c2e7520-7782-43b6-99dd-17ff88900868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129151954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.129151954
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3926040562
Short name T228
Test name
Test status
Simulation time 110730322 ps
CPU time 0.97 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 200848 kb
Host smart-846cdaa1-a54d-4780-8e3c-da359396e447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926040562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3926040562
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2475190647
Short name T198
Test name
Test status
Simulation time 83773430 ps
CPU time 0.87 seconds
Started May 09 12:36:11 PM PDT 24
Finished May 09 12:36:19 PM PDT 24
Peak memory 200660 kb
Host smart-fdc05e4c-c924-47a7-b16f-af7a1ea2aa88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475190647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2475190647
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2797760790
Short name T32
Test name
Test status
Simulation time 1225042284 ps
CPU time 6.01 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:06 PM PDT 24
Peak memory 222500 kb
Host smart-0788df02-946f-46e5-8fb4-5c3e28850f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797760790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2797760790
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.207803278
Short name T353
Test name
Test status
Simulation time 244038905 ps
CPU time 1.02 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 217876 kb
Host smart-b84d9ca3-05f0-433b-9345-c2c8c95e64e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207803278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.207803278
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2660195081
Short name T417
Test name
Test status
Simulation time 117940853 ps
CPU time 0.75 seconds
Started May 09 12:36:23 PM PDT 24
Finished May 09 12:36:32 PM PDT 24
Peak memory 200508 kb
Host smart-6ee0dbf3-58c9-4a70-832e-8c15311a6737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660195081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2660195081
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3870524545
Short name T424
Test name
Test status
Simulation time 2238133305 ps
CPU time 7.24 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 200988 kb
Host smart-a761a40b-5dde-4d25-b786-9d2e29bbb61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870524545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3870524545
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1162103735
Short name T486
Test name
Test status
Simulation time 182537974 ps
CPU time 1.17 seconds
Started May 09 12:35:51 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 200812 kb
Host smart-25778114-fc01-4e8c-8e9b-c72ec5ce5703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162103735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1162103735
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.218692359
Short name T396
Test name
Test status
Simulation time 233205448 ps
CPU time 1.48 seconds
Started May 09 12:36:09 PM PDT 24
Finished May 09 12:36:19 PM PDT 24
Peak memory 201040 kb
Host smart-7054daa0-8393-47c9-adec-71db2aaf06dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218692359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.218692359
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1160996315
Short name T435
Test name
Test status
Simulation time 6684539931 ps
CPU time 26.37 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:37 PM PDT 24
Peak memory 207748 kb
Host smart-62ec0966-1374-430c-a550-30835d19a3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160996315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1160996315
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2964918570
Short name T471
Test name
Test status
Simulation time 378950964 ps
CPU time 2.42 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:14 PM PDT 24
Peak memory 199448 kb
Host smart-42371f48-c008-48ec-bd7a-1ffd4bf534a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964918570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2964918570
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.905957581
Short name T255
Test name
Test status
Simulation time 247524719 ps
CPU time 1.6 seconds
Started May 09 12:36:12 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 200992 kb
Host smart-06857baa-0171-4b37-a647-8c820a20d4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905957581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.905957581
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.338396013
Short name T457
Test name
Test status
Simulation time 69779053 ps
CPU time 0.73 seconds
Started May 09 12:36:14 PM PDT 24
Finished May 09 12:36:23 PM PDT 24
Peak memory 200600 kb
Host smart-27f74b24-dfda-4156-b324-9a70c457e781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338396013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.338396013
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1489996011
Short name T51
Test name
Test status
Simulation time 1229130021 ps
CPU time 5.45 seconds
Started May 09 12:36:09 PM PDT 24
Finished May 09 12:36:22 PM PDT 24
Peak memory 217360 kb
Host smart-8337470b-beb6-48e1-b918-8bc0e7d1debc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489996011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1489996011
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1460232061
Short name T23
Test name
Test status
Simulation time 243357144 ps
CPU time 1 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:12 PM PDT 24
Peak memory 217132 kb
Host smart-a3fa8cd9-3735-4f3e-8d3a-5bb45c6a8867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460232061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1460232061
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2469745425
Short name T372
Test name
Test status
Simulation time 175152394 ps
CPU time 0.85 seconds
Started May 09 12:36:02 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 200508 kb
Host smart-03461ef0-502b-4b30-b091-936680414953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469745425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2469745425
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1301015262
Short name T45
Test name
Test status
Simulation time 1595787396 ps
CPU time 6.75 seconds
Started May 09 12:36:22 PM PDT 24
Finished May 09 12:36:42 PM PDT 24
Peak memory 201028 kb
Host smart-bd9d8ee4-08c2-408d-ab2a-60235267a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301015262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1301015262
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3644509163
Short name T334
Test name
Test status
Simulation time 170246879 ps
CPU time 1.09 seconds
Started May 09 12:36:21 PM PDT 24
Finished May 09 12:36:30 PM PDT 24
Peak memory 200704 kb
Host smart-4e71f8a1-6de1-424b-870f-45d6f6f292d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644509163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3644509163
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1190761869
Short name T262
Test name
Test status
Simulation time 267120892 ps
CPU time 1.46 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:07 PM PDT 24
Peak memory 200980 kb
Host smart-597456a2-f8c1-418f-b59b-dceece632cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190761869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1190761869
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1852760133
Short name T442
Test name
Test status
Simulation time 339447747 ps
CPU time 1.8 seconds
Started May 09 12:36:02 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 200992 kb
Host smart-a750c3a4-9079-498d-98dd-8fcbf9798d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852760133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1852760133
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1174680559
Short name T495
Test name
Test status
Simulation time 450076590 ps
CPU time 2.23 seconds
Started May 09 12:36:02 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 200684 kb
Host smart-addbd730-1fa7-4c78-ab0b-e08bc05e3424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174680559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1174680559
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.986785133
Short name T337
Test name
Test status
Simulation time 125355346 ps
CPU time 0.97 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:12 PM PDT 24
Peak memory 199276 kb
Host smart-fcaa9fab-b96f-4842-80d9-e10c11f62665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986785133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.986785133
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3784702427
Short name T445
Test name
Test status
Simulation time 87522293 ps
CPU time 0.8 seconds
Started May 09 12:36:12 PM PDT 24
Finished May 09 12:36:20 PM PDT 24
Peak memory 200556 kb
Host smart-4c015bc6-02aa-4fd7-abd4-8faf0932d21c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784702427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3784702427
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2771488467
Short name T454
Test name
Test status
Simulation time 1892788700 ps
CPU time 6.83 seconds
Started May 09 12:36:03 PM PDT 24
Finished May 09 12:36:18 PM PDT 24
Peak memory 218476 kb
Host smart-ac248bb2-01b4-42d2-ac7d-af3050a4cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771488467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2771488467
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1099216753
Short name T102
Test name
Test status
Simulation time 244491167 ps
CPU time 1.13 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:12 PM PDT 24
Peak memory 217320 kb
Host smart-53efeea2-e121-4187-aabc-d7ff1c68da91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099216753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1099216753
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.489406128
Short name T430
Test name
Test status
Simulation time 138154305 ps
CPU time 0.8 seconds
Started May 09 12:36:05 PM PDT 24
Finished May 09 12:36:14 PM PDT 24
Peak memory 200620 kb
Host smart-b53b0611-300f-4f38-bf63-1d8b2e4e4d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489406128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.489406128
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1008057965
Short name T133
Test name
Test status
Simulation time 1569744868 ps
CPU time 6.34 seconds
Started May 09 12:36:19 PM PDT 24
Finished May 09 12:36:33 PM PDT 24
Peak memory 200872 kb
Host smart-5bc31e14-3f5f-4efa-83cc-0dd98eeb2619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008057965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1008057965
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2867446606
Short name T275
Test name
Test status
Simulation time 176904700 ps
CPU time 1.14 seconds
Started May 09 12:36:08 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 200760 kb
Host smart-e784510b-f8b7-4ed9-bfcb-b72b6ef95501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867446606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2867446606
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2513924260
Short name T474
Test name
Test status
Simulation time 247408055 ps
CPU time 1.51 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 200956 kb
Host smart-4e65ffb9-a6cc-4ae9-a73c-34ee167ddb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513924260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2513924260
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2100967767
Short name T267
Test name
Test status
Simulation time 10233414018 ps
CPU time 40.8 seconds
Started May 09 12:36:12 PM PDT 24
Finished May 09 12:37:00 PM PDT 24
Peak memory 210260 kb
Host smart-5ae3b228-da41-43bf-88ef-913f9b1488db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100967767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2100967767
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2180311690
Short name T62
Test name
Test status
Simulation time 133742037 ps
CPU time 1.62 seconds
Started May 09 12:35:51 PM PDT 24
Finished May 09 12:35:59 PM PDT 24
Peak memory 200792 kb
Host smart-926f05d3-714a-4886-becf-47c9fc877809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180311690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2180311690
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3700150445
Short name T250
Test name
Test status
Simulation time 185151821 ps
CPU time 1.16 seconds
Started May 09 12:36:19 PM PDT 24
Finished May 09 12:36:33 PM PDT 24
Peak memory 200720 kb
Host smart-508f2972-21c7-403c-991f-97978ccebe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700150445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3700150445
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.45560669
Short name T413
Test name
Test status
Simulation time 2359373039 ps
CPU time 7.88 seconds
Started May 09 12:35:53 PM PDT 24
Finished May 09 12:36:09 PM PDT 24
Peak memory 222328 kb
Host smart-aa41186f-2a1e-499c-b05b-d0ba6469c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45560669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.45560669
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1564591758
Short name T506
Test name
Test status
Simulation time 244161613 ps
CPU time 1.1 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:13 PM PDT 24
Peak memory 217624 kb
Host smart-8d055ab3-d9f5-49e4-9e67-97957237f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564591758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1564591758
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2731315778
Short name T397
Test name
Test status
Simulation time 163858333 ps
CPU time 0.82 seconds
Started May 09 12:36:02 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 200588 kb
Host smart-d9c51330-feb7-4c17-8122-ffdf6f0e5a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731315778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2731315778
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3320201890
Short name T11
Test name
Test status
Simulation time 1106329439 ps
CPU time 5.09 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:04 PM PDT 24
Peak memory 200980 kb
Host smart-efc4ded1-0080-44ed-abaf-16d3a9c5f151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320201890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3320201890
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2818980257
Short name T382
Test name
Test status
Simulation time 102446477 ps
CPU time 0.97 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:05 PM PDT 24
Peak memory 200732 kb
Host smart-a34fce07-d0a4-4839-ba00-cf3a920ad4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818980257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2818980257
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.194261300
Short name T165
Test name
Test status
Simulation time 199958001 ps
CPU time 1.42 seconds
Started May 09 12:36:09 PM PDT 24
Finished May 09 12:36:18 PM PDT 24
Peak memory 200928 kb
Host smart-2819eaaa-479b-4534-a046-f2c951bd5866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194261300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.194261300
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2276977619
Short name T383
Test name
Test status
Simulation time 4977899168 ps
CPU time 17.27 seconds
Started May 09 12:37:26 PM PDT 24
Finished May 09 12:37:57 PM PDT 24
Peak memory 201068 kb
Host smart-dd81e7cf-c2c6-4627-92b6-4fdfbdb5af1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276977619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2276977619
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2431452594
Short name T145
Test name
Test status
Simulation time 124622226 ps
CPU time 1.56 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:01 PM PDT 24
Peak memory 209044 kb
Host smart-361ff9a0-86b8-4259-a456-3cd021a73170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431452594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2431452594
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2527962975
Short name T216
Test name
Test status
Simulation time 130832474 ps
CPU time 1.09 seconds
Started May 09 12:36:14 PM PDT 24
Finished May 09 12:36:32 PM PDT 24
Peak memory 200860 kb
Host smart-c27247c1-0fc5-426a-a46f-0300f3c4762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527962975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2527962975
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.838035632
Short name T497
Test name
Test status
Simulation time 64078757 ps
CPU time 0.7 seconds
Started May 09 12:36:16 PM PDT 24
Finished May 09 12:36:25 PM PDT 24
Peak memory 200704 kb
Host smart-18611195-0dc0-4014-b074-94a31067e246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838035632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.838035632
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2431448827
Short name T44
Test name
Test status
Simulation time 2359004946 ps
CPU time 7.68 seconds
Started May 09 12:36:07 PM PDT 24
Finished May 09 12:36:23 PM PDT 24
Peak memory 222356 kb
Host smart-f37e4e1d-caa0-41ff-962f-46a97f4f1ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431448827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2431448827
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3841223185
Short name T244
Test name
Test status
Simulation time 244194327 ps
CPU time 1.07 seconds
Started May 09 12:36:04 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 217900 kb
Host smart-d2307794-d989-47d2-b5db-204f127c30b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841223185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3841223185
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.951849880
Short name T305
Test name
Test status
Simulation time 220281521 ps
CPU time 0.91 seconds
Started May 09 12:36:18 PM PDT 24
Finished May 09 12:36:27 PM PDT 24
Peak memory 200504 kb
Host smart-07c5be2d-f752-45d3-bac2-146152ae1309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951849880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.951849880
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1674601443
Short name T315
Test name
Test status
Simulation time 1371830428 ps
CPU time 4.92 seconds
Started May 09 12:36:25 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 200872 kb
Host smart-2e19b3f9-f2bf-47e1-8f20-09145fb10c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674601443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1674601443
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3586553583
Short name T221
Test name
Test status
Simulation time 154541832 ps
CPU time 1.11 seconds
Started May 09 12:36:07 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 200696 kb
Host smart-fcd76074-9eb6-4f87-bf67-9096efd3e181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586553583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3586553583
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1242811212
Short name T282
Test name
Test status
Simulation time 230329469 ps
CPU time 1.4 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:14 PM PDT 24
Peak memory 200712 kb
Host smart-08fd96da-6c5a-4dc8-8d09-9a9fd8584cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242811212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1242811212
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3419564193
Short name T64
Test name
Test status
Simulation time 375248900 ps
CPU time 2.06 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:14 PM PDT 24
Peak memory 200484 kb
Host smart-e5216aa6-079d-48a0-a0d1-30d8f15cb534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419564193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3419564193
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3689419232
Short name T279
Test name
Test status
Simulation time 112456125 ps
CPU time 0.99 seconds
Started May 09 12:36:07 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 200696 kb
Host smart-dc17a3f1-2de9-4c7e-901d-06f925df4371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689419232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3689419232
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.4257831132
Short name T537
Test name
Test status
Simulation time 63363396 ps
CPU time 0.73 seconds
Started May 09 12:35:56 PM PDT 24
Finished May 09 12:36:05 PM PDT 24
Peak memory 200572 kb
Host smart-6f5237e6-e446-4a20-bdb8-83d9717d8df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257831132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.4257831132
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.751848154
Short name T371
Test name
Test status
Simulation time 1227124669 ps
CPU time 5.99 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:09 PM PDT 24
Peak memory 218756 kb
Host smart-39f2b792-9bed-4d1a-a13c-ef64c0c58777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751848154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.751848154
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3572958010
Short name T142
Test name
Test status
Simulation time 245034924 ps
CPU time 1.01 seconds
Started May 09 12:36:15 PM PDT 24
Finished May 09 12:36:25 PM PDT 24
Peak memory 218040 kb
Host smart-1715ca1f-7371-46be-91dc-c7484e87d31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572958010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3572958010
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3249023159
Short name T509
Test name
Test status
Simulation time 178274555 ps
CPU time 0.82 seconds
Started May 09 12:35:50 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 200576 kb
Host smart-b5a94f15-f89e-4b43-bbfe-bed2068eb6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249023159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3249023159
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.834898216
Short name T395
Test name
Test status
Simulation time 1405882045 ps
CPU time 5.1 seconds
Started May 09 12:36:13 PM PDT 24
Finished May 09 12:36:26 PM PDT 24
Peak memory 201056 kb
Host smart-c7118a51-03f0-4f5f-8b97-9dc61d265c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834898216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.834898216
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.474215535
Short name T161
Test name
Test status
Simulation time 172039093 ps
CPU time 1.19 seconds
Started May 09 12:36:07 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 200772 kb
Host smart-2c66cc40-f320-43c3-b2fa-ad907a9a527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474215535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.474215535
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4168530288
Short name T379
Test name
Test status
Simulation time 219407451 ps
CPU time 1.38 seconds
Started May 09 12:36:32 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 201056 kb
Host smart-6b25baf1-1918-4035-b336-1db32f333e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168530288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4168530288
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1330798813
Short name T103
Test name
Test status
Simulation time 709745288 ps
CPU time 3.36 seconds
Started May 09 12:36:17 PM PDT 24
Finished May 09 12:36:28 PM PDT 24
Peak memory 200920 kb
Host smart-25ac3086-74c7-450b-8af5-8f5154d1a139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330798813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1330798813
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2190319387
Short name T304
Test name
Test status
Simulation time 464072515 ps
CPU time 2.38 seconds
Started May 09 12:36:11 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 209200 kb
Host smart-2999b7d8-3992-4c7a-b3ca-0e96b95bdd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190319387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2190319387
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1437012139
Short name T463
Test name
Test status
Simulation time 181330553 ps
CPU time 1.24 seconds
Started May 09 12:36:15 PM PDT 24
Finished May 09 12:36:25 PM PDT 24
Peak memory 200840 kb
Host smart-01befb7c-9bcb-44e2-8955-5f3b167f2ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437012139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1437012139
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1636362671
Short name T421
Test name
Test status
Simulation time 64367476 ps
CPU time 0.81 seconds
Started May 09 12:36:27 PM PDT 24
Finished May 09 12:36:36 PM PDT 24
Peak memory 200712 kb
Host smart-0afd007a-ecfd-4804-9a7a-e0e0f8e14544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636362671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1636362671
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1348388170
Short name T380
Test name
Test status
Simulation time 1224832044 ps
CPU time 5.96 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:10 PM PDT 24
Peak memory 222424 kb
Host smart-22057f83-1be3-4872-ad2d-b03f53f5cac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348388170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1348388170
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2578205956
Short name T137
Test name
Test status
Simulation time 244902797 ps
CPU time 1.12 seconds
Started May 09 12:36:22 PM PDT 24
Finished May 09 12:36:30 PM PDT 24
Peak memory 217960 kb
Host smart-a2ec9f60-0f68-4628-a5ab-4bb65e3d2ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578205956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2578205956
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2173816370
Short name T237
Test name
Test status
Simulation time 209250494 ps
CPU time 0.96 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 200664 kb
Host smart-69374b11-7109-4894-b4de-a4343563a245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173816370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2173816370
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4264093588
Short name T331
Test name
Test status
Simulation time 1582468931 ps
CPU time 6.33 seconds
Started May 09 12:35:56 PM PDT 24
Finished May 09 12:36:11 PM PDT 24
Peak memory 201320 kb
Host smart-e362eb22-1974-404c-bcc6-e4e4a1d705cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264093588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4264093588
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1336296720
Short name T420
Test name
Test status
Simulation time 107999697 ps
CPU time 0.98 seconds
Started May 09 12:36:26 PM PDT 24
Finished May 09 12:36:36 PM PDT 24
Peak memory 200832 kb
Host smart-720a375c-7f5b-40f6-bd27-c865f3ff4c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336296720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1336296720
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.559470226
Short name T298
Test name
Test status
Simulation time 111660413 ps
CPU time 1.12 seconds
Started May 09 12:35:53 PM PDT 24
Finished May 09 12:36:02 PM PDT 24
Peak memory 200916 kb
Host smart-149a5e20-f44c-48c3-b8ce-471d9a45cc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559470226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.559470226
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2573876948
Short name T121
Test name
Test status
Simulation time 4265198143 ps
CPU time 14.67 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:15 PM PDT 24
Peak memory 210800 kb
Host smart-c82bcf85-a4f6-4826-8ee5-f9f480d60ef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573876948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2573876948
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3602806975
Short name T369
Test name
Test status
Simulation time 356664639 ps
CPU time 2.18 seconds
Started May 09 12:36:16 PM PDT 24
Finished May 09 12:36:27 PM PDT 24
Peak memory 200792 kb
Host smart-763206fc-fa3c-4fbf-ae66-81d025762193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602806975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3602806975
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2910283605
Short name T266
Test name
Test status
Simulation time 126397713 ps
CPU time 0.97 seconds
Started May 09 12:36:15 PM PDT 24
Finished May 09 12:36:25 PM PDT 24
Peak memory 200780 kb
Host smart-00d2373c-12a8-4fca-82f5-0dc257b44d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910283605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2910283605
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2398993811
Short name T465
Test name
Test status
Simulation time 63789805 ps
CPU time 0.72 seconds
Started May 09 12:35:58 PM PDT 24
Finished May 09 12:36:07 PM PDT 24
Peak memory 200664 kb
Host smart-72937ff0-e20f-4a94-9e81-eb1221a2c453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398993811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2398993811
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1220851300
Short name T54
Test name
Test status
Simulation time 2364844152 ps
CPU time 7.82 seconds
Started May 09 12:36:09 PM PDT 24
Finished May 09 12:36:23 PM PDT 24
Peak memory 222508 kb
Host smart-af0737d6-d292-46a4-8eab-5dbf2374f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220851300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1220851300
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.4147366099
Short name T157
Test name
Test status
Simulation time 243079826 ps
CPU time 1.11 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:08 PM PDT 24
Peak memory 217912 kb
Host smart-85eaf3e0-d974-403c-8975-5e66b8d201eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147366099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.4147366099
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2073120554
Short name T364
Test name
Test status
Simulation time 199651463 ps
CPU time 0.84 seconds
Started May 09 12:36:14 PM PDT 24
Finished May 09 12:36:23 PM PDT 24
Peak memory 200644 kb
Host smart-49da1693-2412-4fb4-a682-cf9e081103c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073120554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2073120554
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3766822850
Short name T204
Test name
Test status
Simulation time 804454014 ps
CPU time 3.83 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:10 PM PDT 24
Peak memory 200940 kb
Host smart-1f13fe6a-c706-4a85-838e-9660a8d224c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766822850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3766822850
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1442347238
Short name T154
Test name
Test status
Simulation time 190324520 ps
CPU time 1.33 seconds
Started May 09 12:36:18 PM PDT 24
Finished May 09 12:36:27 PM PDT 24
Peak memory 201092 kb
Host smart-f9e6e6ee-fb79-42b4-9806-c42ea5b8981b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442347238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1442347238
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3788353705
Short name T158
Test name
Test status
Simulation time 240067863 ps
CPU time 1.17 seconds
Started May 09 12:36:11 PM PDT 24
Finished May 09 12:36:19 PM PDT 24
Peak memory 200848 kb
Host smart-5b6aecec-3af1-494f-9d55-09b1e9759fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788353705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3788353705
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.359591178
Short name T229
Test name
Test status
Simulation time 138782356 ps
CPU time 1.83 seconds
Started May 09 12:36:10 PM PDT 24
Finished May 09 12:36:19 PM PDT 24
Peak memory 200788 kb
Host smart-9217b834-9447-45c5-9a09-38a8d3ea1efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359591178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.359591178
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1547213726
Short name T492
Test name
Test status
Simulation time 122900533 ps
CPU time 0.96 seconds
Started May 09 12:36:12 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 200840 kb
Host smart-ac11f833-a39c-4230-adb0-da76065b899f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547213726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1547213726
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.4277135095
Short name T422
Test name
Test status
Simulation time 82123691 ps
CPU time 0.83 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:07 PM PDT 24
Peak memory 200560 kb
Host smart-d9ab2686-ff98-4e4a-acb9-285ee0bbba5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277135095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4277135095
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2112404032
Short name T50
Test name
Test status
Simulation time 1899712462 ps
CPU time 6.56 seconds
Started May 09 12:36:17 PM PDT 24
Finished May 09 12:36:31 PM PDT 24
Peak memory 217372 kb
Host smart-18c19142-d59c-49ef-a1f9-59d960e4282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112404032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2112404032
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1420143882
Short name T308
Test name
Test status
Simulation time 243397894 ps
CPU time 1.04 seconds
Started May 09 12:36:14 PM PDT 24
Finished May 09 12:36:24 PM PDT 24
Peak memory 218064 kb
Host smart-7a4fb1ae-7390-4f4f-ab8a-dc7673a8f284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420143882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1420143882
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.580464604
Short name T20
Test name
Test status
Simulation time 170913953 ps
CPU time 0.87 seconds
Started May 09 12:36:12 PM PDT 24
Finished May 09 12:36:22 PM PDT 24
Peak memory 200632 kb
Host smart-210a2911-c948-4ec8-a7ed-c8f6950bf225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580464604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.580464604
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1555521752
Short name T519
Test name
Test status
Simulation time 778696268 ps
CPU time 4.11 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:08 PM PDT 24
Peak memory 200884 kb
Host smart-81ab8c54-db7b-45ea-b21a-ed1c6ba637cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555521752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1555521752
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.609462742
Short name T448
Test name
Test status
Simulation time 99659728 ps
CPU time 0.98 seconds
Started May 09 12:36:17 PM PDT 24
Finished May 09 12:36:26 PM PDT 24
Peak memory 200784 kb
Host smart-14d2a629-2cba-4a3d-b309-b6cb53a3ca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609462742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.609462742
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.736536128
Short name T188
Test name
Test status
Simulation time 234906359 ps
CPU time 1.52 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:08 PM PDT 24
Peak memory 200868 kb
Host smart-a9847074-d5e5-47df-9c23-c39b27038533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736536128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.736536128
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2271996205
Short name T333
Test name
Test status
Simulation time 10029573669 ps
CPU time 33.76 seconds
Started May 09 12:35:58 PM PDT 24
Finished May 09 12:36:41 PM PDT 24
Peak memory 209236 kb
Host smart-ab1560a6-6488-4077-89d0-e3079f8662ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271996205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2271996205
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3681673773
Short name T184
Test name
Test status
Simulation time 124321280 ps
CPU time 1.4 seconds
Started May 09 12:36:20 PM PDT 24
Finished May 09 12:36:29 PM PDT 24
Peak memory 200768 kb
Host smart-c4967021-18f0-43aa-a2e3-efe04d6d0e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681673773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3681673773
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.827947261
Short name T467
Test name
Test status
Simulation time 73455334 ps
CPU time 0.8 seconds
Started May 09 12:35:54 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 200716 kb
Host smart-40b6fb8a-feff-4735-9235-b53da43f5682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827947261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.827947261
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.989372196
Short name T75
Test name
Test status
Simulation time 76733574 ps
CPU time 0.8 seconds
Started May 09 12:36:13 PM PDT 24
Finished May 09 12:36:23 PM PDT 24
Peak memory 200552 kb
Host smart-b9794d05-b7d6-46da-a1f2-ae43e65d5178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989372196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.989372196
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1750953727
Short name T366
Test name
Test status
Simulation time 1222241087 ps
CPU time 5.95 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 222400 kb
Host smart-776f5fa7-3d32-43dc-b339-f34d00d6d1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750953727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1750953727
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3252888497
Short name T446
Test name
Test status
Simulation time 244790476 ps
CPU time 1.06 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:07 PM PDT 24
Peak memory 217780 kb
Host smart-e744e95f-96f5-468c-acaf-6dcec5fd8870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252888497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3252888497
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3522825792
Short name T19
Test name
Test status
Simulation time 176899448 ps
CPU time 0.88 seconds
Started May 09 12:36:15 PM PDT 24
Finished May 09 12:36:25 PM PDT 24
Peak memory 200592 kb
Host smart-efea71a0-fee4-452b-bd1d-145e3dbded53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522825792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3522825792
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2689360564
Short name T433
Test name
Test status
Simulation time 1548716283 ps
CPU time 5.84 seconds
Started May 09 12:35:56 PM PDT 24
Finished May 09 12:36:11 PM PDT 24
Peak memory 201324 kb
Host smart-a5a1e449-d932-418d-b27d-c59f3c4bc3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689360564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2689360564
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1028223522
Short name T9
Test name
Test status
Simulation time 176162420 ps
CPU time 1.17 seconds
Started May 09 12:36:24 PM PDT 24
Finished May 09 12:36:33 PM PDT 24
Peak memory 200772 kb
Host smart-a6e71499-5854-43ff-a25c-514db22a98f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028223522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1028223522
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2331777265
Short name T432
Test name
Test status
Simulation time 238911832 ps
CPU time 1.45 seconds
Started May 09 12:36:16 PM PDT 24
Finished May 09 12:36:26 PM PDT 24
Peak memory 200952 kb
Host smart-5aa0d51b-4d03-4054-ab5f-cdbb25e2bb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331777265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2331777265
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3954594416
Short name T120
Test name
Test status
Simulation time 8131550693 ps
CPU time 29.82 seconds
Started May 09 12:35:53 PM PDT 24
Finished May 09 12:36:31 PM PDT 24
Peak memory 209332 kb
Host smart-1a14f194-54bb-4613-bf56-7128d1d2e8a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954594416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3954594416
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.867148781
Short name T390
Test name
Test status
Simulation time 372777370 ps
CPU time 2.31 seconds
Started May 09 12:36:13 PM PDT 24
Finished May 09 12:36:24 PM PDT 24
Peak memory 200700 kb
Host smart-4f61b695-4e9d-4b27-b7b5-35958b328869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867148781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.867148781
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1036593131
Short name T247
Test name
Test status
Simulation time 62031235 ps
CPU time 0.79 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 200572 kb
Host smart-2b1ab382-6df4-4793-9d47-c3b6c9e4271d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036593131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1036593131
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.546296308
Short name T458
Test name
Test status
Simulation time 1229673167 ps
CPU time 5.77 seconds
Started May 09 12:35:50 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 217912 kb
Host smart-f20b3da4-6736-4b50-b465-8dd367947bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546296308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.546296308
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.40492175
Short name T499
Test name
Test status
Simulation time 243705181 ps
CPU time 1.07 seconds
Started May 09 12:36:01 PM PDT 24
Finished May 09 12:36:11 PM PDT 24
Peak memory 218084 kb
Host smart-1b3abc3c-7319-414a-9760-223f0faa8e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40492175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.40492175
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2839935357
Short name T374
Test name
Test status
Simulation time 181954280 ps
CPU time 0.89 seconds
Started May 09 12:35:43 PM PDT 24
Finished May 09 12:35:50 PM PDT 24
Peak memory 200596 kb
Host smart-e094d971-f276-4e4c-82da-1fe2eef50440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839935357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2839935357
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1148939267
Short name T358
Test name
Test status
Simulation time 1236531619 ps
CPU time 4.76 seconds
Started May 09 12:35:53 PM PDT 24
Finished May 09 12:36:06 PM PDT 24
Peak memory 201024 kb
Host smart-85b3e5e9-fcb8-4423-b9b9-57db02fa1b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148939267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1148939267
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2416582134
Short name T77
Test name
Test status
Simulation time 9428899808 ps
CPU time 14.39 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:36:05 PM PDT 24
Peak memory 218264 kb
Host smart-b1c7af7e-d9a8-4611-9cd4-b43934cccbe5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416582134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2416582134
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1184002565
Short name T456
Test name
Test status
Simulation time 177747698 ps
CPU time 1.12 seconds
Started May 09 12:35:44 PM PDT 24
Finished May 09 12:35:50 PM PDT 24
Peak memory 200792 kb
Host smart-4fcd9886-fe48-46fb-a67a-2ccd58645242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184002565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1184002565
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2698152116
Short name T139
Test name
Test status
Simulation time 122373148 ps
CPU time 1.19 seconds
Started May 09 12:36:00 PM PDT 24
Finished May 09 12:36:10 PM PDT 24
Peak memory 200956 kb
Host smart-b21ad6f1-f146-4aef-b51e-badb08950f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698152116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2698152116
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1361020699
Short name T311
Test name
Test status
Simulation time 9180056329 ps
CPU time 29.08 seconds
Started May 09 12:35:59 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 201164 kb
Host smart-a94eff95-2a8d-4325-8f8e-62fe0ec05b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361020699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1361020699
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1307516226
Short name T240
Test name
Test status
Simulation time 318945251 ps
CPU time 2.16 seconds
Started May 09 12:36:02 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 200808 kb
Host smart-02c9940a-e867-4956-bf48-c67d2325f9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307516226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1307516226
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.235786021
Short name T136
Test name
Test status
Simulation time 131615823 ps
CPU time 1.05 seconds
Started May 09 12:35:50 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 200824 kb
Host smart-94daabd3-1251-492d-95bf-9b25c3976ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235786021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.235786021
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2239218892
Short name T168
Test name
Test status
Simulation time 67029508 ps
CPU time 0.79 seconds
Started May 09 12:36:02 PM PDT 24
Finished May 09 12:36:11 PM PDT 24
Peak memory 200700 kb
Host smart-65a944eb-5f08-4eb8-b376-6517595e7d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239218892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2239218892
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1701576850
Short name T53
Test name
Test status
Simulation time 1882536219 ps
CPU time 6.89 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:07 PM PDT 24
Peak memory 222492 kb
Host smart-85182d9b-58aa-4d9f-b357-ac5ffce931d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701576850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1701576850
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3743516043
Short name T327
Test name
Test status
Simulation time 245656928 ps
CPU time 1.01 seconds
Started May 09 12:36:12 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 217740 kb
Host smart-14e5e519-462e-4e39-97a5-faab93406a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743516043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3743516043
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3418525214
Short name T490
Test name
Test status
Simulation time 156735887 ps
CPU time 0.84 seconds
Started May 09 12:35:56 PM PDT 24
Finished May 09 12:36:06 PM PDT 24
Peak memory 200488 kb
Host smart-986dafcd-dd7f-4df0-8d4d-9c2d97055a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418525214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3418525214
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2638471676
Short name T518
Test name
Test status
Simulation time 1186122408 ps
CPU time 4.9 seconds
Started May 09 12:36:00 PM PDT 24
Finished May 09 12:36:14 PM PDT 24
Peak memory 200936 kb
Host smart-823df9eb-1c21-4806-b6ea-1f794bebb7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638471676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2638471676
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3464758206
Short name T336
Test name
Test status
Simulation time 171655269 ps
CPU time 1.1 seconds
Started May 09 12:35:59 PM PDT 24
Finished May 09 12:36:09 PM PDT 24
Peak memory 200744 kb
Host smart-a7242eab-3f68-4205-a042-bc2970c47287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464758206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3464758206
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.790600917
Short name T238
Test name
Test status
Simulation time 114235063 ps
CPU time 1.13 seconds
Started May 09 12:35:59 PM PDT 24
Finished May 09 12:36:09 PM PDT 24
Peak memory 200896 kb
Host smart-9e7cbb1c-0ab9-420d-9428-e09c117d1921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790600917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.790600917
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1230872302
Short name T110
Test name
Test status
Simulation time 3159140644 ps
CPU time 13.94 seconds
Started May 09 12:36:12 PM PDT 24
Finished May 09 12:36:35 PM PDT 24
Peak memory 201036 kb
Host smart-977719de-6301-4094-98ab-4e658a583e14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230872302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1230872302
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2375307631
Short name T489
Test name
Test status
Simulation time 114036651 ps
CPU time 1.39 seconds
Started May 09 12:36:30 PM PDT 24
Finished May 09 12:36:38 PM PDT 24
Peak memory 200852 kb
Host smart-0e372498-3184-4290-a0e3-6541dc808a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375307631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2375307631
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.688995030
Short name T128
Test name
Test status
Simulation time 149875078 ps
CPU time 1.15 seconds
Started May 09 12:36:17 PM PDT 24
Finished May 09 12:36:27 PM PDT 24
Peak memory 200720 kb
Host smart-71582511-6713-45be-bcfc-bf40517f16b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688995030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.688995030
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1724443281
Short name T330
Test name
Test status
Simulation time 73698345 ps
CPU time 0.78 seconds
Started May 09 12:37:22 PM PDT 24
Finished May 09 12:37:37 PM PDT 24
Peak memory 200536 kb
Host smart-34b15b0f-c434-4427-bd94-be99d1aa1a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724443281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1724443281
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2600774687
Short name T33
Test name
Test status
Simulation time 1223158916 ps
CPU time 5.66 seconds
Started May 09 12:35:59 PM PDT 24
Finished May 09 12:36:14 PM PDT 24
Peak memory 222316 kb
Host smart-587efe58-70f0-4ce6-a967-a6b905655b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600774687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2600774687
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1995717864
Short name T277
Test name
Test status
Simulation time 245439873 ps
CPU time 1.03 seconds
Started May 09 12:37:29 PM PDT 24
Finished May 09 12:37:43 PM PDT 24
Peak memory 217828 kb
Host smart-ad93bbac-9637-42fd-9541-cd9b6292adc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995717864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1995717864
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.124638304
Short name T362
Test name
Test status
Simulation time 125912415 ps
CPU time 0.76 seconds
Started May 09 12:36:18 PM PDT 24
Finished May 09 12:36:27 PM PDT 24
Peak memory 200540 kb
Host smart-86364849-6929-474b-89db-7a8e60f93be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124638304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.124638304
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3182795454
Short name T199
Test name
Test status
Simulation time 1801383488 ps
CPU time 6.42 seconds
Started May 09 12:36:01 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 200936 kb
Host smart-168c9602-76a5-4060-81a1-cc8e61468a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182795454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3182795454
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2412909493
Short name T177
Test name
Test status
Simulation time 103572234 ps
CPU time 0.92 seconds
Started May 09 12:37:28 PM PDT 24
Finished May 09 12:37:42 PM PDT 24
Peak memory 200704 kb
Host smart-9f39d261-ff24-4599-ac09-7fbcbfdd0f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412909493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2412909493
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2268097278
Short name T143
Test name
Test status
Simulation time 115321845 ps
CPU time 1.15 seconds
Started May 09 12:36:12 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 200824 kb
Host smart-16cd45f6-efe5-4ec9-b60c-96eb64b9e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268097278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2268097278
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2719052878
Short name T253
Test name
Test status
Simulation time 8160684863 ps
CPU time 26.88 seconds
Started May 09 12:37:29 PM PDT 24
Finished May 09 12:38:09 PM PDT 24
Peak memory 209244 kb
Host smart-a45776b0-8fff-4d46-b04e-645b23772339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719052878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2719052878
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.785607558
Short name T132
Test name
Test status
Simulation time 310167506 ps
CPU time 1.92 seconds
Started May 09 12:36:17 PM PDT 24
Finished May 09 12:36:27 PM PDT 24
Peak memory 208912 kb
Host smart-a1bca7ee-6207-47ca-8e35-f3165fc35a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785607558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.785607558
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1029347915
Short name T319
Test name
Test status
Simulation time 213319964 ps
CPU time 1.34 seconds
Started May 09 12:36:42 PM PDT 24
Finished May 09 12:36:51 PM PDT 24
Peak memory 200768 kb
Host smart-f091d12a-9122-4ab2-b0a6-7855908e7d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029347915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1029347915
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1971876152
Short name T292
Test name
Test status
Simulation time 76245777 ps
CPU time 0.74 seconds
Started May 09 12:37:20 PM PDT 24
Finished May 09 12:37:35 PM PDT 24
Peak memory 200420 kb
Host smart-221a1fa7-2c83-4fca-9328-a3132bf4e9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971876152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1971876152
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3697480381
Short name T57
Test name
Test status
Simulation time 2371973227 ps
CPU time 8.32 seconds
Started May 09 12:35:56 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 218600 kb
Host smart-72f7cf23-e8d1-464b-9c3f-008033dfdd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697480381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3697480381
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1007349027
Short name T361
Test name
Test status
Simulation time 244207059 ps
CPU time 1.09 seconds
Started May 09 12:35:59 PM PDT 24
Finished May 09 12:36:09 PM PDT 24
Peak memory 218008 kb
Host smart-749de24a-c3d4-41f2-9ac5-37da5c271ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007349027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1007349027
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2441560534
Short name T464
Test name
Test status
Simulation time 131283259 ps
CPU time 0.8 seconds
Started May 09 12:37:20 PM PDT 24
Finished May 09 12:37:35 PM PDT 24
Peak memory 200396 kb
Host smart-da99c855-eb73-4770-a99c-254426ac7d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441560534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2441560534
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.529140644
Short name T293
Test name
Test status
Simulation time 1998845534 ps
CPU time 6.72 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:19 PM PDT 24
Peak memory 200088 kb
Host smart-f33245da-5c7c-4b10-91f7-19b3b0d00ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529140644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.529140644
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2197689236
Short name T281
Test name
Test status
Simulation time 110206895 ps
CPU time 0.98 seconds
Started May 09 12:36:01 PM PDT 24
Finished May 09 12:36:11 PM PDT 24
Peak memory 200856 kb
Host smart-45762996-1401-47df-9ed2-817ee1bc4eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197689236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2197689236
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1398275720
Short name T274
Test name
Test status
Simulation time 249439704 ps
CPU time 1.42 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:37:47 PM PDT 24
Peak memory 200928 kb
Host smart-9d2a5684-df21-4290-b456-4d726f594831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398275720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1398275720
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3144319519
Short name T79
Test name
Test status
Simulation time 6454550420 ps
CPU time 22.99 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:38:06 PM PDT 24
Peak memory 209264 kb
Host smart-81615ba7-11b3-495d-a013-a85a04f59b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144319519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3144319519
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2671707441
Short name T230
Test name
Test status
Simulation time 125193235 ps
CPU time 1.5 seconds
Started May 09 12:37:22 PM PDT 24
Finished May 09 12:37:38 PM PDT 24
Peak memory 208924 kb
Host smart-1fbf62ba-ee34-4865-a03c-7032fb852489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671707441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2671707441
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3087896951
Short name T207
Test name
Test status
Simulation time 103528674 ps
CPU time 0.92 seconds
Started May 09 12:36:00 PM PDT 24
Finished May 09 12:36:10 PM PDT 24
Peak memory 200828 kb
Host smart-1cff5592-0970-4d6f-88e5-ab84f8b9a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087896951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3087896951
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.842043583
Short name T438
Test name
Test status
Simulation time 78743453 ps
CPU time 0.75 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:04 PM PDT 24
Peak memory 200648 kb
Host smart-12c02cba-33fd-4911-821e-8486921b27b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842043583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.842043583
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3439727322
Short name T323
Test name
Test status
Simulation time 1897838913 ps
CPU time 6.78 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 221944 kb
Host smart-d30d86c6-271e-458e-9666-38e3a1490be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439727322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3439727322
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.789104864
Short name T415
Test name
Test status
Simulation time 244703259 ps
CPU time 1.02 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:07 PM PDT 24
Peak memory 218008 kb
Host smart-905be890-6363-4b11-bc6a-6853aec0c1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789104864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.789104864
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3318711750
Short name T531
Test name
Test status
Simulation time 79538413 ps
CPU time 0.75 seconds
Started May 09 12:35:56 PM PDT 24
Finished May 09 12:36:05 PM PDT 24
Peak memory 200688 kb
Host smart-fd812c82-245e-4435-acb4-be79117a27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318711750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3318711750
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2543367895
Short name T239
Test name
Test status
Simulation time 993374409 ps
CPU time 4.96 seconds
Started May 09 12:35:58 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 200928 kb
Host smart-3a3355cd-f4aa-43e6-934a-b81704e8e882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543367895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2543367895
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.4143261710
Short name T181
Test name
Test status
Simulation time 156832299 ps
CPU time 1.09 seconds
Started May 09 12:36:14 PM PDT 24
Finished May 09 12:36:24 PM PDT 24
Peak memory 200740 kb
Host smart-649c582e-9f71-46ba-9ccc-131d97367130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143261710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.4143261710
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3876414701
Short name T179
Test name
Test status
Simulation time 191243656 ps
CPU time 1.34 seconds
Started May 09 12:35:58 PM PDT 24
Finished May 09 12:36:09 PM PDT 24
Peak memory 201020 kb
Host smart-4944afa3-4883-487e-a0c8-042159a3ed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876414701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3876414701
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1647955422
Short name T26
Test name
Test status
Simulation time 5915244927 ps
CPU time 24.78 seconds
Started May 09 12:36:22 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 201084 kb
Host smart-0213677d-4cef-4825-9188-0fcb34fd434a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647955422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1647955422
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2558843777
Short name T232
Test name
Test status
Simulation time 121658786 ps
CPU time 1.44 seconds
Started May 09 12:36:19 PM PDT 24
Finished May 09 12:36:28 PM PDT 24
Peak memory 200768 kb
Host smart-a09c52a1-bcbc-4a33-b5f1-348efbfbc992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558843777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2558843777
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3159027772
Short name T307
Test name
Test status
Simulation time 221625337 ps
CPU time 1.31 seconds
Started May 09 12:36:17 PM PDT 24
Finished May 09 12:36:26 PM PDT 24
Peak memory 200732 kb
Host smart-9e182c3f-eb23-4307-a182-6222b044be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159027772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3159027772
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3600402862
Short name T284
Test name
Test status
Simulation time 63242334 ps
CPU time 0.75 seconds
Started May 09 12:36:27 PM PDT 24
Finished May 09 12:36:35 PM PDT 24
Peak memory 200728 kb
Host smart-9aa69684-2ce5-4169-bb91-382fa925421e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600402862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3600402862
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3342290279
Short name T36
Test name
Test status
Simulation time 2333916396 ps
CPU time 8.74 seconds
Started May 09 12:36:10 PM PDT 24
Finished May 09 12:36:26 PM PDT 24
Peak memory 218576 kb
Host smart-09e10ea1-9d87-4bac-a864-12c7252a7e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342290279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3342290279
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2292486184
Short name T345
Test name
Test status
Simulation time 244411023 ps
CPU time 1.09 seconds
Started May 09 12:36:14 PM PDT 24
Finished May 09 12:36:24 PM PDT 24
Peak memory 217872 kb
Host smart-9a227156-fdec-4397-9589-59202c408685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292486184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2292486184
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3243717083
Short name T283
Test name
Test status
Simulation time 182698787 ps
CPU time 0.88 seconds
Started May 09 12:36:32 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 200516 kb
Host smart-54a61e7e-8973-4882-bba0-0c161f926a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243717083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3243717083
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2271865443
Short name T169
Test name
Test status
Simulation time 1712827494 ps
CPU time 6.71 seconds
Started May 09 12:36:25 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 200896 kb
Host smart-07433f1b-903d-47fb-aef1-aa6e840e0f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271865443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2271865443
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3665425470
Short name T141
Test name
Test status
Simulation time 95822888 ps
CPU time 1.03 seconds
Started May 09 12:36:18 PM PDT 24
Finished May 09 12:36:27 PM PDT 24
Peak memory 200864 kb
Host smart-a84a5fc6-07a3-43c7-9002-f4af677315e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665425470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3665425470
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2547125538
Short name T473
Test name
Test status
Simulation time 251196215 ps
CPU time 1.47 seconds
Started May 09 12:36:18 PM PDT 24
Finished May 09 12:36:28 PM PDT 24
Peak memory 201040 kb
Host smart-2bb2f294-5cc7-489f-817d-ea14a6dc7e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547125538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2547125538
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3400399552
Short name T85
Test name
Test status
Simulation time 2797268709 ps
CPU time 9.31 seconds
Started May 09 12:36:11 PM PDT 24
Finished May 09 12:36:28 PM PDT 24
Peak memory 201092 kb
Host smart-e9f42678-2e96-4264-8624-5d8bf6db4bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400399552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3400399552
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.519230893
Short name T507
Test name
Test status
Simulation time 387284943 ps
CPU time 2.38 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 200696 kb
Host smart-31cc8027-de70-4cd8-bbc4-f80a704fcf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519230893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.519230893
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.69430846
Short name T258
Test name
Test status
Simulation time 196491276 ps
CPU time 1.18 seconds
Started May 09 12:36:15 PM PDT 24
Finished May 09 12:36:25 PM PDT 24
Peak memory 200804 kb
Host smart-d8598c12-57b2-423b-878f-114066fd3f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69430846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.69430846
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1942482139
Short name T313
Test name
Test status
Simulation time 86245546 ps
CPU time 0.78 seconds
Started May 09 12:36:25 PM PDT 24
Finished May 09 12:36:34 PM PDT 24
Peak memory 200560 kb
Host smart-a9edf255-6262-46bf-ae7d-cdca11d92b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942482139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1942482139
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1444163330
Short name T539
Test name
Test status
Simulation time 1221174316 ps
CPU time 5.95 seconds
Started May 09 12:36:30 PM PDT 24
Finished May 09 12:36:43 PM PDT 24
Peak memory 217468 kb
Host smart-6e83a893-e00e-42c4-b066-d70e9dbe4499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444163330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1444163330
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.752341855
Short name T494
Test name
Test status
Simulation time 243492683 ps
CPU time 1.09 seconds
Started May 09 12:36:18 PM PDT 24
Finished May 09 12:36:28 PM PDT 24
Peak memory 218080 kb
Host smart-c1c9d32a-88c1-4c43-9a88-b1f57c9af1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752341855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.752341855
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3957580806
Short name T280
Test name
Test status
Simulation time 95197967 ps
CPU time 0.73 seconds
Started May 09 12:36:21 PM PDT 24
Finished May 09 12:36:30 PM PDT 24
Peak memory 200644 kb
Host smart-d455a267-df42-4eec-b286-2671663d75d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957580806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3957580806
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1974180034
Short name T418
Test name
Test status
Simulation time 1232367451 ps
CPU time 5.57 seconds
Started May 09 12:36:06 PM PDT 24
Finished May 09 12:36:19 PM PDT 24
Peak memory 200916 kb
Host smart-69cad617-491b-4e05-84b5-344cd138b2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974180034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1974180034
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.4192228237
Short name T542
Test name
Test status
Simulation time 103118607 ps
CPU time 0.98 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:36:59 PM PDT 24
Peak memory 200756 kb
Host smart-5718bb46-bf66-4a63-8d71-d77a8f4cf119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192228237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.4192228237
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.697505434
Short name T301
Test name
Test status
Simulation time 206320819 ps
CPU time 1.42 seconds
Started May 09 12:36:23 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 201028 kb
Host smart-5922c8ef-eac4-4375-ba4f-2b12841a154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697505434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.697505434
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3921636774
Short name T356
Test name
Test status
Simulation time 4753533368 ps
CPU time 20.02 seconds
Started May 09 12:36:11 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 201036 kb
Host smart-72a657fc-ce99-4442-a5e8-6df6e4fee124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921636774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3921636774
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1459314939
Short name T414
Test name
Test status
Simulation time 129416312 ps
CPU time 1.65 seconds
Started May 09 12:36:20 PM PDT 24
Finished May 09 12:36:30 PM PDT 24
Peak memory 200784 kb
Host smart-d184a108-726e-4861-8856-e163b9107559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459314939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1459314939
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3082366740
Short name T129
Test name
Test status
Simulation time 229274463 ps
CPU time 1.45 seconds
Started May 09 12:36:27 PM PDT 24
Finished May 09 12:36:36 PM PDT 24
Peak memory 200872 kb
Host smart-8b476bb7-5b1c-4a1b-b717-e01971d6e215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082366740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3082366740
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.993567408
Short name T406
Test name
Test status
Simulation time 69493460 ps
CPU time 0.72 seconds
Started May 09 12:36:18 PM PDT 24
Finished May 09 12:36:27 PM PDT 24
Peak memory 200720 kb
Host smart-643d4776-cbcc-46b5-8dc9-399df15fcc63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993567408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.993567408
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2331559313
Short name T34
Test name
Test status
Simulation time 1216742212 ps
CPU time 5.63 seconds
Started May 09 12:36:21 PM PDT 24
Finished May 09 12:36:35 PM PDT 24
Peak memory 217660 kb
Host smart-b3fafac5-62c0-406a-b6c9-9dad47cc29a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331559313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2331559313
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1555432535
Short name T272
Test name
Test status
Simulation time 244109176 ps
CPU time 1.09 seconds
Started May 09 12:36:34 PM PDT 24
Finished May 09 12:36:42 PM PDT 24
Peak memory 218036 kb
Host smart-46920908-bff5-47e1-b409-ead10163edd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555432535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1555432535
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.4143408868
Short name T265
Test name
Test status
Simulation time 168661854 ps
CPU time 0.86 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 200612 kb
Host smart-96d8c07d-c6e4-4ef0-8125-611d262c5ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143408868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.4143408868
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.4212276386
Short name T297
Test name
Test status
Simulation time 1029169209 ps
CPU time 4.74 seconds
Started May 09 12:36:23 PM PDT 24
Finished May 09 12:36:35 PM PDT 24
Peak memory 201012 kb
Host smart-0c84376b-66b1-47e8-8325-be67d1fefec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212276386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.4212276386
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1780362459
Short name T462
Test name
Test status
Simulation time 105248873 ps
CPU time 1.01 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 200772 kb
Host smart-699b6bd3-c4ef-4f78-97a8-431c3cf8f7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780362459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1780362459
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1823168975
Short name T24
Test name
Test status
Simulation time 116449139 ps
CPU time 1.22 seconds
Started May 09 12:36:17 PM PDT 24
Finished May 09 12:36:26 PM PDT 24
Peak memory 201044 kb
Host smart-bda5ab24-4ca6-410c-8255-a67b3c839a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823168975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1823168975
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1243513973
Short name T153
Test name
Test status
Simulation time 7894631077 ps
CPU time 34.07 seconds
Started May 09 12:36:12 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 201136 kb
Host smart-560e3c87-6654-4fd1-82c7-2eb194859a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243513973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1243513973
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.796800189
Short name T409
Test name
Test status
Simulation time 145439079 ps
CPU time 1.73 seconds
Started May 09 12:36:10 PM PDT 24
Finished May 09 12:36:19 PM PDT 24
Peak memory 200764 kb
Host smart-4316b154-b148-42f8-84ae-20d69c8d1b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796800189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.796800189
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.429163180
Short name T194
Test name
Test status
Simulation time 157235474 ps
CPU time 1.18 seconds
Started May 09 12:36:23 PM PDT 24
Finished May 09 12:36:31 PM PDT 24
Peak memory 200904 kb
Host smart-35844367-aae9-4d5a-81de-a0dba3bcc9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429163180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.429163180
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2292318625
Short name T407
Test name
Test status
Simulation time 78077814 ps
CPU time 0.82 seconds
Started May 09 12:36:07 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 200940 kb
Host smart-8d26ad8c-883b-4169-9aac-6773c72ec427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292318625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2292318625
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1163222669
Short name T427
Test name
Test status
Simulation time 2188845277 ps
CPU time 8.02 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:53 PM PDT 24
Peak memory 222476 kb
Host smart-d3006751-f0d9-4611-a4a7-5850f8b24ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163222669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1163222669
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3913228476
Short name T377
Test name
Test status
Simulation time 243982810 ps
CPU time 1.06 seconds
Started May 09 12:36:19 PM PDT 24
Finished May 09 12:36:28 PM PDT 24
Peak memory 218104 kb
Host smart-fe3ef7ec-d2e3-453f-be92-88281f1f62d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913228476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3913228476
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1572262252
Short name T493
Test name
Test status
Simulation time 149948833 ps
CPU time 0.81 seconds
Started May 09 12:36:23 PM PDT 24
Finished May 09 12:36:31 PM PDT 24
Peak memory 200532 kb
Host smart-55792aff-3d6d-4430-9b02-44d5e16f1d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572262252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1572262252
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.920945610
Short name T399
Test name
Test status
Simulation time 1867003449 ps
CPU time 6.7 seconds
Started May 09 12:36:24 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 201048 kb
Host smart-2ff72bff-9ff9-4ee6-8e5d-889a37c2808e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920945610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.920945610
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1097530362
Short name T231
Test name
Test status
Simulation time 148987623 ps
CPU time 1.11 seconds
Started May 09 12:36:51 PM PDT 24
Finished May 09 12:37:03 PM PDT 24
Peak memory 200868 kb
Host smart-931d4a97-6262-478c-a800-28f70c42ea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097530362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1097530362
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3923961125
Short name T151
Test name
Test status
Simulation time 202829204 ps
CPU time 1.37 seconds
Started May 09 12:36:13 PM PDT 24
Finished May 09 12:36:23 PM PDT 24
Peak memory 201024 kb
Host smart-f6525977-88e8-4a79-bad8-8e3ab484d7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923961125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3923961125
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.582265357
Short name T324
Test name
Test status
Simulation time 5401317164 ps
CPU time 23.07 seconds
Started May 09 12:36:18 PM PDT 24
Finished May 09 12:36:49 PM PDT 24
Peak memory 209416 kb
Host smart-402ea307-4e7c-4081-a5f1-516be24d0e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582265357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.582265357
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3162433651
Short name T523
Test name
Test status
Simulation time 125914538 ps
CPU time 1.46 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:47 PM PDT 24
Peak memory 200620 kb
Host smart-4cdfabe2-6402-41fc-aa7b-8193ec0ff391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162433651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3162433651
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2890642303
Short name T47
Test name
Test status
Simulation time 70355817 ps
CPU time 0.8 seconds
Started May 09 12:36:58 PM PDT 24
Finished May 09 12:37:09 PM PDT 24
Peak memory 200848 kb
Host smart-7e55ac8b-7ace-4c55-abd1-96954deff9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890642303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2890642303
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3581369667
Short name T504
Test name
Test status
Simulation time 74066213 ps
CPU time 0.8 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:38 PM PDT 24
Peak memory 200672 kb
Host smart-2feb6411-545e-424d-8709-8772dd23684e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581369667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3581369667
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1517363590
Short name T123
Test name
Test status
Simulation time 2345924116 ps
CPU time 8.44 seconds
Started May 09 12:36:16 PM PDT 24
Finished May 09 12:36:33 PM PDT 24
Peak memory 222592 kb
Host smart-a66873a7-e199-4ff9-8199-314b84e10288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517363590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1517363590
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.767688336
Short name T29
Test name
Test status
Simulation time 243865048 ps
CPU time 1.13 seconds
Started May 09 12:36:11 PM PDT 24
Finished May 09 12:36:20 PM PDT 24
Peak memory 218056 kb
Host smart-28f0a019-8794-4010-a488-1b904808c6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767688336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.767688336
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3667774302
Short name T185
Test name
Test status
Simulation time 111951599 ps
CPU time 0.76 seconds
Started May 09 12:36:22 PM PDT 24
Finished May 09 12:36:30 PM PDT 24
Peak memory 200532 kb
Host smart-e0142e41-a758-465b-8a1b-cee511f4dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667774302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3667774302
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.295134074
Short name T391
Test name
Test status
Simulation time 934044731 ps
CPU time 4.34 seconds
Started May 09 12:36:17 PM PDT 24
Finished May 09 12:36:29 PM PDT 24
Peak memory 200948 kb
Host smart-d64765b2-aa80-414a-85da-4a6e730e6779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295134074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.295134074
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.4141463743
Short name T201
Test name
Test status
Simulation time 103148395 ps
CPU time 0.98 seconds
Started May 09 12:36:13 PM PDT 24
Finished May 09 12:36:23 PM PDT 24
Peak memory 200876 kb
Host smart-58267f78-0b1e-43a0-b1c8-a1a223521ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141463743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.4141463743
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1672291228
Short name T389
Test name
Test status
Simulation time 200996386 ps
CPU time 1.34 seconds
Started May 09 12:36:16 PM PDT 24
Finished May 09 12:36:26 PM PDT 24
Peak memory 200948 kb
Host smart-a0cfdb59-5aa4-4745-9bc3-0365bdb35df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672291228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1672291228
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3492601872
Short name T348
Test name
Test status
Simulation time 2077593370 ps
CPU time 7.78 seconds
Started May 09 12:36:15 PM PDT 24
Finished May 09 12:36:31 PM PDT 24
Peak memory 210048 kb
Host smart-1cbd9130-879d-4dff-be19-adc40f33fffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492601872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3492601872
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1875051390
Short name T80
Test name
Test status
Simulation time 372085007 ps
CPU time 1.95 seconds
Started May 09 12:36:14 PM PDT 24
Finished May 09 12:36:24 PM PDT 24
Peak memory 200836 kb
Host smart-c76b9703-5bcc-4c4d-959e-13f2b2ea105a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875051390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1875051390
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2172882387
Short name T352
Test name
Test status
Simulation time 230822879 ps
CPU time 1.52 seconds
Started May 09 12:36:28 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 200944 kb
Host smart-78de29b3-b121-4014-a29a-af61e643c451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172882387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2172882387
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2340882865
Short name T167
Test name
Test status
Simulation time 66700291 ps
CPU time 0.73 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:53 PM PDT 24
Peak memory 200720 kb
Host smart-0794e622-f753-44c4-b985-d73a5d6f6e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340882865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2340882865
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2287604008
Short name T453
Test name
Test status
Simulation time 244527776 ps
CPU time 1.05 seconds
Started May 09 12:36:57 PM PDT 24
Finished May 09 12:37:08 PM PDT 24
Peak memory 218016 kb
Host smart-00588268-ad46-4a7a-b492-ddd0554dcfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287604008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2287604008
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.173715346
Short name T513
Test name
Test status
Simulation time 130070888 ps
CPU time 0.83 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 200516 kb
Host smart-021d0447-5153-4bd6-be5e-1873186c7383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173715346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.173715346
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.4238542375
Short name T264
Test name
Test status
Simulation time 1194948108 ps
CPU time 5.05 seconds
Started May 09 12:36:16 PM PDT 24
Finished May 09 12:36:30 PM PDT 24
Peak memory 201044 kb
Host smart-7645dd65-09c0-489e-afe0-27bf7f9fcfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238542375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4238542375
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.811443982
Short name T3
Test name
Test status
Simulation time 169285521 ps
CPU time 1.18 seconds
Started May 09 12:36:28 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 200744 kb
Host smart-d7960171-cf3d-45d0-86f1-551affa72df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811443982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.811443982
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3397686091
Short name T355
Test name
Test status
Simulation time 196074729 ps
CPU time 1.36 seconds
Started May 09 12:36:24 PM PDT 24
Finished May 09 12:36:33 PM PDT 24
Peak memory 201056 kb
Host smart-0af0c297-60e8-4b09-ae44-fa72c1fbb643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397686091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3397686091
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3686203480
Short name T7
Test name
Test status
Simulation time 11218447490 ps
CPU time 36 seconds
Started May 09 12:36:21 PM PDT 24
Finished May 09 12:37:05 PM PDT 24
Peak memory 201180 kb
Host smart-fda59e10-37f1-4a44-b378-9e30735472ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686203480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3686203480
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3633461940
Short name T444
Test name
Test status
Simulation time 349742000 ps
CPU time 2.18 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:47 PM PDT 24
Peak memory 200804 kb
Host smart-00b4faf9-1a8b-461e-918d-9959a0369e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633461940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3633461940
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3504549507
Short name T241
Test name
Test status
Simulation time 69158356 ps
CPU time 0.81 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 200864 kb
Host smart-33cb66d2-3af4-4d16-8ccf-5bbfe6d98924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504549507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3504549507
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1102619686
Short name T197
Test name
Test status
Simulation time 56078488 ps
CPU time 0.72 seconds
Started May 09 12:36:05 PM PDT 24
Finished May 09 12:36:14 PM PDT 24
Peak memory 200580 kb
Host smart-55566edc-81aa-4104-836d-dd03231a388c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102619686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1102619686
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3345958657
Short name T59
Test name
Test status
Simulation time 2357126202 ps
CPU time 8.01 seconds
Started May 09 12:35:38 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 218180 kb
Host smart-913940bf-45c2-4fd2-a1f4-360e7f9f6474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345958657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3345958657
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3832977355
Short name T468
Test name
Test status
Simulation time 245317136 ps
CPU time 1.08 seconds
Started May 09 12:35:53 PM PDT 24
Finished May 09 12:36:02 PM PDT 24
Peak memory 217952 kb
Host smart-f23b6039-725e-4f48-8b04-447bb9487936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832977355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3832977355
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2291008034
Short name T425
Test name
Test status
Simulation time 181916549 ps
CPU time 0.83 seconds
Started May 09 12:35:53 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 200612 kb
Host smart-b1d0f288-5407-40de-bfaf-486c5cf6f0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291008034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2291008034
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.863678666
Short name T350
Test name
Test status
Simulation time 1155628020 ps
CPU time 4.52 seconds
Started May 09 12:35:40 PM PDT 24
Finished May 09 12:35:50 PM PDT 24
Peak memory 200992 kb
Host smart-9e72226d-838f-42cf-b0e9-c075f6ee3d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863678666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.863678666
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3855738757
Short name T429
Test name
Test status
Simulation time 145665479 ps
CPU time 1.04 seconds
Started May 09 12:36:07 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 200852 kb
Host smart-7a046d15-6781-4eb5-8257-46a688a597de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855738757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3855738757
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2815479549
Short name T170
Test name
Test status
Simulation time 203237514 ps
CPU time 1.37 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:02 PM PDT 24
Peak memory 200968 kb
Host smart-18260536-7fd4-4c4f-a249-9dd5d6eda08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815479549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2815479549
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2579587596
Short name T288
Test name
Test status
Simulation time 5958362807 ps
CPU time 26.06 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 209204 kb
Host smart-3ab5aaf2-9e2d-4057-b04a-9e612cc855a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579587596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2579587596
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.4069770917
Short name T365
Test name
Test status
Simulation time 143316103 ps
CPU time 1.63 seconds
Started May 09 12:35:51 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 200824 kb
Host smart-73f0d385-33fb-4531-941a-c5a50fe02c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069770917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4069770917
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.92754018
Short name T360
Test name
Test status
Simulation time 212495775 ps
CPU time 1.41 seconds
Started May 09 12:35:47 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 200764 kb
Host smart-d1786ad7-3dd6-40d5-9373-401d6ad7386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92754018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.92754018
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1021506508
Short name T325
Test name
Test status
Simulation time 74075100 ps
CPU time 0.8 seconds
Started May 09 12:36:32 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 200684 kb
Host smart-ece3a366-27e1-4985-9495-64030bb865c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021506508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1021506508
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3398260801
Short name T37
Test name
Test status
Simulation time 1221951174 ps
CPU time 6.05 seconds
Started May 09 12:36:33 PM PDT 24
Finished May 09 12:36:45 PM PDT 24
Peak memory 218372 kb
Host smart-0d8b550a-aa62-4fda-a44f-85b908e78f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398260801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3398260801
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.4292439376
Short name T538
Test name
Test status
Simulation time 244698314 ps
CPU time 1.12 seconds
Started May 09 12:36:25 PM PDT 24
Finished May 09 12:36:34 PM PDT 24
Peak memory 217992 kb
Host smart-bb73f279-9873-4c74-8d6e-52e092dca200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292439376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.4292439376
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1559214408
Short name T375
Test name
Test status
Simulation time 208624148 ps
CPU time 0.9 seconds
Started May 09 12:36:26 PM PDT 24
Finished May 09 12:36:35 PM PDT 24
Peak memory 200564 kb
Host smart-20104bc0-a821-489f-a694-eae4db6de164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559214408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1559214408
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1038730282
Short name T412
Test name
Test status
Simulation time 1997884636 ps
CPU time 8.45 seconds
Started May 09 12:36:29 PM PDT 24
Finished May 09 12:36:45 PM PDT 24
Peak memory 200956 kb
Host smart-5102f490-9194-46e0-9eeb-dae035a493df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038730282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1038730282
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.650327051
Short name T344
Test name
Test status
Simulation time 104567582 ps
CPU time 1.02 seconds
Started May 09 12:36:35 PM PDT 24
Finished May 09 12:36:42 PM PDT 24
Peak memory 200848 kb
Host smart-b6fa2781-0b86-4cd8-973d-5911b53250c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650327051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.650327051
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.817647099
Short name T363
Test name
Test status
Simulation time 198667147 ps
CPU time 1.36 seconds
Started May 09 12:36:24 PM PDT 24
Finished May 09 12:36:33 PM PDT 24
Peak memory 201040 kb
Host smart-c801e463-29d1-49e2-a7c5-63a7be065f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817647099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.817647099
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1720060004
Short name T171
Test name
Test status
Simulation time 1206250208 ps
CPU time 5.34 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 200900 kb
Host smart-edae525e-14f2-4eb0-8c81-284db2d43d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720060004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1720060004
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.561794106
Short name T4
Test name
Test status
Simulation time 386167209 ps
CPU time 2.15 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 200856 kb
Host smart-5efd7673-d308-40e0-bbbe-2bd679f980ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561794106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.561794106
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3460564314
Short name T401
Test name
Test status
Simulation time 149359327 ps
CPU time 1.02 seconds
Started May 09 12:36:40 PM PDT 24
Finished May 09 12:36:48 PM PDT 24
Peak memory 200880 kb
Host smart-e9771cf8-8b17-45e8-834a-56fa1b9bc2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460564314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3460564314
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2798475145
Short name T321
Test name
Test status
Simulation time 75573678 ps
CPU time 0.8 seconds
Started May 09 12:36:30 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 200696 kb
Host smart-bb41f7af-1ec7-4355-8b3a-498c4cfa6168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798475145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2798475145
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3220905316
Short name T367
Test name
Test status
Simulation time 1224530610 ps
CPU time 5.63 seconds
Started May 09 12:36:27 PM PDT 24
Finished May 09 12:36:41 PM PDT 24
Peak memory 222528 kb
Host smart-6aff67c7-3d0f-495b-b0d5-03f9e37b4c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220905316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3220905316
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.927098135
Short name T249
Test name
Test status
Simulation time 244950782 ps
CPU time 1.07 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 217948 kb
Host smart-c8521791-416c-4727-909f-6c5770aa919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927098135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.927098135
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3187450130
Short name T18
Test name
Test status
Simulation time 146081318 ps
CPU time 0.83 seconds
Started May 09 12:36:22 PM PDT 24
Finished May 09 12:36:30 PM PDT 24
Peak memory 200584 kb
Host smart-37060103-4838-43ac-85a7-725e2409f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187450130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3187450130
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.197214455
Short name T84
Test name
Test status
Simulation time 1203172421 ps
CPU time 5.25 seconds
Started May 09 12:36:41 PM PDT 24
Finished May 09 12:36:53 PM PDT 24
Peak memory 200988 kb
Host smart-29f370ca-65f5-426c-a813-2124b767c15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197214455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.197214455
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1316733868
Short name T159
Test name
Test status
Simulation time 109780307 ps
CPU time 0.95 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:37:24 PM PDT 24
Peak memory 200824 kb
Host smart-f9566245-50d7-4ace-b7ee-e68b52394fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316733868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1316733868
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1988017200
Short name T317
Test name
Test status
Simulation time 239373006 ps
CPU time 1.4 seconds
Started May 09 12:36:41 PM PDT 24
Finished May 09 12:36:51 PM PDT 24
Peak memory 200900 kb
Host smart-67be290c-d1d3-44a8-b885-d13e9a893dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988017200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1988017200
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3175196265
Short name T155
Test name
Test status
Simulation time 1231329727 ps
CPU time 6.2 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:44 PM PDT 24
Peak memory 209116 kb
Host smart-416a0f92-db28-4b69-bd3a-35dde1158af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175196265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3175196265
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.206084519
Short name T190
Test name
Test status
Simulation time 468566947 ps
CPU time 2.68 seconds
Started May 09 12:36:25 PM PDT 24
Finished May 09 12:36:38 PM PDT 24
Peak memory 200856 kb
Host smart-7ad6f2be-24d8-4872-b3e6-6649a5134c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206084519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.206084519
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3356334248
Short name T150
Test name
Test status
Simulation time 85856218 ps
CPU time 0.87 seconds
Started May 09 12:36:20 PM PDT 24
Finished May 09 12:36:29 PM PDT 24
Peak memory 200816 kb
Host smart-8e7cda1c-e7bc-439f-b224-2ded07f252d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356334248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3356334248
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1136704288
Short name T370
Test name
Test status
Simulation time 71234503 ps
CPU time 0.74 seconds
Started May 09 12:36:37 PM PDT 24
Finished May 09 12:36:45 PM PDT 24
Peak memory 200668 kb
Host smart-2272cb9a-5f3a-4520-956a-89d47ae76a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136704288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1136704288
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.4173611649
Short name T423
Test name
Test status
Simulation time 1895174694 ps
CPU time 7.14 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:07 PM PDT 24
Peak memory 217900 kb
Host smart-5f51066d-2325-454c-a64a-f3fc41c7cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173611649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4173611649
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.455446287
Short name T193
Test name
Test status
Simulation time 243862149 ps
CPU time 1.17 seconds
Started May 09 12:36:36 PM PDT 24
Finished May 09 12:36:44 PM PDT 24
Peak memory 217908 kb
Host smart-bc07888e-4ce5-45c4-af87-3e4d3d0a8578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455446287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.455446287
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3673101759
Short name T14
Test name
Test status
Simulation time 160611270 ps
CPU time 0.91 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 200620 kb
Host smart-dff95757-2131-4f32-aef3-e5a11f96ee4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673101759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3673101759
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.80186716
Short name T287
Test name
Test status
Simulation time 896240104 ps
CPU time 4.45 seconds
Started May 09 12:36:30 PM PDT 24
Finished May 09 12:36:41 PM PDT 24
Peak memory 200988 kb
Host smart-24bf3f10-aca3-4c5d-a4de-902b2717e2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80186716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.80186716
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1327511115
Short name T387
Test name
Test status
Simulation time 180569854 ps
CPU time 1.11 seconds
Started May 09 12:36:24 PM PDT 24
Finished May 09 12:36:32 PM PDT 24
Peak memory 200780 kb
Host smart-2ff17d10-a9d3-4b48-80a3-4d31f1285e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327511115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1327511115
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3127778696
Short name T455
Test name
Test status
Simulation time 112200052 ps
CPU time 1.17 seconds
Started May 09 12:36:28 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 201024 kb
Host smart-efccca3d-a3ca-4f27-bc5d-f2385a8fa7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127778696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3127778696
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.858320437
Short name T122
Test name
Test status
Simulation time 5404272629 ps
CPU time 19.56 seconds
Started May 09 12:37:06 PM PDT 24
Finished May 09 12:37:38 PM PDT 24
Peak memory 201172 kb
Host smart-fd541e68-11b3-48ae-9c8b-ddb93dacf6c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858320437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.858320437
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3083627087
Short name T517
Test name
Test status
Simulation time 338530233 ps
CPU time 2.06 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 209048 kb
Host smart-65c1bf69-c8c0-4adc-9789-2ec08ea8caca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083627087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3083627087
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3273929810
Short name T320
Test name
Test status
Simulation time 163448311 ps
CPU time 1.07 seconds
Started May 09 12:36:29 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 200812 kb
Host smart-0cbff6ee-39a7-4c4e-a757-df48a6a898c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273929810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3273929810
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.413343277
Short name T174
Test name
Test status
Simulation time 70776747 ps
CPU time 0.76 seconds
Started May 09 12:36:33 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 200608 kb
Host smart-0a7f49a5-6ff8-4400-977a-c6ef4be97f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413343277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.413343277
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3993697374
Short name T58
Test name
Test status
Simulation time 1889762472 ps
CPU time 7.94 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:08 PM PDT 24
Peak memory 218396 kb
Host smart-1c678cff-8cca-44ae-8b12-527a363f304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993697374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3993697374
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2854940862
Short name T285
Test name
Test status
Simulation time 244275853 ps
CPU time 1.18 seconds
Started May 09 12:36:50 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 218072 kb
Host smart-2b7fbbcb-357c-4fe4-b023-0440c37415ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854940862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2854940862
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.4013279795
Short name T394
Test name
Test status
Simulation time 125486874 ps
CPU time 0.8 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 200648 kb
Host smart-3c8dd057-ee28-4ede-82c4-fd99e4775adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013279795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.4013279795
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3085794106
Short name T83
Test name
Test status
Simulation time 2150458073 ps
CPU time 7.77 seconds
Started May 09 12:36:50 PM PDT 24
Finished May 09 12:37:08 PM PDT 24
Peak memory 201156 kb
Host smart-7bfd1c04-894d-449c-ab56-dacd756bf4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085794106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3085794106
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.446999492
Short name T152
Test name
Test status
Simulation time 97995187 ps
CPU time 0.94 seconds
Started May 09 12:36:37 PM PDT 24
Finished May 09 12:36:44 PM PDT 24
Peak memory 200800 kb
Host smart-9400c956-7288-4a8c-a71a-ea3f52aa012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446999492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.446999492
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1102444171
Short name T160
Test name
Test status
Simulation time 130021939 ps
CPU time 1.27 seconds
Started May 09 12:36:36 PM PDT 24
Finished May 09 12:36:44 PM PDT 24
Peak memory 200936 kb
Host smart-74ccd3f9-73fa-4329-afb6-58e20656316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102444171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1102444171
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3548985077
Short name T173
Test name
Test status
Simulation time 6121464134 ps
CPU time 24.78 seconds
Started May 09 12:36:53 PM PDT 24
Finished May 09 12:37:28 PM PDT 24
Peak memory 201124 kb
Host smart-89d76b2e-f5a7-46a7-a497-319a9d40bccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548985077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3548985077
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3739054722
Short name T217
Test name
Test status
Simulation time 416329830 ps
CPU time 2.4 seconds
Started May 09 12:36:23 PM PDT 24
Finished May 09 12:36:33 PM PDT 24
Peak memory 200880 kb
Host smart-ff6cb68e-9ee2-4d66-9a09-632a2175f32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739054722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3739054722
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2765870751
Short name T524
Test name
Test status
Simulation time 83569921 ps
CPU time 0.85 seconds
Started May 09 12:36:27 PM PDT 24
Finished May 09 12:36:36 PM PDT 24
Peak memory 200852 kb
Host smart-7a2f9b5f-f19f-425c-8867-028a3dfe53a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765870751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2765870751
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2935907848
Short name T385
Test name
Test status
Simulation time 71907863 ps
CPU time 0.74 seconds
Started May 09 12:37:09 PM PDT 24
Finished May 09 12:37:23 PM PDT 24
Peak memory 200636 kb
Host smart-9f96df70-2111-4a5f-86c2-e8ace9a2915f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935907848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2935907848
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.918467712
Short name T384
Test name
Test status
Simulation time 1215702198 ps
CPU time 5.52 seconds
Started May 09 12:37:11 PM PDT 24
Finished May 09 12:37:30 PM PDT 24
Peak memory 222564 kb
Host smart-45157864-722c-42e9-890b-3251ee78dea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918467712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.918467712
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3411505959
Short name T246
Test name
Test status
Simulation time 244535475 ps
CPU time 1.07 seconds
Started May 09 12:36:27 PM PDT 24
Finished May 09 12:36:36 PM PDT 24
Peak memory 217952 kb
Host smart-018c3143-71c3-41e0-a518-e5168048e38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411505959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3411505959
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3002816038
Short name T243
Test name
Test status
Simulation time 222448436 ps
CPU time 1.01 seconds
Started May 09 12:36:37 PM PDT 24
Finished May 09 12:36:44 PM PDT 24
Peak memory 200708 kb
Host smart-f2d5e060-63b5-4a5d-8ef6-21768004150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002816038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3002816038
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3195102006
Short name T214
Test name
Test status
Simulation time 898241662 ps
CPU time 4.48 seconds
Started May 09 12:36:23 PM PDT 24
Finished May 09 12:36:35 PM PDT 24
Peak memory 201088 kb
Host smart-c5a366d7-8065-4fef-98c2-7074898a74ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195102006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3195102006
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2030864610
Short name T496
Test name
Test status
Simulation time 111288907 ps
CPU time 1 seconds
Started May 09 12:36:29 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 200908 kb
Host smart-a9238b51-d300-4e54-82f3-a2ffe1071902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030864610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2030864610
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3083174835
Short name T224
Test name
Test status
Simulation time 201321546 ps
CPU time 1.3 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 200980 kb
Host smart-252a1e2a-49e1-4e26-a9a2-029bb33b9101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083174835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3083174835
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2577393033
Short name T431
Test name
Test status
Simulation time 4565533343 ps
CPU time 19.72 seconds
Started May 09 12:36:40 PM PDT 24
Finished May 09 12:37:07 PM PDT 24
Peak memory 210120 kb
Host smart-2dd2cb5c-58cf-4d4c-ac15-5e69a7ef1349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577393033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2577393033
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1415460584
Short name T205
Test name
Test status
Simulation time 459901333 ps
CPU time 2.31 seconds
Started May 09 12:36:37 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 208916 kb
Host smart-32414208-a979-4fd5-b3f4-79400f0b59ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415460584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1415460584
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.124913770
Short name T368
Test name
Test status
Simulation time 79563246 ps
CPU time 0.79 seconds
Started May 09 12:36:29 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 200856 kb
Host smart-df0e4d61-01cd-42a1-8713-feffe4e5ff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124913770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.124913770
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3784935069
Short name T215
Test name
Test status
Simulation time 91328774 ps
CPU time 0.82 seconds
Started May 09 12:36:52 PM PDT 24
Finished May 09 12:37:04 PM PDT 24
Peak memory 200544 kb
Host smart-4a9db63a-8736-4a8c-a668-4187e3ab453a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784935069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3784935069
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.153022315
Short name T460
Test name
Test status
Simulation time 2185251303 ps
CPU time 8.66 seconds
Started May 09 12:36:26 PM PDT 24
Finished May 09 12:36:42 PM PDT 24
Peak memory 218616 kb
Host smart-6cb08569-c42e-42d6-a299-efe8419b01aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153022315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.153022315
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3566381606
Short name T156
Test name
Test status
Simulation time 243742177 ps
CPU time 1.14 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:36:57 PM PDT 24
Peak memory 217940 kb
Host smart-cee6c28f-b26e-4549-ad93-8c62ce0dfda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566381606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3566381606
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.846742759
Short name T22
Test name
Test status
Simulation time 143778435 ps
CPU time 0.81 seconds
Started May 09 12:36:33 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 200560 kb
Host smart-e07a071d-3509-4b7f-aba0-edf23bbf0432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846742759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.846742759
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2806068959
Short name T300
Test name
Test status
Simulation time 957157283 ps
CPU time 4.99 seconds
Started May 09 12:36:29 PM PDT 24
Finished May 09 12:36:41 PM PDT 24
Peak memory 201048 kb
Host smart-72dd7778-829d-43f9-b3cc-7cf93d25526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806068959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2806068959
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1340766848
Short name T259
Test name
Test status
Simulation time 108570019 ps
CPU time 0.99 seconds
Started May 09 12:36:29 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 200764 kb
Host smart-803f7dbd-40b7-4905-8339-be773ce1b26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340766848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1340766848
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1236278312
Short name T8
Test name
Test status
Simulation time 236205656 ps
CPU time 1.4 seconds
Started May 09 12:36:51 PM PDT 24
Finished May 09 12:37:03 PM PDT 24
Peak memory 201084 kb
Host smart-9ffa4428-d8e8-4c19-9baf-579b8297c1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236278312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1236278312
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3969357771
Short name T388
Test name
Test status
Simulation time 5366079173 ps
CPU time 19.78 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:37:13 PM PDT 24
Peak memory 209340 kb
Host smart-a6b314ec-d01b-4a35-91c4-d5a8e2fe0a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969357771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3969357771
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3293169403
Short name T42
Test name
Test status
Simulation time 539828617 ps
CPU time 2.65 seconds
Started May 09 12:36:56 PM PDT 24
Finished May 09 12:37:09 PM PDT 24
Peak memory 200696 kb
Host smart-7505ab5a-6044-4b85-8c8b-30fa9b0daf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293169403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3293169403
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1965468238
Short name T322
Test name
Test status
Simulation time 149283509 ps
CPU time 1.18 seconds
Started May 09 12:36:37 PM PDT 24
Finished May 09 12:36:50 PM PDT 24
Peak memory 200748 kb
Host smart-6de010b1-898b-446b-9b45-d8a8ee8c000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965468238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1965468238
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2772818342
Short name T392
Test name
Test status
Simulation time 75771409 ps
CPU time 0.76 seconds
Started May 09 12:37:03 PM PDT 24
Finished May 09 12:37:15 PM PDT 24
Peak memory 200648 kb
Host smart-c2a0cb03-fd7a-4360-b487-df5001204f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772818342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2772818342
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1847629214
Short name T439
Test name
Test status
Simulation time 1223744739 ps
CPU time 5.31 seconds
Started May 09 12:36:27 PM PDT 24
Finished May 09 12:36:41 PM PDT 24
Peak memory 222504 kb
Host smart-de3a3381-1753-4d73-ac59-921d58868a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847629214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1847629214
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.959574073
Short name T381
Test name
Test status
Simulation time 244912201 ps
CPU time 1.08 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:47 PM PDT 24
Peak memory 217992 kb
Host smart-4076c4ed-1ca0-40a3-821a-0af3296c0f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959574073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.959574073
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.254613523
Short name T290
Test name
Test status
Simulation time 163566499 ps
CPU time 0.85 seconds
Started May 09 12:36:51 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 200632 kb
Host smart-6a9325f0-4f65-4195-bb74-21c2b2acb897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254613523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.254613523
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2366557791
Short name T349
Test name
Test status
Simulation time 932821203 ps
CPU time 4.64 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 201024 kb
Host smart-fb73a54f-b7d7-48f1-8c0f-c40bdbf2f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366557791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2366557791
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2831597829
Short name T43
Test name
Test status
Simulation time 178407767 ps
CPU time 1.16 seconds
Started May 09 12:36:30 PM PDT 24
Finished May 09 12:36:38 PM PDT 24
Peak memory 200732 kb
Host smart-5b0e2a10-d5a0-450a-ab41-81b8426f71d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831597829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2831597829
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3357801386
Short name T436
Test name
Test status
Simulation time 246698613 ps
CPU time 1.4 seconds
Started May 09 12:36:41 PM PDT 24
Finished May 09 12:36:56 PM PDT 24
Peak memory 200992 kb
Host smart-2d0e5b0d-1ccb-452b-8747-bcfb095db052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357801386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3357801386
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2981319272
Short name T144
Test name
Test status
Simulation time 9844989347 ps
CPU time 39.99 seconds
Started May 09 12:36:27 PM PDT 24
Finished May 09 12:37:15 PM PDT 24
Peak memory 209356 kb
Host smart-389209e6-93e8-42b3-a4f6-101ad553116e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981319272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2981319272
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2423412124
Short name T359
Test name
Test status
Simulation time 394243775 ps
CPU time 2.41 seconds
Started May 09 12:36:30 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 200840 kb
Host smart-619e9faf-fcf9-4ea7-8bca-a01fa569f4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423412124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2423412124
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.526904323
Short name T351
Test name
Test status
Simulation time 125496963 ps
CPU time 0.99 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 200764 kb
Host smart-9a8ca5ee-d85a-4659-8368-4082be57a90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526904323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.526904323
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.685425269
Short name T191
Test name
Test status
Simulation time 66407019 ps
CPU time 0.73 seconds
Started May 09 12:37:09 PM PDT 24
Finished May 09 12:37:24 PM PDT 24
Peak memory 200700 kb
Host smart-0fc0781d-adaa-4ad8-8eab-3e47b8211cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685425269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.685425269
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2576348057
Short name T31
Test name
Test status
Simulation time 2352553385 ps
CPU time 8.72 seconds
Started May 09 12:36:57 PM PDT 24
Finished May 09 12:37:16 PM PDT 24
Peak memory 218596 kb
Host smart-50be2fce-c386-40a7-b15c-97d7a5bbd91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576348057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2576348057
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3852511647
Short name T400
Test name
Test status
Simulation time 244571791 ps
CPU time 1.06 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 218164 kb
Host smart-c9e6a704-c071-47c7-bdd1-c21a8e31e77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852511647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3852511647
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.592480297
Short name T186
Test name
Test status
Simulation time 154363204 ps
CPU time 0.91 seconds
Started May 09 12:36:33 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 200612 kb
Host smart-fb715038-82c9-4bb6-8614-28fb0cc8b04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592480297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.592480297
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2826067096
Short name T451
Test name
Test status
Simulation time 1522368299 ps
CPU time 5.37 seconds
Started May 09 12:36:58 PM PDT 24
Finished May 09 12:37:14 PM PDT 24
Peak memory 200968 kb
Host smart-149994b2-4afe-459f-88c4-294e255be34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826067096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2826067096
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1094104477
Short name T220
Test name
Test status
Simulation time 148699301 ps
CPU time 1.12 seconds
Started May 09 12:36:33 PM PDT 24
Finished May 09 12:36:41 PM PDT 24
Peak memory 201116 kb
Host smart-5b43697a-840b-4202-a6ba-4433a61fb08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094104477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1094104477
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1799110455
Short name T13
Test name
Test status
Simulation time 242288085 ps
CPU time 1.55 seconds
Started May 09 12:36:25 PM PDT 24
Finished May 09 12:36:34 PM PDT 24
Peak memory 201020 kb
Host smart-ff5f9aa1-1b56-4e35-a601-d360ba909979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799110455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1799110455
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1053050187
Short name T81
Test name
Test status
Simulation time 9019069633 ps
CPU time 33.55 seconds
Started May 09 12:36:40 PM PDT 24
Finished May 09 12:37:21 PM PDT 24
Peak memory 209304 kb
Host smart-365eee07-26e8-4790-a3c9-0e35e6cd9937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053050187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1053050187
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2274691814
Short name T236
Test name
Test status
Simulation time 456544309 ps
CPU time 2.33 seconds
Started May 09 12:36:36 PM PDT 24
Finished May 09 12:36:45 PM PDT 24
Peak memory 200856 kb
Host smart-8e4cd0a9-6cd6-4c4f-9ffa-1f9d3af8b202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274691814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2274691814
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3179006525
Short name T347
Test name
Test status
Simulation time 59733301 ps
CPU time 0.73 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 200868 kb
Host smart-5ca28240-d5fd-44f6-a46a-9f1e611f2703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179006525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3179006525
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2347628573
Short name T487
Test name
Test status
Simulation time 65365677 ps
CPU time 0.73 seconds
Started May 09 12:36:59 PM PDT 24
Finished May 09 12:37:10 PM PDT 24
Peak memory 200552 kb
Host smart-297cd985-f159-4167-b7d9-2fb280489960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347628573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2347628573
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1126438054
Short name T498
Test name
Test status
Simulation time 1885174290 ps
CPU time 6.76 seconds
Started May 09 12:37:02 PM PDT 24
Finished May 09 12:37:20 PM PDT 24
Peak memory 218292 kb
Host smart-74482438-fe57-44ab-a2c8-5df6543b76f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126438054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1126438054
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.375091839
Short name T332
Test name
Test status
Simulation time 243952075 ps
CPU time 1.02 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 218120 kb
Host smart-b3d660ed-ae22-47a5-b48a-bfd45cb56efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375091839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.375091839
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3691548928
Short name T470
Test name
Test status
Simulation time 109361038 ps
CPU time 0.8 seconds
Started May 09 12:36:35 PM PDT 24
Finished May 09 12:36:42 PM PDT 24
Peak memory 200680 kb
Host smart-a72bbdd2-b2e6-4514-8257-ad76da49d1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691548928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3691548928
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.4139441978
Short name T111
Test name
Test status
Simulation time 1991460136 ps
CPU time 6.67 seconds
Started May 09 12:36:42 PM PDT 24
Finished May 09 12:36:56 PM PDT 24
Peak memory 201012 kb
Host smart-c2878dde-8187-4567-af79-0a077d6a900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139441978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.4139441978
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1006306854
Short name T1
Test name
Test status
Simulation time 108080990 ps
CPU time 0.99 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 200812 kb
Host smart-ad6575f2-c9dc-4de8-bcad-fd1725c381f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006306854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1006306854
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1895947405
Short name T312
Test name
Test status
Simulation time 233493781 ps
CPU time 1.57 seconds
Started May 09 12:36:32 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 201048 kb
Host smart-e8153d77-ad0b-45ef-aa16-53569a4a3eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895947405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1895947405
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2412509439
Short name T530
Test name
Test status
Simulation time 4444447918 ps
CPU time 15.14 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:37:08 PM PDT 24
Peak memory 210884 kb
Host smart-856d4f55-17b2-44c1-9769-b56c9e28696f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412509439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2412509439
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1246475008
Short name T200
Test name
Test status
Simulation time 364358249 ps
CPU time 2.24 seconds
Started May 09 12:36:37 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 200756 kb
Host smart-a6749b7f-6f6a-4932-a7b5-aeff7de56a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246475008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1246475008
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2469058383
Short name T245
Test name
Test status
Simulation time 69860380 ps
CPU time 0.8 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:36:56 PM PDT 24
Peak memory 200860 kb
Host smart-d051dec7-d00c-4b4e-9abc-551489e7d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469058383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2469058383
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3970386931
Short name T257
Test name
Test status
Simulation time 62331193 ps
CPU time 0.73 seconds
Started May 09 12:36:40 PM PDT 24
Finished May 09 12:36:48 PM PDT 24
Peak memory 200700 kb
Host smart-69855d88-51cc-4d31-b461-4b4d88926709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970386931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3970386931
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.172433160
Short name T55
Test name
Test status
Simulation time 1879841387 ps
CPU time 6.81 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:53 PM PDT 24
Peak memory 222000 kb
Host smart-0ad9e2bc-8767-4fff-a4e1-7a414337d90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172433160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.172433160
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3556443182
Short name T212
Test name
Test status
Simulation time 244532377 ps
CPU time 0.99 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 217928 kb
Host smart-5f4ba0a0-f194-4d7d-9922-eb49a98f3afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556443182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3556443182
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1488028266
Short name T479
Test name
Test status
Simulation time 141915574 ps
CPU time 0.83 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:11 PM PDT 24
Peak memory 200676 kb
Host smart-29e214d2-1f49-4e36-b521-18c089706ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488028266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1488028266
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3771930807
Short name T476
Test name
Test status
Simulation time 1076913038 ps
CPU time 5.06 seconds
Started May 09 12:36:57 PM PDT 24
Finished May 09 12:37:12 PM PDT 24
Peak memory 200932 kb
Host smart-34b440bf-0c74-48d4-85e1-f48358613334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771930807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3771930807
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3736207834
Short name T182
Test name
Test status
Simulation time 148077229 ps
CPU time 1.11 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 200868 kb
Host smart-c4b82cff-549c-488d-bf1e-292255246cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736207834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3736207834
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1871068254
Short name T316
Test name
Test status
Simulation time 123999082 ps
CPU time 1.15 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:36:56 PM PDT 24
Peak memory 200984 kb
Host smart-8f68e290-b63b-4526-9285-35d7e0edc752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871068254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1871068254
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2089648580
Short name T502
Test name
Test status
Simulation time 534584832 ps
CPU time 2.38 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:40 PM PDT 24
Peak memory 201340 kb
Host smart-06e2e0a4-7dc1-4bfe-8bcd-84b0b0776abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089648580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2089648580
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.638379798
Short name T192
Test name
Test status
Simulation time 540617117 ps
CPU time 3.07 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:15 PM PDT 24
Peak memory 200872 kb
Host smart-7cdd78e4-4247-46cc-bfb0-bb2159831b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638379798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.638379798
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3132293411
Short name T541
Test name
Test status
Simulation time 198787468 ps
CPU time 1.21 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 200828 kb
Host smart-ad01e9f8-0788-4539-b833-a52f578323ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132293411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3132293411
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1416980859
Short name T166
Test name
Test status
Simulation time 76035101 ps
CPU time 0.78 seconds
Started May 09 12:35:44 PM PDT 24
Finished May 09 12:35:50 PM PDT 24
Peak memory 200604 kb
Host smart-9e2c35d9-c643-41ac-a671-376035e522d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416980859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1416980859
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.502182894
Short name T49
Test name
Test status
Simulation time 1224290616 ps
CPU time 5.29 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 217856 kb
Host smart-c4059114-9fa7-4ac8-814b-45b181708cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502182894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.502182894
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3975131625
Short name T233
Test name
Test status
Simulation time 243949729 ps
CPU time 1.17 seconds
Started May 09 12:35:58 PM PDT 24
Finished May 09 12:36:09 PM PDT 24
Peak memory 218076 kb
Host smart-b2084663-344b-42f5-823c-4e053b1b4f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975131625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3975131625
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.384483549
Short name T17
Test name
Test status
Simulation time 155912752 ps
CPU time 0.86 seconds
Started May 09 12:36:02 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 200520 kb
Host smart-e8fe5374-b6d3-4bdf-91cf-77e38a11ad9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384483549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.384483549
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2770038048
Short name T278
Test name
Test status
Simulation time 2278928439 ps
CPU time 7.97 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 201124 kb
Host smart-e0caff6c-a0a5-473c-8677-f2662e02106d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770038048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2770038048
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4090381443
Short name T74
Test name
Test status
Simulation time 17109135375 ps
CPU time 25.64 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:29 PM PDT 24
Peak memory 218632 kb
Host smart-97f36694-255a-485f-9b58-b039946d7f1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090381443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4090381443
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.807772046
Short name T187
Test name
Test status
Simulation time 145455025 ps
CPU time 1.1 seconds
Started May 09 12:35:50 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 200724 kb
Host smart-16184343-6873-47d3-b30f-785c813defc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807772046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.807772046
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.292023205
Short name T508
Test name
Test status
Simulation time 130618108 ps
CPU time 1.22 seconds
Started May 09 12:35:50 PM PDT 24
Finished May 09 12:35:58 PM PDT 24
Peak memory 200936 kb
Host smart-92f2eaa7-08b1-4576-a9a5-3dc68a3d4e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292023205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.292023205
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1407724879
Short name T314
Test name
Test status
Simulation time 3870148474 ps
CPU time 18.42 seconds
Started May 09 12:35:50 PM PDT 24
Finished May 09 12:36:15 PM PDT 24
Peak memory 217388 kb
Host smart-261c7d8f-7369-46d0-9ba1-7c4ab4388c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407724879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1407724879
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1035526352
Short name T404
Test name
Test status
Simulation time 124538320 ps
CPU time 1.53 seconds
Started May 09 12:35:56 PM PDT 24
Finished May 09 12:36:06 PM PDT 24
Peak memory 208952 kb
Host smart-3cbb4d3a-c35c-4c16-b9e7-6610b6061799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035526352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1035526352
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1132788505
Short name T306
Test name
Test status
Simulation time 134247172 ps
CPU time 1.26 seconds
Started May 09 12:35:56 PM PDT 24
Finished May 09 12:36:05 PM PDT 24
Peak memory 200792 kb
Host smart-576c6baa-9deb-4ecb-9499-aefa30e76a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132788505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1132788505
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2276631407
Short name T235
Test name
Test status
Simulation time 67697041 ps
CPU time 0.75 seconds
Started May 09 12:36:50 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 200680 kb
Host smart-c1185065-085d-429b-a49a-e0b985feaf22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276631407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2276631407
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1413599312
Short name T540
Test name
Test status
Simulation time 1877497518 ps
CPU time 6.81 seconds
Started May 09 12:37:02 PM PDT 24
Finished May 09 12:37:20 PM PDT 24
Peak memory 218368 kb
Host smart-ef64ee22-9bae-4f20-939b-c1ffcee0a9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413599312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1413599312
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3902507986
Short name T447
Test name
Test status
Simulation time 244898563 ps
CPU time 1.06 seconds
Started May 09 12:36:46 PM PDT 24
Finished May 09 12:36:57 PM PDT 24
Peak memory 217892 kb
Host smart-7f47d3f1-09a5-49c3-b6c7-d1268a9e9c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902507986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3902507986
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.477124908
Short name T12
Test name
Test status
Simulation time 133871846 ps
CPU time 0.77 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 200612 kb
Host smart-d75ba691-7494-496d-881f-fb51f28d0388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477124908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.477124908
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1180661014
Short name T295
Test name
Test status
Simulation time 1565671949 ps
CPU time 5.93 seconds
Started May 09 12:36:36 PM PDT 24
Finished May 09 12:36:48 PM PDT 24
Peak memory 200980 kb
Host smart-35ba5ea4-c8d0-494f-868e-24f84d64f6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180661014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1180661014
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2196278540
Short name T222
Test name
Test status
Simulation time 148942885 ps
CPU time 1.14 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 200876 kb
Host smart-e321506f-347d-4d9c-8e2a-ff6925632d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196278540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2196278540
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2327745782
Short name T411
Test name
Test status
Simulation time 250736484 ps
CPU time 1.54 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 201024 kb
Host smart-fddcb12c-609d-4bc1-9e0f-5f73c6bde365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327745782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2327745782
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2677702875
Short name T28
Test name
Test status
Simulation time 218281129 ps
CPU time 1.52 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 200904 kb
Host smart-259bd371-3a50-4df8-b3e6-08545b3cff3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677702875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2677702875
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.272826111
Short name T503
Test name
Test status
Simulation time 404414769 ps
CPU time 2.07 seconds
Started May 09 12:36:42 PM PDT 24
Finished May 09 12:36:52 PM PDT 24
Peak memory 200860 kb
Host smart-225b1753-f5c3-44f0-92dc-8b794bfceb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272826111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.272826111
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.150322353
Short name T209
Test name
Test status
Simulation time 170911157 ps
CPU time 1.31 seconds
Started May 09 12:36:37 PM PDT 24
Finished May 09 12:36:45 PM PDT 24
Peak memory 201076 kb
Host smart-7bf2f0af-0e2a-4476-9aa3-34ee96ecbdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150322353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.150322353
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2446439967
Short name T140
Test name
Test status
Simulation time 63497688 ps
CPU time 0.76 seconds
Started May 09 12:36:40 PM PDT 24
Finished May 09 12:36:48 PM PDT 24
Peak memory 200600 kb
Host smart-4d63d3ed-f836-4b66-96f0-e0a955401d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446439967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2446439967
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1529942924
Short name T514
Test name
Test status
Simulation time 1230626998 ps
CPU time 5.78 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:03 PM PDT 24
Peak memory 218356 kb
Host smart-45b9946c-8e72-4286-a39d-d64af966e242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529942924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1529942924
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.313031293
Short name T270
Test name
Test status
Simulation time 245114658 ps
CPU time 1.03 seconds
Started May 09 12:36:42 PM PDT 24
Finished May 09 12:36:50 PM PDT 24
Peak memory 217828 kb
Host smart-32b95eaa-3580-4c15-aa1b-7293ab332ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313031293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.313031293
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3886006673
Short name T410
Test name
Test status
Simulation time 117198255 ps
CPU time 0.78 seconds
Started May 09 12:37:06 PM PDT 24
Finished May 09 12:37:19 PM PDT 24
Peak memory 200644 kb
Host smart-9ab3a609-5559-4477-af50-5f9519e9641c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886006673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3886006673
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.817450137
Short name T402
Test name
Test status
Simulation time 897463921 ps
CPU time 4.61 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 200948 kb
Host smart-d95121b9-f451-4fb0-97ab-2c52c42955cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817450137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.817450137
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2947525306
Short name T211
Test name
Test status
Simulation time 147232259 ps
CPU time 1.01 seconds
Started May 09 12:36:57 PM PDT 24
Finished May 09 12:37:13 PM PDT 24
Peak memory 200800 kb
Host smart-0360856f-138b-42a5-9ebb-842b520822ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947525306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2947525306
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2828731182
Short name T373
Test name
Test status
Simulation time 115441138 ps
CPU time 1.16 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 201016 kb
Host smart-bc84c9db-b6f4-48da-a28b-cf3e79ace587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828731182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2828731182
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3323981210
Short name T163
Test name
Test status
Simulation time 8948680255 ps
CPU time 33.05 seconds
Started May 09 12:37:03 PM PDT 24
Finished May 09 12:37:48 PM PDT 24
Peak memory 209428 kb
Host smart-c1adfaca-c495-4a95-aae4-9bfd1f1e2120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323981210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3323981210
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2919811754
Short name T25
Test name
Test status
Simulation time 408909123 ps
CPU time 2.1 seconds
Started May 09 12:37:07 PM PDT 24
Finished May 09 12:37:21 PM PDT 24
Peak memory 209096 kb
Host smart-86c3a398-b0fd-4274-b78f-4a1cb8a66b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919811754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2919811754
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.373676141
Short name T86
Test name
Test status
Simulation time 182444129 ps
CPU time 1.23 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 200804 kb
Host smart-3b39f64d-a98a-4ffb-a6da-75decb556407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373676141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.373676141
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3903587846
Short name T469
Test name
Test status
Simulation time 65981431 ps
CPU time 0.75 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 200448 kb
Host smart-5e5c9486-ae1d-453f-84ad-a9be52ef41a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903587846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3903587846
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.235310384
Short name T338
Test name
Test status
Simulation time 1223620867 ps
CPU time 5.62 seconds
Started May 09 12:36:41 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 222552 kb
Host smart-8b622faf-e7a3-4dff-b0b0-80d06655c51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235310384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.235310384
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2696389488
Short name T501
Test name
Test status
Simulation time 245147951 ps
CPU time 1.02 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 217924 kb
Host smart-606e5807-9005-44fd-b863-e73c0286aaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696389488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2696389488
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3805694076
Short name T500
Test name
Test status
Simulation time 110445541 ps
CPU time 0.76 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 200568 kb
Host smart-1f8a23a8-bc18-41aa-b1a4-64e7fba8435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805694076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3805694076
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1587317001
Short name T512
Test name
Test status
Simulation time 969126238 ps
CPU time 4.62 seconds
Started May 09 12:36:53 PM PDT 24
Finished May 09 12:37:09 PM PDT 24
Peak memory 201040 kb
Host smart-2b72f618-4eab-426d-9d76-8cdaa7289c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587317001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1587317001
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1114647014
Short name T533
Test name
Test status
Simulation time 161235539 ps
CPU time 1.13 seconds
Started May 09 12:36:52 PM PDT 24
Finished May 09 12:37:04 PM PDT 24
Peak memory 200892 kb
Host smart-d36befd0-03f9-4f91-831d-125570dbc8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114647014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1114647014
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3177439174
Short name T310
Test name
Test status
Simulation time 111999250 ps
CPU time 1.19 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 201040 kb
Host smart-82b33f9a-77bd-4431-83ef-fbc68edfcf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177439174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3177439174
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4234356753
Short name T340
Test name
Test status
Simulation time 10287730812 ps
CPU time 37.28 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:37:28 PM PDT 24
Peak memory 201432 kb
Host smart-3b68ca8d-2a63-4a61-a041-bba0d9e45859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234356753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4234356753
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.962141408
Short name T526
Test name
Test status
Simulation time 121987590 ps
CPU time 1.62 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 209080 kb
Host smart-05883062-d5c5-425b-becc-4160ea3394e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962141408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.962141408
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1406609958
Short name T63
Test name
Test status
Simulation time 97495203 ps
CPU time 0.9 seconds
Started May 09 12:36:36 PM PDT 24
Finished May 09 12:36:44 PM PDT 24
Peak memory 200852 kb
Host smart-804a4697-5ac7-4247-8cf6-3f00eafaa968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406609958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1406609958
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.4219742423
Short name T452
Test name
Test status
Simulation time 63647327 ps
CPU time 0.81 seconds
Started May 09 12:36:53 PM PDT 24
Finished May 09 12:37:05 PM PDT 24
Peak memory 200560 kb
Host smart-4a8e7234-fbe9-4e01-83be-881eaaf4be0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219742423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.4219742423
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.4230836634
Short name T39
Test name
Test status
Simulation time 1230247713 ps
CPU time 5.54 seconds
Started May 09 12:36:56 PM PDT 24
Finished May 09 12:37:12 PM PDT 24
Peak memory 222488 kb
Host smart-cd0c4cc1-4009-4eab-887f-bd6e0684a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230836634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4230836634
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4175404016
Short name T2
Test name
Test status
Simulation time 243911335 ps
CPU time 1.13 seconds
Started May 09 12:36:31 PM PDT 24
Finished May 09 12:36:39 PM PDT 24
Peak memory 218012 kb
Host smart-0eeaae92-9eaa-40bd-85fe-a822e971ae4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175404016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4175404016
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.4223894182
Short name T346
Test name
Test status
Simulation time 114285662 ps
CPU time 0.8 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 200616 kb
Host smart-445bf70a-156e-4995-87ab-77c3e2c97d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223894182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.4223894182
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1608637808
Short name T260
Test name
Test status
Simulation time 848118983 ps
CPU time 4.07 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:50 PM PDT 24
Peak memory 201044 kb
Host smart-f241f892-0236-412a-b640-124f5160ff4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608637808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1608637808
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3238841518
Short name T261
Test name
Test status
Simulation time 109774946 ps
CPU time 0.95 seconds
Started May 09 12:37:09 PM PDT 24
Finished May 09 12:37:22 PM PDT 24
Peak memory 200872 kb
Host smart-66a1f732-eba8-4270-955f-d7ec8c34f785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238841518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3238841518
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.117879416
Short name T268
Test name
Test status
Simulation time 198524671 ps
CPU time 1.43 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 201020 kb
Host smart-e4a07222-d735-4af6-b963-6070c096062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117879416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.117879416
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2963703393
Short name T328
Test name
Test status
Simulation time 5226363691 ps
CPU time 18.23 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:37:16 PM PDT 24
Peak memory 201172 kb
Host smart-083952db-9661-4584-9346-ba3f85daaba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963703393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2963703393
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3259343432
Short name T357
Test name
Test status
Simulation time 434002199 ps
CPU time 2.3 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 208984 kb
Host smart-a9ece2d9-d472-418d-8ee5-ba411fbb2583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259343432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3259343432
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3001371169
Short name T131
Test name
Test status
Simulation time 107822876 ps
CPU time 0.94 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:46 PM PDT 24
Peak memory 200828 kb
Host smart-811bb062-bf2f-45f5-b80e-09c8bfdc4dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001371169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3001371169
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2622473597
Short name T234
Test name
Test status
Simulation time 71280834 ps
CPU time 0.75 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 200592 kb
Host smart-6b593215-11c9-4b8a-841a-98d762d145f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622473597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2622473597
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.872891639
Short name T475
Test name
Test status
Simulation time 1909579034 ps
CPU time 7.29 seconds
Started May 09 12:36:36 PM PDT 24
Finished May 09 12:36:50 PM PDT 24
Peak memory 218424 kb
Host smart-ed3c2c05-2bba-4649-b05b-fbb8441effce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872891639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.872891639
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1237711562
Short name T449
Test name
Test status
Simulation time 245116030 ps
CPU time 1.04 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 217880 kb
Host smart-81b7b643-478e-4916-968a-bf69c050d123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237711562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1237711562
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3314788168
Short name T440
Test name
Test status
Simulation time 238529763 ps
CPU time 0.94 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:18 PM PDT 24
Peak memory 200636 kb
Host smart-c883768f-f69c-4681-bbc6-ff7ccbc379c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314788168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3314788168
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.578333579
Short name T119
Test name
Test status
Simulation time 1671841885 ps
CPU time 6.06 seconds
Started May 09 12:36:52 PM PDT 24
Finished May 09 12:37:08 PM PDT 24
Peak memory 201048 kb
Host smart-f0c7d8ce-8857-4638-bdcf-39ad36e5b27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578333579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.578333579
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3613511398
Short name T248
Test name
Test status
Simulation time 142574318 ps
CPU time 1.12 seconds
Started May 09 12:36:52 PM PDT 24
Finished May 09 12:37:04 PM PDT 24
Peak memory 200820 kb
Host smart-d38e0c0c-9dbe-4031-9d92-82477478acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613511398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3613511398
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.844603045
Short name T318
Test name
Test status
Simulation time 120699543 ps
CPU time 1.2 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 200924 kb
Host smart-c869ce28-d8d1-4e14-857c-2a6096714788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844603045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.844603045
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1289333844
Short name T450
Test name
Test status
Simulation time 5645703199 ps
CPU time 19.4 seconds
Started May 09 12:36:34 PM PDT 24
Finished May 09 12:37:00 PM PDT 24
Peak memory 201184 kb
Host smart-93128586-bebc-4529-8087-abb4a3b42774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289333844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1289333844
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.153056792
Short name T180
Test name
Test status
Simulation time 71696508 ps
CPU time 0.77 seconds
Started May 09 12:36:57 PM PDT 24
Finished May 09 12:37:08 PM PDT 24
Peak memory 200872 kb
Host smart-b51efb1c-c824-4cc9-acf4-bcbdd486f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153056792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.153056792
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3477363568
Short name T354
Test name
Test status
Simulation time 89998588 ps
CPU time 0.8 seconds
Started May 09 12:36:50 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 200680 kb
Host smart-263354c4-2be4-4ecc-8546-132045d56d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477363568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3477363568
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1512228484
Short name T206
Test name
Test status
Simulation time 2178088990 ps
CPU time 8.02 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:59 PM PDT 24
Peak memory 222624 kb
Host smart-bfcebb10-68b6-43fc-b3bc-d2d44a16a717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512228484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1512228484
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2900101955
Short name T428
Test name
Test status
Simulation time 243863763 ps
CPU time 1.05 seconds
Started May 09 12:36:53 PM PDT 24
Finished May 09 12:37:05 PM PDT 24
Peak memory 217984 kb
Host smart-62aa57a5-e62e-46cd-962a-7c1789e86305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900101955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2900101955
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3235301033
Short name T408
Test name
Test status
Simulation time 84994952 ps
CPU time 0.78 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:18 PM PDT 24
Peak memory 200640 kb
Host smart-33a5a955-7cc7-4efc-9153-0e7bba68027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235301033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3235301033
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1566787659
Short name T195
Test name
Test status
Simulation time 1056203124 ps
CPU time 4.77 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:22 PM PDT 24
Peak memory 201012 kb
Host smart-17acb4bd-9a98-4efe-aeb5-70e97ecc64fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566787659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1566787659
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3267433675
Short name T226
Test name
Test status
Simulation time 186821780 ps
CPU time 1.17 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 200832 kb
Host smart-cac4dd84-4ff0-4662-80fe-dcdc9e210849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267433675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3267433675
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2333065643
Short name T511
Test name
Test status
Simulation time 118287510 ps
CPU time 1.15 seconds
Started May 09 12:37:02 PM PDT 24
Finished May 09 12:37:14 PM PDT 24
Peak memory 201016 kb
Host smart-6c387184-56f9-4fad-8679-deb4b5855d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333065643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2333065643
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2748464550
Short name T341
Test name
Test status
Simulation time 7592499653 ps
CPU time 33.43 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:33 PM PDT 24
Peak memory 209364 kb
Host smart-6512cc2a-ce3d-4891-94a2-a0464a751638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748464550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2748464550
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3857093196
Short name T176
Test name
Test status
Simulation time 148033800 ps
CPU time 1.87 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 200828 kb
Host smart-cb610dd0-b576-40fa-abc6-520945b67713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857093196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3857093196
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3640071136
Short name T273
Test name
Test status
Simulation time 166791550 ps
CPU time 1.14 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 200848 kb
Host smart-af763f23-50d9-45dd-9594-482d698508ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640071136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3640071136
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.972232519
Short name T480
Test name
Test status
Simulation time 88499234 ps
CPU time 0.79 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:19 PM PDT 24
Peak memory 200636 kb
Host smart-86d5c8d4-7f62-44b5-acb8-d59488cfb6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972232519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.972232519
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1946555574
Short name T483
Test name
Test status
Simulation time 2157216133 ps
CPU time 7.55 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 218660 kb
Host smart-9b18547f-fcce-4590-97c2-40db947fa5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946555574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1946555574
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2988110700
Short name T461
Test name
Test status
Simulation time 244857703 ps
CPU time 1.01 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:13 PM PDT 24
Peak memory 217916 kb
Host smart-b6eb7796-ead6-4d06-86b0-628c5fb545da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988110700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2988110700
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3519142168
Short name T405
Test name
Test status
Simulation time 182526969 ps
CPU time 0.96 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 200648 kb
Host smart-069e50a8-13eb-4cc4-9bbd-b9c3f182b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519142168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3519142168
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2791511605
Short name T302
Test name
Test status
Simulation time 1784827852 ps
CPU time 6.51 seconds
Started May 09 12:36:57 PM PDT 24
Finished May 09 12:37:13 PM PDT 24
Peak memory 201020 kb
Host smart-d291d533-0c48-40e7-a5ac-894dc8e9d4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791511605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2791511605
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2920943745
Short name T146
Test name
Test status
Simulation time 113566872 ps
CPU time 1 seconds
Started May 09 12:36:40 PM PDT 24
Finished May 09 12:36:49 PM PDT 24
Peak memory 200872 kb
Host smart-3f5d1d20-aba3-4a37-ba99-b46bb8b94d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920943745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2920943745
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2864866693
Short name T419
Test name
Test status
Simulation time 116194665 ps
CPU time 1.13 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:52 PM PDT 24
Peak memory 200940 kb
Host smart-d615c021-6b20-4478-91e8-93a389f81f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864866693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2864866693
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.4098044613
Short name T227
Test name
Test status
Simulation time 3054675554 ps
CPU time 10.96 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:37:04 PM PDT 24
Peak memory 209372 kb
Host smart-c9d15283-c275-4dd0-a099-a667dc9c8688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098044613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4098044613
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.294124422
Short name T203
Test name
Test status
Simulation time 127742813 ps
CPU time 1.56 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:14 PM PDT 24
Peak memory 208988 kb
Host smart-6c0282a9-08f4-488a-9578-1f61d420534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294124422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.294124422
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1262816497
Short name T172
Test name
Test status
Simulation time 239531465 ps
CPU time 1.49 seconds
Started May 09 12:36:54 PM PDT 24
Finished May 09 12:37:07 PM PDT 24
Peak memory 200984 kb
Host smart-7f093ffa-2728-4cee-99ee-263db35babb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262816497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1262816497
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.873621141
Short name T149
Test name
Test status
Simulation time 98866673 ps
CPU time 0.83 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:37:34 PM PDT 24
Peak memory 200676 kb
Host smart-0686dd96-a823-42bc-b273-1da1e175d349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873621141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.873621141
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3344703712
Short name T532
Test name
Test status
Simulation time 1886679318 ps
CPU time 7.24 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:37:03 PM PDT 24
Peak memory 217388 kb
Host smart-1fad1104-2c6e-41f5-9ee4-b6d11a42b3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344703712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3344703712
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.952376023
Short name T505
Test name
Test status
Simulation time 244983029 ps
CPU time 1.08 seconds
Started May 09 12:36:42 PM PDT 24
Finished May 09 12:36:51 PM PDT 24
Peak memory 217960 kb
Host smart-43c053e6-57ec-4b58-a5a9-5dff419394a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952376023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.952376023
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3431209676
Short name T481
Test name
Test status
Simulation time 199657891 ps
CPU time 0.95 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:36:55 PM PDT 24
Peak memory 200672 kb
Host smart-3e2af067-a15c-4a49-b6c2-7f8017aa2a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431209676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3431209676
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3807733067
Short name T398
Test name
Test status
Simulation time 1665011411 ps
CPU time 6.26 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:57 PM PDT 24
Peak memory 201044 kb
Host smart-90086b8c-1aa5-4027-ba8a-8f52f2db9904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807733067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3807733067
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3079803468
Short name T82
Test name
Test status
Simulation time 175817613 ps
CPU time 1.15 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 200844 kb
Host smart-fec3e8c0-aa12-4057-84c4-95ca9df4dc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079803468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3079803468
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.398440954
Short name T516
Test name
Test status
Simulation time 114699506 ps
CPU time 1.18 seconds
Started May 09 12:36:36 PM PDT 24
Finished May 09 12:36:44 PM PDT 24
Peak memory 201040 kb
Host smart-f1e92c95-f250-4d19-b017-f459b464193c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398440954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.398440954
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2643818675
Short name T329
Test name
Test status
Simulation time 8808652458 ps
CPU time 31.34 seconds
Started May 09 12:36:42 PM PDT 24
Finished May 09 12:37:21 PM PDT 24
Peak memory 209368 kb
Host smart-b289f253-10a1-4ab1-afb6-fc240f5518d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643818675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2643818675
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1486161081
Short name T40
Test name
Test status
Simulation time 146495747 ps
CPU time 1.84 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:19 PM PDT 24
Peak memory 200808 kb
Host smart-8cb1294e-03b7-4d16-b379-1035cc8b2db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486161081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1486161081
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1889784513
Short name T393
Test name
Test status
Simulation time 111817602 ps
CPU time 0.99 seconds
Started May 09 12:36:51 PM PDT 24
Finished May 09 12:37:03 PM PDT 24
Peak memory 200736 kb
Host smart-ffce0f33-04cc-4187-9710-e4bbcfd1b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889784513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1889784513
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3051634603
Short name T46
Test name
Test status
Simulation time 64747497 ps
CPU time 0.74 seconds
Started May 09 12:36:59 PM PDT 24
Finished May 09 12:37:11 PM PDT 24
Peak memory 200672 kb
Host smart-0062a6d3-e945-4efb-9993-6b62fbab872a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051634603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3051634603
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.81051289
Short name T60
Test name
Test status
Simulation time 1226251945 ps
CPU time 5.8 seconds
Started May 09 12:36:51 PM PDT 24
Finished May 09 12:37:07 PM PDT 24
Peak memory 222020 kb
Host smart-51a57862-75ca-4cb9-86f8-1227325d1785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81051289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.81051289
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.280367853
Short name T472
Test name
Test status
Simulation time 244107528 ps
CPU time 1.06 seconds
Started May 09 12:36:54 PM PDT 24
Finished May 09 12:37:06 PM PDT 24
Peak memory 218032 kb
Host smart-1e042e40-6c43-43b3-b3f3-5e97239c71bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280367853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.280367853
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1570030392
Short name T251
Test name
Test status
Simulation time 133696908 ps
CPU time 0.81 seconds
Started May 09 12:36:51 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 200564 kb
Host smart-1bf6b031-be5a-48b2-be12-437bd8122f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570030392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1570030392
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3196797111
Short name T515
Test name
Test status
Simulation time 1497040523 ps
CPU time 5.85 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:52 PM PDT 24
Peak memory 200996 kb
Host smart-31a4fc4e-386c-472f-aed3-bd58816659a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196797111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3196797111
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1573460466
Short name T134
Test name
Test status
Simulation time 172905106 ps
CPU time 1.14 seconds
Started May 09 12:36:36 PM PDT 24
Finished May 09 12:36:43 PM PDT 24
Peak memory 200776 kb
Host smart-fec3731c-60f7-4f8e-b3cc-04b584f76a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573460466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1573460466
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1585014835
Short name T342
Test name
Test status
Simulation time 248025314 ps
CPU time 1.58 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:47 PM PDT 24
Peak memory 201012 kb
Host smart-2b914fbe-1f12-4436-9de5-bbe66246cf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585014835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1585014835
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1751169559
Short name T434
Test name
Test status
Simulation time 3833223062 ps
CPU time 16.91 seconds
Started May 09 12:36:58 PM PDT 24
Finished May 09 12:37:26 PM PDT 24
Peak memory 209392 kb
Host smart-ce67e8e5-ee4e-4023-aea3-58b87a3470bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751169559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1751169559
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3512339994
Short name T459
Test name
Test status
Simulation time 132610453 ps
CPU time 1.61 seconds
Started May 09 12:36:54 PM PDT 24
Finished May 09 12:37:07 PM PDT 24
Peak memory 209072 kb
Host smart-5520f675-178e-4a96-9fd6-718116ca4980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512339994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3512339994
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1836601404
Short name T162
Test name
Test status
Simulation time 140364304 ps
CPU time 1.1 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 200772 kb
Host smart-1958a943-b3fd-4050-8222-62cdf7374b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836601404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1836601404
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3581873643
Short name T218
Test name
Test status
Simulation time 74246117 ps
CPU time 0.77 seconds
Started May 09 12:37:11 PM PDT 24
Finished May 09 12:37:26 PM PDT 24
Peak memory 200636 kb
Host smart-aecd8b49-b814-4bb9-a31d-f6f9a304cc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581873643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3581873643
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2060780440
Short name T35
Test name
Test status
Simulation time 1225044723 ps
CPU time 5.31 seconds
Started May 09 12:36:50 PM PDT 24
Finished May 09 12:37:06 PM PDT 24
Peak memory 222504 kb
Host smart-0ce6eceb-7aa7-4fd4-a6da-d8753ad7154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060780440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2060780440
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3173300057
Short name T403
Test name
Test status
Simulation time 244405019 ps
CPU time 1.05 seconds
Started May 09 12:36:46 PM PDT 24
Finished May 09 12:36:57 PM PDT 24
Peak memory 218000 kb
Host smart-e0361bee-de0f-4af2-8df8-4e7d846acfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173300057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3173300057
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1694968985
Short name T286
Test name
Test status
Simulation time 92999516 ps
CPU time 0.77 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 200680 kb
Host smart-85570c31-51e7-4c44-85e4-78131f715408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694968985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1694968985
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2495703589
Short name T109
Test name
Test status
Simulation time 1940703452 ps
CPU time 7.66 seconds
Started May 09 12:36:38 PM PDT 24
Finished May 09 12:36:52 PM PDT 24
Peak memory 200944 kb
Host smart-d493645e-4729-4e96-b07c-277ee8dd6f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495703589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2495703589
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.4137280710
Short name T339
Test name
Test status
Simulation time 109533186 ps
CPU time 0.93 seconds
Started May 09 12:37:03 PM PDT 24
Finished May 09 12:37:15 PM PDT 24
Peak memory 200872 kb
Host smart-10925b70-8a49-4dea-ad8f-c86beb78d43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137280710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.4137280710
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1609737545
Short name T528
Test name
Test status
Simulation time 122449067 ps
CPU time 1.17 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:13 PM PDT 24
Peak memory 200984 kb
Host smart-734ba906-5747-4af7-9ee6-6e5f398e0f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609737545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1609737545
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1037071349
Short name T485
Test name
Test status
Simulation time 3466773161 ps
CPU time 14.27 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:25 PM PDT 24
Peak memory 210052 kb
Host smart-0d4b0778-0ba3-4525-9dff-01ddb46ea47b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037071349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1037071349
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1179003522
Short name T254
Test name
Test status
Simulation time 486581673 ps
CPU time 2.54 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:00 PM PDT 24
Peak memory 200796 kb
Host smart-d2d285d8-55a8-48e8-897f-ea97b90b5915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179003522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1179003522
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2359869009
Short name T416
Test name
Test status
Simulation time 91995500 ps
CPU time 0.87 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 200876 kb
Host smart-890dd347-0b4e-4a6b-a154-8de9139f44a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359869009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2359869009
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1571520596
Short name T242
Test name
Test status
Simulation time 54077127 ps
CPU time 0.73 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:35:56 PM PDT 24
Peak memory 200948 kb
Host smart-4ab4097c-070a-4b0f-a90c-cea8e04ba2e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571520596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1571520596
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.657821389
Short name T56
Test name
Test status
Simulation time 1905004790 ps
CPU time 7.06 seconds
Started May 09 12:36:00 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 221960 kb
Host smart-8834a828-d6bb-4fba-b5e4-6068c56f8884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657821389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.657821389
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1709879473
Short name T189
Test name
Test status
Simulation time 244247946 ps
CPU time 1.01 seconds
Started May 09 12:35:45 PM PDT 24
Finished May 09 12:35:51 PM PDT 24
Peak memory 217964 kb
Host smart-59acc361-ee44-48b4-bf83-910ca05a132c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709879473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1709879473
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2563802061
Short name T484
Test name
Test status
Simulation time 135910845 ps
CPU time 0.79 seconds
Started May 09 12:35:47 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 200572 kb
Host smart-b5c2aafa-b70c-4246-9129-23170a0193b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563802061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2563802061
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2989793188
Short name T210
Test name
Test status
Simulation time 700496630 ps
CPU time 3.82 seconds
Started May 09 12:35:47 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 200988 kb
Host smart-2f97f0a4-7ac6-4c8f-ad9c-d127a7b3ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989793188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2989793188
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3436838710
Short name T522
Test name
Test status
Simulation time 104370780 ps
CPU time 0.98 seconds
Started May 09 12:36:10 PM PDT 24
Finished May 09 12:36:18 PM PDT 24
Peak memory 200816 kb
Host smart-1b86093a-b065-4fff-9f0f-4d44c28c74a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436838710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3436838710
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1254915305
Short name T525
Test name
Test status
Simulation time 113150791 ps
CPU time 1.18 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:05 PM PDT 24
Peak memory 200936 kb
Host smart-d6e2482f-5c0d-4504-adf9-2e66b1b1a76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254915305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1254915305
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3366878424
Short name T534
Test name
Test status
Simulation time 3973737798 ps
CPU time 17.24 seconds
Started May 09 12:35:39 PM PDT 24
Finished May 09 12:36:02 PM PDT 24
Peak memory 201092 kb
Host smart-3cf99c88-6264-4172-9abe-e5afd557239c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366878424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3366878424
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2857142768
Short name T225
Test name
Test status
Simulation time 155451906 ps
CPU time 1.95 seconds
Started May 09 12:35:35 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 200756 kb
Host smart-4c8d8b39-00c2-4c44-913f-5510d8d6bff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857142768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2857142768
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3756158577
Short name T289
Test name
Test status
Simulation time 180906430 ps
CPU time 1.15 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:07 PM PDT 24
Peak memory 200764 kb
Host smart-fc37c434-8144-404b-930a-262aeb4bfd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756158577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3756158577
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3986763277
Short name T219
Test name
Test status
Simulation time 73983659 ps
CPU time 0.82 seconds
Started May 09 12:35:47 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 200680 kb
Host smart-1e65c0ae-54c4-48c5-b22e-4d5f9707913b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986763277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3986763277
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1404804745
Short name T52
Test name
Test status
Simulation time 1233200420 ps
CPU time 5.71 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:36:01 PM PDT 24
Peak memory 222256 kb
Host smart-adfd27ef-e2c8-467c-bec9-e79da9168418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404804745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1404804745
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3572673983
Short name T269
Test name
Test status
Simulation time 244693759 ps
CPU time 1.1 seconds
Started May 09 12:35:47 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 218076 kb
Host smart-a5243f8d-35ab-45b2-ac9e-3c8b95182807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572673983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3572673983
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2019065272
Short name T21
Test name
Test status
Simulation time 80813295 ps
CPU time 0.75 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:55 PM PDT 24
Peak memory 200564 kb
Host smart-7fc8930f-96ef-421a-838a-071850736086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019065272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2019065272
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2844960217
Short name T520
Test name
Test status
Simulation time 926159164 ps
CPU time 4.57 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:58 PM PDT 24
Peak memory 200992 kb
Host smart-91510a0c-d632-44ed-abb3-ccdaed8daaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844960217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2844960217
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.661715239
Short name T536
Test name
Test status
Simulation time 105080108 ps
CPU time 0.97 seconds
Started May 09 12:36:05 PM PDT 24
Finished May 09 12:36:14 PM PDT 24
Peak memory 200764 kb
Host smart-5ca3dc02-3254-4f3c-b1d9-634f3833a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661715239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.661715239
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1504598439
Short name T443
Test name
Test status
Simulation time 206333814 ps
CPU time 1.34 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:55 PM PDT 24
Peak memory 200916 kb
Host smart-561a0f7a-02a4-4bd8-8483-10466c5b54f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504598439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1504598439
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2758757373
Short name T41
Test name
Test status
Simulation time 2994437410 ps
CPU time 12.02 seconds
Started May 09 12:35:51 PM PDT 24
Finished May 09 12:36:10 PM PDT 24
Peak memory 201188 kb
Host smart-43416097-afd6-449a-8fe7-abc7e9821bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758757373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2758757373
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4129155369
Short name T326
Test name
Test status
Simulation time 301825766 ps
CPU time 2.07 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:55 PM PDT 24
Peak memory 208960 kb
Host smart-ef14b556-da75-450b-93f4-3baa08ed5c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129155369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4129155369
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2896146706
Short name T477
Test name
Test status
Simulation time 130323247 ps
CPU time 0.99 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:05 PM PDT 24
Peak memory 200696 kb
Host smart-1b12a5f5-34a1-4883-b2f7-7a48dd036b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896146706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2896146706
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3502433576
Short name T335
Test name
Test status
Simulation time 68696308 ps
CPU time 0.75 seconds
Started May 09 12:36:09 PM PDT 24
Finished May 09 12:36:18 PM PDT 24
Peak memory 200652 kb
Host smart-2805737a-2e95-42c0-8e31-707a332c060a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502433576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3502433576
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.650033043
Short name T164
Test name
Test status
Simulation time 245207260 ps
CPU time 1.05 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 217904 kb
Host smart-751eed64-02ed-42ce-a0ea-0dd0489630e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650033043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.650033043
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3227665328
Short name T482
Test name
Test status
Simulation time 187401846 ps
CPU time 0.87 seconds
Started May 09 12:36:05 PM PDT 24
Finished May 09 12:36:19 PM PDT 24
Peak memory 200676 kb
Host smart-ee639ac4-762d-4eed-8601-e174f6b36943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227665328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3227665328
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3525647821
Short name T299
Test name
Test status
Simulation time 1715093717 ps
CPU time 6.47 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 200972 kb
Host smart-bde58164-b2b6-4342-88da-40220c12bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525647821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3525647821
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4119812268
Short name T78
Test name
Test status
Simulation time 152905445 ps
CPU time 1.12 seconds
Started May 09 12:36:08 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 200780 kb
Host smart-319ca314-3ea7-40b9-b9c8-226eee35c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119812268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4119812268
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3085126037
Short name T178
Test name
Test status
Simulation time 251290400 ps
CPU time 1.5 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:05 PM PDT 24
Peak memory 201040 kb
Host smart-8d7caa0d-8ee0-4322-9e89-ce3b547e4261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085126037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3085126037
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.337977588
Short name T213
Test name
Test status
Simulation time 376988177 ps
CPU time 2 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:08 PM PDT 24
Peak memory 200776 kb
Host smart-343464c8-f7a2-4cf1-b61a-3162bc6625c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337977588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.337977588
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.202953685
Short name T147
Test name
Test status
Simulation time 79980706 ps
CPU time 0.82 seconds
Started May 09 12:35:56 PM PDT 24
Finished May 09 12:36:05 PM PDT 24
Peak memory 200672 kb
Host smart-bac79513-7664-48b1-a7f1-aff2cd16728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202953685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.202953685
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.4158047199
Short name T529
Test name
Test status
Simulation time 63574275 ps
CPU time 0.79 seconds
Started May 09 12:36:04 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 200708 kb
Host smart-e3a9dbc0-8418-4394-b8c0-7d4f5abffe96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158047199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.4158047199
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2587830241
Short name T488
Test name
Test status
Simulation time 1228828670 ps
CPU time 5.17 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 222544 kb
Host smart-c066ae65-40c6-4cca-8351-c01bb45e97a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587830241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2587830241
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.4186777211
Short name T263
Test name
Test status
Simulation time 244159631 ps
CPU time 1.13 seconds
Started May 09 12:36:01 PM PDT 24
Finished May 09 12:36:11 PM PDT 24
Peak memory 217996 kb
Host smart-bacaad96-a6b5-4b3a-82e5-80b82417e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186777211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.4186777211
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2436251268
Short name T276
Test name
Test status
Simulation time 93273418 ps
CPU time 0.76 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:35:56 PM PDT 24
Peak memory 200640 kb
Host smart-d028e263-454b-4035-bb7f-12da0acbcb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436251268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2436251268
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1078041084
Short name T291
Test name
Test status
Simulation time 689620039 ps
CPU time 3.63 seconds
Started May 09 12:36:13 PM PDT 24
Finished May 09 12:36:25 PM PDT 24
Peak memory 201044 kb
Host smart-5d965d7c-e52a-4166-8323-68f486f623dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078041084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1078041084
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1086865452
Short name T303
Test name
Test status
Simulation time 97651451 ps
CPU time 1.02 seconds
Started May 09 12:35:54 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 200792 kb
Host smart-a2203790-d7d1-437f-ba4b-1065e1adc8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086865452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1086865452
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1114450553
Short name T426
Test name
Test status
Simulation time 111536608 ps
CPU time 1.24 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 200872 kb
Host smart-92248102-cb5b-402c-97e1-ca9e240a7363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114450553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1114450553
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2903518622
Short name T223
Test name
Test status
Simulation time 5369605719 ps
CPU time 22.6 seconds
Started May 09 12:36:02 PM PDT 24
Finished May 09 12:36:34 PM PDT 24
Peak memory 209308 kb
Host smart-e57e4e04-9300-4851-a600-3bad062fd531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903518622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2903518622
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.235363766
Short name T535
Test name
Test status
Simulation time 371448063 ps
CPU time 2.36 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:06 PM PDT 24
Peak memory 200784 kb
Host smart-7ed65a90-7637-4338-8a69-1216e56fb0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235363766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.235363766
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3237248848
Short name T183
Test name
Test status
Simulation time 206486422 ps
CPU time 1.17 seconds
Started May 09 12:36:02 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 200700 kb
Host smart-d4750e31-74a7-4641-b29f-f54254066b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237248848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3237248848
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3017854037
Short name T521
Test name
Test status
Simulation time 72072576 ps
CPU time 0.81 seconds
Started May 09 12:35:58 PM PDT 24
Finished May 09 12:36:08 PM PDT 24
Peak memory 200696 kb
Host smart-5eab61a4-cdef-499a-a170-519290a3db44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017854037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3017854037
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4106893948
Short name T466
Test name
Test status
Simulation time 1902756487 ps
CPU time 8.06 seconds
Started May 09 12:36:14 PM PDT 24
Finished May 09 12:36:31 PM PDT 24
Peak memory 217948 kb
Host smart-b3e62d56-7e9d-47f7-8528-0487213dfaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106893948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4106893948
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3648772431
Short name T138
Test name
Test status
Simulation time 244161175 ps
CPU time 1.05 seconds
Started May 09 12:36:10 PM PDT 24
Finished May 09 12:36:19 PM PDT 24
Peak memory 218036 kb
Host smart-9bf86297-0ff5-47f2-88bc-54eb4205d7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648772431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3648772431
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1977331442
Short name T15
Test name
Test status
Simulation time 121982452 ps
CPU time 0.82 seconds
Started May 09 12:36:11 PM PDT 24
Finished May 09 12:36:22 PM PDT 24
Peak memory 200628 kb
Host smart-2b6978d1-c864-4c39-ae7d-029ea08a1648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977331442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1977331442
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3154945202
Short name T478
Test name
Test status
Simulation time 1002668244 ps
CPU time 4.58 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:16 PM PDT 24
Peak memory 199536 kb
Host smart-9e96520a-9689-41d9-98ae-4471f70a4625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154945202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3154945202
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.805006937
Short name T130
Test name
Test status
Simulation time 104534813 ps
CPU time 0.95 seconds
Started May 09 12:35:55 PM PDT 24
Finished May 09 12:36:04 PM PDT 24
Peak memory 200828 kb
Host smart-2287177f-a1e4-4e32-8913-86e7b26705ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805006937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.805006937
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1289082567
Short name T294
Test name
Test status
Simulation time 260909877 ps
CPU time 1.5 seconds
Started May 09 12:36:01 PM PDT 24
Finished May 09 12:36:11 PM PDT 24
Peak memory 200852 kb
Host smart-f85bb441-9314-41e3-bd90-e3f34074761d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289082567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1289082567
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2552507434
Short name T271
Test name
Test status
Simulation time 11470830246 ps
CPU time 44.46 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:57 PM PDT 24
Peak memory 209096 kb
Host smart-158e213b-3536-44b3-b39a-6027a25fc0d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552507434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2552507434
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3504619333
Short name T27
Test name
Test status
Simulation time 502289333 ps
CPU time 2.68 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:02 PM PDT 24
Peak memory 200820 kb
Host smart-9cddf051-f8af-4438-be52-baede1d233f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504619333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3504619333
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1019215294
Short name T441
Test name
Test status
Simulation time 120689282 ps
CPU time 1.02 seconds
Started May 09 12:36:05 PM PDT 24
Finished May 09 12:36:14 PM PDT 24
Peak memory 200860 kb
Host smart-d6ad01bf-4144-457b-bd6f-cde14fb7ce5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019215294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1019215294
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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