Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8706

1

T1

178

T6

9

T11

21

auto[1]

11244

1

T1

167

T3

4

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6122	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6817	1			T1	119		T2	1		T3	2
reset_info_cp[2]	3045	1			T1	53		T3	1		T4	1
reset_info_cp[4]	4054	1			T1	80		T3	1		T4	1
reset_info_cp[8]	107	1			T1	3		T11	1		T13	1
reset_info_cp[16]	105	1			T1	1		T11	1		T28	1
reset_info_cp[32]	107	1			T1	3		T13	1		T14	2
reset_info_cp[64]	105	1			T13	1		T14	1		T28	1
reset_info_cp[128]	108	1			T1	3		T40	1		T97	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3358	1			T1	61		T11	21		T13	18
reset_info_cp[1]	auto[1]	2839	1			T1	57		T3	1		T4	1
reset_info_cp[2]	auto[0]	982	1			T1	18		T14	17		T28	21
reset_info_cp[2]	auto[1]	2063	1			T1	35		T3	1		T4	1
reset_info_cp[4]	auto[0]	1514	1			T1	41		T14	30		T28	37
reset_info_cp[4]	auto[1]	2540	1			T1	39		T3	1		T4	1
reset_info_cp[8]	auto[0]	43	1			T1	1		T28	1		T79	2
reset_info_cp[8]	auto[1]	64	1			T1	2		T11	1		T13	1
reset_info_cp[16]	auto[0]	39	1			T78	1		T92	1		T130	2
reset_info_cp[16]	auto[1]	66	1			T1	1		T11	1		T28	1
reset_info_cp[32]	auto[0]	46	1			T1	2		T15	2		T98	1
reset_info_cp[32]	auto[1]	61	1			T1	1		T13	1		T14	2
reset_info_cp[64]	auto[0]	40	1			T28	1		T98	1		T90	1
reset_info_cp[64]	auto[1]	65	1			T13	1		T14	1		T79	2
reset_info_cp[128]	auto[0]	39	1			T1	1		T98	2		T51	1
reset_info_cp[128]	auto[1]	69	1			T1	2		T40	1		T97	1