Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/15.rstmgr_sw_rst.2519841673 May 12 03:02:14 PM PDT 24 May 12 03:02:16 PM PDT 24 132569718 ps
T539 /workspace/coverage/default/16.rstmgr_alert_test.1554567861 May 12 03:02:23 PM PDT 24 May 12 03:02:25 PM PDT 24 89943859 ps
T540 /workspace/coverage/default/33.rstmgr_alert_test.6576044 May 12 03:03:17 PM PDT 24 May 12 03:03:18 PM PDT 24 63573973 ps
T541 /workspace/coverage/default/7.rstmgr_alert_test.3169981394 May 12 03:01:40 PM PDT 24 May 12 03:01:41 PM PDT 24 96692093 ps
T542 /workspace/coverage/default/39.rstmgr_stress_all.1947402954 May 12 03:03:33 PM PDT 24 May 12 03:03:53 PM PDT 24 3904102562 ps
T60 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.975469445 May 12 03:05:02 PM PDT 24 May 12 03:05:04 PM PDT 24 117787281 ps
T61 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4135434651 May 12 03:05:04 PM PDT 24 May 12 03:05:08 PM PDT 24 933538203 ps
T62 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.661252852 May 12 03:05:07 PM PDT 24 May 12 03:05:10 PM PDT 24 496994516 ps
T63 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.287540992 May 12 03:04:46 PM PDT 24 May 12 03:04:50 PM PDT 24 465991484 ps
T64 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3614466950 May 12 03:04:47 PM PDT 24 May 12 03:04:50 PM PDT 24 122707101 ps
T106 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1905353700 May 12 03:05:03 PM PDT 24 May 12 03:05:05 PM PDT 24 79233849 ps
T107 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1687898794 May 12 03:04:54 PM PDT 24 May 12 03:04:56 PM PDT 24 185157122 ps
T81 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2242267019 May 12 03:04:46 PM PDT 24 May 12 03:04:49 PM PDT 24 191905353 ps
T108 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4047426609 May 12 03:05:03 PM PDT 24 May 12 03:05:05 PM PDT 24 62782674 ps
T87 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1013427487 May 12 03:04:52 PM PDT 24 May 12 03:04:54 PM PDT 24 467942514 ps
T543 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2402451834 May 12 03:05:01 PM PDT 24 May 12 03:05:03 PM PDT 24 72404815 ps
T109 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4057745124 May 12 03:05:08 PM PDT 24 May 12 03:05:10 PM PDT 24 125118426 ps
T110 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1197300461 May 12 03:05:01 PM PDT 24 May 12 03:05:03 PM PDT 24 142874865 ps
T111 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2851083565 May 12 03:05:09 PM PDT 24 May 12 03:05:11 PM PDT 24 221619492 ps
T82 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4047310778 May 12 03:04:49 PM PDT 24 May 12 03:04:52 PM PDT 24 189659536 ps
T83 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3520765579 May 12 03:05:09 PM PDT 24 May 12 03:05:13 PM PDT 24 933624225 ps
T112 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.74547278 May 12 03:05:02 PM PDT 24 May 12 03:05:05 PM PDT 24 140908261 ps
T88 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3740319155 May 12 03:05:10 PM PDT 24 May 12 03:05:13 PM PDT 24 430901048 ps
T84 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.132183631 May 12 03:05:02 PM PDT 24 May 12 03:05:05 PM PDT 24 200158595 ps
T113 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1731445171 May 12 03:04:53 PM PDT 24 May 12 03:04:55 PM PDT 24 83648118 ps
T85 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2754510250 May 12 03:05:10 PM PDT 24 May 12 03:05:14 PM PDT 24 439790863 ps
T114 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.466324407 May 12 03:05:02 PM PDT 24 May 12 03:05:04 PM PDT 24 65119241 ps
T86 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4276282707 May 12 03:04:51 PM PDT 24 May 12 03:04:53 PM PDT 24 268201840 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3942588298 May 12 03:04:47 PM PDT 24 May 12 03:04:54 PM PDT 24 483075183 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2250293625 May 12 03:04:53 PM PDT 24 May 12 03:05:03 PM PDT 24 2318628206 ps
T127 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.441283930 May 12 03:05:03 PM PDT 24 May 12 03:05:07 PM PDT 24 680202027 ps
T546 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.290936900 May 12 03:04:56 PM PDT 24 May 12 03:04:57 PM PDT 24 76036433 ps
T547 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4104889706 May 12 03:05:06 PM PDT 24 May 12 03:05:08 PM PDT 24 89694806 ps
T115 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2622687656 May 12 03:05:09 PM PDT 24 May 12 03:05:11 PM PDT 24 75037764 ps
T122 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2260511830 May 12 03:04:53 PM PDT 24 May 12 03:04:56 PM PDT 24 477081510 ps
T128 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2032631783 May 12 03:04:45 PM PDT 24 May 12 03:04:48 PM PDT 24 491707380 ps
T89 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1884891995 May 12 03:05:00 PM PDT 24 May 12 03:05:01 PM PDT 24 138522533 ps
T548 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.311736974 May 12 03:05:07 PM PDT 24 May 12 03:05:09 PM PDT 24 115950250 ps
T124 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1293521206 May 12 03:04:54 PM PDT 24 May 12 03:04:57 PM PDT 24 160542044 ps
T549 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2591020716 May 12 03:05:05 PM PDT 24 May 12 03:05:07 PM PDT 24 148779520 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2191188132 May 12 03:04:47 PM PDT 24 May 12 03:04:49 PM PDT 24 94650113 ps
T551 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.989574331 May 12 03:04:59 PM PDT 24 May 12 03:05:02 PM PDT 24 210664951 ps
T552 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.348418837 May 12 03:04:59 PM PDT 24 May 12 03:05:01 PM PDT 24 120749632 ps
T553 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2640719026 May 12 03:04:44 PM PDT 24 May 12 03:04:45 PM PDT 24 88454576 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2032306814 May 12 03:04:47 PM PDT 24 May 12 03:04:50 PM PDT 24 270240397 ps
T555 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4059464617 May 12 03:04:58 PM PDT 24 May 12 03:05:01 PM PDT 24 187329384 ps
T556 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3224451260 May 12 03:05:07 PM PDT 24 May 12 03:05:09 PM PDT 24 157112570 ps
T116 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1516218231 May 12 03:04:57 PM PDT 24 May 12 03:05:01 PM PDT 24 925251207 ps
T557 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1499791240 May 12 03:05:07 PM PDT 24 May 12 03:05:08 PM PDT 24 64410637 ps
T558 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.985273780 May 12 03:04:57 PM PDT 24 May 12 03:04:58 PM PDT 24 124317241 ps
T94 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.382666619 May 12 03:04:52 PM PDT 24 May 12 03:04:54 PM PDT 24 60281313 ps
T559 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2338019649 May 12 03:04:48 PM PDT 24 May 12 03:04:50 PM PDT 24 86076573 ps
T560 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2927631276 May 12 03:04:47 PM PDT 24 May 12 03:04:50 PM PDT 24 102031347 ps
T117 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1831148688 May 12 03:04:56 PM PDT 24 May 12 03:04:59 PM PDT 24 768870499 ps
T561 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.933373065 May 12 03:04:55 PM PDT 24 May 12 03:04:56 PM PDT 24 129196518 ps
T562 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3134869374 May 12 03:04:47 PM PDT 24 May 12 03:04:49 PM PDT 24 57619633 ps
T563 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2165420361 May 12 03:04:44 PM PDT 24 May 12 03:04:47 PM PDT 24 317665951 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.104837517 May 12 03:04:49 PM PDT 24 May 12 03:04:51 PM PDT 24 99158124 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2333381999 May 12 03:04:50 PM PDT 24 May 12 03:04:51 PM PDT 24 98284633 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1704744842 May 12 03:04:47 PM PDT 24 May 12 03:04:50 PM PDT 24 418831353 ps
T567 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4152146356 May 12 03:04:59 PM PDT 24 May 12 03:05:03 PM PDT 24 170998185 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2992853348 May 12 03:04:53 PM PDT 24 May 12 03:04:59 PM PDT 24 477666870 ps
T129 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2018321171 May 12 03:05:09 PM PDT 24 May 12 03:05:13 PM PDT 24 887780418 ps
T569 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4231153600 May 12 03:04:50 PM PDT 24 May 12 03:04:52 PM PDT 24 206691166 ps
T570 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1756080547 May 12 03:04:54 PM PDT 24 May 12 03:04:56 PM PDT 24 70817037 ps
T571 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1650582940 May 12 03:05:03 PM PDT 24 May 12 03:05:05 PM PDT 24 78031510 ps
T572 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.713346258 May 12 03:04:52 PM PDT 24 May 12 03:04:54 PM PDT 24 111364845 ps
T573 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2312424444 May 12 03:05:02 PM PDT 24 May 12 03:05:05 PM PDT 24 232832229 ps
T574 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1966024359 May 12 03:04:57 PM PDT 24 May 12 03:05:00 PM PDT 24 464123516 ps
T575 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1425009278 May 12 03:05:06 PM PDT 24 May 12 03:05:08 PM PDT 24 107189791 ps
T576 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.362992655 May 12 03:04:57 PM PDT 24 May 12 03:04:58 PM PDT 24 81735334 ps
T577 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.186033597 May 12 03:05:06 PM PDT 24 May 12 03:05:10 PM PDT 24 217233851 ps
T119 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2118949841 May 12 03:04:48 PM PDT 24 May 12 03:04:51 PM PDT 24 419362715 ps
T578 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1300284654 May 12 03:04:56 PM PDT 24 May 12 03:04:59 PM PDT 24 270579058 ps
T579 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1676644371 May 12 03:05:08 PM PDT 24 May 12 03:05:10 PM PDT 24 140861637 ps
T580 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1242324525 May 12 03:04:51 PM PDT 24 May 12 03:04:57 PM PDT 24 1183116222 ps
T581 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2496876983 May 12 03:05:08 PM PDT 24 May 12 03:05:10 PM PDT 24 75490355 ps
T582 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1811712201 May 12 03:04:56 PM PDT 24 May 12 03:05:00 PM PDT 24 491497622 ps
T583 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1544965113 May 12 03:05:08 PM PDT 24 May 12 03:05:11 PM PDT 24 138314987 ps
T584 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.54213240 May 12 03:05:02 PM PDT 24 May 12 03:05:05 PM PDT 24 143277787 ps
T121 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3960588332 May 12 03:05:04 PM PDT 24 May 12 03:05:08 PM PDT 24 932625579 ps
T585 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2731441315 May 12 03:04:51 PM PDT 24 May 12 03:04:53 PM PDT 24 226239401 ps
T586 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.425339672 May 12 03:04:59 PM PDT 24 May 12 03:05:01 PM PDT 24 145605846 ps
T123 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1893878280 May 12 03:05:01 PM PDT 24 May 12 03:05:06 PM PDT 24 930156128 ps
T587 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.655218272 May 12 03:05:09 PM PDT 24 May 12 03:05:13 PM PDT 24 410626701 ps
T588 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1798751636 May 12 03:04:54 PM PDT 24 May 12 03:04:56 PM PDT 24 100782515 ps
T589 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2619518726 May 12 03:05:03 PM PDT 24 May 12 03:05:05 PM PDT 24 180950654 ps
T590 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3144687493 May 12 03:05:02 PM PDT 24 May 12 03:05:05 PM PDT 24 144567567 ps
T118 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.320096305 May 12 03:04:59 PM PDT 24 May 12 03:05:03 PM PDT 24 796531470 ps
T591 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2481208255 May 12 03:05:03 PM PDT 24 May 12 03:05:05 PM PDT 24 184953399 ps
T592 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.349273347 May 12 03:05:00 PM PDT 24 May 12 03:05:01 PM PDT 24 79651365 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1084748383 May 12 03:04:46 PM PDT 24 May 12 03:04:48 PM PDT 24 107206664 ps
T120 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.6493954 May 12 03:05:05 PM PDT 24 May 12 03:05:09 PM PDT 24 773571426 ps
T594 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2212949842 May 12 03:05:04 PM PDT 24 May 12 03:05:07 PM PDT 24 209958070 ps
T595 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3780539847 May 12 03:04:53 PM PDT 24 May 12 03:04:55 PM PDT 24 129532631 ps
T596 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3615884689 May 12 03:04:50 PM PDT 24 May 12 03:04:51 PM PDT 24 93069050 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2712003969 May 12 03:04:49 PM PDT 24 May 12 03:04:51 PM PDT 24 156201370 ps
T598 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1929526791 May 12 03:05:10 PM PDT 24 May 12 03:05:12 PM PDT 24 193455176 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.949933022 May 12 03:04:45 PM PDT 24 May 12 03:04:46 PM PDT 24 136655004 ps
T600 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.866209655 May 12 03:04:46 PM PDT 24 May 12 03:04:48 PM PDT 24 89482528 ps
T601 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2339605210 May 12 03:04:51 PM PDT 24 May 12 03:04:53 PM PDT 24 111747591 ps
T602 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2352963849 May 12 03:04:54 PM PDT 24 May 12 03:04:56 PM PDT 24 96074173 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3821513417 May 12 03:04:54 PM PDT 24 May 12 03:04:56 PM PDT 24 415035972 ps
T604 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3229874863 May 12 03:05:07 PM PDT 24 May 12 03:05:10 PM PDT 24 335876496 ps
T605 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3433308219 May 12 03:05:04 PM PDT 24 May 12 03:05:06 PM PDT 24 62110455 ps
T606 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.939715461 May 12 03:04:54 PM PDT 24 May 12 03:04:59 PM PDT 24 509904873 ps
T607 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2343773737 May 12 03:05:05 PM PDT 24 May 12 03:05:07 PM PDT 24 89771609 ps
T608 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3098207774 May 12 03:05:08 PM PDT 24 May 12 03:05:10 PM PDT 24 88899575 ps
T609 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2572222780 May 12 03:04:58 PM PDT 24 May 12 03:05:02 PM PDT 24 168864768 ps
T610 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2303960291 May 12 03:04:47 PM PDT 24 May 12 03:04:50 PM PDT 24 205283178 ps
T611 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.801110805 May 12 03:05:11 PM PDT 24 May 12 03:05:12 PM PDT 24 102528162 ps
T612 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1509552345 May 12 03:05:00 PM PDT 24 May 12 03:05:03 PM PDT 24 157361118 ps
T613 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3266678833 May 12 03:05:02 PM PDT 24 May 12 03:05:05 PM PDT 24 635583195 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.404559235 May 12 03:04:47 PM PDT 24 May 12 03:04:49 PM PDT 24 57188932 ps
T615 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2126696073 May 12 03:04:58 PM PDT 24 May 12 03:05:00 PM PDT 24 234150368 ps
T616 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1392985756 May 12 03:04:47 PM PDT 24 May 12 03:04:49 PM PDT 24 187655600 ps
T617 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.81597061 May 12 03:04:59 PM PDT 24 May 12 03:05:01 PM PDT 24 233197041 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3170738474 May 12 03:04:53 PM PDT 24 May 12 03:04:56 PM PDT 24 154318959 ps
T619 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.445855409 May 12 03:04:56 PM PDT 24 May 12 03:04:58 PM PDT 24 79072267 ps
T620 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3581285726 May 12 03:04:59 PM PDT 24 May 12 03:05:01 PM PDT 24 63162419 ps

Test location /workspace/coverage/default/43.rstmgr_stress_all.2319091281
Short name T1
Test name
Test status
Simulation time 9979443477 ps
CPU time 40.82 seconds
Started May 12 03:03:45 PM PDT 24
Finished May 12 03:04:27 PM PDT 24
Peak memory 217472 kb
Host smart-dccf2016-bdfd-4a77-b24a-9e80c8686b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319091281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2319091281
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.914975680
Short name T8
Test name
Test status
Simulation time 469739403 ps
CPU time 2.45 seconds
Started May 12 03:03:25 PM PDT 24
Finished May 12 03:03:28 PM PDT 24
Peak memory 200864 kb
Host smart-11587d94-91a3-49e4-b38a-1ef7432b0f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914975680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.914975680
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4135434651
Short name T61
Test name
Test status
Simulation time 933538203 ps
CPU time 3.37 seconds
Started May 12 03:05:04 PM PDT 24
Finished May 12 03:05:08 PM PDT 24
Peak memory 200532 kb
Host smart-9d2858dc-cad2-4ec5-8a58-f5ec68946222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135434651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.4135434651
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.989019211
Short name T69
Test name
Test status
Simulation time 28824681715 ps
CPU time 46.8 seconds
Started May 12 03:00:50 PM PDT 24
Finished May 12 03:01:37 PM PDT 24
Peak memory 217616 kb
Host smart-dbd9d2ab-9396-43c1-9119-6b2c1a777480
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989019211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.989019211
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3380710169
Short name T13
Test name
Test status
Simulation time 2368092328 ps
CPU time 7.97 seconds
Started May 12 03:01:32 PM PDT 24
Finished May 12 03:01:41 PM PDT 24
Peak memory 217928 kb
Host smart-1942756f-fe47-44c2-ac80-f26a897c202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380710169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3380710169
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2242267019
Short name T81
Test name
Test status
Simulation time 191905353 ps
CPU time 3.11 seconds
Started May 12 03:04:46 PM PDT 24
Finished May 12 03:04:49 PM PDT 24
Peak memory 208808 kb
Host smart-e7174110-db77-46c1-8489-bd433e8d60ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242267019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2242267019
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2464947966
Short name T99
Test name
Test status
Simulation time 75704058 ps
CPU time 0.8 seconds
Started May 12 03:02:01 PM PDT 24
Finished May 12 03:02:02 PM PDT 24
Peak memory 200716 kb
Host smart-c37f8012-0829-4c3a-961c-55985d4312db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464947966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2464947966
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2253716624
Short name T92
Test name
Test status
Simulation time 11644531361 ps
CPU time 42.43 seconds
Started May 12 03:02:37 PM PDT 24
Finished May 12 03:03:20 PM PDT 24
Peak memory 201188 kb
Host smart-99f59792-4013-4079-a9ae-18e9510bba14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253716624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2253716624
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1812670976
Short name T151
Test name
Test status
Simulation time 154235325 ps
CPU time 1.12 seconds
Started May 12 03:02:25 PM PDT 24
Finished May 12 03:02:27 PM PDT 24
Peak memory 200812 kb
Host smart-efb06bad-a6d9-412c-9922-f7daf2794c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812670976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1812670976
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3791707571
Short name T43
Test name
Test status
Simulation time 1227083373 ps
CPU time 5.7 seconds
Started May 12 03:01:30 PM PDT 24
Finished May 12 03:01:36 PM PDT 24
Peak memory 222580 kb
Host smart-ef3ff779-b0ba-410b-85e5-cb5b19a1bc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791707571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3791707571
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2018321171
Short name T129
Test name
Test status
Simulation time 887780418 ps
CPU time 3.32 seconds
Started May 12 03:05:09 PM PDT 24
Finished May 12 03:05:13 PM PDT 24
Peak memory 200600 kb
Host smart-a48d70b7-46d1-45af-afa4-0b16b8b1ff06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018321171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2018321171
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4152146356
Short name T567
Test name
Test status
Simulation time 170998185 ps
CPU time 2.58 seconds
Started May 12 03:04:59 PM PDT 24
Finished May 12 03:05:03 PM PDT 24
Peak memory 208760 kb
Host smart-6d7e6373-e2df-491f-90e6-d7f3a1fbf894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152146356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.4152146356
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.776969513
Short name T145
Test name
Test status
Simulation time 215152169 ps
CPU time 1.32 seconds
Started May 12 03:00:54 PM PDT 24
Finished May 12 03:00:56 PM PDT 24
Peak memory 200788 kb
Host smart-234409ff-9f4a-4bd5-9c05-c7f368656121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776969513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.776969513
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.466324407
Short name T114
Test name
Test status
Simulation time 65119241 ps
CPU time 0.76 seconds
Started May 12 03:05:02 PM PDT 24
Finished May 12 03:05:04 PM PDT 24
Peak memory 200260 kb
Host smart-c74ca255-a1b1-471a-bf2c-a14e3cbf1078
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466324407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.466324407
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.507784147
Short name T12
Test name
Test status
Simulation time 212023420 ps
CPU time 0.93 seconds
Started May 12 03:00:45 PM PDT 24
Finished May 12 03:00:46 PM PDT 24
Peak memory 200704 kb
Host smart-e51f4a49-8054-40e5-a8f2-cc56aaefb7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507784147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.507784147
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2029414806
Short name T140
Test name
Test status
Simulation time 244611315 ps
CPU time 1.05 seconds
Started May 12 03:01:59 PM PDT 24
Finished May 12 03:02:00 PM PDT 24
Peak memory 217932 kb
Host smart-fb590f78-f3e5-4819-9ad1-6d0ba6e99bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029414806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2029414806
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.320096305
Short name T118
Test name
Test status
Simulation time 796531470 ps
CPU time 3.23 seconds
Started May 12 03:04:59 PM PDT 24
Finished May 12 03:05:03 PM PDT 24
Peak memory 200620 kb
Host smart-bc26a154-4712-4dae-ab7e-3b4837a75867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320096305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.320096305
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3144687493
Short name T590
Test name
Test status
Simulation time 144567567 ps
CPU time 2.03 seconds
Started May 12 03:05:02 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 208820 kb
Host smart-22617790-b042-40b9-aaf7-e2bf4c077b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144687493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3144687493
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1893878280
Short name T123
Test name
Test status
Simulation time 930156128 ps
CPU time 3.62 seconds
Started May 12 03:05:01 PM PDT 24
Finished May 12 03:05:06 PM PDT 24
Peak memory 200600 kb
Host smart-6f354f6f-0ffb-4126-ad66-0f9bb9ae8127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893878280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1893878280
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3960588332
Short name T121
Test name
Test status
Simulation time 932625579 ps
CPU time 3.17 seconds
Started May 12 03:05:04 PM PDT 24
Finished May 12 03:05:08 PM PDT 24
Peak memory 200648 kb
Host smart-55591375-10d5-4810-bd4e-e31c0156554f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960588332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3960588332
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3766169115
Short name T74
Test name
Test status
Simulation time 128065804 ps
CPU time 1.71 seconds
Started May 12 03:00:48 PM PDT 24
Finished May 12 03:00:50 PM PDT 24
Peak memory 200828 kb
Host smart-94be26ea-bd05-4857-9213-3fbec1df0832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766169115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3766169115
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2927631276
Short name T560
Test name
Test status
Simulation time 102031347 ps
CPU time 1.32 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:50 PM PDT 24
Peak memory 200580 kb
Host smart-7d155ee4-8c3d-4246-b6ee-a06bf37c7d7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927631276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
927631276
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3942588298
Short name T544
Test name
Test status
Simulation time 483075183 ps
CPU time 5.86 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:54 PM PDT 24
Peak memory 200492 kb
Host smart-337a7947-70b7-462d-b7b1-88f0ce0f7c17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942588298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
942588298
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2640719026
Short name T553
Test name
Test status
Simulation time 88454576 ps
CPU time 0.84 seconds
Started May 12 03:04:44 PM PDT 24
Finished May 12 03:04:45 PM PDT 24
Peak memory 200312 kb
Host smart-8e9d1382-ba58-4f05-8533-7a59f15219a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640719026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
640719026
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2303960291
Short name T610
Test name
Test status
Simulation time 205283178 ps
CPU time 1.62 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:50 PM PDT 24
Peak memory 212080 kb
Host smart-38e05198-dd1a-4a7d-a087-5d64269c214a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303960291 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2303960291
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.404559235
Short name T614
Test name
Test status
Simulation time 57188932 ps
CPU time 0.76 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:49 PM PDT 24
Peak memory 200360 kb
Host smart-60c501a2-dc04-4235-9016-8fb34ded6ee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404559235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.404559235
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.866209655
Short name T600
Test name
Test status
Simulation time 89482528 ps
CPU time 1 seconds
Started May 12 03:04:46 PM PDT 24
Finished May 12 03:04:48 PM PDT 24
Peak memory 200428 kb
Host smart-859e6b2c-0e46-4564-b356-e8c5d5f60b07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866209655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.866209655
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2165420361
Short name T563
Test name
Test status
Simulation time 317665951 ps
CPU time 2.23 seconds
Started May 12 03:04:44 PM PDT 24
Finished May 12 03:04:47 PM PDT 24
Peak memory 208788 kb
Host smart-c604a8f3-26b0-4231-9d98-cd2f195a4863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165420361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2165420361
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2032631783
Short name T128
Test name
Test status
Simulation time 491707380 ps
CPU time 2.03 seconds
Started May 12 03:04:45 PM PDT 24
Finished May 12 03:04:48 PM PDT 24
Peak memory 200680 kb
Host smart-fd663de5-bf6c-47bc-8d04-7f7ebe4f694e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032631783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2032631783
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1084748383
Short name T593
Test name
Test status
Simulation time 107206664 ps
CPU time 1.34 seconds
Started May 12 03:04:46 PM PDT 24
Finished May 12 03:04:48 PM PDT 24
Peak memory 200548 kb
Host smart-df1f32da-5d75-44a4-99e1-2204bd07edb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084748383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
084748383
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2032306814
Short name T554
Test name
Test status
Simulation time 270240397 ps
CPU time 3.44 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:50 PM PDT 24
Peak memory 200520 kb
Host smart-e1234b96-520a-4af6-b49c-b1adbb1114cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032306814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
032306814
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.949933022
Short name T599
Test name
Test status
Simulation time 136655004 ps
CPU time 1 seconds
Started May 12 03:04:45 PM PDT 24
Finished May 12 03:04:46 PM PDT 24
Peak memory 200348 kb
Host smart-05be9b50-4e30-4e73-8606-fffd83ecba18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949933022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.949933022
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3614466950
Short name T64
Test name
Test status
Simulation time 122707101 ps
CPU time 1.08 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:50 PM PDT 24
Peak memory 200412 kb
Host smart-bfc62ce5-6dbf-470b-b2ab-b853f0bfbccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614466950 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3614466950
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2338019649
Short name T559
Test name
Test status
Simulation time 86076573 ps
CPU time 0.89 seconds
Started May 12 03:04:48 PM PDT 24
Finished May 12 03:04:50 PM PDT 24
Peak memory 200352 kb
Host smart-e5e657ac-cf04-4621-bcc4-d9d0b4c012fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338019649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2338019649
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1392985756
Short name T616
Test name
Test status
Simulation time 187655600 ps
CPU time 1.41 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:49 PM PDT 24
Peak memory 200496 kb
Host smart-a97438fb-7599-40f8-96c9-e856efd40cb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392985756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1392985756
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2118949841
Short name T119
Test name
Test status
Simulation time 419362715 ps
CPU time 1.83 seconds
Started May 12 03:04:48 PM PDT 24
Finished May 12 03:04:51 PM PDT 24
Peak memory 200488 kb
Host smart-b7c38997-f2c0-45f9-aed5-39df0bf72d73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118949841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2118949841
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.348418837
Short name T552
Test name
Test status
Simulation time 120749632 ps
CPU time 1.08 seconds
Started May 12 03:04:59 PM PDT 24
Finished May 12 03:05:01 PM PDT 24
Peak memory 200324 kb
Host smart-d79cd593-e5c9-4676-a0c7-024fb84784a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348418837 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.348418837
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1650582940
Short name T571
Test name
Test status
Simulation time 78031510 ps
CPU time 0.84 seconds
Started May 12 03:05:03 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 200360 kb
Host smart-0f34f0c0-c221-4fc0-9a20-f0df996c0a59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650582940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1650582940
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.349273347
Short name T592
Test name
Test status
Simulation time 79651365 ps
CPU time 1.04 seconds
Started May 12 03:05:00 PM PDT 24
Finished May 12 03:05:01 PM PDT 24
Peak memory 200372 kb
Host smart-74ce5ef4-33df-49dd-8cce-7007671e49e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349273347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.349273347
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.975469445
Short name T60
Test name
Test status
Simulation time 117787281 ps
CPU time 1.27 seconds
Started May 12 03:05:02 PM PDT 24
Finished May 12 03:05:04 PM PDT 24
Peak memory 208640 kb
Host smart-5cf7fc48-b3de-4d44-846b-be7c0e469538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975469445 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.975469445
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1905353700
Short name T106
Test name
Test status
Simulation time 79233849 ps
CPU time 0.97 seconds
Started May 12 03:05:03 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 200372 kb
Host smart-c48b1ae1-41cc-4876-9e41-d739834b5c82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905353700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1905353700
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1509552345
Short name T612
Test name
Test status
Simulation time 157361118 ps
CPU time 2.37 seconds
Started May 12 03:05:00 PM PDT 24
Finished May 12 03:05:03 PM PDT 24
Peak memory 208804 kb
Host smart-bf878f6d-3e69-48e2-b495-a0f73c7915c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509552345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1509552345
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3266678833
Short name T613
Test name
Test status
Simulation time 635583195 ps
CPU time 2.26 seconds
Started May 12 03:05:02 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 200628 kb
Host smart-3d16ef9f-031a-4742-a85f-3bb3e762613f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266678833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3266678833
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1884891995
Short name T89
Test name
Test status
Simulation time 138522533 ps
CPU time 1.13 seconds
Started May 12 03:05:00 PM PDT 24
Finished May 12 03:05:01 PM PDT 24
Peak memory 208608 kb
Host smart-62bfa5bc-da07-409c-8274-132f09e735c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884891995 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1884891995
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4047426609
Short name T108
Test name
Test status
Simulation time 62782674 ps
CPU time 0.88 seconds
Started May 12 03:05:03 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 200364 kb
Host smart-68ed9f2c-1383-4ee2-b600-0134285dba30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047426609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.4047426609
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1197300461
Short name T110
Test name
Test status
Simulation time 142874865 ps
CPU time 1.49 seconds
Started May 12 03:05:01 PM PDT 24
Finished May 12 03:05:03 PM PDT 24
Peak memory 200576 kb
Host smart-ace8353f-dbd6-4564-b9c9-ee5ee73d8234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197300461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1197300461
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.132183631
Short name T84
Test name
Test status
Simulation time 200158595 ps
CPU time 1.91 seconds
Started May 12 03:05:02 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 208860 kb
Host smart-0e6c8283-1dd7-48b7-9245-bebbdfe3aa37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132183631 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.132183631
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2402451834
Short name T543
Test name
Test status
Simulation time 72404815 ps
CPU time 0.85 seconds
Started May 12 03:05:01 PM PDT 24
Finished May 12 03:05:03 PM PDT 24
Peak memory 200384 kb
Host smart-4f14bf0c-ee56-4b48-b085-96975c6baf19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402451834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2402451834
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.74547278
Short name T112
Test name
Test status
Simulation time 140908261 ps
CPU time 1.47 seconds
Started May 12 03:05:02 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 200604 kb
Host smart-d3ff7685-c4a4-4702-af48-d3a2bacd1f4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74547278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sam
e_csr_outstanding.74547278
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.54213240
Short name T584
Test name
Test status
Simulation time 143277787 ps
CPU time 2.09 seconds
Started May 12 03:05:02 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 211516 kb
Host smart-1066b536-d77f-4e57-a8c4-c045c1408dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54213240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.54213240
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2619518726
Short name T589
Test name
Test status
Simulation time 180950654 ps
CPU time 1.23 seconds
Started May 12 03:05:03 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 208704 kb
Host smart-70e7c0e9-6656-4460-a256-f6ea57087211
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619518726 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2619518726
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2343773737
Short name T607
Test name
Test status
Simulation time 89771609 ps
CPU time 0.88 seconds
Started May 12 03:05:05 PM PDT 24
Finished May 12 03:05:07 PM PDT 24
Peak memory 200336 kb
Host smart-dcd256bc-aec7-451e-b8fa-ef1b09889b0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343773737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2343773737
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2591020716
Short name T549
Test name
Test status
Simulation time 148779520 ps
CPU time 1.15 seconds
Started May 12 03:05:05 PM PDT 24
Finished May 12 03:05:07 PM PDT 24
Peak memory 200584 kb
Host smart-a8771847-013a-4ff9-bb19-294fb8f8b0a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591020716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2591020716
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2312424444
Short name T573
Test name
Test status
Simulation time 232832229 ps
CPU time 1.93 seconds
Started May 12 03:05:02 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 216824 kb
Host smart-e36709f9-b884-4362-82fc-73af25f9676c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312424444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2312424444
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.441283930
Short name T127
Test name
Test status
Simulation time 680202027 ps
CPU time 2.34 seconds
Started May 12 03:05:03 PM PDT 24
Finished May 12 03:05:07 PM PDT 24
Peak memory 200600 kb
Host smart-a317ccaf-93e7-4468-b0f9-c150c79ceb0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441283930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.441283930
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2481208255
Short name T591
Test name
Test status
Simulation time 184953399 ps
CPU time 1.19 seconds
Started May 12 03:05:03 PM PDT 24
Finished May 12 03:05:05 PM PDT 24
Peak memory 200564 kb
Host smart-cf3cbebc-068b-4a7e-938a-e97e26ec4f4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481208255 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2481208255
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3433308219
Short name T605
Test name
Test status
Simulation time 62110455 ps
CPU time 0.79 seconds
Started May 12 03:05:04 PM PDT 24
Finished May 12 03:05:06 PM PDT 24
Peak memory 200344 kb
Host smart-358f3a2d-4353-48d6-8dd1-fac19b6e655e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433308219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3433308219
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2212949842
Short name T594
Test name
Test status
Simulation time 209958070 ps
CPU time 1.59 seconds
Started May 12 03:05:04 PM PDT 24
Finished May 12 03:05:07 PM PDT 24
Peak memory 200536 kb
Host smart-06563103-44ed-4ce1-bcc1-2ec80c5546f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212949842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2212949842
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.655218272
Short name T587
Test name
Test status
Simulation time 410626701 ps
CPU time 2.97 seconds
Started May 12 03:05:09 PM PDT 24
Finished May 12 03:05:13 PM PDT 24
Peak memory 208796 kb
Host smart-795b7047-b888-405a-9b9d-38a483aeec8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655218272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.655218272
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.6493954
Short name T120
Test name
Test status
Simulation time 773571426 ps
CPU time 3.13 seconds
Started May 12 03:05:05 PM PDT 24
Finished May 12 03:05:09 PM PDT 24
Peak memory 200664 kb
Host smart-4b0a44ff-493f-4503-a894-46b4d40f996c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6493954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.6493954
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1425009278
Short name T575
Test name
Test status
Simulation time 107189791 ps
CPU time 1.06 seconds
Started May 12 03:05:06 PM PDT 24
Finished May 12 03:05:08 PM PDT 24
Peak memory 208572 kb
Host smart-1d20b15c-a1cc-45cb-bbb8-72ca088c8af9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425009278 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1425009278
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2496876983
Short name T581
Test name
Test status
Simulation time 75490355 ps
CPU time 0.77 seconds
Started May 12 03:05:08 PM PDT 24
Finished May 12 03:05:10 PM PDT 24
Peak memory 200088 kb
Host smart-cae1fbfc-6be7-44b5-8045-34b758c45f0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496876983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2496876983
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3224451260
Short name T556
Test name
Test status
Simulation time 157112570 ps
CPU time 1.19 seconds
Started May 12 03:05:07 PM PDT 24
Finished May 12 03:05:09 PM PDT 24
Peak memory 200340 kb
Host smart-78af0f52-86d7-42e2-a16f-ee1319d4b6c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224451260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3224451260
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.186033597
Short name T577
Test name
Test status
Simulation time 217233851 ps
CPU time 3.12 seconds
Started May 12 03:05:06 PM PDT 24
Finished May 12 03:05:10 PM PDT 24
Peak memory 208724 kb
Host smart-0307689a-78cf-4b2e-8000-1dfe9c3aedd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186033597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.186033597
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1676644371
Short name T579
Test name
Test status
Simulation time 140861637 ps
CPU time 1.1 seconds
Started May 12 03:05:08 PM PDT 24
Finished May 12 03:05:10 PM PDT 24
Peak memory 200484 kb
Host smart-040b4591-bfb9-4b76-8ef2-83a12decc124
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676644371 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1676644371
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1499791240
Short name T557
Test name
Test status
Simulation time 64410637 ps
CPU time 0.76 seconds
Started May 12 03:05:07 PM PDT 24
Finished May 12 03:05:08 PM PDT 24
Peak memory 200336 kb
Host smart-02681372-a87a-473e-89c4-226f55aa7208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499791240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1499791240
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2851083565
Short name T111
Test name
Test status
Simulation time 221619492 ps
CPU time 1.42 seconds
Started May 12 03:05:09 PM PDT 24
Finished May 12 03:05:11 PM PDT 24
Peak memory 200588 kb
Host smart-77098301-6eb3-4a8e-8fea-609eab14d524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851083565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2851083565
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1544965113
Short name T583
Test name
Test status
Simulation time 138314987 ps
CPU time 2.01 seconds
Started May 12 03:05:08 PM PDT 24
Finished May 12 03:05:11 PM PDT 24
Peak memory 208700 kb
Host smart-2c3f1489-a967-4d02-97aa-4986f9648f05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544965113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1544965113
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.661252852
Short name T62
Test name
Test status
Simulation time 496994516 ps
CPU time 2.01 seconds
Started May 12 03:05:07 PM PDT 24
Finished May 12 03:05:10 PM PDT 24
Peak memory 200576 kb
Host smart-e52c6bd8-c128-4abe-8c1b-3f9b5dd722f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661252852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.661252852
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.801110805
Short name T611
Test name
Test status
Simulation time 102528162 ps
CPU time 1.05 seconds
Started May 12 03:05:11 PM PDT 24
Finished May 12 03:05:12 PM PDT 24
Peak memory 208800 kb
Host smart-5b11e98a-c470-4036-a04d-7490a9753430
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801110805 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.801110805
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3098207774
Short name T608
Test name
Test status
Simulation time 88899575 ps
CPU time 0.87 seconds
Started May 12 03:05:08 PM PDT 24
Finished May 12 03:05:10 PM PDT 24
Peak memory 200292 kb
Host smart-ff0a1166-0bc2-4d5a-b71d-ad47f44b0a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098207774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3098207774
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.311736974
Short name T548
Test name
Test status
Simulation time 115950250 ps
CPU time 1.06 seconds
Started May 12 03:05:07 PM PDT 24
Finished May 12 03:05:09 PM PDT 24
Peak memory 200380 kb
Host smart-f4745d45-60b4-4a0d-9b5d-049f09dbacfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311736974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.311736974
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3229874863
Short name T604
Test name
Test status
Simulation time 335876496 ps
CPU time 2.34 seconds
Started May 12 03:05:07 PM PDT 24
Finished May 12 03:05:10 PM PDT 24
Peak memory 200504 kb
Host smart-3b10979b-744b-48e7-a6df-730616b89229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229874863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3229874863
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1929526791
Short name T598
Test name
Test status
Simulation time 193455176 ps
CPU time 1.24 seconds
Started May 12 03:05:10 PM PDT 24
Finished May 12 03:05:12 PM PDT 24
Peak memory 208616 kb
Host smart-46940a3d-ef05-44ce-9a5f-bb5be7530adc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929526791 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1929526791
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2622687656
Short name T115
Test name
Test status
Simulation time 75037764 ps
CPU time 0.85 seconds
Started May 12 03:05:09 PM PDT 24
Finished May 12 03:05:11 PM PDT 24
Peak memory 200384 kb
Host smart-62207a86-a107-40fa-9710-bfd06e217aa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622687656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2622687656
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4057745124
Short name T109
Test name
Test status
Simulation time 125118426 ps
CPU time 1.24 seconds
Started May 12 03:05:08 PM PDT 24
Finished May 12 03:05:10 PM PDT 24
Peak memory 200616 kb
Host smart-05701ee7-8fad-4963-9da9-59d70ccc126b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057745124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4057745124
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2754510250
Short name T85
Test name
Test status
Simulation time 439790863 ps
CPU time 3.13 seconds
Started May 12 03:05:10 PM PDT 24
Finished May 12 03:05:14 PM PDT 24
Peak memory 208804 kb
Host smart-7645cbb8-d7a6-403a-a1b0-9f5021bbdd14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754510250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2754510250
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3740319155
Short name T88
Test name
Test status
Simulation time 430901048 ps
CPU time 1.93 seconds
Started May 12 03:05:10 PM PDT 24
Finished May 12 03:05:13 PM PDT 24
Peak memory 200604 kb
Host smart-403a78fd-bd4b-49f9-9ac8-be4e18e11e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740319155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3740319155
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.104837517
Short name T564
Test name
Test status
Simulation time 99158124 ps
CPU time 1.39 seconds
Started May 12 03:04:49 PM PDT 24
Finished May 12 03:04:51 PM PDT 24
Peak memory 200536 kb
Host smart-9f8ef9ba-7271-4e5e-8343-f5d4e4d7769e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104837517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.104837517
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2992853348
Short name T568
Test name
Test status
Simulation time 477666870 ps
CPU time 5.45 seconds
Started May 12 03:04:53 PM PDT 24
Finished May 12 03:04:59 PM PDT 24
Peak memory 200528 kb
Host smart-a09ee6a0-e843-413a-bd56-f142d3dfd608
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992853348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
992853348
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2191188132
Short name T550
Test name
Test status
Simulation time 94650113 ps
CPU time 0.83 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:49 PM PDT 24
Peak memory 200348 kb
Host smart-4e0547db-ea20-461e-a08f-fda620b8e7f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191188132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
191188132
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4231153600
Short name T569
Test name
Test status
Simulation time 206691166 ps
CPU time 1.31 seconds
Started May 12 03:04:50 PM PDT 24
Finished May 12 03:04:52 PM PDT 24
Peak memory 208612 kb
Host smart-88758969-72b7-43ce-b2dc-274888496378
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231153600 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.4231153600
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3134869374
Short name T562
Test name
Test status
Simulation time 57619633 ps
CPU time 0.78 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:49 PM PDT 24
Peak memory 200316 kb
Host smart-732082c3-f5eb-43e1-8795-486122dac743
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134869374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3134869374
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1731445171
Short name T113
Test name
Test status
Simulation time 83648118 ps
CPU time 1.05 seconds
Started May 12 03:04:53 PM PDT 24
Finished May 12 03:04:55 PM PDT 24
Peak memory 200408 kb
Host smart-6c59de15-2cab-4c86-acfb-8d271d91293d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731445171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1731445171
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.287540992
Short name T63
Test name
Test status
Simulation time 465991484 ps
CPU time 3.81 seconds
Started May 12 03:04:46 PM PDT 24
Finished May 12 03:04:50 PM PDT 24
Peak memory 208728 kb
Host smart-b2445ea3-f4c2-49f0-b3c9-2f19634beb2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287540992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.287540992
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1704744842
Short name T566
Test name
Test status
Simulation time 418831353 ps
CPU time 1.88 seconds
Started May 12 03:04:47 PM PDT 24
Finished May 12 03:04:50 PM PDT 24
Peak memory 200576 kb
Host smart-45d50540-4ead-4cf6-b05a-2198160804d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704744842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1704744842
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2731441315
Short name T585
Test name
Test status
Simulation time 226239401 ps
CPU time 1.72 seconds
Started May 12 03:04:51 PM PDT 24
Finished May 12 03:04:53 PM PDT 24
Peak memory 200564 kb
Host smart-a58f4e4b-9500-4b17-8199-79ae294578c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731441315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
731441315
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1242324525
Short name T580
Test name
Test status
Simulation time 1183116222 ps
CPU time 5.95 seconds
Started May 12 03:04:51 PM PDT 24
Finished May 12 03:04:57 PM PDT 24
Peak memory 200496 kb
Host smart-75591509-0f74-4baa-b591-4f17195eaac8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242324525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
242324525
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2333381999
Short name T565
Test name
Test status
Simulation time 98284633 ps
CPU time 0.83 seconds
Started May 12 03:04:50 PM PDT 24
Finished May 12 03:04:51 PM PDT 24
Peak memory 200360 kb
Host smart-3684f1fe-91fd-4079-aa00-48be153d63e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333381999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
333381999
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4047310778
Short name T82
Test name
Test status
Simulation time 189659536 ps
CPU time 2.02 seconds
Started May 12 03:04:49 PM PDT 24
Finished May 12 03:04:52 PM PDT 24
Peak memory 208872 kb
Host smart-366be838-e483-4d8b-b538-ec7d3b1dbe3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047310778 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.4047310778
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.362992655
Short name T576
Test name
Test status
Simulation time 81735334 ps
CPU time 0.88 seconds
Started May 12 03:04:57 PM PDT 24
Finished May 12 03:04:58 PM PDT 24
Peak memory 200368 kb
Host smart-e106e13f-65cf-4884-90b8-9b01ed516149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362992655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.362992655
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2712003969
Short name T597
Test name
Test status
Simulation time 156201370 ps
CPU time 1.23 seconds
Started May 12 03:04:49 PM PDT 24
Finished May 12 03:04:51 PM PDT 24
Peak memory 200416 kb
Host smart-4756d1bb-2e2f-4935-b3a8-51a8f05e09cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712003969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2712003969
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4276282707
Short name T86
Test name
Test status
Simulation time 268201840 ps
CPU time 2.13 seconds
Started May 12 03:04:51 PM PDT 24
Finished May 12 03:04:53 PM PDT 24
Peak memory 200604 kb
Host smart-6ae49340-4984-4a1b-9af1-1363e4b07b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276282707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.4276282707
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2260511830
Short name T122
Test name
Test status
Simulation time 477081510 ps
CPU time 2.18 seconds
Started May 12 03:04:53 PM PDT 24
Finished May 12 03:04:56 PM PDT 24
Peak memory 200616 kb
Host smart-ad312151-d369-4f22-b5f3-abdcd8ccd173
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260511830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2260511830
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3170738474
Short name T618
Test name
Test status
Simulation time 154318959 ps
CPU time 2.03 seconds
Started May 12 03:04:53 PM PDT 24
Finished May 12 03:04:56 PM PDT 24
Peak memory 200556 kb
Host smart-589188f4-6480-44e4-a2f9-357111b403fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170738474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
170738474
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2250293625
Short name T545
Test name
Test status
Simulation time 2318628206 ps
CPU time 10.16 seconds
Started May 12 03:04:53 PM PDT 24
Finished May 12 03:05:03 PM PDT 24
Peak memory 200560 kb
Host smart-702f0db5-ff86-4faa-941f-7b5885fb74a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250293625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
250293625
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3615884689
Short name T596
Test name
Test status
Simulation time 93069050 ps
CPU time 0.81 seconds
Started May 12 03:04:50 PM PDT 24
Finished May 12 03:04:51 PM PDT 24
Peak memory 200344 kb
Host smart-7955a105-6531-40d0-ace1-0e061bba798f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615884689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
615884689
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.933373065
Short name T561
Test name
Test status
Simulation time 129196518 ps
CPU time 1.03 seconds
Started May 12 03:04:55 PM PDT 24
Finished May 12 03:04:56 PM PDT 24
Peak memory 200404 kb
Host smart-5ee37d88-1538-4283-89b5-2abe8e5a1782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933373065 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.933373065
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.382666619
Short name T94
Test name
Test status
Simulation time 60281313 ps
CPU time 0.78 seconds
Started May 12 03:04:52 PM PDT 24
Finished May 12 03:04:54 PM PDT 24
Peak memory 200352 kb
Host smart-3464dc8b-4fae-4599-9bb4-fa7df1438920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382666619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.382666619
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1687898794
Short name T107
Test name
Test status
Simulation time 185157122 ps
CPU time 1.45 seconds
Started May 12 03:04:54 PM PDT 24
Finished May 12 03:04:56 PM PDT 24
Peak memory 200520 kb
Host smart-c188e94b-9003-4e6f-b68d-fcd3394b62b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687898794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1687898794
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2339605210
Short name T601
Test name
Test status
Simulation time 111747591 ps
CPU time 1.55 seconds
Started May 12 03:04:51 PM PDT 24
Finished May 12 03:04:53 PM PDT 24
Peak memory 208660 kb
Host smart-c39d0e5b-cea4-422e-9f60-9a6b3b95cfbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339605210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2339605210
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1013427487
Short name T87
Test name
Test status
Simulation time 467942514 ps
CPU time 2.14 seconds
Started May 12 03:04:52 PM PDT 24
Finished May 12 03:04:54 PM PDT 24
Peak memory 200556 kb
Host smart-b694e1aa-81cd-49ba-b1b1-002a7fd4ecd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013427487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1013427487
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1798751636
Short name T588
Test name
Test status
Simulation time 100782515 ps
CPU time 0.96 seconds
Started May 12 03:04:54 PM PDT 24
Finished May 12 03:04:56 PM PDT 24
Peak memory 200512 kb
Host smart-4fc9aa3b-983c-4c38-a494-62b391cae7c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798751636 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1798751636
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1756080547
Short name T570
Test name
Test status
Simulation time 70817037 ps
CPU time 0.86 seconds
Started May 12 03:04:54 PM PDT 24
Finished May 12 03:04:56 PM PDT 24
Peak memory 200296 kb
Host smart-3d59708c-40c1-432f-b68a-0a715b6c2d2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756080547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1756080547
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.713346258
Short name T572
Test name
Test status
Simulation time 111364845 ps
CPU time 1.23 seconds
Started May 12 03:04:52 PM PDT 24
Finished May 12 03:04:54 PM PDT 24
Peak memory 200540 kb
Host smart-2829b048-bda5-468b-98f1-0b0d985c23a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713346258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.713346258
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.939715461
Short name T606
Test name
Test status
Simulation time 509904873 ps
CPU time 4.19 seconds
Started May 12 03:04:54 PM PDT 24
Finished May 12 03:04:59 PM PDT 24
Peak memory 208972 kb
Host smart-0bde7f95-fafc-454e-8fd5-fc4b923f85c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939715461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.939715461
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3821513417
Short name T603
Test name
Test status
Simulation time 415035972 ps
CPU time 1.74 seconds
Started May 12 03:04:54 PM PDT 24
Finished May 12 03:04:56 PM PDT 24
Peak memory 200628 kb
Host smart-fc7b5941-4b77-4438-ac2e-08bb9b42e0c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821513417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3821513417
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3780539847
Short name T595
Test name
Test status
Simulation time 129532631 ps
CPU time 1.38 seconds
Started May 12 03:04:53 PM PDT 24
Finished May 12 03:04:55 PM PDT 24
Peak memory 208632 kb
Host smart-c93166d4-d337-42bf-8f83-f996496c168c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780539847 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3780539847
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.290936900
Short name T546
Test name
Test status
Simulation time 76036433 ps
CPU time 0.86 seconds
Started May 12 03:04:56 PM PDT 24
Finished May 12 03:04:57 PM PDT 24
Peak memory 200360 kb
Host smart-1f5a3816-58c1-4523-a9e8-a5b851c90f49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290936900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.290936900
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2352963849
Short name T602
Test name
Test status
Simulation time 96074173 ps
CPU time 1.26 seconds
Started May 12 03:04:54 PM PDT 24
Finished May 12 03:04:56 PM PDT 24
Peak memory 200620 kb
Host smart-04c1bdfc-32a3-4aa3-8ab4-17ba17f97fb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352963849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2352963849
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1293521206
Short name T124
Test name
Test status
Simulation time 160542044 ps
CPU time 2.25 seconds
Started May 12 03:04:54 PM PDT 24
Finished May 12 03:04:57 PM PDT 24
Peak memory 208736 kb
Host smart-cfe20f19-c399-4b09-a723-5aae176d878a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293521206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1293521206
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1831148688
Short name T117
Test name
Test status
Simulation time 768870499 ps
CPU time 2.78 seconds
Started May 12 03:04:56 PM PDT 24
Finished May 12 03:04:59 PM PDT 24
Peak memory 208864 kb
Host smart-0de8ec2d-160e-41ee-ac43-e97f887dd1e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831148688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1831148688
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4059464617
Short name T555
Test name
Test status
Simulation time 187329384 ps
CPU time 2.05 seconds
Started May 12 03:04:58 PM PDT 24
Finished May 12 03:05:01 PM PDT 24
Peak memory 208824 kb
Host smart-865bc267-27ea-4497-a4f4-c94799331c82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059464617 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4059464617
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4104889706
Short name T547
Test name
Test status
Simulation time 89694806 ps
CPU time 0.83 seconds
Started May 12 03:05:06 PM PDT 24
Finished May 12 03:05:08 PM PDT 24
Peak memory 200288 kb
Host smart-036b4575-f184-453c-85f8-d3294b9c48c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104889706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4104889706
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.81597061
Short name T617
Test name
Test status
Simulation time 233197041 ps
CPU time 1.5 seconds
Started May 12 03:04:59 PM PDT 24
Finished May 12 03:05:01 PM PDT 24
Peak memory 200832 kb
Host smart-d29db8d5-1ee0-4a06-ad35-c0a88de753c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81597061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same
_csr_outstanding.81597061
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1811712201
Short name T582
Test name
Test status
Simulation time 491497622 ps
CPU time 3.83 seconds
Started May 12 03:04:56 PM PDT 24
Finished May 12 03:05:00 PM PDT 24
Peak memory 208808 kb
Host smart-6ffe1853-e615-478b-9448-c0c7e963dee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811712201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1811712201
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3520765579
Short name T83
Test name
Test status
Simulation time 933624225 ps
CPU time 3.11 seconds
Started May 12 03:05:09 PM PDT 24
Finished May 12 03:05:13 PM PDT 24
Peak memory 200548 kb
Host smart-81a2b0c7-0170-49f6-b6a5-4cedf9ee74b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520765579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3520765579
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.985273780
Short name T558
Test name
Test status
Simulation time 124317241 ps
CPU time 0.99 seconds
Started May 12 03:04:57 PM PDT 24
Finished May 12 03:04:58 PM PDT 24
Peak memory 200460 kb
Host smart-b016ce26-e0ce-4d9a-8b86-b11ef63c67ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985273780 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.985273780
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.445855409
Short name T619
Test name
Test status
Simulation time 79072267 ps
CPU time 0.9 seconds
Started May 12 03:04:56 PM PDT 24
Finished May 12 03:04:58 PM PDT 24
Peak memory 200472 kb
Host smart-dd01c701-96a2-4701-8489-0d49730568b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445855409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.445855409
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.989574331
Short name T551
Test name
Test status
Simulation time 210664951 ps
CPU time 1.66 seconds
Started May 12 03:04:59 PM PDT 24
Finished May 12 03:05:02 PM PDT 24
Peak memory 200636 kb
Host smart-7f27fe31-a313-40e9-b518-ae221565681f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989574331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.989574331
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1300284654
Short name T578
Test name
Test status
Simulation time 270579058 ps
CPU time 2.18 seconds
Started May 12 03:04:56 PM PDT 24
Finished May 12 03:04:59 PM PDT 24
Peak memory 216868 kb
Host smart-a2c944aa-61f6-43c1-9620-b29a30835384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300284654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1300284654
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1966024359
Short name T574
Test name
Test status
Simulation time 464123516 ps
CPU time 1.95 seconds
Started May 12 03:04:57 PM PDT 24
Finished May 12 03:05:00 PM PDT 24
Peak memory 200672 kb
Host smart-977c076b-27ba-41f2-b0f0-206fe241a4f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966024359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1966024359
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.425339672
Short name T586
Test name
Test status
Simulation time 145605846 ps
CPU time 1.16 seconds
Started May 12 03:04:59 PM PDT 24
Finished May 12 03:05:01 PM PDT 24
Peak memory 200388 kb
Host smart-bf63bce1-1567-4fc1-8edf-76b9c46a14c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425339672 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.425339672
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3581285726
Short name T620
Test name
Test status
Simulation time 63162419 ps
CPU time 0.84 seconds
Started May 12 03:04:59 PM PDT 24
Finished May 12 03:05:01 PM PDT 24
Peak memory 200272 kb
Host smart-a956058f-87e3-4680-b5d2-e5bedb272fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581285726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3581285726
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2126696073
Short name T615
Test name
Test status
Simulation time 234150368 ps
CPU time 1.51 seconds
Started May 12 03:04:58 PM PDT 24
Finished May 12 03:05:00 PM PDT 24
Peak memory 200588 kb
Host smart-e5bf814a-5c96-464a-8d7a-859f17ac15ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126696073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2126696073
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2572222780
Short name T609
Test name
Test status
Simulation time 168864768 ps
CPU time 2.7 seconds
Started May 12 03:04:58 PM PDT 24
Finished May 12 03:05:02 PM PDT 24
Peak memory 208744 kb
Host smart-49a1eb69-f8e2-4136-a06d-1e1d79f6c32a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572222780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2572222780
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1516218231
Short name T116
Test name
Test status
Simulation time 925251207 ps
CPU time 3.26 seconds
Started May 12 03:04:57 PM PDT 24
Finished May 12 03:05:01 PM PDT 24
Peak memory 200556 kb
Host smart-fbae7e86-7e1e-48b6-a974-e25b906d27c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516218231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1516218231
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.192512079
Short name T516
Test name
Test status
Simulation time 83904506 ps
CPU time 0.79 seconds
Started May 12 03:00:55 PM PDT 24
Finished May 12 03:00:56 PM PDT 24
Peak memory 200676 kb
Host smart-d2c3066c-b6b2-457a-b7e0-f56ac1d7bf87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192512079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.192512079
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3662507273
Short name T449
Test name
Test status
Simulation time 2350257593 ps
CPU time 9.11 seconds
Started May 12 03:00:48 PM PDT 24
Finished May 12 03:00:58 PM PDT 24
Peak memory 217904 kb
Host smart-4483b9ab-c0dc-46f5-a837-4ffefedd1aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662507273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3662507273
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2453093859
Short name T457
Test name
Test status
Simulation time 244075624 ps
CPU time 1.22 seconds
Started May 12 03:00:48 PM PDT 24
Finished May 12 03:00:50 PM PDT 24
Peak memory 217944 kb
Host smart-4bce55a1-749d-4be3-bed9-c2defe21916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453093859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2453093859
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3348033424
Short name T296
Test name
Test status
Simulation time 1426920760 ps
CPU time 5.92 seconds
Started May 12 03:00:46 PM PDT 24
Finished May 12 03:00:52 PM PDT 24
Peak memory 201008 kb
Host smart-71fdd8cd-26b8-45e2-87fb-df933aca1af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348033424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3348033424
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.487650935
Short name T343
Test name
Test status
Simulation time 147580218 ps
CPU time 1.13 seconds
Started May 12 03:00:48 PM PDT 24
Finished May 12 03:00:50 PM PDT 24
Peak memory 200892 kb
Host smart-b88d4435-3331-49f6-9632-ef3132255351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487650935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.487650935
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2280420664
Short name T229
Test name
Test status
Simulation time 197153862 ps
CPU time 1.32 seconds
Started May 12 03:00:43 PM PDT 24
Finished May 12 03:00:45 PM PDT 24
Peak memory 201036 kb
Host smart-d1234b46-8259-4984-883c-a19e83904449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280420664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2280420664
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1720384990
Short name T317
Test name
Test status
Simulation time 3860391032 ps
CPU time 16.54 seconds
Started May 12 03:00:52 PM PDT 24
Finished May 12 03:01:08 PM PDT 24
Peak memory 201232 kb
Host smart-8a5eca79-cd68-4162-8021-720187543e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720384990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1720384990
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.205071563
Short name T266
Test name
Test status
Simulation time 193323572 ps
CPU time 1.23 seconds
Started May 12 03:00:49 PM PDT 24
Finished May 12 03:00:50 PM PDT 24
Peak memory 200800 kb
Host smart-63bd79a3-0d0c-49d8-bf40-70798b42b83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205071563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.205071563
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2463264691
Short name T304
Test name
Test status
Simulation time 69526788 ps
CPU time 0.8 seconds
Started May 12 03:01:01 PM PDT 24
Finished May 12 03:01:02 PM PDT 24
Peak memory 200704 kb
Host smart-99450508-04f9-4ab7-be00-ccdb3a9bc6dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463264691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2463264691
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1868049530
Short name T36
Test name
Test status
Simulation time 1231754753 ps
CPU time 6.22 seconds
Started May 12 03:01:01 PM PDT 24
Finished May 12 03:01:07 PM PDT 24
Peak memory 222384 kb
Host smart-43d77327-97a8-43e6-bc05-bd67a757a960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868049530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1868049530
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2929083681
Short name T336
Test name
Test status
Simulation time 243833345 ps
CPU time 1.15 seconds
Started May 12 03:01:00 PM PDT 24
Finished May 12 03:01:02 PM PDT 24
Peak memory 218284 kb
Host smart-67efa88a-0710-4d5b-b658-0380d61cce0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929083681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2929083681
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.748512096
Short name T189
Test name
Test status
Simulation time 184695765 ps
CPU time 0.88 seconds
Started May 12 03:00:53 PM PDT 24
Finished May 12 03:00:54 PM PDT 24
Peak memory 200656 kb
Host smart-d6f8bb6e-3497-40aa-ab62-be30c4193727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748512096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.748512096
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1748912465
Short name T274
Test name
Test status
Simulation time 1999837060 ps
CPU time 7.09 seconds
Started May 12 03:00:55 PM PDT 24
Finished May 12 03:01:03 PM PDT 24
Peak memory 200984 kb
Host smart-387a3490-6eef-4ba5-b498-cca98d44eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748912465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1748912465
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4261334700
Short name T65
Test name
Test status
Simulation time 8747969254 ps
CPU time 13.64 seconds
Started May 12 03:01:01 PM PDT 24
Finished May 12 03:01:15 PM PDT 24
Peak memory 218548 kb
Host smart-5e0011d9-df2f-4b38-b36c-227d7f9901aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261334700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4261334700
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3594461184
Short name T182
Test name
Test status
Simulation time 114568573 ps
CPU time 1 seconds
Started May 12 03:00:58 PM PDT 24
Finished May 12 03:01:00 PM PDT 24
Peak memory 200852 kb
Host smart-90cdf715-fd2a-41e5-8f26-82fcd1a41c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594461184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3594461184
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.888657280
Short name T465
Test name
Test status
Simulation time 112874857 ps
CPU time 1.3 seconds
Started May 12 03:00:57 PM PDT 24
Finished May 12 03:00:59 PM PDT 24
Peak memory 201076 kb
Host smart-e9623727-ba3b-4aab-917a-c5c083266da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888657280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.888657280
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3380820615
Short name T387
Test name
Test status
Simulation time 6213002687 ps
CPU time 23.22 seconds
Started May 12 03:01:01 PM PDT 24
Finished May 12 03:01:24 PM PDT 24
Peak memory 209392 kb
Host smart-48fe6cc0-0783-443e-a881-00752e73a2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380820615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3380820615
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3268671426
Short name T275
Test name
Test status
Simulation time 121150715 ps
CPU time 1.53 seconds
Started May 12 03:00:55 PM PDT 24
Finished May 12 03:00:57 PM PDT 24
Peak memory 200772 kb
Host smart-c8f099d8-118f-4ba0-9483-a2833208d440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268671426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3268671426
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2091644870
Short name T497
Test name
Test status
Simulation time 61448017 ps
CPU time 0.76 seconds
Started May 12 03:02:07 PM PDT 24
Finished May 12 03:02:08 PM PDT 24
Peak memory 200676 kb
Host smart-55472440-20c3-4ded-aa8d-55bff52a535b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091644870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2091644870
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2926919857
Short name T42
Test name
Test status
Simulation time 2363712151 ps
CPU time 8.4 seconds
Started May 12 03:02:06 PM PDT 24
Finished May 12 03:02:15 PM PDT 24
Peak memory 218316 kb
Host smart-0b631dd6-4745-453c-9024-5dd837a1feb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926919857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2926919857
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.125262861
Short name T244
Test name
Test status
Simulation time 244402079 ps
CPU time 1.07 seconds
Started May 12 03:02:05 PM PDT 24
Finished May 12 03:02:06 PM PDT 24
Peak memory 218040 kb
Host smart-eb390d3a-6bcf-4c9a-93e2-386fb608469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125262861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.125262861
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.534717950
Short name T446
Test name
Test status
Simulation time 136246142 ps
CPU time 0.83 seconds
Started May 12 03:01:52 PM PDT 24
Finished May 12 03:01:54 PM PDT 24
Peak memory 200612 kb
Host smart-48e5f5ee-938e-4ede-a209-f6748c6a3c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534717950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.534717950
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.4221054352
Short name T95
Test name
Test status
Simulation time 2032009088 ps
CPU time 7.68 seconds
Started May 12 03:01:53 PM PDT 24
Finished May 12 03:02:01 PM PDT 24
Peak memory 200976 kb
Host smart-f0eed281-de77-4658-bbf0-69d245ffd6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221054352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.4221054352
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.740797693
Short name T413
Test name
Test status
Simulation time 185153773 ps
CPU time 1.21 seconds
Started May 12 03:01:56 PM PDT 24
Finished May 12 03:01:57 PM PDT 24
Peak memory 200892 kb
Host smart-45956b80-b8b9-4fcc-ae35-7ebb9bd45257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740797693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.740797693
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1286063421
Short name T367
Test name
Test status
Simulation time 119830455 ps
CPU time 1.22 seconds
Started May 12 03:01:53 PM PDT 24
Finished May 12 03:01:55 PM PDT 24
Peak memory 201052 kb
Host smart-89742979-ac1a-4011-9f35-6572eda79863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286063421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1286063421
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1828283298
Short name T171
Test name
Test status
Simulation time 2341460043 ps
CPU time 10.42 seconds
Started May 12 03:02:05 PM PDT 24
Finished May 12 03:02:16 PM PDT 24
Peak memory 209360 kb
Host smart-34a29f05-678c-432f-83a6-b25fa28c94c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828283298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1828283298
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2098860202
Short name T499
Test name
Test status
Simulation time 123364650 ps
CPU time 1.48 seconds
Started May 12 03:01:53 PM PDT 24
Finished May 12 03:01:55 PM PDT 24
Peak memory 200820 kb
Host smart-af5bc49a-23fc-47b4-a64c-55daec59d37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098860202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2098860202
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3857626141
Short name T165
Test name
Test status
Simulation time 102831124 ps
CPU time 0.96 seconds
Started May 12 03:01:53 PM PDT 24
Finished May 12 03:01:55 PM PDT 24
Peak memory 200844 kb
Host smart-5c440086-a560-4758-a69f-220657bde330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857626141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3857626141
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1050216037
Short name T242
Test name
Test status
Simulation time 2362008773 ps
CPU time 10.05 seconds
Started May 12 03:01:58 PM PDT 24
Finished May 12 03:02:09 PM PDT 24
Peak memory 218356 kb
Host smart-28aed82f-fa99-48e9-b095-6888790a1651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050216037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1050216037
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.268089968
Short name T219
Test name
Test status
Simulation time 231731944 ps
CPU time 0.96 seconds
Started May 12 03:01:54 PM PDT 24
Finished May 12 03:01:56 PM PDT 24
Peak memory 200664 kb
Host smart-329a1d8e-d0e1-4123-b48a-79050d6ce1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268089968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.268089968
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2051432819
Short name T340
Test name
Test status
Simulation time 1435294498 ps
CPU time 5.56 seconds
Started May 12 03:01:55 PM PDT 24
Finished May 12 03:02:01 PM PDT 24
Peak memory 201028 kb
Host smart-57a64312-12b3-42c2-afb2-dce777891aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051432819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2051432819
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3982851898
Short name T192
Test name
Test status
Simulation time 149397957 ps
CPU time 1.11 seconds
Started May 12 03:01:56 PM PDT 24
Finished May 12 03:01:58 PM PDT 24
Peak memory 200872 kb
Host smart-c2f87e9f-61f8-4cc2-9d71-e2c7ef3b267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982851898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3982851898
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1464641362
Short name T175
Test name
Test status
Simulation time 196495762 ps
CPU time 1.36 seconds
Started May 12 03:01:56 PM PDT 24
Finished May 12 03:01:58 PM PDT 24
Peak memory 201040 kb
Host smart-be1cffeb-2eb9-4a11-92a5-38b2ab3b3e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464641362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1464641362
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.153656706
Short name T391
Test name
Test status
Simulation time 12871134651 ps
CPU time 47.05 seconds
Started May 12 03:02:01 PM PDT 24
Finished May 12 03:02:49 PM PDT 24
Peak memory 201156 kb
Host smart-2f69267f-7097-48f2-9211-e4d9fd336595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153656706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.153656706
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1375783505
Short name T447
Test name
Test status
Simulation time 502900497 ps
CPU time 2.74 seconds
Started May 12 03:02:07 PM PDT 24
Finished May 12 03:02:10 PM PDT 24
Peak memory 200824 kb
Host smart-dfefe4e1-cc63-470e-9a8d-99f792ddaa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375783505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1375783505
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.4142662955
Short name T270
Test name
Test status
Simulation time 167455405 ps
CPU time 1.3 seconds
Started May 12 03:01:57 PM PDT 24
Finished May 12 03:01:59 PM PDT 24
Peak memory 201056 kb
Host smart-6a02175d-a7bc-45a9-95f6-b56457c0ffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142662955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.4142662955
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1798826764
Short name T529
Test name
Test status
Simulation time 62704115 ps
CPU time 0.8 seconds
Started May 12 03:02:06 PM PDT 24
Finished May 12 03:02:08 PM PDT 24
Peak memory 200680 kb
Host smart-b72ec269-b16d-4523-9cbb-d9c4be802091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798826764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1798826764
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.4085514700
Short name T38
Test name
Test status
Simulation time 1224119880 ps
CPU time 5.61 seconds
Started May 12 03:02:02 PM PDT 24
Finished May 12 03:02:08 PM PDT 24
Peak memory 218576 kb
Host smart-1154fed9-92ee-4ae6-b018-dafd41a2a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085514700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.4085514700
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4188604211
Short name T75
Test name
Test status
Simulation time 244397940 ps
CPU time 1.11 seconds
Started May 12 03:02:03 PM PDT 24
Finished May 12 03:02:05 PM PDT 24
Peak memory 217916 kb
Host smart-f450ecac-1f9e-40c5-b6a4-c2aea9f569aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188604211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4188604211
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2113844225
Short name T215
Test name
Test status
Simulation time 110566148 ps
CPU time 0.8 seconds
Started May 12 03:02:00 PM PDT 24
Finished May 12 03:02:01 PM PDT 24
Peak memory 200600 kb
Host smart-fe8bfa23-d354-420e-86bd-1e89fdcc7c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113844225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2113844225
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3004590642
Short name T443
Test name
Test status
Simulation time 1354997074 ps
CPU time 5.83 seconds
Started May 12 03:02:03 PM PDT 24
Finished May 12 03:02:09 PM PDT 24
Peak memory 200968 kb
Host smart-d19d239e-6d22-4951-895e-7db1a47be9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004590642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3004590642
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.4141995704
Short name T390
Test name
Test status
Simulation time 175695414 ps
CPU time 1.2 seconds
Started May 12 03:02:02 PM PDT 24
Finished May 12 03:02:04 PM PDT 24
Peak memory 200824 kb
Host smart-f175f749-2f6d-478a-8fe1-a33ffee4af83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141995704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.4141995704
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2365540282
Short name T262
Test name
Test status
Simulation time 192106416 ps
CPU time 1.43 seconds
Started May 12 03:02:06 PM PDT 24
Finished May 12 03:02:08 PM PDT 24
Peak memory 201012 kb
Host smart-0c58d33e-4a4d-4d69-a38a-552f5d8b670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365540282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2365540282
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1958886555
Short name T178
Test name
Test status
Simulation time 213236487 ps
CPU time 1.39 seconds
Started May 12 03:02:03 PM PDT 24
Finished May 12 03:02:05 PM PDT 24
Peak memory 201068 kb
Host smart-3e6e7d44-2d58-4b89-bdc9-d2d00d86c7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958886555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1958886555
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2992693016
Short name T306
Test name
Test status
Simulation time 118814026 ps
CPU time 1.43 seconds
Started May 12 03:02:06 PM PDT 24
Finished May 12 03:02:08 PM PDT 24
Peak memory 200860 kb
Host smart-3455511e-2837-4615-85a4-9a16a234715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992693016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2992693016
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1816782637
Short name T98
Test name
Test status
Simulation time 198939642 ps
CPU time 1.31 seconds
Started May 12 03:02:04 PM PDT 24
Finished May 12 03:02:05 PM PDT 24
Peak memory 200868 kb
Host smart-76e1c9a2-891e-46aa-9be0-404e900915de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816782637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1816782637
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1102618388
Short name T223
Test name
Test status
Simulation time 66317131 ps
CPU time 0.81 seconds
Started May 12 03:02:10 PM PDT 24
Finished May 12 03:02:11 PM PDT 24
Peak memory 200696 kb
Host smart-27819bff-c837-4fc1-b577-c3c4d185c754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102618388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1102618388
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1489375539
Short name T33
Test name
Test status
Simulation time 1894175411 ps
CPU time 8.64 seconds
Started May 12 03:02:07 PM PDT 24
Finished May 12 03:02:16 PM PDT 24
Peak memory 218488 kb
Host smart-9d0080c3-8699-47ce-91bd-876c6f324d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489375539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1489375539
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1978643266
Short name T374
Test name
Test status
Simulation time 243273154 ps
CPU time 1.09 seconds
Started May 12 03:02:10 PM PDT 24
Finished May 12 03:02:12 PM PDT 24
Peak memory 218184 kb
Host smart-1d53cfb6-6b07-48a9-8c13-7e4c22ddb9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978643266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1978643266
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3798003323
Short name T494
Test name
Test status
Simulation time 145029040 ps
CPU time 0.83 seconds
Started May 12 03:02:06 PM PDT 24
Finished May 12 03:02:08 PM PDT 24
Peak memory 200660 kb
Host smart-0011a561-9bc0-431b-81d0-d635d0fd3823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798003323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3798003323
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3081207222
Short name T91
Test name
Test status
Simulation time 1537077994 ps
CPU time 6.03 seconds
Started May 12 03:02:08 PM PDT 24
Finished May 12 03:02:15 PM PDT 24
Peak memory 201100 kb
Host smart-ee24c724-639d-48a7-8f8b-825b2473c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081207222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3081207222
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.536203222
Short name T408
Test name
Test status
Simulation time 100746715 ps
CPU time 0.95 seconds
Started May 12 03:02:06 PM PDT 24
Finished May 12 03:02:07 PM PDT 24
Peak memory 200876 kb
Host smart-f9ea3734-2072-4719-b5b8-8749a45ecbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536203222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.536203222
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1499877384
Short name T71
Test name
Test status
Simulation time 123412198 ps
CPU time 1.2 seconds
Started May 12 03:02:05 PM PDT 24
Finished May 12 03:02:07 PM PDT 24
Peak memory 201024 kb
Host smart-2a3cacea-1a61-4ea8-bc1a-67764a2c3ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499877384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1499877384
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2249287228
Short name T477
Test name
Test status
Simulation time 8660232718 ps
CPU time 31.13 seconds
Started May 12 03:02:12 PM PDT 24
Finished May 12 03:02:43 PM PDT 24
Peak memory 217472 kb
Host smart-ebbc1634-3011-47b0-a0cc-503f46119a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249287228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2249287228
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2054813420
Short name T210
Test name
Test status
Simulation time 124986699 ps
CPU time 1.67 seconds
Started May 12 03:02:09 PM PDT 24
Finished May 12 03:02:11 PM PDT 24
Peak memory 209092 kb
Host smart-afe5872e-219b-4113-b8f1-51235b50af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054813420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2054813420
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4034993650
Short name T520
Test name
Test status
Simulation time 100899619 ps
CPU time 0.89 seconds
Started May 12 03:02:08 PM PDT 24
Finished May 12 03:02:09 PM PDT 24
Peak memory 200828 kb
Host smart-9aee64fa-ec81-4488-8a6a-5d5bf962e42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034993650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4034993650
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.170171960
Short name T10
Test name
Test status
Simulation time 67032011 ps
CPU time 0.77 seconds
Started May 12 03:02:17 PM PDT 24
Finished May 12 03:02:18 PM PDT 24
Peak memory 200676 kb
Host smart-babbb2e5-055b-4b2e-aa3b-67d6e07dd430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170171960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.170171960
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2039882097
Short name T349
Test name
Test status
Simulation time 2172914803 ps
CPU time 7.65 seconds
Started May 12 03:02:15 PM PDT 24
Finished May 12 03:02:23 PM PDT 24
Peak memory 221556 kb
Host smart-c24ab9d5-b254-4b74-a5c4-5a13502522cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039882097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2039882097
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3525713130
Short name T179
Test name
Test status
Simulation time 244654059 ps
CPU time 1.15 seconds
Started May 12 03:02:13 PM PDT 24
Finished May 12 03:02:14 PM PDT 24
Peak memory 218012 kb
Host smart-ee36da44-e830-4fbf-8356-bafc89fcbb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525713130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3525713130
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3343985491
Short name T20
Test name
Test status
Simulation time 252243567 ps
CPU time 0.95 seconds
Started May 12 03:02:11 PM PDT 24
Finished May 12 03:02:13 PM PDT 24
Peak memory 200596 kb
Host smart-bf21f471-1019-4958-91b3-21328034748e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343985491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3343985491
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3552287510
Short name T278
Test name
Test status
Simulation time 1629125554 ps
CPU time 6.43 seconds
Started May 12 03:02:09 PM PDT 24
Finished May 12 03:02:16 PM PDT 24
Peak memory 201060 kb
Host smart-29058e43-92fb-4a02-a3f2-7b9a49ba80b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552287510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3552287510
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2404315936
Short name T444
Test name
Test status
Simulation time 113360529 ps
CPU time 1.06 seconds
Started May 12 03:02:14 PM PDT 24
Finished May 12 03:02:16 PM PDT 24
Peak memory 200844 kb
Host smart-e41ea47d-110e-4e59-a2cd-5cd7cc8754fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404315936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2404315936
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.344500645
Short name T193
Test name
Test status
Simulation time 261833536 ps
CPU time 1.52 seconds
Started May 12 03:02:10 PM PDT 24
Finished May 12 03:02:12 PM PDT 24
Peak memory 201020 kb
Host smart-989ce88f-ffd7-4444-a0ca-9476ae54df52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344500645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.344500645
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1858239231
Short name T154
Test name
Test status
Simulation time 367779579 ps
CPU time 1.95 seconds
Started May 12 03:02:16 PM PDT 24
Finished May 12 03:02:18 PM PDT 24
Peak memory 201124 kb
Host smart-34048074-f776-40e4-a874-c1156107b767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858239231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1858239231
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3715011858
Short name T301
Test name
Test status
Simulation time 140026426 ps
CPU time 1.94 seconds
Started May 12 03:02:17 PM PDT 24
Finished May 12 03:02:19 PM PDT 24
Peak memory 200820 kb
Host smart-f24371d2-7d3c-4ada-b813-de9762cae0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715011858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3715011858
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.679177820
Short name T292
Test name
Test status
Simulation time 63150691 ps
CPU time 0.81 seconds
Started May 12 03:02:10 PM PDT 24
Finished May 12 03:02:12 PM PDT 24
Peak memory 200860 kb
Host smart-a6ffc21c-2a25-4e74-9cfb-5c12213b937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679177820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.679177820
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3511426975
Short name T273
Test name
Test status
Simulation time 63290157 ps
CPU time 0.77 seconds
Started May 12 03:02:13 PM PDT 24
Finished May 12 03:02:14 PM PDT 24
Peak memory 200720 kb
Host smart-9121acda-54c9-4429-9625-4a3146e4bdeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511426975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3511426975
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.123188327
Short name T45
Test name
Test status
Simulation time 2367134463 ps
CPU time 9 seconds
Started May 12 03:02:12 PM PDT 24
Finished May 12 03:02:21 PM PDT 24
Peak memory 218536 kb
Host smart-ea3c804b-2d52-4750-9c5b-2052c9f6d69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123188327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.123188327
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3400385395
Short name T286
Test name
Test status
Simulation time 244822728 ps
CPU time 1.03 seconds
Started May 12 03:02:14 PM PDT 24
Finished May 12 03:02:16 PM PDT 24
Peak memory 217968 kb
Host smart-99cf39c4-781f-4339-bd71-7a1678161f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400385395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3400385395
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.306052116
Short name T462
Test name
Test status
Simulation time 234250256 ps
CPU time 0.94 seconds
Started May 12 03:02:13 PM PDT 24
Finished May 12 03:02:14 PM PDT 24
Peak memory 200676 kb
Host smart-cc37bd91-4d61-4333-ad77-85273997bb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306052116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.306052116
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1501970324
Short name T208
Test name
Test status
Simulation time 1990012713 ps
CPU time 7.77 seconds
Started May 12 03:02:12 PM PDT 24
Finished May 12 03:02:20 PM PDT 24
Peak memory 201004 kb
Host smart-a404bf73-e6f6-420e-91d7-c3983e0ca7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501970324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1501970324
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.662821032
Short name T289
Test name
Test status
Simulation time 104617384 ps
CPU time 0.96 seconds
Started May 12 03:02:15 PM PDT 24
Finished May 12 03:02:17 PM PDT 24
Peak memory 200904 kb
Host smart-24cdef69-cf48-4b6a-bae5-28f9e0cea094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662821032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.662821032
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3144688571
Short name T338
Test name
Test status
Simulation time 233074003 ps
CPU time 1.5 seconds
Started May 12 03:02:14 PM PDT 24
Finished May 12 03:02:16 PM PDT 24
Peak memory 200976 kb
Host smart-31b4b4d0-5dc9-445e-9af1-516dfac6f52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144688571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3144688571
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.527316274
Short name T419
Test name
Test status
Simulation time 6689925163 ps
CPU time 26.11 seconds
Started May 12 03:02:13 PM PDT 24
Finished May 12 03:02:40 PM PDT 24
Peak memory 201188 kb
Host smart-1f6642f2-980c-4394-835e-fd9d82ebd72f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527316274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.527316274
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2519841673
Short name T538
Test name
Test status
Simulation time 132569718 ps
CPU time 1.62 seconds
Started May 12 03:02:14 PM PDT 24
Finished May 12 03:02:16 PM PDT 24
Peak memory 209068 kb
Host smart-5ca2344f-4db8-4598-8cfa-c9b68884203f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519841673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2519841673
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3848842786
Short name T356
Test name
Test status
Simulation time 219164071 ps
CPU time 1.46 seconds
Started May 12 03:02:13 PM PDT 24
Finished May 12 03:02:15 PM PDT 24
Peak memory 200888 kb
Host smart-beb44cd4-5839-4c5d-be72-994a570d81ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848842786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3848842786
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1554567861
Short name T539
Test name
Test status
Simulation time 89943859 ps
CPU time 0.91 seconds
Started May 12 03:02:23 PM PDT 24
Finished May 12 03:02:25 PM PDT 24
Peak memory 200704 kb
Host smart-a7a91a40-b6fa-4764-a77b-d55cb72007f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554567861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1554567861
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2229959337
Short name T316
Test name
Test status
Simulation time 2357762092 ps
CPU time 9.39 seconds
Started May 12 03:02:19 PM PDT 24
Finished May 12 03:02:28 PM PDT 24
Peak memory 218620 kb
Host smart-bc61d2e1-89a5-4679-a430-3e9cf4a096be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229959337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2229959337
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3383033737
Short name T362
Test name
Test status
Simulation time 244204706 ps
CPU time 1.06 seconds
Started May 12 03:02:22 PM PDT 24
Finished May 12 03:02:24 PM PDT 24
Peak memory 218012 kb
Host smart-32e88b2a-d05b-4f0d-8868-ee0697d17c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383033737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3383033737
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3495229018
Short name T200
Test name
Test status
Simulation time 79495808 ps
CPU time 0.73 seconds
Started May 12 03:02:18 PM PDT 24
Finished May 12 03:02:19 PM PDT 24
Peak memory 200652 kb
Host smart-21556a37-37cf-4443-b406-c1d4eb3d6b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495229018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3495229018
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2171155401
Short name T310
Test name
Test status
Simulation time 696320067 ps
CPU time 3.94 seconds
Started May 12 03:02:23 PM PDT 24
Finished May 12 03:02:28 PM PDT 24
Peak memory 201016 kb
Host smart-4350621a-418a-4695-95ca-1c48674240b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171155401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2171155401
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.4094005855
Short name T269
Test name
Test status
Simulation time 152322321 ps
CPU time 1.19 seconds
Started May 12 03:02:20 PM PDT 24
Finished May 12 03:02:21 PM PDT 24
Peak memory 200868 kb
Host smart-d98b1dea-3bb4-420b-a2e2-976aede11fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094005855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.4094005855
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4125043560
Short name T135
Test name
Test status
Simulation time 125619985 ps
CPU time 1.24 seconds
Started May 12 03:02:17 PM PDT 24
Finished May 12 03:02:19 PM PDT 24
Peak memory 201016 kb
Host smart-2d0f94ae-0500-47ad-b3f1-08a9d1334458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125043560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4125043560
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3107916144
Short name T321
Test name
Test status
Simulation time 1495741499 ps
CPU time 6.47 seconds
Started May 12 03:02:20 PM PDT 24
Finished May 12 03:02:27 PM PDT 24
Peak memory 201008 kb
Host smart-8f66bfcd-c9e4-4bfa-9223-9ce3539973a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107916144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3107916144
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4037117285
Short name T478
Test name
Test status
Simulation time 481820397 ps
CPU time 2.83 seconds
Started May 12 03:02:25 PM PDT 24
Finished May 12 03:02:28 PM PDT 24
Peak memory 200856 kb
Host smart-85ddeb12-b226-461d-9a59-95f72a790838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037117285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4037117285
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1495691161
Short name T214
Test name
Test status
Simulation time 82284396 ps
CPU time 0.87 seconds
Started May 12 03:02:16 PM PDT 24
Finished May 12 03:02:17 PM PDT 24
Peak memory 200804 kb
Host smart-80dbd089-2232-4daf-be50-727f8dc7082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495691161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1495691161
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3457068159
Short name T132
Test name
Test status
Simulation time 75733587 ps
CPU time 0.75 seconds
Started May 12 03:02:23 PM PDT 24
Finished May 12 03:02:25 PM PDT 24
Peak memory 200728 kb
Host smart-6b08a8c9-9e24-4a4f-817a-797e25290614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457068159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3457068159
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3054523233
Short name T311
Test name
Test status
Simulation time 2185806503 ps
CPU time 8.6 seconds
Started May 12 03:02:23 PM PDT 24
Finished May 12 03:02:32 PM PDT 24
Peak memory 222768 kb
Host smart-20a32cb8-8a00-4b7a-95da-767d505cc707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054523233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3054523233
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.4283371163
Short name T281
Test name
Test status
Simulation time 244319303 ps
CPU time 1.12 seconds
Started May 12 03:02:23 PM PDT 24
Finished May 12 03:02:25 PM PDT 24
Peak memory 218088 kb
Host smart-1ae1bef4-c456-4300-a342-12c5412c2cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283371163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.4283371163
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4038652678
Short name T339
Test name
Test status
Simulation time 199615761 ps
CPU time 1.01 seconds
Started May 12 03:02:24 PM PDT 24
Finished May 12 03:02:25 PM PDT 24
Peak memory 200680 kb
Host smart-cc4d5e9f-eab4-4eb5-abfd-a469fbc6d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038652678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4038652678
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3700363577
Short name T198
Test name
Test status
Simulation time 960456104 ps
CPU time 4.6 seconds
Started May 12 03:02:23 PM PDT 24
Finished May 12 03:02:28 PM PDT 24
Peak memory 201000 kb
Host smart-a4b02539-d6c0-47d2-afc2-e8e03dfdd348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700363577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3700363577
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4043004869
Short name T285
Test name
Test status
Simulation time 164117956 ps
CPU time 1.2 seconds
Started May 12 03:02:23 PM PDT 24
Finished May 12 03:02:25 PM PDT 24
Peak memory 200872 kb
Host smart-e95866d9-3152-41bc-80c1-1d322fba1d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043004869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4043004869
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2792899754
Short name T503
Test name
Test status
Simulation time 190162861 ps
CPU time 1.4 seconds
Started May 12 03:02:26 PM PDT 24
Finished May 12 03:02:28 PM PDT 24
Peak memory 200944 kb
Host smart-49a943f6-9560-4dcb-ade9-010867d9b2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792899754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2792899754
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1459535889
Short name T102
Test name
Test status
Simulation time 6258460699 ps
CPU time 24 seconds
Started May 12 03:02:26 PM PDT 24
Finished May 12 03:02:50 PM PDT 24
Peak memory 201084 kb
Host smart-20f743c4-49c5-401a-9d64-66373fde14b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459535889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1459535889
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.439121324
Short name T385
Test name
Test status
Simulation time 312698804 ps
CPU time 2.05 seconds
Started May 12 03:02:23 PM PDT 24
Finished May 12 03:02:26 PM PDT 24
Peak memory 200852 kb
Host smart-f7465a84-f511-4662-bf4c-275101ed6d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439121324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.439121324
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4172533159
Short name T414
Test name
Test status
Simulation time 147413496 ps
CPU time 1.29 seconds
Started May 12 03:02:24 PM PDT 24
Finished May 12 03:02:25 PM PDT 24
Peak memory 200792 kb
Host smart-38c8fe51-5c7b-4d69-bd77-ae5e69e3bb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172533159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4172533159
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2430118722
Short name T280
Test name
Test status
Simulation time 84815863 ps
CPU time 0.88 seconds
Started May 12 03:02:30 PM PDT 24
Finished May 12 03:02:31 PM PDT 24
Peak memory 200676 kb
Host smart-ce33e0ad-7e14-4370-b1c4-41f21ebc7a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430118722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2430118722
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3288757986
Short name T400
Test name
Test status
Simulation time 2355042449 ps
CPU time 9.04 seconds
Started May 12 03:02:28 PM PDT 24
Finished May 12 03:02:37 PM PDT 24
Peak memory 230876 kb
Host smart-002ea0c0-7a94-4a9d-80b4-7a4af73841c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288757986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3288757986
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.717726608
Short name T80
Test name
Test status
Simulation time 244066663 ps
CPU time 1.14 seconds
Started May 12 03:02:30 PM PDT 24
Finished May 12 03:02:32 PM PDT 24
Peak memory 217968 kb
Host smart-6c75ee8d-3c55-4ee5-af93-e2087d630dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717726608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.717726608
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1421631729
Short name T190
Test name
Test status
Simulation time 92249342 ps
CPU time 0.75 seconds
Started May 12 03:02:26 PM PDT 24
Finished May 12 03:02:27 PM PDT 24
Peak memory 200648 kb
Host smart-245b9ae2-ca37-403a-8c38-c45f589bbeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421631729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1421631729
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.294146073
Short name T531
Test name
Test status
Simulation time 677116172 ps
CPU time 3.74 seconds
Started May 12 03:02:26 PM PDT 24
Finished May 12 03:02:30 PM PDT 24
Peak memory 201024 kb
Host smart-127ac7b0-164f-4f4d-b966-db059b29bb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294146073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.294146073
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1979308050
Short name T315
Test name
Test status
Simulation time 121238407 ps
CPU time 1.26 seconds
Started May 12 03:02:28 PM PDT 24
Finished May 12 03:02:29 PM PDT 24
Peak memory 201048 kb
Host smart-3d867abb-e2eb-48bc-9cf9-9f6165670f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979308050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1979308050
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3460926613
Short name T100
Test name
Test status
Simulation time 4981606835 ps
CPU time 22.9 seconds
Started May 12 03:02:29 PM PDT 24
Finished May 12 03:02:53 PM PDT 24
Peak memory 209352 kb
Host smart-750afb15-335a-4a55-958d-258a31e6f562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460926613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3460926613
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.533244328
Short name T382
Test name
Test status
Simulation time 116413096 ps
CPU time 1.66 seconds
Started May 12 03:02:25 PM PDT 24
Finished May 12 03:02:27 PM PDT 24
Peak memory 200804 kb
Host smart-93781c86-fcc7-4278-8249-3f1db350f9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533244328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.533244328
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.757071083
Short name T160
Test name
Test status
Simulation time 173412764 ps
CPU time 1.2 seconds
Started May 12 03:02:26 PM PDT 24
Finished May 12 03:02:27 PM PDT 24
Peak memory 201064 kb
Host smart-71000cc6-1b0c-4a7d-b177-93eee137efc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757071083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.757071083
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3131363032
Short name T166
Test name
Test status
Simulation time 62859963 ps
CPU time 0.73 seconds
Started May 12 03:02:32 PM PDT 24
Finished May 12 03:02:33 PM PDT 24
Peak memory 200704 kb
Host smart-01472c4f-bd0f-4025-83a9-e8519afc639c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131363032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3131363032
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.900322665
Short name T490
Test name
Test status
Simulation time 2373499667 ps
CPU time 8.1 seconds
Started May 12 03:02:34 PM PDT 24
Finished May 12 03:02:42 PM PDT 24
Peak memory 218336 kb
Host smart-f77240ee-f28e-4732-ab5a-c4e0b17f9ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900322665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.900322665
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3105794255
Short name T461
Test name
Test status
Simulation time 244951265 ps
CPU time 1.04 seconds
Started May 12 03:02:34 PM PDT 24
Finished May 12 03:02:36 PM PDT 24
Peak memory 218132 kb
Host smart-13a7f137-a3f0-4edb-bcf9-2eab56766b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105794255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3105794255
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2959718735
Short name T17
Test name
Test status
Simulation time 157608346 ps
CPU time 0.81 seconds
Started May 12 03:02:30 PM PDT 24
Finished May 12 03:02:31 PM PDT 24
Peak memory 200656 kb
Host smart-1bc92dbb-2d11-4527-918a-25cb11c10ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959718735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2959718735
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3104851221
Short name T371
Test name
Test status
Simulation time 1329509576 ps
CPU time 5.95 seconds
Started May 12 03:02:30 PM PDT 24
Finished May 12 03:02:37 PM PDT 24
Peak memory 201184 kb
Host smart-e18f6b86-074a-4d5d-affd-9063515341af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104851221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3104851221
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1125625626
Short name T48
Test name
Test status
Simulation time 149830448 ps
CPU time 1.14 seconds
Started May 12 03:02:32 PM PDT 24
Finished May 12 03:02:34 PM PDT 24
Peak memory 200876 kb
Host smart-97b5d9f7-1d9b-4290-99d0-522aedcc1349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125625626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1125625626
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.288069338
Short name T155
Test name
Test status
Simulation time 232236147 ps
CPU time 1.48 seconds
Started May 12 03:02:30 PM PDT 24
Finished May 12 03:02:32 PM PDT 24
Peak memory 201020 kb
Host smart-b6ec2a01-e522-4467-89b6-5e0bfb321fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288069338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.288069338
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1117166786
Short name T403
Test name
Test status
Simulation time 1770293330 ps
CPU time 8.21 seconds
Started May 12 03:02:35 PM PDT 24
Finished May 12 03:02:44 PM PDT 24
Peak memory 201080 kb
Host smart-4c2123f8-784b-45ee-a226-49a9a6e73e6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117166786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1117166786
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.412236375
Short name T359
Test name
Test status
Simulation time 488778088 ps
CPU time 2.84 seconds
Started May 12 03:02:29 PM PDT 24
Finished May 12 03:02:32 PM PDT 24
Peak memory 209040 kb
Host smart-4b3d7db0-b887-4228-ac35-2b049550f58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412236375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.412236375
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.396446390
Short name T430
Test name
Test status
Simulation time 153238093 ps
CPU time 1.13 seconds
Started May 12 03:02:29 PM PDT 24
Finished May 12 03:02:31 PM PDT 24
Peak memory 200796 kb
Host smart-e0b627ac-5ac5-480e-95ad-3fdae348d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396446390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.396446390
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3155119040
Short name T377
Test name
Test status
Simulation time 55581633 ps
CPU time 0.7 seconds
Started May 12 03:01:11 PM PDT 24
Finished May 12 03:01:12 PM PDT 24
Peak memory 200628 kb
Host smart-b4545a0e-ed89-475d-9bfb-bffded49e8d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155119040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3155119040
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1376794264
Short name T271
Test name
Test status
Simulation time 1895411105 ps
CPU time 7.05 seconds
Started May 12 03:01:07 PM PDT 24
Finished May 12 03:01:15 PM PDT 24
Peak memory 222048 kb
Host smart-3e497a2c-2308-49da-a3b9-4ebd87e968e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376794264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1376794264
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3260409104
Short name T397
Test name
Test status
Simulation time 244110037 ps
CPU time 1.13 seconds
Started May 12 03:01:08 PM PDT 24
Finished May 12 03:01:09 PM PDT 24
Peak memory 218008 kb
Host smart-f58f3377-0251-4891-a585-d922cfdc1dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260409104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3260409104
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1685508372
Short name T435
Test name
Test status
Simulation time 101499560 ps
CPU time 0.78 seconds
Started May 12 03:01:05 PM PDT 24
Finished May 12 03:01:07 PM PDT 24
Peak memory 200612 kb
Host smart-ffc22b35-0f1d-4ad0-9c21-d992cddef8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685508372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1685508372
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.688332427
Short name T332
Test name
Test status
Simulation time 1529868120 ps
CPU time 6.11 seconds
Started May 12 03:01:05 PM PDT 24
Finished May 12 03:01:11 PM PDT 24
Peak memory 201032 kb
Host smart-d7349a59-98d5-421f-a743-5a2617c47ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688332427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.688332427
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.272121294
Short name T68
Test name
Test status
Simulation time 8427148716 ps
CPU time 12.75 seconds
Started May 12 03:01:13 PM PDT 24
Finished May 12 03:01:27 PM PDT 24
Peak memory 217576 kb
Host smart-86fe4834-7ec7-404d-9a01-32d73334d424
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272121294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.272121294
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3852187619
Short name T379
Test name
Test status
Simulation time 148666533 ps
CPU time 1.2 seconds
Started May 12 03:01:08 PM PDT 24
Finished May 12 03:01:10 PM PDT 24
Peak memory 201008 kb
Host smart-a7cde1cf-cf73-4452-ab70-6486cd5bbebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852187619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3852187619
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2248244201
Short name T357
Test name
Test status
Simulation time 251283890 ps
CPU time 1.61 seconds
Started May 12 03:01:04 PM PDT 24
Finished May 12 03:01:06 PM PDT 24
Peak memory 201044 kb
Host smart-b7204d6c-247a-407f-aaff-490ece0ed037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248244201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2248244201
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.439186450
Short name T161
Test name
Test status
Simulation time 2581752489 ps
CPU time 9.8 seconds
Started May 12 03:01:08 PM PDT 24
Finished May 12 03:01:19 PM PDT 24
Peak memory 201120 kb
Host smart-4b7b1bd2-36de-4a29-ad06-1ac062fe5019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439186450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.439186450
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2184964992
Short name T26
Test name
Test status
Simulation time 116908463 ps
CPU time 1.57 seconds
Started May 12 03:01:05 PM PDT 24
Finished May 12 03:01:07 PM PDT 24
Peak memory 200808 kb
Host smart-cb0fa57b-c776-4f2d-abe8-c5c4dbc75e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184964992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2184964992
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1257734581
Short name T294
Test name
Test status
Simulation time 106533167 ps
CPU time 0.91 seconds
Started May 12 03:01:05 PM PDT 24
Finished May 12 03:01:06 PM PDT 24
Peak memory 200892 kb
Host smart-7ef6f902-f856-4613-9eab-dc7911cde2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257734581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1257734581
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.424237158
Short name T149
Test name
Test status
Simulation time 61207542 ps
CPU time 0.77 seconds
Started May 12 03:02:38 PM PDT 24
Finished May 12 03:02:39 PM PDT 24
Peak memory 200648 kb
Host smart-99dc3455-abd6-414c-82af-83eca2983a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424237158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.424237158
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1934103423
Short name T424
Test name
Test status
Simulation time 1889678460 ps
CPU time 7.12 seconds
Started May 12 03:02:36 PM PDT 24
Finished May 12 03:02:44 PM PDT 24
Peak memory 222092 kb
Host smart-a5225371-314a-474f-bb0e-98fd68f70b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934103423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1934103423
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.4166361549
Short name T54
Test name
Test status
Simulation time 244370974 ps
CPU time 1.09 seconds
Started May 12 03:02:37 PM PDT 24
Finished May 12 03:02:38 PM PDT 24
Peak memory 218028 kb
Host smart-ab00a571-8237-44aa-afcc-fc22fb3988ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166361549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.4166361549
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2423769455
Short name T358
Test name
Test status
Simulation time 206827743 ps
CPU time 0.9 seconds
Started May 12 03:02:32 PM PDT 24
Finished May 12 03:02:33 PM PDT 24
Peak memory 200688 kb
Host smart-c7d02603-7ca2-4614-b14b-12cddd252666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423769455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2423769455
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3143937902
Short name T422
Test name
Test status
Simulation time 1738253574 ps
CPU time 6.57 seconds
Started May 12 03:02:34 PM PDT 24
Finished May 12 03:02:41 PM PDT 24
Peak memory 201080 kb
Host smart-71ad8157-7c67-4293-8f62-0e27476997f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143937902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3143937902
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4214148591
Short name T284
Test name
Test status
Simulation time 114525170 ps
CPU time 1.02 seconds
Started May 12 03:02:37 PM PDT 24
Finished May 12 03:02:39 PM PDT 24
Peak memory 201068 kb
Host smart-72b6ba9c-cfe8-4446-af37-cb0f5963d830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214148591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4214148591
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2813151071
Short name T440
Test name
Test status
Simulation time 226748050 ps
CPU time 1.52 seconds
Started May 12 03:02:34 PM PDT 24
Finished May 12 03:02:36 PM PDT 24
Peak memory 201076 kb
Host smart-87d9be10-031e-494c-bad2-e8dcabb094ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813151071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2813151071
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1605865659
Short name T187
Test name
Test status
Simulation time 271360693 ps
CPU time 1.98 seconds
Started May 12 03:02:38 PM PDT 24
Finished May 12 03:02:41 PM PDT 24
Peak memory 200852 kb
Host smart-a68ba0be-cf64-4fc4-9d4a-ebb4b94bffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605865659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1605865659
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2484181795
Short name T234
Test name
Test status
Simulation time 159982755 ps
CPU time 1.11 seconds
Started May 12 03:02:37 PM PDT 24
Finished May 12 03:02:39 PM PDT 24
Peak memory 200796 kb
Host smart-01044cf6-dc86-4512-8adc-460eb03fbd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484181795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2484181795
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1836829519
Short name T360
Test name
Test status
Simulation time 100064382 ps
CPU time 0.87 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:42 PM PDT 24
Peak memory 200720 kb
Host smart-04670bdc-989e-4e65-8491-3c13245e8fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836829519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1836829519
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1989042583
Short name T11
Test name
Test status
Simulation time 1891089947 ps
CPU time 7.66 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:49 PM PDT 24
Peak memory 218500 kb
Host smart-a03e2586-9e9e-4073-9be5-5655620ea860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989042583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1989042583
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3891025971
Short name T211
Test name
Test status
Simulation time 244777311 ps
CPU time 1.12 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:43 PM PDT 24
Peak memory 218056 kb
Host smart-dd5fec7b-e095-4a2b-a33c-d0e82590dcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891025971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3891025971
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.432077829
Short name T19
Test name
Test status
Simulation time 90623349 ps
CPU time 0.76 seconds
Started May 12 03:02:36 PM PDT 24
Finished May 12 03:02:37 PM PDT 24
Peak memory 200616 kb
Host smart-999b77e3-a8b5-4884-859a-e334cc98f457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432077829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.432077829
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.4137347481
Short name T265
Test name
Test status
Simulation time 930831265 ps
CPU time 4.5 seconds
Started May 12 03:02:38 PM PDT 24
Finished May 12 03:02:43 PM PDT 24
Peak memory 201028 kb
Host smart-3954899c-1405-43ca-940c-bb88ca9f21d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137347481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4137347481
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4276393231
Short name T143
Test name
Test status
Simulation time 144234219 ps
CPU time 1.16 seconds
Started May 12 03:02:42 PM PDT 24
Finished May 12 03:02:44 PM PDT 24
Peak memory 200840 kb
Host smart-fd44d023-1860-46fe-a15f-57397b5f15fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276393231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4276393231
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2701447995
Short name T185
Test name
Test status
Simulation time 201027926 ps
CPU time 1.56 seconds
Started May 12 03:02:37 PM PDT 24
Finished May 12 03:02:38 PM PDT 24
Peak memory 201032 kb
Host smart-14ccf4a1-d0be-4b19-8d71-0206cf43df76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701447995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2701447995
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2010906609
Short name T30
Test name
Test status
Simulation time 567448315 ps
CPU time 2.8 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:44 PM PDT 24
Peak memory 201040 kb
Host smart-af05e39c-ca10-4d37-9822-782298301e6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010906609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2010906609
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2964687193
Short name T537
Test name
Test status
Simulation time 281452688 ps
CPU time 1.84 seconds
Started May 12 03:02:39 PM PDT 24
Finished May 12 03:02:41 PM PDT 24
Peak memory 200808 kb
Host smart-73caf57f-e980-4f14-9c0a-7de11eb0d521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964687193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2964687193
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3344077022
Short name T260
Test name
Test status
Simulation time 79037233 ps
CPU time 0.83 seconds
Started May 12 03:02:39 PM PDT 24
Finished May 12 03:02:40 PM PDT 24
Peak memory 200876 kb
Host smart-d39a57b6-b08d-4202-b430-091de26892af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344077022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3344077022
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.4099414025
Short name T204
Test name
Test status
Simulation time 104242621 ps
CPU time 0.83 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:42 PM PDT 24
Peak memory 200676 kb
Host smart-ec5397af-9797-46b0-bea4-f4a7755f9310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099414025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.4099414025
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1650279709
Short name T236
Test name
Test status
Simulation time 1234631822 ps
CPU time 5.37 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:47 PM PDT 24
Peak memory 218472 kb
Host smart-78e45de7-61d7-467b-bd5b-807e8b178858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650279709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1650279709
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2794476094
Short name T522
Test name
Test status
Simulation time 245286762 ps
CPU time 1.09 seconds
Started May 12 03:02:43 PM PDT 24
Finished May 12 03:02:45 PM PDT 24
Peak memory 218152 kb
Host smart-36b3303b-f912-45cb-81c8-207ee4b6398a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794476094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2794476094
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2636030581
Short name T23
Test name
Test status
Simulation time 201612008 ps
CPU time 0.98 seconds
Started May 12 03:02:46 PM PDT 24
Finished May 12 03:02:47 PM PDT 24
Peak memory 200624 kb
Host smart-d54a048e-9c62-489c-ac0e-bc0a2c15fbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636030581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2636030581
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2944494712
Short name T194
Test name
Test status
Simulation time 1020629844 ps
CPU time 4.95 seconds
Started May 12 03:02:43 PM PDT 24
Finished May 12 03:02:48 PM PDT 24
Peak memory 201048 kb
Host smart-2939bbfb-e01e-49ac-ad69-6d82ad4f1198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944494712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2944494712
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1068610458
Short name T469
Test name
Test status
Simulation time 144816409 ps
CPU time 1.11 seconds
Started May 12 03:02:42 PM PDT 24
Finished May 12 03:02:43 PM PDT 24
Peak memory 200852 kb
Host smart-445badfb-e4be-4bdd-a1ef-29e2d375c824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068610458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1068610458
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.189774963
Short name T427
Test name
Test status
Simulation time 195284931 ps
CPU time 1.44 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:43 PM PDT 24
Peak memory 200952 kb
Host smart-e4f910f7-25fc-430c-a946-601901bc1b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189774963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.189774963
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3167409096
Short name T243
Test name
Test status
Simulation time 3790390738 ps
CPU time 18.3 seconds
Started May 12 03:02:45 PM PDT 24
Finished May 12 03:03:04 PM PDT 24
Peak memory 209332 kb
Host smart-61ee6c50-dedb-406b-9067-8f466c0ef982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167409096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3167409096
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1022593711
Short name T384
Test name
Test status
Simulation time 420035458 ps
CPU time 2.31 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:44 PM PDT 24
Peak memory 209256 kb
Host smart-5b19e20c-8ad8-4e7c-b387-ccf5c1f4f4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022593711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1022593711
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3223856592
Short name T345
Test name
Test status
Simulation time 151247983 ps
CPU time 1.26 seconds
Started May 12 03:02:40 PM PDT 24
Finished May 12 03:02:41 PM PDT 24
Peak memory 200872 kb
Host smart-c6f82597-5d92-43bb-8488-49e61b4ceb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223856592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3223856592
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.4063960502
Short name T170
Test name
Test status
Simulation time 63407694 ps
CPU time 0.77 seconds
Started May 12 03:02:44 PM PDT 24
Finished May 12 03:02:45 PM PDT 24
Peak memory 200712 kb
Host smart-775022e9-ab7e-4832-9773-8bd701207c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063960502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.4063960502
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3374009953
Short name T458
Test name
Test status
Simulation time 2180333470 ps
CPU time 8.41 seconds
Started May 12 03:02:43 PM PDT 24
Finished May 12 03:02:52 PM PDT 24
Peak memory 218616 kb
Host smart-f718e18e-36f3-417f-8f72-738ec5eb0a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374009953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3374009953
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1832749144
Short name T485
Test name
Test status
Simulation time 243404469 ps
CPU time 1.16 seconds
Started May 12 03:02:45 PM PDT 24
Finished May 12 03:02:46 PM PDT 24
Peak memory 218112 kb
Host smart-2a04433e-29a9-481b-a823-b22d2a6d69aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832749144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1832749144
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2814112233
Short name T376
Test name
Test status
Simulation time 128192705 ps
CPU time 0.79 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:43 PM PDT 24
Peak memory 200588 kb
Host smart-a9236f18-ff1a-4a19-8fb9-bd446693e67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814112233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2814112233
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3886239111
Short name T256
Test name
Test status
Simulation time 938156849 ps
CPU time 4.53 seconds
Started May 12 03:02:41 PM PDT 24
Finished May 12 03:02:47 PM PDT 24
Peak memory 200940 kb
Host smart-d4e0f4bd-bc07-4a78-9cc5-1a2203d65287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886239111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3886239111
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.770458465
Short name T454
Test name
Test status
Simulation time 190655092 ps
CPU time 1.26 seconds
Started May 12 03:02:43 PM PDT 24
Finished May 12 03:02:45 PM PDT 24
Peak memory 200916 kb
Host smart-ec93dfcb-2de5-4dbf-8c07-9becc75974fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770458465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.770458465
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.467992948
Short name T47
Test name
Test status
Simulation time 121022363 ps
CPU time 1.2 seconds
Started May 12 03:02:45 PM PDT 24
Finished May 12 03:02:47 PM PDT 24
Peak memory 200988 kb
Host smart-75bea0b6-ed48-46c5-8221-bcacc0a26765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467992948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.467992948
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.810781238
Short name T504
Test name
Test status
Simulation time 5481658143 ps
CPU time 27.13 seconds
Started May 12 03:02:47 PM PDT 24
Finished May 12 03:03:14 PM PDT 24
Peak memory 209336 kb
Host smart-62b9454d-ee2b-4296-baf2-b7295c137fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810781238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.810781238
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1128332361
Short name T496
Test name
Test status
Simulation time 424119632 ps
CPU time 2.44 seconds
Started May 12 03:02:43 PM PDT 24
Finished May 12 03:02:47 PM PDT 24
Peak memory 209248 kb
Host smart-cc427474-9527-43d0-b4e6-040f6844cf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128332361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1128332361
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.812006896
Short name T396
Test name
Test status
Simulation time 84277800 ps
CPU time 0.89 seconds
Started May 12 03:02:45 PM PDT 24
Finished May 12 03:02:46 PM PDT 24
Peak memory 200216 kb
Host smart-84c2c2b7-f667-4f5e-8669-3d5aeff35533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812006896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.812006896
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2934741711
Short name T476
Test name
Test status
Simulation time 65291297 ps
CPU time 0.77 seconds
Started May 12 03:02:47 PM PDT 24
Finished May 12 03:02:49 PM PDT 24
Peak memory 200676 kb
Host smart-bc0bad2e-9d9e-4cc4-8c60-cdd9e4e8f3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934741711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2934741711
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3757867033
Short name T473
Test name
Test status
Simulation time 1234790185 ps
CPU time 5.84 seconds
Started May 12 03:02:50 PM PDT 24
Finished May 12 03:02:57 PM PDT 24
Peak memory 218444 kb
Host smart-7468201a-dc6a-4eaa-bd3a-7d10c274b643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757867033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3757867033
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1868982636
Short name T534
Test name
Test status
Simulation time 246083475 ps
CPU time 1.03 seconds
Started May 12 03:02:53 PM PDT 24
Finished May 12 03:02:55 PM PDT 24
Peak memory 218040 kb
Host smart-fffad3f1-4058-41d5-8207-0a0c22abb350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868982636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1868982636
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1612470103
Short name T191
Test name
Test status
Simulation time 200665577 ps
CPU time 0.91 seconds
Started May 12 03:02:47 PM PDT 24
Finished May 12 03:02:49 PM PDT 24
Peak memory 200736 kb
Host smart-fd8d7e96-5512-4e1a-96d6-513a0265ca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612470103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1612470103
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3635599292
Short name T363
Test name
Test status
Simulation time 839253263 ps
CPU time 4.69 seconds
Started May 12 03:02:47 PM PDT 24
Finished May 12 03:02:53 PM PDT 24
Peak memory 201100 kb
Host smart-27ec3615-ec10-425e-a398-5297c8540a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635599292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3635599292
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3734299213
Short name T488
Test name
Test status
Simulation time 148232999 ps
CPU time 1.09 seconds
Started May 12 03:02:53 PM PDT 24
Finished May 12 03:02:54 PM PDT 24
Peak memory 200836 kb
Host smart-ffd2a57e-a2cd-49fb-9199-1a550a3546b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734299213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3734299213
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1980663690
Short name T216
Test name
Test status
Simulation time 121868661 ps
CPU time 1.32 seconds
Started May 12 03:02:45 PM PDT 24
Finished May 12 03:02:47 PM PDT 24
Peak memory 200356 kb
Host smart-5371f5f8-de30-474e-8a4c-327aa4f638b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980663690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1980663690
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.826435497
Short name T40
Test name
Test status
Simulation time 2394255559 ps
CPU time 9.03 seconds
Started May 12 03:02:51 PM PDT 24
Finished May 12 03:03:00 PM PDT 24
Peak memory 201212 kb
Host smart-ac1a6b1c-e503-46ac-a021-1bc9f5e7a83d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826435497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.826435497
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1928895171
Short name T519
Test name
Test status
Simulation time 131202756 ps
CPU time 1.84 seconds
Started May 12 03:02:47 PM PDT 24
Finished May 12 03:02:50 PM PDT 24
Peak memory 200816 kb
Host smart-f91b4bb6-f59c-411f-a59c-9d608de428fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928895171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1928895171
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2288755489
Short name T441
Test name
Test status
Simulation time 215241033 ps
CPU time 1.49 seconds
Started May 12 03:02:48 PM PDT 24
Finished May 12 03:02:50 PM PDT 24
Peak memory 200784 kb
Host smart-2ffcbdb1-d8a6-4a9b-9f09-9ea6e2a3c2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288755489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2288755489
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3002090660
Short name T59
Test name
Test status
Simulation time 71904976 ps
CPU time 0.74 seconds
Started May 12 03:02:52 PM PDT 24
Finished May 12 03:02:53 PM PDT 24
Peak memory 200672 kb
Host smart-72c99e62-da6c-4a30-af0e-73a109d21fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002090660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3002090660
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.4230482318
Short name T241
Test name
Test status
Simulation time 2182164066 ps
CPU time 8.62 seconds
Started May 12 03:02:47 PM PDT 24
Finished May 12 03:02:56 PM PDT 24
Peak memory 222612 kb
Host smart-0095284e-9a39-4f5d-b4c4-1e0d7c2efd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230482318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.4230482318
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.706390687
Short name T297
Test name
Test status
Simulation time 245247289 ps
CPU time 1.05 seconds
Started May 12 03:02:50 PM PDT 24
Finished May 12 03:02:52 PM PDT 24
Peak memory 218136 kb
Host smart-21dc4fa9-7d1d-4cce-9c0a-5027d2438099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706390687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.706390687
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.397597380
Short name T222
Test name
Test status
Simulation time 166694890 ps
CPU time 0.86 seconds
Started May 12 03:02:48 PM PDT 24
Finished May 12 03:02:50 PM PDT 24
Peak memory 200668 kb
Host smart-0810c378-c19a-47e5-b3ef-ac9d66956054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397597380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.397597380
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.4054188698
Short name T407
Test name
Test status
Simulation time 1762537650 ps
CPU time 7.73 seconds
Started May 12 03:02:50 PM PDT 24
Finished May 12 03:02:58 PM PDT 24
Peak memory 201040 kb
Host smart-06c2033d-d0c7-498e-95dd-d253b39d8a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054188698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4054188698
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1334809148
Short name T264
Test name
Test status
Simulation time 98037476 ps
CPU time 1.05 seconds
Started May 12 03:02:47 PM PDT 24
Finished May 12 03:02:49 PM PDT 24
Peak memory 200800 kb
Host smart-792a560d-dec9-43a4-b809-89388f80b48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334809148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1334809148
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.256408524
Short name T479
Test name
Test status
Simulation time 247943027 ps
CPU time 1.46 seconds
Started May 12 03:02:48 PM PDT 24
Finished May 12 03:02:50 PM PDT 24
Peak memory 201048 kb
Host smart-73f380b3-dc91-41ce-a59e-734b981d16b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256408524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.256408524
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.415744096
Short name T205
Test name
Test status
Simulation time 827367661 ps
CPU time 3.91 seconds
Started May 12 03:02:52 PM PDT 24
Finished May 12 03:02:56 PM PDT 24
Peak memory 201048 kb
Host smart-03c13984-f79d-4b46-8b04-7e6ec3ec0252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415744096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.415744096
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.584080719
Short name T136
Test name
Test status
Simulation time 361989577 ps
CPU time 2.5 seconds
Started May 12 03:02:53 PM PDT 24
Finished May 12 03:02:56 PM PDT 24
Peak memory 200828 kb
Host smart-8331f491-f88d-4a30-a66c-ec9f9b55a1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584080719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.584080719
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3928207110
Short name T329
Test name
Test status
Simulation time 66747815 ps
CPU time 0.78 seconds
Started May 12 03:02:50 PM PDT 24
Finished May 12 03:02:51 PM PDT 24
Peak memory 200868 kb
Host smart-88477615-561c-4bcd-8c45-e09dfceabe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928207110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3928207110
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.989835944
Short name T53
Test name
Test status
Simulation time 74409638 ps
CPU time 0.81 seconds
Started May 12 03:02:55 PM PDT 24
Finished May 12 03:02:56 PM PDT 24
Peak memory 200676 kb
Host smart-5c4d866c-0ac6-4863-8f3d-72bccd55741c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989835944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.989835944
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2591906822
Short name T515
Test name
Test status
Simulation time 2164807286 ps
CPU time 9.69 seconds
Started May 12 03:02:55 PM PDT 24
Finished May 12 03:03:05 PM PDT 24
Peak memory 218640 kb
Host smart-d06c7953-8ea4-4edc-b85f-d2bf1ce96c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591906822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2591906822
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3903963361
Short name T393
Test name
Test status
Simulation time 244538065 ps
CPU time 1.16 seconds
Started May 12 03:02:55 PM PDT 24
Finished May 12 03:02:56 PM PDT 24
Peak memory 218020 kb
Host smart-cceed40f-2f26-4cb2-a30d-e00776505008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903963361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3903963361
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1698324036
Short name T429
Test name
Test status
Simulation time 221916526 ps
CPU time 1.03 seconds
Started May 12 03:02:50 PM PDT 24
Finished May 12 03:02:51 PM PDT 24
Peak memory 200612 kb
Host smart-3d47b625-5f41-4d00-b1af-314502c104ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698324036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1698324036
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3821054794
Short name T517
Test name
Test status
Simulation time 927783968 ps
CPU time 4.54 seconds
Started May 12 03:02:53 PM PDT 24
Finished May 12 03:02:58 PM PDT 24
Peak memory 201020 kb
Host smart-b18242c1-096c-4afd-9443-c6de87759478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821054794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3821054794
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2527034408
Short name T142
Test name
Test status
Simulation time 140700195 ps
CPU time 1.16 seconds
Started May 12 03:02:50 PM PDT 24
Finished May 12 03:02:52 PM PDT 24
Peak memory 200868 kb
Host smart-bc720da4-36c0-4a68-9d0f-48c5acfe0c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527034408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2527034408
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1074570367
Short name T126
Test name
Test status
Simulation time 249078599 ps
CPU time 1.69 seconds
Started May 12 03:02:51 PM PDT 24
Finished May 12 03:02:53 PM PDT 24
Peak memory 201032 kb
Host smart-e322c079-11b5-42cc-817c-16cacda4a18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074570367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1074570367
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.4289617881
Short name T333
Test name
Test status
Simulation time 3102723557 ps
CPU time 10.85 seconds
Started May 12 03:02:55 PM PDT 24
Finished May 12 03:03:06 PM PDT 24
Peak memory 209332 kb
Host smart-ad59b17d-e745-46bd-a3fa-9f8eb733bb3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289617881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.4289617881
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1479017058
Short name T319
Test name
Test status
Simulation time 306029461 ps
CPU time 2.15 seconds
Started May 12 03:02:50 PM PDT 24
Finished May 12 03:02:53 PM PDT 24
Peak memory 209092 kb
Host smart-41db0527-9a33-4aa7-84e9-9689528f7e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479017058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1479017058
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.421236663
Short name T453
Test name
Test status
Simulation time 111916372 ps
CPU time 0.99 seconds
Started May 12 03:02:51 PM PDT 24
Finished May 12 03:02:53 PM PDT 24
Peak memory 200760 kb
Host smart-b8b647ba-0f8e-4ee6-8321-491ba9582fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421236663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.421236663
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3807511159
Short name T139
Test name
Test status
Simulation time 79489334 ps
CPU time 0.82 seconds
Started May 12 03:03:02 PM PDT 24
Finished May 12 03:03:03 PM PDT 24
Peak memory 200644 kb
Host smart-2236389c-92d2-40f9-a550-14b69b8244ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807511159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3807511159
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1808734143
Short name T470
Test name
Test status
Simulation time 1225829563 ps
CPU time 5.95 seconds
Started May 12 03:03:01 PM PDT 24
Finished May 12 03:03:07 PM PDT 24
Peak memory 217908 kb
Host smart-f58ca89c-bd51-4cfc-94a6-5f8bf259583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808734143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1808734143
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1303402149
Short name T253
Test name
Test status
Simulation time 244616710 ps
CPU time 1.05 seconds
Started May 12 03:02:59 PM PDT 24
Finished May 12 03:03:01 PM PDT 24
Peak memory 218204 kb
Host smart-5698fcd9-52ad-43dc-b022-7d35437d3f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303402149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1303402149
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2352668768
Short name T412
Test name
Test status
Simulation time 173873512 ps
CPU time 0.83 seconds
Started May 12 03:02:58 PM PDT 24
Finished May 12 03:02:59 PM PDT 24
Peak memory 200644 kb
Host smart-89e05d17-fe4f-4db7-a773-46e9d76ea5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352668768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2352668768
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1936198163
Short name T93
Test name
Test status
Simulation time 1449007492 ps
CPU time 6.85 seconds
Started May 12 03:02:54 PM PDT 24
Finished May 12 03:03:01 PM PDT 24
Peak memory 201004 kb
Host smart-3b353798-e4a0-4fbc-b139-764fad8173b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936198163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1936198163
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1111978058
Short name T495
Test name
Test status
Simulation time 163991217 ps
CPU time 1.2 seconds
Started May 12 03:02:54 PM PDT 24
Finished May 12 03:02:56 PM PDT 24
Peak memory 200808 kb
Host smart-c7fa547f-730c-41d7-b4c0-e8b0fe121c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111978058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1111978058
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2484501264
Short name T530
Test name
Test status
Simulation time 251956507 ps
CPU time 1.52 seconds
Started May 12 03:02:57 PM PDT 24
Finished May 12 03:02:59 PM PDT 24
Peak memory 201064 kb
Host smart-2e939d48-768a-4162-97cf-7a6c7ec5e74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484501264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2484501264
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.92864660
Short name T188
Test name
Test status
Simulation time 13775480258 ps
CPU time 49.17 seconds
Started May 12 03:02:58 PM PDT 24
Finished May 12 03:03:47 PM PDT 24
Peak memory 209420 kb
Host smart-b4ac32e2-9b7b-403e-b4cb-ad0706300f06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92864660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.92864660
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1221969312
Short name T299
Test name
Test status
Simulation time 151191155 ps
CPU time 1.91 seconds
Started May 12 03:02:58 PM PDT 24
Finished May 12 03:03:00 PM PDT 24
Peak memory 200820 kb
Host smart-6ef7da75-ab29-4f35-8b18-a82617944896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221969312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1221969312
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1048693196
Short name T459
Test name
Test status
Simulation time 112329129 ps
CPU time 1.01 seconds
Started May 12 03:02:56 PM PDT 24
Finished May 12 03:02:58 PM PDT 24
Peak memory 200864 kb
Host smart-f13e3494-a77d-4339-954e-37f3f71a3c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048693196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1048693196
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2424352735
Short name T96
Test name
Test status
Simulation time 66657146 ps
CPU time 0.82 seconds
Started May 12 03:03:02 PM PDT 24
Finished May 12 03:03:03 PM PDT 24
Peak memory 200628 kb
Host smart-3098aae3-5b4e-4fd1-9c1f-110f36607961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424352735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2424352735
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3386427207
Short name T57
Test name
Test status
Simulation time 1228465443 ps
CPU time 5.79 seconds
Started May 12 03:02:59 PM PDT 24
Finished May 12 03:03:05 PM PDT 24
Peak memory 217900 kb
Host smart-2fa3f3d1-926c-4df4-969c-244378b0d2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386427207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3386427207
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1230031712
Short name T245
Test name
Test status
Simulation time 244942949 ps
CPU time 1.16 seconds
Started May 12 03:02:59 PM PDT 24
Finished May 12 03:03:01 PM PDT 24
Peak memory 218036 kb
Host smart-7405059a-331b-45af-bd4d-9111629f7e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230031712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1230031712
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3504176528
Short name T212
Test name
Test status
Simulation time 118579568 ps
CPU time 0.82 seconds
Started May 12 03:02:58 PM PDT 24
Finished May 12 03:03:00 PM PDT 24
Peak memory 200688 kb
Host smart-b055af98-c0d1-4ac7-8046-c3ee837ea056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504176528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3504176528
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2448268871
Short name T103
Test name
Test status
Simulation time 877836716 ps
CPU time 4.77 seconds
Started May 12 03:03:00 PM PDT 24
Finished May 12 03:03:05 PM PDT 24
Peak memory 201024 kb
Host smart-f6521a31-9c34-4e63-9150-17f65141660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448268871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2448268871
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.793751838
Short name T183
Test name
Test status
Simulation time 144625077 ps
CPU time 1.13 seconds
Started May 12 03:02:59 PM PDT 24
Finished May 12 03:03:01 PM PDT 24
Peak memory 200896 kb
Host smart-77e38292-e728-40bc-b5ec-f5c3b08c789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793751838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.793751838
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.254598685
Short name T249
Test name
Test status
Simulation time 114238575 ps
CPU time 1.2 seconds
Started May 12 03:03:01 PM PDT 24
Finished May 12 03:03:03 PM PDT 24
Peak memory 201176 kb
Host smart-6277c54f-ac55-44f5-92aa-371fb20e3fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254598685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.254598685
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3148240584
Short name T184
Test name
Test status
Simulation time 505373770 ps
CPU time 2.51 seconds
Started May 12 03:03:03 PM PDT 24
Finished May 12 03:03:07 PM PDT 24
Peak memory 201264 kb
Host smart-e51d0ed8-2f32-477d-9b29-d2d6a76ad642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148240584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3148240584
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.472718191
Short name T402
Test name
Test status
Simulation time 137663151 ps
CPU time 1.88 seconds
Started May 12 03:03:01 PM PDT 24
Finished May 12 03:03:03 PM PDT 24
Peak memory 200848 kb
Host smart-54f27b4a-293b-4515-a7a4-b79bf6acc549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472718191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.472718191
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2130903005
Short name T130
Test name
Test status
Simulation time 107454070 ps
CPU time 1.03 seconds
Started May 12 03:03:01 PM PDT 24
Finished May 12 03:03:03 PM PDT 24
Peak memory 201008 kb
Host smart-f9f4e7b3-2a9f-48c5-ad4a-50b8f4e6dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130903005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2130903005
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3400322913
Short name T237
Test name
Test status
Simulation time 65496037 ps
CPU time 0.78 seconds
Started May 12 03:03:04 PM PDT 24
Finished May 12 03:03:06 PM PDT 24
Peak memory 200632 kb
Host smart-78ab7049-41bc-4527-aa9d-fe54a3325473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400322913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3400322913
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3637826216
Short name T39
Test name
Test status
Simulation time 1897000173 ps
CPU time 7.72 seconds
Started May 12 03:03:05 PM PDT 24
Finished May 12 03:03:13 PM PDT 24
Peak memory 217964 kb
Host smart-baedd6a9-9bf3-4bc9-aa49-d31d6ca474d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637826216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3637826216
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2303142077
Short name T257
Test name
Test status
Simulation time 243693245 ps
CPU time 1.13 seconds
Started May 12 03:03:06 PM PDT 24
Finished May 12 03:03:08 PM PDT 24
Peak memory 218000 kb
Host smart-2e753252-6b1f-4faf-ae8e-b41f84e45482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303142077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2303142077
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.269033469
Short name T24
Test name
Test status
Simulation time 165321965 ps
CPU time 0.87 seconds
Started May 12 03:03:02 PM PDT 24
Finished May 12 03:03:04 PM PDT 24
Peak memory 200812 kb
Host smart-3041115b-706a-46d8-97d8-e2bc85af2012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269033469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.269033469
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3061973053
Short name T431
Test name
Test status
Simulation time 1633839529 ps
CPU time 6.58 seconds
Started May 12 03:03:03 PM PDT 24
Finished May 12 03:03:11 PM PDT 24
Peak memory 201052 kb
Host smart-908c4a4a-884c-41b2-86ea-44448b6981b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061973053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3061973053
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1508003963
Short name T309
Test name
Test status
Simulation time 145577320 ps
CPU time 1.13 seconds
Started May 12 03:03:04 PM PDT 24
Finished May 12 03:03:05 PM PDT 24
Peak memory 200868 kb
Host smart-47a11a27-5b27-4405-ad96-63f0f84b92b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508003963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1508003963
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1015600021
Short name T521
Test name
Test status
Simulation time 202409219 ps
CPU time 1.4 seconds
Started May 12 03:03:02 PM PDT 24
Finished May 12 03:03:04 PM PDT 24
Peak memory 200984 kb
Host smart-435a5461-d2a5-4f6a-b9b6-7f1b2954bd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015600021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1015600021
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1164831785
Short name T405
Test name
Test status
Simulation time 2577591282 ps
CPU time 9.55 seconds
Started May 12 03:03:09 PM PDT 24
Finished May 12 03:03:19 PM PDT 24
Peak memory 201092 kb
Host smart-d9a68f64-3da5-4ceb-8744-2ef466fc4c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164831785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1164831785
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2135773462
Short name T25
Test name
Test status
Simulation time 140857495 ps
CPU time 2 seconds
Started May 12 03:03:01 PM PDT 24
Finished May 12 03:03:04 PM PDT 24
Peak memory 209012 kb
Host smart-226c497c-0289-41ec-bc0f-2fb61cde38d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135773462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2135773462
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1071665018
Short name T51
Test name
Test status
Simulation time 220444641 ps
CPU time 1.37 seconds
Started May 12 03:03:02 PM PDT 24
Finished May 12 03:03:04 PM PDT 24
Peak memory 200796 kb
Host smart-a2a4a6d1-f726-4eb6-9f27-134e954ac362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071665018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1071665018
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1441941296
Short name T471
Test name
Test status
Simulation time 62067230 ps
CPU time 0.74 seconds
Started May 12 03:01:20 PM PDT 24
Finished May 12 03:01:22 PM PDT 24
Peak memory 200688 kb
Host smart-be5fc153-fd3e-4a73-a7ae-9c0e46e099cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441941296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1441941296
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.4218841202
Short name T328
Test name
Test status
Simulation time 1225665442 ps
CPU time 6.06 seconds
Started May 12 03:01:16 PM PDT 24
Finished May 12 03:01:23 PM PDT 24
Peak memory 221992 kb
Host smart-dd78f18c-645f-4ef0-8d86-6b4d0c5acab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218841202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.4218841202
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.4224560766
Short name T267
Test name
Test status
Simulation time 243749853 ps
CPU time 1.03 seconds
Started May 12 03:01:19 PM PDT 24
Finished May 12 03:01:20 PM PDT 24
Peak memory 218044 kb
Host smart-cccd9866-028b-4151-beda-c1cdfa5f3720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224560766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.4224560766
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1789156705
Short name T258
Test name
Test status
Simulation time 193030965 ps
CPU time 0.89 seconds
Started May 12 03:01:15 PM PDT 24
Finished May 12 03:01:16 PM PDT 24
Peak memory 200640 kb
Host smart-5518a355-ecdb-4316-8f0a-76812d386ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789156705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1789156705
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3706225318
Short name T90
Test name
Test status
Simulation time 1351629277 ps
CPU time 5.46 seconds
Started May 12 03:01:16 PM PDT 24
Finished May 12 03:01:22 PM PDT 24
Peak memory 200988 kb
Host smart-66cab879-6245-4b4c-ac16-3cf0cfffdd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706225318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3706225318
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3823806711
Short name T66
Test name
Test status
Simulation time 16665321640 ps
CPU time 26.07 seconds
Started May 12 03:01:18 PM PDT 24
Finished May 12 03:01:45 PM PDT 24
Peak memory 217660 kb
Host smart-f1526901-03d3-4b5f-bd4e-4fa24c4e836e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823806711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3823806711
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.908063598
Short name T484
Test name
Test status
Simulation time 188279934 ps
CPU time 1.3 seconds
Started May 12 03:01:16 PM PDT 24
Finished May 12 03:01:18 PM PDT 24
Peak memory 200788 kb
Host smart-02922ffa-b984-423d-833b-b8827411f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908063598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.908063598
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2829475875
Short name T421
Test name
Test status
Simulation time 255536957 ps
CPU time 1.76 seconds
Started May 12 03:01:17 PM PDT 24
Finished May 12 03:01:19 PM PDT 24
Peak memory 201036 kb
Host smart-32e0e7f7-67f6-4e92-a3ed-94416d8b429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829475875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2829475875
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3047366299
Short name T350
Test name
Test status
Simulation time 15490991593 ps
CPU time 61.78 seconds
Started May 12 03:01:18 PM PDT 24
Finished May 12 03:02:20 PM PDT 24
Peak memory 209396 kb
Host smart-7d469b6b-af4d-4a9c-a32c-95dc66c8f6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047366299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3047366299
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1474418895
Short name T373
Test name
Test status
Simulation time 409278109 ps
CPU time 2.28 seconds
Started May 12 03:01:15 PM PDT 24
Finished May 12 03:01:18 PM PDT 24
Peak memory 200856 kb
Host smart-02ef00f0-0435-4227-a73e-d3c3ceb58cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474418895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1474418895
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1747191685
Short name T9
Test name
Test status
Simulation time 68941223 ps
CPU time 0.78 seconds
Started May 12 03:01:16 PM PDT 24
Finished May 12 03:01:18 PM PDT 24
Peak memory 200756 kb
Host smart-a4281eee-1ed1-4999-92a2-ac9e9e851830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747191685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1747191685
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.968799592
Short name T72
Test name
Test status
Simulation time 179951092 ps
CPU time 0.97 seconds
Started May 12 03:03:10 PM PDT 24
Finished May 12 03:03:11 PM PDT 24
Peak memory 200708 kb
Host smart-6697ebb8-1d79-499e-9ae5-00a3e6bd380a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968799592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.968799592
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1235240269
Short name T31
Test name
Test status
Simulation time 2353757850 ps
CPU time 8.45 seconds
Started May 12 03:03:08 PM PDT 24
Finished May 12 03:03:17 PM PDT 24
Peak memory 218648 kb
Host smart-fcd7246e-81e1-42c4-9590-21f1caf69dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235240269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1235240269
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3598480758
Short name T501
Test name
Test status
Simulation time 245148572 ps
CPU time 1.14 seconds
Started May 12 03:03:12 PM PDT 24
Finished May 12 03:03:14 PM PDT 24
Peak memory 218004 kb
Host smart-2220a6ed-6bdf-4850-8ba4-6312236740cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598480758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3598480758
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1955535179
Short name T209
Test name
Test status
Simulation time 122246514 ps
CPU time 0.88 seconds
Started May 12 03:03:05 PM PDT 24
Finished May 12 03:03:07 PM PDT 24
Peak memory 200632 kb
Host smart-b79b63a5-d576-4bfc-8f13-6d3163c5113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955535179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1955535179
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3465957218
Short name T232
Test name
Test status
Simulation time 1053912899 ps
CPU time 5.35 seconds
Started May 12 03:03:06 PM PDT 24
Finished May 12 03:03:12 PM PDT 24
Peak memory 201040 kb
Host smart-3159bc55-d27e-4e54-b304-7a1a4d801fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465957218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3465957218
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2624225512
Short name T487
Test name
Test status
Simulation time 181833122 ps
CPU time 1.24 seconds
Started May 12 03:03:12 PM PDT 24
Finished May 12 03:03:14 PM PDT 24
Peak memory 200984 kb
Host smart-da2ceeee-16b8-4bba-bfc4-ff8c4b1f5c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624225512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2624225512
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3447279664
Short name T406
Test name
Test status
Simulation time 193039774 ps
CPU time 1.46 seconds
Started May 12 03:03:06 PM PDT 24
Finished May 12 03:03:08 PM PDT 24
Peak memory 201064 kb
Host smart-70a66f58-80d0-458a-8817-d8c1958b6968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447279664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3447279664
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.673539067
Short name T217
Test name
Test status
Simulation time 11936459211 ps
CPU time 41.15 seconds
Started May 12 03:03:10 PM PDT 24
Finished May 12 03:03:51 PM PDT 24
Peak memory 211240 kb
Host smart-309ac15c-4e9c-4fb9-885c-04c4803176ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673539067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.673539067
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1045120392
Short name T467
Test name
Test status
Simulation time 148776248 ps
CPU time 1.86 seconds
Started May 12 03:03:11 PM PDT 24
Finished May 12 03:03:13 PM PDT 24
Peak memory 200864 kb
Host smart-40b06459-37a8-4054-9a1f-f22c08cf92e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045120392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1045120392
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2965232234
Short name T159
Test name
Test status
Simulation time 226625744 ps
CPU time 1.36 seconds
Started May 12 03:03:08 PM PDT 24
Finished May 12 03:03:10 PM PDT 24
Peak memory 200824 kb
Host smart-a776a594-c1d6-4f26-9b26-c767c09dc1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965232234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2965232234
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3401348224
Short name T464
Test name
Test status
Simulation time 65284309 ps
CPU time 0.75 seconds
Started May 12 03:03:14 PM PDT 24
Finished May 12 03:03:15 PM PDT 24
Peak memory 200708 kb
Host smart-dd428e6b-cee1-4d6e-bb7a-89786baa3346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401348224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3401348224
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3222391989
Short name T353
Test name
Test status
Simulation time 2352754409 ps
CPU time 7.95 seconds
Started May 12 03:03:13 PM PDT 24
Finished May 12 03:03:22 PM PDT 24
Peak memory 230724 kb
Host smart-27cb7b78-28f3-4ebc-a0b4-8c895c7a64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222391989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3222391989
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.4104083751
Short name T445
Test name
Test status
Simulation time 244081992 ps
CPU time 1.06 seconds
Started May 12 03:03:14 PM PDT 24
Finished May 12 03:03:15 PM PDT 24
Peak memory 218188 kb
Host smart-f6e4014d-665b-4480-8645-de515242af25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104083751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.4104083751
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.222012588
Short name T320
Test name
Test status
Simulation time 209573909 ps
CPU time 0.91 seconds
Started May 12 03:03:08 PM PDT 24
Finished May 12 03:03:10 PM PDT 24
Peak memory 200644 kb
Host smart-66e20b45-1ac0-4368-975f-33eced60d303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222012588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.222012588
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.388279269
Short name T508
Test name
Test status
Simulation time 701117568 ps
CPU time 3.94 seconds
Started May 12 03:03:11 PM PDT 24
Finished May 12 03:03:15 PM PDT 24
Peak memory 201092 kb
Host smart-99e59173-9f5d-4783-b93d-0bd2644c9adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388279269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.388279269
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3267702611
Short name T76
Test name
Test status
Simulation time 180576014 ps
CPU time 1.2 seconds
Started May 12 03:03:13 PM PDT 24
Finished May 12 03:03:15 PM PDT 24
Peak memory 200992 kb
Host smart-2aac4a6d-c0f7-464e-8199-a2c4b428ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267702611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3267702611
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2235310131
Short name T395
Test name
Test status
Simulation time 201447866 ps
CPU time 1.37 seconds
Started May 12 03:03:09 PM PDT 24
Finished May 12 03:03:11 PM PDT 24
Peak memory 201052 kb
Host smart-21e2a050-9540-43a6-b306-e9f38b1662e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235310131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2235310131
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2254027376
Short name T535
Test name
Test status
Simulation time 257773861 ps
CPU time 1.53 seconds
Started May 12 03:03:11 PM PDT 24
Finished May 12 03:03:13 PM PDT 24
Peak memory 201032 kb
Host smart-c0323f20-496c-4f6e-b183-6353cd95af4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254027376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2254027376
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1550046095
Short name T369
Test name
Test status
Simulation time 356609478 ps
CPU time 2.2 seconds
Started May 12 03:03:12 PM PDT 24
Finished May 12 03:03:15 PM PDT 24
Peak memory 200808 kb
Host smart-80300086-8ab5-4536-828d-f10b07884834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550046095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1550046095
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1339934159
Short name T491
Test name
Test status
Simulation time 129235004 ps
CPU time 1.07 seconds
Started May 12 03:03:14 PM PDT 24
Finished May 12 03:03:15 PM PDT 24
Peak memory 200856 kb
Host smart-c7181622-2076-4c9f-a141-76ad5f180069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339934159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1339934159
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1012133307
Short name T448
Test name
Test status
Simulation time 57746280 ps
CPU time 0.75 seconds
Started May 12 03:03:19 PM PDT 24
Finished May 12 03:03:21 PM PDT 24
Peak memory 200708 kb
Host smart-12d431c7-7a9d-43d9-ae79-f26eb4df76bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012133307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1012133307
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1631785698
Short name T268
Test name
Test status
Simulation time 1219335431 ps
CPU time 6.18 seconds
Started May 12 03:03:15 PM PDT 24
Finished May 12 03:03:21 PM PDT 24
Peak memory 217464 kb
Host smart-e423b3ba-c4c6-473e-ba9d-0dec7667e7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631785698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1631785698
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4255548013
Short name T325
Test name
Test status
Simulation time 243491794 ps
CPU time 1.09 seconds
Started May 12 03:03:20 PM PDT 24
Finished May 12 03:03:21 PM PDT 24
Peak memory 218004 kb
Host smart-8f9e40aa-e737-4408-bc92-a4875b9b8460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255548013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4255548013
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3846277581
Short name T493
Test name
Test status
Simulation time 130451082 ps
CPU time 0.8 seconds
Started May 12 03:03:12 PM PDT 24
Finished May 12 03:03:14 PM PDT 24
Peak memory 200668 kb
Host smart-0c395e18-b059-4c68-ae00-985d6bb4ed38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846277581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3846277581
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2447462928
Short name T173
Test name
Test status
Simulation time 1012294120 ps
CPU time 5.21 seconds
Started May 12 03:03:12 PM PDT 24
Finished May 12 03:03:18 PM PDT 24
Peak memory 200992 kb
Host smart-30818a87-da79-4068-889e-298fbd42295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447462928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2447462928
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.888834468
Short name T460
Test name
Test status
Simulation time 165665146 ps
CPU time 1.14 seconds
Started May 12 03:03:11 PM PDT 24
Finished May 12 03:03:13 PM PDT 24
Peak memory 200884 kb
Host smart-d6c399d2-7d1b-424b-b469-366574e9111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888834468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.888834468
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2760182573
Short name T365
Test name
Test status
Simulation time 116454499 ps
CPU time 1.21 seconds
Started May 12 03:03:15 PM PDT 24
Finished May 12 03:03:17 PM PDT 24
Peak memory 201056 kb
Host smart-e62d0723-d81e-4966-803d-dd0c90bc755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760182573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2760182573
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1725238695
Short name T287
Test name
Test status
Simulation time 1866620860 ps
CPU time 8.59 seconds
Started May 12 03:03:16 PM PDT 24
Finished May 12 03:03:25 PM PDT 24
Peak memory 201084 kb
Host smart-10fa3a80-62a6-48aa-9b50-b4b6d36ae238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725238695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1725238695
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2090934710
Short name T252
Test name
Test status
Simulation time 433490806 ps
CPU time 2.24 seconds
Started May 12 03:03:13 PM PDT 24
Finished May 12 03:03:16 PM PDT 24
Peak memory 209116 kb
Host smart-5d85d226-5c66-43b3-89f7-ed61ee3dd8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090934710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2090934710
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2713983549
Short name T305
Test name
Test status
Simulation time 137154251 ps
CPU time 1.03 seconds
Started May 12 03:03:12 PM PDT 24
Finished May 12 03:03:13 PM PDT 24
Peak memory 200888 kb
Host smart-65526388-fea8-4c5d-ae84-39d5cb977969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713983549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2713983549
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.6576044
Short name T540
Test name
Test status
Simulation time 63573973 ps
CPU time 0.86 seconds
Started May 12 03:03:17 PM PDT 24
Finished May 12 03:03:18 PM PDT 24
Peak memory 200700 kb
Host smart-14d92d4b-7729-4582-b128-8f188782e9ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6576044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.6576044
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1474463147
Short name T37
Test name
Test status
Simulation time 2375464805 ps
CPU time 8.36 seconds
Started May 12 03:03:19 PM PDT 24
Finished May 12 03:03:28 PM PDT 24
Peak memory 218644 kb
Host smart-57c03848-b222-44a5-809a-173a865840a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474463147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1474463147
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3618326475
Short name T156
Test name
Test status
Simulation time 244695598 ps
CPU time 1.07 seconds
Started May 12 03:03:20 PM PDT 24
Finished May 12 03:03:22 PM PDT 24
Peak memory 217856 kb
Host smart-046237c4-15d3-4454-b776-5b9ae7095474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618326475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3618326475
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3050528143
Short name T514
Test name
Test status
Simulation time 95035675 ps
CPU time 0.78 seconds
Started May 12 03:03:20 PM PDT 24
Finished May 12 03:03:21 PM PDT 24
Peak memory 200492 kb
Host smart-41a9f3e0-553a-4f09-bf44-3391c2a6968b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050528143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3050528143
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3204561793
Short name T300
Test name
Test status
Simulation time 836449614 ps
CPU time 4.64 seconds
Started May 12 03:03:15 PM PDT 24
Finished May 12 03:03:21 PM PDT 24
Peak memory 201024 kb
Host smart-11ba1e69-7b2e-4d98-ba06-8af4b952ba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204561793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3204561793
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2218641383
Short name T302
Test name
Test status
Simulation time 99982125 ps
CPU time 1.05 seconds
Started May 12 03:03:17 PM PDT 24
Finished May 12 03:03:18 PM PDT 24
Peak memory 200828 kb
Host smart-8dcab1f2-236c-4ed4-a22f-a3412689a509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218641383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2218641383
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.517879222
Short name T507
Test name
Test status
Simulation time 234523026 ps
CPU time 1.45 seconds
Started May 12 03:03:20 PM PDT 24
Finished May 12 03:03:22 PM PDT 24
Peak memory 201024 kb
Host smart-d70abbbc-3f9e-4fb1-b330-e22bb46558a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517879222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.517879222
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1477681966
Short name T101
Test name
Test status
Simulation time 5507950748 ps
CPU time 19.53 seconds
Started May 12 03:03:16 PM PDT 24
Finished May 12 03:03:36 PM PDT 24
Peak memory 209408 kb
Host smart-5ea16558-f395-48b7-bf1d-2be6e45e0f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477681966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1477681966
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.714883757
Short name T355
Test name
Test status
Simulation time 132622585 ps
CPU time 1.68 seconds
Started May 12 03:03:16 PM PDT 24
Finished May 12 03:03:19 PM PDT 24
Peak memory 200760 kb
Host smart-e23dca71-c2d7-40de-82d0-5fc4117a6921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714883757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.714883757
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3791326636
Short name T231
Test name
Test status
Simulation time 91408074 ps
CPU time 0.91 seconds
Started May 12 03:03:16 PM PDT 24
Finished May 12 03:03:17 PM PDT 24
Peak memory 201072 kb
Host smart-048e03b7-a062-40c0-a791-08b4df74c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791326636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3791326636
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2912954939
Short name T351
Test name
Test status
Simulation time 60831037 ps
CPU time 0.75 seconds
Started May 12 03:03:19 PM PDT 24
Finished May 12 03:03:20 PM PDT 24
Peak memory 200648 kb
Host smart-3a917746-4ece-4660-8376-aafc8e458fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912954939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2912954939
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3325928185
Short name T472
Test name
Test status
Simulation time 1894206404 ps
CPU time 8.32 seconds
Started May 12 03:03:19 PM PDT 24
Finished May 12 03:03:28 PM PDT 24
Peak memory 218492 kb
Host smart-251a81e0-8d79-482a-85ab-755222426c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325928185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3325928185
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.376529122
Short name T418
Test name
Test status
Simulation time 243583612 ps
CPU time 1.12 seconds
Started May 12 03:03:19 PM PDT 24
Finished May 12 03:03:21 PM PDT 24
Peak memory 217960 kb
Host smart-fce9fdab-4b57-46fb-a992-ed3e9139f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376529122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.376529122
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.862621208
Short name T18
Test name
Test status
Simulation time 109569880 ps
CPU time 0.76 seconds
Started May 12 03:03:21 PM PDT 24
Finished May 12 03:03:23 PM PDT 24
Peak memory 200660 kb
Host smart-74d4bff0-ac56-4b64-81fb-b3b7d022231f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862621208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.862621208
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2058654390
Short name T361
Test name
Test status
Simulation time 1505914109 ps
CPU time 5.84 seconds
Started May 12 03:03:20 PM PDT 24
Finished May 12 03:03:27 PM PDT 24
Peak memory 201040 kb
Host smart-e1b0c5b2-c1fb-4d1c-ae4c-aea15e2d38c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058654390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2058654390
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2241826667
Short name T247
Test name
Test status
Simulation time 177078434 ps
CPU time 1.15 seconds
Started May 12 03:03:23 PM PDT 24
Finished May 12 03:03:24 PM PDT 24
Peak memory 200852 kb
Host smart-05b674af-cbb4-4b7c-9143-625eb4d579ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241826667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2241826667
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1150849890
Short name T451
Test name
Test status
Simulation time 121105497 ps
CPU time 1.25 seconds
Started May 12 03:03:21 PM PDT 24
Finished May 12 03:03:22 PM PDT 24
Peak memory 201048 kb
Host smart-f3917683-152e-4185-b2b7-b22a8f8adf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150849890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1150849890
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.885010027
Short name T404
Test name
Test status
Simulation time 16386703246 ps
CPU time 58.58 seconds
Started May 12 03:03:22 PM PDT 24
Finished May 12 03:04:22 PM PDT 24
Peak memory 201140 kb
Host smart-de9f62e8-2403-47ac-8038-cdd513462092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885010027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.885010027
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3393344030
Short name T342
Test name
Test status
Simulation time 145861709 ps
CPU time 1.78 seconds
Started May 12 03:03:20 PM PDT 24
Finished May 12 03:03:22 PM PDT 24
Peak memory 200872 kb
Host smart-8205ee60-4591-48e0-895b-095d5767d187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393344030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3393344030
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.672014186
Short name T6
Test name
Test status
Simulation time 173862080 ps
CPU time 1.12 seconds
Started May 12 03:03:19 PM PDT 24
Finished May 12 03:03:21 PM PDT 24
Peak memory 200820 kb
Host smart-32a17602-49c7-490f-89e9-8ed752a67799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672014186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.672014186
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.728242212
Short name T134
Test name
Test status
Simulation time 94158867 ps
CPU time 0.8 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:03:26 PM PDT 24
Peak memory 200692 kb
Host smart-3f10b192-5d1d-496c-99b6-cd426edd276f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728242212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.728242212
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1930012240
Short name T456
Test name
Test status
Simulation time 1232798454 ps
CPU time 5.67 seconds
Started May 12 03:03:22 PM PDT 24
Finished May 12 03:03:29 PM PDT 24
Peak memory 217884 kb
Host smart-a79ed65f-92bf-4a9a-8d6a-e8a6414dab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930012240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1930012240
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3387039739
Short name T434
Test name
Test status
Simulation time 244277540 ps
CPU time 1.1 seconds
Started May 12 03:03:23 PM PDT 24
Finished May 12 03:03:25 PM PDT 24
Peak memory 217988 kb
Host smart-20250712-2d0a-4153-a26d-3d68ca14ebc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387039739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3387039739
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2232467754
Short name T230
Test name
Test status
Simulation time 94948199 ps
CPU time 0.75 seconds
Started May 12 03:03:25 PM PDT 24
Finished May 12 03:03:26 PM PDT 24
Peak memory 200680 kb
Host smart-7e6cd853-3349-496f-9de9-ba7efc59841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232467754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2232467754
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.976549740
Short name T250
Test name
Test status
Simulation time 1856206216 ps
CPU time 7.15 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:03:32 PM PDT 24
Peak memory 201036 kb
Host smart-1dfe1498-0e06-4c50-a26b-59174ad06f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976549740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.976549740
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2888118922
Short name T150
Test name
Test status
Simulation time 107865360 ps
CPU time 1.08 seconds
Started May 12 03:03:23 PM PDT 24
Finished May 12 03:03:24 PM PDT 24
Peak memory 200832 kb
Host smart-a14c769d-83af-4445-ae81-cae1407e4b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888118922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2888118922
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1341935428
Short name T439
Test name
Test status
Simulation time 111147060 ps
CPU time 1.24 seconds
Started May 12 03:03:20 PM PDT 24
Finished May 12 03:03:22 PM PDT 24
Peak memory 201028 kb
Host smart-c82de114-8c3f-45bb-9225-fe517e9b9f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341935428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1341935428
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.756902355
Short name T533
Test name
Test status
Simulation time 8799931432 ps
CPU time 36.64 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:04:01 PM PDT 24
Peak memory 201180 kb
Host smart-9011b4ce-1cff-47c0-abe2-53a95635e969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756902355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.756902355
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2523006026
Short name T290
Test name
Test status
Simulation time 449459582 ps
CPU time 2.63 seconds
Started May 12 03:03:20 PM PDT 24
Finished May 12 03:03:24 PM PDT 24
Peak memory 200764 kb
Host smart-e77f9292-01f8-408a-93af-a639aa208ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523006026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2523006026
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2233155753
Short name T196
Test name
Test status
Simulation time 147273942 ps
CPU time 1.08 seconds
Started May 12 03:03:21 PM PDT 24
Finished May 12 03:03:23 PM PDT 24
Peak memory 200876 kb
Host smart-fff513be-e247-41da-ad3f-413caf1f2171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233155753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2233155753
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2426261481
Short name T277
Test name
Test status
Simulation time 62655553 ps
CPU time 0.73 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:03:26 PM PDT 24
Peak memory 200704 kb
Host smart-9b5505b8-3c4d-4f49-bd9e-1e91c83a64bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426261481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2426261481
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2927600364
Short name T389
Test name
Test status
Simulation time 1223452721 ps
CPU time 6.84 seconds
Started May 12 03:03:23 PM PDT 24
Finished May 12 03:03:31 PM PDT 24
Peak memory 218488 kb
Host smart-661894b5-fb17-45fa-bde2-6e62ac032eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927600364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2927600364
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.606293380
Short name T27
Test name
Test status
Simulation time 244746103 ps
CPU time 1.15 seconds
Started May 12 03:03:25 PM PDT 24
Finished May 12 03:03:27 PM PDT 24
Peak memory 217988 kb
Host smart-7745344e-cbfe-4bca-bbd3-3afbd955b158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606293380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.606293380
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3698681794
Short name T16
Test name
Test status
Simulation time 111577890 ps
CPU time 0.82 seconds
Started May 12 03:03:22 PM PDT 24
Finished May 12 03:03:24 PM PDT 24
Peak memory 200720 kb
Host smart-ce370583-fdab-41dd-8514-2291715c2cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698681794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3698681794
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3064755342
Short name T158
Test name
Test status
Simulation time 1324419848 ps
CPU time 5.53 seconds
Started May 12 03:03:22 PM PDT 24
Finished May 12 03:03:29 PM PDT 24
Peak memory 200988 kb
Host smart-72126ce0-49b8-4022-9fb2-bf90286cb977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064755342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3064755342
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1456169239
Short name T55
Test name
Test status
Simulation time 104208260 ps
CPU time 1.06 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:03:26 PM PDT 24
Peak memory 200876 kb
Host smart-5948d94c-9bb2-4ebd-af2e-e57997736cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456169239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1456169239
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2282817033
Short name T206
Test name
Test status
Simulation time 123782104 ps
CPU time 1.2 seconds
Started May 12 03:03:20 PM PDT 24
Finished May 12 03:03:22 PM PDT 24
Peak memory 201060 kb
Host smart-9b014f98-6ad1-4ea1-a513-226bd4d67864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282817033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2282817033
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1205739394
Short name T105
Test name
Test status
Simulation time 3331392778 ps
CPU time 18.27 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:03:43 PM PDT 24
Peak memory 201176 kb
Host smart-87217e62-5af2-4d0a-8726-fba9c3e36190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205739394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1205739394
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.393173348
Short name T370
Test name
Test status
Simulation time 118202386 ps
CPU time 1.54 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:03:27 PM PDT 24
Peak memory 200784 kb
Host smart-0fc69e60-c6b7-454a-96e1-95776824de7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393173348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.393173348
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.153170524
Short name T207
Test name
Test status
Simulation time 291615704 ps
CPU time 1.6 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:03:26 PM PDT 24
Peak memory 201288 kb
Host smart-879161ff-84c0-4503-b901-ff44e6e0a6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153170524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.153170524
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2076445193
Short name T164
Test name
Test status
Simulation time 71902362 ps
CPU time 0.82 seconds
Started May 12 03:03:29 PM PDT 24
Finished May 12 03:03:30 PM PDT 24
Peak memory 200716 kb
Host smart-de7da85e-7ea7-426e-8a4c-de5eb26755c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076445193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2076445193
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2505519309
Short name T510
Test name
Test status
Simulation time 1239372841 ps
CPU time 5.43 seconds
Started May 12 03:03:26 PM PDT 24
Finished May 12 03:03:32 PM PDT 24
Peak memory 218424 kb
Host smart-b3e23fa9-88f5-47a7-b214-d4cb93c25959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505519309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2505519309
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3730215803
Short name T49
Test name
Test status
Simulation time 244441708 ps
CPU time 1.01 seconds
Started May 12 03:03:26 PM PDT 24
Finished May 12 03:03:27 PM PDT 24
Peak memory 218016 kb
Host smart-b2eb596d-7986-453e-be84-5364ea670c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730215803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3730215803
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3026440383
Short name T22
Test name
Test status
Simulation time 203985442 ps
CPU time 0.9 seconds
Started May 12 03:03:23 PM PDT 24
Finished May 12 03:03:25 PM PDT 24
Peak memory 200672 kb
Host smart-deab5f9f-cbd9-4c79-81f7-0daf86638aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026440383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3026440383
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1751857670
Short name T401
Test name
Test status
Simulation time 955323650 ps
CPU time 5.17 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:03:29 PM PDT 24
Peak memory 200940 kb
Host smart-98ed142e-08d4-4f6b-bd10-4703a2719525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751857670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1751857670
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2871057714
Short name T420
Test name
Test status
Simulation time 147871791 ps
CPU time 1.2 seconds
Started May 12 03:03:27 PM PDT 24
Finished May 12 03:03:29 PM PDT 24
Peak memory 200764 kb
Host smart-7c1abd24-2264-42c5-a779-7f86a0b04b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871057714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2871057714
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.687681299
Short name T438
Test name
Test status
Simulation time 128124175 ps
CPU time 1.2 seconds
Started May 12 03:03:24 PM PDT 24
Finished May 12 03:03:26 PM PDT 24
Peak memory 201028 kb
Host smart-18cef4cc-a5d4-496f-91fb-b4f47c0d4aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687681299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.687681299
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.36049511
Short name T79
Test name
Test status
Simulation time 6724130616 ps
CPU time 23.12 seconds
Started May 12 03:03:27 PM PDT 24
Finished May 12 03:03:51 PM PDT 24
Peak memory 201168 kb
Host smart-f804fa18-7094-43f7-844a-3901f8bb5326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36049511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.36049511
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2891189858
Short name T97
Test name
Test status
Simulation time 88319958 ps
CPU time 0.83 seconds
Started May 12 03:03:27 PM PDT 24
Finished May 12 03:03:28 PM PDT 24
Peak memory 200796 kb
Host smart-7a0fcb83-f3fc-4a47-8d51-a66987d98948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891189858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2891189858
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1904400642
Short name T228
Test name
Test status
Simulation time 67082816 ps
CPU time 0.78 seconds
Started May 12 03:03:31 PM PDT 24
Finished May 12 03:03:33 PM PDT 24
Peak memory 200640 kb
Host smart-38ed338d-e79f-4878-baca-aca19d038ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904400642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1904400642
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1617136858
Short name T399
Test name
Test status
Simulation time 1219041576 ps
CPU time 6.2 seconds
Started May 12 03:03:31 PM PDT 24
Finished May 12 03:03:38 PM PDT 24
Peak memory 218492 kb
Host smart-de7edf2b-4d1e-4d38-8cda-2a014807cf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617136858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1617136858
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.23553556
Short name T354
Test name
Test status
Simulation time 244957948 ps
CPU time 1.14 seconds
Started May 12 03:03:30 PM PDT 24
Finished May 12 03:03:32 PM PDT 24
Peak memory 218016 kb
Host smart-0ab1ef3c-2625-47d4-b58c-3b19c09e7145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23553556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.23553556
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.975323429
Short name T481
Test name
Test status
Simulation time 100822278 ps
CPU time 0.79 seconds
Started May 12 03:03:25 PM PDT 24
Finished May 12 03:03:27 PM PDT 24
Peak memory 200648 kb
Host smart-bf4b26b9-98c7-44e9-b9c7-c0f4da2fa1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975323429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.975323429
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3354320643
Short name T78
Test name
Test status
Simulation time 1582867008 ps
CPU time 7.22 seconds
Started May 12 03:03:32 PM PDT 24
Finished May 12 03:03:40 PM PDT 24
Peak memory 200988 kb
Host smart-365a7fda-c76e-4fdc-885e-41a9d8d4b865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354320643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3354320643
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3611010463
Short name T263
Test name
Test status
Simulation time 156993602 ps
CPU time 1.14 seconds
Started May 12 03:03:30 PM PDT 24
Finished May 12 03:03:31 PM PDT 24
Peak memory 200764 kb
Host smart-2527d893-48d8-4978-b41a-f9be6568bfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611010463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3611010463
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1241272167
Short name T137
Test name
Test status
Simulation time 193281870 ps
CPU time 1.36 seconds
Started May 12 03:03:32 PM PDT 24
Finished May 12 03:03:34 PM PDT 24
Peak memory 201024 kb
Host smart-037bf5d7-4aee-4f61-b38b-0889243726c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241272167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1241272167
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.733286507
Short name T366
Test name
Test status
Simulation time 5108828821 ps
CPU time 18.59 seconds
Started May 12 03:03:32 PM PDT 24
Finished May 12 03:03:51 PM PDT 24
Peak memory 209352 kb
Host smart-5a451463-3bd4-4b72-b0d6-83b309899679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733286507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.733286507
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3891682419
Short name T347
Test name
Test status
Simulation time 144828355 ps
CPU time 1.71 seconds
Started May 12 03:03:30 PM PDT 24
Finished May 12 03:03:33 PM PDT 24
Peak memory 200904 kb
Host smart-c9713236-16cf-4725-80de-ac266332070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891682419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3891682419
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4220392012
Short name T15
Test name
Test status
Simulation time 206567352 ps
CPU time 1.37 seconds
Started May 12 03:03:29 PM PDT 24
Finished May 12 03:03:30 PM PDT 24
Peak memory 200836 kb
Host smart-dab29778-3793-4444-a987-3ed2d924bc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220392012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4220392012
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.112073044
Short name T279
Test name
Test status
Simulation time 69746838 ps
CPU time 0.78 seconds
Started May 12 03:03:33 PM PDT 24
Finished May 12 03:03:35 PM PDT 24
Peak memory 200708 kb
Host smart-ffbb437d-3bc1-4057-a129-7a086d1a95bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112073044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.112073044
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.477326591
Short name T32
Test name
Test status
Simulation time 1885465699 ps
CPU time 8.08 seconds
Started May 12 03:03:32 PM PDT 24
Finished May 12 03:03:41 PM PDT 24
Peak memory 218464 kb
Host smart-18e9b3eb-7cb1-48be-b692-56a80289cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477326591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.477326591
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.539603488
Short name T337
Test name
Test status
Simulation time 243913056 ps
CPU time 1.06 seconds
Started May 12 03:03:34 PM PDT 24
Finished May 12 03:03:35 PM PDT 24
Peak memory 218072 kb
Host smart-4966940c-4529-4283-8f92-030982bfe25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539603488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.539603488
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3287771714
Short name T203
Test name
Test status
Simulation time 169161874 ps
CPU time 0.96 seconds
Started May 12 03:03:36 PM PDT 24
Finished May 12 03:03:37 PM PDT 24
Peak memory 200724 kb
Host smart-40fc604c-fe69-4650-ab4b-f47addb442d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287771714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3287771714
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.4179275544
Short name T452
Test name
Test status
Simulation time 748752793 ps
CPU time 4.18 seconds
Started May 12 03:03:34 PM PDT 24
Finished May 12 03:03:39 PM PDT 24
Peak memory 201036 kb
Host smart-0c700337-988c-430b-be1d-0d3d845078c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179275544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.4179275544
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2664725617
Short name T4
Test name
Test status
Simulation time 153082986 ps
CPU time 1.18 seconds
Started May 12 03:03:33 PM PDT 24
Finished May 12 03:03:35 PM PDT 24
Peak memory 200848 kb
Host smart-ea38ec61-aa07-4808-9574-f08c8270543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664725617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2664725617
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3378682873
Short name T195
Test name
Test status
Simulation time 123279899 ps
CPU time 1.21 seconds
Started May 12 03:03:32 PM PDT 24
Finished May 12 03:03:34 PM PDT 24
Peak memory 201068 kb
Host smart-9a155208-ac7a-4247-a1ab-7129399d53d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378682873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3378682873
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1947402954
Short name T542
Test name
Test status
Simulation time 3904102562 ps
CPU time 19.16 seconds
Started May 12 03:03:33 PM PDT 24
Finished May 12 03:03:53 PM PDT 24
Peak memory 201176 kb
Host smart-28c3b594-d43f-44ce-a4e4-fa490cc04537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947402954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1947402954
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3647052860
Short name T346
Test name
Test status
Simulation time 141327327 ps
CPU time 1.84 seconds
Started May 12 03:03:32 PM PDT 24
Finished May 12 03:03:35 PM PDT 24
Peak memory 200892 kb
Host smart-727e0f7d-b25b-4030-96f4-c76c376c5a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647052860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3647052860
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1554926025
Short name T221
Test name
Test status
Simulation time 155564859 ps
CPU time 1.2 seconds
Started May 12 03:03:33 PM PDT 24
Finished May 12 03:03:35 PM PDT 24
Peak memory 201068 kb
Host smart-f5bb058c-d800-4ddd-8742-65428fbb8e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554926025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1554926025
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.521723199
Short name T411
Test name
Test status
Simulation time 81945864 ps
CPU time 0.83 seconds
Started May 12 03:01:31 PM PDT 24
Finished May 12 03:01:33 PM PDT 24
Peak memory 200644 kb
Host smart-72e8d942-f727-4fc2-848b-4a1fd9de825e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521723199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.521723199
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2330883895
Short name T46
Test name
Test status
Simulation time 1229498574 ps
CPU time 5.6 seconds
Started May 12 03:01:29 PM PDT 24
Finished May 12 03:01:35 PM PDT 24
Peak memory 221508 kb
Host smart-7d8ec703-5941-4f23-a5df-10df180ee7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330883895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2330883895
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3634957844
Short name T168
Test name
Test status
Simulation time 244198812 ps
CPU time 1.09 seconds
Started May 12 03:01:24 PM PDT 24
Finished May 12 03:01:25 PM PDT 24
Peak memory 217924 kb
Host smart-1a32b2bc-24a0-4c55-996d-057e4d69ffbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634957844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3634957844
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3965697596
Short name T398
Test name
Test status
Simulation time 157820369 ps
CPU time 0.8 seconds
Started May 12 03:01:22 PM PDT 24
Finished May 12 03:01:24 PM PDT 24
Peak memory 200664 kb
Host smart-ce939f0f-a7e0-4853-a02f-3005bdc94c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965697596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3965697596
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2764028752
Short name T104
Test name
Test status
Simulation time 1501670624 ps
CPU time 5.41 seconds
Started May 12 03:01:23 PM PDT 24
Finished May 12 03:01:29 PM PDT 24
Peak memory 201048 kb
Host smart-f16d17dc-ad42-42bd-b459-056ca68861eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764028752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2764028752
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3242132531
Short name T67
Test name
Test status
Simulation time 8853387738 ps
CPU time 12.89 seconds
Started May 12 03:01:29 PM PDT 24
Finished May 12 03:01:42 PM PDT 24
Peak memory 217584 kb
Host smart-a25b3a78-8300-44a4-a172-fcc8ed19be6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242132531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3242132531
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.4246054314
Short name T474
Test name
Test status
Simulation time 156622973 ps
CPU time 1.2 seconds
Started May 12 03:01:24 PM PDT 24
Finished May 12 03:01:26 PM PDT 24
Peak memory 200872 kb
Host smart-26f7070f-24a9-42fd-8d6d-e0ebbfa62521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246054314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.4246054314
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.339714779
Short name T410
Test name
Test status
Simulation time 243447290 ps
CPU time 1.41 seconds
Started May 12 03:01:23 PM PDT 24
Finished May 12 03:01:25 PM PDT 24
Peak memory 201032 kb
Host smart-d14dc61d-0e64-4b28-b277-ebf738397307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339714779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.339714779
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3044699233
Short name T500
Test name
Test status
Simulation time 3095809169 ps
CPU time 13.66 seconds
Started May 12 03:01:29 PM PDT 24
Finished May 12 03:01:43 PM PDT 24
Peak memory 209400 kb
Host smart-09b1e0bf-fbcf-4984-87f6-e2ad3a42df32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044699233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3044699233
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2844363029
Short name T7
Test name
Test status
Simulation time 348916780 ps
CPU time 2.28 seconds
Started May 12 03:01:22 PM PDT 24
Finished May 12 03:01:25 PM PDT 24
Peak memory 200848 kb
Host smart-08681b75-4eb2-41dc-b8fb-75aad07c852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844363029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2844363029
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.846442023
Short name T218
Test name
Test status
Simulation time 183991135 ps
CPU time 1.29 seconds
Started May 12 03:01:22 PM PDT 24
Finished May 12 03:01:24 PM PDT 24
Peak memory 200828 kb
Host smart-17775e26-04f4-436c-99a8-cf686fc56f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846442023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.846442023
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2673798616
Short name T41
Test name
Test status
Simulation time 76579700 ps
CPU time 0.8 seconds
Started May 12 03:03:39 PM PDT 24
Finished May 12 03:03:40 PM PDT 24
Peak memory 200676 kb
Host smart-49cc8f0e-8aa6-44b7-a4a8-bc5a2d3050a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673798616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2673798616
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1461913802
Short name T437
Test name
Test status
Simulation time 1223919077 ps
CPU time 5.96 seconds
Started May 12 03:03:36 PM PDT 24
Finished May 12 03:03:43 PM PDT 24
Peak memory 218552 kb
Host smart-fd36bc42-3505-44fb-9c00-d1630dc944f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461913802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1461913802
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2143723282
Short name T240
Test name
Test status
Simulation time 243107418 ps
CPU time 1.13 seconds
Started May 12 03:03:37 PM PDT 24
Finished May 12 03:03:38 PM PDT 24
Peak memory 217952 kb
Host smart-d7da078f-5f43-4288-908b-cc0ffb9d8cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143723282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2143723282
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1875367693
Short name T378
Test name
Test status
Simulation time 99771676 ps
CPU time 0.75 seconds
Started May 12 03:03:33 PM PDT 24
Finished May 12 03:03:34 PM PDT 24
Peak memory 200616 kb
Host smart-ce5c03ba-64ab-4a34-969b-6a60ae5cbebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875367693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1875367693
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2691511656
Short name T442
Test name
Test status
Simulation time 1370294506 ps
CPU time 6.27 seconds
Started May 12 03:03:37 PM PDT 24
Finished May 12 03:03:44 PM PDT 24
Peak memory 201100 kb
Host smart-7bc61615-5cf6-4072-ad21-5be5a0c6c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691511656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2691511656
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2402120389
Short name T330
Test name
Test status
Simulation time 186152431 ps
CPU time 1.22 seconds
Started May 12 03:03:37 PM PDT 24
Finished May 12 03:03:39 PM PDT 24
Peak memory 200888 kb
Host smart-fd4f5b55-4cc5-43e0-b956-3b6736ea56a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402120389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2402120389
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.468459013
Short name T352
Test name
Test status
Simulation time 190201705 ps
CPU time 1.36 seconds
Started May 12 03:03:35 PM PDT 24
Finished May 12 03:03:36 PM PDT 24
Peak memory 201072 kb
Host smart-624bcb1a-107e-4b72-b1ed-c8686e37ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468459013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.468459013
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.4041716691
Short name T381
Test name
Test status
Simulation time 11533447313 ps
CPU time 44.23 seconds
Started May 12 03:03:36 PM PDT 24
Finished May 12 03:04:21 PM PDT 24
Peak memory 209328 kb
Host smart-187833c9-d9a7-4dd0-8ec6-467b29a8d5f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041716691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4041716691
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2007442536
Short name T186
Test name
Test status
Simulation time 106068906 ps
CPU time 1.46 seconds
Started May 12 03:03:38 PM PDT 24
Finished May 12 03:03:40 PM PDT 24
Peak memory 200856 kb
Host smart-07aad144-09d1-4624-a4bf-b7c3d56a1540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007442536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2007442536
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2642449178
Short name T525
Test name
Test status
Simulation time 67988653 ps
CPU time 0.79 seconds
Started May 12 03:03:39 PM PDT 24
Finished May 12 03:03:40 PM PDT 24
Peak memory 200840 kb
Host smart-dc3be98c-9b65-4997-94ad-bd25b26e5528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642449178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2642449178
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1067418745
Short name T133
Test name
Test status
Simulation time 92035401 ps
CPU time 0.88 seconds
Started May 12 03:03:40 PM PDT 24
Finished May 12 03:03:41 PM PDT 24
Peak memory 200628 kb
Host smart-dda0aa23-2165-4300-b06a-206a4924b125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067418745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1067418745
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3182188356
Short name T44
Test name
Test status
Simulation time 2367847460 ps
CPU time 8.89 seconds
Started May 12 03:03:38 PM PDT 24
Finished May 12 03:03:48 PM PDT 24
Peak memory 218048 kb
Host smart-fd057706-13da-42fe-a083-a5a4683a18b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182188356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3182188356
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1302141559
Short name T73
Test name
Test status
Simulation time 245023820 ps
CPU time 1.07 seconds
Started May 12 03:03:42 PM PDT 24
Finished May 12 03:03:44 PM PDT 24
Peak memory 218000 kb
Host smart-e54dd734-1972-458c-820f-c369a1d027d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302141559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1302141559
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2113215243
Short name T199
Test name
Test status
Simulation time 98492632 ps
CPU time 0.83 seconds
Started May 12 03:03:36 PM PDT 24
Finished May 12 03:03:38 PM PDT 24
Peak memory 200692 kb
Host smart-03172300-cdd2-4435-8494-11db8702cfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113215243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2113215243
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3489809341
Short name T331
Test name
Test status
Simulation time 783915854 ps
CPU time 4.53 seconds
Started May 12 03:03:40 PM PDT 24
Finished May 12 03:03:45 PM PDT 24
Peak memory 201060 kb
Host smart-f975d75f-a9ee-43dd-99e6-391a9744fd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489809341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3489809341
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.403616894
Short name T536
Test name
Test status
Simulation time 155151557 ps
CPU time 1.14 seconds
Started May 12 03:03:35 PM PDT 24
Finished May 12 03:03:37 PM PDT 24
Peak memory 200852 kb
Host smart-05c285fd-8089-4334-b247-a8e838efa194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403616894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.403616894
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1669911786
Short name T177
Test name
Test status
Simulation time 113370556 ps
CPU time 1.24 seconds
Started May 12 03:03:36 PM PDT 24
Finished May 12 03:03:38 PM PDT 24
Peak memory 201040 kb
Host smart-66997be7-d856-490e-80c1-cce845f7cfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669911786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1669911786
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.808855350
Short name T14
Test name
Test status
Simulation time 4598202057 ps
CPU time 20.38 seconds
Started May 12 03:03:40 PM PDT 24
Finished May 12 03:04:01 PM PDT 24
Peak memory 201164 kb
Host smart-e5416bed-21f7-413a-af98-17159eca11ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808855350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.808855350
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.270566521
Short name T486
Test name
Test status
Simulation time 295943153 ps
CPU time 2.12 seconds
Started May 12 03:03:36 PM PDT 24
Finished May 12 03:03:39 PM PDT 24
Peak memory 209112 kb
Host smart-213a0af9-6e4d-40aa-8f88-7a30eee4675b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270566521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.270566521
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1943908094
Short name T423
Test name
Test status
Simulation time 162038913 ps
CPU time 1.17 seconds
Started May 12 03:03:40 PM PDT 24
Finished May 12 03:03:42 PM PDT 24
Peak memory 200880 kb
Host smart-27f679ec-ba1c-4e2a-97fa-3d7547209471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943908094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1943908094
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2120300057
Short name T432
Test name
Test status
Simulation time 75790416 ps
CPU time 0.83 seconds
Started May 12 03:03:43 PM PDT 24
Finished May 12 03:03:45 PM PDT 24
Peak memory 200700 kb
Host smart-5ffcb5c9-cb5f-4fe0-8b70-0c1237626acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120300057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2120300057
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2667334093
Short name T239
Test name
Test status
Simulation time 1234964050 ps
CPU time 5.9 seconds
Started May 12 03:03:45 PM PDT 24
Finished May 12 03:03:51 PM PDT 24
Peak memory 218508 kb
Host smart-0fb19c57-53aa-4b09-9787-2ea637694093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667334093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2667334093
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.248000968
Short name T409
Test name
Test status
Simulation time 244076981 ps
CPU time 1.06 seconds
Started May 12 03:03:43 PM PDT 24
Finished May 12 03:03:45 PM PDT 24
Peak memory 218004 kb
Host smart-4d07e8e4-2c7c-47e7-af06-bcbc6eb1d792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248000968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.248000968
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1127177686
Short name T197
Test name
Test status
Simulation time 142690713 ps
CPU time 0.9 seconds
Started May 12 03:03:39 PM PDT 24
Finished May 12 03:03:40 PM PDT 24
Peak memory 200640 kb
Host smart-439dafad-9d43-487a-8c58-206eb57adef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127177686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1127177686
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.4003712070
Short name T327
Test name
Test status
Simulation time 2058014052 ps
CPU time 8.52 seconds
Started May 12 03:03:40 PM PDT 24
Finished May 12 03:03:49 PM PDT 24
Peak memory 201012 kb
Host smart-bbbe0eca-b280-45c6-bb93-42f6fbbb9cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003712070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.4003712070
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2367132106
Short name T388
Test name
Test status
Simulation time 167200182 ps
CPU time 1.37 seconds
Started May 12 03:03:48 PM PDT 24
Finished May 12 03:03:50 PM PDT 24
Peak memory 200852 kb
Host smart-d23d3004-1bde-4fb8-a519-c701275dad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367132106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2367132106
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.4147521861
Short name T348
Test name
Test status
Simulation time 245736380 ps
CPU time 1.75 seconds
Started May 12 03:03:41 PM PDT 24
Finished May 12 03:03:43 PM PDT 24
Peak memory 201032 kb
Host smart-007aafe7-8126-4504-a943-66888549c891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147521861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4147521861
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.996061180
Short name T259
Test name
Test status
Simulation time 179734208 ps
CPU time 1.3 seconds
Started May 12 03:03:43 PM PDT 24
Finished May 12 03:03:45 PM PDT 24
Peak memory 200700 kb
Host smart-cbbd28d9-b59b-447e-a13f-5dec9015164c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996061180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.996061180
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.202501067
Short name T167
Test name
Test status
Simulation time 263289024 ps
CPU time 1.92 seconds
Started May 12 03:03:39 PM PDT 24
Finished May 12 03:03:42 PM PDT 24
Peak memory 200864 kb
Host smart-2157c9ed-beaf-4b31-814b-20d73b1a6f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202501067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.202501067
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1674672918
Short name T450
Test name
Test status
Simulation time 138606152 ps
CPU time 1.13 seconds
Started May 12 03:03:42 PM PDT 24
Finished May 12 03:03:43 PM PDT 24
Peak memory 200880 kb
Host smart-c7cef334-d2d2-4b80-9e72-b213e400a340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674672918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1674672918
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1896366719
Short name T181
Test name
Test status
Simulation time 61790044 ps
CPU time 0.76 seconds
Started May 12 03:03:48 PM PDT 24
Finished May 12 03:03:49 PM PDT 24
Peak memory 200708 kb
Host smart-d9c29e83-b49e-410b-923a-19f8c41c88c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896366719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1896366719
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1144585776
Short name T246
Test name
Test status
Simulation time 1886333362 ps
CPU time 7.34 seconds
Started May 12 03:03:46 PM PDT 24
Finished May 12 03:03:54 PM PDT 24
Peak memory 217896 kb
Host smart-853c5e33-d5ca-4693-b4c3-82529a6e50b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144585776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1144585776
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.777928791
Short name T489
Test name
Test status
Simulation time 244373262 ps
CPU time 1.15 seconds
Started May 12 03:03:46 PM PDT 24
Finished May 12 03:03:48 PM PDT 24
Peak memory 217988 kb
Host smart-2be3e798-59f2-4eb2-91c4-f9c033585562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777928791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.777928791
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3340630057
Short name T201
Test name
Test status
Simulation time 77364324 ps
CPU time 0.76 seconds
Started May 12 03:03:44 PM PDT 24
Finished May 12 03:03:46 PM PDT 24
Peak memory 200660 kb
Host smart-32dee922-6c80-4982-becd-bbee3400b5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340630057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3340630057
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1390643932
Short name T147
Test name
Test status
Simulation time 1727743820 ps
CPU time 7.45 seconds
Started May 12 03:03:43 PM PDT 24
Finished May 12 03:03:51 PM PDT 24
Peak memory 201012 kb
Host smart-d780de9d-b7d5-4565-8370-a716b7a3630f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390643932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1390643932
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.4191166775
Short name T323
Test name
Test status
Simulation time 152823595 ps
CPU time 1.17 seconds
Started May 12 03:03:43 PM PDT 24
Finished May 12 03:03:45 PM PDT 24
Peak memory 200796 kb
Host smart-b72011be-fac9-4f9e-94ee-854b8302d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191166775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.4191166775
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.930430905
Short name T392
Test name
Test status
Simulation time 197898220 ps
CPU time 1.37 seconds
Started May 12 03:03:45 PM PDT 24
Finished May 12 03:03:47 PM PDT 24
Peak memory 201084 kb
Host smart-f94cfc43-2592-4ab1-9e0e-8cb50ec0f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930430905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.930430905
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.569651281
Short name T2
Test name
Test status
Simulation time 368692938 ps
CPU time 2.44 seconds
Started May 12 03:03:44 PM PDT 24
Finished May 12 03:03:48 PM PDT 24
Peak memory 201064 kb
Host smart-545091ff-b8e1-4287-abc3-bb99d09386ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569651281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.569651281
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.197287300
Short name T505
Test name
Test status
Simulation time 241781297 ps
CPU time 1.51 seconds
Started May 12 03:03:45 PM PDT 24
Finished May 12 03:03:47 PM PDT 24
Peak memory 200980 kb
Host smart-a63b4d07-394a-4302-ab82-a687cb0fd85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197287300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.197287300
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1010338698
Short name T157
Test name
Test status
Simulation time 70192240 ps
CPU time 0.77 seconds
Started May 12 03:03:49 PM PDT 24
Finished May 12 03:03:50 PM PDT 24
Peak memory 200684 kb
Host smart-6f2c94d8-889c-45e2-8aba-9fea6f2fd1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010338698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1010338698
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3704441156
Short name T34
Test name
Test status
Simulation time 1898704735 ps
CPU time 7.85 seconds
Started May 12 03:03:46 PM PDT 24
Finished May 12 03:03:54 PM PDT 24
Peak memory 218504 kb
Host smart-ccbc0b02-9588-47ad-a6fc-db0088fabc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704441156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3704441156
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4267933115
Short name T483
Test name
Test status
Simulation time 243911307 ps
CPU time 1.1 seconds
Started May 12 03:03:51 PM PDT 24
Finished May 12 03:03:53 PM PDT 24
Peak memory 217972 kb
Host smart-4a7031a7-94dd-410a-92cf-b7471f83e079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267933115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4267933115
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1277028523
Short name T433
Test name
Test status
Simulation time 140279059 ps
CPU time 0.86 seconds
Started May 12 03:03:45 PM PDT 24
Finished May 12 03:03:47 PM PDT 24
Peak memory 200676 kb
Host smart-7efbc05a-c85a-4b95-9616-28096760d945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277028523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1277028523
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3297516032
Short name T125
Test name
Test status
Simulation time 1924044904 ps
CPU time 7.31 seconds
Started May 12 03:03:47 PM PDT 24
Finished May 12 03:03:55 PM PDT 24
Peak memory 201052 kb
Host smart-61d1c816-dcd1-4604-92e8-2aa9b60a16ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297516032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3297516032
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3359378850
Short name T169
Test name
Test status
Simulation time 146651623 ps
CPU time 1.04 seconds
Started May 12 03:03:48 PM PDT 24
Finished May 12 03:03:49 PM PDT 24
Peak memory 200892 kb
Host smart-1000562d-9baa-4e0b-826c-7d8964541ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359378850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3359378850
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3223164903
Short name T513
Test name
Test status
Simulation time 118869503 ps
CPU time 1.19 seconds
Started May 12 03:03:48 PM PDT 24
Finished May 12 03:03:49 PM PDT 24
Peak memory 201052 kb
Host smart-9c5714d9-e502-496c-b7df-c8fafca2bee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223164903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3223164903
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2890514666
Short name T213
Test name
Test status
Simulation time 8510844819 ps
CPU time 37.19 seconds
Started May 12 03:03:52 PM PDT 24
Finished May 12 03:04:29 PM PDT 24
Peak memory 209404 kb
Host smart-a5358ff0-be7d-4e84-89ee-f6f23caa196d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890514666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2890514666
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3975846564
Short name T314
Test name
Test status
Simulation time 267152676 ps
CPU time 2.01 seconds
Started May 12 03:03:49 PM PDT 24
Finished May 12 03:03:52 PM PDT 24
Peak memory 200980 kb
Host smart-805949db-fdb6-4576-a78c-54140595774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975846564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3975846564
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2873456586
Short name T318
Test name
Test status
Simulation time 211940556 ps
CPU time 1.26 seconds
Started May 12 03:03:48 PM PDT 24
Finished May 12 03:03:50 PM PDT 24
Peak memory 200888 kb
Host smart-5608459e-fc7e-4666-b4ce-901cf2348b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873456586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2873456586
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1886689364
Short name T380
Test name
Test status
Simulation time 63498604 ps
CPU time 0.76 seconds
Started May 12 03:03:54 PM PDT 24
Finished May 12 03:03:55 PM PDT 24
Peak memory 200712 kb
Host smart-4bf1c75d-6533-4590-af28-8a28c1f356b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886689364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1886689364
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1670141721
Short name T463
Test name
Test status
Simulation time 1228047660 ps
CPU time 5.6 seconds
Started May 12 03:03:50 PM PDT 24
Finished May 12 03:03:56 PM PDT 24
Peak memory 222492 kb
Host smart-79b046db-bd2a-416e-adf0-3d5d062e5209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670141721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1670141721
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3727099030
Short name T291
Test name
Test status
Simulation time 243985266 ps
CPU time 1.02 seconds
Started May 12 03:03:55 PM PDT 24
Finished May 12 03:03:56 PM PDT 24
Peak memory 218020 kb
Host smart-9277a348-8736-4df5-8e00-7fe580e6e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727099030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3727099030
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.602585556
Short name T417
Test name
Test status
Simulation time 90566845 ps
CPU time 0.77 seconds
Started May 12 03:03:53 PM PDT 24
Finished May 12 03:03:54 PM PDT 24
Peak memory 200620 kb
Host smart-6a685797-55c7-46d3-aa3d-94c806981caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602585556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.602585556
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3665877942
Short name T227
Test name
Test status
Simulation time 1847334905 ps
CPU time 7.03 seconds
Started May 12 03:03:51 PM PDT 24
Finished May 12 03:03:58 PM PDT 24
Peak memory 201096 kb
Host smart-bd92eb8b-1f65-4107-ace5-4719dd998c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665877942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3665877942
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3714051847
Short name T224
Test name
Test status
Simulation time 92913056 ps
CPU time 1.02 seconds
Started May 12 03:03:50 PM PDT 24
Finished May 12 03:03:52 PM PDT 24
Peak memory 200828 kb
Host smart-aea45f43-2a5b-4e36-981b-c5755dbba6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714051847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3714051847
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.641238792
Short name T368
Test name
Test status
Simulation time 120488987 ps
CPU time 1.29 seconds
Started May 12 03:03:53 PM PDT 24
Finished May 12 03:03:55 PM PDT 24
Peak memory 200992 kb
Host smart-b618fefc-d95a-4d02-acbf-3aadd0833b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641238792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.641238792
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.721365280
Short name T475
Test name
Test status
Simulation time 2928970083 ps
CPU time 15.99 seconds
Started May 12 03:03:55 PM PDT 24
Finished May 12 03:04:11 PM PDT 24
Peak memory 201196 kb
Host smart-024b8968-81dc-4731-b227-41444804e82d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721365280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.721365280
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.421114082
Short name T344
Test name
Test status
Simulation time 121665435 ps
CPU time 1.49 seconds
Started May 12 03:03:49 PM PDT 24
Finished May 12 03:03:51 PM PDT 24
Peak memory 200876 kb
Host smart-957b72f4-c0e2-4560-8290-add22ae8f3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421114082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.421114082
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1051850955
Short name T372
Test name
Test status
Simulation time 106238536 ps
CPU time 1.09 seconds
Started May 12 03:03:51 PM PDT 24
Finished May 12 03:03:53 PM PDT 24
Peak memory 200856 kb
Host smart-168f197a-5766-4c55-8829-d8ba60947e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051850955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1051850955
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2712686110
Short name T527
Test name
Test status
Simulation time 71449610 ps
CPU time 0.78 seconds
Started May 12 03:03:56 PM PDT 24
Finished May 12 03:03:57 PM PDT 24
Peak memory 200624 kb
Host smart-05b85e90-3655-4dfe-883f-f4ab132eac41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712686110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2712686110
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1454053982
Short name T56
Test name
Test status
Simulation time 2161248501 ps
CPU time 7.46 seconds
Started May 12 03:03:52 PM PDT 24
Finished May 12 03:04:00 PM PDT 24
Peak memory 222576 kb
Host smart-17cb61c2-c0fa-4022-ae15-11a3792df7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454053982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1454053982
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1126548688
Short name T295
Test name
Test status
Simulation time 244108683 ps
CPU time 1.06 seconds
Started May 12 03:03:56 PM PDT 24
Finished May 12 03:03:58 PM PDT 24
Peak memory 218140 kb
Host smart-7cd35958-ff9a-4576-9b1b-7f4abba07a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126548688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1126548688
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.977025873
Short name T293
Test name
Test status
Simulation time 129412967 ps
CPU time 0.81 seconds
Started May 12 03:03:56 PM PDT 24
Finished May 12 03:03:58 PM PDT 24
Peak memory 200596 kb
Host smart-b8eb96f0-6db5-4c0a-9049-59aaf83d1d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977025873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.977025873
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.349210225
Short name T341
Test name
Test status
Simulation time 1515423869 ps
CPU time 5.77 seconds
Started May 12 03:03:53 PM PDT 24
Finished May 12 03:04:00 PM PDT 24
Peak memory 201252 kb
Host smart-bef60df8-213e-4da2-9f6c-95230d57f703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349210225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.349210225
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1386180896
Short name T3
Test name
Test status
Simulation time 143940508 ps
CPU time 1.18 seconds
Started May 12 03:03:56 PM PDT 24
Finished May 12 03:03:58 PM PDT 24
Peak memory 200988 kb
Host smart-8f7eed96-66a8-4a57-8ae4-4ac8af728eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386180896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1386180896
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1471109066
Short name T202
Test name
Test status
Simulation time 126623893 ps
CPU time 1.16 seconds
Started May 12 03:03:53 PM PDT 24
Finished May 12 03:03:55 PM PDT 24
Peak memory 200960 kb
Host smart-2b93018e-934c-44a6-b308-72d5ccf7aa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471109066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1471109066
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3640247908
Short name T225
Test name
Test status
Simulation time 9957352751 ps
CPU time 37.02 seconds
Started May 12 03:03:52 PM PDT 24
Finished May 12 03:04:30 PM PDT 24
Peak memory 209372 kb
Host smart-c733d555-6048-40d7-8398-c229243283e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640247908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3640247908
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.255601136
Short name T502
Test name
Test status
Simulation time 144702158 ps
CPU time 1.83 seconds
Started May 12 03:03:57 PM PDT 24
Finished May 12 03:04:00 PM PDT 24
Peak memory 201024 kb
Host smart-f20b7ded-d328-4552-8a41-2bbcfb34f212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255601136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.255601136
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2891319871
Short name T152
Test name
Test status
Simulation time 116578354 ps
CPU time 0.93 seconds
Started May 12 03:03:53 PM PDT 24
Finished May 12 03:03:54 PM PDT 24
Peak memory 200812 kb
Host smart-45b1e097-5f50-45f2-9eb1-5d68aed1be7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891319871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2891319871
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3574922459
Short name T482
Test name
Test status
Simulation time 70701806 ps
CPU time 0.82 seconds
Started May 12 03:04:01 PM PDT 24
Finished May 12 03:04:02 PM PDT 24
Peak memory 200712 kb
Host smart-9d3ae9d6-1f0a-4356-a416-df899e26a590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574922459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3574922459
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2530756263
Short name T254
Test name
Test status
Simulation time 1892219909 ps
CPU time 6.86 seconds
Started May 12 03:04:00 PM PDT 24
Finished May 12 03:04:07 PM PDT 24
Peak memory 218416 kb
Host smart-6425f286-a495-4bc8-b8d5-f0ea58458f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530756263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2530756263
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3491787420
Short name T153
Test name
Test status
Simulation time 244943535 ps
CPU time 1.11 seconds
Started May 12 03:03:55 PM PDT 24
Finished May 12 03:03:57 PM PDT 24
Peak memory 217956 kb
Host smart-83d2e644-31a7-4202-8bf1-18aaae8c7e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491787420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3491787420
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3047475329
Short name T523
Test name
Test status
Simulation time 88582446 ps
CPU time 0.77 seconds
Started May 12 03:03:52 PM PDT 24
Finished May 12 03:03:53 PM PDT 24
Peak memory 200664 kb
Host smart-0e9d630e-5895-4672-9356-176de8483aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047475329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3047475329
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4079135107
Short name T220
Test name
Test status
Simulation time 802365589 ps
CPU time 4.41 seconds
Started May 12 03:03:55 PM PDT 24
Finished May 12 03:04:00 PM PDT 24
Peak memory 201040 kb
Host smart-cc8a2f05-b787-48bd-9281-acd30429d9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079135107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4079135107
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3881878331
Short name T29
Test name
Test status
Simulation time 162622539 ps
CPU time 1.19 seconds
Started May 12 03:03:56 PM PDT 24
Finished May 12 03:03:58 PM PDT 24
Peak memory 200852 kb
Host smart-b7318d96-7e04-4e13-a60e-df2a748a236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881878331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3881878331
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1649625688
Short name T248
Test name
Test status
Simulation time 253276547 ps
CPU time 1.56 seconds
Started May 12 03:03:56 PM PDT 24
Finished May 12 03:03:58 PM PDT 24
Peak memory 201012 kb
Host smart-1d13108f-a65c-4dba-b24f-d8aecf449afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649625688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1649625688
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.120287385
Short name T326
Test name
Test status
Simulation time 6506750090 ps
CPU time 33.55 seconds
Started May 12 03:03:57 PM PDT 24
Finished May 12 03:04:31 PM PDT 24
Peak memory 210136 kb
Host smart-7b5be6cd-7dc2-4666-b682-f38b711e149a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120287385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.120287385
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.572978336
Short name T506
Test name
Test status
Simulation time 314689991 ps
CPU time 1.82 seconds
Started May 12 03:03:51 PM PDT 24
Finished May 12 03:03:53 PM PDT 24
Peak memory 200844 kb
Host smart-45d07446-193e-491b-abb4-d191bee2a783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572978336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.572978336
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4214374431
Short name T283
Test name
Test status
Simulation time 135112212 ps
CPU time 1.19 seconds
Started May 12 03:03:54 PM PDT 24
Finished May 12 03:03:56 PM PDT 24
Peak memory 200764 kb
Host smart-de5d5a0e-b24f-4d40-9da3-fb0fe72502db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214374431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4214374431
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3886911932
Short name T426
Test name
Test status
Simulation time 61445218 ps
CPU time 0.78 seconds
Started May 12 03:03:56 PM PDT 24
Finished May 12 03:03:58 PM PDT 24
Peak memory 200688 kb
Host smart-09b2e725-0d40-4f7b-af28-cbfbcd7edc05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886911932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3886911932
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3379137335
Short name T35
Test name
Test status
Simulation time 1886578616 ps
CPU time 6.79 seconds
Started May 12 03:04:02 PM PDT 24
Finished May 12 03:04:10 PM PDT 24
Peak memory 217568 kb
Host smart-5b010116-f980-4934-b84d-eb156a8ae6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379137335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3379137335
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3094943359
Short name T383
Test name
Test status
Simulation time 244166123 ps
CPU time 1.2 seconds
Started May 12 03:03:56 PM PDT 24
Finished May 12 03:03:57 PM PDT 24
Peak memory 218020 kb
Host smart-b16a9aa6-260f-4970-bfa8-7f5a022cac71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094943359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3094943359
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1025808009
Short name T509
Test name
Test status
Simulation time 200737852 ps
CPU time 0.93 seconds
Started May 12 03:03:58 PM PDT 24
Finished May 12 03:03:59 PM PDT 24
Peak memory 200680 kb
Host smart-a43b86bd-6b4e-4b49-b159-f713ec5cccc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025808009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1025808009
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1430619541
Short name T276
Test name
Test status
Simulation time 1432175952 ps
CPU time 5.97 seconds
Started May 12 03:03:56 PM PDT 24
Finished May 12 03:04:03 PM PDT 24
Peak memory 201056 kb
Host smart-05fd04e0-766b-4aed-a583-3c6c7cd8f57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430619541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1430619541
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3543316865
Short name T77
Test name
Test status
Simulation time 148191266 ps
CPU time 1.2 seconds
Started May 12 03:03:57 PM PDT 24
Finished May 12 03:03:59 PM PDT 24
Peak memory 200892 kb
Host smart-4c23bb98-b3d3-4fab-9e84-24be27687bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543316865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3543316865
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2977359391
Short name T313
Test name
Test status
Simulation time 230657577 ps
CPU time 1.49 seconds
Started May 12 03:03:57 PM PDT 24
Finished May 12 03:03:59 PM PDT 24
Peak memory 201088 kb
Host smart-ee154e63-7003-4e1b-b403-d56328d2fc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977359391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2977359391
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1495962469
Short name T375
Test name
Test status
Simulation time 6490376038 ps
CPU time 26.23 seconds
Started May 12 03:04:01 PM PDT 24
Finished May 12 03:04:28 PM PDT 24
Peak memory 217256 kb
Host smart-039f7fff-d7ee-4608-a48e-cbae150f77ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495962469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1495962469
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3136343912
Short name T52
Test name
Test status
Simulation time 341535066 ps
CPU time 2.34 seconds
Started May 12 03:03:57 PM PDT 24
Finished May 12 03:04:00 PM PDT 24
Peak memory 200864 kb
Host smart-922965df-4ea8-49a5-81d5-0055184fc980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136343912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3136343912
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3749939914
Short name T163
Test name
Test status
Simulation time 216913276 ps
CPU time 1.41 seconds
Started May 12 03:03:57 PM PDT 24
Finished May 12 03:03:59 PM PDT 24
Peak memory 201052 kb
Host smart-e5712ec3-e3fd-4cf7-9fab-3e6cc56cbe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749939914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3749939914
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3049191682
Short name T255
Test name
Test status
Simulation time 68273062 ps
CPU time 0.75 seconds
Started May 12 03:04:00 PM PDT 24
Finished May 12 03:04:01 PM PDT 24
Peak memory 200616 kb
Host smart-c85dbb9c-8373-433f-a952-4cc48c6280f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049191682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3049191682
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.629907738
Short name T58
Test name
Test status
Simulation time 1225287928 ps
CPU time 5.57 seconds
Started May 12 03:04:03 PM PDT 24
Finished May 12 03:04:09 PM PDT 24
Peak memory 222496 kb
Host smart-08061cf1-b7f9-44ab-b503-0cd156ff87ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629907738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.629907738
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1559098442
Short name T303
Test name
Test status
Simulation time 243862577 ps
CPU time 1.11 seconds
Started May 12 03:03:59 PM PDT 24
Finished May 12 03:04:01 PM PDT 24
Peak memory 218028 kb
Host smart-47847c76-9ca9-4fc5-b651-a4a37acedb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559098442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1559098442
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2868839578
Short name T364
Test name
Test status
Simulation time 186041241 ps
CPU time 0.86 seconds
Started May 12 03:04:03 PM PDT 24
Finished May 12 03:04:05 PM PDT 24
Peak memory 200660 kb
Host smart-31aa22b8-c994-48a4-87d4-5d61029fa4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868839578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2868839578
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1923770150
Short name T146
Test name
Test status
Simulation time 966586179 ps
CPU time 5.14 seconds
Started May 12 03:04:01 PM PDT 24
Finished May 12 03:04:07 PM PDT 24
Peak memory 200996 kb
Host smart-c31f5e4a-fcdb-4891-861e-09f6603976ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923770150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1923770150
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1233296821
Short name T524
Test name
Test status
Simulation time 151568313 ps
CPU time 1.16 seconds
Started May 12 03:03:59 PM PDT 24
Finished May 12 03:04:01 PM PDT 24
Peak memory 200912 kb
Host smart-e7d512a3-2977-4fc9-a2c5-d77a4479d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233296821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1233296821
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1392666588
Short name T162
Test name
Test status
Simulation time 115199555 ps
CPU time 1.25 seconds
Started May 12 03:03:57 PM PDT 24
Finished May 12 03:03:59 PM PDT 24
Peak memory 201060 kb
Host smart-db1cde7c-77da-48a9-b249-45ed7b29d7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392666588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1392666588
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3885789730
Short name T28
Test name
Test status
Simulation time 12699334362 ps
CPU time 43.77 seconds
Started May 12 03:03:59 PM PDT 24
Finished May 12 03:04:44 PM PDT 24
Peak memory 209364 kb
Host smart-1391e56b-d37a-477a-b30b-1a6678f9d521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885789730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3885789730
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3576089601
Short name T288
Test name
Test status
Simulation time 365706100 ps
CPU time 2.48 seconds
Started May 12 03:04:01 PM PDT 24
Finished May 12 03:04:04 PM PDT 24
Peak memory 200848 kb
Host smart-cc4a68c6-4354-42e5-a0e7-ba7c41c85ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576089601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3576089601
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2744267909
Short name T436
Test name
Test status
Simulation time 230732035 ps
CPU time 1.42 seconds
Started May 12 03:04:01 PM PDT 24
Finished May 12 03:04:03 PM PDT 24
Peak memory 200976 kb
Host smart-8006ba37-98d0-43c9-bd70-bb7b326d92af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744267909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2744267909
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.671581242
Short name T282
Test name
Test status
Simulation time 61861004 ps
CPU time 0.74 seconds
Started May 12 03:01:31 PM PDT 24
Finished May 12 03:01:32 PM PDT 24
Peak memory 200708 kb
Host smart-56482109-5191-4dd7-a95d-f82137ff75ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671581242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.671581242
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1048927565
Short name T298
Test name
Test status
Simulation time 245109009 ps
CPU time 1.07 seconds
Started May 12 03:01:28 PM PDT 24
Finished May 12 03:01:30 PM PDT 24
Peak memory 218008 kb
Host smart-0d1b1a57-3c7d-4cfc-98cc-ea4d16fe7565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048927565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1048927565
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.51513835
Short name T468
Test name
Test status
Simulation time 112196698 ps
CPU time 0.78 seconds
Started May 12 03:01:29 PM PDT 24
Finished May 12 03:01:31 PM PDT 24
Peak memory 200684 kb
Host smart-364c88cd-d2c2-49ea-84d2-433f7157eee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51513835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.51513835
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1566006369
Short name T235
Test name
Test status
Simulation time 1810797096 ps
CPU time 7.9 seconds
Started May 12 03:01:31 PM PDT 24
Finished May 12 03:01:40 PM PDT 24
Peak memory 200936 kb
Host smart-0c7e6d99-9204-4c69-9498-a29d2062edc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566006369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1566006369
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3149519597
Short name T324
Test name
Test status
Simulation time 111524586 ps
CPU time 1.02 seconds
Started May 12 03:01:31 PM PDT 24
Finished May 12 03:01:33 PM PDT 24
Peak memory 200776 kb
Host smart-9ad2d422-b5e4-4ee0-bf29-a18dd7a747ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149519597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3149519597
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2241586933
Short name T141
Test name
Test status
Simulation time 118814996 ps
CPU time 1.19 seconds
Started May 12 03:01:28 PM PDT 24
Finished May 12 03:01:30 PM PDT 24
Peak memory 201024 kb
Host smart-7f8ac5a1-f655-491c-ae6a-f995b2ebad04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241586933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2241586933
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2836819488
Short name T322
Test name
Test status
Simulation time 11028041203 ps
CPU time 35.79 seconds
Started May 12 03:01:32 PM PDT 24
Finished May 12 03:02:08 PM PDT 24
Peak memory 209536 kb
Host smart-f8a935cc-da63-43ed-a26d-296fdc64a210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836819488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2836819488
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2210430757
Short name T176
Test name
Test status
Simulation time 382320266 ps
CPU time 2.72 seconds
Started May 12 03:01:29 PM PDT 24
Finished May 12 03:01:32 PM PDT 24
Peak memory 200844 kb
Host smart-e4517b5a-4141-4fea-b993-f1f377877016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210430757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2210430757
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1752153696
Short name T131
Test name
Test status
Simulation time 126984439 ps
CPU time 1.13 seconds
Started May 12 03:01:28 PM PDT 24
Finished May 12 03:01:30 PM PDT 24
Peak memory 200864 kb
Host smart-dacb9c70-adbb-4316-a137-9944dd19f9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752153696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1752153696
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3190956899
Short name T172
Test name
Test status
Simulation time 66867450 ps
CPU time 0.76 seconds
Started May 12 03:01:34 PM PDT 24
Finished May 12 03:01:35 PM PDT 24
Peak memory 200672 kb
Host smart-203e84df-286d-47e4-b667-ebbc197338ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190956899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3190956899
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4188913194
Short name T5
Test name
Test status
Simulation time 244190770 ps
CPU time 1.15 seconds
Started May 12 03:01:32 PM PDT 24
Finished May 12 03:01:34 PM PDT 24
Peak memory 218192 kb
Host smart-eb89c1d0-ee23-4b96-b561-b820d1694aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188913194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.4188913194
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2339370691
Short name T526
Test name
Test status
Simulation time 169277105 ps
CPU time 0.92 seconds
Started May 12 03:01:31 PM PDT 24
Finished May 12 03:01:33 PM PDT 24
Peak memory 200680 kb
Host smart-bf78c160-de36-456f-b304-2cd9ffce4210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339370691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2339370691
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3193203446
Short name T428
Test name
Test status
Simulation time 1962333226 ps
CPU time 8.13 seconds
Started May 12 03:01:33 PM PDT 24
Finished May 12 03:01:41 PM PDT 24
Peak memory 201036 kb
Host smart-16d857a0-0ea8-437a-812f-9f659246e245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193203446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3193203446
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.618909966
Short name T307
Test name
Test status
Simulation time 101039387 ps
CPU time 1.06 seconds
Started May 12 03:01:33 PM PDT 24
Finished May 12 03:01:35 PM PDT 24
Peak memory 200912 kb
Host smart-7d107f86-1986-4298-8dad-36a98b6d3b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618909966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.618909966
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3101506469
Short name T518
Test name
Test status
Simulation time 120040799 ps
CPU time 1.23 seconds
Started May 12 03:01:28 PM PDT 24
Finished May 12 03:01:29 PM PDT 24
Peak memory 201004 kb
Host smart-53708594-e895-472c-a398-a4407dc1fd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101506469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3101506469
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3019429926
Short name T466
Test name
Test status
Simulation time 4301598308 ps
CPU time 19.46 seconds
Started May 12 03:01:32 PM PDT 24
Finished May 12 03:01:52 PM PDT 24
Peak memory 201236 kb
Host smart-47d5c64d-a4e0-4428-aa42-1429c96a4048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019429926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3019429926
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2350241721
Short name T180
Test name
Test status
Simulation time 122409436 ps
CPU time 1.62 seconds
Started May 12 03:01:33 PM PDT 24
Finished May 12 03:01:35 PM PDT 24
Peak memory 209064 kb
Host smart-3918327a-4c0d-4773-bac2-0afa4d62563a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350241721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2350241721
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.93208956
Short name T144
Test name
Test status
Simulation time 85538105 ps
CPU time 0.89 seconds
Started May 12 03:01:32 PM PDT 24
Finished May 12 03:01:33 PM PDT 24
Peak memory 200912 kb
Host smart-25c5a8cf-26d0-41d0-910b-1536cfddb356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93208956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.93208956
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3169981394
Short name T541
Test name
Test status
Simulation time 96692093 ps
CPU time 0.85 seconds
Started May 12 03:01:40 PM PDT 24
Finished May 12 03:01:41 PM PDT 24
Peak memory 200628 kb
Host smart-83317660-bb6d-4132-b955-e801d97b693e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169981394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3169981394
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1682712982
Short name T415
Test name
Test status
Simulation time 1223961211 ps
CPU time 5.69 seconds
Started May 12 03:01:38 PM PDT 24
Finished May 12 03:01:44 PM PDT 24
Peak memory 222032 kb
Host smart-d370392d-b38e-4bf9-b68c-e81b961fd1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682712982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1682712982
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3872174913
Short name T308
Test name
Test status
Simulation time 244789105 ps
CPU time 1.06 seconds
Started May 12 03:01:39 PM PDT 24
Finished May 12 03:01:40 PM PDT 24
Peak memory 218000 kb
Host smart-779c3b17-6067-4555-86df-d936f80f20fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872174913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3872174913
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.4118808281
Short name T233
Test name
Test status
Simulation time 223664458 ps
CPU time 0.93 seconds
Started May 12 03:01:37 PM PDT 24
Finished May 12 03:01:38 PM PDT 24
Peak memory 200612 kb
Host smart-d8cebf2b-9d1b-4ad3-96af-184664e16755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118808281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.4118808281
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.565043441
Short name T226
Test name
Test status
Simulation time 1104336354 ps
CPU time 5.5 seconds
Started May 12 03:01:38 PM PDT 24
Finished May 12 03:01:44 PM PDT 24
Peak memory 201072 kb
Host smart-58843348-2de6-48a4-89a9-63285d0f1d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565043441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.565043441
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2466411032
Short name T512
Test name
Test status
Simulation time 184743158 ps
CPU time 1.25 seconds
Started May 12 03:01:41 PM PDT 24
Finished May 12 03:01:42 PM PDT 24
Peak memory 200880 kb
Host smart-ad37a210-da7c-427f-97d1-241ff7fc53e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466411032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2466411032
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.585657338
Short name T455
Test name
Test status
Simulation time 260577602 ps
CPU time 1.62 seconds
Started May 12 03:01:37 PM PDT 24
Finished May 12 03:01:39 PM PDT 24
Peak memory 201064 kb
Host smart-33a56020-f303-4a28-a459-2b4a9e4af456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585657338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.585657338
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3351279592
Short name T386
Test name
Test status
Simulation time 6136085499 ps
CPU time 24.71 seconds
Started May 12 03:01:40 PM PDT 24
Finished May 12 03:02:05 PM PDT 24
Peak memory 209336 kb
Host smart-867a4307-f7be-4dfb-96bd-1e5df91a9d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351279592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3351279592
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3367722221
Short name T251
Test name
Test status
Simulation time 147693835 ps
CPU time 2.04 seconds
Started May 12 03:01:40 PM PDT 24
Finished May 12 03:01:42 PM PDT 24
Peak memory 200852 kb
Host smart-5c2a9eb3-09f9-4dd7-b042-767085b63706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367722221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3367722221
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1633359439
Short name T528
Test name
Test status
Simulation time 170372748 ps
CPU time 1.22 seconds
Started May 12 03:01:41 PM PDT 24
Finished May 12 03:01:42 PM PDT 24
Peak memory 200984 kb
Host smart-17e16b90-125e-471e-8d0f-994f2ba59bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633359439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1633359439
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.7918915
Short name T335
Test name
Test status
Simulation time 61443596 ps
CPU time 0.76 seconds
Started May 12 03:01:47 PM PDT 24
Finished May 12 03:01:48 PM PDT 24
Peak memory 200700 kb
Host smart-f53dbc9a-1e8f-452a-8b54-979361887332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7918915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.7918915
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2926457129
Short name T261
Test name
Test status
Simulation time 1894079017 ps
CPU time 8.16 seconds
Started May 12 03:01:42 PM PDT 24
Finished May 12 03:01:51 PM PDT 24
Peak memory 218480 kb
Host smart-022ded6c-8a2c-495b-83da-68690749b9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926457129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2926457129
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3328936621
Short name T50
Test name
Test status
Simulation time 245107872 ps
CPU time 1.09 seconds
Started May 12 03:01:46 PM PDT 24
Finished May 12 03:01:48 PM PDT 24
Peak memory 217968 kb
Host smart-f48680f1-b398-46c1-b8fc-eee856d79cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328936621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3328936621
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.460223691
Short name T21
Test name
Test status
Simulation time 203365698 ps
CPU time 0.88 seconds
Started May 12 03:01:42 PM PDT 24
Finished May 12 03:01:43 PM PDT 24
Peak memory 200676 kb
Host smart-206d359e-e95f-413f-a810-7922406d3d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460223691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.460223691
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.369283108
Short name T272
Test name
Test status
Simulation time 732528243 ps
CPU time 3.82 seconds
Started May 12 03:01:38 PM PDT 24
Finished May 12 03:01:43 PM PDT 24
Peak memory 201064 kb
Host smart-72380862-3ed5-445e-9143-227014164a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369283108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.369283108
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3813497521
Short name T498
Test name
Test status
Simulation time 157783346 ps
CPU time 1.3 seconds
Started May 12 03:01:42 PM PDT 24
Finished May 12 03:01:43 PM PDT 24
Peak memory 200836 kb
Host smart-70cc9aa1-0c15-4ac3-ab95-fe43c0f538f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813497521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3813497521
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3411344419
Short name T312
Test name
Test status
Simulation time 109523547 ps
CPU time 1.24 seconds
Started May 12 03:01:38 PM PDT 24
Finished May 12 03:01:40 PM PDT 24
Peak memory 200988 kb
Host smart-37df4bee-9ca8-4630-a45d-a1faca52af56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411344419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3411344419
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3720978677
Short name T416
Test name
Test status
Simulation time 8477132220 ps
CPU time 37.57 seconds
Started May 12 03:01:47 PM PDT 24
Finished May 12 03:02:25 PM PDT 24
Peak memory 201196 kb
Host smart-5442a698-3b37-4663-adf7-d5116ce5213a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720978677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3720978677
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1511628675
Short name T511
Test name
Test status
Simulation time 385112480 ps
CPU time 2.28 seconds
Started May 12 03:01:40 PM PDT 24
Finished May 12 03:01:43 PM PDT 24
Peak memory 200852 kb
Host smart-f0b0d5c3-4b30-43ff-bb13-2a3d03ce915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511628675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1511628675
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3179866697
Short name T174
Test name
Test status
Simulation time 143286931 ps
CPU time 1.28 seconds
Started May 12 03:01:39 PM PDT 24
Finished May 12 03:01:40 PM PDT 24
Peak memory 200812 kb
Host smart-9aa605e6-c012-4004-84dc-08c651f373a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179866697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3179866697
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3142325159
Short name T425
Test name
Test status
Simulation time 79825327 ps
CPU time 0.84 seconds
Started May 12 03:01:49 PM PDT 24
Finished May 12 03:01:50 PM PDT 24
Peak memory 200884 kb
Host smart-cc7ee1b5-8398-40e2-b405-280f13caae08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142325159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3142325159
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4202297276
Short name T238
Test name
Test status
Simulation time 1219791411 ps
CPU time 5.9 seconds
Started May 12 03:01:52 PM PDT 24
Finished May 12 03:01:59 PM PDT 24
Peak memory 218500 kb
Host smart-c84a12c6-dbc2-4f91-a27c-dccb88a29379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202297276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4202297276
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1000218578
Short name T532
Test name
Test status
Simulation time 244289281 ps
CPU time 1.08 seconds
Started May 12 03:01:49 PM PDT 24
Finished May 12 03:01:51 PM PDT 24
Peak memory 218152 kb
Host smart-82f89cb9-603c-4f73-ac42-fdfe1b47bf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000218578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1000218578
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3934919704
Short name T480
Test name
Test status
Simulation time 196864541 ps
CPU time 0.95 seconds
Started May 12 03:01:49 PM PDT 24
Finished May 12 03:01:51 PM PDT 24
Peak memory 200692 kb
Host smart-dc0ec852-bddd-4090-ade3-d73f9e434981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934919704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3934919704
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2043601203
Short name T492
Test name
Test status
Simulation time 718612565 ps
CPU time 3.84 seconds
Started May 12 03:01:50 PM PDT 24
Finished May 12 03:01:54 PM PDT 24
Peak memory 201024 kb
Host smart-01f6ff34-01e7-481e-bde1-55eaec0f8a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043601203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2043601203
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1053841968
Short name T70
Test name
Test status
Simulation time 105942803 ps
CPU time 0.94 seconds
Started May 12 03:01:51 PM PDT 24
Finished May 12 03:01:52 PM PDT 24
Peak memory 200868 kb
Host smart-402d0af0-7cc1-45f9-a3ed-4c08db4b9ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053841968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1053841968
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3417288130
Short name T148
Test name
Test status
Simulation time 196536739 ps
CPU time 1.39 seconds
Started May 12 03:01:47 PM PDT 24
Finished May 12 03:01:49 PM PDT 24
Peak memory 200956 kb
Host smart-463c229c-e884-46c8-8101-d7692dbd10bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417288130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3417288130
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.249556079
Short name T334
Test name
Test status
Simulation time 2206134930 ps
CPU time 8.51 seconds
Started May 12 03:01:51 PM PDT 24
Finished May 12 03:02:00 PM PDT 24
Peak memory 201160 kb
Host smart-c83d4126-ea71-4566-93ac-192db31b3c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249556079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.249556079
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1101325488
Short name T394
Test name
Test status
Simulation time 341790125 ps
CPU time 2.34 seconds
Started May 12 03:01:52 PM PDT 24
Finished May 12 03:01:54 PM PDT 24
Peak memory 200984 kb
Host smart-80908052-66db-4e75-911a-dbb300edc191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101325488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1101325488
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2830775068
Short name T138
Test name
Test status
Simulation time 74396450 ps
CPU time 0.81 seconds
Started May 12 03:01:49 PM PDT 24
Finished May 12 03:01:51 PM PDT 24
Peak memory 200892 kb
Host smart-3eacfd6c-14ce-4f56-a5f2-077d80ba9533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830775068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2830775068
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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