Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7908

1

T2

185

T7

8

T10

183

auto[1]

10951

1

T2

170

T3

4

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5837	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6441	1			T1	1		T2	136		T3	2
reset_info_cp[2]	2964	1			T2	54		T3	1		T5	1
reset_info_cp[4]	3679	1			T2	71		T3	1		T5	1
reset_info_cp[8]	105	1			T3	1		T10	4		T12	2
reset_info_cp[16]	115	1			T2	4		T10	1		T11	2
reset_info_cp[32]	128	1			T2	1		T10	3		T11	1
reset_info_cp[64]	111	1			T26	2		T27	2		T28	3
reset_info_cp[128]	99	1			T10	5		T11	2		T27	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3085	1			T2	71		T10	52		T11	21
reset_info_cp[1]	auto[1]	2736	1			T2	64		T3	1		T5	1
reset_info_cp[2]	auto[0]	920	1			T2	22		T10	21		T12	10
reset_info_cp[2]	auto[1]	2044	1			T2	32		T3	1		T5	1
reset_info_cp[4]	auto[0]	1324	1			T2	35		T10	42		T12	14
reset_info_cp[4]	auto[1]	2355	1			T2	36		T3	1		T5	1
reset_info_cp[8]	auto[0]	41	1			T10	2		T12	1		T28	1
reset_info_cp[8]	auto[1]	64	1			T3	1		T10	2		T12	1
reset_info_cp[16]	auto[0]	48	1			T2	2		T10	1		T26	1
reset_info_cp[16]	auto[1]	67	1			T2	2		T11	2		T33	1
reset_info_cp[32]	auto[0]	41	1			T77	1		T133	1		T96	3
reset_info_cp[32]	auto[1]	87	1			T2	1		T10	3		T11	1
reset_info_cp[64]	auto[0]	50	1			T26	2		T27	2		T28	2
reset_info_cp[64]	auto[1]	61	1			T28	1		T77	1		T60	1
reset_info_cp[128]	auto[0]	35	1			T10	2		T28	1		T92	1
reset_info_cp[128]	auto[1]	64	1			T10	3		T11	2		T27	1