Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2892100834 May 14 12:43:55 PM PDT 24 May 14 12:44:05 PM PDT 24 1913592124 ps
T539 /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2648181322 May 14 12:43:20 PM PDT 24 May 14 12:43:28 PM PDT 24 1880590360 ps
T540 /workspace/coverage/default/42.rstmgr_stress_all.4189883776 May 14 12:44:45 PM PDT 24 May 14 12:45:08 PM PDT 24 5351151873 ps
T541 /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4098444131 May 14 12:44:30 PM PDT 24 May 14 12:44:33 PM PDT 24 246189494 ps
T542 /workspace/coverage/default/48.rstmgr_reset.961777929 May 14 12:44:40 PM PDT 24 May 14 12:44:50 PM PDT 24 1932914519 ps
T62 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1584776461 May 14 12:43:09 PM PDT 24 May 14 12:43:11 PM PDT 24 60701275 ps
T68 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3851748604 May 14 12:43:02 PM PDT 24 May 14 12:43:08 PM PDT 24 176286179 ps
T63 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2976856229 May 14 12:43:01 PM PDT 24 May 14 12:43:06 PM PDT 24 170320363 ps
T64 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2043749344 May 14 12:43:00 PM PDT 24 May 14 12:43:05 PM PDT 24 109911859 ps
T65 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3964242402 May 14 12:42:45 PM PDT 24 May 14 12:42:53 PM PDT 24 920922847 ps
T66 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.438735066 May 14 12:42:46 PM PDT 24 May 14 12:42:53 PM PDT 24 129701906 ps
T69 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1496223231 May 14 12:42:49 PM PDT 24 May 14 12:42:57 PM PDT 24 496946933 ps
T84 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.512507488 May 14 12:43:03 PM PDT 24 May 14 12:43:08 PM PDT 24 190822037 ps
T85 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1564012523 May 14 12:42:49 PM PDT 24 May 14 12:42:55 PM PDT 24 107314775 ps
T100 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3625273403 May 14 12:42:49 PM PDT 24 May 14 12:42:55 PM PDT 24 58985243 ps
T86 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.901579452 May 14 12:43:01 PM PDT 24 May 14 12:43:08 PM PDT 24 872380357 ps
T87 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1403339522 May 14 12:42:50 PM PDT 24 May 14 12:42:56 PM PDT 24 120440018 ps
T101 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3231877610 May 14 12:42:59 PM PDT 24 May 14 12:43:05 PM PDT 24 138666491 ps
T102 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1482717744 May 14 12:43:05 PM PDT 24 May 14 12:43:09 PM PDT 24 256083270 ps
T88 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1638400116 May 14 12:43:00 PM PDT 24 May 14 12:43:06 PM PDT 24 169582822 ps
T89 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2544535727 May 14 12:42:58 PM PDT 24 May 14 12:43:04 PM PDT 24 412487189 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3299414220 May 14 12:43:02 PM PDT 24 May 14 12:43:07 PM PDT 24 207077839 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2232213755 May 14 12:42:55 PM PDT 24 May 14 12:42:59 PM PDT 24 235618114 ps
T90 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.689209934 May 14 12:42:54 PM PDT 24 May 14 12:43:00 PM PDT 24 478077133 ps
T91 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.75232427 May 14 12:42:55 PM PDT 24 May 14 12:42:59 PM PDT 24 155287669 ps
T108 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4001574790 May 14 12:43:11 PM PDT 24 May 14 12:43:14 PM PDT 24 175732366 ps
T110 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3103871091 May 14 12:42:52 PM PDT 24 May 14 12:42:59 PM PDT 24 887378229 ps
T109 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2840245939 May 14 12:42:50 PM PDT 24 May 14 12:42:57 PM PDT 24 160575038 ps
T545 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.684485646 May 14 12:42:59 PM PDT 24 May 14 12:43:04 PM PDT 24 83322598 ps
T103 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2343731970 May 14 12:43:03 PM PDT 24 May 14 12:43:07 PM PDT 24 79700956 ps
T546 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3659985237 May 14 12:42:57 PM PDT 24 May 14 12:43:01 PM PDT 24 69036415 ps
T104 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3504012140 May 14 12:42:48 PM PDT 24 May 14 12:42:54 PM PDT 24 77540835 ps
T547 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2955153139 May 14 12:43:03 PM PDT 24 May 14 12:43:08 PM PDT 24 138568032 ps
T118 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2208235990 May 14 12:43:06 PM PDT 24 May 14 12:43:11 PM PDT 24 556868382 ps
T105 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.95375422 May 14 12:42:57 PM PDT 24 May 14 12:43:00 PM PDT 24 135949340 ps
T548 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2584948550 May 14 12:42:45 PM PDT 24 May 14 12:42:51 PM PDT 24 105606237 ps
T549 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2202758090 May 14 12:42:59 PM PDT 24 May 14 12:43:06 PM PDT 24 273901464 ps
T106 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1881592467 May 14 12:43:00 PM PDT 24 May 14 12:43:06 PM PDT 24 133618610 ps
T93 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2246006418 May 14 12:42:41 PM PDT 24 May 14 12:42:46 PM PDT 24 78286986 ps
T107 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3510703488 May 14 12:42:45 PM PDT 24 May 14 12:42:52 PM PDT 24 255488984 ps
T550 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2297428486 May 14 12:42:49 PM PDT 24 May 14 12:42:56 PM PDT 24 429709353 ps
T551 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3984113071 May 14 12:43:01 PM PDT 24 May 14 12:43:09 PM PDT 24 607579183 ps
T552 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3635542995 May 14 12:42:41 PM PDT 24 May 14 12:42:46 PM PDT 24 68694633 ps
T130 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1952245820 May 14 12:42:49 PM PDT 24 May 14 12:42:56 PM PDT 24 446449422 ps
T553 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3950068657 May 14 12:42:50 PM PDT 24 May 14 12:42:55 PM PDT 24 77404718 ps
T113 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2431751363 May 14 12:42:54 PM PDT 24 May 14 12:42:59 PM PDT 24 485650392 ps
T554 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1767272425 May 14 12:42:57 PM PDT 24 May 14 12:43:01 PM PDT 24 82031832 ps
T555 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3368610212 May 14 12:42:50 PM PDT 24 May 14 12:42:56 PM PDT 24 234483204 ps
T556 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1586796199 May 14 12:42:51 PM PDT 24 May 14 12:42:56 PM PDT 24 117815262 ps
T557 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2068812249 May 14 12:42:59 PM PDT 24 May 14 12:43:06 PM PDT 24 499697420 ps
T111 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.583069699 May 14 12:43:00 PM PDT 24 May 14 12:43:08 PM PDT 24 953755276 ps
T558 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2857284966 May 14 12:42:57 PM PDT 24 May 14 12:43:00 PM PDT 24 113830534 ps
T559 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2170627945 May 14 12:42:58 PM PDT 24 May 14 12:43:02 PM PDT 24 91698386 ps
T560 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.591257328 May 14 12:42:58 PM PDT 24 May 14 12:43:02 PM PDT 24 85988918 ps
T116 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1289720712 May 14 12:43:08 PM PDT 24 May 14 12:43:11 PM PDT 24 485794500 ps
T114 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4280100670 May 14 12:43:13 PM PDT 24 May 14 12:43:17 PM PDT 24 991076752 ps
T561 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.458136894 May 14 12:42:58 PM PDT 24 May 14 12:43:02 PM PDT 24 146579503 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3092339947 May 14 12:42:57 PM PDT 24 May 14 12:43:07 PM PDT 24 1551500861 ps
T563 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2702401923 May 14 12:42:50 PM PDT 24 May 14 12:42:55 PM PDT 24 62646945 ps
T564 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3216872566 May 14 12:43:03 PM PDT 24 May 14 12:43:08 PM PDT 24 451735903 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.57960398 May 14 12:42:55 PM PDT 24 May 14 12:42:58 PM PDT 24 70665441 ps
T566 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2197351481 May 14 12:42:50 PM PDT 24 May 14 12:42:56 PM PDT 24 79482102 ps
T567 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3352220581 May 14 12:43:05 PM PDT 24 May 14 12:43:08 PM PDT 24 125121794 ps
T568 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2726819810 May 14 12:42:49 PM PDT 24 May 14 12:42:57 PM PDT 24 511360584 ps
T569 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.22822125 May 14 12:42:59 PM PDT 24 May 14 12:43:05 PM PDT 24 158532564 ps
T570 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3609332629 May 14 12:43:02 PM PDT 24 May 14 12:43:07 PM PDT 24 138166897 ps
T571 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.896676603 May 14 12:42:56 PM PDT 24 May 14 12:43:01 PM PDT 24 802110579 ps
T572 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3211728871 May 14 12:43:05 PM PDT 24 May 14 12:43:10 PM PDT 24 297738978 ps
T115 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.355106266 May 14 12:42:59 PM PDT 24 May 14 12:43:07 PM PDT 24 864960180 ps
T573 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1610531219 May 14 12:42:59 PM PDT 24 May 14 12:43:04 PM PDT 24 79655594 ps
T574 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3009500466 May 14 12:43:00 PM PDT 24 May 14 12:43:06 PM PDT 24 248402223 ps
T575 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2303923764 May 14 12:42:53 PM PDT 24 May 14 12:42:58 PM PDT 24 236832410 ps
T576 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1474923464 May 14 12:42:59 PM PDT 24 May 14 12:43:05 PM PDT 24 126575650 ps
T577 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1998689448 May 14 12:42:54 PM PDT 24 May 14 12:42:59 PM PDT 24 533820053 ps
T578 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3892305137 May 14 12:43:01 PM PDT 24 May 14 12:43:06 PM PDT 24 89955439 ps
T579 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2275218030 May 14 12:42:49 PM PDT 24 May 14 12:42:56 PM PDT 24 202492707 ps
T580 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.414938721 May 14 12:42:47 PM PDT 24 May 14 12:42:54 PM PDT 24 103538747 ps
T581 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2797738597 May 14 12:42:59 PM PDT 24 May 14 12:43:04 PM PDT 24 62326880 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.358810324 May 14 12:42:44 PM PDT 24 May 14 12:42:53 PM PDT 24 639538775 ps
T583 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.757569813 May 14 12:42:58 PM PDT 24 May 14 12:43:04 PM PDT 24 166738387 ps
T584 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3169709177 May 14 12:42:43 PM PDT 24 May 14 12:42:48 PM PDT 24 69622585 ps
T585 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3936407033 May 14 12:43:00 PM PDT 24 May 14 12:43:06 PM PDT 24 200665444 ps
T586 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1234001394 May 14 12:43:12 PM PDT 24 May 14 12:43:14 PM PDT 24 259524497 ps
T587 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3603809862 May 14 12:42:49 PM PDT 24 May 14 12:42:59 PM PDT 24 481901229 ps
T588 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1606755398 May 14 12:42:43 PM PDT 24 May 14 12:42:48 PM PDT 24 198357720 ps
T112 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.929902876 May 14 12:42:47 PM PDT 24 May 14 12:42:53 PM PDT 24 462573808 ps
T589 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.262505772 May 14 12:42:58 PM PDT 24 May 14 12:43:07 PM PDT 24 1168246226 ps
T590 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.196588469 May 14 12:43:06 PM PDT 24 May 14 12:43:09 PM PDT 24 114028989 ps
T131 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.425190658 May 14 12:43:00 PM PDT 24 May 14 12:43:06 PM PDT 24 424410056 ps
T591 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2737839849 May 14 12:43:10 PM PDT 24 May 14 12:43:15 PM PDT 24 876126210 ps
T592 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4229955775 May 14 12:43:02 PM PDT 24 May 14 12:43:06 PM PDT 24 74403967 ps
T593 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2474179228 May 14 12:43:09 PM PDT 24 May 14 12:43:11 PM PDT 24 182239328 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.582100329 May 14 12:42:58 PM PDT 24 May 14 12:43:02 PM PDT 24 123278763 ps
T595 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3915933988 May 14 12:42:59 PM PDT 24 May 14 12:43:05 PM PDT 24 416911083 ps
T596 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3177521372 May 14 12:43:00 PM PDT 24 May 14 12:43:05 PM PDT 24 137541163 ps
T597 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2974686616 May 14 12:42:58 PM PDT 24 May 14 12:43:03 PM PDT 24 58534273 ps
T598 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4199450615 May 14 12:43:09 PM PDT 24 May 14 12:43:11 PM PDT 24 121230383 ps
T599 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2654746841 May 14 12:42:52 PM PDT 24 May 14 12:42:57 PM PDT 24 239534414 ps
T117 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2988365319 May 14 12:42:57 PM PDT 24 May 14 12:43:03 PM PDT 24 945367217 ps
T600 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2407090043 May 14 12:42:52 PM PDT 24 May 14 12:42:58 PM PDT 24 331209950 ps
T601 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1198889848 May 14 12:42:43 PM PDT 24 May 14 12:42:53 PM PDT 24 1185838749 ps
T602 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3230139580 May 14 12:42:57 PM PDT 24 May 14 12:43:01 PM PDT 24 115022034 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1876384454 May 14 12:42:51 PM PDT 24 May 14 12:42:56 PM PDT 24 62874439 ps
T604 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4241610981 May 14 12:42:51 PM PDT 24 May 14 12:42:57 PM PDT 24 138741814 ps
T605 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1647897827 May 14 12:42:54 PM PDT 24 May 14 12:43:00 PM PDT 24 419823883 ps
T606 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2951143165 May 14 12:42:58 PM PDT 24 May 14 12:43:02 PM PDT 24 108451319 ps
T607 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1047766039 May 14 12:42:59 PM PDT 24 May 14 12:43:04 PM PDT 24 180036582 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3009434262 May 14 12:42:53 PM PDT 24 May 14 12:42:57 PM PDT 24 111454721 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3873192173 May 14 12:43:00 PM PDT 24 May 14 12:43:06 PM PDT 24 288151482 ps
T610 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2223876442 May 14 12:43:03 PM PDT 24 May 14 12:43:08 PM PDT 24 213702998 ps
T611 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.234446826 May 14 12:43:00 PM PDT 24 May 14 12:43:14 PM PDT 24 2286222166 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1628394691 May 14 12:43:00 PM PDT 24 May 14 12:43:07 PM PDT 24 948415588 ps
T613 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4116183192 May 14 12:43:00 PM PDT 24 May 14 12:43:06 PM PDT 24 153784420 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.356179345 May 14 12:43:06 PM PDT 24 May 14 12:43:09 PM PDT 24 116035763 ps
T615 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.483384942 May 14 12:42:42 PM PDT 24 May 14 12:42:47 PM PDT 24 125908935 ps
T616 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2294333016 May 14 12:42:45 PM PDT 24 May 14 12:42:51 PM PDT 24 167874775 ps
T617 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3984752478 May 14 12:42:57 PM PDT 24 May 14 12:43:01 PM PDT 24 54198159 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1256274572 May 14 12:42:52 PM PDT 24 May 14 12:42:56 PM PDT 24 134070028 ps
T619 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.520116795 May 14 12:43:04 PM PDT 24 May 14 12:43:08 PM PDT 24 149245853 ps
T620 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1074532655 May 14 12:43:00 PM PDT 24 May 14 12:43:08 PM PDT 24 928830147 ps

Test location /workspace/coverage/default/16.rstmgr_stress_all.754556541
Short name T2
Test name
Test status
Simulation time 6648587768 ps
CPU time 30.14 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:44:23 PM PDT 24
Peak memory 208784 kb
Host smart-a14bb4dd-47c6-4cd9-b232-37539cf22bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754556541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.754556541
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.256516057
Short name T78
Test name
Test status
Simulation time 365453455 ps
CPU time 2.04 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 208740 kb
Host smart-bdcee8ff-f9cf-41f8-bd6d-f15c34dcbf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256516057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.256516057
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1403339522
Short name T87
Test name
Test status
Simulation time 120440018 ps
CPU time 1.34 seconds
Started May 14 12:42:50 PM PDT 24
Finished May 14 12:42:56 PM PDT 24
Peak memory 208572 kb
Host smart-ef177e43-0442-4d04-93cb-0bc9a78ff953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403339522 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1403339522
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1861210541
Short name T70
Test name
Test status
Simulation time 16528785588 ps
CPU time 27.64 seconds
Started May 14 12:43:26 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 217408 kb
Host smart-5486ea12-d231-4f8c-b6c4-74d59a6d3150
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861210541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1861210541
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2787348192
Short name T11
Test name
Test status
Simulation time 2358166477 ps
CPU time 7.98 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:44:03 PM PDT 24
Peak memory 217876 kb
Host smart-0fe77ca9-b9f6-44e6-955d-eb486388031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787348192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2787348192
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3770174191
Short name T96
Test name
Test status
Simulation time 17131501092 ps
CPU time 55.09 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:45:28 PM PDT 24
Peak memory 200708 kb
Host smart-9b357ee1-cd19-4c18-83f6-735f14feefd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770174191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3770174191
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.901579452
Short name T86
Test name
Test status
Simulation time 872380357 ps
CPU time 3.22 seconds
Started May 14 12:43:01 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 200432 kb
Host smart-4c843988-21e1-49b3-862f-3436ed812fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901579452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.901579452
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1921297194
Short name T32
Test name
Test status
Simulation time 56039578 ps
CPU time 0.71 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 200196 kb
Host smart-74008c32-26c0-4fab-9491-9f6f139eecb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921297194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1921297194
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.4831954
Short name T144
Test name
Test status
Simulation time 174328211 ps
CPU time 1.15 seconds
Started May 14 12:43:22 PM PDT 24
Finished May 14 12:43:24 PM PDT 24
Peak memory 200340 kb
Host smart-be25782c-ebe2-4b32-b0c2-1b1ca4d56c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4831954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.4831954
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.4264241268
Short name T34
Test name
Test status
Simulation time 2356914711 ps
CPU time 8.44 seconds
Started May 14 12:43:58 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 217308 kb
Host smart-f6096509-d9f4-444b-bb91-b640f3ebbc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264241268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.4264241268
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.583069699
Short name T111
Test name
Test status
Simulation time 953755276 ps
CPU time 3.23 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 200464 kb
Host smart-2f6ad719-749d-4da8-b045-674ed7af7782
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583069699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
583069699
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1925075735
Short name T133
Test name
Test status
Simulation time 115529049 ps
CPU time 1.1 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:03 PM PDT 24
Peak memory 200300 kb
Host smart-1c6adf08-5981-40f6-91fb-33126f1f3a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925075735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1925075735
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3984113071
Short name T551
Test name
Test status
Simulation time 607579183 ps
CPU time 3.93 seconds
Started May 14 12:43:01 PM PDT 24
Finished May 14 12:43:09 PM PDT 24
Peak memory 212800 kb
Host smart-76341290-1454-4627-b985-b36c8a96701d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984113071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3984113071
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3616951620
Short name T60
Test name
Test status
Simulation time 1226874155 ps
CPU time 5.31 seconds
Started May 14 12:44:00 PM PDT 24
Finished May 14 12:44:08 PM PDT 24
Peak memory 217380 kb
Host smart-8e614ac5-fe1b-4355-8b7b-b4e871d329a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616951620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3616951620
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3504012140
Short name T104
Test name
Test status
Simulation time 77540835 ps
CPU time 0.82 seconds
Started May 14 12:42:48 PM PDT 24
Finished May 14 12:42:54 PM PDT 24
Peak memory 200236 kb
Host smart-b3cee0fc-7347-4a24-942e-8082e9ef8095
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504012140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3504012140
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3120832316
Short name T18
Test name
Test status
Simulation time 122030006 ps
CPU time 0.76 seconds
Started May 14 12:43:09 PM PDT 24
Finished May 14 12:43:11 PM PDT 24
Peak memory 200144 kb
Host smart-704ce55d-1158-452d-8b50-d0e57008ad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120832316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3120832316
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1676097606
Short name T75
Test name
Test status
Simulation time 2201001176 ps
CPU time 7.9 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:44:01 PM PDT 24
Peak memory 201024 kb
Host smart-e7ecc930-f813-477e-9ccd-bed3abcd007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676097606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1676097606
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3207156181
Short name T41
Test name
Test status
Simulation time 2371040793 ps
CPU time 8.73 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:44:02 PM PDT 24
Peak memory 218076 kb
Host smart-f167b589-5355-4e24-9ced-c9fad0943a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207156181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3207156181
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3964242402
Short name T65
Test name
Test status
Simulation time 920922847 ps
CPU time 2.97 seconds
Started May 14 12:42:45 PM PDT 24
Finished May 14 12:42:53 PM PDT 24
Peak memory 200464 kb
Host smart-af582adb-8829-405e-a1ad-2c36c36ad681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964242402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3964242402
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2988365319
Short name T117
Test name
Test status
Simulation time 945367217 ps
CPU time 3.09 seconds
Started May 14 12:42:57 PM PDT 24
Finished May 14 12:43:03 PM PDT 24
Peak memory 200432 kb
Host smart-2d559d54-702f-45f3-81ce-07ce9e16300b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988365319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2988365319
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2431751363
Short name T113
Test name
Test status
Simulation time 485650392 ps
CPU time 1.97 seconds
Started May 14 12:42:54 PM PDT 24
Finished May 14 12:42:59 PM PDT 24
Peak memory 200440 kb
Host smart-104c1e92-1eea-4437-8c1d-e41c08c4e7a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431751363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2431751363
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2232213755
Short name T544
Test name
Test status
Simulation time 235618114 ps
CPU time 1.56 seconds
Started May 14 12:42:55 PM PDT 24
Finished May 14 12:42:59 PM PDT 24
Peak memory 200332 kb
Host smart-992369a5-4401-4144-a904-0482d340de5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232213755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
232213755
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3603809862
Short name T587
Test name
Test status
Simulation time 481901229 ps
CPU time 5.67 seconds
Started May 14 12:42:49 PM PDT 24
Finished May 14 12:42:59 PM PDT 24
Peak memory 216660 kb
Host smart-d48f12b9-d0fa-4d9c-b745-144b4a5c0433
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603809862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
603809862
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3177521372
Short name T596
Test name
Test status
Simulation time 137541163 ps
CPU time 0.95 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:05 PM PDT 24
Peak memory 200088 kb
Host smart-2c95a762-4fb7-4e95-822a-9eb12878c9c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177521372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
177521372
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2043749344
Short name T64
Test name
Test status
Simulation time 109911859 ps
CPU time 1.06 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:05 PM PDT 24
Peak memory 209504 kb
Host smart-5b97b0ad-ac3f-4867-99e5-840e59ce502d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043749344 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2043749344
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2974686616
Short name T597
Test name
Test status
Simulation time 58534273 ps
CPU time 0.73 seconds
Started May 14 12:42:58 PM PDT 24
Finished May 14 12:43:03 PM PDT 24
Peak memory 200228 kb
Host smart-fb43780f-ea39-4623-8b6d-0cdc3f0c47c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974686616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2974686616
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.483384942
Short name T615
Test name
Test status
Simulation time 125908935 ps
CPU time 1.28 seconds
Started May 14 12:42:42 PM PDT 24
Finished May 14 12:42:47 PM PDT 24
Peak memory 200540 kb
Host smart-bba15b82-e22c-4a58-a26e-5532bca37b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483384942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.483384942
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.689209934
Short name T90
Test name
Test status
Simulation time 478077133 ps
CPU time 3 seconds
Started May 14 12:42:54 PM PDT 24
Finished May 14 12:43:00 PM PDT 24
Peak memory 211924 kb
Host smart-3aba1172-52e7-4205-9178-6439a73805fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689209934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.689209934
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2951143165
Short name T606
Test name
Test status
Simulation time 108451319 ps
CPU time 1.34 seconds
Started May 14 12:42:58 PM PDT 24
Finished May 14 12:43:02 PM PDT 24
Peak memory 200428 kb
Host smart-677ed647-1bd3-417b-8fca-b7a8c3330d71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951143165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
951143165
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1198889848
Short name T601
Test name
Test status
Simulation time 1185838749 ps
CPU time 5.31 seconds
Started May 14 12:42:43 PM PDT 24
Finished May 14 12:42:53 PM PDT 24
Peak memory 200400 kb
Host smart-014d3dbe-6208-4f54-a78a-e2d4c6660f9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198889848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
198889848
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1256274572
Short name T618
Test name
Test status
Simulation time 134070028 ps
CPU time 0.89 seconds
Started May 14 12:42:52 PM PDT 24
Finished May 14 12:42:56 PM PDT 24
Peak memory 200060 kb
Host smart-67dd9254-354d-4a8e-9a7f-a619cf71bb2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256274572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
256274572
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2294333016
Short name T616
Test name
Test status
Simulation time 167874775 ps
CPU time 1.37 seconds
Started May 14 12:42:45 PM PDT 24
Finished May 14 12:42:51 PM PDT 24
Peak memory 208748 kb
Host smart-81c1e345-451d-40c6-9465-6f02d7c28e13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294333016 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2294333016
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3635542995
Short name T552
Test name
Test status
Simulation time 68694633 ps
CPU time 0.79 seconds
Started May 14 12:42:41 PM PDT 24
Finished May 14 12:42:46 PM PDT 24
Peak memory 200156 kb
Host smart-c9051088-585f-4294-bb1d-c54348471806
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635542995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3635542995
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.582100329
Short name T594
Test name
Test status
Simulation time 123278763 ps
CPU time 1.07 seconds
Started May 14 12:42:58 PM PDT 24
Finished May 14 12:43:02 PM PDT 24
Peak memory 200160 kb
Host smart-60989b05-ea10-4285-a443-97e5cb3335b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582100329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.582100329
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.22822125
Short name T569
Test name
Test status
Simulation time 158532564 ps
CPU time 2.13 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:05 PM PDT 24
Peak memory 208616 kb
Host smart-4aaebbd9-1a50-4352-9d9b-6d730ba1f3de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22822125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.22822125
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1564012523
Short name T85
Test name
Test status
Simulation time 107314775 ps
CPU time 0.91 seconds
Started May 14 12:42:49 PM PDT 24
Finished May 14 12:42:55 PM PDT 24
Peak memory 200376 kb
Host smart-c657c190-6e2b-4e80-8ea6-a82bd84a0532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564012523 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1564012523
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.438735066
Short name T66
Test name
Test status
Simulation time 129701906 ps
CPU time 1.37 seconds
Started May 14 12:42:46 PM PDT 24
Finished May 14 12:42:53 PM PDT 24
Peak memory 200400 kb
Host smart-98117956-bfb8-4da8-93e7-5f6568bbe999
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438735066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.438735066
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2840245939
Short name T109
Test name
Test status
Simulation time 160575038 ps
CPU time 2.12 seconds
Started May 14 12:42:50 PM PDT 24
Finished May 14 12:42:57 PM PDT 24
Peak memory 208692 kb
Host smart-52bd77cc-067d-4721-8b31-1375a91370bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840245939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2840245939
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.929902876
Short name T112
Test name
Test status
Simulation time 462573808 ps
CPU time 1.81 seconds
Started May 14 12:42:47 PM PDT 24
Finished May 14 12:42:53 PM PDT 24
Peak memory 200484 kb
Host smart-198b2c83-71c4-4eae-9945-8cf1395e3b99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929902876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.929902876
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2976856229
Short name T63
Test name
Test status
Simulation time 170320363 ps
CPU time 1.17 seconds
Started May 14 12:43:01 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 200248 kb
Host smart-557ed9ad-af49-4cb6-b359-7ceb9b097c2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976856229 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2976856229
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1767272425
Short name T554
Test name
Test status
Simulation time 82031832 ps
CPU time 0.89 seconds
Started May 14 12:42:57 PM PDT 24
Finished May 14 12:43:01 PM PDT 24
Peak memory 200200 kb
Host smart-4b8ccc71-f31c-4ec3-a777-83985f7304fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767272425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1767272425
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3950068657
Short name T553
Test name
Test status
Simulation time 77404718 ps
CPU time 0.96 seconds
Started May 14 12:42:50 PM PDT 24
Finished May 14 12:42:55 PM PDT 24
Peak memory 200340 kb
Host smart-0f7246fb-4746-440a-b8cf-d958b8828590
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950068657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3950068657
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3009434262
Short name T608
Test name
Test status
Simulation time 111454721 ps
CPU time 0.99 seconds
Started May 14 12:42:53 PM PDT 24
Finished May 14 12:42:57 PM PDT 24
Peak memory 200268 kb
Host smart-dc832c10-7a1e-49dc-ae42-49eba61fb8d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009434262 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3009434262
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2197351481
Short name T566
Test name
Test status
Simulation time 79482102 ps
CPU time 0.84 seconds
Started May 14 12:42:50 PM PDT 24
Finished May 14 12:42:56 PM PDT 24
Peak memory 200112 kb
Host smart-1821882a-c833-4d5b-bdee-986569505047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197351481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2197351481
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3368610212
Short name T555
Test name
Test status
Simulation time 234483204 ps
CPU time 1.56 seconds
Started May 14 12:42:50 PM PDT 24
Finished May 14 12:42:56 PM PDT 24
Peak memory 200340 kb
Host smart-841899c3-77cf-4cbd-ba98-6040230821ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368610212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3368610212
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1496223231
Short name T69
Test name
Test status
Simulation time 496946933 ps
CPU time 3.05 seconds
Started May 14 12:42:49 PM PDT 24
Finished May 14 12:42:57 PM PDT 24
Peak memory 211244 kb
Host smart-f84ad4ac-bf83-40fe-b431-9c78cae7ab22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496223231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1496223231
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2297428486
Short name T550
Test name
Test status
Simulation time 429709353 ps
CPU time 1.76 seconds
Started May 14 12:42:49 PM PDT 24
Finished May 14 12:42:56 PM PDT 24
Peak memory 200448 kb
Host smart-83f9bc1b-7449-4c7f-a573-919cc2f32fea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297428486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2297428486
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2955153139
Short name T547
Test name
Test status
Simulation time 138568032 ps
CPU time 1.06 seconds
Started May 14 12:43:03 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 208436 kb
Host smart-74822acf-505f-411c-b88b-fcfef99d458f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955153139 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2955153139
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.684485646
Short name T545
Test name
Test status
Simulation time 83322598 ps
CPU time 0.86 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:04 PM PDT 24
Peak memory 200276 kb
Host smart-881b8eb5-0c4c-4535-b0ab-5bea311a073d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684485646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.684485646
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2223876442
Short name T610
Test name
Test status
Simulation time 213702998 ps
CPU time 1.44 seconds
Started May 14 12:43:03 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 200364 kb
Host smart-f739cefd-6974-4512-8bbc-96493141cce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223876442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2223876442
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3915933988
Short name T595
Test name
Test status
Simulation time 416911083 ps
CPU time 2.89 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:05 PM PDT 24
Peak memory 211992 kb
Host smart-3a75b102-e79e-4126-bebc-6c9edc617d70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915933988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3915933988
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1289720712
Short name T116
Test name
Test status
Simulation time 485794500 ps
CPU time 1.97 seconds
Started May 14 12:43:08 PM PDT 24
Finished May 14 12:43:11 PM PDT 24
Peak memory 200448 kb
Host smart-9c3ed550-2b60-410e-a1df-0aebfb9123a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289720712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1289720712
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.520116795
Short name T619
Test name
Test status
Simulation time 149245853 ps
CPU time 1.28 seconds
Started May 14 12:43:04 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 208652 kb
Host smart-4bba3bfc-304a-44a9-9941-af60f130c36a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520116795 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.520116795
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1610531219
Short name T573
Test name
Test status
Simulation time 79655594 ps
CPU time 0.89 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:04 PM PDT 24
Peak memory 200140 kb
Host smart-a730d695-b165-45ab-99c0-01975d249f1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610531219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1610531219
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1474923464
Short name T576
Test name
Test status
Simulation time 126575650 ps
CPU time 1.31 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:05 PM PDT 24
Peak memory 200416 kb
Host smart-f036e858-5d86-4b13-9d0d-3baa70d2a600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474923464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1474923464
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3211728871
Short name T572
Test name
Test status
Simulation time 297738978 ps
CPU time 2.27 seconds
Started May 14 12:43:05 PM PDT 24
Finished May 14 12:43:10 PM PDT 24
Peak memory 208640 kb
Host smart-b7731ddb-32d1-46c4-ba99-3e9724f9daac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211728871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3211728871
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.75232427
Short name T91
Test name
Test status
Simulation time 155287669 ps
CPU time 1.35 seconds
Started May 14 12:42:55 PM PDT 24
Finished May 14 12:42:59 PM PDT 24
Peak memory 208552 kb
Host smart-19d0e6c1-1118-4b2e-9a72-1638f6b021f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75232427 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.75232427
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2797738597
Short name T581
Test name
Test status
Simulation time 62326880 ps
CPU time 0.78 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:04 PM PDT 24
Peak memory 200584 kb
Host smart-979f7641-ab57-4c5f-92b3-7d5b7cacccdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797738597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2797738597
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2654746841
Short name T599
Test name
Test status
Simulation time 239534414 ps
CPU time 1.47 seconds
Started May 14 12:42:52 PM PDT 24
Finished May 14 12:42:57 PM PDT 24
Peak memory 200420 kb
Host smart-ae6e75d4-daab-4682-9ff9-659dd5eb6cff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654746841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2654746841
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2407090043
Short name T600
Test name
Test status
Simulation time 331209950 ps
CPU time 2.17 seconds
Started May 14 12:42:52 PM PDT 24
Finished May 14 12:42:58 PM PDT 24
Peak memory 208628 kb
Host smart-ec72e115-ec2d-44ee-838a-10e5ab1c599c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407090043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2407090043
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1998689448
Short name T577
Test name
Test status
Simulation time 533820053 ps
CPU time 1.91 seconds
Started May 14 12:42:54 PM PDT 24
Finished May 14 12:42:59 PM PDT 24
Peak memory 200464 kb
Host smart-2331ba33-c27f-4fd9-b6cb-20e69fb0b01d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998689448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1998689448
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.356179345
Short name T614
Test name
Test status
Simulation time 116035763 ps
CPU time 1.2 seconds
Started May 14 12:43:06 PM PDT 24
Finished May 14 12:43:09 PM PDT 24
Peak memory 208512 kb
Host smart-fdaf8887-e6dd-4af0-af9b-29d04ff095e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356179345 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.356179345
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3892305137
Short name T578
Test name
Test status
Simulation time 89955439 ps
CPU time 0.89 seconds
Started May 14 12:43:01 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 200212 kb
Host smart-66385161-03f8-457f-82f8-07dc8174370d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892305137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3892305137
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4199450615
Short name T598
Test name
Test status
Simulation time 121230383 ps
CPU time 1.1 seconds
Started May 14 12:43:09 PM PDT 24
Finished May 14 12:43:11 PM PDT 24
Peak memory 200224 kb
Host smart-f370f214-ab25-4b01-8e61-9606465e98ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199450615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.4199450615
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2202758090
Short name T549
Test name
Test status
Simulation time 273901464 ps
CPU time 2.2 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 208580 kb
Host smart-cb959a40-2860-43d0-a1c4-cd85d846d7d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202758090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2202758090
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3216872566
Short name T564
Test name
Test status
Simulation time 451735903 ps
CPU time 1.79 seconds
Started May 14 12:43:03 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 200620 kb
Host smart-cde1de5a-7aeb-445c-8436-4797f277af7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216872566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3216872566
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.512507488
Short name T84
Test name
Test status
Simulation time 190822037 ps
CPU time 1.23 seconds
Started May 14 12:43:03 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 208384 kb
Host smart-8753a42e-8ab5-49d0-b8ae-b45b08c6f940
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512507488 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.512507488
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4229955775
Short name T592
Test name
Test status
Simulation time 74403967 ps
CPU time 0.8 seconds
Started May 14 12:43:02 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 200144 kb
Host smart-e21100eb-a3e3-4699-a545-6e65662603d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229955775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.4229955775
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1881592467
Short name T106
Test name
Test status
Simulation time 133618610 ps
CPU time 1.28 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 200476 kb
Host smart-07348fe1-de21-4721-a267-6f899637e8cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881592467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1881592467
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2208235990
Short name T118
Test name
Test status
Simulation time 556868382 ps
CPU time 3.26 seconds
Started May 14 12:43:06 PM PDT 24
Finished May 14 12:43:11 PM PDT 24
Peak memory 208664 kb
Host smart-76cf6fac-6d35-4baa-a924-87df9a9754a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208235990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2208235990
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2474179228
Short name T593
Test name
Test status
Simulation time 182239328 ps
CPU time 1.18 seconds
Started May 14 12:43:09 PM PDT 24
Finished May 14 12:43:11 PM PDT 24
Peak memory 200320 kb
Host smart-8229f202-1a38-4351-a06c-fc2ac8450aa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474179228 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2474179228
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2343731970
Short name T103
Test name
Test status
Simulation time 79700956 ps
CPU time 0.82 seconds
Started May 14 12:43:03 PM PDT 24
Finished May 14 12:43:07 PM PDT 24
Peak memory 200056 kb
Host smart-ffd56a6e-9bc6-4fdd-96ba-afd59e5ad7c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343731970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2343731970
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1482717744
Short name T102
Test name
Test status
Simulation time 256083270 ps
CPU time 1.62 seconds
Started May 14 12:43:05 PM PDT 24
Finished May 14 12:43:09 PM PDT 24
Peak memory 200600 kb
Host smart-2eb84697-69e4-4a43-9dbb-c09d93b9e882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482717744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1482717744
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3009500466
Short name T574
Test name
Test status
Simulation time 248402223 ps
CPU time 1.86 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 208600 kb
Host smart-7118ac2b-79c9-4e5e-9933-a461ab15d65b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009500466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3009500466
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4280100670
Short name T114
Test name
Test status
Simulation time 991076752 ps
CPU time 3.06 seconds
Started May 14 12:43:13 PM PDT 24
Finished May 14 12:43:17 PM PDT 24
Peak memory 200396 kb
Host smart-3b7beb13-f1ee-4441-bf95-caf6be1d74cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280100670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.4280100670
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4001574790
Short name T108
Test name
Test status
Simulation time 175732366 ps
CPU time 1.53 seconds
Started May 14 12:43:11 PM PDT 24
Finished May 14 12:43:14 PM PDT 24
Peak memory 208624 kb
Host smart-b1259cbe-652c-4271-84a8-3aabd6a07ce2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001574790 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4001574790
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1584776461
Short name T62
Test name
Test status
Simulation time 60701275 ps
CPU time 0.78 seconds
Started May 14 12:43:09 PM PDT 24
Finished May 14 12:43:11 PM PDT 24
Peak memory 200164 kb
Host smart-5d5c64c9-a87b-4408-bb15-4dc70adf346c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584776461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1584776461
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1234001394
Short name T586
Test name
Test status
Simulation time 259524497 ps
CPU time 1.56 seconds
Started May 14 12:43:12 PM PDT 24
Finished May 14 12:43:14 PM PDT 24
Peak memory 200384 kb
Host smart-606c5e0a-3627-425f-b834-59c39ea7bc57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234001394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1234001394
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3851748604
Short name T68
Test name
Test status
Simulation time 176286179 ps
CPU time 2.57 seconds
Started May 14 12:43:02 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 208584 kb
Host smart-52be8930-d672-47f8-b4dd-c2aad21f93a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851748604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3851748604
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2737839849
Short name T591
Test name
Test status
Simulation time 876126210 ps
CPU time 3.24 seconds
Started May 14 12:43:10 PM PDT 24
Finished May 14 12:43:15 PM PDT 24
Peak memory 200468 kb
Host smart-4d8a6ecc-aec6-4304-9666-c96b8f75d71b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737839849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2737839849
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.414938721
Short name T580
Test name
Test status
Simulation time 103538747 ps
CPU time 1.32 seconds
Started May 14 12:42:47 PM PDT 24
Finished May 14 12:42:54 PM PDT 24
Peak memory 200232 kb
Host smart-e3b12857-1175-4021-b54b-6d265a86c7fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414938721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.414938721
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.262505772
Short name T589
Test name
Test status
Simulation time 1168246226 ps
CPU time 5.42 seconds
Started May 14 12:42:58 PM PDT 24
Finished May 14 12:43:07 PM PDT 24
Peak memory 200564 kb
Host smart-4f7af7c8-6d71-4636-8001-9dcea839439c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262505772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.262505772
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2170627945
Short name T559
Test name
Test status
Simulation time 91698386 ps
CPU time 0.81 seconds
Started May 14 12:42:58 PM PDT 24
Finished May 14 12:43:02 PM PDT 24
Peak memory 200160 kb
Host smart-d662e01f-51fa-4ad8-b3c3-9e0005c24eee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170627945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
170627945
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1638400116
Short name T88
Test name
Test status
Simulation time 169582822 ps
CPU time 1.55 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 208880 kb
Host smart-3c2df9ec-3a2a-47d5-93aa-97e44da9cf46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638400116 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1638400116
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3659985237
Short name T546
Test name
Test status
Simulation time 69036415 ps
CPU time 0.8 seconds
Started May 14 12:42:57 PM PDT 24
Finished May 14 12:43:01 PM PDT 24
Peak memory 200196 kb
Host smart-43647f52-0a40-4030-a7c9-3bb66ff17b50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659985237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3659985237
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3510703488
Short name T107
Test name
Test status
Simulation time 255488984 ps
CPU time 1.67 seconds
Started May 14 12:42:45 PM PDT 24
Finished May 14 12:42:52 PM PDT 24
Peak memory 200396 kb
Host smart-3dfee332-1595-479d-ac7b-3365c8009a18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510703488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3510703488
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.358810324
Short name T582
Test name
Test status
Simulation time 639538775 ps
CPU time 3.84 seconds
Started May 14 12:42:44 PM PDT 24
Finished May 14 12:42:53 PM PDT 24
Peak memory 208604 kb
Host smart-debc3423-bf5a-4978-9fcd-7653ae362d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358810324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.358810324
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1628394691
Short name T612
Test name
Test status
Simulation time 948415588 ps
CPU time 3.07 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:07 PM PDT 24
Peak memory 200424 kb
Host smart-b5e1cbf0-1a73-4ad8-b265-91540b917fce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628394691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1628394691
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4116183192
Short name T613
Test name
Test status
Simulation time 153784420 ps
CPU time 1.99 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 200356 kb
Host smart-132d955d-073d-4624-8dcb-ce47a49e0567
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116183192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
116183192
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.234446826
Short name T611
Test name
Test status
Simulation time 2286222166 ps
CPU time 9.81 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:14 PM PDT 24
Peak memory 200408 kb
Host smart-31fde036-28d9-4fd0-97e7-884e82c8b381
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234446826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.234446826
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2584948550
Short name T548
Test name
Test status
Simulation time 105606237 ps
CPU time 0.82 seconds
Started May 14 12:42:45 PM PDT 24
Finished May 14 12:42:51 PM PDT 24
Peak memory 200564 kb
Host smart-38a44609-4e06-4b63-8b53-24a846197f67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584948550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
584948550
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2857284966
Short name T558
Test name
Test status
Simulation time 113830534 ps
CPU time 0.96 seconds
Started May 14 12:42:57 PM PDT 24
Finished May 14 12:43:00 PM PDT 24
Peak memory 200316 kb
Host smart-be30968d-a61d-4673-9f6b-c0981f9cc3d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857284966 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2857284966
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3169709177
Short name T584
Test name
Test status
Simulation time 69622585 ps
CPU time 0.79 seconds
Started May 14 12:42:43 PM PDT 24
Finished May 14 12:42:48 PM PDT 24
Peak memory 200172 kb
Host smart-c8f4af7d-927f-4b03-bbd2-79c78311b453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169709177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3169709177
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3230139580
Short name T602
Test name
Test status
Simulation time 115022034 ps
CPU time 1 seconds
Started May 14 12:42:57 PM PDT 24
Finished May 14 12:43:01 PM PDT 24
Peak memory 200212 kb
Host smart-fe0f2fb8-f8d5-4a1e-a911-a1b3fb91a96b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230139580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3230139580
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3873192173
Short name T609
Test name
Test status
Simulation time 288151482 ps
CPU time 2.18 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 208628 kb
Host smart-710665fa-52e9-403b-ac9c-669b91ace8bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873192173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3873192173
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.896676603
Short name T571
Test name
Test status
Simulation time 802110579 ps
CPU time 2.62 seconds
Started May 14 12:42:56 PM PDT 24
Finished May 14 12:43:01 PM PDT 24
Peak memory 200372 kb
Host smart-e9ea6538-a4df-4246-987b-3d568697fcdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896676603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
896676603
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3299414220
Short name T543
Test name
Test status
Simulation time 207077839 ps
CPU time 1.56 seconds
Started May 14 12:43:02 PM PDT 24
Finished May 14 12:43:07 PM PDT 24
Peak memory 200392 kb
Host smart-a915202b-c5ca-4f52-86a1-e4ad7e1c4593
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299414220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
299414220
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3092339947
Short name T562
Test name
Test status
Simulation time 1551500861 ps
CPU time 7.83 seconds
Started May 14 12:42:57 PM PDT 24
Finished May 14 12:43:07 PM PDT 24
Peak memory 200356 kb
Host smart-f124f6b5-b440-4d8b-9901-a1b8ffb74a44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092339947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
092339947
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.458136894
Short name T561
Test name
Test status
Simulation time 146579503 ps
CPU time 0.92 seconds
Started May 14 12:42:58 PM PDT 24
Finished May 14 12:43:02 PM PDT 24
Peak memory 200196 kb
Host smart-f37066b5-8588-4632-87e3-caf10c57b0d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458136894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.458136894
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3936407033
Short name T585
Test name
Test status
Simulation time 200665444 ps
CPU time 1.2 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 200284 kb
Host smart-d981e022-3f8d-456b-a6de-1dc55a5008db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936407033 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3936407033
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2246006418
Short name T93
Test name
Test status
Simulation time 78286986 ps
CPU time 0.8 seconds
Started May 14 12:42:41 PM PDT 24
Finished May 14 12:42:46 PM PDT 24
Peak memory 200116 kb
Host smart-17262a4b-bd13-42cb-bba2-6caf94dcc211
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246006418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2246006418
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1606755398
Short name T588
Test name
Test status
Simulation time 198357720 ps
CPU time 1.46 seconds
Started May 14 12:42:43 PM PDT 24
Finished May 14 12:42:48 PM PDT 24
Peak memory 200508 kb
Host smart-eb820aab-fe19-445c-bfac-e90fa24b867b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606755398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1606755398
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1647897827
Short name T605
Test name
Test status
Simulation time 419823883 ps
CPU time 3.1 seconds
Started May 14 12:42:54 PM PDT 24
Finished May 14 12:43:00 PM PDT 24
Peak memory 208592 kb
Host smart-38e350b8-0acb-4ee3-a850-db7c796fa7b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647897827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1647897827
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.425190658
Short name T131
Test name
Test status
Simulation time 424410056 ps
CPU time 1.73 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 200408 kb
Host smart-0c03d12f-f7f7-4408-adb1-3676bb6a7f82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425190658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
425190658
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1876384454
Short name T603
Test name
Test status
Simulation time 62874439 ps
CPU time 0.79 seconds
Started May 14 12:42:51 PM PDT 24
Finished May 14 12:42:56 PM PDT 24
Peak memory 200200 kb
Host smart-7e81d854-d8e9-49ff-82d0-d6ec3fdcafa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876384454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1876384454
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3609332629
Short name T570
Test name
Test status
Simulation time 138166897 ps
CPU time 1.15 seconds
Started May 14 12:43:02 PM PDT 24
Finished May 14 12:43:07 PM PDT 24
Peak memory 200272 kb
Host smart-da09403b-8f43-4bee-a93d-8bbc863b3498
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609332629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3609332629
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.757569813
Short name T583
Test name
Test status
Simulation time 166738387 ps
CPU time 2.46 seconds
Started May 14 12:42:58 PM PDT 24
Finished May 14 12:43:04 PM PDT 24
Peak memory 208640 kb
Host smart-acda9e5a-2996-4012-805e-8e25e39f27ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757569813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.757569813
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.355106266
Short name T115
Test name
Test status
Simulation time 864960180 ps
CPU time 3.23 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:07 PM PDT 24
Peak memory 200504 kb
Host smart-56c3c0a8-8b97-41ea-98ee-1bad3589b69b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355106266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
355106266
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1047766039
Short name T607
Test name
Test status
Simulation time 180036582 ps
CPU time 1.22 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:04 PM PDT 24
Peak memory 209660 kb
Host smart-1abe454b-d771-497e-a957-6a6ae172b4c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047766039 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1047766039
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3625273403
Short name T100
Test name
Test status
Simulation time 58985243 ps
CPU time 0.75 seconds
Started May 14 12:42:49 PM PDT 24
Finished May 14 12:42:55 PM PDT 24
Peak memory 200264 kb
Host smart-2c11b01e-2300-406f-873d-e456722136cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625273403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3625273403
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3352220581
Short name T567
Test name
Test status
Simulation time 125121794 ps
CPU time 1.05 seconds
Started May 14 12:43:05 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 200116 kb
Host smart-1dd7f1fa-16cc-46ce-837b-81370c8a1aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352220581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3352220581
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2068812249
Short name T557
Test name
Test status
Simulation time 499697420 ps
CPU time 3.26 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:06 PM PDT 24
Peak memory 212208 kb
Host smart-5f785be5-f9d5-4876-ade7-1ce285553e68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068812249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2068812249
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1074532655
Short name T620
Test name
Test status
Simulation time 928830147 ps
CPU time 3.04 seconds
Started May 14 12:43:00 PM PDT 24
Finished May 14 12:43:08 PM PDT 24
Peak memory 200484 kb
Host smart-49d41675-a953-4e3c-81ba-195899f3db38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074532655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1074532655
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1586796199
Short name T556
Test name
Test status
Simulation time 117815262 ps
CPU time 1 seconds
Started May 14 12:42:51 PM PDT 24
Finished May 14 12:42:56 PM PDT 24
Peak memory 200312 kb
Host smart-cb084bf1-0d4b-4395-ab7b-39748347b733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586796199 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1586796199
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2702401923
Short name T563
Test name
Test status
Simulation time 62646945 ps
CPU time 0.85 seconds
Started May 14 12:42:50 PM PDT 24
Finished May 14 12:42:55 PM PDT 24
Peak memory 200156 kb
Host smart-e3372337-9c3a-4b1f-bf3b-759dcfcd1186
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702401923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2702401923
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3231877610
Short name T101
Test name
Test status
Simulation time 138666491 ps
CPU time 1.36 seconds
Started May 14 12:42:59 PM PDT 24
Finished May 14 12:43:05 PM PDT 24
Peak memory 200324 kb
Host smart-60f2eb63-76ea-4939-94a5-6003486eb167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231877610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3231877610
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2726819810
Short name T568
Test name
Test status
Simulation time 511360584 ps
CPU time 3.24 seconds
Started May 14 12:42:49 PM PDT 24
Finished May 14 12:42:57 PM PDT 24
Peak memory 208676 kb
Host smart-2da69f44-c9f8-4931-b704-6a4efdc3f5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726819810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2726819810
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2544535727
Short name T89
Test name
Test status
Simulation time 412487189 ps
CPU time 1.79 seconds
Started May 14 12:42:58 PM PDT 24
Finished May 14 12:43:04 PM PDT 24
Peak memory 200480 kb
Host smart-471f41a7-5fac-4c8a-8d19-960fe1f27686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544535727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2544535727
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2275218030
Short name T579
Test name
Test status
Simulation time 202492707 ps
CPU time 2.01 seconds
Started May 14 12:42:49 PM PDT 24
Finished May 14 12:42:56 PM PDT 24
Peak memory 208672 kb
Host smart-151d90ec-8a05-454f-a929-c205261add6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275218030 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2275218030
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.57960398
Short name T565
Test name
Test status
Simulation time 70665441 ps
CPU time 0.76 seconds
Started May 14 12:42:55 PM PDT 24
Finished May 14 12:42:58 PM PDT 24
Peak memory 200128 kb
Host smart-664695b4-9804-4780-8728-69b07e5f2858
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57960398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.57960398
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.95375422
Short name T105
Test name
Test status
Simulation time 135949340 ps
CPU time 1.26 seconds
Started May 14 12:42:57 PM PDT 24
Finished May 14 12:43:00 PM PDT 24
Peak memory 200468 kb
Host smart-670725a8-84ec-4ce0-a80d-08b7f7f659dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95375422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same
_csr_outstanding.95375422
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4241610981
Short name T604
Test name
Test status
Simulation time 138741814 ps
CPU time 1.94 seconds
Started May 14 12:42:51 PM PDT 24
Finished May 14 12:42:57 PM PDT 24
Peak memory 216772 kb
Host smart-f67aa904-0e90-4742-a147-ba651628f5d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241610981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.4241610981
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3103871091
Short name T110
Test name
Test status
Simulation time 887378229 ps
CPU time 2.98 seconds
Started May 14 12:42:52 PM PDT 24
Finished May 14 12:42:59 PM PDT 24
Peak memory 200396 kb
Host smart-c190e1db-2b61-4e9c-aa46-812007344a92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103871091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3103871091
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.196588469
Short name T590
Test name
Test status
Simulation time 114028989 ps
CPU time 0.88 seconds
Started May 14 12:43:06 PM PDT 24
Finished May 14 12:43:09 PM PDT 24
Peak memory 200268 kb
Host smart-d4e65542-4f8a-4ec8-b262-aa5ade52bd7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196588469 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.196588469
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3984752478
Short name T617
Test name
Test status
Simulation time 54198159 ps
CPU time 0.72 seconds
Started May 14 12:42:57 PM PDT 24
Finished May 14 12:43:01 PM PDT 24
Peak memory 200312 kb
Host smart-a69b430a-65b3-4333-b8f7-2271c8c98321
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984752478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3984752478
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.591257328
Short name T560
Test name
Test status
Simulation time 85988918 ps
CPU time 0.94 seconds
Started May 14 12:42:58 PM PDT 24
Finished May 14 12:43:02 PM PDT 24
Peak memory 200364 kb
Host smart-d383786f-5007-4911-a17b-12b2e12681f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591257328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.591257328
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2303923764
Short name T575
Test name
Test status
Simulation time 236832410 ps
CPU time 1.78 seconds
Started May 14 12:42:53 PM PDT 24
Finished May 14 12:42:58 PM PDT 24
Peak memory 210504 kb
Host smart-d06a1dec-e0cb-4e0c-ad37-663b351f409d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303923764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2303923764
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1952245820
Short name T130
Test name
Test status
Simulation time 446449422 ps
CPU time 1.76 seconds
Started May 14 12:42:49 PM PDT 24
Finished May 14 12:42:56 PM PDT 24
Peak memory 200520 kb
Host smart-f0b90285-32f4-4895-98b1-c1d7d1b20150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952245820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1952245820
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.943618723
Short name T155
Test name
Test status
Simulation time 82416329 ps
CPU time 0.75 seconds
Started May 14 12:43:09 PM PDT 24
Finished May 14 12:43:11 PM PDT 24
Peak memory 200132 kb
Host smart-919ec5c4-750d-427d-b89e-5f89b4cac20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943618723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.943618723
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1924680525
Short name T35
Test name
Test status
Simulation time 1225201326 ps
CPU time 5.46 seconds
Started May 14 12:43:10 PM PDT 24
Finished May 14 12:43:16 PM PDT 24
Peak memory 222000 kb
Host smart-bc9d6b74-0994-4a79-ba04-2dee568383fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924680525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1924680525
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2797447256
Short name T392
Test name
Test status
Simulation time 243903857 ps
CPU time 1.07 seconds
Started May 14 12:43:11 PM PDT 24
Finished May 14 12:43:13 PM PDT 24
Peak memory 217428 kb
Host smart-b5bb7a58-ed3a-4b33-be4d-2f2ccf7bf95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797447256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2797447256
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1365429314
Short name T326
Test name
Test status
Simulation time 1771086572 ps
CPU time 6.88 seconds
Started May 14 12:43:10 PM PDT 24
Finished May 14 12:43:18 PM PDT 24
Peak memory 200536 kb
Host smart-c98dc80d-10fd-4471-a186-0481a0f556ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365429314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1365429314
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.30944355
Short name T71
Test name
Test status
Simulation time 8401063599 ps
CPU time 12.35 seconds
Started May 14 12:43:11 PM PDT 24
Finished May 14 12:43:25 PM PDT 24
Peak memory 217712 kb
Host smart-42d9831c-cf30-461a-9277-a467401caaa4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30944355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.30944355
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2598002126
Short name T463
Test name
Test status
Simulation time 106693085 ps
CPU time 0.96 seconds
Started May 14 12:43:11 PM PDT 24
Finished May 14 12:43:13 PM PDT 24
Peak memory 200344 kb
Host smart-e5763906-0dcf-47ff-9a85-58a6aa82adf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598002126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2598002126
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.385968559
Short name T436
Test name
Test status
Simulation time 111855337 ps
CPU time 1.1 seconds
Started May 14 12:43:10 PM PDT 24
Finished May 14 12:43:12 PM PDT 24
Peak memory 200644 kb
Host smart-dcb2f75a-4522-49dd-8e39-ba27f31e1da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385968559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.385968559
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2087777755
Short name T416
Test name
Test status
Simulation time 3217931741 ps
CPU time 11.58 seconds
Started May 14 12:43:11 PM PDT 24
Finished May 14 12:43:24 PM PDT 24
Peak memory 200652 kb
Host smart-d0e4ddc3-6800-4882-8003-f1f8db459416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087777755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2087777755
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3220422236
Short name T310
Test name
Test status
Simulation time 329694848 ps
CPU time 2.15 seconds
Started May 14 12:43:11 PM PDT 24
Finished May 14 12:43:14 PM PDT 24
Peak memory 200340 kb
Host smart-13219c9d-0eac-4f37-85e5-a20aa7c8d280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220422236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3220422236
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.701392282
Short name T394
Test name
Test status
Simulation time 217452380 ps
CPU time 1.46 seconds
Started May 14 12:43:12 PM PDT 24
Finished May 14 12:43:14 PM PDT 24
Peak memory 200284 kb
Host smart-b73786fb-803c-4420-8162-1550327eba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701392282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.701392282
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3255659783
Short name T524
Test name
Test status
Simulation time 84666026 ps
CPU time 0.84 seconds
Started May 14 12:43:22 PM PDT 24
Finished May 14 12:43:23 PM PDT 24
Peak memory 200260 kb
Host smart-f4309c48-b702-47d8-84dc-9a5e41b8a3fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255659783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3255659783
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3470381258
Short name T520
Test name
Test status
Simulation time 1216671841 ps
CPU time 5.45 seconds
Started May 14 12:43:20 PM PDT 24
Finished May 14 12:43:26 PM PDT 24
Peak memory 217848 kb
Host smart-b3bc1937-c86c-441f-ba41-66efd9ba77c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470381258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3470381258
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4085349255
Short name T519
Test name
Test status
Simulation time 243775441 ps
CPU time 1.13 seconds
Started May 14 12:43:21 PM PDT 24
Finished May 14 12:43:22 PM PDT 24
Peak memory 217400 kb
Host smart-a8eb8fb0-71c7-4e01-968c-f81f40947fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085349255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4085349255
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.352159641
Short name T148
Test name
Test status
Simulation time 111499261 ps
CPU time 0.84 seconds
Started May 14 12:43:12 PM PDT 24
Finished May 14 12:43:14 PM PDT 24
Peak memory 200220 kb
Host smart-5d1c4a1d-d682-4a12-9465-a60e239f1fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352159641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.352159641
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1365220477
Short name T175
Test name
Test status
Simulation time 1775296513 ps
CPU time 7.58 seconds
Started May 14 12:43:11 PM PDT 24
Finished May 14 12:43:20 PM PDT 24
Peak memory 200556 kb
Host smart-0f9e1735-de10-45e1-a593-2b9cf11555fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365220477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1365220477
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1922447773
Short name T72
Test name
Test status
Simulation time 8423801747 ps
CPU time 14.14 seconds
Started May 14 12:43:20 PM PDT 24
Finished May 14 12:43:35 PM PDT 24
Peak memory 217756 kb
Host smart-87fe817c-0fa7-4cc1-9762-49d03959cd2a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922447773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1922447773
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3487387961
Short name T209
Test name
Test status
Simulation time 195534312 ps
CPU time 1.37 seconds
Started May 14 12:43:13 PM PDT 24
Finished May 14 12:43:15 PM PDT 24
Peak memory 200540 kb
Host smart-6d290ffe-05e1-4a4e-a48a-7cf81d72f31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487387961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3487387961
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3335841379
Short name T317
Test name
Test status
Simulation time 5200986297 ps
CPU time 23.44 seconds
Started May 14 12:43:21 PM PDT 24
Finished May 14 12:43:45 PM PDT 24
Peak memory 208832 kb
Host smart-2a87ce98-d666-4766-976d-06f18d6e34b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335841379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3335841379
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.345725970
Short name T363
Test name
Test status
Simulation time 321530057 ps
CPU time 2.11 seconds
Started May 14 12:43:10 PM PDT 24
Finished May 14 12:43:14 PM PDT 24
Peak memory 208564 kb
Host smart-73fd9e99-e36f-425d-84d7-def8282f3ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345725970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.345725970
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3517281824
Short name T440
Test name
Test status
Simulation time 153236140 ps
CPU time 1.03 seconds
Started May 14 12:43:11 PM PDT 24
Finished May 14 12:43:13 PM PDT 24
Peak memory 200348 kb
Host smart-0cc6e8da-2c91-4979-846a-bbc40dd551d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517281824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3517281824
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2343383474
Short name T243
Test name
Test status
Simulation time 77912093 ps
CPU time 0.8 seconds
Started May 14 12:43:36 PM PDT 24
Finished May 14 12:43:37 PM PDT 24
Peak memory 200212 kb
Host smart-5ac4f54f-690a-4a45-9ec2-7aa249a2a2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343383474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2343383474
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1142757981
Short name T47
Test name
Test status
Simulation time 1889623492 ps
CPU time 6.69 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:48 PM PDT 24
Peak memory 217028 kb
Host smart-bc663045-de9c-4904-8b28-128882521fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142757981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1142757981
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3368016853
Short name T438
Test name
Test status
Simulation time 244826955 ps
CPU time 1.17 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 217604 kb
Host smart-8761e5c6-891e-4e77-af30-f70bfadf3c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368016853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3368016853
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3420174110
Short name T419
Test name
Test status
Simulation time 176690202 ps
CPU time 0.88 seconds
Started May 14 12:43:38 PM PDT 24
Finished May 14 12:43:41 PM PDT 24
Peak memory 200092 kb
Host smart-c178a6a2-682c-4a48-a360-5a6adb168fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420174110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3420174110
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.963845136
Short name T92
Test name
Test status
Simulation time 985541784 ps
CPU time 4.87 seconds
Started May 14 12:43:38 PM PDT 24
Finished May 14 12:43:45 PM PDT 24
Peak memory 200468 kb
Host smart-ba9a0ef4-0459-4c92-bc64-d2007d41a5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963845136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.963845136
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.914891969
Short name T247
Test name
Test status
Simulation time 191446170 ps
CPU time 1.18 seconds
Started May 14 12:43:42 PM PDT 24
Finished May 14 12:43:46 PM PDT 24
Peak memory 200376 kb
Host smart-ec128a8d-a0d6-4cf8-8f98-bbb0960315aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914891969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.914891969
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1124981028
Short name T345
Test name
Test status
Simulation time 198238550 ps
CPU time 1.34 seconds
Started May 14 12:43:38 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 200604 kb
Host smart-e4521744-8a69-40c5-9893-fe0a1030235b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124981028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1124981028
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.4106624223
Short name T262
Test name
Test status
Simulation time 15148727467 ps
CPU time 56.22 seconds
Started May 14 12:43:41 PM PDT 24
Finished May 14 12:44:40 PM PDT 24
Peak memory 200688 kb
Host smart-8ca58093-9467-4a56-8e84-e32b88649125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106624223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.4106624223
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2391735133
Short name T191
Test name
Test status
Simulation time 265665732 ps
CPU time 1.7 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:44 PM PDT 24
Peak memory 200268 kb
Host smart-676eba39-9bb2-4a01-9a3b-e6882368b25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391735133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2391735133
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2979337902
Short name T335
Test name
Test status
Simulation time 158749495 ps
CPU time 1.2 seconds
Started May 14 12:43:35 PM PDT 24
Finished May 14 12:43:37 PM PDT 24
Peak memory 200544 kb
Host smart-ad666f51-05c0-4df2-b1b6-04c530ef7c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979337902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2979337902
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2895404551
Short name T421
Test name
Test status
Simulation time 72108732 ps
CPU time 0.78 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:43:48 PM PDT 24
Peak memory 200172 kb
Host smart-d0eb8952-320c-4ef7-897c-c12c5940fcfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895404551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2895404551
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3963319491
Short name T40
Test name
Test status
Simulation time 2348514341 ps
CPU time 9.15 seconds
Started May 14 12:43:53 PM PDT 24
Finished May 14 12:44:05 PM PDT 24
Peak memory 217548 kb
Host smart-8de5eb9f-5f98-4bee-ac1c-a39cb688f562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963319491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3963319491
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3630630611
Short name T525
Test name
Test status
Simulation time 244905335 ps
CPU time 1.12 seconds
Started May 14 12:43:55 PM PDT 24
Finished May 14 12:43:59 PM PDT 24
Peak memory 217500 kb
Host smart-e8c341a1-c7e1-4770-b3ef-2fd8a2082764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630630611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3630630611
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1106817144
Short name T166
Test name
Test status
Simulation time 183079158 ps
CPU time 0.9 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 200164 kb
Host smart-6c8d328e-4ae0-4f6a-ae29-17d7edd7cd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106817144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1106817144
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2655820268
Short name T439
Test name
Test status
Simulation time 1760219926 ps
CPU time 6.86 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:50 PM PDT 24
Peak memory 200512 kb
Host smart-8198edf8-94c5-436d-8d59-4e20ffbaf6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655820268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2655820268
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.993943629
Short name T287
Test name
Test status
Simulation time 108733482 ps
CPU time 1.01 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 200220 kb
Host smart-5b5b85ee-df04-4fba-b89e-6a552f77ec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993943629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.993943629
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.958675886
Short name T322
Test name
Test status
Simulation time 119569028 ps
CPU time 1.21 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:44 PM PDT 24
Peak memory 200508 kb
Host smart-0aee8dd5-7a5f-40a6-a9a2-86901ab08da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958675886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.958675886
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2242043788
Short name T352
Test name
Test status
Simulation time 6409869546 ps
CPU time 25.18 seconds
Started May 14 12:43:45 PM PDT 24
Finished May 14 12:44:11 PM PDT 24
Peak memory 208904 kb
Host smart-c22777b5-c0f5-413c-aa3a-947ad376c6a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242043788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2242043788
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1291008610
Short name T150
Test name
Test status
Simulation time 118442587 ps
CPU time 1.47 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 200700 kb
Host smart-993fbdd7-4aaa-40ab-a981-f612546f7d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291008610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1291008610
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.970132610
Short name T292
Test name
Test status
Simulation time 120568426 ps
CPU time 0.92 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 200444 kb
Host smart-7fd8f9e8-b342-4f18-ac7f-aeb812ebdddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970132610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.970132610
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1136671694
Short name T213
Test name
Test status
Simulation time 64494344 ps
CPU time 0.73 seconds
Started May 14 12:43:48 PM PDT 24
Finished May 14 12:43:51 PM PDT 24
Peak memory 200252 kb
Host smart-5999d281-d878-4edf-ae53-6439f53ea496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136671694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1136671694
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3867521427
Short name T324
Test name
Test status
Simulation time 1227467006 ps
CPU time 5.36 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:43:53 PM PDT 24
Peak memory 222084 kb
Host smart-5b62a4b0-b0dd-4555-98de-0e3d040eb2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867521427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3867521427
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1161731297
Short name T379
Test name
Test status
Simulation time 244530465 ps
CPU time 1.02 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 217432 kb
Host smart-dd5f6a47-8e3c-4ac2-ac49-5df04c24d627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161731297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1161731297
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2340492954
Short name T367
Test name
Test status
Simulation time 105781564 ps
CPU time 0.81 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 200144 kb
Host smart-1e9ff295-ef25-4016-8e91-394577103e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340492954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2340492954
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1164812207
Short name T505
Test name
Test status
Simulation time 1917173296 ps
CPU time 6.78 seconds
Started May 14 12:43:49 PM PDT 24
Finished May 14 12:43:58 PM PDT 24
Peak memory 200492 kb
Host smart-92ae4f4b-b7a0-4774-832c-246499738182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164812207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1164812207
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.328048625
Short name T14
Test name
Test status
Simulation time 185656438 ps
CPU time 1.22 seconds
Started May 14 12:43:48 PM PDT 24
Finished May 14 12:43:51 PM PDT 24
Peak memory 200360 kb
Host smart-40c1c9b6-a084-445c-83b3-556f22549ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328048625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.328048625
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1144239984
Short name T464
Test name
Test status
Simulation time 111484896 ps
CPU time 1.14 seconds
Started May 14 12:43:45 PM PDT 24
Finished May 14 12:43:47 PM PDT 24
Peak memory 200436 kb
Host smart-9562de78-51bd-456e-8b2c-2f4ec696cd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144239984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1144239984
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2780817307
Short name T309
Test name
Test status
Simulation time 4561073237 ps
CPU time 19.24 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:44:07 PM PDT 24
Peak memory 210260 kb
Host smart-155bc62b-5b13-4699-8d46-92a4f05c448e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780817307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2780817307
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1971871239
Short name T61
Test name
Test status
Simulation time 114446066 ps
CPU time 1.48 seconds
Started May 14 12:43:49 PM PDT 24
Finished May 14 12:43:52 PM PDT 24
Peak memory 200324 kb
Host smart-9b8eef02-ae93-4260-a090-d8133b2bac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971871239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1971871239
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3112078852
Short name T162
Test name
Test status
Simulation time 75522643 ps
CPU time 0.83 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:43:48 PM PDT 24
Peak memory 200344 kb
Host smart-cd8c9c2c-cff4-4bdd-8aa8-ec563bf067fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112078852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3112078852
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2799649322
Short name T319
Test name
Test status
Simulation time 245084299 ps
CPU time 1.05 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 217672 kb
Host smart-55dd024f-d097-4923-bbb1-c57019c481d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799649322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2799649322
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1081745914
Short name T395
Test name
Test status
Simulation time 141958392 ps
CPU time 0.92 seconds
Started May 14 12:43:53 PM PDT 24
Finished May 14 12:43:57 PM PDT 24
Peak memory 200120 kb
Host smart-4d7d77bf-c0bf-48c8-946e-c932fca405f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081745914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1081745914
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.756383953
Short name T385
Test name
Test status
Simulation time 1468922208 ps
CPU time 5.63 seconds
Started May 14 12:43:48 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 200536 kb
Host smart-b4ce7801-b529-4d01-9cee-2465ee2a7eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756383953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.756383953
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1708943404
Short name T177
Test name
Test status
Simulation time 155746275 ps
CPU time 1.2 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:57 PM PDT 24
Peak memory 200296 kb
Host smart-38ae18ca-b793-4fdc-aa7b-5c12e152d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708943404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1708943404
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2858238816
Short name T312
Test name
Test status
Simulation time 114866834 ps
CPU time 1.2 seconds
Started May 14 12:43:54 PM PDT 24
Finished May 14 12:43:58 PM PDT 24
Peak memory 200476 kb
Host smart-13ebaab5-eba8-468f-a6f2-abc2ce81aac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858238816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2858238816
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1029324264
Short name T499
Test name
Test status
Simulation time 6159496416 ps
CPU time 23.4 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:44:11 PM PDT 24
Peak memory 208884 kb
Host smart-cbfb1c6b-31a2-473e-bf52-267569eb49e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029324264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1029324264
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3274716117
Short name T29
Test name
Test status
Simulation time 137147461 ps
CPU time 1.8 seconds
Started May 14 12:43:53 PM PDT 24
Finished May 14 12:43:58 PM PDT 24
Peak memory 200392 kb
Host smart-35bbac9e-3af2-43a1-a1fe-f0b182e88f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274716117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3274716117
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1663409856
Short name T354
Test name
Test status
Simulation time 69329375 ps
CPU time 0.86 seconds
Started May 14 12:43:49 PM PDT 24
Finished May 14 12:43:52 PM PDT 24
Peak memory 200332 kb
Host smart-e83aff4b-405b-4447-8b56-ab3e5e2d406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663409856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1663409856
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1531787299
Short name T510
Test name
Test status
Simulation time 59165080 ps
CPU time 0.74 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 200260 kb
Host smart-44ac042e-43b9-4892-99cd-75bc35c75c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531787299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1531787299
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.576749352
Short name T435
Test name
Test status
Simulation time 1895334640 ps
CPU time 7.14 seconds
Started May 14 12:43:47 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 217980 kb
Host smart-d074bd23-cd82-4317-ad47-c0c8f4212a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576749352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.576749352
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2750281407
Short name T349
Test name
Test status
Simulation time 244452297 ps
CPU time 1.03 seconds
Started May 14 12:43:48 PM PDT 24
Finished May 14 12:43:51 PM PDT 24
Peak memory 217388 kb
Host smart-6058daff-ff38-405c-b84b-c53bba787d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750281407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2750281407
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3695043705
Short name T20
Test name
Test status
Simulation time 105446963 ps
CPU time 0.74 seconds
Started May 14 12:43:49 PM PDT 24
Finished May 14 12:43:52 PM PDT 24
Peak memory 200220 kb
Host smart-c961011e-1992-4d69-9abd-9cea79cf619b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695043705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3695043705
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.566256496
Short name T511
Test name
Test status
Simulation time 173034357 ps
CPU time 1.17 seconds
Started May 14 12:43:53 PM PDT 24
Finished May 14 12:43:57 PM PDT 24
Peak memory 200320 kb
Host smart-42e6bf2d-bf13-4128-aa55-4550e55c2e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566256496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.566256496
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.330402745
Short name T483
Test name
Test status
Simulation time 121372209 ps
CPU time 1.25 seconds
Started May 14 12:43:47 PM PDT 24
Finished May 14 12:43:50 PM PDT 24
Peak memory 200616 kb
Host smart-ff1a1b96-0b4c-4759-9f31-e9f3d74b2b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330402745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.330402745
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3202120638
Short name T501
Test name
Test status
Simulation time 3417512569 ps
CPU time 17.05 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:44:05 PM PDT 24
Peak memory 210480 kb
Host smart-fa6579aa-ff9e-42e2-bd32-61be8d236368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202120638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3202120638
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3810959178
Short name T142
Test name
Test status
Simulation time 151190918 ps
CPU time 1.89 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:43:49 PM PDT 24
Peak memory 200432 kb
Host smart-9c986bff-e256-44bc-9d6d-43b267419bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810959178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3810959178
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.466714320
Short name T320
Test name
Test status
Simulation time 231233611 ps
CPU time 1.32 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 200372 kb
Host smart-61e6bb12-482a-4c89-bbe9-3adc3ae422e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466714320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.466714320
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2027702969
Short name T4
Test name
Test status
Simulation time 79364142 ps
CPU time 0.76 seconds
Started May 14 12:43:45 PM PDT 24
Finished May 14 12:43:47 PM PDT 24
Peak memory 200184 kb
Host smart-f328e72e-a3b7-41cc-9f13-674f5c03ce4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027702969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2027702969
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2314428287
Short name T293
Test name
Test status
Simulation time 1888347195 ps
CPU time 8.5 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:44:02 PM PDT 24
Peak memory 217392 kb
Host smart-022a8a01-95f3-4fe6-a167-1036309ccdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314428287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2314428287
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2992396868
Short name T52
Test name
Test status
Simulation time 244647841 ps
CPU time 1.12 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 217584 kb
Host smart-7084e216-7821-48ab-bc1c-528e6481dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992396868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2992396868
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3257330586
Short name T230
Test name
Test status
Simulation time 232901403 ps
CPU time 1 seconds
Started May 14 12:43:45 PM PDT 24
Finished May 14 12:43:47 PM PDT 24
Peak memory 200124 kb
Host smart-4fc809a8-c6b8-4a72-8d6f-98052237a688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257330586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3257330586
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2623832308
Short name T418
Test name
Test status
Simulation time 1392419922 ps
CPU time 6.26 seconds
Started May 14 12:43:49 PM PDT 24
Finished May 14 12:43:57 PM PDT 24
Peak memory 200520 kb
Host smart-ab4c10ae-2729-4b25-ad0e-ea532ed07ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623832308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2623832308
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2465606874
Short name T54
Test name
Test status
Simulation time 169245210 ps
CPU time 1.13 seconds
Started May 14 12:43:48 PM PDT 24
Finished May 14 12:43:51 PM PDT 24
Peak memory 200340 kb
Host smart-37d0bd86-e3f1-406a-9219-394b39c4e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465606874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2465606874
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.856261995
Short name T276
Test name
Test status
Simulation time 187692984 ps
CPU time 1.35 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 200628 kb
Host smart-907f2ef1-a6c0-46f6-b1bb-5ee9496ebd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856261995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.856261995
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2909446829
Short name T399
Test name
Test status
Simulation time 5790496345 ps
CPU time 21.03 seconds
Started May 14 12:43:56 PM PDT 24
Finished May 14 12:44:19 PM PDT 24
Peak memory 200780 kb
Host smart-8128026b-e738-4e8d-832f-294a44c46f55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909446829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2909446829
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3440755364
Short name T396
Test name
Test status
Simulation time 358655078 ps
CPU time 2.02 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 200284 kb
Host smart-077fcf99-c87e-40cf-8917-503a141e2526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440755364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3440755364
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.440958517
Short name T377
Test name
Test status
Simulation time 60230986 ps
CPU time 0.76 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:43:53 PM PDT 24
Peak memory 200292 kb
Host smart-3580966f-1c8f-4a65-90e9-35c205c3ff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440958517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.440958517
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2840799090
Short name T223
Test name
Test status
Simulation time 60277738 ps
CPU time 0.77 seconds
Started May 14 12:43:48 PM PDT 24
Finished May 14 12:43:51 PM PDT 24
Peak memory 200156 kb
Host smart-3cb1aed9-d4d8-46ea-b4bb-2062e19e0947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840799090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2840799090
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1872043916
Short name T425
Test name
Test status
Simulation time 1904714516 ps
CPU time 7.41 seconds
Started May 14 12:43:47 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 218064 kb
Host smart-f0a9c0c9-0fb8-48af-982f-2e382615a6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872043916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1872043916
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2982981578
Short name T409
Test name
Test status
Simulation time 244666908 ps
CPU time 1.02 seconds
Started May 14 12:43:47 PM PDT 24
Finished May 14 12:43:50 PM PDT 24
Peak memory 217464 kb
Host smart-379b2bc1-621c-42c0-98aa-56cc1b71da21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982981578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2982981578
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3002422728
Short name T16
Test name
Test status
Simulation time 118240998 ps
CPU time 0.83 seconds
Started May 14 12:43:48 PM PDT 24
Finished May 14 12:43:51 PM PDT 24
Peak memory 200192 kb
Host smart-cf047421-9429-4f02-9867-0ffae4a40ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002422728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3002422728
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4244656707
Short name T484
Test name
Test status
Simulation time 1036333399 ps
CPU time 5.01 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:59 PM PDT 24
Peak memory 200584 kb
Host smart-f6f5332c-d09c-456a-bdd0-8a57472bf206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244656707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4244656707
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2476917224
Short name T443
Test name
Test status
Simulation time 162451780 ps
CPU time 1.17 seconds
Started May 14 12:43:45 PM PDT 24
Finished May 14 12:43:48 PM PDT 24
Peak memory 200408 kb
Host smart-dd53481b-55fa-4fab-8fb2-c01236bc7078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476917224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2476917224
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.243363651
Short name T67
Test name
Test status
Simulation time 120861425 ps
CPU time 1.2 seconds
Started May 14 12:43:47 PM PDT 24
Finished May 14 12:43:50 PM PDT 24
Peak memory 200532 kb
Host smart-ca993d6b-ecd9-45fd-bb76-1a886827d728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243363651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.243363651
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1336346
Short name T161
Test name
Test status
Simulation time 450459807 ps
CPU time 2.48 seconds
Started May 14 12:43:47 PM PDT 24
Finished May 14 12:43:52 PM PDT 24
Peak memory 200308 kb
Host smart-df44df81-a78b-4a8f-8a89-079ed38bdca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1336346
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2301792600
Short name T388
Test name
Test status
Simulation time 79570814 ps
CPU time 0.88 seconds
Started May 14 12:43:56 PM PDT 24
Finished May 14 12:44:00 PM PDT 24
Peak memory 200292 kb
Host smart-72420541-7b72-4197-9075-2eb0d479f75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301792600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2301792600
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.755687572
Short name T152
Test name
Test status
Simulation time 62363350 ps
CPU time 0.79 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 200272 kb
Host smart-3111469c-c9f1-4af5-b581-e184a29828ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755687572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.755687572
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.171387297
Short name T414
Test name
Test status
Simulation time 2342925713 ps
CPU time 8.02 seconds
Started May 14 12:43:56 PM PDT 24
Finished May 14 12:44:07 PM PDT 24
Peak memory 218072 kb
Host smart-42bd7568-3318-4ef6-affd-c5fa664447a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171387297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.171387297
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2788470737
Short name T370
Test name
Test status
Simulation time 244208888 ps
CPU time 1.06 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:43:48 PM PDT 24
Peak memory 217440 kb
Host smart-683392b1-5c4c-4721-a841-354d3fcefee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788470737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2788470737
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3543804967
Short name T400
Test name
Test status
Simulation time 141817106 ps
CPU time 0.81 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:43:48 PM PDT 24
Peak memory 200156 kb
Host smart-5f173c90-34e0-46f0-9962-c2cb17a86454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543804967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3543804967
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3303378553
Short name T242
Test name
Test status
Simulation time 858375394 ps
CPU time 3.98 seconds
Started May 14 12:43:45 PM PDT 24
Finished May 14 12:43:50 PM PDT 24
Peak memory 200616 kb
Host smart-3a8afd19-5e33-4951-a6e0-4c4df01d9601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303378553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3303378553
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1095848074
Short name T200
Test name
Test status
Simulation time 166150329 ps
CPU time 1.17 seconds
Started May 14 12:43:47 PM PDT 24
Finished May 14 12:43:50 PM PDT 24
Peak memory 200396 kb
Host smart-560ff41b-797e-46d2-a31b-256aa0b2c3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095848074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1095848074
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2153374170
Short name T299
Test name
Test status
Simulation time 117569123 ps
CPU time 1.12 seconds
Started May 14 12:43:46 PM PDT 24
Finished May 14 12:43:49 PM PDT 24
Peak memory 200580 kb
Host smart-a91d1598-74ea-4661-9b05-99fde767b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153374170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2153374170
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3779968233
Short name T475
Test name
Test status
Simulation time 514366235 ps
CPU time 2.19 seconds
Started May 14 12:43:48 PM PDT 24
Finished May 14 12:43:52 PM PDT 24
Peak memory 200576 kb
Host smart-707d3fcd-14c9-4a12-b8b6-db652142e84a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779968233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3779968233
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3571058199
Short name T235
Test name
Test status
Simulation time 127775728 ps
CPU time 1.5 seconds
Started May 14 12:43:47 PM PDT 24
Finished May 14 12:43:50 PM PDT 24
Peak memory 208500 kb
Host smart-647fe150-0d02-4a7d-a4ca-042a17c0d5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571058199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3571058199
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.788378224
Short name T372
Test name
Test status
Simulation time 146913365 ps
CPU time 1.3 seconds
Started May 14 12:43:48 PM PDT 24
Finished May 14 12:43:51 PM PDT 24
Peak memory 200540 kb
Host smart-69320503-c437-4177-9141-d7ee693f4499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788378224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.788378224
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.313151326
Short name T502
Test name
Test status
Simulation time 61157922 ps
CPU time 0.77 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 200124 kb
Host smart-c67ffbcc-7a05-4dd8-85ed-cc865b93eb2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313151326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.313151326
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1423682729
Short name T33
Test name
Test status
Simulation time 1228911345 ps
CPU time 5.54 seconds
Started May 14 12:43:56 PM PDT 24
Finished May 14 12:44:04 PM PDT 24
Peak memory 222124 kb
Host smart-d1b6324b-9048-4889-bccc-6a39bc6937a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423682729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1423682729
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4230885673
Short name T236
Test name
Test status
Simulation time 244406630 ps
CPU time 1.18 seconds
Started May 14 12:43:55 PM PDT 24
Finished May 14 12:43:59 PM PDT 24
Peak memory 217572 kb
Host smart-e186a06b-a0a1-4c9d-ba07-b35b2869b190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230885673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4230885673
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2626839657
Short name T23
Test name
Test status
Simulation time 225326887 ps
CPU time 0.91 seconds
Started May 14 12:43:53 PM PDT 24
Finished May 14 12:43:57 PM PDT 24
Peak memory 200212 kb
Host smart-9295d526-86dd-4b32-9c47-c4f8d57c6508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626839657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2626839657
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1887326056
Short name T50
Test name
Test status
Simulation time 913255127 ps
CPU time 4.47 seconds
Started May 14 12:43:47 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 200500 kb
Host smart-62567012-92fd-45be-8016-3b96c12cfe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887326056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1887326056
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2441536522
Short name T325
Test name
Test status
Simulation time 183323359 ps
CPU time 1.15 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 200344 kb
Host smart-72ed63ad-393e-4b76-9160-4beaff12c418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441536522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2441536522
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3058663038
Short name T459
Test name
Test status
Simulation time 126785263 ps
CPU time 1.16 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 200540 kb
Host smart-d3e2b3b0-3d51-491a-8fd4-5d2a64e95b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058663038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3058663038
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3632426464
Short name T466
Test name
Test status
Simulation time 2497137878 ps
CPU time 11.09 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:44:04 PM PDT 24
Peak memory 200696 kb
Host smart-d3b687d1-f017-4f81-96b4-1c9cafd9dbaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632426464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3632426464
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3744869888
Short name T341
Test name
Test status
Simulation time 139982436 ps
CPU time 1.86 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 200424 kb
Host smart-93030957-28e0-4033-9340-1fb84eea1b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744869888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3744869888
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1256372822
Short name T138
Test name
Test status
Simulation time 102957775 ps
CPU time 0.88 seconds
Started May 14 12:43:53 PM PDT 24
Finished May 14 12:43:57 PM PDT 24
Peak memory 200292 kb
Host smart-f3f8d2b1-65bf-47f1-942b-8b17bdef05f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256372822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1256372822
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4214085369
Short name T434
Test name
Test status
Simulation time 76615529 ps
CPU time 0.81 seconds
Started May 14 12:43:56 PM PDT 24
Finished May 14 12:44:00 PM PDT 24
Peak memory 200148 kb
Host smart-df91a1ef-52ce-4d41-bae6-e390bd434229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214085369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4214085369
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3696158467
Short name T391
Test name
Test status
Simulation time 1886996132 ps
CPU time 7.01 seconds
Started May 14 12:44:00 PM PDT 24
Finished May 14 12:44:10 PM PDT 24
Peak memory 217504 kb
Host smart-291fc5c8-41ca-4b48-b7b9-0baedaa15233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696158467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3696158467
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1673994545
Short name T257
Test name
Test status
Simulation time 244358955 ps
CPU time 1.11 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 217416 kb
Host smart-40bd12f7-76ca-47a8-be53-8e3de6dc0986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673994545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1673994545
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1269050605
Short name T199
Test name
Test status
Simulation time 142692537 ps
CPU time 0.82 seconds
Started May 14 12:43:53 PM PDT 24
Finished May 14 12:43:57 PM PDT 24
Peak memory 200236 kb
Host smart-6131f8dc-664c-49b5-8e87-2977abea8f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269050605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1269050605
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1343423490
Short name T431
Test name
Test status
Simulation time 1576133740 ps
CPU time 5.86 seconds
Started May 14 12:43:55 PM PDT 24
Finished May 14 12:44:03 PM PDT 24
Peak memory 200564 kb
Host smart-66706460-6758-4205-91be-60ba9e87338a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343423490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1343423490
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1836936822
Short name T304
Test name
Test status
Simulation time 183233906 ps
CPU time 1.25 seconds
Started May 14 12:43:57 PM PDT 24
Finished May 14 12:44:00 PM PDT 24
Peak memory 200316 kb
Host smart-cb918d5d-cfd3-4218-90d3-1127539a648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836936822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1836936822
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3434475712
Short name T507
Test name
Test status
Simulation time 116034615 ps
CPU time 1.27 seconds
Started May 14 12:43:54 PM PDT 24
Finished May 14 12:43:58 PM PDT 24
Peak memory 200292 kb
Host smart-57b5b4fd-145b-4dac-926b-669f365a567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434475712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3434475712
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.661292698
Short name T55
Test name
Test status
Simulation time 937987790 ps
CPU time 5.11 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:13 PM PDT 24
Peak memory 200504 kb
Host smart-70cd201a-072e-4215-99d7-cf9167d2b184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661292698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.661292698
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1834204873
Short name T239
Test name
Test status
Simulation time 128031595 ps
CPU time 0.96 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:03 PM PDT 24
Peak memory 200336 kb
Host smart-b02701bd-a6c6-45c1-8d8b-e1207931c369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834204873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1834204873
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1419684259
Short name T219
Test name
Test status
Simulation time 68490458 ps
CPU time 0.77 seconds
Started May 14 12:43:28 PM PDT 24
Finished May 14 12:43:30 PM PDT 24
Peak memory 200212 kb
Host smart-ca763586-3fbc-44b0-969a-23c6b827d57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419684259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1419684259
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2648181322
Short name T539
Test name
Test status
Simulation time 1880590360 ps
CPU time 6.99 seconds
Started May 14 12:43:20 PM PDT 24
Finished May 14 12:43:28 PM PDT 24
Peak memory 221932 kb
Host smart-72adda28-b698-4638-9ff2-61c01d9d3ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648181322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2648181322
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2857198216
Short name T231
Test name
Test status
Simulation time 244399974 ps
CPU time 1 seconds
Started May 14 12:43:21 PM PDT 24
Finished May 14 12:43:23 PM PDT 24
Peak memory 217488 kb
Host smart-d460b4c1-2562-4d80-9594-f3fe9ad6ba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857198216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2857198216
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4266230715
Short name T449
Test name
Test status
Simulation time 251820518 ps
CPU time 0.95 seconds
Started May 14 12:43:20 PM PDT 24
Finished May 14 12:43:22 PM PDT 24
Peak memory 200100 kb
Host smart-b9a05386-6855-4f60-93bc-6e32c61c92df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266230715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4266230715
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2359150792
Short name T375
Test name
Test status
Simulation time 1542004231 ps
CPU time 6.05 seconds
Started May 14 12:43:20 PM PDT 24
Finished May 14 12:43:26 PM PDT 24
Peak memory 200508 kb
Host smart-8771b871-dba2-4877-adc7-d23ab3e1e56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359150792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2359150792
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.40006635
Short name T73
Test name
Test status
Simulation time 8307723031 ps
CPU time 13.89 seconds
Started May 14 12:43:24 PM PDT 24
Finished May 14 12:43:38 PM PDT 24
Peak memory 217360 kb
Host smart-01f406da-0b3e-44d6-914e-666826f027b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40006635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.40006635
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1926592683
Short name T523
Test name
Test status
Simulation time 94031937 ps
CPU time 0.98 seconds
Started May 14 12:43:22 PM PDT 24
Finished May 14 12:43:24 PM PDT 24
Peak memory 200356 kb
Host smart-5eee8d4f-0591-4922-9fcc-4d85220fc3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926592683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1926592683
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2435480287
Short name T240
Test name
Test status
Simulation time 249400147 ps
CPU time 1.42 seconds
Started May 14 12:43:19 PM PDT 24
Finished May 14 12:43:21 PM PDT 24
Peak memory 200516 kb
Host smart-9713bcd5-2169-4dc4-b2c8-bb1fb483a32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435480287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2435480287
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.15443714
Short name T189
Test name
Test status
Simulation time 2895256208 ps
CPU time 15.44 seconds
Started May 14 12:43:25 PM PDT 24
Finished May 14 12:43:41 PM PDT 24
Peak memory 200676 kb
Host smart-ce4e2ac3-2a05-4e3a-aa90-1d853c608d2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15443714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.15443714
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1294903925
Short name T250
Test name
Test status
Simulation time 131107956 ps
CPU time 1.78 seconds
Started May 14 12:43:25 PM PDT 24
Finished May 14 12:43:27 PM PDT 24
Peak memory 208616 kb
Host smart-707580f5-5d87-49af-8fd2-9ad3bec85d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294903925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1294903925
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2862154690
Short name T332
Test name
Test status
Simulation time 130658787 ps
CPU time 1.02 seconds
Started May 14 12:43:21 PM PDT 24
Finished May 14 12:43:23 PM PDT 24
Peak memory 200448 kb
Host smart-64b2ee6d-c597-42f3-8d40-210d41df09c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862154690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2862154690
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3181433378
Short name T316
Test name
Test status
Simulation time 70399168 ps
CPU time 0.74 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200216 kb
Host smart-53e68c1c-5397-44c5-88fd-d4b58e511f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181433378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3181433378
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2834918964
Short name T259
Test name
Test status
Simulation time 2368554885 ps
CPU time 7.82 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:44:03 PM PDT 24
Peak memory 222136 kb
Host smart-69f488c4-1da3-44eb-bc37-1ed4f3f485e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834918964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2834918964
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3417408068
Short name T172
Test name
Test status
Simulation time 244195331 ps
CPU time 1.18 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 217424 kb
Host smart-b2787838-04d3-4005-8670-803c78cb9d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417408068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3417408068
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.841022224
Short name T390
Test name
Test status
Simulation time 92415907 ps
CPU time 0.78 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:55 PM PDT 24
Peak memory 200244 kb
Host smart-0ee130d5-c3a3-4475-8305-265185c688e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841022224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.841022224
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1227959156
Short name T154
Test name
Test status
Simulation time 1484116650 ps
CPU time 6 seconds
Started May 14 12:43:56 PM PDT 24
Finished May 14 12:44:05 PM PDT 24
Peak memory 200524 kb
Host smart-f53f2ec6-a84a-414b-8018-f68e66bef851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227959156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1227959156
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.904608765
Short name T413
Test name
Test status
Simulation time 112896890 ps
CPU time 1 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200404 kb
Host smart-1541ef32-e7e8-490d-ab10-06e75e4860e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904608765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.904608765
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1955347641
Short name T374
Test name
Test status
Simulation time 110403049 ps
CPU time 1.21 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200488 kb
Host smart-f961bc31-2530-43bd-94af-bd44161829a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955347641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1955347641
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.572822045
Short name T123
Test name
Test status
Simulation time 8280423241 ps
CPU time 29.99 seconds
Started May 14 12:44:00 PM PDT 24
Finished May 14 12:44:32 PM PDT 24
Peak memory 208864 kb
Host smart-b2d3987c-f790-4065-abf8-9ae5d657852c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572822045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.572822045
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1075852483
Short name T404
Test name
Test status
Simulation time 336870468 ps
CPU time 2.24 seconds
Started May 14 12:43:53 PM PDT 24
Finished May 14 12:43:58 PM PDT 24
Peak memory 208604 kb
Host smart-ea7be0d6-66e3-4882-bbbe-073ae210f8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075852483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1075852483
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1718912501
Short name T346
Test name
Test status
Simulation time 66248434 ps
CPU time 0.75 seconds
Started May 14 12:43:56 PM PDT 24
Finished May 14 12:43:59 PM PDT 24
Peak memory 200368 kb
Host smart-3b2b06f1-7560-41b2-a986-a519d3331a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718912501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1718912501
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2338074513
Short name T286
Test name
Test status
Simulation time 60573568 ps
CPU time 0.71 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 200256 kb
Host smart-d20d4d4f-cb1a-4336-adfd-2140e7e60ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338074513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2338074513
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1141990975
Short name T298
Test name
Test status
Simulation time 244363462 ps
CPU time 1.11 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 217380 kb
Host smart-84c19df2-e8a7-48e2-9ca2-253f7d4c9887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141990975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1141990975
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2345580343
Short name T531
Test name
Test status
Simulation time 122900821 ps
CPU time 0.81 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200192 kb
Host smart-a6087707-3eb2-41a9-8821-b88a2965c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345580343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2345580343
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.607997051
Short name T205
Test name
Test status
Simulation time 764490046 ps
CPU time 4.04 seconds
Started May 14 12:44:01 PM PDT 24
Finished May 14 12:44:07 PM PDT 24
Peak memory 200552 kb
Host smart-58c8f89e-7e10-4f19-9f64-aa83cd65fbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607997051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.607997051
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3300759397
Short name T296
Test name
Test status
Simulation time 150081418 ps
CPU time 1.09 seconds
Started May 14 12:43:56 PM PDT 24
Finished May 14 12:44:00 PM PDT 24
Peak memory 200360 kb
Host smart-c41e0f4c-7eee-42f7-8af6-c6a8e167088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300759397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3300759397
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2179610017
Short name T164
Test name
Test status
Simulation time 199370042 ps
CPU time 1.35 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200556 kb
Host smart-390eb15f-dd50-434c-a261-ba1ec99a02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179610017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2179610017
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1439631476
Short name T291
Test name
Test status
Simulation time 1551210095 ps
CPU time 6.09 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:14 PM PDT 24
Peak memory 200592 kb
Host smart-4d887c07-4253-49ab-94af-478d6dbea750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439631476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1439631476
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1405678728
Short name T237
Test name
Test status
Simulation time 466662520 ps
CPU time 2.5 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:10 PM PDT 24
Peak memory 200348 kb
Host smart-73d87f8b-a53e-43a5-ad19-648d71a97b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405678728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1405678728
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.818094158
Short name T272
Test name
Test status
Simulation time 155737223 ps
CPU time 1.01 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 200288 kb
Host smart-72ac8b68-fca1-45fc-a4d3-c82bd65102ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818094158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.818094158
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3288916013
Short name T321
Test name
Test status
Simulation time 71905228 ps
CPU time 0.71 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:02 PM PDT 24
Peak memory 200156 kb
Host smart-7272fccc-e35e-4481-b51f-979c56109766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288916013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3288916013
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2892100834
Short name T538
Test name
Test status
Simulation time 1913592124 ps
CPU time 6.79 seconds
Started May 14 12:43:55 PM PDT 24
Finished May 14 12:44:05 PM PDT 24
Peak memory 216992 kb
Host smart-547b1d97-740b-4448-9b2b-47aa0585d350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892100834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2892100834
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.365088012
Short name T136
Test name
Test status
Simulation time 244161968 ps
CPU time 1.22 seconds
Started May 14 12:43:55 PM PDT 24
Finished May 14 12:43:59 PM PDT 24
Peak memory 217580 kb
Host smart-17568bd7-45b7-48b6-a168-972ec8f1c644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365088012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.365088012
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2969370452
Short name T17
Test name
Test status
Simulation time 154374785 ps
CPU time 0.84 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 200172 kb
Host smart-49e7b39f-decb-42db-bff6-132bac84dd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969370452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2969370452
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2965611312
Short name T121
Test name
Test status
Simulation time 1593134446 ps
CPU time 5.55 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:13 PM PDT 24
Peak memory 200564 kb
Host smart-2f200e13-1633-42a3-98e7-2379f55f2050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965611312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2965611312
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3618067489
Short name T51
Test name
Test status
Simulation time 151579719 ps
CPU time 1.17 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200356 kb
Host smart-c5785fbc-4030-4497-b3c2-5cb21e29b595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618067489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3618067489
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3002278958
Short name T453
Test name
Test status
Simulation time 201320247 ps
CPU time 1.46 seconds
Started May 14 12:43:52 PM PDT 24
Finished May 14 12:43:56 PM PDT 24
Peak memory 200508 kb
Host smart-f3112def-c000-422c-bc08-f3af4d7b5e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002278958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3002278958
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.96414660
Short name T280
Test name
Test status
Simulation time 3062510804 ps
CPU time 13.61 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:22 PM PDT 24
Peak memory 200900 kb
Host smart-963dcd6b-f727-434d-8d4b-8c238eb77ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96414660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.96414660
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1489835578
Short name T369
Test name
Test status
Simulation time 314858371 ps
CPU time 2.21 seconds
Started May 14 12:44:00 PM PDT 24
Finished May 14 12:44:05 PM PDT 24
Peak memory 208524 kb
Host smart-f88dbd8f-0240-4ffe-9602-80aca44a5b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489835578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1489835578
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1020015999
Short name T294
Test name
Test status
Simulation time 187365064 ps
CPU time 1.17 seconds
Started May 14 12:43:50 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 200348 kb
Host smart-a7ee7883-d294-4aac-9fa7-a3011eae95b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020015999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1020015999
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3630068029
Short name T485
Test name
Test status
Simulation time 80491665 ps
CPU time 0.76 seconds
Started May 14 12:43:58 PM PDT 24
Finished May 14 12:44:01 PM PDT 24
Peak memory 200260 kb
Host smart-617f953f-9cd4-4e7e-bf73-77c7ebab9409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630068029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3630068029
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2964583756
Short name T140
Test name
Test status
Simulation time 244370788 ps
CPU time 1.09 seconds
Started May 14 12:44:03 PM PDT 24
Finished May 14 12:44:05 PM PDT 24
Peak memory 217796 kb
Host smart-d9fac83d-775e-42d6-9892-e67a3e41f539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964583756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2964583756
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3137906702
Short name T350
Test name
Test status
Simulation time 135907930 ps
CPU time 0.81 seconds
Started May 14 12:43:51 PM PDT 24
Finished May 14 12:43:54 PM PDT 24
Peak memory 200224 kb
Host smart-dec05a6f-b67a-489c-a29c-0e4725d2c6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137906702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3137906702
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1196598223
Short name T169
Test name
Test status
Simulation time 767318782 ps
CPU time 3.78 seconds
Started May 14 12:44:00 PM PDT 24
Finished May 14 12:44:06 PM PDT 24
Peak memory 200528 kb
Host smart-db511884-7bc8-487a-9ae0-cabf620c84b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196598223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1196598223
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1115529352
Short name T401
Test name
Test status
Simulation time 177704456 ps
CPU time 1.3 seconds
Started May 14 12:43:58 PM PDT 24
Finished May 14 12:44:02 PM PDT 24
Peak memory 200340 kb
Host smart-ebbca087-1049-41ff-9610-fe89355df446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115529352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1115529352
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3991343548
Short name T347
Test name
Test status
Simulation time 254898557 ps
CPU time 1.55 seconds
Started May 14 12:43:54 PM PDT 24
Finished May 14 12:43:59 PM PDT 24
Peak memory 200232 kb
Host smart-7262d52e-340f-4a1e-ad15-ed8e5394db66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991343548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3991343548
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2107431572
Short name T297
Test name
Test status
Simulation time 6914912510 ps
CPU time 22.85 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:31 PM PDT 24
Peak memory 208904 kb
Host smart-961b3154-d5b0-4289-87e4-05591f106ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107431572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2107431572
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1508060322
Short name T127
Test name
Test status
Simulation time 464323836 ps
CPU time 2.61 seconds
Started May 14 12:43:57 PM PDT 24
Finished May 14 12:44:02 PM PDT 24
Peak memory 200412 kb
Host smart-e71bf07d-8c8b-45b9-a819-37f4e0f6dcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508060322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1508060322
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3341020434
Short name T244
Test name
Test status
Simulation time 96440150 ps
CPU time 0.86 seconds
Started May 14 12:43:57 PM PDT 24
Finished May 14 12:44:00 PM PDT 24
Peak memory 200212 kb
Host smart-7ef609d9-d9cb-4b0c-ae1a-23e4532f93f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341020434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3341020434
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3019993072
Short name T461
Test name
Test status
Simulation time 1887369571 ps
CPU time 7.68 seconds
Started May 14 12:44:01 PM PDT 24
Finished May 14 12:44:10 PM PDT 24
Peak memory 218044 kb
Host smart-0fec5200-13e8-443f-9d9a-bd519d3dbc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019993072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3019993072
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2344423723
Short name T82
Test name
Test status
Simulation time 244415139 ps
CPU time 1.1 seconds
Started May 14 12:43:57 PM PDT 24
Finished May 14 12:44:01 PM PDT 24
Peak memory 217640 kb
Host smart-0a90ed16-4a54-4770-9db9-63adaf6371eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344423723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2344423723
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.829863931
Short name T25
Test name
Test status
Simulation time 123240798 ps
CPU time 0.78 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:02 PM PDT 24
Peak memory 200208 kb
Host smart-b691832c-08f7-4d63-a30d-46b284eecc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829863931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.829863931
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.674894675
Short name T441
Test name
Test status
Simulation time 1256367545 ps
CPU time 4.7 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:06 PM PDT 24
Peak memory 200544 kb
Host smart-f0be9be1-fbea-4c59-858a-98fce68ef85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674894675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.674894675
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2037511529
Short name T145
Test name
Test status
Simulation time 143359773 ps
CPU time 1.08 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:02 PM PDT 24
Peak memory 200388 kb
Host smart-f998a5d0-ec6c-438d-b67d-390266d144a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037511529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2037511529
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1568391925
Short name T513
Test name
Test status
Simulation time 118373654 ps
CPU time 1.2 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:03 PM PDT 24
Peak memory 200568 kb
Host smart-6d94656a-6ad2-48c1-8af3-434d71c534d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568391925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1568391925
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3579464041
Short name T380
Test name
Test status
Simulation time 2623019531 ps
CPU time 12.5 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:14 PM PDT 24
Peak memory 209380 kb
Host smart-55575d9f-7471-400f-be8c-a41a62e6c22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579464041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3579464041
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1359016909
Short name T80
Test name
Test status
Simulation time 354774630 ps
CPU time 2.12 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:10 PM PDT 24
Peak memory 200352 kb
Host smart-49491dde-f60c-43ef-a372-b8080e2de431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359016909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1359016909
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2752303877
Short name T157
Test name
Test status
Simulation time 73909549 ps
CPU time 0.75 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:01 PM PDT 24
Peak memory 200420 kb
Host smart-e83cdb77-7574-448a-a389-67c1fbe5d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752303877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2752303877
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1378671542
Short name T344
Test name
Test status
Simulation time 74397107 ps
CPU time 0.77 seconds
Started May 14 12:44:07 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200212 kb
Host smart-5b98a5fb-442a-4d44-a4dc-9aad85c70b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378671542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1378671542
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.734035872
Short name T283
Test name
Test status
Simulation time 244158829 ps
CPU time 1.05 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:03 PM PDT 24
Peak memory 217364 kb
Host smart-8b959ad0-17c3-4ca4-b213-d2bf7524a6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734035872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.734035872
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3376546139
Short name T315
Test name
Test status
Simulation time 89619009 ps
CPU time 0.82 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:02 PM PDT 24
Peak memory 200248 kb
Host smart-a0d50345-134a-44ad-90bf-3333eeb8cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376546139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3376546139
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1549432196
Short name T94
Test name
Test status
Simulation time 1786800738 ps
CPU time 6.49 seconds
Started May 14 12:43:57 PM PDT 24
Finished May 14 12:44:06 PM PDT 24
Peak memory 200580 kb
Host smart-a5926002-9ed1-4995-b0d4-78362cfceadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549432196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1549432196
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1308136316
Short name T465
Test name
Test status
Simulation time 169449155 ps
CPU time 1.16 seconds
Started May 14 12:43:58 PM PDT 24
Finished May 14 12:44:01 PM PDT 24
Peak memory 200336 kb
Host smart-63e019e4-36d2-4366-b7e7-30eb27f66b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308136316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1308136316
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1009914849
Short name T469
Test name
Test status
Simulation time 194565434 ps
CPU time 1.47 seconds
Started May 14 12:44:01 PM PDT 24
Finished May 14 12:44:04 PM PDT 24
Peak memory 200552 kb
Host smart-0fae2e2e-006d-46b1-9cc9-826997b8288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009914849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1009914849
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.620248264
Short name T27
Test name
Test status
Simulation time 5496284029 ps
CPU time 23.52 seconds
Started May 14 12:44:03 PM PDT 24
Finished May 14 12:44:27 PM PDT 24
Peak memory 210896 kb
Host smart-5089920c-8ce7-4f00-aa59-043374bd2002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620248264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.620248264
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.207133517
Short name T340
Test name
Test status
Simulation time 122243965 ps
CPU time 1.59 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:10 PM PDT 24
Peak memory 208604 kb
Host smart-9df91c93-2bd5-49c7-ad0e-7929b1ed9ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207133517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.207133517
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1815569651
Short name T495
Test name
Test status
Simulation time 243610285 ps
CPU time 1.53 seconds
Started May 14 12:43:59 PM PDT 24
Finished May 14 12:44:03 PM PDT 24
Peak memory 200516 kb
Host smart-0d70f29e-16e6-4c67-9ada-8e940323a68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815569651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1815569651
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3489908094
Short name T412
Test name
Test status
Simulation time 74571856 ps
CPU time 0.78 seconds
Started May 14 12:44:05 PM PDT 24
Finished May 14 12:44:07 PM PDT 24
Peak memory 200152 kb
Host smart-dcee176e-5cc0-4d1f-82dd-555de83b87c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489908094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3489908094
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1024081663
Short name T300
Test name
Test status
Simulation time 2371793846 ps
CPU time 9.12 seconds
Started May 14 12:44:07 PM PDT 24
Finished May 14 12:44:18 PM PDT 24
Peak memory 222288 kb
Host smart-bda8a563-e238-445f-b5ef-8151875a5d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024081663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1024081663
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2735819802
Short name T398
Test name
Test status
Simulation time 243440899 ps
CPU time 1.07 seconds
Started May 14 12:44:08 PM PDT 24
Finished May 14 12:44:11 PM PDT 24
Peak memory 217564 kb
Host smart-29bfc6ff-24a2-45fb-959f-20d2fda79052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735819802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2735819802
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1566791531
Short name T246
Test name
Test status
Simulation time 188409828 ps
CPU time 0.87 seconds
Started May 14 12:44:07 PM PDT 24
Finished May 14 12:44:10 PM PDT 24
Peak memory 200240 kb
Host smart-f00c931d-2b87-4709-a900-7e653f726130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566791531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1566791531
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1286062133
Short name T407
Test name
Test status
Simulation time 1451286701 ps
CPU time 5.16 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:12 PM PDT 24
Peak memory 200592 kb
Host smart-3a53d757-72c0-4050-863e-1c9a8c514d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286062133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1286062133
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3062762442
Short name T266
Test name
Test status
Simulation time 98366286 ps
CPU time 1.03 seconds
Started May 14 12:44:05 PM PDT 24
Finished May 14 12:44:07 PM PDT 24
Peak memory 200336 kb
Host smart-c90d0383-2f2e-41ad-9353-4e243b7a5d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062762442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3062762442
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3831835383
Short name T216
Test name
Test status
Simulation time 233916996 ps
CPU time 1.51 seconds
Started May 14 12:44:07 PM PDT 24
Finished May 14 12:44:10 PM PDT 24
Peak memory 200612 kb
Host smart-80593065-4384-4a2e-ae24-e5921829145c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831835383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3831835383
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1518944909
Short name T424
Test name
Test status
Simulation time 4449314076 ps
CPU time 15.56 seconds
Started May 14 12:44:05 PM PDT 24
Finished May 14 12:44:21 PM PDT 24
Peak memory 200748 kb
Host smart-9cb4a9c2-06b1-4e82-b87a-180a6e9b75cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518944909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1518944909
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2076603912
Short name T473
Test name
Test status
Simulation time 520377215 ps
CPU time 2.75 seconds
Started May 14 12:44:04 PM PDT 24
Finished May 14 12:44:08 PM PDT 24
Peak memory 200384 kb
Host smart-de06dcb0-528a-40d5-8c0e-c816f7f92b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076603912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2076603912
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1685539618
Short name T339
Test name
Test status
Simulation time 140692061 ps
CPU time 1.16 seconds
Started May 14 12:44:09 PM PDT 24
Finished May 14 12:44:12 PM PDT 24
Peak memory 200292 kb
Host smart-c89e1965-7a0b-4314-bc4c-18318bb1ad40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685539618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1685539618
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2362157070
Short name T183
Test name
Test status
Simulation time 61239975 ps
CPU time 0.75 seconds
Started May 14 12:44:05 PM PDT 24
Finished May 14 12:44:06 PM PDT 24
Peak memory 200172 kb
Host smart-e79c4427-287b-486b-9d96-cc02189e4baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362157070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2362157070
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.20102595
Short name T57
Test name
Test status
Simulation time 1224251340 ps
CPU time 5.54 seconds
Started May 14 12:44:05 PM PDT 24
Finished May 14 12:44:11 PM PDT 24
Peak memory 216916 kb
Host smart-046200e2-f778-4b4d-a2dd-d7f470c88890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20102595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.20102595
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1808705132
Short name T423
Test name
Test status
Simulation time 245030314 ps
CPU time 1.06 seconds
Started May 14 12:44:08 PM PDT 24
Finished May 14 12:44:11 PM PDT 24
Peak memory 217680 kb
Host smart-938e5074-17df-4712-8b75-a59e5d7bbd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808705132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1808705132
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.646798170
Short name T24
Test name
Test status
Simulation time 164026597 ps
CPU time 0.91 seconds
Started May 14 12:44:10 PM PDT 24
Finished May 14 12:44:12 PM PDT 24
Peak memory 200208 kb
Host smart-f3b17c0d-e0ce-4646-b961-d688d188ed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646798170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.646798170
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1761089979
Short name T251
Test name
Test status
Simulation time 912964670 ps
CPU time 4.61 seconds
Started May 14 12:44:08 PM PDT 24
Finished May 14 12:44:15 PM PDT 24
Peak memory 200568 kb
Host smart-4db62ec6-0238-4760-af84-7deeb2f14674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761089979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1761089979
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.736718838
Short name T141
Test name
Test status
Simulation time 97856513 ps
CPU time 0.95 seconds
Started May 14 12:44:08 PM PDT 24
Finished May 14 12:44:11 PM PDT 24
Peak memory 200460 kb
Host smart-a05cc9b2-2df0-4499-9c2e-f2acb0be92c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736718838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.736718838
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.806291544
Short name T256
Test name
Test status
Simulation time 126455560 ps
CPU time 1.18 seconds
Started May 14 12:44:09 PM PDT 24
Finished May 14 12:44:12 PM PDT 24
Peak memory 200476 kb
Host smart-814d2abc-5d9d-4c85-9368-bbc575d35145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806291544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.806291544
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2364440232
Short name T452
Test name
Test status
Simulation time 244983783 ps
CPU time 1.29 seconds
Started May 14 12:44:07 PM PDT 24
Finished May 14 12:44:10 PM PDT 24
Peak memory 200372 kb
Host smart-5bb2baff-415c-48fd-896e-03babfc256be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364440232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2364440232
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3387043828
Short name T160
Test name
Test status
Simulation time 144790918 ps
CPU time 1.8 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200456 kb
Host smart-cf15fa18-196f-4dd8-b339-e3a21497af4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387043828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3387043828
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.678896478
Short name T430
Test name
Test status
Simulation time 120236675 ps
CPU time 1.01 seconds
Started May 14 12:44:07 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200452 kb
Host smart-27cd41ff-af3d-4393-8555-ab8f8fc385ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678896478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.678896478
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.327522361
Short name T415
Test name
Test status
Simulation time 149914355 ps
CPU time 0.91 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:16 PM PDT 24
Peak memory 200264 kb
Host smart-104b35f7-e870-4685-81c8-01268dd4e52d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327522361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.327522361
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1634190484
Short name T46
Test name
Test status
Simulation time 1231616865 ps
CPU time 6.43 seconds
Started May 14 12:44:18 PM PDT 24
Finished May 14 12:44:25 PM PDT 24
Peak memory 221624 kb
Host smart-56631d5f-e45b-487e-841f-b24405448baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634190484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1634190484
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.284630239
Short name T139
Test name
Test status
Simulation time 244072930 ps
CPU time 1.05 seconds
Started May 14 12:44:13 PM PDT 24
Finished May 14 12:44:16 PM PDT 24
Peak memory 217404 kb
Host smart-2dbde2f8-c306-49d0-aa4e-b4c99c5a522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284630239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.284630239
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2497657988
Short name T22
Test name
Test status
Simulation time 183829513 ps
CPU time 0.87 seconds
Started May 14 12:44:09 PM PDT 24
Finished May 14 12:44:11 PM PDT 24
Peak memory 200212 kb
Host smart-c266ca3e-9e75-4803-a205-3a4bbc30269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497657988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2497657988
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.170416094
Short name T254
Test name
Test status
Simulation time 1057241385 ps
CPU time 5.1 seconds
Started May 14 12:44:07 PM PDT 24
Finished May 14 12:44:14 PM PDT 24
Peak memory 200608 kb
Host smart-0adf080e-dd6d-49f5-b9af-71286296ff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170416094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.170416094
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3142731334
Short name T288
Test name
Test status
Simulation time 141623227 ps
CPU time 1.07 seconds
Started May 14 12:44:09 PM PDT 24
Finished May 14 12:44:12 PM PDT 24
Peak memory 200400 kb
Host smart-a59dde87-153c-4ae7-a503-e11c65a084be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142731334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3142731334
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1273766451
Short name T533
Test name
Test status
Simulation time 187995452 ps
CPU time 1.3 seconds
Started May 14 12:44:07 PM PDT 24
Finished May 14 12:44:10 PM PDT 24
Peak memory 200536 kb
Host smart-d597fc09-0ce6-4c6a-9c88-1aa742699ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273766451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1273766451
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1797673263
Short name T217
Test name
Test status
Simulation time 179332371 ps
CPU time 1.17 seconds
Started May 14 12:44:15 PM PDT 24
Finished May 14 12:44:17 PM PDT 24
Peak memory 200352 kb
Host smart-ea3d489a-4f67-417b-a8c8-6138e164ee67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797673263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1797673263
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1034438769
Short name T6
Test name
Test status
Simulation time 341363824 ps
CPU time 2.1 seconds
Started May 14 12:44:06 PM PDT 24
Finished May 14 12:44:09 PM PDT 24
Peak memory 200324 kb
Host smart-07060eb9-2624-451f-b504-6319ed4040d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034438769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1034438769
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3860277915
Short name T188
Test name
Test status
Simulation time 138411405 ps
CPU time 1.08 seconds
Started May 14 12:44:05 PM PDT 24
Finished May 14 12:44:07 PM PDT 24
Peak memory 200396 kb
Host smart-254fd42c-436c-4b53-8491-5587f11fd66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860277915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3860277915
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3435263930
Short name T498
Test name
Test status
Simulation time 77621101 ps
CPU time 0.77 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:16 PM PDT 24
Peak memory 200148 kb
Host smart-8df97e77-6694-41a7-8e9e-14979a9f19b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435263930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3435263930
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2055343470
Short name T275
Test name
Test status
Simulation time 1882707193 ps
CPU time 7.88 seconds
Started May 14 12:44:22 PM PDT 24
Finished May 14 12:44:31 PM PDT 24
Peak memory 221584 kb
Host smart-8dd0523e-863d-4943-963c-4b775e15e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055343470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2055343470
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.658633012
Short name T371
Test name
Test status
Simulation time 243741707 ps
CPU time 1.08 seconds
Started May 14 12:44:18 PM PDT 24
Finished May 14 12:44:20 PM PDT 24
Peak memory 217772 kb
Host smart-dfbe7bdd-6241-48b7-9936-0d139cba6446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658633012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.658633012
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.394316665
Short name T311
Test name
Test status
Simulation time 103733188 ps
CPU time 0.75 seconds
Started May 14 12:44:21 PM PDT 24
Finished May 14 12:44:22 PM PDT 24
Peak memory 200188 kb
Host smart-a1054133-98da-4949-8e52-4882684f399c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394316665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.394316665
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2063402099
Short name T402
Test name
Test status
Simulation time 872702031 ps
CPU time 4.28 seconds
Started May 14 12:44:15 PM PDT 24
Finished May 14 12:44:20 PM PDT 24
Peak memory 200524 kb
Host smart-8ccb412a-e4de-4659-84c0-00cf839c8774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063402099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2063402099
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3407248695
Short name T334
Test name
Test status
Simulation time 189235077 ps
CPU time 1.24 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:17 PM PDT 24
Peak memory 200332 kb
Host smart-aed8e659-e48a-49b0-87b1-a5677508f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407248695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3407248695
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2674812161
Short name T227
Test name
Test status
Simulation time 121359773 ps
CPU time 1.23 seconds
Started May 14 12:44:15 PM PDT 24
Finished May 14 12:44:17 PM PDT 24
Peak memory 200484 kb
Host smart-e3756ba5-a845-44ea-a216-152ab784f489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674812161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2674812161
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1541675236
Short name T98
Test name
Test status
Simulation time 3616678851 ps
CPU time 15.92 seconds
Started May 14 12:44:22 PM PDT 24
Finished May 14 12:44:39 PM PDT 24
Peak memory 208940 kb
Host smart-ac126d3e-8c4e-4f3f-a42a-d7e584cd2022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541675236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1541675236
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3642844060
Short name T508
Test name
Test status
Simulation time 305490796 ps
CPU time 1.92 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:18 PM PDT 24
Peak memory 208560 kb
Host smart-54353e1f-ec7f-44e0-8395-4a172cf2ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642844060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3642844060
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3799906645
Short name T504
Test name
Test status
Simulation time 132623172 ps
CPU time 0.98 seconds
Started May 14 12:44:15 PM PDT 24
Finished May 14 12:44:17 PM PDT 24
Peak memory 200344 kb
Host smart-be1bb013-8808-4fa3-b9ee-967c47a302ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799906645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3799906645
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1656861128
Short name T353
Test name
Test status
Simulation time 64695309 ps
CPU time 0.75 seconds
Started May 14 12:43:27 PM PDT 24
Finished May 14 12:43:29 PM PDT 24
Peak memory 200168 kb
Host smart-bb3b411f-65f6-4260-8fc1-2476adbe6b77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656861128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1656861128
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1604954868
Short name T265
Test name
Test status
Simulation time 2175175340 ps
CPU time 7.65 seconds
Started May 14 12:43:31 PM PDT 24
Finished May 14 12:43:39 PM PDT 24
Peak memory 217760 kb
Host smart-08ca678f-c43e-45aa-a853-b8b7032be522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604954868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1604954868
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.735100145
Short name T147
Test name
Test status
Simulation time 244858503 ps
CPU time 1.05 seconds
Started May 14 12:43:31 PM PDT 24
Finished May 14 12:43:33 PM PDT 24
Peak memory 217312 kb
Host smart-e432a80b-30f2-42ee-814e-c6c056fae4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735100145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.735100145
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.452395115
Short name T143
Test name
Test status
Simulation time 185874151 ps
CPU time 0.89 seconds
Started May 14 12:43:31 PM PDT 24
Finished May 14 12:43:33 PM PDT 24
Peak memory 200092 kb
Host smart-cb1f44f9-8a20-4895-b06c-41d4634c3cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452395115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.452395115
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3101769773
Short name T422
Test name
Test status
Simulation time 2076250933 ps
CPU time 7.93 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:38 PM PDT 24
Peak memory 200520 kb
Host smart-7804d1c8-756f-4c46-94e1-13b7747251d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101769773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3101769773
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1295822681
Short name T149
Test name
Test status
Simulation time 99248127 ps
CPU time 0.99 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:31 PM PDT 24
Peak memory 200424 kb
Host smart-0bf5e2d5-8b63-4967-9d6f-27afcdc51dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295822681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1295822681
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3693493793
Short name T214
Test name
Test status
Simulation time 191114397 ps
CPU time 1.32 seconds
Started May 14 12:43:31 PM PDT 24
Finished May 14 12:43:33 PM PDT 24
Peak memory 200528 kb
Host smart-1c828472-bd2d-4e01-81b0-55bd736e8f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693493793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3693493793
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3581389257
Short name T10
Test name
Test status
Simulation time 9725266503 ps
CPU time 33.15 seconds
Started May 14 12:43:27 PM PDT 24
Finished May 14 12:44:01 PM PDT 24
Peak memory 200616 kb
Host smart-1d7ad790-e0ab-49c0-b5c5-4cbe7bec9051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581389257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3581389257
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3601687650
Short name T165
Test name
Test status
Simulation time 339116466 ps
CPU time 1.82 seconds
Started May 14 12:43:30 PM PDT 24
Finished May 14 12:43:32 PM PDT 24
Peak memory 200320 kb
Host smart-fcc753fa-b2b5-4a67-95ea-56677c1ff1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601687650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3601687650
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3783258408
Short name T515
Test name
Test status
Simulation time 126484688 ps
CPU time 1.06 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:31 PM PDT 24
Peak memory 200372 kb
Host smart-49ca908e-72b1-4f05-8429-9500363569f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783258408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3783258408
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2447568553
Short name T225
Test name
Test status
Simulation time 90582759 ps
CPU time 0.88 seconds
Started May 14 12:44:18 PM PDT 24
Finished May 14 12:44:19 PM PDT 24
Peak memory 199844 kb
Host smart-84edab1d-dcab-4f74-bc8d-0763b2eeb4fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447568553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2447568553
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.688724396
Short name T451
Test name
Test status
Simulation time 1893372399 ps
CPU time 7.52 seconds
Started May 14 12:44:18 PM PDT 24
Finished May 14 12:44:26 PM PDT 24
Peak memory 222132 kb
Host smart-7b882e96-7ad0-4ed8-9457-b2f363ab26a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688724396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.688724396
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3129147285
Short name T305
Test name
Test status
Simulation time 243989676 ps
CPU time 1.02 seconds
Started May 14 12:44:15 PM PDT 24
Finished May 14 12:44:17 PM PDT 24
Peak memory 217436 kb
Host smart-7ca4178b-9792-44b7-915f-faae22a11c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129147285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3129147285
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1969488585
Short name T329
Test name
Test status
Simulation time 184072965 ps
CPU time 0.84 seconds
Started May 14 12:44:13 PM PDT 24
Finished May 14 12:44:16 PM PDT 24
Peak memory 200200 kb
Host smart-b9f780b5-7fa6-4cde-9d61-110e414afef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969488585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1969488585
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2669066128
Short name T120
Test name
Test status
Simulation time 1558411401 ps
CPU time 6.14 seconds
Started May 14 12:44:13 PM PDT 24
Finished May 14 12:44:21 PM PDT 24
Peak memory 200564 kb
Host smart-efb873af-b91f-48ae-9b9e-6908d134e554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669066128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2669066128
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.862528715
Short name T146
Test name
Test status
Simulation time 97748400 ps
CPU time 1.07 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:16 PM PDT 24
Peak memory 200404 kb
Host smart-1d99b6ae-4494-490f-93d1-ae5b7c414d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862528715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.862528715
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4033284623
Short name T168
Test name
Test status
Simulation time 118290418 ps
CPU time 1.13 seconds
Started May 14 12:44:12 PM PDT 24
Finished May 14 12:44:14 PM PDT 24
Peak memory 200632 kb
Host smart-a9513909-1bc7-4446-a6e4-77008abe328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033284623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4033284623
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3830898381
Short name T222
Test name
Test status
Simulation time 1575950651 ps
CPU time 6.14 seconds
Started May 14 12:44:15 PM PDT 24
Finished May 14 12:44:22 PM PDT 24
Peak memory 200568 kb
Host smart-71bbfc25-a749-4789-99b7-997b03ef842d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830898381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3830898381
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.877678130
Short name T181
Test name
Test status
Simulation time 121032499 ps
CPU time 1.44 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:17 PM PDT 24
Peak memory 200340 kb
Host smart-3e3728dd-5524-407a-ba9f-b1c5403a3568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877678130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.877678130
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3359346326
Short name T277
Test name
Test status
Simulation time 197869337 ps
CPU time 1.22 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:17 PM PDT 24
Peak memory 200476 kb
Host smart-59120792-bd43-44b8-bf02-d6aa0bebf882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359346326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3359346326
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3246709981
Short name T526
Test name
Test status
Simulation time 72409468 ps
CPU time 0.79 seconds
Started May 14 12:44:13 PM PDT 24
Finished May 14 12:44:16 PM PDT 24
Peak memory 200100 kb
Host smart-4562e114-a3df-4fd4-a485-6b18377e59dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246709981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3246709981
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3295999731
Short name T356
Test name
Test status
Simulation time 1887303693 ps
CPU time 6.7 seconds
Started May 14 12:44:15 PM PDT 24
Finished May 14 12:44:23 PM PDT 24
Peak memory 222048 kb
Host smart-2ab25ec1-1d11-4f31-9a0f-a8dfef1c9d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295999731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3295999731
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1680859336
Short name T420
Test name
Test status
Simulation time 243818149 ps
CPU time 1.13 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:17 PM PDT 24
Peak memory 217584 kb
Host smart-aa70ff01-cf66-4ebc-b725-07852c22cdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680859336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1680859336
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1371115604
Short name T193
Test name
Test status
Simulation time 150944176 ps
CPU time 0.85 seconds
Started May 14 12:44:16 PM PDT 24
Finished May 14 12:44:18 PM PDT 24
Peak memory 200152 kb
Host smart-a1f3afbd-7842-422d-b278-1c18c9a72c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371115604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1371115604
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.4178080125
Short name T376
Test name
Test status
Simulation time 926081834 ps
CPU time 4.54 seconds
Started May 14 12:44:22 PM PDT 24
Finished May 14 12:44:27 PM PDT 24
Peak memory 200588 kb
Host smart-374a0e7d-8762-4e16-82d3-65f06a3b2266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178080125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4178080125
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.250326708
Short name T366
Test name
Test status
Simulation time 182358943 ps
CPU time 1.16 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:17 PM PDT 24
Peak memory 200324 kb
Host smart-1b1e9a59-2507-4ce6-9eea-ca807b42b020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250326708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.250326708
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2912079229
Short name T301
Test name
Test status
Simulation time 237693717 ps
CPU time 1.48 seconds
Started May 14 12:44:12 PM PDT 24
Finished May 14 12:44:14 PM PDT 24
Peak memory 200560 kb
Host smart-5eec3511-8f2d-480b-ab51-341d375a4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912079229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2912079229
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3359799647
Short name T12
Test name
Test status
Simulation time 2553515724 ps
CPU time 12.41 seconds
Started May 14 12:44:14 PM PDT 24
Finished May 14 12:44:28 PM PDT 24
Peak memory 210208 kb
Host smart-ec3aad60-dfd3-4c3f-a787-3abf320700d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359799647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3359799647
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3454977487
Short name T171
Test name
Test status
Simulation time 265775774 ps
CPU time 1.84 seconds
Started May 14 12:44:12 PM PDT 24
Finished May 14 12:44:15 PM PDT 24
Peak memory 200496 kb
Host smart-c1cc7fdb-674a-4c24-8ee8-4baeaa56056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454977487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3454977487
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.375455508
Short name T487
Test name
Test status
Simulation time 68624420 ps
CPU time 0.77 seconds
Started May 14 12:44:12 PM PDT 24
Finished May 14 12:44:14 PM PDT 24
Peak memory 200344 kb
Host smart-fbb34958-3d03-406e-8c03-1b9dcd757f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375455508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.375455508
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2446991305
Short name T9
Test name
Test status
Simulation time 62066474 ps
CPU time 0.75 seconds
Started May 14 12:44:27 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200184 kb
Host smart-2af2fd10-bf33-4b3d-b43a-cd4eb87ce690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446991305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2446991305
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1459405620
Short name T284
Test name
Test status
Simulation time 1893336563 ps
CPU time 7.35 seconds
Started May 14 12:44:23 PM PDT 24
Finished May 14 12:44:32 PM PDT 24
Peak memory 217364 kb
Host smart-04c5360c-9d21-499a-bd8e-02b988e306c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459405620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1459405620
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1872245727
Short name T403
Test name
Test status
Simulation time 244702771 ps
CPU time 1.1 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:27 PM PDT 24
Peak memory 217508 kb
Host smart-5e1dcf25-b05e-410c-83a9-b2a8c07ee010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872245727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1872245727
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.846282468
Short name T348
Test name
Test status
Simulation time 77146500 ps
CPU time 0.72 seconds
Started May 14 12:44:26 PM PDT 24
Finished May 14 12:44:28 PM PDT 24
Peak memory 200192 kb
Host smart-39047521-7195-40fb-bce7-54898ba2bf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846282468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.846282468
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1289674601
Short name T273
Test name
Test status
Simulation time 761670786 ps
CPU time 4.21 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:30 PM PDT 24
Peak memory 200532 kb
Host smart-c3e0664e-388d-433d-a2b1-ae360c00794e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289674601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1289674601
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3627744313
Short name T182
Test name
Test status
Simulation time 157443684 ps
CPU time 1.14 seconds
Started May 14 12:44:21 PM PDT 24
Finished May 14 12:44:23 PM PDT 24
Peak memory 200380 kb
Host smart-7bf8f92f-8003-40f2-8e1c-9cd960e19565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627744313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3627744313
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3280515149
Short name T176
Test name
Test status
Simulation time 121982812 ps
CPU time 1.16 seconds
Started May 14 12:44:20 PM PDT 24
Finished May 14 12:44:21 PM PDT 24
Peak memory 200516 kb
Host smart-63820fe6-9d98-4453-8595-95e9a3c0b201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280515149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3280515149
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.177464261
Short name T97
Test name
Test status
Simulation time 11604875272 ps
CPU time 39.44 seconds
Started May 14 12:44:24 PM PDT 24
Finished May 14 12:45:05 PM PDT 24
Peak memory 209208 kb
Host smart-83bb21fe-85fe-4d27-8305-f683c34a1f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177464261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.177464261
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.188221862
Short name T522
Test name
Test status
Simulation time 290375227 ps
CPU time 1.96 seconds
Started May 14 12:44:23 PM PDT 24
Finished May 14 12:44:26 PM PDT 24
Peak memory 208676 kb
Host smart-5ea8c945-24e0-496c-b8bd-a519cb650be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188221862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.188221862
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3227904998
Short name T496
Test name
Test status
Simulation time 85484362 ps
CPU time 0.82 seconds
Started May 14 12:44:20 PM PDT 24
Finished May 14 12:44:22 PM PDT 24
Peak memory 200412 kb
Host smart-a9e7b819-01bd-41b6-90b0-195e68f87084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227904998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3227904998
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1560155764
Short name T158
Test name
Test status
Simulation time 74201418 ps
CPU time 0.8 seconds
Started May 14 12:44:22 PM PDT 24
Finished May 14 12:44:24 PM PDT 24
Peak memory 200128 kb
Host smart-37ec4ced-676f-4445-b0c7-32bce55ae78e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560155764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1560155764
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.90859745
Short name T58
Test name
Test status
Simulation time 2353926778 ps
CPU time 8.27 seconds
Started May 14 12:44:22 PM PDT 24
Finished May 14 12:44:31 PM PDT 24
Peak memory 218160 kb
Host smart-ee1ea461-2b79-4f50-aa05-0783ef75fa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90859745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.90859745
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2796186594
Short name T426
Test name
Test status
Simulation time 249151818 ps
CPU time 1.2 seconds
Started May 14 12:44:22 PM PDT 24
Finished May 14 12:44:25 PM PDT 24
Peak memory 217456 kb
Host smart-0022c971-5c03-4f68-bc99-0f3bbbf746c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796186594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2796186594
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.865183807
Short name T509
Test name
Test status
Simulation time 130205329 ps
CPU time 0.86 seconds
Started May 14 12:44:24 PM PDT 24
Finished May 14 12:44:26 PM PDT 24
Peak memory 200124 kb
Host smart-f13a4c85-4f1b-4e52-87a2-5c0852570641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865183807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.865183807
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.889884584
Short name T393
Test name
Test status
Simulation time 1186999837 ps
CPU time 5.45 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:32 PM PDT 24
Peak memory 200700 kb
Host smart-46387c8f-bf4e-44bf-aee4-f4191e54c536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889884584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.889884584
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2268369616
Short name T202
Test name
Test status
Simulation time 100070389 ps
CPU time 1.05 seconds
Started May 14 12:44:26 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200400 kb
Host smart-98ec56cd-f162-4aab-b3ae-c411a7f2467a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268369616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2268369616
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.143265855
Short name T125
Test name
Test status
Simulation time 235534879 ps
CPU time 1.57 seconds
Started May 14 12:44:26 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200568 kb
Host smart-513e34b0-d1cc-4203-8ec4-60f379ac0bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143265855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.143265855
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2922518573
Short name T134
Test name
Test status
Simulation time 361835120 ps
CPU time 1.78 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:28 PM PDT 24
Peak memory 200620 kb
Host smart-7bb33a55-f6ab-4e26-9a9c-3866f9e8797a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922518573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2922518573
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.260736534
Short name T81
Test name
Test status
Simulation time 441739702 ps
CPU time 2.31 seconds
Started May 14 12:44:28 PM PDT 24
Finished May 14 12:44:32 PM PDT 24
Peak memory 200448 kb
Host smart-ab6c1d4e-187c-48de-a768-42a2e776fef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260736534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.260736534
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.870511729
Short name T343
Test name
Test status
Simulation time 155495366 ps
CPU time 1.22 seconds
Started May 14 12:44:22 PM PDT 24
Finished May 14 12:44:25 PM PDT 24
Peak memory 200516 kb
Host smart-e413c3d1-f2dd-4e3d-a419-34050fdbdb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870511729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.870511729
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.613691788
Short name T318
Test name
Test status
Simulation time 89869257 ps
CPU time 0.8 seconds
Started May 14 12:44:24 PM PDT 24
Finished May 14 12:44:26 PM PDT 24
Peak memory 200260 kb
Host smart-bb5c39c3-3fcf-4db0-8468-070fc757e259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613691788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.613691788
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.926776532
Short name T271
Test name
Test status
Simulation time 1893005296 ps
CPU time 7.06 seconds
Started May 14 12:44:29 PM PDT 24
Finished May 14 12:44:37 PM PDT 24
Peak memory 218064 kb
Host smart-1624e8f7-a9ab-4a62-a3fc-da145248ff4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926776532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.926776532
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4097628954
Short name T529
Test name
Test status
Simulation time 244359702 ps
CPU time 1.01 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:27 PM PDT 24
Peak memory 217476 kb
Host smart-eb231ca3-1cee-4179-975b-9fd90a783e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097628954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4097628954
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3834847441
Short name T211
Test name
Test status
Simulation time 183033167 ps
CPU time 0.89 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:35 PM PDT 24
Peak memory 200236 kb
Host smart-9d3d27d2-9425-418c-b355-d031483e40ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834847441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3834847441
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2447693473
Short name T95
Test name
Test status
Simulation time 886619772 ps
CPU time 4.22 seconds
Started May 14 12:44:22 PM PDT 24
Finished May 14 12:44:27 PM PDT 24
Peak memory 200528 kb
Host smart-e4f4ed7c-303c-4453-a96a-e24a4b78849d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447693473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2447693473
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2142632974
Short name T174
Test name
Test status
Simulation time 146620403 ps
CPU time 1.18 seconds
Started May 14 12:44:27 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200404 kb
Host smart-c60de9bc-86a8-40c5-a6a9-afaa985a552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142632974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2142632974
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2997938361
Short name T410
Test name
Test status
Simulation time 116024554 ps
CPU time 1.15 seconds
Started May 14 12:44:26 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200500 kb
Host smart-93a56275-3b9e-4380-b9af-60ee041c16b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997938361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2997938361
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3862783406
Short name T186
Test name
Test status
Simulation time 2771920479 ps
CPU time 13.55 seconds
Started May 14 12:44:21 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200736 kb
Host smart-45a0acc6-7008-43fb-9f9f-444e54907d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862783406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3862783406
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3337495851
Short name T228
Test name
Test status
Simulation time 116663357 ps
CPU time 1.54 seconds
Started May 14 12:44:24 PM PDT 24
Finished May 14 12:44:26 PM PDT 24
Peak memory 200704 kb
Host smart-43762b33-cdcb-47da-ab26-5b5ab2bdf354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337495851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3337495851
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3639695352
Short name T184
Test name
Test status
Simulation time 173277917 ps
CPU time 1.18 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:28 PM PDT 24
Peak memory 200360 kb
Host smart-ee78ab2e-9a8b-483e-a957-7e7c04510c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639695352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3639695352
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3553509379
Short name T220
Test name
Test status
Simulation time 70067721 ps
CPU time 0.79 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:27 PM PDT 24
Peak memory 200152 kb
Host smart-df7181dc-6f26-4ace-b409-59940b61cc69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553509379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3553509379
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1992446417
Short name T224
Test name
Test status
Simulation time 1239840976 ps
CPU time 5.8 seconds
Started May 14 12:44:23 PM PDT 24
Finished May 14 12:44:30 PM PDT 24
Peak memory 222060 kb
Host smart-cef2a0b5-524a-4811-a26a-2b1be6057032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992446417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1992446417
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2658623496
Short name T536
Test name
Test status
Simulation time 244204430 ps
CPU time 1.05 seconds
Started May 14 12:44:26 PM PDT 24
Finished May 14 12:44:28 PM PDT 24
Peak memory 217484 kb
Host smart-63f10583-4418-420b-b125-26bd16c1fe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658623496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2658623496
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1592430848
Short name T537
Test name
Test status
Simulation time 84747471 ps
CPU time 0.74 seconds
Started May 14 12:44:27 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200160 kb
Host smart-bd0905ff-e717-4b0f-bf5a-881e43126f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592430848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1592430848
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2431140804
Short name T450
Test name
Test status
Simulation time 831916138 ps
CPU time 3.72 seconds
Started May 14 12:44:28 PM PDT 24
Finished May 14 12:44:34 PM PDT 24
Peak memory 200608 kb
Host smart-e2e3534d-2a39-4e9e-82e3-3faccf8b54f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431140804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2431140804
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2579399426
Short name T198
Test name
Test status
Simulation time 145456181 ps
CPU time 1.07 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:28 PM PDT 24
Peak memory 200336 kb
Host smart-fe049c1b-c6a8-4d76-858b-4f2c774e3664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579399426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2579399426
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3020910263
Short name T253
Test name
Test status
Simulation time 252774592 ps
CPU time 1.51 seconds
Started May 14 12:44:29 PM PDT 24
Finished May 14 12:44:32 PM PDT 24
Peak memory 200580 kb
Host smart-ab668160-d7c1-4bfb-9729-1ac555772fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020910263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3020910263
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1133533631
Short name T28
Test name
Test status
Simulation time 5263108943 ps
CPU time 19.83 seconds
Started May 14 12:44:20 PM PDT 24
Finished May 14 12:44:40 PM PDT 24
Peak memory 208908 kb
Host smart-4e673d60-f31c-475d-99ce-a441728c350f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133533631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1133533631
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2505403480
Short name T477
Test name
Test status
Simulation time 124787608 ps
CPU time 1.46 seconds
Started May 14 12:44:26 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200412 kb
Host smart-d5c7fc96-63b0-4357-a46b-347642c01574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505403480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2505403480
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3515554761
Short name T493
Test name
Test status
Simulation time 218535620 ps
CPU time 1.34 seconds
Started May 14 12:44:27 PM PDT 24
Finished May 14 12:44:30 PM PDT 24
Peak memory 200396 kb
Host smart-e2ab5788-66a6-40aa-9bbb-5dbd074653a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515554761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3515554761
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.600337292
Short name T229
Test name
Test status
Simulation time 70997951 ps
CPU time 0.8 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:33 PM PDT 24
Peak memory 200236 kb
Host smart-65c2c807-87f4-45ea-9d53-448418adcce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600337292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.600337292
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3237748796
Short name T43
Test name
Test status
Simulation time 1894472084 ps
CPU time 7.28 seconds
Started May 14 12:44:27 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 222120 kb
Host smart-cf96df66-421e-4549-8338-f0cc927d6e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237748796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3237748796
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2704259138
Short name T307
Test name
Test status
Simulation time 244317658 ps
CPU time 1.14 seconds
Started May 14 12:44:24 PM PDT 24
Finished May 14 12:44:26 PM PDT 24
Peak memory 217516 kb
Host smart-441047e2-9285-4277-a473-9b0dee9f3567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704259138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2704259138
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.546910045
Short name T478
Test name
Test status
Simulation time 184361574 ps
CPU time 0.92 seconds
Started May 14 12:44:23 PM PDT 24
Finished May 14 12:44:25 PM PDT 24
Peak memory 200164 kb
Host smart-365734ec-f34c-4600-8e16-2f9d598f6ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546910045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.546910045
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.303520600
Short name T447
Test name
Test status
Simulation time 1860833878 ps
CPU time 7.36 seconds
Started May 14 12:44:27 PM PDT 24
Finished May 14 12:44:37 PM PDT 24
Peak memory 200532 kb
Host smart-7a9b16b2-78f2-41ea-b3c4-bc1b70bceabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303520600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.303520600
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1140878238
Short name T212
Test name
Test status
Simulation time 96943655 ps
CPU time 0.99 seconds
Started May 14 12:44:26 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200348 kb
Host smart-77c0af47-7c55-4d24-8a3e-12222d9522d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140878238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1140878238
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2722716459
Short name T355
Test name
Test status
Simulation time 123439335 ps
CPU time 1.15 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:28 PM PDT 24
Peak memory 200520 kb
Host smart-8d790c41-ddd7-45a7-bfd0-49eeabbc0a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722716459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2722716459
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1342884941
Short name T185
Test name
Test status
Simulation time 1145663512 ps
CPU time 5.49 seconds
Started May 14 12:44:23 PM PDT 24
Finished May 14 12:44:30 PM PDT 24
Peak memory 200680 kb
Host smart-880c5c2c-2a2a-4996-a050-98f64e237244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342884941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1342884941
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.51372597
Short name T373
Test name
Test status
Simulation time 126399242 ps
CPU time 1.62 seconds
Started May 14 12:44:25 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200488 kb
Host smart-79b27559-d361-47c5-ad85-5a968ee20590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51372597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.51372597
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1807057859
Short name T408
Test name
Test status
Simulation time 143534495 ps
CPU time 1.14 seconds
Started May 14 12:44:26 PM PDT 24
Finished May 14 12:44:29 PM PDT 24
Peak memory 200372 kb
Host smart-05c20fb9-cb9e-40a5-81af-20ebd1918be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807057859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1807057859
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1400106787
Short name T192
Test name
Test status
Simulation time 73066817 ps
CPU time 0.84 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:34 PM PDT 24
Peak memory 200172 kb
Host smart-bf230c1a-c93e-4f11-9029-8ea3aa20725f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400106787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1400106787
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1375163261
Short name T36
Test name
Test status
Simulation time 1882499458 ps
CPU time 7.37 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:40 PM PDT 24
Peak memory 221996 kb
Host smart-97bb8e56-817e-4ca0-bad5-7c6d28c5b06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375163261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1375163261
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.134880411
Short name T1
Test name
Test status
Simulation time 243834101 ps
CPU time 1.06 seconds
Started May 14 12:44:34 PM PDT 24
Finished May 14 12:44:37 PM PDT 24
Peak memory 217412 kb
Host smart-3e3b9e12-f1ec-4dad-8fe9-3f219fef7942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134880411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.134880411
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1054783179
Short name T382
Test name
Test status
Simulation time 95493817 ps
CPU time 0.76 seconds
Started May 14 12:44:28 PM PDT 24
Finished May 14 12:44:31 PM PDT 24
Peak memory 200148 kb
Host smart-396d78aa-4501-480f-a2c2-0cfc8e92a0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054783179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1054783179
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.928922535
Short name T281
Test name
Test status
Simulation time 751909684 ps
CPU time 4.03 seconds
Started May 14 12:44:32 PM PDT 24
Finished May 14 12:44:38 PM PDT 24
Peak memory 200564 kb
Host smart-aee8262b-2b1c-447e-bb39-33516a81beae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928922535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.928922535
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.4160572978
Short name T173
Test name
Test status
Simulation time 107280391 ps
CPU time 1.01 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:33 PM PDT 24
Peak memory 200396 kb
Host smart-afd81fb2-5dec-4c49-a4a6-4b75c14da34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160572978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.4160572978
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.821005444
Short name T208
Test name
Test status
Simulation time 244275201 ps
CPU time 1.42 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:35 PM PDT 24
Peak memory 200516 kb
Host smart-37294f7e-c273-4aa4-ad88-5a3b497d8d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821005444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.821005444
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2500286582
Short name T83
Test name
Test status
Simulation time 3750320547 ps
CPU time 16.04 seconds
Started May 14 12:44:29 PM PDT 24
Finished May 14 12:44:47 PM PDT 24
Peak memory 200688 kb
Host smart-25c88230-48bd-46a5-b57d-607d03a41541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500286582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2500286582
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3342044701
Short name T167
Test name
Test status
Simulation time 315781314 ps
CPU time 1.91 seconds
Started May 14 12:44:32 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200288 kb
Host smart-46ceabe9-1007-44ff-9000-1e4c57e53d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342044701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3342044701
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3031561917
Short name T234
Test name
Test status
Simulation time 136904624 ps
CPU time 1.16 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:34 PM PDT 24
Peak memory 200384 kb
Host smart-b2e6688d-a599-4341-b62d-75186cf988f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031561917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3031561917
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2956066652
Short name T278
Test name
Test status
Simulation time 72694534 ps
CPU time 0.77 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:32 PM PDT 24
Peak memory 200220 kb
Host smart-6c90a9b3-5848-4f69-8501-d858397fb1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956066652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2956066652
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3591466629
Short name T59
Test name
Test status
Simulation time 1228704901 ps
CPU time 5.38 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:39 PM PDT 24
Peak memory 217572 kb
Host smart-a207cd9f-3762-49be-9b1b-ef6fa495a33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591466629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3591466629
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4098444131
Short name T541
Test name
Test status
Simulation time 246189494 ps
CPU time 1.13 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:33 PM PDT 24
Peak memory 217480 kb
Host smart-8b8303a2-8353-4ec3-bdd3-1b2d47330c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098444131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4098444131
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2685637436
Short name T411
Test name
Test status
Simulation time 142154303 ps
CPU time 0.83 seconds
Started May 14 12:44:33 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200152 kb
Host smart-7e40dea2-d953-4a41-8570-97e3b792679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685637436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2685637436
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2995442539
Short name T362
Test name
Test status
Simulation time 1619294964 ps
CPU time 6.3 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:39 PM PDT 24
Peak memory 200540 kb
Host smart-ae651438-bf86-4df5-8b53-bab93b5c300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995442539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2995442539
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2691598224
Short name T156
Test name
Test status
Simulation time 145498159 ps
CPU time 1.07 seconds
Started May 14 12:44:29 PM PDT 24
Finished May 14 12:44:32 PM PDT 24
Peak memory 200340 kb
Host smart-70236809-dfea-45fd-9799-fba693f2b398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691598224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2691598224
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2614634043
Short name T442
Test name
Test status
Simulation time 111987224 ps
CPU time 1.15 seconds
Started May 14 12:44:33 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200516 kb
Host smart-9426fc10-db85-406e-b01d-e9a6ba832c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614634043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2614634043
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.407153801
Short name T285
Test name
Test status
Simulation time 156024614 ps
CPU time 1.74 seconds
Started May 14 12:44:29 PM PDT 24
Finished May 14 12:44:33 PM PDT 24
Peak memory 200392 kb
Host smart-9bea18b1-a270-4809-8792-e22e7e899810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407153801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.407153801
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4076507295
Short name T267
Test name
Test status
Simulation time 79114120 ps
CPU time 0.81 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:32 PM PDT 24
Peak memory 200292 kb
Host smart-f90f983d-ac29-4631-a334-9570955481aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076507295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4076507295
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.931870484
Short name T494
Test name
Test status
Simulation time 56161436 ps
CPU time 0.74 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:34 PM PDT 24
Peak memory 200212 kb
Host smart-353810dc-eb19-41bc-a4e8-7ab218082f56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931870484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.931870484
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3049246241
Short name T37
Test name
Test status
Simulation time 1884581952 ps
CPU time 6.89 seconds
Started May 14 12:44:34 PM PDT 24
Finished May 14 12:44:43 PM PDT 24
Peak memory 218032 kb
Host smart-2a9ed4e0-1046-46d7-b61f-7d8d8811170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049246241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3049246241
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2246109908
Short name T467
Test name
Test status
Simulation time 245193368 ps
CPU time 1.19 seconds
Started May 14 12:44:32 PM PDT 24
Finished May 14 12:44:35 PM PDT 24
Peak memory 217488 kb
Host smart-280b4393-fc0c-4f41-a183-6de411a4b086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246109908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2246109908
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.4247782823
Short name T468
Test name
Test status
Simulation time 193398766 ps
CPU time 0.91 seconds
Started May 14 12:44:35 PM PDT 24
Finished May 14 12:44:37 PM PDT 24
Peak memory 200248 kb
Host smart-33fdab3a-a691-48c1-bf5e-8b88cfd5ecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247782823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.4247782823
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.35592278
Short name T30
Test name
Test status
Simulation time 1991298265 ps
CPU time 8.13 seconds
Started May 14 12:44:29 PM PDT 24
Finished May 14 12:44:39 PM PDT 24
Peak memory 200512 kb
Host smart-677b6794-73a4-4024-8386-924712245612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35592278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.35592278
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.4231691819
Short name T456
Test name
Test status
Simulation time 96699256 ps
CPU time 1.01 seconds
Started May 14 12:44:29 PM PDT 24
Finished May 14 12:44:31 PM PDT 24
Peak memory 200372 kb
Host smart-4f528b4c-c301-481f-bc97-4746ddc04d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231691819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.4231691819
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.4238141892
Short name T328
Test name
Test status
Simulation time 121526153 ps
CPU time 1.16 seconds
Started May 14 12:44:33 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200512 kb
Host smart-aa5b6ca0-12de-474b-a628-48f9b86b6005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238141892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.4238141892
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3992435057
Short name T338
Test name
Test status
Simulation time 7266760947 ps
CPU time 29.3 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:45:01 PM PDT 24
Peak memory 208868 kb
Host smart-3ae8e7dc-83db-49d4-91bc-744a4174ea5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992435057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3992435057
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2788674469
Short name T462
Test name
Test status
Simulation time 300323642 ps
CPU time 2.1 seconds
Started May 14 12:44:32 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200328 kb
Host smart-41ab4a2d-e8f5-4577-8041-dccd420613f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788674469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2788674469
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1241323184
Short name T15
Test name
Test status
Simulation time 89411411 ps
CPU time 0.92 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:33 PM PDT 24
Peak memory 200384 kb
Host smart-b6d59d0e-9baa-4403-a81e-0429e742b9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241323184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1241323184
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2747499876
Short name T137
Test name
Test status
Simulation time 85948891 ps
CPU time 0.86 seconds
Started May 14 12:43:28 PM PDT 24
Finished May 14 12:43:30 PM PDT 24
Peak memory 200164 kb
Host smart-ee51a82a-5103-43e4-abae-29d71e7da681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747499876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2747499876
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2897770734
Short name T521
Test name
Test status
Simulation time 1221083170 ps
CPU time 5.41 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:35 PM PDT 24
Peak memory 222068 kb
Host smart-aaaf3e44-6db5-475c-a6c9-d77b876cf76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897770734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2897770734
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3403312461
Short name T500
Test name
Test status
Simulation time 244488451 ps
CPU time 1.08 seconds
Started May 14 12:43:31 PM PDT 24
Finished May 14 12:43:33 PM PDT 24
Peak memory 217520 kb
Host smart-b8b63d35-2e9e-4ff9-bead-e7d6a5baa825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403312461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3403312461
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.424206864
Short name T263
Test name
Test status
Simulation time 190874104 ps
CPU time 0.93 seconds
Started May 14 12:43:30 PM PDT 24
Finished May 14 12:43:32 PM PDT 24
Peak memory 200140 kb
Host smart-43b5403a-a2ff-4eb2-a983-5396f93baed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424206864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.424206864
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2573659152
Short name T270
Test name
Test status
Simulation time 1528424771 ps
CPU time 6.33 seconds
Started May 14 12:43:27 PM PDT 24
Finished May 14 12:43:35 PM PDT 24
Peak memory 200516 kb
Host smart-2ce06fe1-43bb-4805-9858-cf92fa78c290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573659152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2573659152
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.373215518
Short name T53
Test name
Test status
Simulation time 8285429176 ps
CPU time 15.03 seconds
Started May 14 12:43:27 PM PDT 24
Finished May 14 12:43:44 PM PDT 24
Peak memory 217440 kb
Host smart-5e35e58c-baba-48bd-829b-3b183f9f4aa7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373215518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.373215518
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2309534624
Short name T446
Test name
Test status
Simulation time 112579125 ps
CPU time 1 seconds
Started May 14 12:43:28 PM PDT 24
Finished May 14 12:43:30 PM PDT 24
Peak memory 200328 kb
Host smart-9c146032-3de8-4ee5-9307-c158d9054a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309534624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2309534624
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3031356088
Short name T178
Test name
Test status
Simulation time 129606610 ps
CPU time 1.19 seconds
Started May 14 12:43:28 PM PDT 24
Finished May 14 12:43:31 PM PDT 24
Peak memory 200896 kb
Host smart-407467c3-51d4-44ce-9756-157e32155a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031356088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3031356088
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2838123458
Short name T428
Test name
Test status
Simulation time 8441149242 ps
CPU time 27.51 seconds
Started May 14 12:43:32 PM PDT 24
Finished May 14 12:44:00 PM PDT 24
Peak memory 217092 kb
Host smart-8f310b85-36cc-4fd5-ab8c-6783f0430ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838123458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2838123458
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.288222688
Short name T480
Test name
Test status
Simulation time 373704692 ps
CPU time 2.26 seconds
Started May 14 12:43:28 PM PDT 24
Finished May 14 12:43:31 PM PDT 24
Peak memory 200328 kb
Host smart-873833c2-af69-42eb-ba18-4885b4c2e277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288222688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.288222688
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2751489412
Short name T383
Test name
Test status
Simulation time 103996673 ps
CPU time 0.95 seconds
Started May 14 12:43:31 PM PDT 24
Finished May 14 12:43:32 PM PDT 24
Peak memory 200424 kb
Host smart-9e72debf-34f8-4592-b620-048509c61954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751489412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2751489412
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.967086554
Short name T308
Test name
Test status
Simulation time 58372877 ps
CPU time 0.74 seconds
Started May 14 12:44:32 PM PDT 24
Finished May 14 12:44:35 PM PDT 24
Peak memory 200232 kb
Host smart-2b2e5c4b-5777-4068-820d-e41efd8874aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967086554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.967086554
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3794900096
Short name T38
Test name
Test status
Simulation time 1885677694 ps
CPU time 6.94 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:40 PM PDT 24
Peak memory 218016 kb
Host smart-58e100ff-7375-4aac-929b-36ac2d2a588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794900096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3794900096
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2646602093
Short name T268
Test name
Test status
Simulation time 245274794 ps
CPU time 1.04 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:32 PM PDT 24
Peak memory 217336 kb
Host smart-2ef8a73c-c0e2-48b1-aa8a-951537907cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646602093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2646602093
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3537569530
Short name T21
Test name
Test status
Simulation time 105563726 ps
CPU time 0.74 seconds
Started May 14 12:44:35 PM PDT 24
Finished May 14 12:44:37 PM PDT 24
Peak memory 200248 kb
Host smart-445db21e-8724-4991-a252-1db7c9d4cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537569530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3537569530
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1665109817
Short name T330
Test name
Test status
Simulation time 996960201 ps
CPU time 4.85 seconds
Started May 14 12:44:34 PM PDT 24
Finished May 14 12:44:40 PM PDT 24
Peak memory 200600 kb
Host smart-5ca53b58-c1a6-42d6-850d-8c28b818952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665109817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1665109817
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2899772026
Short name T5
Test name
Test status
Simulation time 107196885 ps
CPU time 1 seconds
Started May 14 12:44:33 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200388 kb
Host smart-dde64259-098c-44f4-98f2-742a392bfae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899772026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2899772026
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1771149170
Short name T187
Test name
Test status
Simulation time 232833283 ps
CPU time 1.44 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:33 PM PDT 24
Peak memory 200560 kb
Host smart-3f657762-ccc9-4784-9ce2-bdd90307e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771149170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1771149170
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.889648154
Short name T31
Test name
Test status
Simulation time 756252898 ps
CPU time 3.3 seconds
Started May 14 12:44:34 PM PDT 24
Finished May 14 12:44:39 PM PDT 24
Peak memory 200536 kb
Host smart-0f6be2f0-a188-4ff3-abea-634f41138d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889648154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.889648154
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.4224189649
Short name T197
Test name
Test status
Simulation time 344788113 ps
CPU time 2.22 seconds
Started May 14 12:44:36 PM PDT 24
Finished May 14 12:44:39 PM PDT 24
Peak memory 200424 kb
Host smart-937e975d-bc79-412a-9d92-3aa745b8422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224189649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4224189649
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3285217151
Short name T384
Test name
Test status
Simulation time 100123117 ps
CPU time 1.01 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:33 PM PDT 24
Peak memory 200444 kb
Host smart-74ad3264-f43d-4996-9f50-a557a688a367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285217151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3285217151
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2322153045
Short name T153
Test name
Test status
Simulation time 68033944 ps
CPU time 0.77 seconds
Started May 14 12:44:32 PM PDT 24
Finished May 14 12:44:35 PM PDT 24
Peak memory 200252 kb
Host smart-6b820382-0f2c-4704-b9e1-ab133a979139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322153045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2322153045
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1053538680
Short name T490
Test name
Test status
Simulation time 1220919535 ps
CPU time 6.02 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:39 PM PDT 24
Peak memory 222124 kb
Host smart-96698668-d60e-4b84-a378-03cb0d731121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053538680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1053538680
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2896537492
Short name T497
Test name
Test status
Simulation time 242982808 ps
CPU time 1.13 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:34 PM PDT 24
Peak memory 217392 kb
Host smart-54365230-84eb-4210-8d34-4410aef58405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896537492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2896537492
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3257975506
Short name T264
Test name
Test status
Simulation time 126115396 ps
CPU time 0.86 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:34 PM PDT 24
Peak memory 200192 kb
Host smart-da0b2a88-b6da-4a0a-bec5-0c9e12eb74f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257975506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3257975506
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1063743079
Short name T359
Test name
Test status
Simulation time 774778665 ps
CPU time 4.29 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200592 kb
Host smart-1f670fb2-7c6d-4fa2-a8e0-d9ee0d92ec84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063743079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1063743079
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3181749008
Short name T448
Test name
Test status
Simulation time 97068745 ps
CPU time 0.97 seconds
Started May 14 12:44:28 PM PDT 24
Finished May 14 12:44:31 PM PDT 24
Peak memory 200432 kb
Host smart-d938a73d-057e-4b38-8868-48f280e9de99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181749008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3181749008
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.971408348
Short name T269
Test name
Test status
Simulation time 203865794 ps
CPU time 1.35 seconds
Started May 14 12:44:32 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200480 kb
Host smart-59fb9f0e-a424-4be0-a512-d06291794881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971408348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.971408348
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.509967107
Short name T119
Test name
Test status
Simulation time 4845279183 ps
CPU time 15.57 seconds
Started May 14 12:44:36 PM PDT 24
Finished May 14 12:44:53 PM PDT 24
Peak memory 200764 kb
Host smart-d9c2baa8-f237-460f-87d1-26dd30d321a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509967107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.509967107
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.4174891598
Short name T306
Test name
Test status
Simulation time 122364368 ps
CPU time 1.51 seconds
Started May 14 12:44:31 PM PDT 24
Finished May 14 12:44:35 PM PDT 24
Peak memory 200380 kb
Host smart-20dc3150-0532-4bcb-af5d-a77d393bceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174891598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.4174891598
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.270566336
Short name T313
Test name
Test status
Simulation time 247234094 ps
CPU time 1.33 seconds
Started May 14 12:44:30 PM PDT 24
Finished May 14 12:44:33 PM PDT 24
Peak memory 200308 kb
Host smart-c558cdb8-8962-45ed-829a-6336097aa86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270566336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.270566336
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3614723035
Short name T535
Test name
Test status
Simulation time 73492487 ps
CPU time 0.8 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:44:41 PM PDT 24
Peak memory 200168 kb
Host smart-f0cfd1a8-1741-40d3-8baf-16f35bd17ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614723035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3614723035
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3510497291
Short name T397
Test name
Test status
Simulation time 1226788901 ps
CPU time 5.53 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:48 PM PDT 24
Peak memory 222136 kb
Host smart-500fc231-4e06-43ac-a36a-f88774011871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510497291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3510497291
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.62810565
Short name T518
Test name
Test status
Simulation time 245037097 ps
CPU time 1.13 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:44 PM PDT 24
Peak memory 217636 kb
Host smart-12e2f94d-5c46-461a-ba2d-2af6953b1aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62810565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.62810565
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3756397935
Short name T512
Test name
Test status
Simulation time 99208010 ps
CPU time 0.76 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 200308 kb
Host smart-fa087deb-ee7e-491a-92a2-45ee32c5fe9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756397935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3756397935
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.673030550
Short name T226
Test name
Test status
Simulation time 911796051 ps
CPU time 4.69 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:48 PM PDT 24
Peak memory 200636 kb
Host smart-300f0d01-b03e-4eb4-8526-3bb1db12fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673030550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.673030550
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2519585173
Short name T445
Test name
Test status
Simulation time 100363257 ps
CPU time 0.97 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:43 PM PDT 24
Peak memory 200400 kb
Host smart-ad475210-ea75-41f2-a501-7220c2ee2f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519585173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2519585173
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3779447860
Short name T13
Test name
Test status
Simulation time 120826127 ps
CPU time 1.21 seconds
Started May 14 12:44:32 PM PDT 24
Finished May 14 12:44:36 PM PDT 24
Peak memory 200580 kb
Host smart-7e40a8cc-f056-46d3-a9d3-ffcd72bc1856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779447860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3779447860
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4189883776
Short name T540
Test name
Test status
Simulation time 5351151873 ps
CPU time 19.28 seconds
Started May 14 12:44:45 PM PDT 24
Finished May 14 12:45:08 PM PDT 24
Peak memory 200732 kb
Host smart-96479be1-19de-4891-830b-4344bc27928c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189883776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4189883776
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2071699353
Short name T56
Test name
Test status
Simulation time 398036677 ps
CPU time 2.32 seconds
Started May 14 12:44:37 PM PDT 24
Finished May 14 12:44:41 PM PDT 24
Peak memory 200320 kb
Host smart-8f36bdb4-6224-4b32-83d1-037c74865167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071699353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2071699353
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3921780736
Short name T365
Test name
Test status
Simulation time 106653112 ps
CPU time 0.97 seconds
Started May 14 12:44:37 PM PDT 24
Finished May 14 12:44:38 PM PDT 24
Peak memory 200396 kb
Host smart-0d43c975-2f00-4a0b-9ccc-8c57698cb92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921780736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3921780736
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.546617532
Short name T42
Test name
Test status
Simulation time 85779815 ps
CPU time 0.83 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:44:41 PM PDT 24
Peak memory 200188 kb
Host smart-f1cd634c-12bc-4e44-a9e0-552c2242a0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546617532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.546617532
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1019270639
Short name T260
Test name
Test status
Simulation time 1232366276 ps
CPU time 5.33 seconds
Started May 14 12:44:37 PM PDT 24
Finished May 14 12:44:44 PM PDT 24
Peak memory 222068 kb
Host smart-9b748df7-5558-4353-a841-b475f737aa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019270639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1019270639
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4848753
Short name T215
Test name
Test status
Simulation time 243496306 ps
CPU time 1.1 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:45 PM PDT 24
Peak memory 217548 kb
Host smart-1f4c47d1-b5bf-4b36-810f-26e428ac1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4848753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4848753
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3326605096
Short name T429
Test name
Test status
Simulation time 143066156 ps
CPU time 0.85 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:44 PM PDT 24
Peak memory 200192 kb
Host smart-a4ae9fb8-3981-46d0-b310-235b0c7c7d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326605096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3326605096
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3777899662
Short name T122
Test name
Test status
Simulation time 1453044720 ps
CPU time 5.41 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:44:44 PM PDT 24
Peak memory 200568 kb
Host smart-2bf406b0-d9af-499f-b952-37ddab6c595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777899662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3777899662
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2023383311
Short name T506
Test name
Test status
Simulation time 156826039 ps
CPU time 1.16 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:44:41 PM PDT 24
Peak memory 200428 kb
Host smart-f7f3546b-d154-43aa-906c-e67977a67692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023383311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2023383311
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1113641615
Short name T196
Test name
Test status
Simulation time 109275513 ps
CPU time 1.2 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:43 PM PDT 24
Peak memory 200552 kb
Host smart-d7697041-228d-427f-a5ea-d25e9a390b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113641615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1113641615
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1920653849
Short name T207
Test name
Test status
Simulation time 925202786 ps
CPU time 4.37 seconds
Started May 14 12:44:41 PM PDT 24
Finished May 14 12:44:49 PM PDT 24
Peak memory 200668 kb
Host smart-6121cee9-0c42-43c3-9aa2-c802b940de74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920653849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1920653849
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.293668353
Short name T203
Test name
Test status
Simulation time 329946412 ps
CPU time 1.89 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:45 PM PDT 24
Peak memory 200352 kb
Host smart-5c4d9555-9591-496d-9290-4ea765c3e6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293668353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.293668353
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.613039066
Short name T336
Test name
Test status
Simulation time 152575514 ps
CPU time 1.05 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:44:42 PM PDT 24
Peak memory 200292 kb
Host smart-cf6375df-daf4-4e8b-99e6-c58afd7959b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613039066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.613039066
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.793165069
Short name T488
Test name
Test status
Simulation time 70149510 ps
CPU time 0.87 seconds
Started May 14 12:44:41 PM PDT 24
Finished May 14 12:44:50 PM PDT 24
Peak memory 200520 kb
Host smart-e7ce2f4e-74f8-42fb-b772-4a55f3dd51be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793165069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.793165069
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3780992494
Short name T358
Test name
Test status
Simulation time 2362762773 ps
CPU time 8.55 seconds
Started May 14 12:44:41 PM PDT 24
Finished May 14 12:44:53 PM PDT 24
Peak memory 218280 kb
Host smart-f75a99b9-15a6-48af-86dd-2624d132447b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780992494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3780992494
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3133864708
Short name T357
Test name
Test status
Simulation time 244565656 ps
CPU time 1.05 seconds
Started May 14 12:44:41 PM PDT 24
Finished May 14 12:44:45 PM PDT 24
Peak memory 217740 kb
Host smart-56b7e5de-556d-47d5-bd68-e506cafab181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133864708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3133864708
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2935540295
Short name T530
Test name
Test status
Simulation time 138780082 ps
CPU time 0.81 seconds
Started May 14 12:44:45 PM PDT 24
Finished May 14 12:44:49 PM PDT 24
Peak memory 199888 kb
Host smart-762066eb-39c9-4b6e-9100-9dadd809b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935540295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2935540295
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3814495297
Short name T232
Test name
Test status
Simulation time 906250272 ps
CPU time 4.52 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:48 PM PDT 24
Peak memory 200584 kb
Host smart-689b69d4-8e3f-4988-8d36-7484dfef98be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814495297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3814495297
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2293280797
Short name T201
Test name
Test status
Simulation time 112695428 ps
CPU time 1.06 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:44:40 PM PDT 24
Peak memory 200480 kb
Host smart-ac0f82bc-260c-4def-b416-83ac8d389929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293280797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2293280797
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1618734656
Short name T180
Test name
Test status
Simulation time 256286600 ps
CPU time 1.54 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:47 PM PDT 24
Peak memory 200520 kb
Host smart-abd3b51f-4e7b-4da2-b0ac-26a629e97935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618734656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1618734656
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3484903744
Short name T444
Test name
Test status
Simulation time 9153392263 ps
CPU time 31.15 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:45:13 PM PDT 24
Peak memory 208948 kb
Host smart-bfcbd9ae-01c1-4c6e-b195-66ed285538c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484903744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3484903744
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2912061042
Short name T491
Test name
Test status
Simulation time 440490311 ps
CPU time 2.34 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:45 PM PDT 24
Peak memory 208572 kb
Host smart-e4a6a68a-de54-44d0-8ffd-c3df28a56d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912061042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2912061042
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.493049466
Short name T248
Test name
Test status
Simulation time 138314723 ps
CPU time 1.11 seconds
Started May 14 12:44:43 PM PDT 24
Finished May 14 12:44:47 PM PDT 24
Peak memory 200396 kb
Host smart-b5b848eb-b4c5-474b-a50d-9b12be17788d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493049466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.493049466
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3163498141
Short name T303
Test name
Test status
Simulation time 70859642 ps
CPU time 0.74 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 200272 kb
Host smart-afdfd0f5-bbb9-4256-af94-243a860edf50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163498141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3163498141
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1305993641
Short name T458
Test name
Test status
Simulation time 1896661938 ps
CPU time 7.78 seconds
Started May 14 12:44:36 PM PDT 24
Finished May 14 12:44:45 PM PDT 24
Peak memory 217404 kb
Host smart-e0805ecf-9087-4d03-849f-1b3a81b0cb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305993641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1305993641
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1967728535
Short name T8
Test name
Test status
Simulation time 245240040 ps
CPU time 1.14 seconds
Started May 14 12:44:41 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 217520 kb
Host smart-1bf7e6eb-6829-4f78-8ef7-b8af73062347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967728535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1967728535
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2962053461
Short name T290
Test name
Test status
Simulation time 92107808 ps
CPU time 0.74 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:44:41 PM PDT 24
Peak memory 200244 kb
Host smart-2d38010c-153a-430f-bab5-02d41aeb2d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962053461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2962053461
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.387083562
Short name T26
Test name
Test status
Simulation time 1117872951 ps
CPU time 5.79 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 200564 kb
Host smart-a505dd63-ad03-4c82-ba0c-483fff0b323f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387083562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.387083562
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.4053375944
Short name T195
Test name
Test status
Simulation time 176330051 ps
CPU time 1.15 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 200416 kb
Host smart-06ac7738-6bd0-4963-bf6e-9dcf48a60d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053375944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.4053375944
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2339884083
Short name T170
Test name
Test status
Simulation time 115985582 ps
CPU time 1.21 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 200524 kb
Host smart-b3a7e810-050e-4702-9641-42cb92ef0424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339884083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2339884083
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3467337756
Short name T333
Test name
Test status
Simulation time 10979491264 ps
CPU time 35.62 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:45:16 PM PDT 24
Peak memory 200724 kb
Host smart-fc211cc4-1249-4654-823a-07fa9a5cf411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467337756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3467337756
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2169093891
Short name T194
Test name
Test status
Simulation time 410899239 ps
CPU time 2.38 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:45 PM PDT 24
Peak memory 208584 kb
Host smart-369b5716-2ec3-4ea5-adf7-f2182deb7544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169093891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2169093891
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3543267800
Short name T454
Test name
Test status
Simulation time 175824410 ps
CPU time 1.16 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:43 PM PDT 24
Peak memory 200384 kb
Host smart-9af892a4-c847-4d07-8037-2f0de4fe6823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543267800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3543267800
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.389365364
Short name T516
Test name
Test status
Simulation time 67791072 ps
CPU time 0.77 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:44 PM PDT 24
Peak memory 200152 kb
Host smart-4eeb63f0-d074-4ef8-87f8-715bcfd2825e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389365364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.389365364
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.366198302
Short name T249
Test name
Test status
Simulation time 1887291069 ps
CPU time 7.25 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:52 PM PDT 24
Peak memory 218040 kb
Host smart-5011e2b7-d78a-49c5-a528-071ff47af715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366198302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.366198302
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.4008650020
Short name T282
Test name
Test status
Simulation time 244195295 ps
CPU time 1.2 seconds
Started May 14 12:44:36 PM PDT 24
Finished May 14 12:44:38 PM PDT 24
Peak memory 217576 kb
Host smart-94b47354-cfe4-46c7-b00b-8dbc39c69ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008650020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.4008650020
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3548977610
Short name T514
Test name
Test status
Simulation time 111606192 ps
CPU time 0.76 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:43 PM PDT 24
Peak memory 200188 kb
Host smart-54174fe9-167c-4a7b-81b9-df3c3d35b2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548977610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3548977610
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.481707612
Short name T405
Test name
Test status
Simulation time 1446374836 ps
CPU time 5.6 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:47 PM PDT 24
Peak memory 200504 kb
Host smart-601044b7-9629-4c5a-9a71-3f26d1430a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481707612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.481707612
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3159602831
Short name T245
Test name
Test status
Simulation time 183781524 ps
CPU time 1.32 seconds
Started May 14 12:44:47 PM PDT 24
Finished May 14 12:44:52 PM PDT 24
Peak memory 200404 kb
Host smart-6d75157b-8d93-438a-b8da-8b0255d78813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159602831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3159602831
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.622814636
Short name T190
Test name
Test status
Simulation time 196116837 ps
CPU time 1.45 seconds
Started May 14 12:44:45 PM PDT 24
Finished May 14 12:44:49 PM PDT 24
Peak memory 200632 kb
Host smart-01680d26-4bbf-4d24-977f-c2adffaf1f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622814636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.622814636
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2717121150
Short name T534
Test name
Test status
Simulation time 4913660295 ps
CPU time 23.96 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:45:04 PM PDT 24
Peak memory 210680 kb
Host smart-6e389845-8004-4f0e-ab20-0b2f4473580f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717121150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2717121150
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.931295677
Short name T381
Test name
Test status
Simulation time 141747616 ps
CPU time 1.72 seconds
Started May 14 12:44:37 PM PDT 24
Finished May 14 12:44:39 PM PDT 24
Peak memory 200444 kb
Host smart-8623fe0f-be02-4744-b10e-2771f020d0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931295677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.931295677
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2414452147
Short name T132
Test name
Test status
Simulation time 134457698 ps
CPU time 1.22 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:44 PM PDT 24
Peak memory 200384 kb
Host smart-4944ee2d-4861-457f-8390-45dcce86908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414452147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2414452147
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3336872748
Short name T241
Test name
Test status
Simulation time 82165204 ps
CPU time 0.79 seconds
Started May 14 12:44:38 PM PDT 24
Finished May 14 12:44:40 PM PDT 24
Peak memory 200268 kb
Host smart-6d6d1616-569d-4417-b1a9-c2a6e02cd650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336872748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3336872748
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.476231356
Short name T279
Test name
Test status
Simulation time 1215409388 ps
CPU time 6.05 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:48 PM PDT 24
Peak memory 217112 kb
Host smart-79215748-0b64-49ec-b55c-484dd1d284dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476231356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.476231356
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1814506104
Short name T327
Test name
Test status
Simulation time 243748806 ps
CPU time 1.04 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:45 PM PDT 24
Peak memory 217500 kb
Host smart-869fae4d-f7d6-49a2-9670-cc168e287364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814506104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1814506104
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2518000453
Short name T159
Test name
Test status
Simulation time 223704997 ps
CPU time 0.89 seconds
Started May 14 12:44:37 PM PDT 24
Finished May 14 12:44:39 PM PDT 24
Peak memory 200148 kb
Host smart-5ca88c81-08b4-4a79-85e0-99cdc6e95bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518000453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2518000453
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.421241225
Short name T471
Test name
Test status
Simulation time 809336393 ps
CPU time 4.48 seconds
Started May 14 12:44:45 PM PDT 24
Finished May 14 12:44:52 PM PDT 24
Peak memory 200156 kb
Host smart-d793fc67-7fcc-45bb-ae38-ffa55b5826cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421241225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.421241225
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1750119561
Short name T517
Test name
Test status
Simulation time 143983591 ps
CPU time 1.07 seconds
Started May 14 12:44:43 PM PDT 24
Finished May 14 12:44:47 PM PDT 24
Peak memory 200432 kb
Host smart-df3a4d21-d1f3-4722-9984-38d29c10cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750119561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1750119561
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4136666886
Short name T79
Test name
Test status
Simulation time 125582941 ps
CPU time 1.16 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 200568 kb
Host smart-4ac79141-ca44-444a-9feb-47d00c29906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136666886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4136666886
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3886841042
Short name T77
Test name
Test status
Simulation time 1087174442 ps
CPU time 5.32 seconds
Started May 14 12:44:48 PM PDT 24
Finished May 14 12:44:57 PM PDT 24
Peak memory 200616 kb
Host smart-28feed64-1d54-4226-88e4-db9dcb5c14cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886841042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3886841042
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2007858296
Short name T476
Test name
Test status
Simulation time 436159633 ps
CPU time 2.61 seconds
Started May 14 12:44:45 PM PDT 24
Finished May 14 12:44:50 PM PDT 24
Peak memory 200708 kb
Host smart-879969bb-e982-4e6f-b98c-8450be4d0a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007858296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2007858296
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.999161189
Short name T238
Test name
Test status
Simulation time 70949421 ps
CPU time 0.78 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:44 PM PDT 24
Peak memory 200332 kb
Host smart-c81dc9ca-48f9-4ab3-8126-41c8f469445d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999161189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.999161189
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4085854605
Short name T368
Test name
Test status
Simulation time 65782791 ps
CPU time 0.8 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 200284 kb
Host smart-748d06ce-d75b-4ace-a1cb-b4b92bc1021b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085854605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4085854605
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3893317695
Short name T48
Test name
Test status
Simulation time 1885042796 ps
CPU time 7.37 seconds
Started May 14 12:44:45 PM PDT 24
Finished May 14 12:44:55 PM PDT 24
Peak memory 220896 kb
Host smart-e8c88df0-7d33-46cd-8053-ed626391bd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893317695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3893317695
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2794525127
Short name T432
Test name
Test status
Simulation time 243866500 ps
CPU time 1.08 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 217600 kb
Host smart-6dbfc9ed-9f0a-41bd-bd3b-7bc1ba1b5d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794525127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2794525127
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1031348953
Short name T314
Test name
Test status
Simulation time 114901471 ps
CPU time 0.78 seconds
Started May 14 12:44:39 PM PDT 24
Finished May 14 12:44:44 PM PDT 24
Peak memory 200108 kb
Host smart-a151a09d-936e-4633-9c7d-a4a2b024cc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031348953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1031348953
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.961777929
Short name T542
Test name
Test status
Simulation time 1932914519 ps
CPU time 7.01 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:50 PM PDT 24
Peak memory 200596 kb
Host smart-09e7c6c2-e4dd-44c1-8cee-f0206e08329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961777929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.961777929
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2734676939
Short name T364
Test name
Test status
Simulation time 174120618 ps
CPU time 1.26 seconds
Started May 14 12:44:45 PM PDT 24
Finished May 14 12:44:49 PM PDT 24
Peak memory 199588 kb
Host smart-b763e16a-bb27-4cf7-aa1c-17d05dbd203d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734676939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2734676939
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2139910297
Short name T128
Test name
Test status
Simulation time 226402816 ps
CPU time 1.53 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 200480 kb
Host smart-dadeaa41-febc-4ff6-ae76-52c5a48fd225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139910297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2139910297
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1180634596
Short name T503
Test name
Test status
Simulation time 1684119658 ps
CPU time 6.09 seconds
Started May 14 12:44:43 PM PDT 24
Finished May 14 12:44:52 PM PDT 24
Peak memory 200564 kb
Host smart-f6f33451-62d0-4db5-b80d-bb93f56b11a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180634596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1180634596
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1173638963
Short name T472
Test name
Test status
Simulation time 115289743 ps
CPU time 1.55 seconds
Started May 14 12:44:43 PM PDT 24
Finished May 14 12:44:47 PM PDT 24
Peak memory 200336 kb
Host smart-8cb3c7b9-6cdc-4df0-afa1-19ad3c4d7f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173638963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1173638963
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1048632932
Short name T258
Test name
Test status
Simulation time 90488072 ps
CPU time 0.86 seconds
Started May 14 12:44:42 PM PDT 24
Finished May 14 12:44:46 PM PDT 24
Peak memory 200444 kb
Host smart-db8f4b85-cfba-4d92-8124-7eb4a417d8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048632932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1048632932
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4045768317
Short name T489
Test name
Test status
Simulation time 94447026 ps
CPU time 0.9 seconds
Started May 14 12:44:46 PM PDT 24
Finished May 14 12:44:51 PM PDT 24
Peak memory 200304 kb
Host smart-f79366d1-5705-426c-b017-2c2dd43215ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045768317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4045768317
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2868058406
Short name T457
Test name
Test status
Simulation time 1894093316 ps
CPU time 6.81 seconds
Started May 14 12:44:47 PM PDT 24
Finished May 14 12:44:57 PM PDT 24
Peak memory 222036 kb
Host smart-b54925d9-bb0c-4ec9-8d70-79ef0084a2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868058406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2868058406
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2413870319
Short name T302
Test name
Test status
Simulation time 246025851 ps
CPU time 1.05 seconds
Started May 14 12:44:47 PM PDT 24
Finished May 14 12:44:52 PM PDT 24
Peak memory 217632 kb
Host smart-7a9f9df1-f680-4834-898f-c7adc53a41a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413870319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2413870319
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2640904723
Short name T406
Test name
Test status
Simulation time 103332159 ps
CPU time 0.81 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:45 PM PDT 24
Peak memory 200212 kb
Host smart-feaa4eec-268e-4ecb-926c-90f75ee42896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640904723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2640904723
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.4139682320
Short name T218
Test name
Test status
Simulation time 1537700699 ps
CPU time 6.28 seconds
Started May 14 12:44:44 PM PDT 24
Finished May 14 12:44:53 PM PDT 24
Peak memory 200584 kb
Host smart-91dd148a-bae2-4295-b060-716f833ebb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139682320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.4139682320
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1262314229
Short name T3
Test name
Test status
Simulation time 98828185 ps
CPU time 0.97 seconds
Started May 14 12:44:47 PM PDT 24
Finished May 14 12:44:52 PM PDT 24
Peak memory 200296 kb
Host smart-4c3274d8-cafb-4b56-8b62-d1339d6190e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262314229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1262314229
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2045961055
Short name T233
Test name
Test status
Simulation time 256903032 ps
CPU time 1.54 seconds
Started May 14 12:44:40 PM PDT 24
Finished May 14 12:44:45 PM PDT 24
Peak memory 200632 kb
Host smart-52dc4bc8-a7ec-4270-addc-4967ccdd292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045961055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2045961055
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.266364717
Short name T323
Test name
Test status
Simulation time 10469117011 ps
CPU time 36.72 seconds
Started May 14 12:44:48 PM PDT 24
Finished May 14 12:45:28 PM PDT 24
Peak memory 208904 kb
Host smart-ef55986e-c0e7-49a7-a74c-4670841c652c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266364717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.266364717
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.592573796
Short name T486
Test name
Test status
Simulation time 142149802 ps
CPU time 1.85 seconds
Started May 14 12:44:46 PM PDT 24
Finished May 14 12:44:50 PM PDT 24
Peak memory 200464 kb
Host smart-39b7c6ba-33c0-479c-9960-51fb392dddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592573796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.592573796
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2424391033
Short name T255
Test name
Test status
Simulation time 61871042 ps
CPU time 0.75 seconds
Started May 14 12:44:46 PM PDT 24
Finished May 14 12:44:50 PM PDT 24
Peak memory 200448 kb
Host smart-4753fbcd-07b2-4d47-b141-50346da9f054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424391033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2424391033
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2492000752
Short name T479
Test name
Test status
Simulation time 76528158 ps
CPU time 0.78 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:31 PM PDT 24
Peak memory 200172 kb
Host smart-4aadb0fc-05e6-4d75-b1a4-f83ddd97836e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492000752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2492000752
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1598963114
Short name T44
Test name
Test status
Simulation time 1221074559 ps
CPU time 5.2 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:35 PM PDT 24
Peak memory 218044 kb
Host smart-24532046-9b75-4e52-9e70-136d05b08aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598963114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1598963114
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3962877012
Short name T295
Test name
Test status
Simulation time 243742152 ps
CPU time 1.13 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:31 PM PDT 24
Peak memory 217388 kb
Host smart-0fcbb0f5-46fd-4cb7-b6ce-7c3c413a9fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962877012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3962877012
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1460224427
Short name T19
Test name
Test status
Simulation time 119204172 ps
CPU time 0.8 seconds
Started May 14 12:43:27 PM PDT 24
Finished May 14 12:43:29 PM PDT 24
Peak memory 200108 kb
Host smart-8a30d9c4-ae0c-4d6e-82d2-37e1a3ebeea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460224427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1460224427
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3364069302
Short name T455
Test name
Test status
Simulation time 1276921307 ps
CPU time 5.11 seconds
Started May 14 12:43:27 PM PDT 24
Finished May 14 12:43:33 PM PDT 24
Peak memory 200556 kb
Host smart-04467690-068d-48f5-8c80-04c896bbbe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364069302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3364069302
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3471156944
Short name T361
Test name
Test status
Simulation time 174328411 ps
CPU time 1.27 seconds
Started May 14 12:43:27 PM PDT 24
Finished May 14 12:43:30 PM PDT 24
Peak memory 200452 kb
Host smart-c5b679a5-51bc-42a0-8a88-435a19e8cc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471156944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3471156944
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1628979974
Short name T76
Test name
Test status
Simulation time 114021992 ps
CPU time 1.18 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:31 PM PDT 24
Peak memory 200604 kb
Host smart-67feb468-7000-4ec7-8a9f-c709ccf06535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628979974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1628979974
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.758871603
Short name T527
Test name
Test status
Simulation time 15517532970 ps
CPU time 50.61 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:44:21 PM PDT 24
Peak memory 200648 kb
Host smart-9e3e8860-1caf-41a0-9248-c3988352e22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758871603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.758871603
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1864964714
Short name T126
Test name
Test status
Simulation time 402452828 ps
CPU time 2.47 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:33 PM PDT 24
Peak memory 200324 kb
Host smart-d19e0910-49af-4f15-b26b-736ab9b200e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864964714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1864964714
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2855607392
Short name T151
Test name
Test status
Simulation time 79487238 ps
CPU time 0.79 seconds
Started May 14 12:43:28 PM PDT 24
Finished May 14 12:43:30 PM PDT 24
Peak memory 200360 kb
Host smart-14dd7263-219e-4a58-acca-82414b539c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855607392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2855607392
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2827580430
Short name T210
Test name
Test status
Simulation time 52950793 ps
CPU time 0.69 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 200144 kb
Host smart-a1a475de-dc9b-4655-a018-91d8a56a7922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827580430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2827580430
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3130589797
Short name T45
Test name
Test status
Simulation time 1225132825 ps
CPU time 5.29 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:48 PM PDT 24
Peak memory 217968 kb
Host smart-7b502b57-ae79-4cf8-9d7f-5118550978e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130589797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3130589797
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1538501256
Short name T460
Test name
Test status
Simulation time 243697997 ps
CPU time 1.16 seconds
Started May 14 12:43:38 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 217568 kb
Host smart-349506d4-14bd-4d8c-91e3-fa3fad840bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538501256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1538501256
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2872973690
Short name T470
Test name
Test status
Simulation time 120823506 ps
CPU time 0.89 seconds
Started May 14 12:43:37 PM PDT 24
Finished May 14 12:43:39 PM PDT 24
Peak memory 200116 kb
Host smart-e06c3f40-aeb9-4835-b793-990dd1ea7028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872973690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2872973690
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.183734360
Short name T274
Test name
Test status
Simulation time 739195189 ps
CPU time 3.54 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:47 PM PDT 24
Peak memory 200540 kb
Host smart-53a21740-4aff-4b7a-ae24-86cc9cf965b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183734360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.183734360
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2662351248
Short name T492
Test name
Test status
Simulation time 96445278 ps
CPU time 0.96 seconds
Started May 14 12:43:36 PM PDT 24
Finished May 14 12:43:38 PM PDT 24
Peak memory 200368 kb
Host smart-46571fe7-3663-408d-b673-f6134f77da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662351248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2662351248
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4157338060
Short name T417
Test name
Test status
Simulation time 115196104 ps
CPU time 1.17 seconds
Started May 14 12:43:29 PM PDT 24
Finished May 14 12:43:32 PM PDT 24
Peak memory 200472 kb
Host smart-630dc3ac-6cc5-4798-8ac8-911d473d016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157338060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4157338060
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.4255395848
Short name T427
Test name
Test status
Simulation time 6758635875 ps
CPU time 28.91 seconds
Started May 14 12:43:36 PM PDT 24
Finished May 14 12:44:06 PM PDT 24
Peak memory 200784 kb
Host smart-a01d5435-2ed5-4bf6-aa21-f82376dda332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255395848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.4255395848
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.169742405
Short name T206
Test name
Test status
Simulation time 481151645 ps
CPU time 2.56 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:45 PM PDT 24
Peak memory 200324 kb
Host smart-49b87f96-5a97-4a16-9864-212844affafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169742405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.169742405
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.770213557
Short name T124
Test name
Test status
Simulation time 284738830 ps
CPU time 1.45 seconds
Started May 14 12:43:37 PM PDT 24
Finished May 14 12:43:41 PM PDT 24
Peak memory 200712 kb
Host smart-f627f83c-5a6e-4842-922c-2d5b7745f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770213557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.770213557
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2022571189
Short name T433
Test name
Test status
Simulation time 69039242 ps
CPU time 0.83 seconds
Started May 14 12:43:37 PM PDT 24
Finished May 14 12:43:39 PM PDT 24
Peak memory 200216 kb
Host smart-d98517ab-bd9f-4bf6-b204-8aef5a859acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022571189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2022571189
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3224951281
Short name T129
Test name
Test status
Simulation time 1223746840 ps
CPU time 5.33 seconds
Started May 14 12:43:35 PM PDT 24
Finished May 14 12:43:41 PM PDT 24
Peak memory 217968 kb
Host smart-7398396a-3b78-4635-bfcb-6cd17b3c9e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224951281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3224951281
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2408340502
Short name T261
Test name
Test status
Simulation time 245244770 ps
CPU time 1.03 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:44 PM PDT 24
Peak memory 217508 kb
Host smart-343236f0-93e6-4036-b941-5ad30cb62890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408340502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2408340502
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2145466424
Short name T351
Test name
Test status
Simulation time 221363269 ps
CPU time 0.9 seconds
Started May 14 12:43:38 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 200108 kb
Host smart-a343080a-72bc-4847-a80f-92f4adce0f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145466424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2145466424
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3486874211
Short name T389
Test name
Test status
Simulation time 1542992059 ps
CPU time 5.75 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:49 PM PDT 24
Peak memory 200544 kb
Host smart-5279dfcf-2b3e-45a9-81b5-2fdaca250d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486874211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3486874211
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3405154816
Short name T360
Test name
Test status
Simulation time 170244628 ps
CPU time 1.17 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 200344 kb
Host smart-78c78d0b-c093-4457-a3ee-bfef83a217d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405154816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3405154816
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.589802782
Short name T474
Test name
Test status
Simulation time 253539751 ps
CPU time 1.58 seconds
Started May 14 12:43:38 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 200588 kb
Host smart-48a93e68-4ed6-416c-8638-b6f248e42d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589802782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.589802782
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3118384246
Short name T386
Test name
Test status
Simulation time 1949923731 ps
CPU time 8.26 seconds
Started May 14 12:43:38 PM PDT 24
Finished May 14 12:43:48 PM PDT 24
Peak memory 208740 kb
Host smart-f12b064f-a4d9-4566-a5da-e6832422dc83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118384246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3118384246
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.658570535
Short name T342
Test name
Test status
Simulation time 114067072 ps
CPU time 1.43 seconds
Started May 14 12:43:41 PM PDT 24
Finished May 14 12:43:45 PM PDT 24
Peak memory 200352 kb
Host smart-fabc6d13-8bc6-40fa-ade6-52cd3669f35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658570535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.658570535
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3434560942
Short name T7
Test name
Test status
Simulation time 113109010 ps
CPU time 0.99 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 200324 kb
Host smart-ede634e5-f186-4484-8131-b3d151a94380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434560942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3434560942
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2833822689
Short name T387
Test name
Test status
Simulation time 63605622 ps
CPU time 0.76 seconds
Started May 14 12:43:36 PM PDT 24
Finished May 14 12:43:38 PM PDT 24
Peak memory 200132 kb
Host smart-6a1d6055-f6d1-4e8a-992d-d7f7ad14405d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833822689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2833822689
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1631212229
Short name T39
Test name
Test status
Simulation time 1211832756 ps
CPU time 5.76 seconds
Started May 14 12:43:36 PM PDT 24
Finished May 14 12:43:43 PM PDT 24
Peak memory 217940 kb
Host smart-4f0e592f-9212-4ac1-8971-7b7553ea9a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631212229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1631212229
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2316890649
Short name T437
Test name
Test status
Simulation time 244231568 ps
CPU time 1.01 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 217388 kb
Host smart-ea584d49-609e-4944-bff6-4b6183dcf6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316890649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2316890649
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3325196315
Short name T163
Test name
Test status
Simulation time 224700731 ps
CPU time 0.95 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:44 PM PDT 24
Peak memory 200236 kb
Host smart-1dc763b4-ab83-40bb-87a7-872a7cd59c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325196315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3325196315
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.366246639
Short name T337
Test name
Test status
Simulation time 796155229 ps
CPU time 3.98 seconds
Started May 14 12:43:38 PM PDT 24
Finished May 14 12:43:44 PM PDT 24
Peak memory 200504 kb
Host smart-e4973b75-0d4f-4c35-a6d0-74654a562b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366246639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.366246639
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1325344008
Short name T135
Test name
Test status
Simulation time 92206359 ps
CPU time 1.01 seconds
Started May 14 12:43:37 PM PDT 24
Finished May 14 12:43:39 PM PDT 24
Peak memory 200420 kb
Host smart-bbc7080c-87d7-4cd6-bd1b-b74bfc51bee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325344008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1325344008
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.4180169850
Short name T252
Test name
Test status
Simulation time 115450204 ps
CPU time 1.13 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:43 PM PDT 24
Peak memory 200600 kb
Host smart-1c49c988-015c-419d-8664-d2c0376b32d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180169850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4180169850
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2642960643
Short name T482
Test name
Test status
Simulation time 11196497762 ps
CPU time 37.32 seconds
Started May 14 12:43:38 PM PDT 24
Finished May 14 12:44:18 PM PDT 24
Peak memory 208912 kb
Host smart-e9689345-81ac-484c-a93a-27e52ffb405c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642960643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2642960643
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3554117169
Short name T481
Test name
Test status
Simulation time 472525222 ps
CPU time 2.34 seconds
Started May 14 12:43:36 PM PDT 24
Finished May 14 12:43:40 PM PDT 24
Peak memory 200340 kb
Host smart-429d0995-60d0-4e49-85e7-d87d1bf5074a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554117169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3554117169
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1361533869
Short name T221
Test name
Test status
Simulation time 136611071 ps
CPU time 1.13 seconds
Started May 14 12:43:41 PM PDT 24
Finished May 14 12:43:45 PM PDT 24
Peak memory 200336 kb
Host smart-56114d96-5425-44f1-810e-7e4de600a765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361533869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1361533869
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2749900699
Short name T74
Test name
Test status
Simulation time 72369564 ps
CPU time 0.74 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:43 PM PDT 24
Peak memory 200252 kb
Host smart-dc9d8583-a8f6-4937-9112-ed17f311238c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749900699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2749900699
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1719374026
Short name T528
Test name
Test status
Simulation time 2355808201 ps
CPU time 8.4 seconds
Started May 14 12:43:41 PM PDT 24
Finished May 14 12:43:52 PM PDT 24
Peak memory 218112 kb
Host smart-f2b25146-98d6-4e10-9c07-521e4d283d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719374026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1719374026
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3012918073
Short name T532
Test name
Test status
Simulation time 244909032 ps
CPU time 1.06 seconds
Started May 14 12:43:37 PM PDT 24
Finished May 14 12:43:39 PM PDT 24
Peak memory 217336 kb
Host smart-cdbfe158-b701-4faf-a17f-44ab20061f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012918073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3012918073
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2946300086
Short name T289
Test name
Test status
Simulation time 120241605 ps
CPU time 0.77 seconds
Started May 14 12:43:37 PM PDT 24
Finished May 14 12:43:40 PM PDT 24
Peak memory 200140 kb
Host smart-11e0c774-8df4-4210-864b-14e0c0727461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946300086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2946300086
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3634391856
Short name T179
Test name
Test status
Simulation time 1618872449 ps
CPU time 6.25 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:47 PM PDT 24
Peak memory 200612 kb
Host smart-66189e8c-d61a-494e-bc46-0f330b14f7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634391856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3634391856
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4018569119
Short name T331
Test name
Test status
Simulation time 141326433 ps
CPU time 1.12 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:43:44 PM PDT 24
Peak memory 200336 kb
Host smart-ec3b8687-5977-4502-a72f-1c990c350b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018569119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.4018569119
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2241022032
Short name T49
Test name
Test status
Simulation time 122410289 ps
CPU time 1.15 seconds
Started May 14 12:43:39 PM PDT 24
Finished May 14 12:43:42 PM PDT 24
Peak memory 200508 kb
Host smart-c5533ed2-60ef-4ca2-87e5-2f10a1bee8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241022032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2241022032
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1622033865
Short name T99
Test name
Test status
Simulation time 10842247443 ps
CPU time 40.97 seconds
Started May 14 12:43:40 PM PDT 24
Finished May 14 12:44:24 PM PDT 24
Peak memory 200796 kb
Host smart-de520462-a7de-4d79-8618-601b8e2e93ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622033865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1622033865
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4198832020
Short name T378
Test name
Test status
Simulation time 245209293 ps
CPU time 1.77 seconds
Started May 14 12:43:35 PM PDT 24
Finished May 14 12:43:38 PM PDT 24
Peak memory 200336 kb
Host smart-5f7861fd-fe81-4c4a-a59c-cd6454e63025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198832020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4198832020
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.718358892
Short name T204
Test name
Test status
Simulation time 102622213 ps
CPU time 0.87 seconds
Started May 14 12:43:42 PM PDT 24
Finished May 14 12:43:45 PM PDT 24
Peak memory 200352 kb
Host smart-8561943c-c172-4990-8ec6-84fc812e3085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718358892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.718358892
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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