Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8826

1

T1

16

T11

4

T14

34

auto[1]

11635

1

T1

85

T5

4

T11

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6239	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6878	1			T1	27		T2	1		T3	1
reset_info_cp[2]	3130	1			T1	14		T5	1		T14	9
reset_info_cp[4]	4254	1			T1	21		T5	1		T14	20
reset_info_cp[8]	124	1			T15	2		T16	1		T17	1
reset_info_cp[16]	109	1			T15	1		T16	1		T26	2
reset_info_cp[32]	113	1			T1	2		T15	1		T26	1
reset_info_cp[64]	114	1			T1	1		T14	2		T17	1
reset_info_cp[128]	120	1			T11	1		T14	1		T15	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3350	1			T1	16		T14	12		T15	34
reset_info_cp[1]	auto[1]	2908	1			T1	10		T5	1		T14	5
reset_info_cp[2]	auto[0]	1006	1			T14	2		T15	7		T17	3
reset_info_cp[2]	auto[1]	2124	1			T1	14		T5	1		T14	7
reset_info_cp[4]	auto[0]	1564	1			T14	10		T15	22		T17	6
reset_info_cp[4]	auto[1]	2690	1			T1	21		T5	1		T14	10
reset_info_cp[8]	auto[0]	57	1			T15	2		T16	1		T86	1
reset_info_cp[8]	auto[1]	67	1			T17	1		T26	2		T95	2
reset_info_cp[16]	auto[0]	38	1			T16	1		T95	1		T96	1
reset_info_cp[16]	auto[1]	71	1			T15	1		T26	2		T49	2
reset_info_cp[32]	auto[0]	39	1			T28	1		T93	1		T95	1
reset_info_cp[32]	auto[1]	74	1			T1	2		T15	1		T26	1
reset_info_cp[64]	auto[0]	43	1			T17	1		T26	2		T86	1
reset_info_cp[64]	auto[1]	71	1			T1	1		T14	2		T93	1
reset_info_cp[128]	auto[0]	44	1			T11	1		T15	1		T16	1
reset_info_cp[128]	auto[1]	76	1			T14	1		T26	2		T95	1