Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T535 /workspace/coverage/default/13.rstmgr_stress_all.1864301190 May 16 12:24:04 PM PDT 24 May 16 12:24:17 PM PDT 24 1126738477 ps
T536 /workspace/coverage/default/4.rstmgr_reset.822549369 May 16 12:18:40 PM PDT 24 May 16 12:18:48 PM PDT 24 1166788575 ps
T537 /workspace/coverage/default/8.rstmgr_alert_test.3546577696 May 16 12:24:32 PM PDT 24 May 16 12:24:50 PM PDT 24 88744909 ps
T538 /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1121815000 May 16 12:23:55 PM PDT 24 May 16 12:24:01 PM PDT 24 143537638 ps
T539 /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2672563664 May 16 12:19:34 PM PDT 24 May 16 12:19:36 PM PDT 24 173530856 ps
T64 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.169587333 May 16 12:42:46 PM PDT 24 May 16 12:42:50 PM PDT 24 187355720 ps
T65 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1885536835 May 16 12:42:49 PM PDT 24 May 16 12:42:55 PM PDT 24 72077017 ps
T66 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3205840738 May 16 12:42:45 PM PDT 24 May 16 12:42:49 PM PDT 24 132408136 ps
T67 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.241432826 May 16 12:42:35 PM PDT 24 May 16 12:42:43 PM PDT 24 249236655 ps
T69 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1296627796 May 16 12:42:33 PM PDT 24 May 16 12:42:40 PM PDT 24 113147963 ps
T68 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.636736714 May 16 12:42:30 PM PDT 24 May 16 12:42:34 PM PDT 24 204068779 ps
T101 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1982879650 May 16 12:42:31 PM PDT 24 May 16 12:42:37 PM PDT 24 241075739 ps
T70 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3430809670 May 16 12:42:49 PM PDT 24 May 16 12:42:59 PM PDT 24 586198229 ps
T91 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3269749985 May 16 12:42:35 PM PDT 24 May 16 12:42:42 PM PDT 24 94657599 ps
T71 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.477292217 May 16 12:42:29 PM PDT 24 May 16 12:42:34 PM PDT 24 222202935 ps
T72 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3968430439 May 16 12:42:32 PM PDT 24 May 16 12:42:38 PM PDT 24 132113063 ps
T73 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2737961669 May 16 12:42:45 PM PDT 24 May 16 12:42:50 PM PDT 24 211316697 ps
T102 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.715375928 May 16 12:42:33 PM PDT 24 May 16 12:42:39 PM PDT 24 74566197 ps
T127 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2028863250 May 16 12:42:33 PM PDT 24 May 16 12:42:40 PM PDT 24 81909972 ps
T103 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3028263167 May 16 12:42:52 PM PDT 24 May 16 12:42:59 PM PDT 24 80243573 ps
T92 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3728259762 May 16 12:42:35 PM PDT 24 May 16 12:42:43 PM PDT 24 170745016 ps
T540 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1685578030 May 16 12:42:44 PM PDT 24 May 16 12:42:48 PM PDT 24 110199512 ps
T109 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2892967329 May 16 12:42:33 PM PDT 24 May 16 12:42:42 PM PDT 24 942033027 ps
T112 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3049959209 May 16 12:42:44 PM PDT 24 May 16 12:42:50 PM PDT 24 191858985 ps
T104 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2619808397 May 16 12:42:45 PM PDT 24 May 16 12:42:50 PM PDT 24 218314863 ps
T105 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.201538469 May 16 12:42:51 PM PDT 24 May 16 12:42:58 PM PDT 24 193567140 ps
T110 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.104388870 May 16 12:42:29 PM PDT 24 May 16 12:42:34 PM PDT 24 476207322 ps
T541 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.412900973 May 16 12:42:43 PM PDT 24 May 16 12:42:48 PM PDT 24 185613773 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3044158434 May 16 12:42:35 PM PDT 24 May 16 12:42:42 PM PDT 24 72023510 ps
T106 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1446923889 May 16 12:42:34 PM PDT 24 May 16 12:42:41 PM PDT 24 81705590 ps
T543 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3617353444 May 16 12:42:33 PM PDT 24 May 16 12:42:47 PM PDT 24 1544248111 ps
T113 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3061664300 May 16 12:42:48 PM PDT 24 May 16 12:42:55 PM PDT 24 226067682 ps
T544 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3408800189 May 16 12:42:48 PM PDT 24 May 16 12:42:54 PM PDT 24 81159183 ps
T111 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3525010591 May 16 12:42:42 PM PDT 24 May 16 12:42:49 PM PDT 24 913376355 ps
T107 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1094340922 May 16 12:42:49 PM PDT 24 May 16 12:42:55 PM PDT 24 119568096 ps
T545 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4269914230 May 16 12:42:32 PM PDT 24 May 16 12:42:39 PM PDT 24 174155544 ps
T546 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1424609080 May 16 12:42:24 PM PDT 24 May 16 12:42:27 PM PDT 24 97116970 ps
T114 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1964797845 May 16 12:42:45 PM PDT 24 May 16 12:42:51 PM PDT 24 512276257 ps
T118 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3018586720 May 16 12:42:45 PM PDT 24 May 16 12:42:51 PM PDT 24 872323732 ps
T547 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1300822503 May 16 12:42:48 PM PDT 24 May 16 12:42:54 PM PDT 24 184358847 ps
T548 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2018398680 May 16 12:42:31 PM PDT 24 May 16 12:42:37 PM PDT 24 102450451 ps
T108 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.644818061 May 16 12:42:33 PM PDT 24 May 16 12:42:40 PM PDT 24 223404368 ps
T549 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2966753901 May 16 12:42:30 PM PDT 24 May 16 12:42:35 PM PDT 24 220159010 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.349999537 May 16 12:42:33 PM PDT 24 May 16 12:42:40 PM PDT 24 163539268 ps
T551 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2890988623 May 16 12:42:47 PM PDT 24 May 16 12:42:52 PM PDT 24 176246015 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3010347423 May 16 12:42:30 PM PDT 24 May 16 12:42:34 PM PDT 24 86235194 ps
T553 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3301666949 May 16 12:42:34 PM PDT 24 May 16 12:42:42 PM PDT 24 88818247 ps
T554 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3186232228 May 16 12:42:37 PM PDT 24 May 16 12:42:43 PM PDT 24 66113243 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3216373930 May 16 12:42:35 PM PDT 24 May 16 12:42:42 PM PDT 24 91198613 ps
T556 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3018906343 May 16 12:42:31 PM PDT 24 May 16 12:42:36 PM PDT 24 67193306 ps
T557 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3601673620 May 16 12:42:36 PM PDT 24 May 16 12:42:43 PM PDT 24 68274398 ps
T119 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1979713660 May 16 12:42:49 PM PDT 24 May 16 12:42:57 PM PDT 24 883544337 ps
T558 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2414436264 May 16 12:42:47 PM PDT 24 May 16 12:42:52 PM PDT 24 123818456 ps
T115 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.880801936 May 16 12:42:44 PM PDT 24 May 16 12:42:50 PM PDT 24 923949420 ps
T559 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1227576317 May 16 12:42:37 PM PDT 24 May 16 12:42:44 PM PDT 24 219749420 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1491515860 May 16 12:42:33 PM PDT 24 May 16 12:42:41 PM PDT 24 413537075 ps
T561 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2298592243 May 16 12:42:51 PM PDT 24 May 16 12:42:58 PM PDT 24 245193193 ps
T562 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1029203325 May 16 12:42:50 PM PDT 24 May 16 12:42:56 PM PDT 24 134523910 ps
T563 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1438601201 May 16 12:42:29 PM PDT 24 May 16 12:42:36 PM PDT 24 798378825 ps
T564 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1914225397 May 16 12:42:36 PM PDT 24 May 16 12:42:43 PM PDT 24 152529798 ps
T565 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.220287634 May 16 12:42:43 PM PDT 24 May 16 12:42:47 PM PDT 24 80412426 ps
T566 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2334328964 May 16 12:42:47 PM PDT 24 May 16 12:42:52 PM PDT 24 217540897 ps
T567 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1499106578 May 16 12:42:35 PM PDT 24 May 16 12:42:44 PM PDT 24 427494778 ps
T568 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.862295561 May 16 12:42:45 PM PDT 24 May 16 12:42:49 PM PDT 24 468994756 ps
T569 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.304390253 May 16 12:42:44 PM PDT 24 May 16 12:42:48 PM PDT 24 116956832 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1869378294 May 16 12:42:32 PM PDT 24 May 16 12:42:38 PM PDT 24 86860756 ps
T571 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3059118486 May 16 12:42:35 PM PDT 24 May 16 12:42:44 PM PDT 24 178401274 ps
T572 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.791342888 May 16 12:42:30 PM PDT 24 May 16 12:42:34 PM PDT 24 68741159 ps
T573 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.423909087 May 16 12:42:37 PM PDT 24 May 16 12:42:43 PM PDT 24 78028853 ps
T126 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2102969426 May 16 12:42:36 PM PDT 24 May 16 12:42:45 PM PDT 24 887826880 ps
T574 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.801860708 May 16 12:42:35 PM PDT 24 May 16 12:42:44 PM PDT 24 231788315 ps
T575 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1935583986 May 16 12:42:31 PM PDT 24 May 16 12:42:37 PM PDT 24 75444462 ps
T117 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2678051177 May 16 12:42:35 PM PDT 24 May 16 12:42:44 PM PDT 24 475242910 ps
T576 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.213288371 May 16 12:42:36 PM PDT 24 May 16 12:42:44 PM PDT 24 471571402 ps
T116 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4276292916 May 16 12:42:36 PM PDT 24 May 16 12:42:44 PM PDT 24 488415015 ps
T577 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1291328305 May 16 12:42:34 PM PDT 24 May 16 12:42:42 PM PDT 24 443818246 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2508390039 May 16 12:42:34 PM PDT 24 May 16 12:42:41 PM PDT 24 189823651 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.593567525 May 16 12:42:35 PM PDT 24 May 16 12:42:44 PM PDT 24 953581642 ps
T580 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2415616525 May 16 12:42:35 PM PDT 24 May 16 12:42:43 PM PDT 24 179362674 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3675655777 May 16 12:42:35 PM PDT 24 May 16 12:42:43 PM PDT 24 499494869 ps
T582 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4198572406 May 16 12:42:44 PM PDT 24 May 16 12:42:48 PM PDT 24 145165619 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3454444017 May 16 12:42:30 PM PDT 24 May 16 12:42:35 PM PDT 24 413663574 ps
T584 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3900944281 May 16 12:42:45 PM PDT 24 May 16 12:42:49 PM PDT 24 64904174 ps
T585 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4252953480 May 16 12:42:31 PM PDT 24 May 16 12:42:36 PM PDT 24 162201177 ps
T586 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2103042499 May 16 12:42:43 PM PDT 24 May 16 12:42:48 PM PDT 24 266751080 ps
T587 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3069154259 May 16 12:42:33 PM PDT 24 May 16 12:42:40 PM PDT 24 81031305 ps
T588 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1520808868 May 16 12:42:35 PM PDT 24 May 16 12:42:42 PM PDT 24 66610872 ps
T589 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2331918970 May 16 12:42:34 PM PDT 24 May 16 12:42:41 PM PDT 24 83865507 ps
T590 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3778321947 May 16 12:42:44 PM PDT 24 May 16 12:42:49 PM PDT 24 138831842 ps
T591 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.143619995 May 16 12:42:33 PM PDT 24 May 16 12:42:40 PM PDT 24 174988199 ps
T592 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1036333790 May 16 12:42:33 PM PDT 24 May 16 12:42:40 PM PDT 24 148861517 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3473610637 May 16 12:42:34 PM PDT 24 May 16 12:42:43 PM PDT 24 558544547 ps
T594 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2061846295 May 16 12:42:30 PM PDT 24 May 16 12:42:34 PM PDT 24 187325907 ps
T595 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4133899752 May 16 12:42:30 PM PDT 24 May 16 12:42:33 PM PDT 24 78110984 ps
T596 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3897099348 May 16 12:42:44 PM PDT 24 May 16 12:42:49 PM PDT 24 138235831 ps
T597 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2470862316 May 16 12:42:32 PM PDT 24 May 16 12:42:39 PM PDT 24 207123537 ps
T598 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.911565090 May 16 12:42:45 PM PDT 24 May 16 12:42:49 PM PDT 24 140746531 ps
T599 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2603132259 May 16 12:42:34 PM PDT 24 May 16 12:42:43 PM PDT 24 882282141 ps
T600 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2956884558 May 16 12:42:29 PM PDT 24 May 16 12:42:33 PM PDT 24 85279153 ps
T601 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1756786815 May 16 12:42:48 PM PDT 24 May 16 12:42:53 PM PDT 24 84199913 ps
T602 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1071100897 May 16 12:42:42 PM PDT 24 May 16 12:42:46 PM PDT 24 80707301 ps
T603 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4273368550 May 16 12:42:34 PM PDT 24 May 16 12:42:43 PM PDT 24 185356897 ps
T604 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1576762369 May 16 12:42:31 PM PDT 24 May 16 12:42:36 PM PDT 24 141621160 ps
T120 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.879599090 May 16 12:42:34 PM PDT 24 May 16 12:42:43 PM PDT 24 787330180 ps
T605 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3683796425 May 16 12:42:45 PM PDT 24 May 16 12:42:49 PM PDT 24 492660090 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1310938945 May 16 12:42:34 PM PDT 24 May 16 12:42:41 PM PDT 24 104362096 ps
T607 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1750421104 May 16 12:42:45 PM PDT 24 May 16 12:42:49 PM PDT 24 58490142 ps
T608 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.40239571 May 16 12:42:48 PM PDT 24 May 16 12:42:55 PM PDT 24 193531329 ps
T609 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2222126575 May 16 12:42:31 PM PDT 24 May 16 12:42:35 PM PDT 24 93948327 ps
T610 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2149252413 May 16 12:42:33 PM PDT 24 May 16 12:42:40 PM PDT 24 126232535 ps
T611 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1185927727 May 16 12:42:33 PM PDT 24 May 16 12:42:40 PM PDT 24 111828839 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2463893860 May 16 12:42:34 PM PDT 24 May 16 12:42:43 PM PDT 24 267661196 ps
T613 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1604760350 May 16 12:42:30 PM PDT 24 May 16 12:42:36 PM PDT 24 368622508 ps
T614 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.4251690980 May 16 12:42:47 PM PDT 24 May 16 12:42:51 PM PDT 24 417745264 ps
T615 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1219513848 May 16 12:42:43 PM PDT 24 May 16 12:42:47 PM PDT 24 92657047 ps
T616 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3094507398 May 16 12:42:33 PM PDT 24 May 16 12:42:47 PM PDT 24 1544079017 ps
T617 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.456970255 May 16 12:42:34 PM PDT 24 May 16 12:42:43 PM PDT 24 299413902 ps
T618 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1707843276 May 16 12:42:46 PM PDT 24 May 16 12:42:52 PM PDT 24 871699877 ps
T619 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1348614434 May 16 12:42:35 PM PDT 24 May 16 12:42:42 PM PDT 24 246856677 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2815673127 May 16 12:42:33 PM PDT 24 May 16 12:42:44 PM PDT 24 478998420 ps

Test location /workspace/coverage/default/12.rstmgr_smoke.1720262379
Short name T5
Test name
Test status
Simulation time 107578423 ps
CPU time 1.16 seconds
Started May 16 12:19:07 PM PDT 24
Finished May 16 12:19:09 PM PDT 24
Peak memory 200572 kb
Host smart-dc7d2da4-1183-4435-9706-d52dbdc757d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720262379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1720262379
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.439515112
Short name T26
Test name
Test status
Simulation time 13273764295 ps
CPU time 46.35 seconds
Started May 16 12:23:31 PM PDT 24
Finished May 16 12:24:21 PM PDT 24
Peak memory 208540 kb
Host smart-a6f58cc8-a306-4cc1-8ebc-d36a78ddac61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439515112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.439515112
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3214573851
Short name T3
Test name
Test status
Simulation time 8360722171 ps
CPU time 13.32 seconds
Started May 16 12:23:55 PM PDT 24
Finished May 16 12:24:13 PM PDT 24
Peak memory 217092 kb
Host smart-57dc92e2-b531-4868-82aa-62b326b5fa1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214573851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3214573851
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3968430439
Short name T72
Test name
Test status
Simulation time 132113063 ps
CPU time 1.45 seconds
Started May 16 12:42:32 PM PDT 24
Finished May 16 12:42:38 PM PDT 24
Peak memory 208500 kb
Host smart-281077e6-5cc1-4da1-a8bc-e9364f12eb08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968430439 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3968430439
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2838587491
Short name T13
Test name
Test status
Simulation time 385750246 ps
CPU time 2.51 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:14 PM PDT 24
Peak memory 200060 kb
Host smart-9502cdca-742c-4184-9a49-03d84afc8f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838587491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2838587491
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3401680924
Short name T1
Test name
Test status
Simulation time 2361832915 ps
CPU time 7.84 seconds
Started May 16 12:24:15 PM PDT 24
Finished May 16 12:24:36 PM PDT 24
Peak memory 217516 kb
Host smart-7c8cfeaa-f1a5-48b8-a914-8a710055e6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401680924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3401680924
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3525010591
Short name T111
Test name
Test status
Simulation time 913376355 ps
CPU time 3.46 seconds
Started May 16 12:42:42 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 200544 kb
Host smart-d0bb3fcb-b1fc-4b03-8dc7-74a5e7e6904e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525010591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3525010591
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1460061681
Short name T95
Test name
Test status
Simulation time 11972793485 ps
CPU time 40.13 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:24:01 PM PDT 24
Peak memory 198912 kb
Host smart-8323e891-a312-423e-89ba-9c579fa550e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460061681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1460061681
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2284190550
Short name T76
Test name
Test status
Simulation time 81404245 ps
CPU time 0.9 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:46 PM PDT 24
Peak memory 198468 kb
Host smart-390c63e2-a890-4aa9-ade6-c69fd9204729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284190550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2284190550
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1964797845
Short name T114
Test name
Test status
Simulation time 512276257 ps
CPU time 3.89 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:51 PM PDT 24
Peak memory 216708 kb
Host smart-97aece52-611d-433d-87e0-43e25b5fe737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964797845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1964797845
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1736684244
Short name T82
Test name
Test status
Simulation time 154571825 ps
CPU time 1.2 seconds
Started May 16 12:18:37 PM PDT 24
Finished May 16 12:18:41 PM PDT 24
Peak memory 199620 kb
Host smart-78ce947b-a31c-4095-ae1c-3ef1ffd83a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736684244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1736684244
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2892967329
Short name T109
Test name
Test status
Simulation time 942033027 ps
CPU time 3.04 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:42 PM PDT 24
Peak memory 200540 kb
Host smart-caaf8e5d-2d89-46c1-bae9-5847b45940ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892967329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2892967329
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2805672335
Short name T33
Test name
Test status
Simulation time 2169836171 ps
CPU time 7.57 seconds
Started May 16 12:24:39 PM PDT 24
Finished May 16 12:25:05 PM PDT 24
Peak memory 217624 kb
Host smart-24260a7b-3568-459e-b789-592977d64118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805672335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2805672335
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1652465246
Short name T53
Test name
Test status
Simulation time 1235871628 ps
CPU time 5.58 seconds
Started May 16 12:24:18 PM PDT 24
Finished May 16 12:24:38 PM PDT 24
Peak memory 218036 kb
Host smart-8bda5db7-47d3-4ada-b5ef-d32979f1d600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652465246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1652465246
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1190133916
Short name T158
Test name
Test status
Simulation time 75028385 ps
CPU time 0.91 seconds
Started May 16 12:18:45 PM PDT 24
Finished May 16 12:18:49 PM PDT 24
Peak memory 200460 kb
Host smart-b2f81070-5e22-4875-9ef0-3f1b0687d9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190133916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1190133916
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.241432826
Short name T67
Test name
Test status
Simulation time 249236655 ps
CPU time 1.55 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200612 kb
Host smart-27b2d7b6-cddd-47fb-a12f-feff487701c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241432826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.241432826
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.520671811
Short name T20
Test name
Test status
Simulation time 81899367 ps
CPU time 0.78 seconds
Started May 16 12:22:04 PM PDT 24
Finished May 16 12:22:06 PM PDT 24
Peak memory 200152 kb
Host smart-bc01d503-29e1-45f2-a157-f071edaa1e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520671811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.520671811
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.594311703
Short name T148
Test name
Test status
Simulation time 244445600 ps
CPU time 1.1 seconds
Started May 16 12:23:56 PM PDT 24
Finished May 16 12:24:01 PM PDT 24
Peak memory 217252 kb
Host smart-527797e7-3ef0-48f8-8569-bba0498b914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594311703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.594311703
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2678051177
Short name T117
Test name
Test status
Simulation time 475242910 ps
CPU time 2.23 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 200724 kb
Host smart-b120925a-95da-41e5-963c-96334ea01959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678051177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2678051177
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2794061021
Short name T217
Test name
Test status
Simulation time 4593778867 ps
CPU time 22.57 seconds
Started May 16 12:24:02 PM PDT 24
Finished May 16 12:24:29 PM PDT 24
Peak memory 200556 kb
Host smart-fb275266-587c-457e-88ab-d3694c603196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794061021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2794061021
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.349999537
Short name T550
Test name
Test status
Simulation time 163539268 ps
CPU time 1.87 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 200384 kb
Host smart-4226ef69-4b04-4d99-b777-b641f255831a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349999537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.349999537
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3094507398
Short name T616
Test name
Test status
Simulation time 1544079017 ps
CPU time 8.04 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:47 PM PDT 24
Peak memory 200440 kb
Host smart-df19c08c-8893-4cb3-b292-72341ea6e802
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094507398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
094507398
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2222126575
Short name T609
Test name
Test status
Simulation time 93948327 ps
CPU time 0.85 seconds
Started May 16 12:42:31 PM PDT 24
Finished May 16 12:42:35 PM PDT 24
Peak memory 200236 kb
Host smart-4a61353e-e52b-465e-911c-05221790ac9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222126575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
222126575
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4269914230
Short name T545
Test name
Test status
Simulation time 174155544 ps
CPU time 1.54 seconds
Started May 16 12:42:32 PM PDT 24
Finished May 16 12:42:39 PM PDT 24
Peak memory 208964 kb
Host smart-4025c4eb-5489-481c-9085-471858a3a16e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269914230 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.4269914230
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3044158434
Short name T542
Test name
Test status
Simulation time 72023510 ps
CPU time 0.79 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:42 PM PDT 24
Peak memory 200280 kb
Host smart-f4df406e-bd20-4516-96db-d65099e808b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044158434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3044158434
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1348614434
Short name T619
Test name
Test status
Simulation time 246856677 ps
CPU time 1.48 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:42 PM PDT 24
Peak memory 200560 kb
Host smart-cc218e64-e185-4c2b-80e0-53887114c08b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348614434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1348614434
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.477292217
Short name T71
Test name
Test status
Simulation time 222202935 ps
CPU time 1.92 seconds
Started May 16 12:42:29 PM PDT 24
Finished May 16 12:42:34 PM PDT 24
Peak memory 216824 kb
Host smart-75e4e430-fa92-4e09-8e8b-22f4ba96da40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477292217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.477292217
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1491515860
Short name T560
Test name
Test status
Simulation time 413537075 ps
CPU time 2.46 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:41 PM PDT 24
Peak memory 200452 kb
Host smart-7edf42c8-8333-418f-955b-b0ff55ca1570
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491515860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
491515860
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2815673127
Short name T620
Test name
Test status
Simulation time 478998420 ps
CPU time 5.36 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 200460 kb
Host smart-f05a3926-4799-4f2f-aaea-84713dec1925
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815673127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
815673127
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3216373930
Short name T555
Test name
Test status
Simulation time 91198613 ps
CPU time 0.76 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:42 PM PDT 24
Peak memory 200176 kb
Host smart-4d5ca545-236b-43e7-8d4f-5290c8def141
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216373930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
216373930
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.4133899752
Short name T595
Test name
Test status
Simulation time 78110984 ps
CPU time 0.77 seconds
Started May 16 12:42:30 PM PDT 24
Finished May 16 12:42:33 PM PDT 24
Peak memory 200292 kb
Host smart-f4b2a136-a2b5-4d35-9de3-5590f39b4c16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133899752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.4133899752
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2149252413
Short name T610
Test name
Test status
Simulation time 126232535 ps
CPU time 1.06 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 200260 kb
Host smart-d636ff31-a638-4a6b-8c93-fa09f3b7d4e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149252413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2149252413
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1499106578
Short name T567
Test name
Test status
Simulation time 427494778 ps
CPU time 3.08 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 211608 kb
Host smart-5ee8a502-27ae-4d9a-86cf-292c273bf2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499106578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1499106578
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3473610637
Short name T593
Test name
Test status
Simulation time 558544547 ps
CPU time 2.05 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200460 kb
Host smart-bc6f2aae-96ec-4baf-8373-e57c10c848d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473610637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3473610637
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1914225397
Short name T564
Test name
Test status
Simulation time 152529798 ps
CPU time 1.11 seconds
Started May 16 12:42:36 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200556 kb
Host smart-d5cf4611-c79b-49ba-a38d-51574952a27c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914225397 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1914225397
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3186232228
Short name T554
Test name
Test status
Simulation time 66113243 ps
CPU time 0.82 seconds
Started May 16 12:42:37 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200208 kb
Host smart-3d26a2f8-8f46-4857-979d-7f309bc25d51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186232228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3186232228
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3728259762
Short name T92
Test name
Test status
Simulation time 170745016 ps
CPU time 2.25 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 208708 kb
Host smart-b44fd06c-7b93-48d1-b6a7-d135c19fa527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728259762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3728259762
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2102969426
Short name T126
Test name
Test status
Simulation time 887826880 ps
CPU time 3.02 seconds
Started May 16 12:42:36 PM PDT 24
Finished May 16 12:42:45 PM PDT 24
Peak memory 200580 kb
Host smart-82869d2f-029b-4bf9-ab5c-083f4c7e5ecf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102969426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2102969426
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4198572406
Short name T582
Test name
Test status
Simulation time 145165619 ps
CPU time 1.08 seconds
Started May 16 12:42:44 PM PDT 24
Finished May 16 12:42:48 PM PDT 24
Peak memory 200428 kb
Host smart-a40224b2-72a0-420a-83d9-9a9a4b61ef16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198572406 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.4198572406
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.423909087
Short name T573
Test name
Test status
Simulation time 78028853 ps
CPU time 0.78 seconds
Started May 16 12:42:37 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200320 kb
Host smart-ef76db5e-fc17-4494-bbe4-d4d37b53fdd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423909087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.423909087
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2414436264
Short name T558
Test name
Test status
Simulation time 123818456 ps
CPU time 1.1 seconds
Started May 16 12:42:47 PM PDT 24
Finished May 16 12:42:52 PM PDT 24
Peak memory 200304 kb
Host smart-166af7c8-8a9e-4eb1-a224-1496871e4b84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414436264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2414436264
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1227576317
Short name T559
Test name
Test status
Simulation time 219749420 ps
CPU time 1.58 seconds
Started May 16 12:42:37 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 210804 kb
Host smart-f3c74e35-30d1-4811-87da-aaf99e8442db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227576317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1227576317
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4276292916
Short name T116
Test name
Test status
Simulation time 488415015 ps
CPU time 1.89 seconds
Started May 16 12:42:36 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 200468 kb
Host smart-719efe38-fb80-47b4-9d7c-7e63940c1245
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276292916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4276292916
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.412900973
Short name T541
Test name
Test status
Simulation time 185613773 ps
CPU time 1.21 seconds
Started May 16 12:42:43 PM PDT 24
Finished May 16 12:42:48 PM PDT 24
Peak memory 200356 kb
Host smart-9f972276-3ce8-4961-b9e6-aeb865609ff2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412900973 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.412900973
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1885536835
Short name T65
Test name
Test status
Simulation time 72077017 ps
CPU time 0.79 seconds
Started May 16 12:42:49 PM PDT 24
Finished May 16 12:42:55 PM PDT 24
Peak memory 200200 kb
Host smart-501ccc3a-79b5-4c63-bf8d-819c88b0d980
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885536835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1885536835
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2103042499
Short name T586
Test name
Test status
Simulation time 266751080 ps
CPU time 1.67 seconds
Started May 16 12:42:43 PM PDT 24
Finished May 16 12:42:48 PM PDT 24
Peak memory 200412 kb
Host smart-55778f78-4b5c-423e-afcb-e47fb9486e92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103042499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2103042499
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3778321947
Short name T590
Test name
Test status
Simulation time 138831842 ps
CPU time 1.98 seconds
Started May 16 12:42:44 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 208740 kb
Host smart-b6ffabec-277f-47dd-a40c-407b27fa4850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778321947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3778321947
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.862295561
Short name T568
Test name
Test status
Simulation time 468994756 ps
CPU time 2.06 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 200588 kb
Host smart-3ba9a9bd-9d27-4fff-8783-2dad6a7f159e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862295561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.862295561
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2334328964
Short name T566
Test name
Test status
Simulation time 217540897 ps
CPU time 1.45 seconds
Started May 16 12:42:47 PM PDT 24
Finished May 16 12:42:52 PM PDT 24
Peak memory 208500 kb
Host smart-ad3f3ad6-6b43-4337-a907-2177c0420f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334328964 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2334328964
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.220287634
Short name T565
Test name
Test status
Simulation time 80412426 ps
CPU time 0.83 seconds
Started May 16 12:42:43 PM PDT 24
Finished May 16 12:42:47 PM PDT 24
Peak memory 200228 kb
Host smart-844879fc-06e8-4c03-88b9-4976185e023f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220287634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.220287634
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2890988623
Short name T551
Test name
Test status
Simulation time 176246015 ps
CPU time 1.37 seconds
Started May 16 12:42:47 PM PDT 24
Finished May 16 12:42:52 PM PDT 24
Peak memory 200512 kb
Host smart-e031d22d-35dc-4cc4-afd3-44d0286c0a6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890988623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2890988623
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3061664300
Short name T113
Test name
Test status
Simulation time 226067682 ps
CPU time 3.14 seconds
Started May 16 12:42:48 PM PDT 24
Finished May 16 12:42:55 PM PDT 24
Peak memory 216820 kb
Host smart-6064a425-d999-4c23-ba95-a0b05df7f3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061664300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3061664300
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.880801936
Short name T115
Test name
Test status
Simulation time 923949420 ps
CPU time 3.02 seconds
Started May 16 12:42:44 PM PDT 24
Finished May 16 12:42:50 PM PDT 24
Peak memory 200432 kb
Host smart-49c330e7-b701-4833-af0c-6b3c69d307c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880801936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.880801936
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.169587333
Short name T64
Test name
Test status
Simulation time 187355720 ps
CPU time 1.16 seconds
Started May 16 12:42:46 PM PDT 24
Finished May 16 12:42:50 PM PDT 24
Peak memory 200404 kb
Host smart-92a0b599-f308-427b-9374-8eb32b657d57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169587333 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.169587333
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1756786815
Short name T601
Test name
Test status
Simulation time 84199913 ps
CPU time 0.81 seconds
Started May 16 12:42:48 PM PDT 24
Finished May 16 12:42:53 PM PDT 24
Peak memory 200284 kb
Host smart-75900bfe-3637-4201-88ce-e90681a0f713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756786815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1756786815
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1094340922
Short name T107
Test name
Test status
Simulation time 119568096 ps
CPU time 0.99 seconds
Started May 16 12:42:49 PM PDT 24
Finished May 16 12:42:55 PM PDT 24
Peak memory 200324 kb
Host smart-83e7b4c0-2e3e-4b4c-a947-2588c22743fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094340922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1094340922
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2737961669
Short name T73
Test name
Test status
Simulation time 211316697 ps
CPU time 1.8 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:50 PM PDT 24
Peak memory 208632 kb
Host smart-94b9e88c-a709-41e8-8a51-dcb26bc40a13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737961669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2737961669
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.4251690980
Short name T614
Test name
Test status
Simulation time 417745264 ps
CPU time 1.75 seconds
Started May 16 12:42:47 PM PDT 24
Finished May 16 12:42:51 PM PDT 24
Peak memory 200580 kb
Host smart-e4d5f53f-38f2-4aaf-9acb-5db98a8936f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251690980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.4251690980
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.304390253
Short name T569
Test name
Test status
Simulation time 116956832 ps
CPU time 1.22 seconds
Started May 16 12:42:44 PM PDT 24
Finished May 16 12:42:48 PM PDT 24
Peak memory 208564 kb
Host smart-649491df-ac44-4e57-9234-6ea133d91c90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304390253 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.304390253
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1750421104
Short name T607
Test name
Test status
Simulation time 58490142 ps
CPU time 0.74 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 200220 kb
Host smart-326a56c6-a7ab-4bea-8b4d-12fb35ca3080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750421104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1750421104
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1029203325
Short name T562
Test name
Test status
Simulation time 134523910 ps
CPU time 1.17 seconds
Started May 16 12:42:50 PM PDT 24
Finished May 16 12:42:56 PM PDT 24
Peak memory 200324 kb
Host smart-9022bb5f-5f1d-435d-a5a6-0c4356af96a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029203325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1029203325
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2298592243
Short name T561
Test name
Test status
Simulation time 245193193 ps
CPU time 1.81 seconds
Started May 16 12:42:51 PM PDT 24
Finished May 16 12:42:58 PM PDT 24
Peak memory 208620 kb
Host smart-898a42d0-c255-428f-bd85-b1ddfc06b0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298592243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2298592243
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1707843276
Short name T618
Test name
Test status
Simulation time 871699877 ps
CPU time 3.28 seconds
Started May 16 12:42:46 PM PDT 24
Finished May 16 12:42:52 PM PDT 24
Peak memory 200548 kb
Host smart-fe4c9965-7832-419f-9f5b-9e0180a7f50d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707843276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1707843276
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1300822503
Short name T547
Test name
Test status
Simulation time 184358847 ps
CPU time 1.13 seconds
Started May 16 12:42:48 PM PDT 24
Finished May 16 12:42:54 PM PDT 24
Peak memory 200404 kb
Host smart-1880119c-9dca-401f-b0c9-4c08c40ad147
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300822503 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1300822503
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3900944281
Short name T584
Test name
Test status
Simulation time 64904174 ps
CPU time 0.78 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 200220 kb
Host smart-7ca79193-b347-44f9-9eb9-4724409220de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900944281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3900944281
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.201538469
Short name T105
Test name
Test status
Simulation time 193567140 ps
CPU time 1.38 seconds
Started May 16 12:42:51 PM PDT 24
Finished May 16 12:42:58 PM PDT 24
Peak memory 200416 kb
Host smart-34a23b62-7950-4cdb-a49b-ebc4b4cf35ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201538469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.201538469
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3430809670
Short name T70
Test name
Test status
Simulation time 586198229 ps
CPU time 4.23 seconds
Started May 16 12:42:49 PM PDT 24
Finished May 16 12:42:59 PM PDT 24
Peak memory 212204 kb
Host smart-e9bf9cd6-8a7d-47e9-abad-76ba8a845928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430809670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3430809670
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3205840738
Short name T66
Test name
Test status
Simulation time 132408136 ps
CPU time 1 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 200356 kb
Host smart-8e093715-8aa1-477b-8bd1-f7ba87b62835
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205840738 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3205840738
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3408800189
Short name T544
Test name
Test status
Simulation time 81159183 ps
CPU time 0.82 seconds
Started May 16 12:42:48 PM PDT 24
Finished May 16 12:42:54 PM PDT 24
Peak memory 200208 kb
Host smart-43db1f35-8385-43b9-b0d3-ecf434e83eb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408800189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3408800189
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2619808397
Short name T104
Test name
Test status
Simulation time 218314863 ps
CPU time 1.46 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:50 PM PDT 24
Peak memory 200504 kb
Host smart-568b1c7f-c38a-49aa-88b1-357842981880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619808397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2619808397
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.40239571
Short name T608
Test name
Test status
Simulation time 193531329 ps
CPU time 2.52 seconds
Started May 16 12:42:48 PM PDT 24
Finished May 16 12:42:55 PM PDT 24
Peak memory 216856 kb
Host smart-6497743f-4caa-4337-911b-37ae92827fe9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40239571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.40239571
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3683796425
Short name T605
Test name
Test status
Simulation time 492660090 ps
CPU time 2.08 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 200600 kb
Host smart-601d539c-da7b-4fef-a355-6b86a0716223
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683796425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3683796425
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3897099348
Short name T596
Test name
Test status
Simulation time 138235831 ps
CPU time 1.43 seconds
Started May 16 12:42:44 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 208820 kb
Host smart-9760b6b6-687c-4b1b-ae43-b9db9a352b96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897099348 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3897099348
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1071100897
Short name T602
Test name
Test status
Simulation time 80707301 ps
CPU time 0.79 seconds
Started May 16 12:42:42 PM PDT 24
Finished May 16 12:42:46 PM PDT 24
Peak memory 200168 kb
Host smart-1a110f21-ddfa-4b3d-81f7-7f45536969c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071100897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1071100897
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3028263167
Short name T103
Test name
Test status
Simulation time 80243573 ps
CPU time 1 seconds
Started May 16 12:42:52 PM PDT 24
Finished May 16 12:42:59 PM PDT 24
Peak memory 200332 kb
Host smart-f29bc871-dd5b-4d71-95aa-c6533ff5d889
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028263167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3028263167
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1979713660
Short name T119
Test name
Test status
Simulation time 883544337 ps
CPU time 3.08 seconds
Started May 16 12:42:49 PM PDT 24
Finished May 16 12:42:57 PM PDT 24
Peak memory 200528 kb
Host smart-1612f49d-8750-4069-b55b-0da5ad75128e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979713660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1979713660
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1685578030
Short name T540
Test name
Test status
Simulation time 110199512 ps
CPU time 0.94 seconds
Started May 16 12:42:44 PM PDT 24
Finished May 16 12:42:48 PM PDT 24
Peak memory 208524 kb
Host smart-e111091c-c47a-45a9-ba8e-b113d8253722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685578030 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1685578030
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1219513848
Short name T615
Test name
Test status
Simulation time 92657047 ps
CPU time 0.92 seconds
Started May 16 12:42:43 PM PDT 24
Finished May 16 12:42:47 PM PDT 24
Peak memory 200196 kb
Host smart-9d31d077-283a-44a2-958b-f42860dbbb7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219513848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1219513848
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.911565090
Short name T598
Test name
Test status
Simulation time 140746531 ps
CPU time 1.23 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:49 PM PDT 24
Peak memory 200544 kb
Host smart-af31e46e-3bec-44de-bc68-ada4e6d67b78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911565090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.911565090
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3049959209
Short name T112
Test name
Test status
Simulation time 191858985 ps
CPU time 2.6 seconds
Started May 16 12:42:44 PM PDT 24
Finished May 16 12:42:50 PM PDT 24
Peak memory 208596 kb
Host smart-76dbd29e-008d-485c-b719-ecc483956315
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049959209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3049959209
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3018586720
Short name T118
Test name
Test status
Simulation time 872323732 ps
CPU time 2.99 seconds
Started May 16 12:42:45 PM PDT 24
Finished May 16 12:42:51 PM PDT 24
Peak memory 200580 kb
Host smart-a2f25d01-9d71-4f3b-977a-a71e3f3f12d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018586720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3018586720
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1310938945
Short name T606
Test name
Test status
Simulation time 104362096 ps
CPU time 1.34 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:41 PM PDT 24
Peak memory 200500 kb
Host smart-53fe4e0e-e017-45bb-a3fa-c6a0c697a156
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310938945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
310938945
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1438601201
Short name T563
Test name
Test status
Simulation time 798378825 ps
CPU time 4.33 seconds
Started May 16 12:42:29 PM PDT 24
Finished May 16 12:42:36 PM PDT 24
Peak memory 200516 kb
Host smart-8e31ad96-6c64-448d-a80b-2c2457a39581
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438601201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
438601201
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1036333790
Short name T592
Test name
Test status
Simulation time 148861517 ps
CPU time 0.96 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 200196 kb
Host smart-43d667be-ed3c-45ad-b6f6-a8b86a3b7825
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036333790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
036333790
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3269749985
Short name T91
Test name
Test status
Simulation time 94657599 ps
CPU time 0.89 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:42 PM PDT 24
Peak memory 200484 kb
Host smart-78573fcc-e64c-4d8d-9915-04fddb2846a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269749985 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3269749985
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3018906343
Short name T556
Test name
Test status
Simulation time 67193306 ps
CPU time 0.77 seconds
Started May 16 12:42:31 PM PDT 24
Finished May 16 12:42:36 PM PDT 24
Peak memory 200340 kb
Host smart-8ab35da5-feec-4234-ba5b-ce71316e7106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018906343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3018906343
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3301666949
Short name T553
Test name
Test status
Simulation time 88818247 ps
CPU time 1.02 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:42 PM PDT 24
Peak memory 200252 kb
Host smart-94bc3239-66e6-4c8c-acac-37778773a484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301666949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3301666949
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3454444017
Short name T583
Test name
Test status
Simulation time 413663574 ps
CPU time 2.65 seconds
Started May 16 12:42:30 PM PDT 24
Finished May 16 12:42:35 PM PDT 24
Peak memory 211736 kb
Host smart-fdc65af1-df7b-4898-b315-fbc63b29c82c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454444017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3454444017
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.213288371
Short name T576
Test name
Test status
Simulation time 471571402 ps
CPU time 1.87 seconds
Started May 16 12:42:36 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 200748 kb
Host smart-ce4a6983-be4b-4d77-b234-2701150e4949
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213288371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
213288371
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1185927727
Short name T611
Test name
Test status
Simulation time 111828839 ps
CPU time 1.4 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 200468 kb
Host smart-a3186dc5-d73f-4853-bf33-7ed71cb81863
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185927727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
185927727
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3617353444
Short name T543
Test name
Test status
Simulation time 1544248111 ps
CPU time 7.67 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:47 PM PDT 24
Peak memory 208652 kb
Host smart-17ea0a1d-31e0-4bcd-8996-58758b2d8482
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617353444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
617353444
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3010347423
Short name T552
Test name
Test status
Simulation time 86235194 ps
CPU time 0.8 seconds
Started May 16 12:42:30 PM PDT 24
Finished May 16 12:42:34 PM PDT 24
Peak memory 200128 kb
Host smart-4e44df4c-2825-42d1-808b-0b9e96d04d40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010347423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
010347423
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2061846295
Short name T594
Test name
Test status
Simulation time 187325907 ps
CPU time 1.84 seconds
Started May 16 12:42:30 PM PDT 24
Finished May 16 12:42:34 PM PDT 24
Peak memory 208736 kb
Host smart-522216fc-f952-4ca2-8546-0debdc3787b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061846295 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2061846295
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1869378294
Short name T570
Test name
Test status
Simulation time 86860756 ps
CPU time 0.85 seconds
Started May 16 12:42:32 PM PDT 24
Finished May 16 12:42:38 PM PDT 24
Peak memory 200272 kb
Host smart-4044b1d5-c576-4b60-9002-f8e5214d9eac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869378294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1869378294
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1982879650
Short name T101
Test name
Test status
Simulation time 241075739 ps
CPU time 1.53 seconds
Started May 16 12:42:31 PM PDT 24
Finished May 16 12:42:37 PM PDT 24
Peak memory 200544 kb
Host smart-003e1168-5324-47a0-89c1-df8b2945b72c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982879650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1982879650
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2018398680
Short name T548
Test name
Test status
Simulation time 102450451 ps
CPU time 1.18 seconds
Started May 16 12:42:31 PM PDT 24
Finished May 16 12:42:37 PM PDT 24
Peak memory 200404 kb
Host smart-13b2451b-3292-4752-b59b-66e316d5d86a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018398680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2018398680
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1291328305
Short name T577
Test name
Test status
Simulation time 443818246 ps
CPU time 1.75 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:42 PM PDT 24
Peak memory 200436 kb
Host smart-a5c786f9-344d-41b7-a64a-dfa42208ad64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291328305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1291328305
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1424609080
Short name T546
Test name
Test status
Simulation time 97116970 ps
CPU time 1.25 seconds
Started May 16 12:42:24 PM PDT 24
Finished May 16 12:42:27 PM PDT 24
Peak memory 200368 kb
Host smart-1dd10143-b82b-4389-b0f1-f04418c2f5c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424609080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
424609080
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2463893860
Short name T612
Test name
Test status
Simulation time 267661196 ps
CPU time 3.15 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200352 kb
Host smart-c4a58bd1-c080-4140-b978-8702e6881797
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463893860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
463893860
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1576762369
Short name T604
Test name
Test status
Simulation time 141621160 ps
CPU time 0.91 seconds
Started May 16 12:42:31 PM PDT 24
Finished May 16 12:42:36 PM PDT 24
Peak memory 200272 kb
Host smart-44da8c09-d129-43ee-8168-16436079971f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576762369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
576762369
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2508390039
Short name T578
Test name
Test status
Simulation time 189823651 ps
CPU time 1.29 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:41 PM PDT 24
Peak memory 208640 kb
Host smart-2f31bf40-3745-4896-96e7-2370a6705e2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508390039 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2508390039
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1935583986
Short name T575
Test name
Test status
Simulation time 75444462 ps
CPU time 0.76 seconds
Started May 16 12:42:31 PM PDT 24
Finished May 16 12:42:37 PM PDT 24
Peak memory 200316 kb
Host smart-513e8177-8546-4822-9705-60a558b21c74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935583986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1935583986
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.715375928
Short name T102
Test name
Test status
Simulation time 74566197 ps
CPU time 0.89 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:39 PM PDT 24
Peak memory 200336 kb
Host smart-27dbb7ca-ed68-4de4-a267-2844979a1314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715375928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.715375928
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3059118486
Short name T571
Test name
Test status
Simulation time 178401274 ps
CPU time 2.4 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 208712 kb
Host smart-a5492123-ae08-42ac-8309-6735c9623222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059118486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3059118486
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.593567525
Short name T579
Test name
Test status
Simulation time 953581642 ps
CPU time 3.03 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 200580 kb
Host smart-b1521bee-c458-430d-b262-b5ee141bb834
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593567525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
593567525
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1296627796
Short name T69
Test name
Test status
Simulation time 113147963 ps
CPU time 0.87 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 200400 kb
Host smart-4c9c8c09-4558-4f02-b4c1-e6147f2c735d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296627796 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1296627796
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2028863250
Short name T127
Test name
Test status
Simulation time 81909972 ps
CPU time 0.85 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 200276 kb
Host smart-402f18b1-df85-4dca-8538-135d5befdc5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028863250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2028863250
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.644818061
Short name T108
Test name
Test status
Simulation time 223404368 ps
CPU time 1.43 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 200432 kb
Host smart-a7176f14-b351-4a25-8ac6-f4432c132af1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644818061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.644818061
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2470862316
Short name T597
Test name
Test status
Simulation time 207123537 ps
CPU time 1.71 seconds
Started May 16 12:42:32 PM PDT 24
Finished May 16 12:42:39 PM PDT 24
Peak memory 208636 kb
Host smart-e619a34e-06a1-455a-a4f5-48a3b8429415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470862316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2470862316
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.104388870
Short name T110
Test name
Test status
Simulation time 476207322 ps
CPU time 2.1 seconds
Started May 16 12:42:29 PM PDT 24
Finished May 16 12:42:34 PM PDT 24
Peak memory 200560 kb
Host smart-5b5e7a57-5ded-4cf0-bb73-ba4fed7c7ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104388870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
104388870
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4252953480
Short name T585
Test name
Test status
Simulation time 162201177 ps
CPU time 1.16 seconds
Started May 16 12:42:31 PM PDT 24
Finished May 16 12:42:36 PM PDT 24
Peak memory 200492 kb
Host smart-a9c523f7-2821-4a67-81bf-40dbfb85b0f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252953480 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.4252953480
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2331918970
Short name T589
Test name
Test status
Simulation time 83865507 ps
CPU time 0.9 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:41 PM PDT 24
Peak memory 200192 kb
Host smart-1a800031-0042-47ba-855a-7ea365ca9d37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331918970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2331918970
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2956884558
Short name T600
Test name
Test status
Simulation time 85279153 ps
CPU time 1.05 seconds
Started May 16 12:42:29 PM PDT 24
Finished May 16 12:42:33 PM PDT 24
Peak memory 200296 kb
Host smart-1f3492c9-f2de-4a79-9446-47c5ebcdb503
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956884558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2956884558
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4273368550
Short name T603
Test name
Test status
Simulation time 185356897 ps
CPU time 2.56 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 208660 kb
Host smart-6d38453b-2b29-4f65-817a-587f42558eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273368550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4273368550
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.879599090
Short name T120
Test name
Test status
Simulation time 787330180 ps
CPU time 2.75 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200568 kb
Host smart-612ffc56-4ab9-4bd3-83c8-9f96d6f2b6b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879599090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
879599090
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.143619995
Short name T591
Test name
Test status
Simulation time 174988199 ps
CPU time 1.2 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 208628 kb
Host smart-1fd15e8f-c198-4f0a-afd3-17da520a8b08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143619995 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.143619995
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3601673620
Short name T557
Test name
Test status
Simulation time 68274398 ps
CPU time 0.76 seconds
Started May 16 12:42:36 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200208 kb
Host smart-f17f7dbb-2f93-42aa-b5b7-75af2f1ff053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601673620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3601673620
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3069154259
Short name T587
Test name
Test status
Simulation time 81031305 ps
CPU time 1.07 seconds
Started May 16 12:42:33 PM PDT 24
Finished May 16 12:42:40 PM PDT 24
Peak memory 200324 kb
Host smart-2d7f925a-1e6d-44cb-9082-80a5a228fb3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069154259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3069154259
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1604760350
Short name T613
Test name
Test status
Simulation time 368622508 ps
CPU time 2.49 seconds
Started May 16 12:42:30 PM PDT 24
Finished May 16 12:42:36 PM PDT 24
Peak memory 212200 kb
Host smart-375a4563-322c-4489-8503-07a3403e1749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604760350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1604760350
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2603132259
Short name T599
Test name
Test status
Simulation time 882282141 ps
CPU time 3.09 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200540 kb
Host smart-584f4049-7249-4a6d-9a49-08acd56c2c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603132259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2603132259
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.636736714
Short name T68
Test name
Test status
Simulation time 204068779 ps
CPU time 1.27 seconds
Started May 16 12:42:30 PM PDT 24
Finished May 16 12:42:34 PM PDT 24
Peak memory 208496 kb
Host smart-b8b9a08a-d836-4128-9117-1f79fb67badc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636736714 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.636736714
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1520808868
Short name T588
Test name
Test status
Simulation time 66610872 ps
CPU time 0.74 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:42 PM PDT 24
Peak memory 200280 kb
Host smart-a13c617f-7d2b-4874-b397-402bfead822f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520808868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1520808868
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1446923889
Short name T106
Test name
Test status
Simulation time 81705590 ps
CPU time 0.96 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:41 PM PDT 24
Peak memory 200248 kb
Host smart-9bab5a6c-8c24-493a-b66a-e9ba202d0187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446923889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1446923889
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.801860708
Short name T574
Test name
Test status
Simulation time 231788315 ps
CPU time 1.97 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:44 PM PDT 24
Peak memory 208860 kb
Host smart-386581ce-c852-4be3-93f7-3b63208020ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801860708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.801860708
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2415616525
Short name T580
Test name
Test status
Simulation time 179362674 ps
CPU time 1.65 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 208680 kb
Host smart-906b9af9-5abf-4dec-8555-9ebada33898e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415616525 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2415616525
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.791342888
Short name T572
Test name
Test status
Simulation time 68741159 ps
CPU time 0.76 seconds
Started May 16 12:42:30 PM PDT 24
Finished May 16 12:42:34 PM PDT 24
Peak memory 200116 kb
Host smart-93f70360-69cf-4e14-917b-3ce8b9ae8ccf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791342888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.791342888
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2966753901
Short name T549
Test name
Test status
Simulation time 220159010 ps
CPU time 1.4 seconds
Started May 16 12:42:30 PM PDT 24
Finished May 16 12:42:35 PM PDT 24
Peak memory 200492 kb
Host smart-992be502-b6ad-4f63-8d39-00f094697a79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966753901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2966753901
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.456970255
Short name T617
Test name
Test status
Simulation time 299413902 ps
CPU time 2.28 seconds
Started May 16 12:42:34 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 208600 kb
Host smart-f60926c9-6222-42cf-bd51-4aaf75a19919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456970255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.456970255
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3675655777
Short name T581
Test name
Test status
Simulation time 499494869 ps
CPU time 1.94 seconds
Started May 16 12:42:35 PM PDT 24
Finished May 16 12:42:43 PM PDT 24
Peak memory 200608 kb
Host smart-65b95858-f77e-4111-8173-24e424a8a805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675655777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3675655777
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2108201740
Short name T376
Test name
Test status
Simulation time 72280806 ps
CPU time 0.76 seconds
Started May 16 12:20:19 PM PDT 24
Finished May 16 12:20:21 PM PDT 24
Peak memory 200240 kb
Host smart-a5df46ec-ece7-49fe-9901-345b6ecee823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108201740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2108201740
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2669190130
Short name T468
Test name
Test status
Simulation time 1218828694 ps
CPU time 5.93 seconds
Started May 16 12:18:40 PM PDT 24
Finished May 16 12:18:49 PM PDT 24
Peak memory 217064 kb
Host smart-015c730a-5202-4ca1-b888-0ab02526abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669190130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2669190130
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2295628924
Short name T240
Test name
Test status
Simulation time 181497129 ps
CPU time 0.93 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:30 PM PDT 24
Peak memory 199952 kb
Host smart-5d57c86a-1a1e-4d28-950d-df711aba9a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295628924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2295628924
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3933195287
Short name T189
Test name
Test status
Simulation time 1303240657 ps
CPU time 5.05 seconds
Started May 16 12:18:45 PM PDT 24
Finished May 16 12:18:54 PM PDT 24
Peak memory 200712 kb
Host smart-49d71d9c-1961-4de5-b143-ff8947a5738c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933195287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3933195287
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.825834862
Short name T74
Test name
Test status
Simulation time 8712263541 ps
CPU time 13.66 seconds
Started May 16 12:18:40 PM PDT 24
Finished May 16 12:18:57 PM PDT 24
Peak memory 217516 kb
Host smart-a9ff0840-9f2f-4680-a9bd-a8ae8d9a242d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825834862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.825834862
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.59129711
Short name T431
Test name
Test status
Simulation time 114701028 ps
CPU time 1.1 seconds
Started May 16 12:24:20 PM PDT 24
Finished May 16 12:24:36 PM PDT 24
Peak memory 200280 kb
Host smart-bbe35894-5cac-462e-b935-f4b8b3f75381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59129711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.59129711
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.4006894182
Short name T385
Test name
Test status
Simulation time 128697659 ps
CPU time 1.52 seconds
Started May 16 12:23:25 PM PDT 24
Finished May 16 12:23:32 PM PDT 24
Peak memory 199124 kb
Host smart-f5ac9d1e-fcc8-4c40-babd-dc4ef10b6b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006894182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4006894182
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1276505663
Short name T283
Test name
Test status
Simulation time 221032592 ps
CPU time 1.36 seconds
Started May 16 12:18:44 PM PDT 24
Finished May 16 12:18:49 PM PDT 24
Peak memory 200408 kb
Host smart-e4109629-816c-4951-84e7-ebac10eea48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276505663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1276505663
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1930247991
Short name T204
Test name
Test status
Simulation time 85740988 ps
CPU time 0.82 seconds
Started May 16 12:24:02 PM PDT 24
Finished May 16 12:24:09 PM PDT 24
Peak memory 200020 kb
Host smart-b6629a7c-801e-40ac-82ed-1b058eef58ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930247991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1930247991
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3899308290
Short name T475
Test name
Test status
Simulation time 1228425500 ps
CPU time 6.1 seconds
Started May 16 12:21:11 PM PDT 24
Finished May 16 12:21:18 PM PDT 24
Peak memory 217484 kb
Host smart-76fa3f4c-480f-46c4-9b1d-8a91ed065efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899308290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3899308290
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1986938320
Short name T132
Test name
Test status
Simulation time 245279577 ps
CPU time 1.26 seconds
Started May 16 12:18:36 PM PDT 24
Finished May 16 12:18:39 PM PDT 24
Peak memory 216680 kb
Host smart-b5c92389-edf7-444c-bf68-b1a07b76bf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986938320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1986938320
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2354430386
Short name T358
Test name
Test status
Simulation time 120408025 ps
CPU time 0.77 seconds
Started May 16 12:18:44 PM PDT 24
Finished May 16 12:18:48 PM PDT 24
Peak memory 200244 kb
Host smart-ebcf7794-666a-4f46-be28-4509bcdd74fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354430386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2354430386
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2412016950
Short name T244
Test name
Test status
Simulation time 1700716240 ps
CPU time 6.1 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:56 PM PDT 24
Peak memory 199832 kb
Host smart-3f9480c1-84c1-42e3-8d4d-8f712a4c2b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412016950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2412016950
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3015085092
Short name T78
Test name
Test status
Simulation time 8307012197 ps
CPU time 16.28 seconds
Started May 16 12:18:43 PM PDT 24
Finished May 16 12:19:03 PM PDT 24
Peak memory 216228 kb
Host smart-32ae5c4b-9524-4903-ab73-4fb47412fa8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015085092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3015085092
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3694251415
Short name T258
Test name
Test status
Simulation time 139994381 ps
CPU time 1.1 seconds
Started May 16 12:18:41 PM PDT 24
Finished May 16 12:18:45 PM PDT 24
Peak memory 200400 kb
Host smart-2efc5bf2-1290-4626-a9ca-ca767f12e80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694251415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3694251415
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2165565274
Short name T195
Test name
Test status
Simulation time 198824212 ps
CPU time 1.44 seconds
Started May 16 12:21:29 PM PDT 24
Finished May 16 12:21:32 PM PDT 24
Peak memory 200636 kb
Host smart-bdd09b0f-ef16-4c3e-9505-3c1c70d8c32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165565274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2165565274
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3826064857
Short name T81
Test name
Test status
Simulation time 326865826 ps
CPU time 1.95 seconds
Started May 16 12:23:56 PM PDT 24
Finished May 16 12:24:02 PM PDT 24
Peak memory 200324 kb
Host smart-8ce05fb7-ad94-4ed0-93ea-1a7bbaaab218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826064857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3826064857
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.281221988
Short name T323
Test name
Test status
Simulation time 550661790 ps
CPU time 2.92 seconds
Started May 16 12:18:37 PM PDT 24
Finished May 16 12:18:42 PM PDT 24
Peak memory 200476 kb
Host smart-f7ae2d81-0411-49a2-9007-731c32344599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281221988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.281221988
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3484154819
Short name T414
Test name
Test status
Simulation time 75235177 ps
CPU time 0.84 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:25 PM PDT 24
Peak memory 200168 kb
Host smart-60a60373-d51a-4966-b9b4-6d554b4ac2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484154819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3484154819
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1647855497
Short name T474
Test name
Test status
Simulation time 244901346 ps
CPU time 1 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:52 PM PDT 24
Peak memory 217476 kb
Host smart-c4b400cc-a069-40e3-b3b5-522a5571f5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647855497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1647855497
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1989130903
Short name T494
Test name
Test status
Simulation time 166443103 ps
CPU time 0.86 seconds
Started May 16 12:19:58 PM PDT 24
Finished May 16 12:20:00 PM PDT 24
Peak memory 200236 kb
Host smart-b599c1ae-5e81-4143-8ada-c88021323267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989130903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1989130903
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2517009345
Short name T14
Test name
Test status
Simulation time 1917830197 ps
CPU time 6.89 seconds
Started May 16 12:20:15 PM PDT 24
Finished May 16 12:20:24 PM PDT 24
Peak memory 200752 kb
Host smart-f70baf4f-c34c-45cf-afeb-a14bca886c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517009345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2517009345
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1629136323
Short name T514
Test name
Test status
Simulation time 158398447 ps
CPU time 1.09 seconds
Started May 16 12:20:28 PM PDT 24
Finished May 16 12:20:30 PM PDT 24
Peak memory 200388 kb
Host smart-0822ff25-9000-40f9-86d8-0b86a4b3d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629136323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1629136323
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.4070470532
Short name T241
Test name
Test status
Simulation time 127369808 ps
CPU time 1.19 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:51 PM PDT 24
Peak memory 198532 kb
Host smart-5cf261e8-d5d3-4ff3-9a10-bab534a35f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070470532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.4070470532
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1010863129
Short name T299
Test name
Test status
Simulation time 3761551158 ps
CPU time 16.59 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:25:07 PM PDT 24
Peak memory 200280 kb
Host smart-a183205f-1cdb-4c03-9cba-f813d9a9e821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010863129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1010863129
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3038683010
Short name T335
Test name
Test status
Simulation time 293445875 ps
CPU time 2.03 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:52 PM PDT 24
Peak memory 206100 kb
Host smart-96680373-4ce3-4251-ab2d-b2a820a75341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038683010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3038683010
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4218205571
Short name T16
Test name
Test status
Simulation time 221370107 ps
CPU time 1.32 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:51 PM PDT 24
Peak memory 198608 kb
Host smart-e38aca65-48ea-4196-92c9-fe7ea2701ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218205571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4218205571
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3905219544
Short name T342
Test name
Test status
Simulation time 75482335 ps
CPU time 0.79 seconds
Started May 16 12:21:39 PM PDT 24
Finished May 16 12:21:41 PM PDT 24
Peak memory 200084 kb
Host smart-3b5463fa-c804-479a-8c63-e67428a69282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905219544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3905219544
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1060114878
Short name T36
Test name
Test status
Simulation time 1889547848 ps
CPU time 7.13 seconds
Started May 16 12:22:37 PM PDT 24
Finished May 16 12:22:45 PM PDT 24
Peak memory 218020 kb
Host smart-89f88e6d-5208-45b2-86c3-95facce3cff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060114878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1060114878
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1321754442
Short name T415
Test name
Test status
Simulation time 251115742 ps
CPU time 1.11 seconds
Started May 16 12:22:12 PM PDT 24
Finished May 16 12:22:14 PM PDT 24
Peak memory 217540 kb
Host smart-0618c451-bda0-487d-bbdb-dd95c6ebcb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321754442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1321754442
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2430570311
Short name T224
Test name
Test status
Simulation time 118166248 ps
CPU time 0.85 seconds
Started May 16 12:21:45 PM PDT 24
Finished May 16 12:21:47 PM PDT 24
Peak memory 200284 kb
Host smart-ab582c15-c486-440a-b512-9acecfe9fa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430570311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2430570311
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3876268047
Short name T418
Test name
Test status
Simulation time 963796593 ps
CPU time 4.38 seconds
Started May 16 12:24:38 PM PDT 24
Finished May 16 12:25:02 PM PDT 24
Peak memory 200568 kb
Host smart-f4b3f9d1-c796-4c14-9d24-5df5a2164963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876268047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3876268047
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2331473020
Short name T484
Test name
Test status
Simulation time 139538656 ps
CPU time 1.1 seconds
Started May 16 12:21:49 PM PDT 24
Finished May 16 12:21:52 PM PDT 24
Peak memory 200408 kb
Host smart-f7865dad-cfc9-44d0-9368-bb6938462cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331473020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2331473020
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1548726122
Short name T194
Test name
Test status
Simulation time 253160586 ps
CPU time 1.56 seconds
Started May 16 12:21:54 PM PDT 24
Finished May 16 12:21:57 PM PDT 24
Peak memory 200704 kb
Host smart-c028a524-5db7-4d49-8bc7-595130725804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548726122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1548726122
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3645069907
Short name T326
Test name
Test status
Simulation time 9807395658 ps
CPU time 37.18 seconds
Started May 16 12:22:15 PM PDT 24
Finished May 16 12:22:53 PM PDT 24
Peak memory 208888 kb
Host smart-a84540fe-6b31-4660-9adc-4abfceb226ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645069907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3645069907
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2606329117
Short name T513
Test name
Test status
Simulation time 278497843 ps
CPU time 1.96 seconds
Started May 16 12:23:51 PM PDT 24
Finished May 16 12:23:56 PM PDT 24
Peak memory 200552 kb
Host smart-770c5c22-6a12-4055-acbb-74593f909f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606329117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2606329117
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1104150901
Short name T366
Test name
Test status
Simulation time 92615764 ps
CPU time 0.94 seconds
Started May 16 12:21:25 PM PDT 24
Finished May 16 12:21:27 PM PDT 24
Peak memory 197092 kb
Host smart-5f4f5323-9731-4bdf-91f3-b62c119db644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104150901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1104150901
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3178379251
Short name T381
Test name
Test status
Simulation time 76619538 ps
CPU time 0.89 seconds
Started May 16 12:22:44 PM PDT 24
Finished May 16 12:22:46 PM PDT 24
Peak memory 200240 kb
Host smart-01943527-bbd2-47c7-adf0-87cbdb7f68a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178379251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3178379251
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2527901229
Short name T58
Test name
Test status
Simulation time 2360966711 ps
CPU time 7.94 seconds
Started May 16 12:21:55 PM PDT 24
Finished May 16 12:22:05 PM PDT 24
Peak memory 221556 kb
Host smart-da6041d9-6023-40de-8b21-fde0ec5c368e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527901229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2527901229
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2004037225
Short name T177
Test name
Test status
Simulation time 243956536 ps
CPU time 1.18 seconds
Started May 16 12:21:39 PM PDT 24
Finished May 16 12:21:40 PM PDT 24
Peak memory 217492 kb
Host smart-4bcbdbe9-f3e3-4bb8-a3e9-aa15b61dd0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004037225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2004037225
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.4284226738
Short name T223
Test name
Test status
Simulation time 102374777 ps
CPU time 0.86 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:46 PM PDT 24
Peak memory 198328 kb
Host smart-48240705-1259-4c50-bc19-b8ad964fa6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284226738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.4284226738
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.481963811
Short name T363
Test name
Test status
Simulation time 838912458 ps
CPU time 4.25 seconds
Started May 16 12:23:56 PM PDT 24
Finished May 16 12:24:04 PM PDT 24
Peak memory 200548 kb
Host smart-9f3401b7-cf4a-4654-84b4-ad1c30048c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481963811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.481963811
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1191125140
Short name T404
Test name
Test status
Simulation time 180984781 ps
CPU time 1.18 seconds
Started May 16 12:23:46 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 200020 kb
Host smart-8870d524-565b-44e9-8afd-3b9ad9e48c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191125140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1191125140
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3276345785
Short name T48
Test name
Test status
Simulation time 7231135211 ps
CPU time 26.76 seconds
Started May 16 12:19:30 PM PDT 24
Finished May 16 12:19:58 PM PDT 24
Peak memory 200700 kb
Host smart-b717b6a4-15e3-4871-9fb1-cafd43703eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276345785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3276345785
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.696321047
Short name T449
Test name
Test status
Simulation time 255070977 ps
CPU time 1.91 seconds
Started May 16 12:22:38 PM PDT 24
Finished May 16 12:22:41 PM PDT 24
Peak memory 200452 kb
Host smart-27bcdded-b8c4-4796-ad08-5cb17cb3ed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696321047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.696321047
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2508702047
Short name T129
Test name
Test status
Simulation time 236731580 ps
CPU time 1.39 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:23:23 PM PDT 24
Peak memory 199488 kb
Host smart-b887dcc6-cc51-4ac2-acea-831fe8203823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508702047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2508702047
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1101971888
Short name T192
Test name
Test status
Simulation time 75238162 ps
CPU time 0.74 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:15 PM PDT 24
Peak memory 199828 kb
Host smart-849d50d6-a9bf-4759-a0ab-de40d8e2a879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101971888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1101971888
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1560466257
Short name T61
Test name
Test status
Simulation time 1231296535 ps
CPU time 5.22 seconds
Started May 16 12:24:11 PM PDT 24
Finished May 16 12:24:28 PM PDT 24
Peak memory 217972 kb
Host smart-c2923c5a-3aab-4610-851e-de440e0dee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560466257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1560466257
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1586547746
Short name T408
Test name
Test status
Simulation time 244207345 ps
CPU time 1.07 seconds
Started May 16 12:24:06 PM PDT 24
Finished May 16 12:24:17 PM PDT 24
Peak memory 217288 kb
Host smart-ac81acbe-07a8-4a0f-8f8d-a8674b246e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586547746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1586547746
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1616993512
Short name T370
Test name
Test status
Simulation time 142855884 ps
CPU time 0.81 seconds
Started May 16 12:22:54 PM PDT 24
Finished May 16 12:22:56 PM PDT 24
Peak memory 200292 kb
Host smart-77319be1-852a-43a3-b50b-57dbdbd39b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616993512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1616993512
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2765958724
Short name T433
Test name
Test status
Simulation time 909324415 ps
CPU time 3.99 seconds
Started May 16 12:23:57 PM PDT 24
Finished May 16 12:24:05 PM PDT 24
Peak memory 200440 kb
Host smart-01261371-5927-4c1c-a9fd-ac19a48acefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765958724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2765958724
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2382784381
Short name T318
Test name
Test status
Simulation time 112780328 ps
CPU time 1.17 seconds
Started May 16 12:22:01 PM PDT 24
Finished May 16 12:22:05 PM PDT 24
Peak memory 198948 kb
Host smart-cf3bd043-1efc-4b35-8341-9d6a30bc581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382784381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2382784381
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.257295901
Short name T389
Test name
Test status
Simulation time 195741739 ps
CPU time 1.47 seconds
Started May 16 12:22:51 PM PDT 24
Finished May 16 12:22:54 PM PDT 24
Peak memory 200588 kb
Host smart-e385c959-a389-48ba-bfe5-38e1768610c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257295901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.257295901
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1864301190
Short name T535
Test name
Test status
Simulation time 1126738477 ps
CPU time 4.82 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:17 PM PDT 24
Peak memory 208152 kb
Host smart-b67b8c9d-1727-474e-b37f-d576a542f1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864301190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1864301190
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3599601742
Short name T135
Test name
Test status
Simulation time 296028200 ps
CPU time 1.9 seconds
Started May 16 12:22:49 PM PDT 24
Finished May 16 12:22:52 PM PDT 24
Peak memory 208528 kb
Host smart-9204fab0-50fe-41d7-8fc4-5dc033d9664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599601742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3599601742
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.419208390
Short name T398
Test name
Test status
Simulation time 95577994 ps
CPU time 0.89 seconds
Started May 16 12:22:54 PM PDT 24
Finished May 16 12:22:55 PM PDT 24
Peak memory 200472 kb
Host smart-dd4a94e1-cfce-4659-864c-211d3bc2dc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419208390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.419208390
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1962416010
Short name T391
Test name
Test status
Simulation time 70190953 ps
CPU time 0.83 seconds
Started May 16 12:22:13 PM PDT 24
Finished May 16 12:22:14 PM PDT 24
Peak memory 200284 kb
Host smart-c307e826-59bf-49d3-96f1-695c3799d785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962416010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1962416010
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.782697613
Short name T511
Test name
Test status
Simulation time 1903504166 ps
CPU time 7.02 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:21 PM PDT 24
Peak memory 221496 kb
Host smart-309f109c-d496-4af6-96af-bd1a946618cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782697613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.782697613
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.414613453
Short name T253
Test name
Test status
Simulation time 244236999 ps
CPU time 1.14 seconds
Started May 16 12:22:08 PM PDT 24
Finished May 16 12:22:10 PM PDT 24
Peak memory 217488 kb
Host smart-dcfbd662-0079-4e2d-9502-2dd6b26daebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414613453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.414613453
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4278036875
Short name T516
Test name
Test status
Simulation time 182149637 ps
CPU time 0.89 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:14 PM PDT 24
Peak memory 199844 kb
Host smart-c44a3758-b956-4e52-96fd-af3567cb4ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278036875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4278036875
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1080259450
Short name T340
Test name
Test status
Simulation time 872670926 ps
CPU time 4.55 seconds
Started May 16 12:21:28 PM PDT 24
Finished May 16 12:21:34 PM PDT 24
Peak memory 200684 kb
Host smart-1dad8cef-f6e7-4157-b5f6-841325324bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080259450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1080259450
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.4281094598
Short name T80
Test name
Test status
Simulation time 171441179 ps
CPU time 1.23 seconds
Started May 16 12:24:11 PM PDT 24
Finished May 16 12:24:25 PM PDT 24
Peak memory 199396 kb
Host smart-234c8c14-00ba-4d02-a396-2e3ad9f38b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281094598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.4281094598
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.284331928
Short name T302
Test name
Test status
Simulation time 259944606 ps
CPU time 1.41 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:16 PM PDT 24
Peak memory 200208 kb
Host smart-85ffc9a0-cbe1-4ed3-b341-f23db591c63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284331928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.284331928
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1742648115
Short name T477
Test name
Test status
Simulation time 7373383865 ps
CPU time 32.19 seconds
Started May 16 12:20:13 PM PDT 24
Finished May 16 12:20:47 PM PDT 24
Peak memory 209692 kb
Host smart-820bd635-c901-4893-b12f-a6e202f09212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742648115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1742648115
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2745750243
Short name T361
Test name
Test status
Simulation time 474537495 ps
CPU time 2.49 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:16 PM PDT 24
Peak memory 199196 kb
Host smart-6ae12221-9bc8-4678-9f80-8ca0cb36d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745750243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2745750243
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3232914327
Short name T136
Test name
Test status
Simulation time 297326281 ps
CPU time 1.7 seconds
Started May 16 12:21:26 PM PDT 24
Finished May 16 12:21:30 PM PDT 24
Peak memory 200584 kb
Host smart-b8140cc0-76ad-4ed3-bedf-1d7e9949f31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232914327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3232914327
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3779028782
Short name T528
Test name
Test status
Simulation time 91404627 ps
CPU time 0.87 seconds
Started May 16 12:18:59 PM PDT 24
Finished May 16 12:19:01 PM PDT 24
Peak memory 200256 kb
Host smart-225d0c82-315d-4fcd-b0dc-7737edea951e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779028782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3779028782
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2682073927
Short name T55
Test name
Test status
Simulation time 2182926958 ps
CPU time 7.53 seconds
Started May 16 12:18:55 PM PDT 24
Finished May 16 12:19:04 PM PDT 24
Peak memory 217532 kb
Host smart-e055bf41-4e85-4017-be7a-3ec5451adfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682073927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2682073927
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.605181787
Short name T352
Test name
Test status
Simulation time 245371201 ps
CPU time 1.1 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 216964 kb
Host smart-a7731364-1bf1-4447-b168-29b412169fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605181787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.605181787
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2121606283
Short name T359
Test name
Test status
Simulation time 1347456776 ps
CPU time 5.39 seconds
Started May 16 12:18:54 PM PDT 24
Finished May 16 12:19:01 PM PDT 24
Peak memory 200668 kb
Host smart-ee22635c-c33c-4ba1-beeb-93d8e4fae05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121606283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2121606283
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.415348653
Short name T501
Test name
Test status
Simulation time 108327582 ps
CPU time 1.05 seconds
Started May 16 12:21:04 PM PDT 24
Finished May 16 12:21:06 PM PDT 24
Peak memory 200568 kb
Host smart-b628178b-6942-4f30-95a4-48ce8c502db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415348653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.415348653
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3142401795
Short name T334
Test name
Test status
Simulation time 119275248 ps
CPU time 1.13 seconds
Started May 16 12:22:15 PM PDT 24
Finished May 16 12:22:17 PM PDT 24
Peak memory 200520 kb
Host smart-00105825-1773-4723-9399-06e0e7963d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142401795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3142401795
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1628828401
Short name T226
Test name
Test status
Simulation time 4048472082 ps
CPU time 20.22 seconds
Started May 16 12:19:27 PM PDT 24
Finished May 16 12:19:48 PM PDT 24
Peak memory 209052 kb
Host smart-83d72315-c9fa-4a18-aaff-3558fad41571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628828401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1628828401
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2701196531
Short name T85
Test name
Test status
Simulation time 400858174 ps
CPU time 2.13 seconds
Started May 16 12:23:46 PM PDT 24
Finished May 16 12:23:53 PM PDT 24
Peak memory 198748 kb
Host smart-db1bc430-114e-496c-8e0c-e5e1f8aea403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701196531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2701196531
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2738478640
Short name T483
Test name
Test status
Simulation time 185815584 ps
CPU time 1.25 seconds
Started May 16 12:23:46 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 199520 kb
Host smart-892af55e-2461-4835-bece-ebac8931773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738478640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2738478640
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1040373083
Short name T237
Test name
Test status
Simulation time 61820492 ps
CPU time 0.74 seconds
Started May 16 12:23:24 PM PDT 24
Finished May 16 12:23:31 PM PDT 24
Peak memory 198904 kb
Host smart-28b5e385-46af-4c29-9cc0-1d9caf46e5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040373083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1040373083
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1935967790
Short name T280
Test name
Test status
Simulation time 248115291 ps
CPU time 1.08 seconds
Started May 16 12:23:25 PM PDT 24
Finished May 16 12:23:32 PM PDT 24
Peak memory 217056 kb
Host smart-8884e44a-8064-47da-9912-5c1b6ce96bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935967790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1935967790
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.4124122032
Short name T485
Test name
Test status
Simulation time 221118524 ps
CPU time 0.96 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:14 PM PDT 24
Peak memory 200012 kb
Host smart-33e808ab-2bf6-4af9-974a-3ae60af98a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124122032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4124122032
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4152455024
Short name T236
Test name
Test status
Simulation time 1423630732 ps
CPU time 5.62 seconds
Started May 16 12:24:14 PM PDT 24
Finished May 16 12:24:33 PM PDT 24
Peak memory 199408 kb
Host smart-004409c0-ceed-45bf-97d8-8369e2da0102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152455024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4152455024
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2424961047
Short name T374
Test name
Test status
Simulation time 181949478 ps
CPU time 1.09 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:12 PM PDT 24
Peak memory 200084 kb
Host smart-e11fcd65-c297-4f85-9557-8ce7aabc84ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424961047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2424961047
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1724685653
Short name T480
Test name
Test status
Simulation time 205951809 ps
CPU time 1.42 seconds
Started May 16 12:24:33 PM PDT 24
Finished May 16 12:24:53 PM PDT 24
Peak memory 199424 kb
Host smart-17e30835-a8ad-4236-869f-e5a566563ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724685653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1724685653
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2240748942
Short name T420
Test name
Test status
Simulation time 8665805988 ps
CPU time 32.05 seconds
Started May 16 12:23:24 PM PDT 24
Finished May 16 12:24:02 PM PDT 24
Peak memory 208908 kb
Host smart-aca801c3-5df7-473d-85ad-02e573ff85bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240748942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2240748942
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2540480561
Short name T153
Test name
Test status
Simulation time 393957149 ps
CPU time 2.26 seconds
Started May 16 12:24:41 PM PDT 24
Finished May 16 12:25:06 PM PDT 24
Peak memory 200164 kb
Host smart-9d8f7ecb-c165-4163-acee-6db23331f494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540480561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2540480561
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3669307144
Short name T297
Test name
Test status
Simulation time 151203732 ps
CPU time 1.13 seconds
Started May 16 12:18:54 PM PDT 24
Finished May 16 12:18:57 PM PDT 24
Peak memory 200300 kb
Host smart-18c52233-395c-4962-8d79-c744d48e8276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669307144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3669307144
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1221792620
Short name T284
Test name
Test status
Simulation time 81105370 ps
CPU time 0.85 seconds
Started May 16 12:24:55 PM PDT 24
Finished May 16 12:25:10 PM PDT 24
Peak memory 199380 kb
Host smart-b7f51e39-dec3-4253-ab28-9ab9dd3309e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221792620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1221792620
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1162466133
Short name T62
Test name
Test status
Simulation time 1213666994 ps
CPU time 5.81 seconds
Started May 16 12:19:21 PM PDT 24
Finished May 16 12:19:27 PM PDT 24
Peak memory 217568 kb
Host smart-ec76d183-99c4-401e-8037-26e82deae54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162466133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1162466133
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3260117000
Short name T233
Test name
Test status
Simulation time 243582149 ps
CPU time 1.15 seconds
Started May 16 12:19:12 PM PDT 24
Finished May 16 12:19:14 PM PDT 24
Peak memory 217448 kb
Host smart-686c770b-b6b3-4a65-8806-8b45cf8755f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260117000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3260117000
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4006831889
Short name T454
Test name
Test status
Simulation time 157371456 ps
CPU time 1 seconds
Started May 16 12:19:11 PM PDT 24
Finished May 16 12:19:13 PM PDT 24
Peak memory 200272 kb
Host smart-9cf25814-024a-463f-99c2-ecb0e1de8171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006831889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4006831889
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.4062445247
Short name T218
Test name
Test status
Simulation time 1586163515 ps
CPU time 5.98 seconds
Started May 16 12:19:07 PM PDT 24
Finished May 16 12:19:14 PM PDT 24
Peak memory 200596 kb
Host smart-46f87927-0233-460a-a171-4b853646b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062445247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4062445247
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1415537955
Short name T205
Test name
Test status
Simulation time 143707811 ps
CPU time 1.2 seconds
Started May 16 12:21:28 PM PDT 24
Finished May 16 12:21:30 PM PDT 24
Peak memory 200568 kb
Host smart-68d87be1-e601-4b11-b3db-6098245e4339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415537955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1415537955
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3587338275
Short name T131
Test name
Test status
Simulation time 199866122 ps
CPU time 1.35 seconds
Started May 16 12:23:25 PM PDT 24
Finished May 16 12:23:32 PM PDT 24
Peak memory 200172 kb
Host smart-ff861104-767b-421a-9013-14ba8217befa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587338275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3587338275
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2278494840
Short name T421
Test name
Test status
Simulation time 1694174675 ps
CPU time 6.87 seconds
Started May 16 12:22:48 PM PDT 24
Finished May 16 12:22:56 PM PDT 24
Peak memory 200560 kb
Host smart-2c84f35f-b1b9-42c6-b8ab-ac428aafb1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278494840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2278494840
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2902906751
Short name T291
Test name
Test status
Simulation time 264065986 ps
CPU time 1.8 seconds
Started May 16 12:19:11 PM PDT 24
Finished May 16 12:19:13 PM PDT 24
Peak memory 200456 kb
Host smart-50232e22-b820-4c1a-8474-47c2def2afe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902906751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2902906751
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2801631709
Short name T139
Test name
Test status
Simulation time 129499813 ps
CPU time 1.07 seconds
Started May 16 12:19:13 PM PDT 24
Finished May 16 12:19:15 PM PDT 24
Peak memory 200420 kb
Host smart-4d71421c-7d70-48fc-93ee-ad8da7b07ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801631709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2801631709
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2194128263
Short name T229
Test name
Test status
Simulation time 74740379 ps
CPU time 0.86 seconds
Started May 16 12:21:14 PM PDT 24
Finished May 16 12:21:16 PM PDT 24
Peak memory 200204 kb
Host smart-8441e515-c739-434b-abd8-1a2386576c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194128263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2194128263
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1873298535
Short name T463
Test name
Test status
Simulation time 2175584943 ps
CPU time 8.56 seconds
Started May 16 12:19:26 PM PDT 24
Finished May 16 12:19:36 PM PDT 24
Peak memory 217240 kb
Host smart-3f73b978-0747-4b02-93fd-faa47982ecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873298535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1873298535
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.391765689
Short name T429
Test name
Test status
Simulation time 244404991 ps
CPU time 1.08 seconds
Started May 16 12:19:41 PM PDT 24
Finished May 16 12:19:44 PM PDT 24
Peak memory 217596 kb
Host smart-0fa141b3-c1ab-4b4b-8017-1d7738bae75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391765689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.391765689
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.602013854
Short name T502
Test name
Test status
Simulation time 92902098 ps
CPU time 0.75 seconds
Started May 16 12:23:22 PM PDT 24
Finished May 16 12:23:28 PM PDT 24
Peak memory 199460 kb
Host smart-ae1a829b-1e57-4f64-b821-078cec343827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602013854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.602013854
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1483389808
Short name T246
Test name
Test status
Simulation time 1291748272 ps
CPU time 5.37 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:19 PM PDT 24
Peak memory 199380 kb
Host smart-2079872e-82f4-4a11-9265-53c0b96c2c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483389808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1483389808
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2754734392
Short name T272
Test name
Test status
Simulation time 144661036 ps
CPU time 1.11 seconds
Started May 16 12:19:41 PM PDT 24
Finished May 16 12:19:43 PM PDT 24
Peak memory 200484 kb
Host smart-2e1de2a7-d7ba-4c4e-834c-40d96e162c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754734392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2754734392
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3574881413
Short name T309
Test name
Test status
Simulation time 251080313 ps
CPU time 1.54 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:15 PM PDT 24
Peak memory 199612 kb
Host smart-7fd7fc50-ad0f-48e4-8008-cadd6bc51fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574881413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3574881413
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.4199069495
Short name T491
Test name
Test status
Simulation time 4655911048 ps
CPU time 21.42 seconds
Started May 16 12:20:47 PM PDT 24
Finished May 16 12:21:09 PM PDT 24
Peak memory 200824 kb
Host smart-1c6bebc2-c010-43cf-9339-30e191da27f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199069495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4199069495
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3534812636
Short name T161
Test name
Test status
Simulation time 106157764 ps
CPU time 1.02 seconds
Started May 16 12:22:11 PM PDT 24
Finished May 16 12:22:13 PM PDT 24
Peak memory 200556 kb
Host smart-3b8197ed-6d3f-40af-9cf9-a2c40dddc13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534812636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3534812636
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.413752487
Short name T208
Test name
Test status
Simulation time 89449157 ps
CPU time 0.82 seconds
Started May 16 12:21:26 PM PDT 24
Finished May 16 12:21:28 PM PDT 24
Peak memory 199952 kb
Host smart-683cccf3-d9e4-495f-babd-f057c2088653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413752487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.413752487
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.8206473
Short name T396
Test name
Test status
Simulation time 1883341475 ps
CPU time 6.81 seconds
Started May 16 12:23:20 PM PDT 24
Finished May 16 12:23:31 PM PDT 24
Peak memory 217216 kb
Host smart-3896083e-a3b4-4fbe-a5a8-a000a5d50681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8206473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.8206473
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2987187191
Short name T186
Test name
Test status
Simulation time 245613235 ps
CPU time 1.12 seconds
Started May 16 12:21:25 PM PDT 24
Finished May 16 12:21:27 PM PDT 24
Peak memory 214296 kb
Host smart-0dac38d8-4815-42a6-931e-ce262da08993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987187191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2987187191
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1813510509
Short name T534
Test name
Test status
Simulation time 171861834 ps
CPU time 0.85 seconds
Started May 16 12:19:40 PM PDT 24
Finished May 16 12:19:42 PM PDT 24
Peak memory 200292 kb
Host smart-83bccce0-9d5a-4532-b0db-86bf7f75fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813510509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1813510509
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.4272024044
Short name T395
Test name
Test status
Simulation time 748206215 ps
CPU time 3.97 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:28 PM PDT 24
Peak memory 200524 kb
Host smart-29d3ea84-2b7b-480f-9250-21e0f85a0c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272024044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.4272024044
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3026516662
Short name T448
Test name
Test status
Simulation time 160784307 ps
CPU time 1.11 seconds
Started May 16 12:19:41 PM PDT 24
Finished May 16 12:19:43 PM PDT 24
Peak memory 200484 kb
Host smart-49b722d1-4c3e-4672-9ac4-0a4414c98f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026516662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3026516662
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2720849806
Short name T151
Test name
Test status
Simulation time 123362394 ps
CPU time 1.19 seconds
Started May 16 12:21:25 PM PDT 24
Finished May 16 12:21:28 PM PDT 24
Peak memory 198240 kb
Host smart-f0ffbd6d-e552-4aec-9f18-6651640daea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720849806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2720849806
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3275430828
Short name T187
Test name
Test status
Simulation time 9978609468 ps
CPU time 32.52 seconds
Started May 16 12:23:19 PM PDT 24
Finished May 16 12:23:56 PM PDT 24
Peak memory 199168 kb
Host smart-ca2c7ff4-7c52-4925-8e1c-f44e2447da23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275430828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3275430828
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3937443979
Short name T525
Test name
Test status
Simulation time 354875414 ps
CPU time 2.22 seconds
Started May 16 12:23:19 PM PDT 24
Finished May 16 12:23:26 PM PDT 24
Peak memory 198892 kb
Host smart-f9578ce2-10c6-4fa6-9baa-5d71483d763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937443979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3937443979
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3926574284
Short name T167
Test name
Test status
Simulation time 65074005 ps
CPU time 0.78 seconds
Started May 16 12:24:14 PM PDT 24
Finished May 16 12:24:27 PM PDT 24
Peak memory 200216 kb
Host smart-0a335aca-5cbd-406e-bd4c-5c17a902b899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926574284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3926574284
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3386018272
Short name T276
Test name
Test status
Simulation time 76863443 ps
CPU time 0.81 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:13 PM PDT 24
Peak memory 200008 kb
Host smart-4d766fda-63fa-4cdf-8a77-710f45314af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386018272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3386018272
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2324252253
Short name T63
Test name
Test status
Simulation time 1890091113 ps
CPU time 7.51 seconds
Started May 16 12:18:38 PM PDT 24
Finished May 16 12:18:48 PM PDT 24
Peak memory 217656 kb
Host smart-c7f5ef4d-c9ea-424a-92c3-163ec9fbe2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324252253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2324252253
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.937504380
Short name T314
Test name
Test status
Simulation time 244862702 ps
CPU time 1.16 seconds
Started May 16 12:18:43 PM PDT 24
Finished May 16 12:18:48 PM PDT 24
Peak memory 215824 kb
Host smart-e6e887e0-76a2-4bcd-a48e-c3b54bdea0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937504380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.937504380
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1755358541
Short name T401
Test name
Test status
Simulation time 208439228 ps
CPU time 0.86 seconds
Started May 16 12:25:09 PM PDT 24
Finished May 16 12:25:16 PM PDT 24
Peak memory 199952 kb
Host smart-ed90a14c-b858-443c-96dd-aafe896d9328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755358541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1755358541
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1385201245
Short name T324
Test name
Test status
Simulation time 1453786221 ps
CPU time 5.75 seconds
Started May 16 12:18:38 PM PDT 24
Finished May 16 12:18:46 PM PDT 24
Peak memory 200212 kb
Host smart-e7b04db8-4762-45a9-bf4e-97790ba69493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385201245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1385201245
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1816483601
Short name T75
Test name
Test status
Simulation time 16540863091 ps
CPU time 25.7 seconds
Started May 16 12:18:45 PM PDT 24
Finished May 16 12:19:15 PM PDT 24
Peak memory 217512 kb
Host smart-d5b0fe68-c804-4a3c-ba14-3b81b9b082b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816483601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1816483601
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.17793547
Short name T294
Test name
Test status
Simulation time 179117881 ps
CPU time 1.37 seconds
Started May 16 12:18:39 PM PDT 24
Finished May 16 12:18:44 PM PDT 24
Peak memory 200396 kb
Host smart-4440627b-f8df-49ed-9be3-247d07ea6ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17793547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.17793547
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2434288344
Short name T130
Test name
Test status
Simulation time 114109856 ps
CPU time 1.14 seconds
Started May 16 12:23:24 PM PDT 24
Finished May 16 12:23:31 PM PDT 24
Peak memory 198956 kb
Host smart-06464308-9098-4423-a120-1a76d5e94bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434288344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2434288344
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1138789373
Short name T452
Test name
Test status
Simulation time 1051208144 ps
CPU time 5.05 seconds
Started May 16 12:19:18 PM PDT 24
Finished May 16 12:19:25 PM PDT 24
Peak memory 208664 kb
Host smart-04da5019-6d18-4260-ad4d-7977ff82b6ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138789373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1138789373
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1689834786
Short name T171
Test name
Test status
Simulation time 406743875 ps
CPU time 2.27 seconds
Started May 16 12:23:55 PM PDT 24
Finished May 16 12:24:02 PM PDT 24
Peak memory 200008 kb
Host smart-d8f9c434-4a37-4552-b7ad-74e8aac3c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689834786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1689834786
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3485573150
Short name T403
Test name
Test status
Simulation time 240747924 ps
CPU time 1.3 seconds
Started May 16 12:24:19 PM PDT 24
Finished May 16 12:24:35 PM PDT 24
Peak memory 200288 kb
Host smart-cba91028-11aa-4e1a-983e-b897ddc46424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485573150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3485573150
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1297831091
Short name T147
Test name
Test status
Simulation time 57411207 ps
CPU time 0.86 seconds
Started May 16 12:21:15 PM PDT 24
Finished May 16 12:21:18 PM PDT 24
Peak memory 198864 kb
Host smart-726f54cc-8040-45e6-889d-271295322b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297831091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1297831091
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3317586342
Short name T54
Test name
Test status
Simulation time 1913301097 ps
CPU time 6.69 seconds
Started May 16 12:24:01 PM PDT 24
Finished May 16 12:24:12 PM PDT 24
Peak memory 221072 kb
Host smart-ee09eb6f-810e-48e2-9438-e5675f3a207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317586342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3317586342
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3535804098
Short name T450
Test name
Test status
Simulation time 244442545 ps
CPU time 1.17 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:30 PM PDT 24
Peak memory 217296 kb
Host smart-c817918e-310f-4720-83b6-aca19e25180c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535804098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3535804098
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.370055155
Short name T518
Test name
Test status
Simulation time 195486765 ps
CPU time 0.9 seconds
Started May 16 12:24:14 PM PDT 24
Finished May 16 12:24:27 PM PDT 24
Peak memory 200028 kb
Host smart-e57b733d-2092-46d7-91de-3577fbf2e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370055155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.370055155
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.561474341
Short name T293
Test name
Test status
Simulation time 1806754203 ps
CPU time 7.56 seconds
Started May 16 12:21:16 PM PDT 24
Finished May 16 12:21:25 PM PDT 24
Peak memory 200228 kb
Host smart-bdc5cc41-ba67-4ff7-933c-b05b114b49f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561474341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.561474341
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2672563664
Short name T539
Test name
Test status
Simulation time 173530856 ps
CPU time 1.25 seconds
Started May 16 12:19:34 PM PDT 24
Finished May 16 12:19:36 PM PDT 24
Peak memory 200464 kb
Host smart-e5dcf047-8e2b-4cba-b89e-f29e217dbde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672563664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2672563664
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2131935993
Short name T459
Test name
Test status
Simulation time 123497622 ps
CPU time 1.13 seconds
Started May 16 12:24:06 PM PDT 24
Finished May 16 12:24:18 PM PDT 24
Peak memory 199580 kb
Host smart-c3e26094-a6a2-4b99-95e1-ba16e5181979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131935993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2131935993
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2719029830
Short name T305
Test name
Test status
Simulation time 4190697634 ps
CPU time 18.34 seconds
Started May 16 12:22:12 PM PDT 24
Finished May 16 12:22:31 PM PDT 24
Peak memory 208988 kb
Host smart-47cfa25c-a690-41e7-8045-cc96ba1115a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719029830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2719029830
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3761766701
Short name T300
Test name
Test status
Simulation time 386192019 ps
CPU time 2.21 seconds
Started May 16 12:21:15 PM PDT 24
Finished May 16 12:21:19 PM PDT 24
Peak memory 206416 kb
Host smart-0b9e05da-2aae-4d85-bee9-3ff8d9edbc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761766701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3761766701
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2418102636
Short name T339
Test name
Test status
Simulation time 87531673 ps
CPU time 0.84 seconds
Started May 16 12:24:14 PM PDT 24
Finished May 16 12:24:28 PM PDT 24
Peak memory 199284 kb
Host smart-f69f8c77-0af5-487c-9f35-2004c5947c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418102636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2418102636
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3790903724
Short name T346
Test name
Test status
Simulation time 100696968 ps
CPU time 0.91 seconds
Started May 16 12:21:15 PM PDT 24
Finished May 16 12:21:18 PM PDT 24
Peak memory 197900 kb
Host smart-e81b6a09-8025-42f4-a81e-f0e3d7145c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790903724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3790903724
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3591637205
Short name T37
Test name
Test status
Simulation time 1234830173 ps
CPU time 6.17 seconds
Started May 16 12:24:01 PM PDT 24
Finished May 16 12:24:12 PM PDT 24
Peak memory 216580 kb
Host smart-21e553c9-3979-411c-9c6f-3ea56e94118b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591637205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3591637205
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1696388309
Short name T175
Test name
Test status
Simulation time 244701947 ps
CPU time 1.06 seconds
Started May 16 12:19:45 PM PDT 24
Finished May 16 12:19:47 PM PDT 24
Peak memory 217524 kb
Host smart-423064d7-a36c-4736-8152-eb47f39e309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696388309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1696388309
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.4170228263
Short name T500
Test name
Test status
Simulation time 126027177 ps
CPU time 0.95 seconds
Started May 16 12:19:31 PM PDT 24
Finished May 16 12:19:33 PM PDT 24
Peak memory 200236 kb
Host smart-77cf0e74-bd22-4369-ba10-5cb65254828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170228263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.4170228263
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1676811963
Short name T425
Test name
Test status
Simulation time 841922201 ps
CPU time 4.29 seconds
Started May 16 12:21:15 PM PDT 24
Finished May 16 12:21:21 PM PDT 24
Peak memory 197880 kb
Host smart-f276ff65-c97a-4381-b843-708c997eb6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676811963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1676811963
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3475603579
Short name T344
Test name
Test status
Simulation time 173998463 ps
CPU time 1.13 seconds
Started May 16 12:24:02 PM PDT 24
Finished May 16 12:24:08 PM PDT 24
Peak memory 199988 kb
Host smart-2ce7b6aa-54b0-470c-b6b9-fb1c44c211b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475603579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3475603579
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1182294956
Short name T128
Test name
Test status
Simulation time 191581250 ps
CPU time 1.46 seconds
Started May 16 12:19:37 PM PDT 24
Finished May 16 12:19:39 PM PDT 24
Peak memory 200572 kb
Host smart-f0e9897e-0d9b-47df-80ad-9294c6582b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182294956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1182294956
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.4221548331
Short name T464
Test name
Test status
Simulation time 7838476298 ps
CPU time 34.44 seconds
Started May 16 12:21:16 PM PDT 24
Finished May 16 12:21:52 PM PDT 24
Peak memory 208556 kb
Host smart-cb3086c5-8fbc-4da1-8323-f22f82a17950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221548331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4221548331
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3405683766
Short name T267
Test name
Test status
Simulation time 133237834 ps
CPU time 1.66 seconds
Started May 16 12:19:45 PM PDT 24
Finished May 16 12:19:47 PM PDT 24
Peak memory 208604 kb
Host smart-7a6cf2aa-bc37-47c9-95b5-04eb2857fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405683766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3405683766
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.866736862
Short name T493
Test name
Test status
Simulation time 123077613 ps
CPU time 1.06 seconds
Started May 16 12:21:15 PM PDT 24
Finished May 16 12:21:18 PM PDT 24
Peak memory 197688 kb
Host smart-c95a5a50-768a-4315-b330-41b7258732f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866736862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.866736862
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1763213831
Short name T476
Test name
Test status
Simulation time 75450020 ps
CPU time 0.82 seconds
Started May 16 12:20:57 PM PDT 24
Finished May 16 12:20:59 PM PDT 24
Peak memory 200384 kb
Host smart-c97a7fb9-ec79-42dd-a986-c5f6fef86493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763213831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1763213831
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3759163276
Short name T30
Test name
Test status
Simulation time 2344336286 ps
CPU time 8.39 seconds
Started May 16 12:19:44 PM PDT 24
Finished May 16 12:19:53 PM PDT 24
Peak memory 222240 kb
Host smart-67dddf0f-5095-4b1e-b7f6-426c22acfa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759163276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3759163276
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2295341884
Short name T378
Test name
Test status
Simulation time 243954470 ps
CPU time 1.05 seconds
Started May 16 12:25:17 PM PDT 24
Finished May 16 12:25:21 PM PDT 24
Peak memory 217364 kb
Host smart-f54c95bd-af1b-4920-8fd7-b88e3e2d90ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295341884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2295341884
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1397966626
Short name T255
Test name
Test status
Simulation time 230401183 ps
CPU time 0.95 seconds
Started May 16 12:22:01 PM PDT 24
Finished May 16 12:22:04 PM PDT 24
Peak memory 198648 kb
Host smart-0f300db7-bf87-432b-acf8-9e573d938df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397966626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1397966626
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3521913725
Short name T313
Test name
Test status
Simulation time 1160496430 ps
CPU time 5.34 seconds
Started May 16 12:25:16 PM PDT 24
Finished May 16 12:25:25 PM PDT 24
Peak memory 200460 kb
Host smart-d9a671ef-0c9d-45f8-a92d-b57cab254b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521913725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3521913725
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.946766965
Short name T446
Test name
Test status
Simulation time 182614942 ps
CPU time 1.23 seconds
Started May 16 12:21:15 PM PDT 24
Finished May 16 12:21:18 PM PDT 24
Peak memory 198792 kb
Host smart-b9da3eba-ac4e-43fd-8438-0c14133e8697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946766965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.946766965
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3013086467
Short name T447
Test name
Test status
Simulation time 233152708 ps
CPU time 1.45 seconds
Started May 16 12:19:44 PM PDT 24
Finished May 16 12:19:47 PM PDT 24
Peak memory 200584 kb
Host smart-c5c121ea-66bf-479f-a009-819942e468ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013086467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3013086467
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.620998056
Short name T345
Test name
Test status
Simulation time 3606100112 ps
CPU time 14.7 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:26 PM PDT 24
Peak memory 200400 kb
Host smart-fd97ceb8-38af-424c-acd8-591d8d637043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620998056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.620998056
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3297283056
Short name T231
Test name
Test status
Simulation time 137245675 ps
CPU time 1.57 seconds
Started May 16 12:21:16 PM PDT 24
Finished May 16 12:21:20 PM PDT 24
Peak memory 208272 kb
Host smart-e2cf0f7c-a457-4ed2-8a01-14eff6f9c3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297283056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3297283056
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1449273699
Short name T279
Test name
Test status
Simulation time 80408927 ps
CPU time 0.74 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:11 PM PDT 24
Peak memory 200020 kb
Host smart-f03a4588-9bf1-44af-b314-78f011ff94ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449273699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1449273699
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3107070241
Short name T164
Test name
Test status
Simulation time 70107670 ps
CPU time 0.79 seconds
Started May 16 12:24:06 PM PDT 24
Finished May 16 12:24:17 PM PDT 24
Peak memory 199072 kb
Host smart-db178be9-b1dc-4535-8e6a-290db7ddbe50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107070241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3107070241
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3544544835
Short name T207
Test name
Test status
Simulation time 2386919347 ps
CPU time 8.09 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:37 PM PDT 24
Peak memory 229952 kb
Host smart-4c788023-feb8-42fe-bcec-c383cf579428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544544835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3544544835
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3895337157
Short name T465
Test name
Test status
Simulation time 244250964 ps
CPU time 1.22 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:31 PM PDT 24
Peak memory 215936 kb
Host smart-900edec6-6810-4430-9216-3e1053aa0865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895337157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3895337157
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.4209064149
Short name T288
Test name
Test status
Simulation time 137532909 ps
CPU time 0.87 seconds
Started May 16 12:21:25 PM PDT 24
Finished May 16 12:21:27 PM PDT 24
Peak memory 196768 kb
Host smart-c8f2fc8f-99b7-4e5b-8259-09e0229038bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209064149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.4209064149
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2155713334
Short name T179
Test name
Test status
Simulation time 1443671073 ps
CPU time 6.13 seconds
Started May 16 12:21:26 PM PDT 24
Finished May 16 12:21:34 PM PDT 24
Peak memory 200252 kb
Host smart-8e73fcb9-9e32-4e96-8f30-0f6bb20c91dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155713334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2155713334
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3607465315
Short name T180
Test name
Test status
Simulation time 188905396 ps
CPU time 1.26 seconds
Started May 16 12:20:04 PM PDT 24
Finished May 16 12:20:06 PM PDT 24
Peak memory 200464 kb
Host smart-fe384e0b-5d18-4d92-a0ce-34090d5f29e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607465315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3607465315
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.4293630942
Short name T292
Test name
Test status
Simulation time 115941388 ps
CPU time 1.28 seconds
Started May 16 12:21:25 PM PDT 24
Finished May 16 12:21:28 PM PDT 24
Peak memory 197676 kb
Host smart-b2776ad6-6217-4c4c-a53e-de9568409e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293630942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4293630942
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1608649747
Short name T89
Test name
Test status
Simulation time 3889594278 ps
CPU time 16.73 seconds
Started May 16 12:24:17 PM PDT 24
Finished May 16 12:24:47 PM PDT 24
Peak memory 216580 kb
Host smart-62c69b99-251d-4710-b23e-a754d052c097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608649747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1608649747
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2819001391
Short name T230
Test name
Test status
Simulation time 324871681 ps
CPU time 2.06 seconds
Started May 16 12:21:26 PM PDT 24
Finished May 16 12:21:30 PM PDT 24
Peak memory 200092 kb
Host smart-c2c276a3-5d19-47dd-ac96-f2973382e8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819001391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2819001391
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1164945237
Short name T252
Test name
Test status
Simulation time 75115549 ps
CPU time 0.87 seconds
Started May 16 12:20:32 PM PDT 24
Finished May 16 12:20:33 PM PDT 24
Peak memory 200492 kb
Host smart-e311a7fe-3cca-460e-88b5-f55b18e94ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164945237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1164945237
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1878622428
Short name T508
Test name
Test status
Simulation time 118035283 ps
CPU time 0.86 seconds
Started May 16 12:24:02 PM PDT 24
Finished May 16 12:24:09 PM PDT 24
Peak memory 200024 kb
Host smart-8bff55d6-e58e-43fb-a70a-54e331f7173a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878622428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1878622428
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.84189601
Short name T432
Test name
Test status
Simulation time 1897749648 ps
CPU time 7.28 seconds
Started May 16 12:20:11 PM PDT 24
Finished May 16 12:20:20 PM PDT 24
Peak memory 217512 kb
Host smart-201f13bf-5f07-41ad-b1d6-ad3e5256ff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84189601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.84189601
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1502316954
Short name T371
Test name
Test status
Simulation time 244500274 ps
CPU time 1.09 seconds
Started May 16 12:24:01 PM PDT 24
Finished May 16 12:24:07 PM PDT 24
Peak memory 216664 kb
Host smart-5e976818-71d6-4351-abf9-ee86f1e80aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502316954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1502316954
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1943293217
Short name T439
Test name
Test status
Simulation time 90897695 ps
CPU time 0.75 seconds
Started May 16 12:22:49 PM PDT 24
Finished May 16 12:22:50 PM PDT 24
Peak memory 200240 kb
Host smart-3547c350-b564-4e0b-a37c-55bb039068dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943293217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1943293217
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3826861387
Short name T46
Test name
Test status
Simulation time 1792716535 ps
CPU time 6.14 seconds
Started May 16 12:25:13 PM PDT 24
Finished May 16 12:25:23 PM PDT 24
Peak memory 200460 kb
Host smart-6ccfb5ad-e30f-4459-bff6-537bf4925533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826861387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3826861387
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2228907530
Short name T424
Test name
Test status
Simulation time 178788119 ps
CPU time 1.17 seconds
Started May 16 12:25:16 PM PDT 24
Finished May 16 12:25:20 PM PDT 24
Peak memory 200276 kb
Host smart-f3185078-7395-463f-80e2-091e90fb0414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228907530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2228907530
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2444478592
Short name T453
Test name
Test status
Simulation time 258367810 ps
CPU time 1.47 seconds
Started May 16 12:22:42 PM PDT 24
Finished May 16 12:22:44 PM PDT 24
Peak memory 200752 kb
Host smart-f1eafd6a-b8d7-4dff-9d86-255de147b3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444478592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2444478592
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.4081548891
Short name T96
Test name
Test status
Simulation time 5663036269 ps
CPU time 24.12 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:54 PM PDT 24
Peak memory 199236 kb
Host smart-7d369bde-4b41-4e63-bff3-4ca542327373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081548891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.4081548891
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2005557614
Short name T4
Test name
Test status
Simulation time 333576180 ps
CPU time 1.97 seconds
Started May 16 12:22:49 PM PDT 24
Finished May 16 12:22:53 PM PDT 24
Peak memory 200408 kb
Host smart-464a429d-5c7c-40fe-9193-4785acb81623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005557614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2005557614
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.4105545399
Short name T467
Test name
Test status
Simulation time 175702754 ps
CPU time 1.2 seconds
Started May 16 12:24:58 PM PDT 24
Finished May 16 12:25:11 PM PDT 24
Peak memory 199504 kb
Host smart-27d0c3ab-083e-4e79-b147-438ec92b0ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105545399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.4105545399
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1473864563
Short name T515
Test name
Test status
Simulation time 1890761123 ps
CPU time 7.12 seconds
Started May 16 12:25:09 PM PDT 24
Finished May 16 12:25:22 PM PDT 24
Peak memory 216812 kb
Host smart-29edf89e-aaa6-4dff-bd0e-5347d67817e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473864563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1473864563
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.856692138
Short name T387
Test name
Test status
Simulation time 245416669 ps
CPU time 1 seconds
Started May 16 12:25:13 PM PDT 24
Finished May 16 12:25:18 PM PDT 24
Peak memory 217340 kb
Host smart-6ae8a4cf-d866-45ca-889e-33dbf3a30fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856692138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.856692138
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2454982617
Short name T12
Test name
Test status
Simulation time 167994081 ps
CPU time 0.83 seconds
Started May 16 12:22:04 PM PDT 24
Finished May 16 12:22:06 PM PDT 24
Peak memory 200160 kb
Host smart-6ba7c6db-325a-4eb8-8ba0-43a42a2e6e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454982617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2454982617
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.679632602
Short name T121
Test name
Test status
Simulation time 1701217868 ps
CPU time 7.06 seconds
Started May 16 12:20:30 PM PDT 24
Finished May 16 12:20:38 PM PDT 24
Peak memory 200692 kb
Host smart-2b39d5ab-ee84-4330-b393-b6432baf2d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679632602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.679632602
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3515459313
Short name T512
Test name
Test status
Simulation time 99526451 ps
CPU time 0.99 seconds
Started May 16 12:21:59 PM PDT 24
Finished May 16 12:22:01 PM PDT 24
Peak memory 200408 kb
Host smart-a95a7fcf-f2b4-4d0f-97d2-89d84ce49424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515459313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3515459313
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2393452930
Short name T271
Test name
Test status
Simulation time 253689847 ps
CPU time 1.44 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:31 PM PDT 24
Peak memory 199980 kb
Host smart-216441c5-2ea1-4d60-bcf1-7329e2a95af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393452930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2393452930
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2284791136
Short name T281
Test name
Test status
Simulation time 303232435 ps
CPU time 2.05 seconds
Started May 16 12:25:08 PM PDT 24
Finished May 16 12:25:16 PM PDT 24
Peak memory 200348 kb
Host smart-71a936d0-ffa4-4762-b600-3aa83ae81b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284791136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2284791136
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.306591129
Short name T470
Test name
Test status
Simulation time 433700832 ps
CPU time 2.35 seconds
Started May 16 12:22:04 PM PDT 24
Finished May 16 12:22:07 PM PDT 24
Peak memory 208760 kb
Host smart-602fddea-eb7a-4fc3-aa84-33ac203f8f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306591129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.306591129
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.194009190
Short name T316
Test name
Test status
Simulation time 146651512 ps
CPU time 0.99 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:12 PM PDT 24
Peak memory 200180 kb
Host smart-1ab32f57-36ae-4892-bdd4-76c36398258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194009190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.194009190
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.800701661
Short name T56
Test name
Test status
Simulation time 87156941 ps
CPU time 0.84 seconds
Started May 16 12:22:50 PM PDT 24
Finished May 16 12:22:52 PM PDT 24
Peak memory 200180 kb
Host smart-724f01b4-e4a0-4df7-ade1-bbfadf26f0b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800701661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.800701661
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2677606214
Short name T38
Test name
Test status
Simulation time 1910632183 ps
CPU time 7.64 seconds
Started May 16 12:24:31 PM PDT 24
Finished May 16 12:24:56 PM PDT 24
Peak memory 221640 kb
Host smart-0f890f4d-e9b5-400d-9bd8-5b242fbced9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677606214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2677606214
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.770345147
Short name T486
Test name
Test status
Simulation time 243946584 ps
CPU time 1 seconds
Started May 16 12:23:56 PM PDT 24
Finished May 16 12:24:01 PM PDT 24
Peak memory 217328 kb
Host smart-db1de6ac-1cab-4724-87e6-2961f88bdc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770345147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.770345147
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1800941811
Short name T285
Test name
Test status
Simulation time 165745779 ps
CPU time 0.88 seconds
Started May 16 12:25:08 PM PDT 24
Finished May 16 12:25:15 PM PDT 24
Peak memory 199768 kb
Host smart-6a6807ff-c17f-486b-90da-f3ca8303c88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800941811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1800941811
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1367722360
Short name T365
Test name
Test status
Simulation time 928547041 ps
CPU time 4.75 seconds
Started May 16 12:23:46 PM PDT 24
Finished May 16 12:23:55 PM PDT 24
Peak memory 199012 kb
Host smart-dd6c9b73-9c0e-4681-9bd7-6414c8a2be78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367722360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1367722360
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3743981240
Short name T413
Test name
Test status
Simulation time 183982555 ps
CPU time 1.38 seconds
Started May 16 12:23:08 PM PDT 24
Finished May 16 12:23:10 PM PDT 24
Peak memory 200568 kb
Host smart-b593aa29-e70d-472f-8451-fcfb2b541a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743981240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3743981240
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2471388955
Short name T290
Test name
Test status
Simulation time 108155127 ps
CPU time 1.11 seconds
Started May 16 12:25:04 PM PDT 24
Finished May 16 12:25:14 PM PDT 24
Peak memory 200316 kb
Host smart-299df1f8-6719-4b0c-aca9-fa1d77f7dfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471388955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2471388955
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.519410983
Short name T383
Test name
Test status
Simulation time 2029348169 ps
CPU time 8.72 seconds
Started May 16 12:22:22 PM PDT 24
Finished May 16 12:22:32 PM PDT 24
Peak memory 200524 kb
Host smart-7407fd0c-9e06-491d-ad10-603b7e9dc24e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519410983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.519410983
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3917025899
Short name T154
Test name
Test status
Simulation time 322416954 ps
CPU time 1.96 seconds
Started May 16 12:20:21 PM PDT 24
Finished May 16 12:20:24 PM PDT 24
Peak memory 200380 kb
Host smart-3d0dcb09-403d-4873-9fa5-dd673ee9136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917025899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3917025899
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2868735867
Short name T306
Test name
Test status
Simulation time 60081338 ps
CPU time 0.81 seconds
Started May 16 12:20:30 PM PDT 24
Finished May 16 12:20:32 PM PDT 24
Peak memory 200404 kb
Host smart-4da9a214-4b58-4a91-b474-192ea58ad515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868735867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2868735867
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.382750053
Short name T173
Test name
Test status
Simulation time 60831044 ps
CPU time 0.78 seconds
Started May 16 12:22:11 PM PDT 24
Finished May 16 12:22:12 PM PDT 24
Peak memory 200292 kb
Host smart-982b672d-3ac4-4564-9917-b67ddb6a6574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382750053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.382750053
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2497428763
Short name T8
Test name
Test status
Simulation time 244704064 ps
CPU time 1.02 seconds
Started May 16 12:24:31 PM PDT 24
Finished May 16 12:24:50 PM PDT 24
Peak memory 217480 kb
Host smart-a506207a-7f16-4135-8f2d-83cb96835118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497428763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2497428763
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2334146327
Short name T22
Test name
Test status
Simulation time 200416455 ps
CPU time 0.97 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:50 PM PDT 24
Peak memory 197996 kb
Host smart-f7f101fc-840b-492e-89ff-a7db61ac1e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334146327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2334146327
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2216824239
Short name T328
Test name
Test status
Simulation time 1587468448 ps
CPU time 5.69 seconds
Started May 16 12:21:43 PM PDT 24
Finished May 16 12:21:50 PM PDT 24
Peak memory 200592 kb
Host smart-5e1603c2-9403-41ac-bf93-161ca7bb1e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216824239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2216824239
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.883616206
Short name T526
Test name
Test status
Simulation time 114448548 ps
CPU time 0.97 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:10 PM PDT 24
Peak memory 200332 kb
Host smart-c112413b-5efa-411c-8636-3749ef0e41f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883616206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.883616206
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3635884274
Short name T517
Test name
Test status
Simulation time 252150920 ps
CPU time 1.64 seconds
Started May 16 12:20:39 PM PDT 24
Finished May 16 12:20:41 PM PDT 24
Peak memory 200664 kb
Host smart-5351f5a9-dd61-4a4e-a4bf-1dfc33afc1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635884274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3635884274
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.885799480
Short name T427
Test name
Test status
Simulation time 1722171780 ps
CPU time 6.15 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:18 PM PDT 24
Peak memory 199708 kb
Host smart-be01a5c4-f308-4bde-8b5d-52e4a2839c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885799480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.885799480
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.4175724250
Short name T419
Test name
Test status
Simulation time 144122612 ps
CPU time 1.79 seconds
Started May 16 12:21:43 PM PDT 24
Finished May 16 12:21:45 PM PDT 24
Peak memory 200452 kb
Host smart-0d8c8752-f349-4153-add9-2c0991ab902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175724250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4175724250
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3455268211
Short name T298
Test name
Test status
Simulation time 165613600 ps
CPU time 1.18 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:14 PM PDT 24
Peak memory 200128 kb
Host smart-3becb412-e8a6-4d2c-b393-c0ecb00044d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455268211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3455268211
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4253127490
Short name T295
Test name
Test status
Simulation time 63997029 ps
CPU time 0.77 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 199672 kb
Host smart-2b6381a1-3b56-492a-b935-aa96b6006350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253127490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4253127490
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.304266849
Short name T406
Test name
Test status
Simulation time 1223285491 ps
CPU time 5.43 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:23:56 PM PDT 24
Peak memory 217112 kb
Host smart-0d60ac9d-5d6d-4f3f-8f96-004fd2569f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304266849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.304266849
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.852813796
Short name T412
Test name
Test status
Simulation time 244067390 ps
CPU time 1.1 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:12 PM PDT 24
Peak memory 216660 kb
Host smart-f8452cff-0908-435e-abce-e89d39a08731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852813796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.852813796
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1041204805
Short name T496
Test name
Test status
Simulation time 95948891 ps
CPU time 0.79 seconds
Started May 16 12:24:19 PM PDT 24
Finished May 16 12:24:35 PM PDT 24
Peak memory 199908 kb
Host smart-01196657-8119-44f4-a2e0-37f442e2e5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041204805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1041204805
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.502801460
Short name T146
Test name
Test status
Simulation time 818702058 ps
CPU time 4.46 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:18 PM PDT 24
Peak memory 200412 kb
Host smart-82bf44e3-dff6-4733-99b0-171203e4b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502801460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.502801460
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.646848419
Short name T249
Test name
Test status
Simulation time 145242531 ps
CPU time 1.16 seconds
Started May 16 12:20:45 PM PDT 24
Finished May 16 12:20:47 PM PDT 24
Peak memory 200568 kb
Host smart-8e36d3e2-8a3c-453a-90e8-861362a076ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646848419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.646848419
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3159716414
Short name T210
Test name
Test status
Simulation time 261121226 ps
CPU time 1.49 seconds
Started May 16 12:24:11 PM PDT 24
Finished May 16 12:24:25 PM PDT 24
Peak memory 199620 kb
Host smart-3d609885-a37c-45eb-abe1-53a8f34e8a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159716414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3159716414
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1988904346
Short name T462
Test name
Test status
Simulation time 1615047280 ps
CPU time 5.62 seconds
Started May 16 12:24:05 PM PDT 24
Finished May 16 12:24:20 PM PDT 24
Peak memory 200432 kb
Host smart-b9669c7b-9cae-46d2-af48-89a402f2b114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988904346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1988904346
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3685820731
Short name T124
Test name
Test status
Simulation time 359197380 ps
CPU time 2.02 seconds
Started May 16 12:20:56 PM PDT 24
Finished May 16 12:20:59 PM PDT 24
Peak memory 200440 kb
Host smart-31796720-a58b-4b71-b100-60aef3c59e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685820731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3685820731
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1756556735
Short name T86
Test name
Test status
Simulation time 116939597 ps
CPU time 1.04 seconds
Started May 16 12:23:46 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 198912 kb
Host smart-0897c99c-c933-4ce5-9629-0fd8cc767ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756556735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1756556735
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.115524565
Short name T409
Test name
Test status
Simulation time 70858564 ps
CPU time 0.76 seconds
Started May 16 12:23:54 PM PDT 24
Finished May 16 12:23:58 PM PDT 24
Peak memory 200192 kb
Host smart-8eb52e09-c634-4812-b79b-7cda0a871999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115524565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.115524565
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1425569618
Short name T260
Test name
Test status
Simulation time 2359342529 ps
CPU time 8.48 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:54 PM PDT 24
Peak memory 216500 kb
Host smart-42ba53c1-94e2-466e-84a1-0d4a15d13642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425569618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1425569618
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3193757557
Short name T348
Test name
Test status
Simulation time 244773603 ps
CPU time 1.08 seconds
Started May 16 12:20:55 PM PDT 24
Finished May 16 12:20:56 PM PDT 24
Peak memory 217628 kb
Host smart-128438b1-e165-45b5-9182-d5b279517f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193757557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3193757557
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.513746258
Short name T317
Test name
Test status
Simulation time 190990980 ps
CPU time 0.9 seconds
Started May 16 12:23:46 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 199296 kb
Host smart-24d111e5-1476-4d6d-810f-6750cccb416c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513746258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.513746258
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.903634688
Short name T394
Test name
Test status
Simulation time 940085770 ps
CPU time 4.81 seconds
Started May 16 12:20:47 PM PDT 24
Finished May 16 12:20:53 PM PDT 24
Peak memory 200712 kb
Host smart-396519d6-6b8a-4ad3-b6b7-693587318e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903634688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.903634688
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2296821010
Short name T44
Test name
Test status
Simulation time 104647423 ps
CPU time 1.03 seconds
Started May 16 12:21:39 PM PDT 24
Finished May 16 12:21:41 PM PDT 24
Peak memory 200332 kb
Host smart-0d69e9f8-8f2d-4ee5-81ab-b602bfcdbd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296821010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2296821010
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1183007657
Short name T506
Test name
Test status
Simulation time 200874183 ps
CPU time 1.31 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:13 PM PDT 24
Peak memory 200268 kb
Host smart-33c31034-2af7-468d-b7f6-cfd31c8aa6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183007657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1183007657
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3764634561
Short name T47
Test name
Test status
Simulation time 8616219080 ps
CPU time 37.25 seconds
Started May 16 12:21:25 PM PDT 24
Finished May 16 12:22:04 PM PDT 24
Peak memory 210632 kb
Host smart-79cbb2e1-e8a3-4101-9806-dd0e416c9e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764634561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3764634561
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.4048318064
Short name T362
Test name
Test status
Simulation time 146873914 ps
CPU time 1.79 seconds
Started May 16 12:24:05 PM PDT 24
Finished May 16 12:24:17 PM PDT 24
Peak memory 200176 kb
Host smart-61600c71-a253-4372-91d7-89747c66c32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048318064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.4048318064
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1598637688
Short name T354
Test name
Test status
Simulation time 101820764 ps
CPU time 0.96 seconds
Started May 16 12:24:05 PM PDT 24
Finished May 16 12:24:16 PM PDT 24
Peak memory 200184 kb
Host smart-f9ba90f6-acd7-4022-bf16-c713a4f26dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598637688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1598637688
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2444023105
Short name T489
Test name
Test status
Simulation time 63901701 ps
CPU time 0.74 seconds
Started May 16 12:23:55 PM PDT 24
Finished May 16 12:24:00 PM PDT 24
Peak memory 199600 kb
Host smart-1f0d2e30-6d8c-4dd9-9b06-c7b772dfd510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444023105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2444023105
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.174573078
Short name T60
Test name
Test status
Simulation time 1229865746 ps
CPU time 5.85 seconds
Started May 16 12:18:43 PM PDT 24
Finished May 16 12:18:53 PM PDT 24
Peak memory 216048 kb
Host smart-3487fded-6513-454e-86a5-454dda53d173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174573078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.174573078
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1270200412
Short name T278
Test name
Test status
Simulation time 249398221 ps
CPU time 1 seconds
Started May 16 12:18:44 PM PDT 24
Finished May 16 12:18:48 PM PDT 24
Peak memory 217492 kb
Host smart-1c836c1d-8269-4819-8337-cd45208327e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270200412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1270200412
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.768087560
Short name T6
Test name
Test status
Simulation time 122945472 ps
CPU time 0.81 seconds
Started May 16 12:23:25 PM PDT 24
Finished May 16 12:23:31 PM PDT 24
Peak memory 199704 kb
Host smart-96885e45-d3c4-4152-bdc8-bb376865b8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768087560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.768087560
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2556134599
Short name T315
Test name
Test status
Simulation time 1371508620 ps
CPU time 5.94 seconds
Started May 16 12:18:39 PM PDT 24
Finished May 16 12:18:48 PM PDT 24
Peak memory 200728 kb
Host smart-37a3a891-9dff-410d-ae86-d6c0ba00bf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556134599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2556134599
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.530958035
Short name T455
Test name
Test status
Simulation time 169829019 ps
CPU time 1.18 seconds
Started May 16 12:18:53 PM PDT 24
Finished May 16 12:18:56 PM PDT 24
Peak memory 200172 kb
Host smart-7e2f2d07-a50a-4e60-9ecf-70ffa0eb8bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530958035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.530958035
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2394387794
Short name T215
Test name
Test status
Simulation time 202696395 ps
CPU time 1.38 seconds
Started May 16 12:18:39 PM PDT 24
Finished May 16 12:18:43 PM PDT 24
Peak memory 200724 kb
Host smart-567d9cbc-d868-404a-b349-4bcea3b80882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394387794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2394387794
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.455689702
Short name T479
Test name
Test status
Simulation time 7302754908 ps
CPU time 26.26 seconds
Started May 16 12:23:56 PM PDT 24
Finished May 16 12:24:27 PM PDT 24
Peak memory 208752 kb
Host smart-f14af769-a683-46ab-b142-fb78988cb379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455689702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.455689702
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1196220211
Short name T282
Test name
Test status
Simulation time 534070777 ps
CPU time 2.59 seconds
Started May 16 12:23:57 PM PDT 24
Finished May 16 12:24:03 PM PDT 24
Peak memory 200176 kb
Host smart-04a8b501-e348-4986-9614-09729642a9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196220211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1196220211
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3903093307
Short name T238
Test name
Test status
Simulation time 211149844 ps
CPU time 1.29 seconds
Started May 16 12:19:18 PM PDT 24
Finished May 16 12:19:21 PM PDT 24
Peak memory 200284 kb
Host smart-024bed88-fcac-46ad-9a2a-e0ae3be4a553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903093307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3903093307
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1498782340
Short name T277
Test name
Test status
Simulation time 62909768 ps
CPU time 0.8 seconds
Started May 16 12:20:57 PM PDT 24
Finished May 16 12:20:59 PM PDT 24
Peak memory 200240 kb
Host smart-5c4df80c-0081-4830-a507-2befc8be0ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498782340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1498782340
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1253402742
Short name T472
Test name
Test status
Simulation time 1884788410 ps
CPU time 7.56 seconds
Started May 16 12:23:24 PM PDT 24
Finished May 16 12:23:37 PM PDT 24
Peak memory 217840 kb
Host smart-1b2127de-d935-4485-bdd3-f11c30744e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253402742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1253402742
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3113619976
Short name T228
Test name
Test status
Simulation time 244072607 ps
CPU time 1.05 seconds
Started May 16 12:23:22 PM PDT 24
Finished May 16 12:23:29 PM PDT 24
Peak memory 216900 kb
Host smart-f215833a-0699-413c-ba35-4f1d4974fda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113619976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3113619976
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.490171283
Short name T23
Test name
Test status
Simulation time 200440365 ps
CPU time 0.88 seconds
Started May 16 12:23:22 PM PDT 24
Finished May 16 12:23:29 PM PDT 24
Peak memory 199400 kb
Host smart-1ae445f9-6b94-4ee8-b400-378b19b30883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490171283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.490171283
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1051574422
Short name T522
Test name
Test status
Simulation time 1669300824 ps
CPU time 6.82 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:35 PM PDT 24
Peak memory 198296 kb
Host smart-acf4c686-656b-43cf-980c-97c103e375bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051574422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1051574422
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3363228204
Short name T428
Test name
Test status
Simulation time 97154652 ps
CPU time 1.03 seconds
Started May 16 12:22:44 PM PDT 24
Finished May 16 12:22:47 PM PDT 24
Peak memory 200408 kb
Host smart-b8b5f4f6-c753-4ed1-a466-65bef0cd186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363228204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3363228204
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2857938633
Short name T254
Test name
Test status
Simulation time 192700311 ps
CPU time 1.34 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:14 PM PDT 24
Peak memory 200412 kb
Host smart-298d54ae-01d2-41f9-86bd-fa13a3c0d39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857938633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2857938633
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.498052315
Short name T380
Test name
Test status
Simulation time 6312115074 ps
CPU time 20.56 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:49 PM PDT 24
Peak memory 200020 kb
Host smart-b4357e21-68d3-40b8-80cb-8c0a8b4631db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498052315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.498052315
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2253800098
Short name T199
Test name
Test status
Simulation time 262699420 ps
CPU time 1.71 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:31 PM PDT 24
Peak memory 199964 kb
Host smart-4388292b-6b2b-473f-823f-3a7223105380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253800098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2253800098
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.424593724
Short name T478
Test name
Test status
Simulation time 60404135 ps
CPU time 0.71 seconds
Started May 16 12:24:14 PM PDT 24
Finished May 16 12:24:27 PM PDT 24
Peak memory 200212 kb
Host smart-00011556-5abc-42d2-89d4-351d478c99ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424593724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.424593724
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2051107392
Short name T209
Test name
Test status
Simulation time 57493562 ps
CPU time 0.81 seconds
Started May 16 12:22:44 PM PDT 24
Finished May 16 12:22:46 PM PDT 24
Peak memory 200284 kb
Host smart-af01075f-dcf2-4365-ab86-c52e57a1c20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051107392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2051107392
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2564500317
Short name T379
Test name
Test status
Simulation time 2358542514 ps
CPU time 8.61 seconds
Started May 16 12:21:09 PM PDT 24
Finished May 16 12:21:18 PM PDT 24
Peak memory 218068 kb
Host smart-e36168f9-8d9a-419a-abea-a2906368e981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564500317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2564500317
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1922539072
Short name T18
Test name
Test status
Simulation time 244406003 ps
CPU time 1.2 seconds
Started May 16 12:21:16 PM PDT 24
Finished May 16 12:21:18 PM PDT 24
Peak memory 217704 kb
Host smart-546509b3-48e0-47ae-ac73-98e815eaa24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922539072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1922539072
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3343810634
Short name T307
Test name
Test status
Simulation time 130164539 ps
CPU time 0.78 seconds
Started May 16 12:22:13 PM PDT 24
Finished May 16 12:22:15 PM PDT 24
Peak memory 200156 kb
Host smart-a6bbf01f-fd94-4714-a60e-f03ef4fd7aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343810634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3343810634
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.368760227
Short name T301
Test name
Test status
Simulation time 1755581822 ps
CPU time 5.78 seconds
Started May 16 12:22:48 PM PDT 24
Finished May 16 12:22:55 PM PDT 24
Peak memory 200272 kb
Host smart-e7e91a49-5279-465f-8b1d-b9e88a1a3c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368760227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.368760227
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3212839686
Short name T397
Test name
Test status
Simulation time 139289447 ps
CPU time 1.11 seconds
Started May 16 12:22:26 PM PDT 24
Finished May 16 12:22:29 PM PDT 24
Peak memory 200460 kb
Host smart-b316334b-d229-4134-89af-90fc3710620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212839686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3212839686
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.984546507
Short name T303
Test name
Test status
Simulation time 111328610 ps
CPU time 1.11 seconds
Started May 16 12:23:24 PM PDT 24
Finished May 16 12:23:31 PM PDT 24
Peak memory 200352 kb
Host smart-1873dc2e-9f51-43df-8b32-f0ef5c10e538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984546507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.984546507
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.4022918684
Short name T373
Test name
Test status
Simulation time 7493375210 ps
CPU time 25.21 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:54 PM PDT 24
Peak memory 208672 kb
Host smart-533a699b-7176-413a-9372-442b96306e41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022918684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4022918684
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.731170683
Short name T168
Test name
Test status
Simulation time 288242335 ps
CPU time 2.02 seconds
Started May 16 12:24:14 PM PDT 24
Finished May 16 12:24:30 PM PDT 24
Peak memory 207316 kb
Host smart-f4837252-6aa0-4e9a-a467-ddb940155e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731170683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.731170683
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2180306415
Short name T311
Test name
Test status
Simulation time 128697960 ps
CPU time 1.13 seconds
Started May 16 12:24:14 PM PDT 24
Finished May 16 12:24:29 PM PDT 24
Peak memory 199268 kb
Host smart-ab81c218-d00a-4438-baa1-a1628ca38844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180306415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2180306415
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.739812702
Short name T77
Test name
Test status
Simulation time 73606781 ps
CPU time 0.77 seconds
Started May 16 12:22:26 PM PDT 24
Finished May 16 12:22:28 PM PDT 24
Peak memory 200180 kb
Host smart-e95e6503-e3a2-4c59-99bc-1ff1db5e841b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739812702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.739812702
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1652083324
Short name T59
Test name
Test status
Simulation time 1883747724 ps
CPU time 7.01 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:36 PM PDT 24
Peak memory 216816 kb
Host smart-8364715f-a49e-4b9d-9a3c-b9631cd750cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652083324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1652083324
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.145489424
Short name T350
Test name
Test status
Simulation time 244532661 ps
CPU time 1.03 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:31 PM PDT 24
Peak memory 217332 kb
Host smart-b4d3d4b3-c7bc-4c86-ba64-4a727645c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145489424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.145489424
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2004181290
Short name T417
Test name
Test status
Simulation time 84739564 ps
CPU time 0.74 seconds
Started May 16 12:21:21 PM PDT 24
Finished May 16 12:21:23 PM PDT 24
Peak memory 200236 kb
Host smart-bdf8ba12-b365-45f7-adad-6546ae1d0e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004181290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2004181290
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1543431006
Short name T123
Test name
Test status
Simulation time 1529166706 ps
CPU time 5.62 seconds
Started May 16 12:24:07 PM PDT 24
Finished May 16 12:24:24 PM PDT 24
Peak memory 199872 kb
Host smart-d4a46d28-2f93-4c45-912d-e2bf2ed5b99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543431006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1543431006
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.961117807
Short name T434
Test name
Test status
Simulation time 170778857 ps
CPU time 1.1 seconds
Started May 16 12:24:04 PM PDT 24
Finished May 16 12:24:15 PM PDT 24
Peak memory 200012 kb
Host smart-f48dc0e2-fff1-442e-9b40-444e39f42884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961117807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.961117807
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2996667170
Short name T390
Test name
Test status
Simulation time 250987895 ps
CPU time 1.61 seconds
Started May 16 12:23:57 PM PDT 24
Finished May 16 12:24:03 PM PDT 24
Peak memory 200436 kb
Host smart-90d27848-743d-4c27-8057-e22d5a1785ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996667170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2996667170
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.514047375
Short name T263
Test name
Test status
Simulation time 10871276811 ps
CPU time 34.44 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:25:03 PM PDT 24
Peak memory 200472 kb
Host smart-77fb8f67-da9f-46e9-bcdb-2c97e30fc2d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514047375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.514047375
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4202190490
Short name T9
Test name
Test status
Simulation time 269200185 ps
CPU time 1.9 seconds
Started May 16 12:21:11 PM PDT 24
Finished May 16 12:21:14 PM PDT 24
Peak memory 200456 kb
Host smart-e899d212-b33b-4912-bad5-7e999c1939a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202190490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4202190490
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.661075829
Short name T520
Test name
Test status
Simulation time 97738981 ps
CPU time 0.92 seconds
Started May 16 12:23:57 PM PDT 24
Finished May 16 12:24:02 PM PDT 24
Peak memory 200248 kb
Host smart-10281541-b884-4993-ab50-d0c6b26f79d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661075829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.661075829
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1838252992
Short name T162
Test name
Test status
Simulation time 81649183 ps
CPU time 0.78 seconds
Started May 16 12:23:15 PM PDT 24
Finished May 16 12:23:18 PM PDT 24
Peak memory 199808 kb
Host smart-6a22c14e-9b53-4f23-8f21-08492ed0a26c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838252992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1838252992
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3284124927
Short name T521
Test name
Test status
Simulation time 2373468632 ps
CPU time 7.92 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:23:59 PM PDT 24
Peak memory 217884 kb
Host smart-047772af-87e0-4dc7-9626-97c124697e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284124927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3284124927
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3055081549
Short name T133
Test name
Test status
Simulation time 243873684 ps
CPU time 1.07 seconds
Started May 16 12:23:20 PM PDT 24
Finished May 16 12:23:25 PM PDT 24
Peak memory 217268 kb
Host smart-e3d4cb3c-435d-4761-a831-8fdf6a7b1cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055081549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3055081549
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3968208986
Short name T473
Test name
Test status
Simulation time 87196021 ps
CPU time 0.77 seconds
Started May 16 12:22:20 PM PDT 24
Finished May 16 12:22:21 PM PDT 24
Peak memory 200212 kb
Host smart-3cade97e-ead4-4650-a09e-f9cd35da94a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968208986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3968208986
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.613159015
Short name T28
Test name
Test status
Simulation time 1451718342 ps
CPU time 5.72 seconds
Started May 16 12:21:21 PM PDT 24
Finished May 16 12:21:28 PM PDT 24
Peak memory 200692 kb
Host smart-ef03504e-c9e3-4057-abc1-9a79eb39684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613159015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.613159015
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.4219934707
Short name T172
Test name
Test status
Simulation time 167374372 ps
CPU time 1.13 seconds
Started May 16 12:23:19 PM PDT 24
Finished May 16 12:23:24 PM PDT 24
Peak memory 200148 kb
Host smart-2dc3af9d-1ed2-43de-90a1-f434337c0f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219934707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.4219934707
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3605578157
Short name T482
Test name
Test status
Simulation time 121359204 ps
CPU time 1.18 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:31 PM PDT 24
Peak memory 200408 kb
Host smart-ee5940b2-9abe-413e-acdc-64c6b56c16d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605578157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3605578157
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3374347774
Short name T201
Test name
Test status
Simulation time 5074739479 ps
CPU time 18.34 seconds
Started May 16 12:22:14 PM PDT 24
Finished May 16 12:22:33 PM PDT 24
Peak memory 210528 kb
Host smart-07527106-c2e5-43a0-85b5-71b9ac6f1671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374347774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3374347774
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2413250059
Short name T507
Test name
Test status
Simulation time 139041906 ps
CPU time 1.73 seconds
Started May 16 12:21:21 PM PDT 24
Finished May 16 12:21:24 PM PDT 24
Peak memory 208636 kb
Host smart-7c5d7c1a-e173-4d51-a47b-b4a360ed40e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413250059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2413250059
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1376876515
Short name T322
Test name
Test status
Simulation time 88915093 ps
CPU time 0.85 seconds
Started May 16 12:21:21 PM PDT 24
Finished May 16 12:21:23 PM PDT 24
Peak memory 200484 kb
Host smart-cf807546-6a82-4ad7-a0c6-b0e9921720d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376876515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1376876515
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2590263104
Short name T256
Test name
Test status
Simulation time 70988530 ps
CPU time 0.81 seconds
Started May 16 12:21:24 PM PDT 24
Finished May 16 12:21:25 PM PDT 24
Peak memory 200280 kb
Host smart-a03eb67c-ffcc-41da-9656-728b4d93634b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590263104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2590263104
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3821240297
Short name T343
Test name
Test status
Simulation time 2348630053 ps
CPU time 8.64 seconds
Started May 16 12:23:53 PM PDT 24
Finished May 16 12:24:05 PM PDT 24
Peak memory 217404 kb
Host smart-3053e5ba-da81-4252-834e-fea5c7e0a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821240297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3821240297
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3075144719
Short name T29
Test name
Test status
Simulation time 244492671 ps
CPU time 1.06 seconds
Started May 16 12:23:53 PM PDT 24
Finished May 16 12:23:57 PM PDT 24
Peak memory 216812 kb
Host smart-fc5cf2c5-e250-45a3-bedb-7a3048d8d434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075144719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3075144719
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.144240237
Short name T369
Test name
Test status
Simulation time 126569699 ps
CPU time 0.83 seconds
Started May 16 12:23:46 PM PDT 24
Finished May 16 12:23:51 PM PDT 24
Peak memory 198776 kb
Host smart-ededd2b3-c33d-4601-a8d2-bd95c6fccde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144240237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.144240237
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.575558853
Short name T458
Test name
Test status
Simulation time 851160649 ps
CPU time 4.75 seconds
Started May 16 12:23:46 PM PDT 24
Finished May 16 12:23:55 PM PDT 24
Peak memory 199192 kb
Host smart-3c0f8b61-535a-4cc0-840a-9acab1dbbafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575558853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.575558853
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.727773616
Short name T349
Test name
Test status
Simulation time 180990335 ps
CPU time 1.17 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:23:22 PM PDT 24
Peak memory 199080 kb
Host smart-89cf3426-f715-4709-8890-c2b60053034a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727773616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.727773616
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1903514265
Short name T287
Test name
Test status
Simulation time 124705619 ps
CPU time 1.16 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 200212 kb
Host smart-59fc5c4c-53dd-4916-97c9-e8c2f6148b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903514265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1903514265
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.998954168
Short name T235
Test name
Test status
Simulation time 1595455644 ps
CPU time 7.53 seconds
Started May 16 12:21:28 PM PDT 24
Finished May 16 12:21:37 PM PDT 24
Peak memory 208860 kb
Host smart-deb73e15-ccaa-4e45-a866-bbc6e0f85f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998954168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.998954168
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.711292950
Short name T242
Test name
Test status
Simulation time 132695289 ps
CPU time 1.58 seconds
Started May 16 12:23:15 PM PDT 24
Finished May 16 12:23:18 PM PDT 24
Peak memory 198580 kb
Host smart-e14a4196-f066-44da-aff3-6e289a2786e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711292950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.711292950
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1873592658
Short name T178
Test name
Test status
Simulation time 117040663 ps
CPU time 1.04 seconds
Started May 16 12:21:21 PM PDT 24
Finished May 16 12:21:23 PM PDT 24
Peak memory 200468 kb
Host smart-a14cf9be-bf7a-47e1-b48a-257301ee9753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873592658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1873592658
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3590500429
Short name T183
Test name
Test status
Simulation time 71788592 ps
CPU time 0.81 seconds
Started May 16 12:21:36 PM PDT 24
Finished May 16 12:21:38 PM PDT 24
Peak memory 200204 kb
Host smart-fb453833-5938-46f4-8fca-71d45c550106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590500429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3590500429
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.108597118
Short name T34
Test name
Test status
Simulation time 1220378258 ps
CPU time 5.73 seconds
Started May 16 12:23:45 PM PDT 24
Finished May 16 12:23:56 PM PDT 24
Peak memory 216364 kb
Host smart-50424b35-357c-4b96-ae3e-b2ef9a7d479a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108597118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.108597118
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.111247287
Short name T435
Test name
Test status
Simulation time 244707396 ps
CPU time 1.09 seconds
Started May 16 12:23:46 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 216172 kb
Host smart-b7b82f0c-c855-41a9-ac43-f20794eb7b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111247287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.111247287
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2498642114
Short name T269
Test name
Test status
Simulation time 217238442 ps
CPU time 0.86 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 199936 kb
Host smart-c2ca52b6-313b-4acd-802b-804680577103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498642114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2498642114
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1793173931
Short name T274
Test name
Test status
Simulation time 1589833571 ps
CPU time 6.23 seconds
Started May 16 12:23:54 PM PDT 24
Finished May 16 12:24:04 PM PDT 24
Peak memory 200420 kb
Host smart-92d7c126-8032-40eb-9582-2768b3d88316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793173931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1793173931
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2464849582
Short name T437
Test name
Test status
Simulation time 160237576 ps
CPU time 1.18 seconds
Started May 16 12:21:28 PM PDT 24
Finished May 16 12:21:31 PM PDT 24
Peak memory 200460 kb
Host smart-02022f48-b440-4319-8100-a79749b597bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464849582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2464849582
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1447419888
Short name T331
Test name
Test status
Simulation time 200403141 ps
CPU time 1.35 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 200252 kb
Host smart-cccff3c8-715f-42ce-af67-71cadbf6e7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447419888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1447419888
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2505709057
Short name T338
Test name
Test status
Simulation time 11844492448 ps
CPU time 45.01 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:24:36 PM PDT 24
Peak memory 200400 kb
Host smart-cb2f0cee-0a3e-4f5b-908d-34c71f72ad12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505709057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2505709057
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.19938239
Short name T174
Test name
Test status
Simulation time 262411276 ps
CPU time 1.76 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:23:53 PM PDT 24
Peak memory 200028 kb
Host smart-66a0640c-0cc7-4aa8-a86c-931f456ddf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19938239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.19938239
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2706571
Short name T422
Test name
Test status
Simulation time 151361332 ps
CPU time 1.06 seconds
Started May 16 12:23:47 PM PDT 24
Finished May 16 12:23:52 PM PDT 24
Peak memory 200040 kb
Host smart-2d7832da-0278-4716-8593-4afd60a03ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2706571
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1525555551
Short name T392
Test name
Test status
Simulation time 78247365 ps
CPU time 0.85 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:46 PM PDT 24
Peak memory 198188 kb
Host smart-0c1bd351-08de-487e-8686-903892c511e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525555551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1525555551
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2490254895
Short name T443
Test name
Test status
Simulation time 1906878854 ps
CPU time 6.92 seconds
Started May 16 12:21:36 PM PDT 24
Finished May 16 12:21:44 PM PDT 24
Peak memory 217636 kb
Host smart-7c5e4506-5253-4743-8401-5f5549411e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490254895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2490254895
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.847204408
Short name T7
Test name
Test status
Simulation time 244119119 ps
CPU time 1.04 seconds
Started May 16 12:23:18 PM PDT 24
Finished May 16 12:23:23 PM PDT 24
Peak memory 217204 kb
Host smart-2765fbfc-5918-489f-a93c-05612703a03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847204408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.847204408
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1775414556
Short name T191
Test name
Test status
Simulation time 185125176 ps
CPU time 0.97 seconds
Started May 16 12:23:18 PM PDT 24
Finished May 16 12:23:23 PM PDT 24
Peak memory 199956 kb
Host smart-b7542d64-8a88-457d-ad31-7a3304deeebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775414556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1775414556
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.4214583627
Short name T45
Test name
Test status
Simulation time 1823210407 ps
CPU time 6.3 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:34 PM PDT 24
Peak memory 200208 kb
Host smart-927611fc-fd75-40f6-bec9-92e1b40967be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214583627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4214583627
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2566464821
Short name T487
Test name
Test status
Simulation time 172236687 ps
CPU time 1.21 seconds
Started May 16 12:23:22 PM PDT 24
Finished May 16 12:23:29 PM PDT 24
Peak memory 199332 kb
Host smart-f24424b0-5229-4557-8605-ca18869a4260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566464821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2566464821
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2116950551
Short name T125
Test name
Test status
Simulation time 254374220 ps
CPU time 1.54 seconds
Started May 16 12:23:18 PM PDT 24
Finished May 16 12:23:23 PM PDT 24
Peak memory 199072 kb
Host smart-2e2d12e9-2643-4146-b426-b981bbc13ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116950551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2116950551
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1163290357
Short name T159
Test name
Test status
Simulation time 398076899 ps
CPU time 2.45 seconds
Started May 16 12:21:45 PM PDT 24
Finished May 16 12:21:48 PM PDT 24
Peak memory 200556 kb
Host smart-5f66f1f1-a6b9-49e2-b593-4d16b4b27be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163290357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1163290357
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2760516952
Short name T355
Test name
Test status
Simulation time 139697783 ps
CPU time 1.05 seconds
Started May 16 12:23:22 PM PDT 24
Finished May 16 12:23:29 PM PDT 24
Peak memory 199224 kb
Host smart-e1558b74-d213-492e-aa73-382ff49c07ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760516952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2760516952
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1936361854
Short name T444
Test name
Test status
Simulation time 68661195 ps
CPU time 0.79 seconds
Started May 16 12:22:26 PM PDT 24
Finished May 16 12:22:28 PM PDT 24
Peak memory 200180 kb
Host smart-299c024d-c61b-4d12-9089-1f8c54977bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936361854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1936361854
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3601433551
Short name T51
Test name
Test status
Simulation time 1235197724 ps
CPU time 5.8 seconds
Started May 16 12:23:07 PM PDT 24
Finished May 16 12:23:14 PM PDT 24
Peak memory 222060 kb
Host smart-52498b84-1828-4113-9005-f9eacfd0a72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601433551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3601433551
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3939084404
Short name T495
Test name
Test status
Simulation time 243528259 ps
CPU time 1.12 seconds
Started May 16 12:24:06 PM PDT 24
Finished May 16 12:24:18 PM PDT 24
Peak memory 216368 kb
Host smart-23fce635-7dbd-40f6-835a-70ea420ae205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939084404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3939084404
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1002994311
Short name T232
Test name
Test status
Simulation time 172831244 ps
CPU time 0.93 seconds
Started May 16 12:24:06 PM PDT 24
Finished May 16 12:24:17 PM PDT 24
Peak memory 198792 kb
Host smart-c868e674-88b8-4666-90ec-d5957db02467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002994311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1002994311
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1172093984
Short name T98
Test name
Test status
Simulation time 1611715128 ps
CPU time 6.13 seconds
Started May 16 12:22:25 PM PDT 24
Finished May 16 12:22:32 PM PDT 24
Peak memory 200640 kb
Host smart-e5c483c5-5fdf-4088-90fe-1096f46916bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172093984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1172093984
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.201552751
Short name T184
Test name
Test status
Simulation time 173076902 ps
CPU time 1.08 seconds
Started May 16 12:22:15 PM PDT 24
Finished May 16 12:22:17 PM PDT 24
Peak memory 200336 kb
Host smart-3cc727dc-8052-4848-acc9-37caaa911810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201552751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.201552751
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.465967008
Short name T259
Test name
Test status
Simulation time 111527691 ps
CPU time 1.19 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:29 PM PDT 24
Peak memory 200220 kb
Host smart-343db84f-d31b-4a24-bc6f-dbe2e39899e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465967008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.465967008
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.171103176
Short name T214
Test name
Test status
Simulation time 13200012163 ps
CPU time 51.7 seconds
Started May 16 12:21:45 PM PDT 24
Finished May 16 12:22:37 PM PDT 24
Peak memory 200784 kb
Host smart-70336ed4-d64a-4d63-96bf-e8927ef18500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171103176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.171103176
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.983108915
Short name T197
Test name
Test status
Simulation time 274286858 ps
CPU time 1.86 seconds
Started May 16 12:24:06 PM PDT 24
Finished May 16 12:24:19 PM PDT 24
Peak memory 200108 kb
Host smart-a828a140-601c-4438-a812-c5cd7e735a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983108915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.983108915
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.168578391
Short name T221
Test name
Test status
Simulation time 95028900 ps
CPU time 0.93 seconds
Started May 16 12:21:54 PM PDT 24
Finished May 16 12:21:57 PM PDT 24
Peak memory 200420 kb
Host smart-be81d554-1a00-499a-a43f-019997f5be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168578391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.168578391
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3440482320
Short name T531
Test name
Test status
Simulation time 71857211 ps
CPU time 0.76 seconds
Started May 16 12:23:16 PM PDT 24
Finished May 16 12:23:18 PM PDT 24
Peak memory 199808 kb
Host smart-99190bf3-8e1c-45e8-b9bc-5219f44ce940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440482320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3440482320
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3570796049
Short name T32
Test name
Test status
Simulation time 2374096870 ps
CPU time 8.19 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:23:29 PM PDT 24
Peak memory 216916 kb
Host smart-48d243d0-7a53-4a26-872a-8459feebb730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570796049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3570796049
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.616226337
Short name T329
Test name
Test status
Simulation time 244399081 ps
CPU time 1.08 seconds
Started May 16 12:21:55 PM PDT 24
Finished May 16 12:21:58 PM PDT 24
Peak memory 217600 kb
Host smart-ce173109-cee5-47db-b047-4d2347d28a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616226337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.616226337
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4041584440
Short name T510
Test name
Test status
Simulation time 169526414 ps
CPU time 0.85 seconds
Started May 16 12:24:14 PM PDT 24
Finished May 16 12:24:27 PM PDT 24
Peak memory 200032 kb
Host smart-4770e952-706b-4c48-afd9-92aa1708b279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041584440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4041584440
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2547239233
Short name T99
Test name
Test status
Simulation time 1836263709 ps
CPU time 6.15 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:23:28 PM PDT 24
Peak memory 199516 kb
Host smart-29bae64a-f4b7-41f1-8ca5-5105a0445a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547239233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2547239233
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2677217689
Short name T332
Test name
Test status
Simulation time 109149116 ps
CPU time 0.95 seconds
Started May 16 12:23:15 PM PDT 24
Finished May 16 12:23:18 PM PDT 24
Peak memory 199972 kb
Host smart-d99e95df-083d-472e-a003-9c7c8ef3d88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677217689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2677217689
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2407266448
Short name T152
Test name
Test status
Simulation time 240615412 ps
CPU time 1.43 seconds
Started May 16 12:24:26 PM PDT 24
Finished May 16 12:24:44 PM PDT 24
Peak memory 200344 kb
Host smart-cdc170f4-4ac9-4fae-b271-752868295a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407266448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2407266448
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1033002316
Short name T296
Test name
Test status
Simulation time 6233243703 ps
CPU time 28.7 seconds
Started May 16 12:21:55 PM PDT 24
Finished May 16 12:22:26 PM PDT 24
Peak memory 217112 kb
Host smart-64d01fb1-5a9d-45df-b023-597895bd045a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033002316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1033002316
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2224740613
Short name T270
Test name
Test status
Simulation time 450867545 ps
CPU time 2.42 seconds
Started May 16 12:23:15 PM PDT 24
Finished May 16 12:23:19 PM PDT 24
Peak memory 198772 kb
Host smart-c4e8adeb-e436-439d-9ef2-7f7b96797731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224740613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2224740613
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2945990412
Short name T523
Test name
Test status
Simulation time 223736364 ps
CPU time 1.36 seconds
Started May 16 12:21:55 PM PDT 24
Finished May 16 12:21:58 PM PDT 24
Peak memory 200456 kb
Host smart-f9032a73-141c-41d0-b39e-941070150f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945990412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2945990412
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2890159376
Short name T137
Test name
Test status
Simulation time 68372712 ps
CPU time 0.77 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:23:22 PM PDT 24
Peak memory 198184 kb
Host smart-4e6e01f7-ffc6-479e-b3cd-8de5fbee5e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890159376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2890159376
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3527539474
Short name T384
Test name
Test status
Simulation time 1877592725 ps
CPU time 6.64 seconds
Started May 16 12:23:20 PM PDT 24
Finished May 16 12:23:30 PM PDT 24
Peak memory 216808 kb
Host smart-30b046f7-8117-49b1-b4ee-de848a97b991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527539474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3527539474
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1190749501
Short name T266
Test name
Test status
Simulation time 244946232 ps
CPU time 1.05 seconds
Started May 16 12:23:20 PM PDT 24
Finished May 16 12:23:24 PM PDT 24
Peak memory 217224 kb
Host smart-a8297c08-410f-4e0d-a618-1f89fad6abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190749501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1190749501
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3813020163
Short name T375
Test name
Test status
Simulation time 175735898 ps
CPU time 0.84 seconds
Started May 16 12:23:20 PM PDT 24
Finished May 16 12:23:25 PM PDT 24
Peak memory 199968 kb
Host smart-a1769ba8-f02d-4410-8be2-3bcdde7bb9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813020163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3813020163
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.915511316
Short name T97
Test name
Test status
Simulation time 1771916357 ps
CPU time 6.06 seconds
Started May 16 12:23:19 PM PDT 24
Finished May 16 12:23:28 PM PDT 24
Peak memory 200368 kb
Host smart-e2af7220-fdb2-459a-97dd-1a6ca7c80021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915511316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.915511316
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.199506427
Short name T357
Test name
Test status
Simulation time 105613735 ps
CPU time 1.12 seconds
Started May 16 12:23:15 PM PDT 24
Finished May 16 12:23:18 PM PDT 24
Peak memory 198668 kb
Host smart-b73c44d4-c88f-4c90-802b-4404d49a8903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199506427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.199506427
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3391469359
Short name T492
Test name
Test status
Simulation time 121452781 ps
CPU time 1.16 seconds
Started May 16 12:23:20 PM PDT 24
Finished May 16 12:23:25 PM PDT 24
Peak memory 200216 kb
Host smart-60b026b2-517c-467c-a5ed-8296ca380d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391469359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3391469359
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.4141798709
Short name T203
Test name
Test status
Simulation time 1037784863 ps
CPU time 4.6 seconds
Started May 16 12:23:18 PM PDT 24
Finished May 16 12:23:27 PM PDT 24
Peak memory 200340 kb
Host smart-dcafc632-4eb0-4158-82a2-9b36af97851a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141798709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.4141798709
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2950304611
Short name T88
Test name
Test status
Simulation time 141324502 ps
CPU time 1.68 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:23:23 PM PDT 24
Peak memory 198936 kb
Host smart-e1df12b8-7f5c-42f0-9bd1-77851b5f968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950304611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2950304611
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1317696302
Short name T142
Test name
Test status
Simulation time 104999827 ps
CPU time 0.95 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:23:22 PM PDT 24
Peak memory 198828 kb
Host smart-bce2f56a-5c2e-4b1b-af14-0dff29073e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317696302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1317696302
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2107835671
Short name T440
Test name
Test status
Simulation time 55566411 ps
CPU time 0.75 seconds
Started May 16 12:24:42 PM PDT 24
Finished May 16 12:25:01 PM PDT 24
Peak memory 199860 kb
Host smart-7c2ea786-0fad-422c-9864-da929e0a63a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107835671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2107835671
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2065231900
Short name T35
Test name
Test status
Simulation time 1221076845 ps
CPU time 5.24 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:15 PM PDT 24
Peak memory 220352 kb
Host smart-23b8034b-a578-4518-80b3-95c83fc0597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065231900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2065231900
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3858059314
Short name T140
Test name
Test status
Simulation time 244232664 ps
CPU time 1.12 seconds
Started May 16 12:24:01 PM PDT 24
Finished May 16 12:24:06 PM PDT 24
Peak memory 216820 kb
Host smart-74d59502-fd14-458e-9628-e17d53d4e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858059314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3858059314
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1128397791
Short name T10
Test name
Test status
Simulation time 141570184 ps
CPU time 0.79 seconds
Started May 16 12:24:02 PM PDT 24
Finished May 16 12:24:07 PM PDT 24
Peak memory 199896 kb
Host smart-5e2cb3bb-5897-4810-8115-43b6e536f75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128397791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1128397791
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.822549369
Short name T536
Test name
Test status
Simulation time 1166788575 ps
CPU time 5.29 seconds
Started May 16 12:18:40 PM PDT 24
Finished May 16 12:18:48 PM PDT 24
Peak memory 200616 kb
Host smart-59e13c21-b035-4ce4-988c-70b52a7edaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822549369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.822549369
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.425095769
Short name T79
Test name
Test status
Simulation time 8487468072 ps
CPU time 14.26 seconds
Started May 16 12:25:08 PM PDT 24
Finished May 16 12:25:29 PM PDT 24
Peak memory 217100 kb
Host smart-61bc4bbe-a5d3-4891-ad2a-0126be1da2d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425095769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.425095769
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.835349916
Short name T27
Test name
Test status
Simulation time 161452939 ps
CPU time 1.07 seconds
Started May 16 12:18:44 PM PDT 24
Finished May 16 12:18:48 PM PDT 24
Peak memory 200304 kb
Host smart-4831f3fe-2996-4fe3-a2e5-c343dda02451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835349916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.835349916
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.730800645
Short name T402
Test name
Test status
Simulation time 202123194 ps
CPU time 1.42 seconds
Started May 16 12:21:03 PM PDT 24
Finished May 16 12:21:05 PM PDT 24
Peak memory 200664 kb
Host smart-24864054-6c34-499e-9e5e-c64ebc0bf5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730800645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.730800645
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3125935234
Short name T15
Test name
Test status
Simulation time 4309818709 ps
CPU time 16.08 seconds
Started May 16 12:19:18 PM PDT 24
Finished May 16 12:19:36 PM PDT 24
Peak memory 208948 kb
Host smart-fcb65d8d-e3f1-4fa7-99e0-ff20df4f6740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125935234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3125935234
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2323660739
Short name T2
Test name
Test status
Simulation time 460318935 ps
CPU time 2.6 seconds
Started May 16 12:18:43 PM PDT 24
Finished May 16 12:18:50 PM PDT 24
Peak memory 198940 kb
Host smart-718ada69-7d02-4636-899e-6bd692f91f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323660739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2323660739
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3138122789
Short name T141
Test name
Test status
Simulation time 243664404 ps
CPU time 1.46 seconds
Started May 16 12:23:24 PM PDT 24
Finished May 16 12:23:31 PM PDT 24
Peak memory 199048 kb
Host smart-dcf414b0-8995-48ff-a55a-722db66f042e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138122789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3138122789
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.190188127
Short name T268
Test name
Test status
Simulation time 58366689 ps
CPU time 0.73 seconds
Started May 16 12:23:35 PM PDT 24
Finished May 16 12:23:38 PM PDT 24
Peak memory 199160 kb
Host smart-b92bbf59-6a9f-4faa-b2bd-203ba1df3c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190188127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.190188127
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1291406445
Short name T445
Test name
Test status
Simulation time 2360131648 ps
CPU time 8.42 seconds
Started May 16 12:23:35 PM PDT 24
Finished May 16 12:23:46 PM PDT 24
Peak memory 221136 kb
Host smart-33581902-6565-41ee-bc46-f16fab91d1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291406445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1291406445
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1399550415
Short name T181
Test name
Test status
Simulation time 244404863 ps
CPU time 1.09 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:46 PM PDT 24
Peak memory 214804 kb
Host smart-db4309f2-642b-4f93-acf5-26c6905f97ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399550415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1399550415
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.825605656
Short name T248
Test name
Test status
Simulation time 184652584 ps
CPU time 0.88 seconds
Started May 16 12:23:35 PM PDT 24
Finished May 16 12:23:39 PM PDT 24
Peak memory 199068 kb
Host smart-6f03874e-16a9-4184-81b4-291880105103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825605656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.825605656
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3143662303
Short name T399
Test name
Test status
Simulation time 1750748718 ps
CPU time 6.73 seconds
Started May 16 12:23:19 PM PDT 24
Finished May 16 12:23:30 PM PDT 24
Peak memory 199184 kb
Host smart-0df7e734-251b-4258-bef5-6391d37b2587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143662303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3143662303
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2376297073
Short name T193
Test name
Test status
Simulation time 105070158 ps
CPU time 1.05 seconds
Started May 16 12:23:35 PM PDT 24
Finished May 16 12:23:39 PM PDT 24
Peak memory 199852 kb
Host smart-33067cdd-b9a0-4869-86d5-f0d37cdaba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376297073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2376297073
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.522162917
Short name T347
Test name
Test status
Simulation time 195290743 ps
CPU time 1.44 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:23:23 PM PDT 24
Peak memory 198448 kb
Host smart-748ffc2d-0511-409d-80ca-efd42efd2fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522162917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.522162917
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3275407641
Short name T289
Test name
Test status
Simulation time 13969400000 ps
CPU time 49.28 seconds
Started May 16 12:22:07 PM PDT 24
Finished May 16 12:22:57 PM PDT 24
Peak memory 208956 kb
Host smart-9eaa9dc1-af63-4733-9f39-0319dfa68cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275407641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3275407641
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.72038032
Short name T505
Test name
Test status
Simulation time 292446869 ps
CPU time 1.96 seconds
Started May 16 12:23:20 PM PDT 24
Finished May 16 12:23:27 PM PDT 24
Peak memory 199988 kb
Host smart-ac955c2d-48a4-4e60-bdac-7f6e671e8dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72038032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.72038032
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3858717439
Short name T426
Test name
Test status
Simulation time 240571542 ps
CPU time 1.49 seconds
Started May 16 12:23:17 PM PDT 24
Finished May 16 12:23:23 PM PDT 24
Peak memory 198516 kb
Host smart-fc229df2-93e0-4794-bc22-ae2ab0f3e291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858717439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3858717439
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.715441335
Short name T149
Test name
Test status
Simulation time 72076234 ps
CPU time 0.83 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:29 PM PDT 24
Peak memory 198592 kb
Host smart-056621c8-88d7-4ad1-8546-49a755488745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715441335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.715441335
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2096665664
Short name T50
Test name
Test status
Simulation time 1899554864 ps
CPU time 7.29 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:36 PM PDT 24
Peak memory 215884 kb
Host smart-178ac5a4-1023-424e-bfc5-6d6164e6ac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096665664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2096665664
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3119901687
Short name T411
Test name
Test status
Simulation time 244204166 ps
CPU time 1.15 seconds
Started May 16 12:23:29 PM PDT 24
Finished May 16 12:23:35 PM PDT 24
Peak memory 216504 kb
Host smart-d07f062c-8491-420a-8fd5-7fb710036e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119901687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3119901687
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1532843926
Short name T330
Test name
Test status
Simulation time 164153779 ps
CPU time 0.88 seconds
Started May 16 12:23:30 PM PDT 24
Finished May 16 12:23:35 PM PDT 24
Peak memory 199020 kb
Host smart-325682ea-37d3-41a1-abd7-f03728c1fea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532843926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1532843926
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.4228329458
Short name T40
Test name
Test status
Simulation time 1259917291 ps
CPU time 5.24 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:34 PM PDT 24
Peak memory 198436 kb
Host smart-82b909e3-2e89-41b2-9bcb-e4dcaa75d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228329458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.4228329458
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2802156839
Short name T319
Test name
Test status
Simulation time 150037265 ps
CPU time 1.15 seconds
Started May 16 12:23:23 PM PDT 24
Finished May 16 12:23:30 PM PDT 24
Peak memory 198852 kb
Host smart-9f1cb68c-eb29-4ea4-bcd8-8abc2a2a276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802156839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2802156839
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.389295332
Short name T156
Test name
Test status
Simulation time 224905040 ps
CPU time 1.51 seconds
Started May 16 12:22:12 PM PDT 24
Finished May 16 12:22:14 PM PDT 24
Peak memory 200728 kb
Host smart-c4abf490-1db1-487d-bbf9-e8e4cfaaf55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389295332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.389295332
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2903590913
Short name T377
Test name
Test status
Simulation time 120288033 ps
CPU time 1.5 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:47 PM PDT 24
Peak memory 197884 kb
Host smart-c8a27be5-d705-4a94-a1a4-c15aa0d21390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903590913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2903590913
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2053965475
Short name T160
Test name
Test status
Simulation time 114453668 ps
CPU time 1 seconds
Started May 16 12:23:24 PM PDT 24
Finished May 16 12:23:30 PM PDT 24
Peak memory 200116 kb
Host smart-e4290667-6c7a-4c0b-bbbf-be6265089583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053965475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2053965475
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1599560911
Short name T304
Test name
Test status
Simulation time 83654665 ps
CPU time 0.83 seconds
Started May 16 12:22:16 PM PDT 24
Finished May 16 12:22:18 PM PDT 24
Peak memory 200180 kb
Host smart-e436370b-d8f6-4908-9eb4-3933f60cfb31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599560911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1599560911
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.407095845
Short name T438
Test name
Test status
Simulation time 1221006001 ps
CPU time 5.44 seconds
Started May 16 12:23:44 PM PDT 24
Finished May 16 12:23:54 PM PDT 24
Peak memory 217820 kb
Host smart-88b3ce97-74d5-4d69-83f0-293df6b66bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407095845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.407095845
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.50913287
Short name T490
Test name
Test status
Simulation time 244741707 ps
CPU time 1.06 seconds
Started May 16 12:23:43 PM PDT 24
Finished May 16 12:23:48 PM PDT 24
Peak memory 216256 kb
Host smart-b4f742f2-1b8e-4fd2-aa70-057ad1817fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50913287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.50913287
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1387442853
Short name T499
Test name
Test status
Simulation time 201564790 ps
CPU time 0.88 seconds
Started May 16 12:22:15 PM PDT 24
Finished May 16 12:22:17 PM PDT 24
Peak memory 200152 kb
Host smart-9edf4995-820b-4b3e-9e46-76be61ea869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387442853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1387442853
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3144991499
Short name T264
Test name
Test status
Simulation time 1813374211 ps
CPU time 6.24 seconds
Started May 16 12:23:55 PM PDT 24
Finished May 16 12:24:05 PM PDT 24
Peak memory 200436 kb
Host smart-130b7a16-67b6-43a7-b7b1-dd0df338f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144991499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3144991499
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.393485870
Short name T185
Test name
Test status
Simulation time 159737061 ps
CPU time 1.06 seconds
Started May 16 12:24:25 PM PDT 24
Finished May 16 12:24:42 PM PDT 24
Peak memory 200120 kb
Host smart-f2f11508-f431-46d0-88e5-cf9c1ad7ff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393485870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.393485870
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2651125880
Short name T43
Test name
Test status
Simulation time 112362172 ps
CPU time 1.13 seconds
Started May 16 12:23:54 PM PDT 24
Finished May 16 12:23:59 PM PDT 24
Peak memory 200400 kb
Host smart-622da88e-b924-4adb-a6dc-481d0d86c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651125880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2651125880
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1280758832
Short name T262
Test name
Test status
Simulation time 2847544526 ps
CPU time 10.63 seconds
Started May 16 12:23:43 PM PDT 24
Finished May 16 12:23:58 PM PDT 24
Peak memory 199572 kb
Host smart-d55f7d8f-547e-4780-92cf-cd55a1b52dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280758832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1280758832
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2303866536
Short name T87
Test name
Test status
Simulation time 521150459 ps
CPU time 2.73 seconds
Started May 16 12:23:43 PM PDT 24
Finished May 16 12:23:50 PM PDT 24
Peak memory 198916 kb
Host smart-108150db-6580-4329-8c4e-8a92bc4782de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303866536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2303866536
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4207132441
Short name T213
Test name
Test status
Simulation time 150493592 ps
CPU time 1.1 seconds
Started May 16 12:23:05 PM PDT 24
Finished May 16 12:23:07 PM PDT 24
Peak memory 200404 kb
Host smart-d57058a2-a7aa-42b0-af41-f6aaa59058f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207132441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4207132441
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.4229423992
Short name T364
Test name
Test status
Simulation time 74691415 ps
CPU time 0.8 seconds
Started May 16 12:24:17 PM PDT 24
Finished May 16 12:24:32 PM PDT 24
Peak memory 199368 kb
Host smart-83da96f9-46d4-4c06-bef2-ed5f85dbaba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229423992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.4229423992
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1812485220
Short name T49
Test name
Test status
Simulation time 1895177882 ps
CPU time 7.07 seconds
Started May 16 12:23:43 PM PDT 24
Finished May 16 12:23:54 PM PDT 24
Peak memory 217656 kb
Host smart-f82dda52-a3c7-486d-8b26-7e931b619fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812485220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1812485220
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1198219709
Short name T488
Test name
Test status
Simulation time 244273783 ps
CPU time 1.14 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:46 PM PDT 24
Peak memory 214868 kb
Host smart-e555ce06-cc78-41ff-b390-03bbc9538487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198219709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1198219709
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1357164986
Short name T25
Test name
Test status
Simulation time 219609591 ps
CPU time 0.9 seconds
Started May 16 12:23:42 PM PDT 24
Finished May 16 12:23:47 PM PDT 24
Peak memory 199808 kb
Host smart-975cfdb2-bcd4-4b22-9e0e-8a3e3aa2ec50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357164986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1357164986
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3246158253
Short name T337
Test name
Test status
Simulation time 891490384 ps
CPU time 4.91 seconds
Started May 16 12:22:50 PM PDT 24
Finished May 16 12:22:56 PM PDT 24
Peak memory 200588 kb
Host smart-e70ef496-e98b-49bd-8d10-4cc61d56f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246158253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3246158253
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1069604875
Short name T157
Test name
Test status
Simulation time 99860549 ps
CPU time 0.94 seconds
Started May 16 12:23:42 PM PDT 24
Finished May 16 12:23:47 PM PDT 24
Peak memory 199764 kb
Host smart-7f8df634-4f28-4cd8-8c26-a5046d57af85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069604875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1069604875
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2424632694
Short name T245
Test name
Test status
Simulation time 118580949 ps
CPU time 1.14 seconds
Started May 16 12:23:42 PM PDT 24
Finished May 16 12:23:47 PM PDT 24
Peak memory 200168 kb
Host smart-01e78bf6-7125-4302-a82e-11586f6ef6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424632694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2424632694
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.710354726
Short name T442
Test name
Test status
Simulation time 3049856457 ps
CPU time 13.74 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:59 PM PDT 24
Peak memory 206464 kb
Host smart-b632ad26-7f45-4d03-8023-334048ccae86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710354726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.710354726
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3071104707
Short name T84
Test name
Test status
Simulation time 305324442 ps
CPU time 1.89 seconds
Started May 16 12:24:26 PM PDT 24
Finished May 16 12:24:46 PM PDT 24
Peak memory 208356 kb
Host smart-cf30f783-0bcc-4248-a90f-c5cb36ee3fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071104707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3071104707
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1534399679
Short name T503
Test name
Test status
Simulation time 150374928 ps
CPU time 1.17 seconds
Started May 16 12:23:44 PM PDT 24
Finished May 16 12:23:50 PM PDT 24
Peak memory 200160 kb
Host smart-ca982ec1-cd1e-4af4-9703-fdbbbc438acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534399679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1534399679
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2139930913
Short name T227
Test name
Test status
Simulation time 66869626 ps
CPU time 0.72 seconds
Started May 16 12:24:25 PM PDT 24
Finished May 16 12:24:42 PM PDT 24
Peak memory 199952 kb
Host smart-0f2aea4b-d0e6-4dc9-b42c-fa0c903da0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139930913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2139930913
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1548822773
Short name T481
Test name
Test status
Simulation time 2355046122 ps
CPU time 8 seconds
Started May 16 12:24:27 PM PDT 24
Finished May 16 12:24:53 PM PDT 24
Peak memory 217620 kb
Host smart-683ae030-acae-412a-aa56-1fa5ed96f492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548822773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1548822773
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3542260916
Short name T212
Test name
Test status
Simulation time 246911467 ps
CPU time 1.01 seconds
Started May 16 12:23:42 PM PDT 24
Finished May 16 12:23:47 PM PDT 24
Peak memory 217128 kb
Host smart-496ff6df-67f3-44cd-a631-4279222a576b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542260916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3542260916
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.198543910
Short name T19
Test name
Test status
Simulation time 83647889 ps
CPU time 0.74 seconds
Started May 16 12:22:49 PM PDT 24
Finished May 16 12:22:51 PM PDT 24
Peak memory 200212 kb
Host smart-c04ee756-7fba-4387-9342-c86e281479f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198543910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.198543910
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3594017470
Short name T308
Test name
Test status
Simulation time 807657971 ps
CPU time 4.27 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:50 PM PDT 24
Peak memory 198272 kb
Host smart-b8aff83b-6a80-4fcf-a135-8e546b237d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594017470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3594017470
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1723873836
Short name T275
Test name
Test status
Simulation time 159864112 ps
CPU time 1.07 seconds
Started May 16 12:24:26 PM PDT 24
Finished May 16 12:24:44 PM PDT 24
Peak memory 200128 kb
Host smart-c1d7ce5a-b48b-4d9d-8d59-ed01fc7aa66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723873836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1723873836
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3858819009
Short name T169
Test name
Test status
Simulation time 116832677 ps
CPU time 1.18 seconds
Started May 16 12:23:43 PM PDT 24
Finished May 16 12:23:48 PM PDT 24
Peak memory 199428 kb
Host smart-f9a3c755-b903-4bfa-950e-8a1f989fa42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858819009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3858819009
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.22721202
Short name T211
Test name
Test status
Simulation time 12266128396 ps
CPU time 38.53 seconds
Started May 16 12:24:33 PM PDT 24
Finished May 16 12:25:30 PM PDT 24
Peak memory 199564 kb
Host smart-cde4bdf7-34d3-4f96-a5e3-fcac542e61cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.22721202
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3024882673
Short name T182
Test name
Test status
Simulation time 416039856 ps
CPU time 2.22 seconds
Started May 16 12:24:41 PM PDT 24
Finished May 16 12:25:03 PM PDT 24
Peak memory 208400 kb
Host smart-0521767c-b5c6-4443-8dfd-b5d1f46c17d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024882673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3024882673
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1682763628
Short name T423
Test name
Test status
Simulation time 112614792 ps
CPU time 1.05 seconds
Started May 16 12:24:41 PM PDT 24
Finished May 16 12:25:00 PM PDT 24
Peak memory 200088 kb
Host smart-e659bba0-0923-441d-ae25-259655aefc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682763628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1682763628
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2980157995
Short name T247
Test name
Test status
Simulation time 52200912 ps
CPU time 0.74 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:45 PM PDT 24
Peak memory 199016 kb
Host smart-8d7cc6ad-6722-4b5f-8282-9f4a09608e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980157995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2980157995
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2374837652
Short name T457
Test name
Test status
Simulation time 1886054004 ps
CPU time 7.17 seconds
Started May 16 12:23:43 PM PDT 24
Finished May 16 12:23:54 PM PDT 24
Peak memory 217484 kb
Host smart-f0bf0368-6b90-4481-a049-4783f2325ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374837652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2374837652
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3923116173
Short name T436
Test name
Test status
Simulation time 244693011 ps
CPU time 1.12 seconds
Started May 16 12:23:54 PM PDT 24
Finished May 16 12:23:59 PM PDT 24
Peak memory 217348 kb
Host smart-fadaf880-8010-4c39-8ddb-c58c01827e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923116173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3923116173
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3550737891
Short name T405
Test name
Test status
Simulation time 169746022 ps
CPU time 0.87 seconds
Started May 16 12:23:43 PM PDT 24
Finished May 16 12:23:48 PM PDT 24
Peak memory 199160 kb
Host smart-46d44b83-f5fe-4fae-8909-aa6dc9390a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550737891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3550737891
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3463262201
Short name T17
Test name
Test status
Simulation time 1608050954 ps
CPU time 6.52 seconds
Started May 16 12:23:44 PM PDT 24
Finished May 16 12:23:54 PM PDT 24
Peak memory 200256 kb
Host smart-25e02e8a-5209-4cf5-8552-248e142aa5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463262201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3463262201
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3909560214
Short name T461
Test name
Test status
Simulation time 143657505 ps
CPU time 1.02 seconds
Started May 16 12:23:42 PM PDT 24
Finished May 16 12:23:47 PM PDT 24
Peak memory 199796 kb
Host smart-a90efec2-adee-4d9b-abf8-42644088957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909560214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3909560214
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.588854187
Short name T225
Test name
Test status
Simulation time 207859797 ps
CPU time 1.33 seconds
Started May 16 12:23:42 PM PDT 24
Finished May 16 12:23:47 PM PDT 24
Peak memory 200208 kb
Host smart-bda61401-c984-44d1-8ae2-7dd1fca6df65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588854187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.588854187
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1518752317
Short name T367
Test name
Test status
Simulation time 4808813711 ps
CPU time 20.53 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:24:05 PM PDT 24
Peak memory 200432 kb
Host smart-908a7829-df2f-4e80-a10d-a761c952678e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518752317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1518752317
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2398817512
Short name T327
Test name
Test status
Simulation time 325370254 ps
CPU time 2 seconds
Started May 16 12:24:26 PM PDT 24
Finished May 16 12:24:45 PM PDT 24
Peak memory 200116 kb
Host smart-52c94a96-aa0e-4210-983f-7b74023cd26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398817512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2398817512
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1928388348
Short name T11
Test name
Test status
Simulation time 103743911 ps
CPU time 0.87 seconds
Started May 16 12:24:26 PM PDT 24
Finished May 16 12:24:45 PM PDT 24
Peak memory 200124 kb
Host smart-76d7b830-175a-481c-b033-cd26aa277775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928388348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1928388348
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2942280290
Short name T341
Test name
Test status
Simulation time 61022776 ps
CPU time 0.74 seconds
Started May 16 12:23:55 PM PDT 24
Finished May 16 12:24:00 PM PDT 24
Peak memory 199868 kb
Host smart-bf42c4cd-25c3-4402-bdf2-7bb1703e4bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942280290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2942280290
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1694974837
Short name T41
Test name
Test status
Simulation time 1238080248 ps
CPU time 6.12 seconds
Started May 16 12:22:38 PM PDT 24
Finished May 16 12:22:45 PM PDT 24
Peak memory 222116 kb
Host smart-ca647423-b535-4e53-ae30-f3484c4277f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694974837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1694974837
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1225456283
Short name T498
Test name
Test status
Simulation time 244944805 ps
CPU time 1.11 seconds
Started May 16 12:22:35 PM PDT 24
Finished May 16 12:22:37 PM PDT 24
Peak memory 217572 kb
Host smart-121d63f4-68ec-4d91-9365-dd0ede0847b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225456283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1225456283
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.383553884
Short name T368
Test name
Test status
Simulation time 223774429 ps
CPU time 0.88 seconds
Started May 16 12:23:53 PM PDT 24
Finished May 16 12:23:57 PM PDT 24
Peak memory 199920 kb
Host smart-21866942-b924-4484-a193-7e6480cf4c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383553884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.383553884
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3525589245
Short name T273
Test name
Test status
Simulation time 992880373 ps
CPU time 4.66 seconds
Started May 16 12:23:42 PM PDT 24
Finished May 16 12:23:50 PM PDT 24
Peak memory 200284 kb
Host smart-f04f680a-4ef7-4793-b6c5-9b75e31bbc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525589245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3525589245
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2422640692
Short name T144
Test name
Test status
Simulation time 181315797 ps
CPU time 1.15 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:45 PM PDT 24
Peak memory 199228 kb
Host smart-9fda916f-76f7-4fff-b35e-0344eed20ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422640692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2422640692
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.6733102
Short name T460
Test name
Test status
Simulation time 112445087 ps
CPU time 1.2 seconds
Started May 16 12:23:42 PM PDT 24
Finished May 16 12:23:47 PM PDT 24
Peak memory 200284 kb
Host smart-2e61d163-817b-4fb5-ac6a-c3ad4165c893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6733102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.6733102
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2636571527
Short name T90
Test name
Test status
Simulation time 6585341710 ps
CPU time 28.93 seconds
Started May 16 12:24:19 PM PDT 24
Finished May 16 12:25:03 PM PDT 24
Peak memory 200756 kb
Host smart-56c5d735-1369-4273-96e9-06a03232deae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636571527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2636571527
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3478776284
Short name T198
Test name
Test status
Simulation time 328866166 ps
CPU time 1.98 seconds
Started May 16 12:23:43 PM PDT 24
Finished May 16 12:23:49 PM PDT 24
Peak memory 208284 kb
Host smart-f8c0cab0-ecec-498e-aeda-f4d1207e8b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478776284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3478776284
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1868934856
Short name T219
Test name
Test status
Simulation time 83491291 ps
CPU time 0.86 seconds
Started May 16 12:23:41 PM PDT 24
Finished May 16 12:23:45 PM PDT 24
Peak memory 199480 kb
Host smart-399a8479-7e62-41b8-b48e-544a18ecef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868934856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1868934856
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1394679946
Short name T176
Test name
Test status
Simulation time 58688122 ps
CPU time 0.73 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:25 PM PDT 24
Peak memory 200240 kb
Host smart-a69211c4-61b7-4060-bee7-83edaa671fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394679946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1394679946
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.954436749
Short name T466
Test name
Test status
Simulation time 1907294103 ps
CPU time 7.3 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:32 PM PDT 24
Peak memory 218060 kb
Host smart-a25efeef-c5b7-4e96-a266-141307851b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954436749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.954436749
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2074826913
Short name T206
Test name
Test status
Simulation time 243773735 ps
CPU time 1.08 seconds
Started May 16 12:22:53 PM PDT 24
Finished May 16 12:22:55 PM PDT 24
Peak memory 217448 kb
Host smart-6cbb9fa2-9c9c-4221-a017-7eb641838033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074826913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2074826913
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2768779066
Short name T24
Test name
Test status
Simulation time 170191027 ps
CPU time 0.88 seconds
Started May 16 12:23:55 PM PDT 24
Finished May 16 12:24:00 PM PDT 24
Peak memory 199816 kb
Host smart-2dafdaa6-65ec-4a34-99bf-f52ba5dcddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768779066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2768779066
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2922851718
Short name T243
Test name
Test status
Simulation time 1649796815 ps
CPU time 6.52 seconds
Started May 16 12:23:57 PM PDT 24
Finished May 16 12:24:08 PM PDT 24
Peak memory 200444 kb
Host smart-bd24d58e-2299-4135-8afc-f25433e232cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922851718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2922851718
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1121815000
Short name T538
Test name
Test status
Simulation time 143537638 ps
CPU time 1.12 seconds
Started May 16 12:23:55 PM PDT 24
Finished May 16 12:24:01 PM PDT 24
Peak memory 200020 kb
Host smart-f08927b2-2c3d-41e6-b551-2c321d696e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121815000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1121815000
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3341931836
Short name T190
Test name
Test status
Simulation time 227523112 ps
CPU time 1.45 seconds
Started May 16 12:24:20 PM PDT 24
Finished May 16 12:24:36 PM PDT 24
Peak memory 200576 kb
Host smart-e45efa74-f17e-4fe9-8210-5b772e7cfcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341931836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3341931836
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2067387315
Short name T430
Test name
Test status
Simulation time 7696299111 ps
CPU time 34.37 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:59 PM PDT 24
Peak memory 208940 kb
Host smart-7258bb71-bd87-4b44-a62a-98d10bb5b0ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067387315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2067387315
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.4060867321
Short name T530
Test name
Test status
Simulation time 117033005 ps
CPU time 1.42 seconds
Started May 16 12:24:07 PM PDT 24
Finished May 16 12:24:19 PM PDT 24
Peak memory 200384 kb
Host smart-0e6c1d20-74bf-4cb9-bd52-c78688a2fc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060867321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4060867321
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3252261059
Short name T170
Test name
Test status
Simulation time 170399888 ps
CPU time 1.21 seconds
Started May 16 12:22:42 PM PDT 24
Finished May 16 12:22:44 PM PDT 24
Peak memory 200556 kb
Host smart-273c80a8-8c6e-4252-bd35-2cf8f7ee5d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252261059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3252261059
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4237212289
Short name T143
Test name
Test status
Simulation time 67288537 ps
CPU time 0.76 seconds
Started May 16 12:24:48 PM PDT 24
Finished May 16 12:25:07 PM PDT 24
Peak memory 199296 kb
Host smart-9301a7fe-8c2c-464c-96e8-8f72c047f352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237212289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4237212289
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1195897272
Short name T416
Test name
Test status
Simulation time 1900380602 ps
CPU time 7.57 seconds
Started May 16 12:22:49 PM PDT 24
Finished May 16 12:22:58 PM PDT 24
Peak memory 221200 kb
Host smart-bb362bed-4991-45e4-a8c5-5a141b197d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195897272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1195897272
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.348129700
Short name T166
Test name
Test status
Simulation time 243532117 ps
CPU time 1.18 seconds
Started May 16 12:22:57 PM PDT 24
Finished May 16 12:22:59 PM PDT 24
Peak memory 217712 kb
Host smart-fe826317-2c21-4929-808a-2c14a79aca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348129700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.348129700
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2189502249
Short name T410
Test name
Test status
Simulation time 135539099 ps
CPU time 0.84 seconds
Started May 16 12:22:48 PM PDT 24
Finished May 16 12:22:50 PM PDT 24
Peak memory 199964 kb
Host smart-8f97009b-ec19-4b7d-8339-e7f3febb476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189502249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2189502249
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1068668206
Short name T533
Test name
Test status
Simulation time 1560877994 ps
CPU time 5.41 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:30 PM PDT 24
Peak memory 200440 kb
Host smart-74d21d78-9b87-49e3-b1ff-6fda65927412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068668206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1068668206
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3166190196
Short name T529
Test name
Test status
Simulation time 106857651 ps
CPU time 1.02 seconds
Started May 16 12:22:51 PM PDT 24
Finished May 16 12:22:54 PM PDT 24
Peak memory 200348 kb
Host smart-bf8fd6ec-732a-42c9-95e5-899fedc47d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166190196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3166190196
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.888168726
Short name T382
Test name
Test status
Simulation time 116156816 ps
CPU time 1.14 seconds
Started May 16 12:23:55 PM PDT 24
Finished May 16 12:24:01 PM PDT 24
Peak memory 199696 kb
Host smart-1a5445fb-40cc-461e-b393-267c97ce5a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888168726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.888168726
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.848750516
Short name T196
Test name
Test status
Simulation time 4576146241 ps
CPU time 22.29 seconds
Started May 16 12:22:55 PM PDT 24
Finished May 16 12:23:18 PM PDT 24
Peak memory 209016 kb
Host smart-2615511a-f6f9-4c45-a3a4-df0a889ec7d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848750516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.848750516
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2922439233
Short name T200
Test name
Test status
Simulation time 394694567 ps
CPU time 2.32 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:27 PM PDT 24
Peak memory 200244 kb
Host smart-6df2da96-5109-43ac-933f-8b3024f47618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922439233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2922439233
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1003004271
Short name T509
Test name
Test status
Simulation time 226203760 ps
CPU time 1.32 seconds
Started May 16 12:22:48 PM PDT 24
Finished May 16 12:22:50 PM PDT 24
Peak memory 200420 kb
Host smart-f56be275-a378-4271-be89-7e5373178a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003004271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1003004271
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.659400337
Short name T325
Test name
Test status
Simulation time 81493132 ps
CPU time 0.77 seconds
Started May 16 12:24:37 PM PDT 24
Finished May 16 12:24:57 PM PDT 24
Peak memory 199296 kb
Host smart-11c84cc8-1d5b-4749-84a5-8e9e0d7b7feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659400337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.659400337
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1542538448
Short name T57
Test name
Test status
Simulation time 1895248427 ps
CPU time 7.03 seconds
Started May 16 12:24:41 PM PDT 24
Finished May 16 12:25:06 PM PDT 24
Peak memory 217684 kb
Host smart-3619dc0e-4825-4f18-bd2c-fed32f768b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542538448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1542538448
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3073964824
Short name T407
Test name
Test status
Simulation time 244112585 ps
CPU time 1.23 seconds
Started May 16 12:22:57 PM PDT 24
Finished May 16 12:22:59 PM PDT 24
Peak memory 217552 kb
Host smart-a7a2f6bb-aac1-4dc2-ba6f-f83c80be7a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073964824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3073964824
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2685485035
Short name T234
Test name
Test status
Simulation time 185699326 ps
CPU time 0.92 seconds
Started May 16 12:24:48 PM PDT 24
Finished May 16 12:25:07 PM PDT 24
Peak memory 199260 kb
Host smart-ffab13d4-d64d-498d-a2e1-7af3a3c2c0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685485035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2685485035
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.235599441
Short name T100
Test name
Test status
Simulation time 1546835271 ps
CPU time 5.65 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:31 PM PDT 24
Peak memory 200032 kb
Host smart-ebad37fd-9e32-4ee5-9335-b83603bbcdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235599441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.235599441
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3656661691
Short name T150
Test name
Test status
Simulation time 92903565 ps
CPU time 1.04 seconds
Started May 16 12:22:57 PM PDT 24
Finished May 16 12:22:59 PM PDT 24
Peak memory 200484 kb
Host smart-65d0d921-cf95-451b-83d7-62668f040e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656661691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3656661691
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2874288048
Short name T265
Test name
Test status
Simulation time 245445973 ps
CPU time 1.35 seconds
Started May 16 12:24:13 PM PDT 24
Finished May 16 12:24:27 PM PDT 24
Peak memory 200216 kb
Host smart-ec94635a-0ff0-4813-a16d-3e8c4ae996cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874288048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2874288048
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2221783605
Short name T202
Test name
Test status
Simulation time 2155086209 ps
CPU time 9.7 seconds
Started May 16 12:24:13 PM PDT 24
Finished May 16 12:24:35 PM PDT 24
Peak memory 208500 kb
Host smart-5225f9f3-eee7-467c-b70a-ad35ee5177b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221783605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2221783605
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.4030881773
Short name T497
Test name
Test status
Simulation time 141235500 ps
CPU time 1.75 seconds
Started May 16 12:24:15 PM PDT 24
Finished May 16 12:24:30 PM PDT 24
Peak memory 199656 kb
Host smart-589e0d65-e172-4ac2-ae1e-61391ff53a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030881773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.4030881773
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2986586377
Short name T165
Test name
Test status
Simulation time 146820804 ps
CPU time 0.97 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:26 PM PDT 24
Peak memory 199972 kb
Host smart-fa709129-6988-4bb2-95c0-03c1a63b36c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986586377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2986586377
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2057840274
Short name T353
Test name
Test status
Simulation time 58526063 ps
CPU time 0.74 seconds
Started May 16 12:19:30 PM PDT 24
Finished May 16 12:19:33 PM PDT 24
Peak memory 200384 kb
Host smart-9dc75455-aad0-42ac-9216-f6fa4d856fb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057840274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2057840274
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.4042135558
Short name T31
Test name
Test status
Simulation time 2365095674 ps
CPU time 9.03 seconds
Started May 16 12:21:16 PM PDT 24
Finished May 16 12:21:27 PM PDT 24
Peak memory 221816 kb
Host smart-3fad38e9-8266-44bf-b13d-ee721a72708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042135558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4042135558
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2953890576
Short name T155
Test name
Test status
Simulation time 244204155 ps
CPU time 1.07 seconds
Started May 16 12:19:02 PM PDT 24
Finished May 16 12:19:04 PM PDT 24
Peak memory 217528 kb
Host smart-4983acbb-717d-4bef-8926-96274d0e65f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953890576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2953890576
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2137904677
Short name T333
Test name
Test status
Simulation time 185735302 ps
CPU time 0.93 seconds
Started May 16 12:22:46 PM PDT 24
Finished May 16 12:22:48 PM PDT 24
Peak memory 200112 kb
Host smart-e5b1a558-ac55-4d14-a390-e6c78b7b6421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137904677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2137904677
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2259954463
Short name T257
Test name
Test status
Simulation time 764493396 ps
CPU time 3.87 seconds
Started May 16 12:20:30 PM PDT 24
Finished May 16 12:20:34 PM PDT 24
Peak memory 200692 kb
Host smart-0ded0b48-e038-4b0d-8be0-514dacb1938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259954463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2259954463
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3246361504
Short name T336
Test name
Test status
Simulation time 94744466 ps
CPU time 0.91 seconds
Started May 16 12:25:16 PM PDT 24
Finished May 16 12:25:20 PM PDT 24
Peak memory 200288 kb
Host smart-e3feb8eb-974c-446c-9234-d6c3ad8db820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246361504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3246361504
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2483741768
Short name T163
Test name
Test status
Simulation time 206117832 ps
CPU time 1.51 seconds
Started May 16 12:20:02 PM PDT 24
Finished May 16 12:20:05 PM PDT 24
Peak memory 200600 kb
Host smart-c825d8ac-7a5b-4498-830f-d95900d10d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483741768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2483741768
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.616306613
Short name T441
Test name
Test status
Simulation time 118359619 ps
CPU time 0.84 seconds
Started May 16 12:20:13 PM PDT 24
Finished May 16 12:20:15 PM PDT 24
Peak memory 200244 kb
Host smart-6b1449ac-d2bd-4c3d-bc26-31a68c833689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616306613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.616306613
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.868758558
Short name T261
Test name
Test status
Simulation time 376289778 ps
CPU time 2.35 seconds
Started May 16 12:20:13 PM PDT 24
Finished May 16 12:20:17 PM PDT 24
Peak memory 200556 kb
Host smart-1364d7bc-291a-409f-bd5c-96a2fd32b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868758558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.868758558
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1971453376
Short name T222
Test name
Test status
Simulation time 231036412 ps
CPU time 1.4 seconds
Started May 16 12:20:32 PM PDT 24
Finished May 16 12:20:34 PM PDT 24
Peak memory 200480 kb
Host smart-34c91363-761d-44ac-935b-787ccd34f529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971453376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1971453376
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.4260066716
Short name T386
Test name
Test status
Simulation time 59070665 ps
CPU time 0.75 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:25 PM PDT 24
Peak memory 200172 kb
Host smart-dfcdfd37-0fba-408d-872c-ad6bf7b7d9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260066716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4260066716
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.816834794
Short name T527
Test name
Test status
Simulation time 2164922135 ps
CPU time 7.57 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:57 PM PDT 24
Peak memory 215184 kb
Host smart-f2c2c5ef-ffa2-498b-9009-926b4318695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816834794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.816834794
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.169767492
Short name T188
Test name
Test status
Simulation time 243790657 ps
CPU time 1.01 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:31 PM PDT 24
Peak memory 217144 kb
Host smart-468972b4-842e-4f79-9408-ce8a3aeed6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169767492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.169767492
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1926194782
Short name T351
Test name
Test status
Simulation time 86497288 ps
CPU time 0.77 seconds
Started May 16 12:20:03 PM PDT 24
Finished May 16 12:20:05 PM PDT 24
Peak memory 200316 kb
Host smart-bf400db1-3515-445e-aaf3-730b7b7605b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926194782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1926194782
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2320304540
Short name T122
Test name
Test status
Simulation time 1989916793 ps
CPU time 7.87 seconds
Started May 16 12:20:43 PM PDT 24
Finished May 16 12:20:51 PM PDT 24
Peak memory 200608 kb
Host smart-71fe6c8b-9de5-496d-99cb-bc884caf0908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320304540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2320304540
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1252433169
Short name T388
Test name
Test status
Simulation time 148374466 ps
CPU time 1.23 seconds
Started May 16 12:22:47 PM PDT 24
Finished May 16 12:22:50 PM PDT 24
Peak memory 200464 kb
Host smart-5e599715-b970-4b7a-92ed-c9766f263d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252433169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1252433169
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2389395599
Short name T360
Test name
Test status
Simulation time 245040532 ps
CPU time 1.42 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:51 PM PDT 24
Peak memory 198496 kb
Host smart-1383015b-1da9-40f3-a40c-b6b56d8dd5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389395599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2389395599
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1097502531
Short name T372
Test name
Test status
Simulation time 3919553048 ps
CPU time 19.2 seconds
Started May 16 12:20:57 PM PDT 24
Finished May 16 12:21:17 PM PDT 24
Peak memory 210660 kb
Host smart-85a68fb4-edb6-4773-923b-7d1719645555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097502531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1097502531
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2824410607
Short name T216
Test name
Test status
Simulation time 439947089 ps
CPU time 2.59 seconds
Started May 16 12:24:03 PM PDT 24
Finished May 16 12:24:12 PM PDT 24
Peak memory 200176 kb
Host smart-eb5cd1d8-38ac-4112-99a1-24751994bccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824410607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2824410607
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1131621210
Short name T504
Test name
Test status
Simulation time 185704666 ps
CPU time 1.23 seconds
Started May 16 12:21:19 PM PDT 24
Finished May 16 12:21:21 PM PDT 24
Peak memory 200556 kb
Host smart-e166dbef-a102-4d86-bec9-f5a37532c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131621210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1131621210
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.75105543
Short name T451
Test name
Test status
Simulation time 74233651 ps
CPU time 0.85 seconds
Started May 16 12:20:44 PM PDT 24
Finished May 16 12:20:46 PM PDT 24
Peak memory 200260 kb
Host smart-0d06558b-ee84-4b7c-985f-826b1e59ce17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75105543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.75105543
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1996012002
Short name T400
Test name
Test status
Simulation time 1220488992 ps
CPU time 6.37 seconds
Started May 16 12:20:00 PM PDT 24
Finished May 16 12:20:08 PM PDT 24
Peak memory 222268 kb
Host smart-293acf57-b9e0-4972-b011-51ceb6ed1a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996012002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1996012002
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4091101456
Short name T456
Test name
Test status
Simulation time 245116202 ps
CPU time 1.12 seconds
Started May 16 12:20:41 PM PDT 24
Finished May 16 12:20:43 PM PDT 24
Peak memory 217652 kb
Host smart-d31bc099-3b13-4783-8a99-15afeb3b00eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091101456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4091101456
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2942882868
Short name T286
Test name
Test status
Simulation time 172956622 ps
CPU time 0.86 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:51 PM PDT 24
Peak memory 199760 kb
Host smart-5ec9da33-132e-46ba-adef-2fdd1bbbe2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942882868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2942882868
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.308602758
Short name T471
Test name
Test status
Simulation time 841920428 ps
CPU time 3.77 seconds
Started May 16 12:21:15 PM PDT 24
Finished May 16 12:21:21 PM PDT 24
Peak memory 198584 kb
Host smart-93459074-5300-4185-9521-12dd5743550f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308602758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.308602758
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2599100960
Short name T519
Test name
Test status
Simulation time 139149132 ps
CPU time 1.02 seconds
Started May 16 12:24:18 PM PDT 24
Finished May 16 12:24:33 PM PDT 24
Peak memory 200428 kb
Host smart-6d2269b6-fe7d-483f-a51e-4e592f0d0552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599100960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2599100960
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.442686868
Short name T320
Test name
Test status
Simulation time 199788234 ps
CPU time 1.4 seconds
Started May 16 12:24:02 PM PDT 24
Finished May 16 12:24:08 PM PDT 24
Peak memory 200296 kb
Host smart-ea2a07ff-e3d2-4b8e-abb5-debeab2b34cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442686868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.442686868
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.607425212
Short name T321
Test name
Test status
Simulation time 3130844512 ps
CPU time 12.43 seconds
Started May 16 12:20:28 PM PDT 24
Finished May 16 12:20:41 PM PDT 24
Peak memory 208988 kb
Host smart-110ed7e6-a4b4-4232-8bde-e3a0fda6468c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607425212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.607425212
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2981725815
Short name T83
Test name
Test status
Simulation time 413330525 ps
CPU time 2.49 seconds
Started May 16 12:19:24 PM PDT 24
Finished May 16 12:19:27 PM PDT 24
Peak memory 200456 kb
Host smart-8892b399-3328-4665-a569-22117de2dab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981725815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2981725815
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2612340250
Short name T356
Test name
Test status
Simulation time 63071140 ps
CPU time 0.87 seconds
Started May 16 12:19:55 PM PDT 24
Finished May 16 12:19:57 PM PDT 24
Peak memory 200456 kb
Host smart-47d27ae5-1ce3-45d1-965b-27fb288d025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612340250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2612340250
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3546577696
Short name T537
Test name
Test status
Simulation time 88744909 ps
CPU time 0.9 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:50 PM PDT 24
Peak memory 197708 kb
Host smart-b7fa924d-dafb-45ae-9da5-655c854ed7c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546577696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3546577696
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.388866651
Short name T39
Test name
Test status
Simulation time 2346757426 ps
CPU time 7.89 seconds
Started May 16 12:21:03 PM PDT 24
Finished May 16 12:21:12 PM PDT 24
Peak memory 222256 kb
Host smart-39195051-dda8-46de-b6e0-098b542fc602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388866651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.388866651
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.191696085
Short name T312
Test name
Test status
Simulation time 243737500 ps
CPU time 1.16 seconds
Started May 16 12:24:12 PM PDT 24
Finished May 16 12:24:25 PM PDT 24
Peak memory 217468 kb
Host smart-96335c96-4c09-4361-84da-d2685a3d6395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191696085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.191696085
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2038644320
Short name T393
Test name
Test status
Simulation time 145650569 ps
CPU time 0.99 seconds
Started May 16 12:23:56 PM PDT 24
Finished May 16 12:24:02 PM PDT 24
Peak memory 199360 kb
Host smart-c8df7d89-5648-48d4-9f43-1bf5c7a819f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038644320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2038644320
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2928826678
Short name T94
Test name
Test status
Simulation time 753162645 ps
CPU time 3.82 seconds
Started May 16 12:24:26 PM PDT 24
Finished May 16 12:24:48 PM PDT 24
Peak memory 200348 kb
Host smart-453f5b3d-9be6-45a4-8eb4-2ec6d72ce0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928826678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2928826678
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2095572092
Short name T251
Test name
Test status
Simulation time 153277169 ps
CPU time 1.17 seconds
Started May 16 12:21:32 PM PDT 24
Finished May 16 12:21:34 PM PDT 24
Peak memory 200464 kb
Host smart-3dfcdaba-45cd-4031-a188-60acaf434e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095572092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2095572092
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2534417385
Short name T134
Test name
Test status
Simulation time 205488710 ps
CPU time 1.43 seconds
Started May 16 12:24:16 PM PDT 24
Finished May 16 12:24:31 PM PDT 24
Peak memory 198904 kb
Host smart-c0dc1e61-c9c7-4820-b23f-ff50bb3bcf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534417385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2534417385
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.412294387
Short name T145
Test name
Test status
Simulation time 300084010 ps
CPU time 1.55 seconds
Started May 16 12:24:10 PM PDT 24
Finished May 16 12:24:23 PM PDT 24
Peak memory 200340 kb
Host smart-8da19884-dbcd-4b30-af85-1584407ddd3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412294387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.412294387
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1543652337
Short name T524
Test name
Test status
Simulation time 480990466 ps
CPU time 2.63 seconds
Started May 16 12:22:01 PM PDT 24
Finished May 16 12:22:06 PM PDT 24
Peak memory 198888 kb
Host smart-12fe3060-733d-4201-8e7c-bd24a3ecd1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543652337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1543652337
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1235650527
Short name T239
Test name
Test status
Simulation time 118491397 ps
CPU time 0.91 seconds
Started May 16 12:24:33 PM PDT 24
Finished May 16 12:24:52 PM PDT 24
Peak memory 200036 kb
Host smart-1eb05c20-00c9-4af7-87a6-969f8047d037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235650527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1235650527
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2815305321
Short name T310
Test name
Test status
Simulation time 69867731 ps
CPU time 0.83 seconds
Started May 16 12:21:25 PM PDT 24
Finished May 16 12:21:27 PM PDT 24
Peak memory 197172 kb
Host smart-61a6bb27-c5b0-4305-9a4b-22446572568c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815305321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2815305321
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.349337467
Short name T52
Test name
Test status
Simulation time 1895927237 ps
CPU time 7.22 seconds
Started May 16 12:21:25 PM PDT 24
Finished May 16 12:21:34 PM PDT 24
Peak memory 217660 kb
Host smart-1ce9f39b-bf09-4d93-8965-7f161a9c12d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349337467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.349337467
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.875316452
Short name T532
Test name
Test status
Simulation time 243402274 ps
CPU time 1.1 seconds
Started May 16 12:24:32 PM PDT 24
Finished May 16 12:24:52 PM PDT 24
Peak memory 217304 kb
Host smart-b1553729-e115-420e-b267-269bd8a7e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875316452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.875316452
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1142417227
Short name T21
Test name
Test status
Simulation time 201695858 ps
CPU time 0.89 seconds
Started May 16 12:19:41 PM PDT 24
Finished May 16 12:19:43 PM PDT 24
Peak memory 200316 kb
Host smart-eb0eda8d-c8e5-4612-b94a-dd5fed989265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142417227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1142417227
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2941423490
Short name T250
Test name
Test status
Simulation time 959130161 ps
CPU time 5.03 seconds
Started May 16 12:20:17 PM PDT 24
Finished May 16 12:20:23 PM PDT 24
Peak memory 200648 kb
Host smart-5e6dacd9-cc39-478e-8ecd-053f43bd96d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941423490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2941423490
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3719700356
Short name T469
Test name
Test status
Simulation time 100528261 ps
CPU time 1.01 seconds
Started May 16 12:21:02 PM PDT 24
Finished May 16 12:21:04 PM PDT 24
Peak memory 200464 kb
Host smart-cb4d68e6-2dbb-4b56-b128-309092333a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719700356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3719700356
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2999701338
Short name T42
Test name
Test status
Simulation time 120066094 ps
CPU time 1.24 seconds
Started May 16 12:19:44 PM PDT 24
Finished May 16 12:19:47 PM PDT 24
Peak memory 200600 kb
Host smart-62c4fead-c7e3-4037-a65f-cd3942669620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999701338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2999701338
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3720915911
Short name T93
Test name
Test status
Simulation time 5026245435 ps
CPU time 15.79 seconds
Started May 16 12:21:26 PM PDT 24
Finished May 16 12:21:44 PM PDT 24
Peak memory 216620 kb
Host smart-b1586fe9-4641-4b93-a333-d84f3ff39b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720915911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3720915911
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4155844572
Short name T220
Test name
Test status
Simulation time 152236882 ps
CPU time 1.86 seconds
Started May 16 12:21:41 PM PDT 24
Finished May 16 12:21:43 PM PDT 24
Peak memory 200380 kb
Host smart-0a638bc7-5402-4977-885f-9fbdad099eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155844572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4155844572
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.438892552
Short name T138
Test name
Test status
Simulation time 94618425 ps
CPU time 0.93 seconds
Started May 16 12:20:45 PM PDT 24
Finished May 16 12:20:47 PM PDT 24
Peak memory 200428 kb
Host smart-af617180-3065-444b-a922-82b94eab866d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438892552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.438892552
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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